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| author | Iru Cai <mytbk920423@gmail.com> | 2019-10-30 14:21:52 +0800 |
|---|---|---|
| committer | Iru Cai <mytbk920423@gmail.com> | 2019-10-30 14:48:38 +0800 |
| commit | ae51f41d14f548d494ac41e0d21137c5a4c3f59c (patch) | |
| tree | 6ddb9d1aaa7bd5bad5bbf8497edc2e08ff208d79 /arch/riscv/include/asm/byteorder.h | |
| download | uext4-ae51f41d14f548d494ac41e0d21137c5a4c3f59c.tar.xz | |
import the U-Boot code and make it compile
Diffstat (limited to 'arch/riscv/include/asm/byteorder.h')
| -rw-r--r-- | arch/riscv/include/asm/byteorder.h | 35 |
1 files changed, 35 insertions, 0 deletions
diff --git a/arch/riscv/include/asm/byteorder.h b/arch/riscv/include/asm/byteorder.h new file mode 100644 index 0000000..d26ac56 --- /dev/null +++ b/arch/riscv/include/asm/byteorder.h @@ -0,0 +1,35 @@ +/* + * linux/include/asm-arm/byteorder.h + * + * Copyright (C) 2017 Andes Technology Corporation + * Rick Chen, Andes Technology Corporation <rick@andestech.com> + * + * ARM Endian-ness. In little endian mode, the data bus is connected such + * that byte accesses appear as: + * 0 = d0...d7, 1 = d8...d15, 2 = d16...d23, 3 = d24...d31 + * and word accesses (data or instruction) appear as: + * d0...d31 + * + * When in big endian mode, byte accesses appear as: + * 0 = d24...d31, 1 = d16...d23, 2 = d8...d15, 3 = d0...d7 + * and word accesses (data or instruction) appear as: + * d0...d31 + */ + +#ifndef __ASM_RISCV_BYTEORDER_H +#define __ASM_RISCV_BYTEORDER_H + +#include <asm/types.h> + +#if !defined(__STRICT_ANSI__) || defined(__KERNEL__) +# define __BYTEORDER_HAS_U64__ +# define __SWAB_64_THRU_32__ +#endif + +#ifdef __RISCVEB__ +#include <linux/byteorder/big_endian.h> +#else +#include <linux/byteorder/little_endian.h> +#endif + +#endif |