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author | Iru Cai <mytbk920423@gmail.com> | 2019-10-30 14:21:52 +0800 |
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committer | Iru Cai <mytbk920423@gmail.com> | 2019-10-30 14:48:38 +0800 |
commit | ae51f41d14f548d494ac41e0d21137c5a4c3f59c (patch) | |
tree | 6ddb9d1aaa7bd5bad5bbf8497edc2e08ff208d79 /arch/xtensa/include/asm/cache.h | |
download | uext4-ae51f41d14f548d494ac41e0d21137c5a4c3f59c.tar.xz |
import the U-Boot code and make it compile
Diffstat (limited to 'arch/xtensa/include/asm/cache.h')
-rw-r--r-- | arch/xtensa/include/asm/cache.h | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/arch/xtensa/include/asm/cache.h b/arch/xtensa/include/asm/cache.h new file mode 100644 index 0000000..68b8330 --- /dev/null +++ b/arch/xtensa/include/asm/cache.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2009 Tensilica Inc. + */ +#ifndef _XTENSA_CACHE_H +#define _XTENSA_CACHE_H + +#include <asm/arch/core.h> + +#define ARCH_DMA_MINALIGN XCHAL_DCACHE_LINESIZE + +#ifndef __ASSEMBLY__ + +void __flush_dcache_all(void); +void __flush_invalidate_dcache_range(unsigned long addr, unsigned long size); +void __invalidate_dcache_all(void); +void __invalidate_dcache_range(unsigned long addr, unsigned long size); + +void __invalidate_icache_all(void); +void __invalidate_icache_range(unsigned long addr, unsigned long size); + +#endif + +#endif /* _XTENSA_CACHE_H */ |