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author | Iru Cai <mytbk920423@gmail.com> | 2019-10-30 14:21:52 +0800 |
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committer | Iru Cai <mytbk920423@gmail.com> | 2019-10-30 14:48:38 +0800 |
commit | ae51f41d14f548d494ac41e0d21137c5a4c3f59c (patch) | |
tree | 6ddb9d1aaa7bd5bad5bbf8497edc2e08ff208d79 /include/configs/sama5d3xek.h | |
download | uext4-ae51f41d14f548d494ac41e0d21137c5a4c3f59c.tar.xz |
import the U-Boot code and make it compile
Diffstat (limited to 'include/configs/sama5d3xek.h')
-rw-r--r-- | include/configs/sama5d3xek.h | 98 |
1 files changed, 98 insertions, 0 deletions
diff --git a/include/configs/sama5d3xek.h b/include/configs/sama5d3xek.h new file mode 100644 index 0000000..3a712b5 --- /dev/null +++ b/include/configs/sama5d3xek.h @@ -0,0 +1,98 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Configuation settings for the SAMA5D3xEK board. + * + * Copyright (C) 2012 - 2013 Atmel + * + * based on at91sam9m10g45ek.h by: + * Stelian Pop <stelian@popies.net> + * Lead Tech Design <www.leadtechdesign.com> + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include "at91-sama5_common.h" + +/* + * This needs to be defined for the OHCI code to work but it is defined as + * ATMEL_ID_UHPHS in the CPU specific header files. + */ +#define ATMEL_ID_UHP 32 + +/* + * Specify the clock enable bit in the PMC_SCER register. + */ +#define ATMEL_PMC_UHP (1 << 6) + +/* board specific (not enough SRAM) */ +#define CONFIG_SAMA5D3_LCD_BASE 0x23E00000 + +/* NOR flash */ +#ifdef CONFIG_MTD_NOR_FLASH +#define CONFIG_SYS_FLASH_BASE 0x10000000 +#define CONFIG_SYS_MAX_FLASH_SECT 131 +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#endif + +/* SDRAM */ +#define CONFIG_SYS_SDRAM_BASE 0x20000000 +#define CONFIG_SYS_SDRAM_SIZE 0x20000000 + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_INIT_SP_ADDR 0x318000 +#else +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE) +#endif + +/* SerialFlash */ + +/* NAND flash */ +#ifdef CONFIG_CMD_NAND +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x60000000 +/* our ALE is AD21 */ +#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) +/* our CLE is AD22 */ +#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) +#define CONFIG_SYS_NAND_ONFI_DETECTION +#endif + +/* USB */ +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_ATMEL_CLK_SEL_UPLL +#define CONFIG_USB_OHCI_NEW +#define CONFIG_SYS_USB_OHCI_CPU_INIT +#define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_BASE_OHCI +#define CONFIG_SYS_USB_OHCI_SLOT_NAME "sama5d3" +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 3 +#endif + +#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ + +/* SPL */ +#define CONFIG_SPL_MAX_SIZE 0x18000 +#define CONFIG_SPL_BSS_START_ADDR 0x20000000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 +#define CONFIG_SYS_SPL_MALLOC_START 0x20080000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 + +#define CONFIG_SYS_MONITOR_LEN (512 << 10) + +#ifdef CONFIG_SD_BOOT +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 +#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" +#elif CONFIG_NAND_BOOT +#define CONFIG_SPL_NAND_DRIVERS +#define CONFIG_SPL_NAND_BASE +#endif +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_PAGE_SIZE 0x800 +#define CONFIG_SYS_NAND_PAGE_COUNT 64 +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000 +#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0 + +#endif |