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| author | Iru Cai <mytbk920423@gmail.com> | 2019-10-30 14:21:52 +0800 |
|---|---|---|
| committer | Iru Cai <mytbk920423@gmail.com> | 2019-10-30 14:48:38 +0800 |
| commit | ae51f41d14f548d494ac41e0d21137c5a4c3f59c (patch) | |
| tree | 6ddb9d1aaa7bd5bad5bbf8497edc2e08ff208d79 /include/configs/zynq_cse.h | |
| download | uext4-ae51f41d14f548d494ac41e0d21137c5a4c3f59c.tar.xz | |
import the U-Boot code and make it compile
Diffstat (limited to 'include/configs/zynq_cse.h')
| -rw-r--r-- | include/configs/zynq_cse.h | 34 |
1 files changed, 34 insertions, 0 deletions
diff --git a/include/configs/zynq_cse.h b/include/configs/zynq_cse.h new file mode 100644 index 0000000..917f35b --- /dev/null +++ b/include/configs/zynq_cse.h @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2013 - 2017 Xilinx. + * + * Configuration settings for the Xilinx Zynq CSE board. + * See zynq-common.h for Zynq common configs + */ + +#ifndef __CONFIG_ZYNQ_CSE_H +#define __CONFIG_ZYNQ_CSE_H + +#define CONFIG_SKIP_LOWLEVEL_INIT + +#include <configs/zynq-common.h> + +/* Undef unneeded configs */ +#undef CONFIG_EXTRA_ENV_SETTINGS +#undef CONFIG_ZLIB +#undef CONFIG_GZIP + +#undef CONFIG_SYS_CBSIZE + +#define CONFIG_SYS_CBSIZE 1024 + +#undef CONFIG_SYS_INIT_RAM_ADDR +#undef CONFIG_SYS_INIT_RAM_SIZE +#define CONFIG_SYS_INIT_RAM_ADDR 0xFFFDE000 +#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 +#undef CONFIG_SPL_BSS_START_ADDR +#undef CONFIG_SPL_BSS_MAX_SIZE +#define CONFIG_SPL_BSS_START_ADDR 0x20000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x8000 + +#endif /* __CONFIG_ZYNQ_CSE_H */ |