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author | Iru Cai <mytbk920423@gmail.com> | 2019-10-30 15:44:39 +0800 |
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committer | Iru Cai <mytbk920423@gmail.com> | 2019-10-30 15:44:39 +0800 |
commit | 63cf543b3cc4d6e21d680bde234f697a5588c66e (patch) | |
tree | 6b1ea4cd9525e1ebeee8fb5ed427127197707022 /include/dt-bindings/memory/stm32-sdram.h | |
parent | a899a6c0ed9a3066557fb170850f977b6bd7366f (diff) | |
download | uext4-63cf543b3cc4d6e21d680bde234f697a5588c66e.tar.xz |
rm include/dt-bindings
Diffstat (limited to 'include/dt-bindings/memory/stm32-sdram.h')
-rw-r--r-- | include/dt-bindings/memory/stm32-sdram.h | 46 |
1 files changed, 0 insertions, 46 deletions
diff --git a/include/dt-bindings/memory/stm32-sdram.h b/include/dt-bindings/memory/stm32-sdram.h deleted file mode 100644 index ab91d2b..0000000 --- a/include/dt-bindings/memory/stm32-sdram.h +++ /dev/null @@ -1,46 +0,0 @@ -#ifndef DT_BINDINGS_STM32_SDRAM_H -#define DT_BINDINGS_STM32_SDRAM_H - -#define NO_COL_8 0x0 -#define NO_COL_9 0x1 -#define NO_COL_10 0x2 -#define NO_COL_11 0x3 - -#define NO_ROW_11 0x0 -#define NO_ROW_12 0x1 -#define NO_ROW_13 0x2 - -#define MWIDTH_8 0x0 -#define MWIDTH_16 0x1 -#define MWIDTH_32 0x2 -#define BANKS_2 0x0 -#define BANKS_4 0x1 -#define CAS_1 0x1 -#define CAS_2 0x2 -#define CAS_3 0x3 -#define SDCLK_DIS 0x0 -#define SDCLK_2 0x2 -#define SDCLK_3 0x3 -#define RD_BURST_EN 0x1 -#define RD_BURST_DIS 0x0 -#define RD_PIPE_DL_0 0x0 -#define RD_PIPE_DL_1 0x1 -#define RD_PIPE_DL_2 0x2 - -/* Timing = value +1 cycles */ -#define TMRD_1 (1 - 1) -#define TMRD_2 (2 - 1) -#define TMRD_3 (3 - 1) -#define TXSR_1 (1 - 1) -#define TXSR_6 (6 - 1) -#define TXSR_7 (7 - 1) -#define TRAS_1 (1 - 1) -#define TRAS_4 (4 - 1) -#define TRC_6 (6 - 1) -#define TWR_1 (1 - 1) -#define TWR_2 (2 - 1) -#define TRP_2 (2 - 1) -#define TRCD_1 (1 - 1) -#define TRCD_2 (2 - 1) - -#endif |