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authorIru Cai <mytbk920423@gmail.com>2019-10-30 15:44:39 +0800
committerIru Cai <mytbk920423@gmail.com>2019-10-30 15:44:39 +0800
commit63cf543b3cc4d6e21d680bde234f697a5588c66e (patch)
tree6b1ea4cd9525e1ebeee8fb5ed427127197707022
parenta899a6c0ed9a3066557fb170850f977b6bd7366f (diff)
downloaduext4-63cf543b3cc4d6e21d680bde234f697a5588c66e.tar.xz
rm include/dt-bindings
-rw-r--r--include/dt-bindings/bus/ti-sysc.h22
-rw-r--r--include/dt-bindings/clk/mpc83xx-clk.h33
-rw-r--r--include/dt-bindings/clk/ti-dra7-atl.h40
-rw-r--r--include/dt-bindings/clock/am3.h227
-rw-r--r--include/dt-bindings/clock/ast2500-scu.h30
-rw-r--r--include/dt-bindings/clock/at91.h23
-rw-r--r--include/dt-bindings/clock/axg-aoclkc.h31
-rw-r--r--include/dt-bindings/clock/axg-audio-clkc.h84
-rw-r--r--include/dt-bindings/clock/axg-clkc.h76
-rw-r--r--include/dt-bindings/clock/bcm2835-aux.h9
-rw-r--r--include/dt-bindings/clock/bcm2835.h60
-rw-r--r--include/dt-bindings/clock/bcm3380-clock.h22
-rw-r--r--include/dt-bindings/clock/bcm6318-clock.h47
-rw-r--r--include/dt-bindings/clock/bcm63268-clock.h51
-rw-r--r--include/dt-bindings/clock/bcm6328-clock.h24
-rw-r--r--include/dt-bindings/clock/bcm6338-clock.h18
-rw-r--r--include/dt-bindings/clock/bcm6348-clock.h21
-rw-r--r--include/dt-bindings/clock/bcm6358-clock.h23
-rw-r--r--include/dt-bindings/clock/bcm6362-clock.h32
-rw-r--r--include/dt-bindings/clock/bcm6368-clock.h30
-rw-r--r--include/dt-bindings/clock/boston-clock.h12
-rw-r--r--include/dt-bindings/clock/exynos7420-clk.h207
-rw-r--r--include/dt-bindings/clock/g12a-aoclkc.h36
-rw-r--r--include/dt-bindings/clock/g12a-clkc.h147
-rw-r--r--include/dt-bindings/clock/gxbb-aoclkc.h67
-rw-r--r--include/dt-bindings/clock/gxbb-clkc.h129
-rw-r--r--include/dt-bindings/clock/hi3660-clock.h214
-rw-r--r--include/dt-bindings/clock/hi6220-clock.h173
-rw-r--r--include/dt-bindings/clock/histb-clock.h82
-rw-r--r--include/dt-bindings/clock/imx5-clock.h219
-rw-r--r--include/dt-bindings/clock/imx6qdl-clock.h274
-rw-r--r--include/dt-bindings/clock/imx6sl-clock.h180
-rw-r--r--include/dt-bindings/clock/imx6sll-clock.h204
-rw-r--r--include/dt-bindings/clock/imx6sx-clock.h280
-rw-r--r--include/dt-bindings/clock/imx6ul-clock.h262
-rw-r--r--include/dt-bindings/clock/imx7d-clock.h459
-rw-r--r--include/dt-bindings/clock/imx7ulp-clock.h161
-rw-r--r--include/dt-bindings/clock/imx8mm-clock.h253
-rw-r--r--include/dt-bindings/clock/imx8mq-clock.h612
-rw-r--r--include/dt-bindings/clock/imx8qm-clock.h846
-rw-r--r--include/dt-bindings/clock/imx8qxp-clock.h583
-rw-r--r--include/dt-bindings/clock/jz4780-cgu.h89
-rw-r--r--include/dt-bindings/clock/maxim,max77802.h22
-rw-r--r--include/dt-bindings/clock/microchip,clock.h28
-rw-r--r--include/dt-bindings/clock/mt7623-clk.h413
-rw-r--r--include/dt-bindings/clock/mt7628-clk.h37
-rw-r--r--include/dt-bindings/clock/mt7629-clk.h206
-rw-r--r--include/dt-bindings/clock/mt8516-clk.h251
-rw-r--r--include/dt-bindings/clock/r7s72100-clock.h112
-rw-r--r--include/dt-bindings/clock/r8a7790-clock.h162
-rw-r--r--include/dt-bindings/clock/r8a7790-cpg-mssr.h48
-rw-r--r--include/dt-bindings/clock/r8a7791-clock.h165
-rw-r--r--include/dt-bindings/clock/r8a7791-cpg-mssr.h44
-rw-r--r--include/dt-bindings/clock/r8a7792-clock.h102
-rw-r--r--include/dt-bindings/clock/r8a7792-cpg-mssr.h39
-rw-r--r--include/dt-bindings/clock/r8a7793-clock.h159
-rw-r--r--include/dt-bindings/clock/r8a7793-cpg-mssr.h44
-rw-r--r--include/dt-bindings/clock/r8a7794-clock.h137
-rw-r--r--include/dt-bindings/clock/r8a7794-cpg-mssr.h43
-rw-r--r--include/dt-bindings/clock/r8a7795-cpg-mssr.h66
-rw-r--r--include/dt-bindings/clock/r8a7796-cpg-mssr.h65
-rw-r--r--include/dt-bindings/clock/r8a77965-cpg-mssr.h62
-rw-r--r--include/dt-bindings/clock/r8a77970-cpg-mssr.h48
-rw-r--r--include/dt-bindings/clock/r8a77980-cpg-mssr.h51
-rw-r--r--include/dt-bindings/clock/r8a77990-cpg-mssr.h62
-rw-r--r--include/dt-bindings/clock/r8a77995-cpg-mssr.h54
-rw-r--r--include/dt-bindings/clock/renesas-cpg-mssr.h15
-rw-r--r--include/dt-bindings/clock/rk3036-cru.h185
-rw-r--r--include/dt-bindings/clock/rk3066a-cru.h31
-rw-r--r--include/dt-bindings/clock/rk3128-cru.h189
-rw-r--r--include/dt-bindings/clock/rk3188-cru-common.h255
-rw-r--r--include/dt-bindings/clock/rk3188-cru.h47
-rw-r--r--include/dt-bindings/clock/rk3228-cru.h237
-rw-r--r--include/dt-bindings/clock/rk3288-cru.h370
-rw-r--r--include/dt-bindings/clock/rk3328-cru.h393
-rw-r--r--include/dt-bindings/clock/rk3368-cru.h384
-rw-r--r--include/dt-bindings/clock/rk3399-cru.h749
-rw-r--r--include/dt-bindings/clock/rockchip,rk808.h11
-rw-r--r--include/dt-bindings/clock/rv1108-cru.h356
-rw-r--r--include/dt-bindings/clock/s900_cmu.h77
-rw-r--r--include/dt-bindings/clock/sifive-fu540-prci.h18
-rw-r--r--include/dt-bindings/clock/snps,hsdk-cgu.h42
-rw-r--r--include/dt-bindings/clock/stih407-clks.h90
-rw-r--r--include/dt-bindings/clock/stih410-clks.h25
-rw-r--r--include/dt-bindings/clock/stm32fx-clock.h60
-rw-r--r--include/dt-bindings/clock/stm32h7-clks.h167
-rw-r--r--include/dt-bindings/clock/stm32mp1-clks.h251
-rw-r--r--include/dt-bindings/clock/stm32mp1-clksrc.h284
-rw-r--r--include/dt-bindings/clock/sun4i-a10-ccu.h202
-rw-r--r--include/dt-bindings/clock/sun4i-a10-pll2.h53
-rw-r--r--include/dt-bindings/clock/sun50i-a64-ccu.h136
-rw-r--r--include/dt-bindings/clock/sun50i-h6-ccu.h125
-rw-r--r--include/dt-bindings/clock/sun50i-h6-r-ccu.h24
-rw-r--r--include/dt-bindings/clock/sun5i-ccu.h106
-rw-r--r--include/dt-bindings/clock/sun6i-a31-ccu.h191
-rw-r--r--include/dt-bindings/clock/sun7i-a20-ccu.h53
-rw-r--r--include/dt-bindings/clock/sun8i-a23-a33-ccu.h127
-rw-r--r--include/dt-bindings/clock/sun8i-a83t-ccu.h140
-rw-r--r--include/dt-bindings/clock/sun8i-de2.h18
-rw-r--r--include/dt-bindings/clock/sun8i-h3-ccu.h145
-rw-r--r--include/dt-bindings/clock/sun8i-r-ccu.h59
-rw-r--r--include/dt-bindings/clock/sun8i-r40-ccu.h187
-rw-r--r--include/dt-bindings/clock/sun8i-tcon-top.h11
-rw-r--r--include/dt-bindings/clock/sun8i-v3s-ccu.h107
-rw-r--r--include/dt-bindings/clock/sun9i-a80-ccu.h162
-rw-r--r--include/dt-bindings/clock/sun9i-a80-de.h80
-rw-r--r--include/dt-bindings/clock/sun9i-a80-usb.h59
-rw-r--r--include/dt-bindings/clock/tegra114-car.h343
-rw-r--r--include/dt-bindings/clock/tegra124-car-common.h345
-rw-r--r--include/dt-bindings/clock/tegra124-car.h19
-rw-r--r--include/dt-bindings/clock/tegra186-clock.h940
-rw-r--r--include/dt-bindings/clock/tegra20-car.h158
-rw-r--r--include/dt-bindings/clock/tegra210-car.h401
-rw-r--r--include/dt-bindings/clock/tegra30-car.h273
-rw-r--r--include/dt-bindings/clock/xlnx-zynqmp-clk.h126
-rw-r--r--include/dt-bindings/comphy/comphy_data.h62
-rw-r--r--include/dt-bindings/dma/at91.h52
-rw-r--r--include/dt-bindings/dma/bcm6318-dma.h14
-rw-r--r--include/dt-bindings/dma/bcm63268-dma.h14
-rw-r--r--include/dt-bindings/dma/bcm6328-dma.h14
-rw-r--r--include/dt-bindings/dma/bcm6338-dma.h14
-rw-r--r--include/dt-bindings/dma/bcm6348-dma.h16
-rw-r--r--include/dt-bindings/dma/bcm6358-dma.h16
-rw-r--r--include/dt-bindings/dma/bcm6362-dma.h14
-rw-r--r--include/dt-bindings/dma/bcm6368-dma.h14
-rw-r--r--include/dt-bindings/dma/k3-udma.h31
-rw-r--r--include/dt-bindings/dma/sun4i-a10.h56
-rw-r--r--include/dt-bindings/gpio/gpio.h36
-rw-r--r--include/dt-bindings/gpio/meson-axg-gpio.h116
-rw-r--r--include/dt-bindings/gpio/meson-g12a-gpio.h114
-rw-r--r--include/dt-bindings/gpio/meson-gxbb-gpio.h154
-rw-r--r--include/dt-bindings/gpio/meson-gxl-gpio.h131
-rw-r--r--include/dt-bindings/gpio/tegra-gpio.h51
-rw-r--r--include/dt-bindings/gpio/tegra186-gpio.h59
-rw-r--r--include/dt-bindings/gpio/uniphier-gpio.h18
-rw-r--r--include/dt-bindings/gpio/x86-gpio.h43
-rw-r--r--include/dt-bindings/input/input.h17
-rw-r--r--include/dt-bindings/input/linux-event-codes.h805
-rw-r--r--include/dt-bindings/interrupt-controller/arm-gic.h22
-rw-r--r--include/dt-bindings/interrupt-controller/irq-st.h30
-rw-r--r--include/dt-bindings/interrupt-controller/irq.h19
-rw-r--r--include/dt-bindings/interrupt-controller/mips-gic.h9
-rw-r--r--include/dt-bindings/interrupt-router/intel-irq.h30
-rw-r--r--include/dt-bindings/leds/leds-netxbig.h18
-rw-r--r--include/dt-bindings/leds/leds-ns2.h9
-rw-r--r--include/dt-bindings/leds/leds-pca9532.h18
-rw-r--r--include/dt-bindings/mailbox/tegra186-hsp.h19
-rw-r--r--include/dt-bindings/media/omap3-isp.h22
-rw-r--r--include/dt-bindings/memory/mpc83xx-sdram.h161
-rw-r--r--include/dt-bindings/memory/rk3368-dmc.h30
-rw-r--r--include/dt-bindings/memory/stm32-sdram.h46
-rw-r--r--include/dt-bindings/memory/tegra114-mc.h25
-rw-r--r--include/dt-bindings/memory/tegra124-mc.h31
-rw-r--r--include/dt-bindings/memory/tegra210-mc.h36
-rw-r--r--include/dt-bindings/memory/tegra30-mc.h24
-rw-r--r--include/dt-bindings/mfd/st,stpmic1.h46
-rw-r--r--include/dt-bindings/mfd/st-lpc.h16
-rw-r--r--include/dt-bindings/mfd/stm32f4-rcc.h108
-rw-r--r--include/dt-bindings/mfd/stm32f7-rcc.h114
-rw-r--r--include/dt-bindings/mfd/stm32h7-rcc.h138
-rw-r--r--include/dt-bindings/mrc/quark.h82
-rw-r--r--include/dt-bindings/mscc/jr2_data.h19
-rw-r--r--include/dt-bindings/mscc/luton_data.h17
-rw-r--r--include/dt-bindings/mscc/ocelot_data.h19
-rw-r--r--include/dt-bindings/mscc/serval_data.h19
-rw-r--r--include/dt-bindings/net/microchip-lan78xx.h21
-rw-r--r--include/dt-bindings/net/ti-dp83867.h49
-rw-r--r--include/dt-bindings/phy/phy-am654-serdes.h13
-rw-r--r--include/dt-bindings/phy/phy.h19
-rw-r--r--include/dt-bindings/pinctrl/am33xx.h43
-rw-r--r--include/dt-bindings/pinctrl/am43xx.h39
-rw-r--r--include/dt-bindings/pinctrl/at91.h46
-rw-r--r--include/dt-bindings/pinctrl/bcm2835.h26
-rw-r--r--include/dt-bindings/pinctrl/dra.h80
-rw-r--r--include/dt-bindings/pinctrl/hisi.h74
-rw-r--r--include/dt-bindings/pinctrl/k3.h41
-rw-r--r--include/dt-bindings/pinctrl/omap.h93
-rw-r--r--include/dt-bindings/pinctrl/pads-imx8qm.h961
-rw-r--r--include/dt-bindings/pinctrl/pads-imx8qxp.h757
-rw-r--r--include/dt-bindings/pinctrl/pinctrl-snapdragon.h22
-rw-r--r--include/dt-bindings/pinctrl/pinctrl-tegra-xusb.h7
-rw-r--r--include/dt-bindings/pinctrl/pinctrl-tegra.h37
-rw-r--r--include/dt-bindings/pinctrl/pins-imx8mq.h632
-rw-r--r--include/dt-bindings/pinctrl/r7s72100-pinctrl.h18
-rw-r--r--include/dt-bindings/pinctrl/rockchip.h60
-rw-r--r--include/dt-bindings/pinctrl/stm32-pinfunc.h42
-rw-r--r--include/dt-bindings/pinctrl/sun4i-a10.h62
-rw-r--r--include/dt-bindings/pmic/sandbox_pmic.h34
-rw-r--r--include/dt-bindings/power-domain/bcm6318-power-domain.h12
-rw-r--r--include/dt-bindings/power-domain/bcm63268-power-domain.h24
-rw-r--r--include/dt-bindings/power-domain/bcm6328-power-domain.h20
-rw-r--r--include/dt-bindings/power-domain/bcm6362-power-domain.h24
-rw-r--r--include/dt-bindings/power-domain/rk3288.h11
-rw-r--r--include/dt-bindings/power/imx7-power.h16
-rwxr-xr-xinclude/dt-bindings/power/imx8mq-power.h21
-rw-r--r--include/dt-bindings/power/meson-g12a-power.h13
-rw-r--r--include/dt-bindings/power/meson-sm1-power.h18
-rw-r--r--include/dt-bindings/power/mt7623-power.h19
-rw-r--r--include/dt-bindings/power/mt7629-power.h13
-rw-r--r--include/dt-bindings/power/r8a7790-sysc.h34
-rw-r--r--include/dt-bindings/power/r8a7791-sysc.h26
-rw-r--r--include/dt-bindings/power/r8a7792-sysc.h26
-rw-r--r--include/dt-bindings/power/r8a7793-sysc.h28
-rw-r--r--include/dt-bindings/power/r8a7794-sysc.h26
-rw-r--r--include/dt-bindings/power/r8a7795-sysc.h42
-rw-r--r--include/dt-bindings/power/r8a7796-sysc.h36
-rw-r--r--include/dt-bindings/power/r8a77965-sysc.h29
-rw-r--r--include/dt-bindings/power/r8a77970-sysc.h31
-rw-r--r--include/dt-bindings/power/r8a77980-sysc.h43
-rw-r--r--include/dt-bindings/power/r8a77990-sysc.h26
-rw-r--r--include/dt-bindings/power/r8a77995-sysc.h23
-rw-r--r--include/dt-bindings/power/raspberrypi-power.h41
-rw-r--r--include/dt-bindings/power/rk3399-power.h53
-rw-r--r--include/dt-bindings/power/tegra186-powergate.h28
-rw-r--r--include/dt-bindings/power/xlnx-zynqmp-power.h39
-rw-r--r--include/dt-bindings/pwm/pwm.h14
-rw-r--r--include/dt-bindings/regulator/maxim,max77802.h18
-rw-r--r--include/dt-bindings/reset/altr,rst-mgr-a10.h110
-rw-r--r--include/dt-bindings/reset/altr,rst-mgr-s10.h96
-rw-r--r--include/dt-bindings/reset/altr,rst-mgr.h82
-rw-r--r--include/dt-bindings/reset/amlogic,meson-axg-audio-arb.h17
-rw-r--r--include/dt-bindings/reset/amlogic,meson-axg-reset.h124
-rw-r--r--include/dt-bindings/reset/amlogic,meson-g12a-audio-reset.h38
-rw-r--r--include/dt-bindings/reset/amlogic,meson-g12a-reset.h137
-rw-r--r--include/dt-bindings/reset/amlogic,meson-gxbb-reset.h210
-rw-r--r--include/dt-bindings/reset/ast2500-reset.h44
-rw-r--r--include/dt-bindings/reset/axg-aoclkc.h20
-rw-r--r--include/dt-bindings/reset/bcm3380-reset.h15
-rw-r--r--include/dt-bindings/reset/bcm6318-reset.h25
-rw-r--r--include/dt-bindings/reset/bcm63268-reset.h31
-rw-r--r--include/dt-bindings/reset/bcm6328-reset.h23
-rw-r--r--include/dt-bindings/reset/bcm6338-reset.h21
-rw-r--r--include/dt-bindings/reset/bcm6348-reset.h21
-rw-r--r--include/dt-bindings/reset/bcm6358-reset.h20
-rw-r--r--include/dt-bindings/reset/bcm6362-reset.h27
-rw-r--r--include/dt-bindings/reset/bcm6368-reset.h21
-rw-r--r--include/dt-bindings/reset/g12a-aoclkc.h18
-rw-r--r--include/dt-bindings/reset/gxbb-aoclkc.h66
-rw-r--r--include/dt-bindings/reset/imx7-reset.h52
-rwxr-xr-xinclude/dt-bindings/reset/imx8mq-reset.h64
-rw-r--r--include/dt-bindings/reset/mt7623-reset.h25
-rw-r--r--include/dt-bindings/reset/mt7628-reset.h36
-rw-r--r--include/dt-bindings/reset/mt7629-reset.h36
-rw-r--r--include/dt-bindings/reset/stih407-resets.h65
-rw-r--r--include/dt-bindings/reset/stm32mp1-resets.h108
-rw-r--r--include/dt-bindings/reset/sun4i-a10-ccu.h69
-rw-r--r--include/dt-bindings/reset/sun50i-a64-ccu.h98
-rw-r--r--include/dt-bindings/reset/sun50i-h6-ccu.h73
-rw-r--r--include/dt-bindings/reset/sun50i-h6-r-ccu.h17
-rw-r--r--include/dt-bindings/reset/sun5i-ccu.h32
-rw-r--r--include/dt-bindings/reset/sun6i-a31-ccu.h106
-rw-r--r--include/dt-bindings/reset/sun8i-a23-a33-ccu.h87
-rw-r--r--include/dt-bindings/reset/sun8i-a83t-ccu.h98
-rw-r--r--include/dt-bindings/reset/sun8i-de2.h14
-rw-r--r--include/dt-bindings/reset/sun8i-h3-ccu.h103
-rw-r--r--include/dt-bindings/reset/sun8i-r-ccu.h53
-rw-r--r--include/dt-bindings/reset/sun8i-r40-ccu.h130
-rw-r--r--include/dt-bindings/reset/sun8i-v3s-ccu.h78
-rw-r--r--include/dt-bindings/reset/sun9i-a80-ccu.h102
-rw-r--r--include/dt-bindings/reset/sun9i-a80-de.h58
-rw-r--r--include/dt-bindings/reset/sun9i-a80-usb.h56
-rw-r--r--include/dt-bindings/reset/tegra124-car.h12
-rw-r--r--include/dt-bindings/reset/tegra186-reset.h205
-rw-r--r--include/dt-bindings/reset/ti-syscon.h38
-rw-r--r--include/dt-bindings/reset/xlnx-zynqmp-resets.h130
-rw-r--r--include/dt-bindings/soc/bcm2835-pm.h28
-rw-r--r--include/dt-bindings/soc/imx8_pd.h188
-rw-r--r--include/dt-bindings/soc/imx_rsrc.h557
-rw-r--r--include/dt-bindings/soc/ti,sci_pm_domain.h9
-rw-r--r--include/dt-bindings/sound/azalia.h44
-rw-r--r--include/dt-bindings/sound/meson-g12a-tohdmitx.h13
-rw-r--r--include/dt-bindings/sound/tlv320aic31xx-micbias.h8
-rw-r--r--include/dt-bindings/thermal/tegra124-soctherm.h14
-rw-r--r--include/dt-bindings/thermal/thermal.h17
-rw-r--r--include/dt-bindings/video/rk3288.h11
275 files changed, 0 insertions, 28556 deletions
diff --git a/include/dt-bindings/bus/ti-sysc.h b/include/dt-bindings/bus/ti-sysc.h
deleted file mode 100644
index 2c00537..0000000
--- a/include/dt-bindings/bus/ti-sysc.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/* TI sysc interconnect target module defines */
-
-/* Generic sysc found on omap2 and later, also known as type1 */
-#define SYSC_OMAP2_CLOCKACTIVITY (3 << 8)
-#define SYSC_OMAP2_EMUFREE (1 << 5)
-#define SYSC_OMAP2_ENAWAKEUP (1 << 2)
-#define SYSC_OMAP2_SOFTRESET (1 << 1)
-#define SYSC_OMAP2_AUTOIDLE (1 << 0)
-
-/* Generic sysc found on omap4 and later, also known as type2 */
-#define SYSC_OMAP4_DMADISABLE (1 << 16)
-#define SYSC_OMAP4_FREEEMU (1 << 1) /* Also known as EMUFREE */
-#define SYSC_OMAP4_SOFTRESET (1 << 0)
-
-/* SmartReflex sysc found on 36xx and later */
-#define SYSC_OMAP3_SR_ENAWAKEUP (1 << 26)
-
-/* SYSCONFIG STANDBYMODE/MIDLEMODE/SIDLEMODE supported by hardware */
-#define SYSC_IDLE_FORCE 0
-#define SYSC_IDLE_NO 1
-#define SYSC_IDLE_SMART 2
-#define SYSC_IDLE_SMART_WKUP 3
diff --git a/include/dt-bindings/clk/mpc83xx-clk.h b/include/dt-bindings/clk/mpc83xx-clk.h
deleted file mode 100644
index db4ea15..0000000
--- a/include/dt-bindings/clk/mpc83xx-clk.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2018
- * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
- */
-
-#ifndef DT_BINDINGS_MPC83XX_CLK_H
-#define DT_BINDINGS_MPC83XX_CLK_H
-#define MPC83XX_CLK_CORE 0
-#define MPC83XX_CLK_CSB 1
-#define MPC83XX_CLK_QE 2
-#define MPC83XX_CLK_BRG 3
-#define MPC83XX_CLK_LBIU 4
-#define MPC83XX_CLK_LCLK 5
-#define MPC83XX_CLK_MEM 6
-#define MPC83XX_CLK_MEM_SEC 7
-#define MPC83XX_CLK_ENC 8
-#define MPC83XX_CLK_I2C1 9
-#define MPC83XX_CLK_I2C2 10
-#define MPC83XX_CLK_TDM 11
-#define MPC83XX_CLK_SDHC 12
-#define MPC83XX_CLK_TSEC1 13
-#define MPC83XX_CLK_TSEC2 14
-#define MPC83XX_CLK_USBDR 15
-#define MPC83XX_CLK_USBMPH 16
-#define MPC83XX_CLK_PCIEXP1 17
-#define MPC83XX_CLK_PCIEXP2 18
-#define MPC83XX_CLK_SATA 19
-#define MPC83XX_CLK_DMAC 20
-#define MPC83XX_CLK_PCI 21
-/* Count */
-#define MPC83XX_CLK_COUNT 22
-#endif /* DT_BINDINGS_MPC83XX_CLK_H */
diff --git a/include/dt-bindings/clk/ti-dra7-atl.h b/include/dt-bindings/clk/ti-dra7-atl.h
deleted file mode 100644
index 42dd416..0000000
--- a/include/dt-bindings/clk/ti-dra7-atl.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * This header provides constants for DRA7 ATL (Audio Tracking Logic)
- *
- * The constants defined in this header are used in dts files
- *
- * Copyright (C) 2013 Texas Instruments, Inc.
- *
- * Peter Ujfalusi <peter.ujfalusi@ti.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef _DT_BINDINGS_CLK_DRA7_ATL_H
-#define _DT_BINDINGS_CLK_DRA7_ATL_H
-
-#define DRA7_ATL_WS_MCASP1_FSR 0
-#define DRA7_ATL_WS_MCASP1_FSX 1
-#define DRA7_ATL_WS_MCASP2_FSR 2
-#define DRA7_ATL_WS_MCASP2_FSX 3
-#define DRA7_ATL_WS_MCASP3_FSX 4
-#define DRA7_ATL_WS_MCASP4_FSX 5
-#define DRA7_ATL_WS_MCASP5_FSX 6
-#define DRA7_ATL_WS_MCASP6_FSX 7
-#define DRA7_ATL_WS_MCASP7_FSX 8
-#define DRA7_ATL_WS_MCASP8_FSX 9
-#define DRA7_ATL_WS_MCASP8_AHCLKX 10
-#define DRA7_ATL_WS_XREF_CLK3 11
-#define DRA7_ATL_WS_XREF_CLK0 12
-#define DRA7_ATL_WS_XREF_CLK1 13
-#define DRA7_ATL_WS_XREF_CLK2 14
-#define DRA7_ATL_WS_OSC1_X1 15
-
-#endif
diff --git a/include/dt-bindings/clock/am3.h b/include/dt-bindings/clock/am3.h
deleted file mode 100644
index 86a8806..0000000
--- a/include/dt-bindings/clock/am3.h
+++ /dev/null
@@ -1,227 +0,0 @@
-/*
- * Copyright 2017 Texas Instruments, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-#ifndef __DT_BINDINGS_CLK_AM3_H
-#define __DT_BINDINGS_CLK_AM3_H
-
-#define AM3_CLKCTRL_OFFSET 0x0
-#define AM3_CLKCTRL_INDEX(offset) ((offset) - AM3_CLKCTRL_OFFSET)
-
-/* XXX: Compatibility part begin, remove this once compatibility support is no longer needed */
-
-/* l4_per clocks */
-#define AM3_L4_PER_CLKCTRL_OFFSET 0x14
-#define AM3_L4_PER_CLKCTRL_INDEX(offset) ((offset) - AM3_L4_PER_CLKCTRL_OFFSET)
-#define AM3_CPGMAC0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x14)
-#define AM3_LCDC_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x18)
-#define AM3_USB_OTG_HS_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x1c)
-#define AM3_TPTC0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x24)
-#define AM3_EMIF_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x28)
-#define AM3_OCMCRAM_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x2c)
-#define AM3_GPMC_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x30)
-#define AM3_MCASP0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x34)
-#define AM3_UART6_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x38)
-#define AM3_MMC1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x3c)
-#define AM3_ELM_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x40)
-#define AM3_I2C3_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x44)
-#define AM3_I2C2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x48)
-#define AM3_SPI0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x4c)
-#define AM3_SPI1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x50)
-#define AM3_L4_LS_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x60)
-#define AM3_MCASP1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x68)
-#define AM3_UART2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x6c)
-#define AM3_UART3_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x70)
-#define AM3_UART4_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x74)
-#define AM3_UART5_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x78)
-#define AM3_TIMER7_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x7c)
-#define AM3_TIMER2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x80)
-#define AM3_TIMER3_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x84)
-#define AM3_TIMER4_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x88)
-#define AM3_RNG_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x90)
-#define AM3_AES_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x94)
-#define AM3_SHAM_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xa0)
-#define AM3_GPIO2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xac)
-#define AM3_GPIO3_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xb0)
-#define AM3_GPIO4_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xb4)
-#define AM3_TPCC_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xbc)
-#define AM3_D_CAN0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xc0)
-#define AM3_D_CAN1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xc4)
-#define AM3_EPWMSS1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xcc)
-#define AM3_EPWMSS0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xd4)
-#define AM3_EPWMSS2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xd8)
-#define AM3_L3_INSTR_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xdc)
-#define AM3_L3_MAIN_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xe0)
-#define AM3_PRUSS_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xe8)
-#define AM3_TIMER5_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xec)
-#define AM3_TIMER6_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xf0)
-#define AM3_MMC2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xf4)
-#define AM3_MMC3_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xf8)
-#define AM3_TPTC1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xfc)
-#define AM3_TPTC2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x100)
-#define AM3_SPINLOCK_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x10c)
-#define AM3_MAILBOX_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x110)
-#define AM3_L4_HS_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x120)
-#define AM3_OCPWP_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x130)
-#define AM3_CLKDIV32K_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x14c)
-
-/* l4_wkup clocks */
-#define AM3_L4_WKUP_CLKCTRL_OFFSET 0x4
-#define AM3_L4_WKUP_CLKCTRL_INDEX(offset) ((offset) - AM3_L4_WKUP_CLKCTRL_OFFSET)
-#define AM3_CONTROL_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0x4)
-#define AM3_GPIO1_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0x8)
-#define AM3_L4_WKUP_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xc)
-#define AM3_DEBUGSS_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0x14)
-#define AM3_WKUP_M3_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xb0)
-#define AM3_UART1_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xb4)
-#define AM3_I2C1_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xb8)
-#define AM3_ADC_TSC_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xbc)
-#define AM3_SMARTREFLEX0_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xc0)
-#define AM3_TIMER1_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xc4)
-#define AM3_SMARTREFLEX1_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xc8)
-#define AM3_WD_TIMER2_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xd4)
-
-/* mpu clocks */
-#define AM3_MPU_CLKCTRL_OFFSET 0x4
-#define AM3_MPU_CLKCTRL_INDEX(offset) ((offset) - AM3_MPU_CLKCTRL_OFFSET)
-#define AM3_MPU_CLKCTRL AM3_MPU_CLKCTRL_INDEX(0x4)
-
-/* l4_rtc clocks */
-#define AM3_RTC_CLKCTRL AM3_CLKCTRL_INDEX(0x0)
-
-/* gfx_l3 clocks */
-#define AM3_GFX_L3_CLKCTRL_OFFSET 0x4
-#define AM3_GFX_L3_CLKCTRL_INDEX(offset) ((offset) - AM3_GFX_L3_CLKCTRL_OFFSET)
-#define AM3_GFX_CLKCTRL AM3_GFX_L3_CLKCTRL_INDEX(0x4)
-
-/* l4_cefuse clocks */
-#define AM3_L4_CEFUSE_CLKCTRL_OFFSET 0x20
-#define AM3_L4_CEFUSE_CLKCTRL_INDEX(offset) ((offset) - AM3_L4_CEFUSE_CLKCTRL_OFFSET)
-#define AM3_CEFUSE_CLKCTRL AM3_L4_CEFUSE_CLKCTRL_INDEX(0x20)
-
-/* XXX: Compatibility part end */
-
-/* l4ls clocks */
-#define AM3_L4LS_CLKCTRL_OFFSET 0x38
-#define AM3_L4LS_CLKCTRL_INDEX(offset) ((offset) - AM3_L4LS_CLKCTRL_OFFSET)
-#define AM3_L4LS_UART6_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x38)
-#define AM3_L4LS_MMC1_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x3c)
-#define AM3_L4LS_ELM_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x40)
-#define AM3_L4LS_I2C3_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x44)
-#define AM3_L4LS_I2C2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x48)
-#define AM3_L4LS_SPI0_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x4c)
-#define AM3_L4LS_SPI1_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x50)
-#define AM3_L4LS_L4_LS_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x60)
-#define AM3_L4LS_UART2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x6c)
-#define AM3_L4LS_UART3_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x70)
-#define AM3_L4LS_UART4_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x74)
-#define AM3_L4LS_UART5_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x78)
-#define AM3_L4LS_TIMER7_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x7c)
-#define AM3_L4LS_TIMER2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x80)
-#define AM3_L4LS_TIMER3_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x84)
-#define AM3_L4LS_TIMER4_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x88)
-#define AM3_L4LS_RNG_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x90)
-#define AM3_L4LS_GPIO2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xac)
-#define AM3_L4LS_GPIO3_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xb0)
-#define AM3_L4LS_GPIO4_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xb4)
-#define AM3_L4LS_D_CAN0_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xc0)
-#define AM3_L4LS_D_CAN1_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xc4)
-#define AM3_L4LS_EPWMSS1_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xcc)
-#define AM3_L4LS_EPWMSS0_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xd4)
-#define AM3_L4LS_EPWMSS2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xd8)
-#define AM3_L4LS_TIMER5_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xec)
-#define AM3_L4LS_TIMER6_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xf0)
-#define AM3_L4LS_MMC2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xf4)
-#define AM3_L4LS_SPINLOCK_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x10c)
-#define AM3_L4LS_MAILBOX_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x110)
-#define AM3_L4LS_OCPWP_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x130)
-
-/* l3s clocks */
-#define AM3_L3S_CLKCTRL_OFFSET 0x1c
-#define AM3_L3S_CLKCTRL_INDEX(offset) ((offset) - AM3_L3S_CLKCTRL_OFFSET)
-#define AM3_L3S_USB_OTG_HS_CLKCTRL AM3_L3S_CLKCTRL_INDEX(0x1c)
-#define AM3_L3S_GPMC_CLKCTRL AM3_L3S_CLKCTRL_INDEX(0x30)
-#define AM3_L3S_MCASP0_CLKCTRL AM3_L3S_CLKCTRL_INDEX(0x34)
-#define AM3_L3S_MCASP1_CLKCTRL AM3_L3S_CLKCTRL_INDEX(0x68)
-#define AM3_L3S_MMC3_CLKCTRL AM3_L3S_CLKCTRL_INDEX(0xf8)
-
-/* l3 clocks */
-#define AM3_L3_CLKCTRL_OFFSET 0x24
-#define AM3_L3_CLKCTRL_INDEX(offset) ((offset) - AM3_L3_CLKCTRL_OFFSET)
-#define AM3_L3_TPTC0_CLKCTRL AM3_L3_CLKCTRL_INDEX(0x24)
-#define AM3_L3_EMIF_CLKCTRL AM3_L3_CLKCTRL_INDEX(0x28)
-#define AM3_L3_OCMCRAM_CLKCTRL AM3_L3_CLKCTRL_INDEX(0x2c)
-#define AM3_L3_AES_CLKCTRL AM3_L3_CLKCTRL_INDEX(0x94)
-#define AM3_L3_SHAM_CLKCTRL AM3_L3_CLKCTRL_INDEX(0xa0)
-#define AM3_L3_TPCC_CLKCTRL AM3_L3_CLKCTRL_INDEX(0xbc)
-#define AM3_L3_L3_INSTR_CLKCTRL AM3_L3_CLKCTRL_INDEX(0xdc)
-#define AM3_L3_L3_MAIN_CLKCTRL AM3_L3_CLKCTRL_INDEX(0xe0)
-#define AM3_L3_TPTC1_CLKCTRL AM3_L3_CLKCTRL_INDEX(0xfc)
-#define AM3_L3_TPTC2_CLKCTRL AM3_L3_CLKCTRL_INDEX(0x100)
-
-/* l4hs clocks */
-#define AM3_L4HS_CLKCTRL_OFFSET 0x120
-#define AM3_L4HS_CLKCTRL_INDEX(offset) ((offset) - AM3_L4HS_CLKCTRL_OFFSET)
-#define AM3_L4HS_L4_HS_CLKCTRL AM3_L4HS_CLKCTRL_INDEX(0x120)
-
-/* pruss_ocp clocks */
-#define AM3_PRUSS_OCP_CLKCTRL_OFFSET 0xe8
-#define AM3_PRUSS_OCP_CLKCTRL_INDEX(offset) ((offset) - AM3_PRUSS_OCP_CLKCTRL_OFFSET)
-#define AM3_PRUSS_OCP_PRUSS_CLKCTRL AM3_PRUSS_OCP_CLKCTRL_INDEX(0xe8)
-
-/* cpsw_125mhz clocks */
-#define AM3_CPSW_125MHZ_CPGMAC0_CLKCTRL AM3_CLKCTRL_INDEX(0x14)
-
-/* lcdc clocks */
-#define AM3_LCDC_CLKCTRL_OFFSET 0x18
-#define AM3_LCDC_CLKCTRL_INDEX(offset) ((offset) - AM3_LCDC_CLKCTRL_OFFSET)
-#define AM3_LCDC_LCDC_CLKCTRL AM3_LCDC_CLKCTRL_INDEX(0x18)
-
-/* clk_24mhz clocks */
-#define AM3_CLK_24MHZ_CLKCTRL_OFFSET 0x14c
-#define AM3_CLK_24MHZ_CLKCTRL_INDEX(offset) ((offset) - AM3_CLK_24MHZ_CLKCTRL_OFFSET)
-#define AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL AM3_CLK_24MHZ_CLKCTRL_INDEX(0x14c)
-
-/* l4_wkup clocks */
-#define AM3_L4_WKUP_CONTROL_CLKCTRL AM3_CLKCTRL_INDEX(0x4)
-#define AM3_L4_WKUP_GPIO1_CLKCTRL AM3_CLKCTRL_INDEX(0x8)
-#define AM3_L4_WKUP_L4_WKUP_CLKCTRL AM3_CLKCTRL_INDEX(0xc)
-#define AM3_L4_WKUP_UART1_CLKCTRL AM3_CLKCTRL_INDEX(0xb4)
-#define AM3_L4_WKUP_I2C1_CLKCTRL AM3_CLKCTRL_INDEX(0xb8)
-#define AM3_L4_WKUP_ADC_TSC_CLKCTRL AM3_CLKCTRL_INDEX(0xbc)
-#define AM3_L4_WKUP_SMARTREFLEX0_CLKCTRL AM3_CLKCTRL_INDEX(0xc0)
-#define AM3_L4_WKUP_TIMER1_CLKCTRL AM3_CLKCTRL_INDEX(0xc4)
-#define AM3_L4_WKUP_SMARTREFLEX1_CLKCTRL AM3_CLKCTRL_INDEX(0xc8)
-#define AM3_L4_WKUP_WD_TIMER2_CLKCTRL AM3_CLKCTRL_INDEX(0xd4)
-
-/* l3_aon clocks */
-#define AM3_L3_AON_CLKCTRL_OFFSET 0x14
-#define AM3_L3_AON_CLKCTRL_INDEX(offset) ((offset) - AM3_L3_AON_CLKCTRL_OFFSET)
-#define AM3_L3_AON_DEBUGSS_CLKCTRL AM3_L3_AON_CLKCTRL_INDEX(0x14)
-
-/* l4_wkup_aon clocks */
-#define AM3_L4_WKUP_AON_CLKCTRL_OFFSET 0xb0
-#define AM3_L4_WKUP_AON_CLKCTRL_INDEX(offset) ((offset) - AM3_L4_WKUP_AON_CLKCTRL_OFFSET)
-#define AM3_L4_WKUP_AON_WKUP_M3_CLKCTRL AM3_L4_WKUP_AON_CLKCTRL_INDEX(0xb0)
-
-/* mpu clocks */
-#define AM3_MPU_MPU_CLKCTRL AM3_CLKCTRL_INDEX(0x4)
-
-/* l4_rtc clocks */
-#define AM3_L4_RTC_RTC_CLKCTRL AM3_CLKCTRL_INDEX(0x0)
-
-/* gfx_l3 clocks */
-#define AM3_GFX_L3_GFX_CLKCTRL AM3_CLKCTRL_INDEX(0x4)
-
-/* l4_cefuse clocks */
-#define AM3_L4_CEFUSE_CEFUSE_CLKCTRL AM3_CLKCTRL_INDEX(0x20)
-
-#endif
diff --git a/include/dt-bindings/clock/ast2500-scu.h b/include/dt-bindings/clock/ast2500-scu.h
deleted file mode 100644
index 4803abe..0000000
--- a/include/dt-bindings/clock/ast2500-scu.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2016 Google Inc.
- */
-
-/* Core Clocks */
-#define PLL_HPLL 1
-#define PLL_DPLL 2
-#define PLL_D2PLL 3
-#define PLL_MPLL 4
-#define ARMCLK 5
-
-
-/* Bus Clocks, derived from core clocks */
-#define BCLK_PCLK 101
-#define BCLK_LHCLK 102
-#define BCLK_MACCLK 103
-#define BCLK_SDCLK 104
-#define BCLK_ARMCLK 105
-
-#define MCLK_DDR 201
-
-/* Special clocks */
-#define PCLK_UART1 501
-#define PCLK_UART2 502
-#define PCLK_UART3 503
-#define PCLK_UART4 504
-#define PCLK_UART5 505
-#define PCLK_MAC1 506
-#define PCLK_MAC2 507
diff --git a/include/dt-bindings/clock/at91.h b/include/dt-bindings/clock/at91.h
deleted file mode 100644
index ab3ee24..0000000
--- a/include/dt-bindings/clock/at91.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * This header provides constants for AT91 pmc status.
- *
- * The constants defined in this header are being used in dts.
- *
- * Licensed under GPLv2 or later.
- */
-
-#ifndef _DT_BINDINGS_CLK_AT91_H
-#define _DT_BINDINGS_CLK_AT91_H
-
-#define AT91_PMC_MOSCS 0 /* MOSCS Flag */
-#define AT91_PMC_LOCKA 1 /* PLLA Lock */
-#define AT91_PMC_LOCKB 2 /* PLLB Lock */
-#define AT91_PMC_MCKRDY 3 /* Master Clock */
-#define AT91_PMC_LOCKU 6 /* UPLL Lock */
-#define AT91_PMC_PCKRDY(id) (8 + (id)) /* Programmable Clock */
-#define AT91_PMC_MOSCSELS 16 /* Main Oscillator Selection */
-#define AT91_PMC_MOSCRCS 17 /* Main On-Chip RC */
-#define AT91_PMC_CFDEV 18 /* Clock Failure Detector Event */
-#define AT91_PMC_GCKRDY 24 /* Generated Clocks */
-
-#endif
diff --git a/include/dt-bindings/clock/axg-aoclkc.h b/include/dt-bindings/clock/axg-aoclkc.h
deleted file mode 100644
index 8ec4a26..0000000
--- a/include/dt-bindings/clock/axg-aoclkc.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
-/*
- * Copyright (c) 2016 BayLibre, SAS
- * Author: Neil Armstrong <narmstrong@baylibre.com>
- *
- * Copyright (c) 2018 Amlogic, inc.
- * Author: Qiufang Dai <qiufang.dai@amlogic.com>
- */
-
-#ifndef DT_BINDINGS_CLOCK_AMLOGIC_MESON_AXG_AOCLK
-#define DT_BINDINGS_CLOCK_AMLOGIC_MESON_AXG_AOCLK
-
-#define CLKID_AO_REMOTE 0
-#define CLKID_AO_I2C_MASTER 1
-#define CLKID_AO_I2C_SLAVE 2
-#define CLKID_AO_UART1 3
-#define CLKID_AO_UART2 4
-#define CLKID_AO_IR_BLASTER 5
-#define CLKID_AO_SAR_ADC 6
-#define CLKID_AO_CLK81 7
-#define CLKID_AO_SAR_ADC_SEL 8
-#define CLKID_AO_SAR_ADC_DIV 9
-#define CLKID_AO_SAR_ADC_CLK 10
-#define CLKID_AO_CTS_OSCIN 11
-#define CLKID_AO_32K_PRE 12
-#define CLKID_AO_32K_DIV 13
-#define CLKID_AO_32K_SEL 14
-#define CLKID_AO_32K 15
-#define CLKID_AO_CTS_RTC_OSCIN 16
-
-#endif
diff --git a/include/dt-bindings/clock/axg-audio-clkc.h b/include/dt-bindings/clock/axg-audio-clkc.h
deleted file mode 100644
index 75901c6..0000000
--- a/include/dt-bindings/clock/axg-audio-clkc.h
+++ /dev/null
@@ -1,84 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
-/*
- * Copyright (c) 2018 Baylibre SAS.
- * Author: Jerome Brunet <jbrunet@baylibre.com>
- */
-
-#ifndef __AXG_AUDIO_CLKC_BINDINGS_H
-#define __AXG_AUDIO_CLKC_BINDINGS_H
-
-#define AUD_CLKID_DDR_ARB 29
-#define AUD_CLKID_PDM 30
-#define AUD_CLKID_TDMIN_A 31
-#define AUD_CLKID_TDMIN_B 32
-#define AUD_CLKID_TDMIN_C 33
-#define AUD_CLKID_TDMIN_LB 34
-#define AUD_CLKID_TDMOUT_A 35
-#define AUD_CLKID_TDMOUT_B 36
-#define AUD_CLKID_TDMOUT_C 37
-#define AUD_CLKID_FRDDR_A 38
-#define AUD_CLKID_FRDDR_B 39
-#define AUD_CLKID_FRDDR_C 40
-#define AUD_CLKID_TODDR_A 41
-#define AUD_CLKID_TODDR_B 42
-#define AUD_CLKID_TODDR_C 43
-#define AUD_CLKID_LOOPBACK 44
-#define AUD_CLKID_SPDIFIN 45
-#define AUD_CLKID_SPDIFOUT 46
-#define AUD_CLKID_RESAMPLE 47
-#define AUD_CLKID_POWER_DETECT 48
-#define AUD_CLKID_MST_A_MCLK 49
-#define AUD_CLKID_MST_B_MCLK 50
-#define AUD_CLKID_MST_C_MCLK 51
-#define AUD_CLKID_MST_D_MCLK 52
-#define AUD_CLKID_MST_E_MCLK 53
-#define AUD_CLKID_MST_F_MCLK 54
-#define AUD_CLKID_SPDIFOUT_CLK 55
-#define AUD_CLKID_SPDIFIN_CLK 56
-#define AUD_CLKID_PDM_DCLK 57
-#define AUD_CLKID_PDM_SYSCLK 58
-#define AUD_CLKID_MST_A_SCLK 79
-#define AUD_CLKID_MST_B_SCLK 80
-#define AUD_CLKID_MST_C_SCLK 81
-#define AUD_CLKID_MST_D_SCLK 82
-#define AUD_CLKID_MST_E_SCLK 83
-#define AUD_CLKID_MST_F_SCLK 84
-#define AUD_CLKID_MST_A_LRCLK 86
-#define AUD_CLKID_MST_B_LRCLK 87
-#define AUD_CLKID_MST_C_LRCLK 88
-#define AUD_CLKID_MST_D_LRCLK 89
-#define AUD_CLKID_MST_E_LRCLK 90
-#define AUD_CLKID_MST_F_LRCLK 91
-#define AUD_CLKID_TDMIN_A_SCLK_SEL 116
-#define AUD_CLKID_TDMIN_B_SCLK_SEL 117
-#define AUD_CLKID_TDMIN_C_SCLK_SEL 118
-#define AUD_CLKID_TDMIN_LB_SCLK_SEL 119
-#define AUD_CLKID_TDMOUT_A_SCLK_SEL 120
-#define AUD_CLKID_TDMOUT_B_SCLK_SEL 121
-#define AUD_CLKID_TDMOUT_C_SCLK_SEL 122
-#define AUD_CLKID_TDMIN_A_SCLK 123
-#define AUD_CLKID_TDMIN_B_SCLK 124
-#define AUD_CLKID_TDMIN_C_SCLK 125
-#define AUD_CLKID_TDMIN_LB_SCLK 126
-#define AUD_CLKID_TDMOUT_A_SCLK 127
-#define AUD_CLKID_TDMOUT_B_SCLK 128
-#define AUD_CLKID_TDMOUT_C_SCLK 129
-#define AUD_CLKID_TDMIN_A_LRCLK 130
-#define AUD_CLKID_TDMIN_B_LRCLK 131
-#define AUD_CLKID_TDMIN_C_LRCLK 132
-#define AUD_CLKID_TDMIN_LB_LRCLK 133
-#define AUD_CLKID_TDMOUT_A_LRCLK 134
-#define AUD_CLKID_TDMOUT_B_LRCLK 135
-#define AUD_CLKID_TDMOUT_C_LRCLK 136
-#define AUD_CLKID_SPDIFOUT_B 151
-#define AUD_CLKID_SPDIFOUT_B_CLK 152
-#define AUD_CLKID_TDM_MCLK_PAD0 155
-#define AUD_CLKID_TDM_MCLK_PAD1 156
-#define AUD_CLKID_TDM_LRCLK_PAD0 157
-#define AUD_CLKID_TDM_LRCLK_PAD1 158
-#define AUD_CLKID_TDM_LRCLK_PAD2 159
-#define AUD_CLKID_TDM_SCLK_PAD0 160
-#define AUD_CLKID_TDM_SCLK_PAD1 161
-#define AUD_CLKID_TDM_SCLK_PAD2 162
-
-#endif /* __AXG_AUDIO_CLKC_BINDINGS_H */
diff --git a/include/dt-bindings/clock/axg-clkc.h b/include/dt-bindings/clock/axg-clkc.h
deleted file mode 100644
index fd1f938..0000000
--- a/include/dt-bindings/clock/axg-clkc.h
+++ /dev/null
@@ -1,76 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
-/*
- * Meson-AXG clock tree IDs
- *
- * Copyright (c) 2017 Amlogic, Inc. All rights reserved.
- */
-
-#ifndef __AXG_CLKC_H
-#define __AXG_CLKC_H
-
-#define CLKID_SYS_PLL 0
-#define CLKID_FIXED_PLL 1
-#define CLKID_FCLK_DIV2 2
-#define CLKID_FCLK_DIV3 3
-#define CLKID_FCLK_DIV4 4
-#define CLKID_FCLK_DIV5 5
-#define CLKID_FCLK_DIV7 6
-#define CLKID_GP0_PLL 7
-#define CLKID_CLK81 10
-#define CLKID_MPLL0 11
-#define CLKID_MPLL1 12
-#define CLKID_MPLL2 13
-#define CLKID_MPLL3 14
-#define CLKID_DDR 15
-#define CLKID_AUDIO_LOCKER 16
-#define CLKID_MIPI_DSI_HOST 17
-#define CLKID_ISA 18
-#define CLKID_PL301 19
-#define CLKID_PERIPHS 20
-#define CLKID_SPICC0 21
-#define CLKID_I2C 22
-#define CLKID_RNG0 23
-#define CLKID_UART0 24
-#define CLKID_MIPI_DSI_PHY 25
-#define CLKID_SPICC1 26
-#define CLKID_PCIE_A 27
-#define CLKID_PCIE_B 28
-#define CLKID_HIU_IFACE 29
-#define CLKID_ASSIST_MISC 30
-#define CLKID_SD_EMMC_B 31
-#define CLKID_SD_EMMC_C 32
-#define CLKID_DMA 33
-#define CLKID_SPI 34
-#define CLKID_AUDIO 35
-#define CLKID_ETH 36
-#define CLKID_UART1 37
-#define CLKID_G2D 38
-#define CLKID_USB0 39
-#define CLKID_USB1 40
-#define CLKID_RESET 41
-#define CLKID_USB 42
-#define CLKID_AHB_ARB0 43
-#define CLKID_EFUSE 44
-#define CLKID_BOOT_ROM 45
-#define CLKID_AHB_DATA_BUS 46
-#define CLKID_AHB_CTRL_BUS 47
-#define CLKID_USB1_DDR_BRIDGE 48
-#define CLKID_USB0_DDR_BRIDGE 49
-#define CLKID_MMC_PCLK 50
-#define CLKID_VPU_INTR 51
-#define CLKID_SEC_AHB_AHB3_BRIDGE 52
-#define CLKID_GIC 53
-#define CLKID_AO_MEDIA_CPU 54
-#define CLKID_AO_AHB_SRAM 55
-#define CLKID_AO_AHB_BUS 56
-#define CLKID_AO_IFACE 57
-#define CLKID_AO_I2C 58
-#define CLKID_SD_EMMC_B_CLK0 59
-#define CLKID_SD_EMMC_C_CLK0 60
-#define CLKID_HIFI_PLL 69
-#define CLKID_PCIE_CML_EN0 79
-#define CLKID_PCIE_CML_EN1 80
-#define CLKID_MIPI_ENABLE 81
-#define CLKID_GEN_CLK 84
-
-#endif /* __AXG_CLKC_H */
diff --git a/include/dt-bindings/clock/bcm2835-aux.h b/include/dt-bindings/clock/bcm2835-aux.h
deleted file mode 100644
index bb79de3..0000000
--- a/include/dt-bindings/clock/bcm2835-aux.h
+++ /dev/null
@@ -1,9 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2015 Broadcom Corporation
- */
-
-#define BCM2835_AUX_CLOCK_UART 0
-#define BCM2835_AUX_CLOCK_SPI1 1
-#define BCM2835_AUX_CLOCK_SPI2 2
-#define BCM2835_AUX_CLOCK_COUNT 3
diff --git a/include/dt-bindings/clock/bcm2835.h b/include/dt-bindings/clock/bcm2835.h
deleted file mode 100644
index 2cec01f..0000000
--- a/include/dt-bindings/clock/bcm2835.h
+++ /dev/null
@@ -1,60 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2015 Broadcom Corporation
- */
-
-#define BCM2835_PLLA 0
-#define BCM2835_PLLB 1
-#define BCM2835_PLLC 2
-#define BCM2835_PLLD 3
-#define BCM2835_PLLH 4
-
-#define BCM2835_PLLA_CORE 5
-#define BCM2835_PLLA_PER 6
-#define BCM2835_PLLB_ARM 7
-#define BCM2835_PLLC_CORE0 8
-#define BCM2835_PLLC_CORE1 9
-#define BCM2835_PLLC_CORE2 10
-#define BCM2835_PLLC_PER 11
-#define BCM2835_PLLD_CORE 12
-#define BCM2835_PLLD_PER 13
-#define BCM2835_PLLH_RCAL 14
-#define BCM2835_PLLH_AUX 15
-#define BCM2835_PLLH_PIX 16
-
-#define BCM2835_CLOCK_TIMER 17
-#define BCM2835_CLOCK_OTP 18
-#define BCM2835_CLOCK_UART 19
-#define BCM2835_CLOCK_VPU 20
-#define BCM2835_CLOCK_V3D 21
-#define BCM2835_CLOCK_ISP 22
-#define BCM2835_CLOCK_H264 23
-#define BCM2835_CLOCK_VEC 24
-#define BCM2835_CLOCK_HSM 25
-#define BCM2835_CLOCK_SDRAM 26
-#define BCM2835_CLOCK_TSENS 27
-#define BCM2835_CLOCK_EMMC 28
-#define BCM2835_CLOCK_PERI_IMAGE 29
-#define BCM2835_CLOCK_PWM 30
-#define BCM2835_CLOCK_PCM 31
-
-#define BCM2835_PLLA_DSI0 32
-#define BCM2835_PLLA_CCP2 33
-#define BCM2835_PLLD_DSI0 34
-#define BCM2835_PLLD_DSI1 35
-
-#define BCM2835_CLOCK_AVEO 36
-#define BCM2835_CLOCK_DFT 37
-#define BCM2835_CLOCK_GP0 38
-#define BCM2835_CLOCK_GP1 39
-#define BCM2835_CLOCK_GP2 40
-#define BCM2835_CLOCK_SLIM 41
-#define BCM2835_CLOCK_SMI 42
-#define BCM2835_CLOCK_TEC 43
-#define BCM2835_CLOCK_DPI 44
-#define BCM2835_CLOCK_CAM0 45
-#define BCM2835_CLOCK_CAM1 46
-#define BCM2835_CLOCK_DSI0E 47
-#define BCM2835_CLOCK_DSI1E 48
-#define BCM2835_CLOCK_DSI0P 49
-#define BCM2835_CLOCK_DSI1P 50
diff --git a/include/dt-bindings/clock/bcm3380-clock.h b/include/dt-bindings/clock/bcm3380-clock.h
deleted file mode 100644
index 998d08f..0000000
--- a/include/dt-bindings/clock/bcm3380-clock.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
- *
- * Derived from Broadcom GPL Source Code:
- * Copyright (C) Broadcom Corporation
- */
-
-#ifndef __DT_BINDINGS_CLOCK_BCM3380_H
-#define __DT_BINDINGS_CLOCK_BCM3380_H
-
-#define BCM3380_CLK0_DDR 0
-#define BCM3380_CLK0_FPM 1
-#define BCM3380_CLK0_CRYPTO 2
-#define BCM3380_CLK0_EPHY 3
-#define BCM3380_CLK0_PCIE 16
-#define BCM3380_CLK0_SPI 17
-#define BCM3380_CLK0_ENET0 18
-#define BCM3380_CLK0_ENET1 19
-#define BCM3380_CLK0_PCM 27
-
-#endif /* __DT_BINDINGS_CLOCK_BCM3380_H */
diff --git a/include/dt-bindings/clock/bcm6318-clock.h b/include/dt-bindings/clock/bcm6318-clock.h
deleted file mode 100644
index 3f10448..0000000
--- a/include/dt-bindings/clock/bcm6318-clock.h
+++ /dev/null
@@ -1,47 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2018 Álvaro Fernández Rojas <noltari@gmail.com>
- *
- * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
- */
-
-#ifndef __DT_BINDINGS_CLOCK_BCM6318_H
-#define __DT_BINDINGS_CLOCK_BCM6318_H
-
-#define BCM6318_CLK_ADSL_ASB 0
-#define BCM6318_CLK_USB_ASB 1
-#define BCM6318_CLK_MIPS_ASB 2
-#define BCM6318_CLK_PCIE_ASB 3
-#define BCM6318_CLK_PHYMIPS_ASB 4
-#define BCM6318_CLK_ROBOSW_ASB 5
-#define BCM6318_CLK_SAR_ASB 6
-#define BCM6318_CLK_SDR_ASB 7
-#define BCM6318_CLK_SWREG_ASB 8
-#define BCM6318_CLK_PERIPH_ASB 9
-#define BCM6318_CLK_CPUBUS160 10
-#define BCM6318_CLK_ADSL 11
-#define BCM6318_CLK_SAR125 12
-#define BCM6318_CLK_MIPS 13
-#define BCM6318_CLK_PCIE 14
-#define BCM6318_CLK_ROBOSW250 16
-#define BCM6318_CLK_ROBOSW025 17
-#define BCM6318_CLK_SDR 19
-#define BCM6318_CLK_USB 20
-#define BCM6318_CLK_HSSPI 25
-#define BCM6318_CLK_PCIE25 27
-#define BCM6318_CLK_PHYMIPS 28
-#define BCM6318_CLK_AFE 29
-#define BCM6318_CLK_QPROC 30
-
-#define BCM6318_UCLK_ADSL 0
-#define BCM6318_UCLK_ARB 1
-#define BCM6318_UCLK_MIPS 2
-#define BCM6318_UCLK_PCIE 3
-#define BCM6318_UCLK_PERIPH 4
-#define BCM6318_UCLK_PHYMIPS 5
-#define BCM6318_UCLK_ROBOSW 6
-#define BCM6318_UCLK_SAR 7
-#define BCM6318_UCLK_SDR 8
-#define BCM6318_UCLK_USB 9
-
-#endif /* __DT_BINDINGS_CLOCK_BCM6318_H */
diff --git a/include/dt-bindings/clock/bcm63268-clock.h b/include/dt-bindings/clock/bcm63268-clock.h
deleted file mode 100644
index 2725dcd..0000000
--- a/include/dt-bindings/clock/bcm63268-clock.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
- *
- * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
- */
-
-#ifndef __DT_BINDINGS_CLOCK_BCM63268_H
-#define __DT_BINDINGS_CLOCK_BCM63268_H
-
-#define BCM63268_CLK_GLESS 0
-#define BCM63268_CLK_VDSL_QPROC 1
-#define BCM63268_CLK_VDSL_AFE 2
-#define BCM63268_CLK_VDSL 3
-#define BCM63268_CLK_MIPS 4
-#define BCM63268_CLK_WLAN_OCP 5
-#define BCM63268_CLK_DECT 6
-#define BCM63268_CLK_FAP0 7
-#define BCM63268_CLK_FAP1 8
-#define BCM63268_CLK_SAR 9
-#define BCM63268_CLK_ROBOSW 10
-#define BCM63268_CLK_PCM 11
-#define BCM63268_CLK_USBD 12
-#define BCM63268_CLK_USBH 13
-#define BCM63268_CLK_IPSEC 14
-#define BCM63268_CLK_SPI 15
-#define BCM63268_CLK_HSSPI 16
-#define BCM63268_CLK_PCIE 17
-#define BCM63268_CLK_PHYMIPS 18
-#define BCM63268_CLK_GMAC 19
-#define BCM63268_CLK_NAND 20
-#define BCM63268_CLK_TBUS 27
-#define BCM63268_CLK_ROBOSW250 31
-
-#define BCM63268_TCLK_EPHY1 0
-#define BCM63268_TCLK_EPHY2 1
-#define BCM63268_TCLK_EPHY3 2
-#define BCM63268_TCLK_GPHY 3
-#define BCM63268_TCLK_DSL 4
-#define BCM63268_TCLK_WO_EPHY 5
-#define BCM63268_TCLK_WO_DSL 6
-#define BCM63268_TCLK_FAP1 11
-#define BCM63268_TCLK_FAP2 15
-#define BCM63268_TCLK_UTO_50 16
-#define BCM63268_TCLK_UTO_EXT 17
-#define BCM63268_TCLK_USB_REF 18
-#define BCM63268_TCLK_SW_RST 29
-#define BCM63268_TCLK_HW_RST 30
-#define BCM63268_TCLK_POR_RST 31
-
-#endif /* __DT_BINDINGS_CLOCK_BCM63268_H */
diff --git a/include/dt-bindings/clock/bcm6328-clock.h b/include/dt-bindings/clock/bcm6328-clock.h
deleted file mode 100644
index 6f1e018..0000000
--- a/include/dt-bindings/clock/bcm6328-clock.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
- *
- * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
- */
-
-#ifndef __DT_BINDINGS_CLOCK_BCM6328_H
-#define __DT_BINDINGS_CLOCK_BCM6328_H
-
-#define BCM6328_CLK_PHYMIPS 0
-#define BCM6328_CLK_ADSL_QPROC 1
-#define BCM6328_CLK_ADSL_AFE 2
-#define BCM6328_CLK_ADSL 3
-#define BCM6328_CLK_MIPS 4
-#define BCM6328_CLK_SAR 5
-#define BCM6328_CLK_PCM 6
-#define BCM6328_CLK_USBD 7
-#define BCM6328_CLK_USBH 8
-#define BCM6328_CLK_HSSPI 9
-#define BCM6328_CLK_PCIE 10
-#define BCM6328_CLK_ROBOSW 11
-
-#endif /* __DT_BINDINGS_CLOCK_BCM6328_H */
diff --git a/include/dt-bindings/clock/bcm6338-clock.h b/include/dt-bindings/clock/bcm6338-clock.h
deleted file mode 100644
index 489aa1f..0000000
--- a/include/dt-bindings/clock/bcm6338-clock.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
- *
- * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
- */
-
-#ifndef __DT_BINDINGS_CLOCK_BCM6338_H
-#define __DT_BINDINGS_CLOCK_BCM6338_H
-
-#define BCM6338_CLK_ADSL 0
-#define BCM6338_CLK_MPI 1
-#define BCM6338_CLK_SDRAM 2
-#define BCM6338_CLK_ENET 4
-#define BCM6338_CLK_SAR 5
-#define BCM6338_CLK_SPI 9
-
-#endif /* __DT_BINDINGS_CLOCK_BCM6338_H */
diff --git a/include/dt-bindings/clock/bcm6348-clock.h b/include/dt-bindings/clock/bcm6348-clock.h
deleted file mode 100644
index c67a7fe..0000000
--- a/include/dt-bindings/clock/bcm6348-clock.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
- *
- * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
- */
-
-#ifndef __DT_BINDINGS_CLOCK_BCM6348_H
-#define __DT_BINDINGS_CLOCK_BCM6348_H
-
-#define BCM6348_CLK_ADSL 0
-#define BCM6348_CLK_MPI 1
-#define BCM6348_CLK_SDRAM 2
-#define BCM6348_CLK_M2M 3
-#define BCM6348_CLK_ENET 4
-#define BCM6348_CLK_SAR 5
-#define BCM6348_CLK_USBS 6
-#define BCM6348_CLK_USBH 8
-#define BCM6348_CLK_SPI 9
-
-#endif /* __DT_BINDINGS_CLOCK_BCM6348_H */
diff --git a/include/dt-bindings/clock/bcm6358-clock.h b/include/dt-bindings/clock/bcm6358-clock.h
deleted file mode 100644
index a7529bc..0000000
--- a/include/dt-bindings/clock/bcm6358-clock.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
- *
- * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
- */
-
-#ifndef __DT_BINDINGS_CLOCK_BCM6358_H
-#define __DT_BINDINGS_CLOCK_BCM6358_H
-
-#define BCM6358_CLK_ENET 4
-#define BCM6358_CLK_ADSL 5
-#define BCM6358_CLK_PCM 8
-#define BCM6358_CLK_SPI 9
-#define BCM6358_CLK_USBS 10
-#define BCM6358_CLK_SAR 11
-#define BCM6358_CLK_EMUSB 17
-#define BCM6358_CLK_ENET0 18
-#define BCM6358_CLK_ENET1 19
-#define BCM6358_CLK_USBSU 20
-#define BCM6358_CLK_EPHY 21
-
-#endif /* __DT_BINDINGS_CLOCK_BCM6358_H */
diff --git a/include/dt-bindings/clock/bcm6362-clock.h b/include/dt-bindings/clock/bcm6362-clock.h
deleted file mode 100644
index d3770c5..0000000
--- a/include/dt-bindings/clock/bcm6362-clock.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2018 Álvaro Fernández Rojas <noltari@gmail.com>
- *
- * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
- */
-
-#ifndef __DT_BINDINGS_CLOCK_BCM6362_H
-#define __DT_BINDINGS_CLOCK_BCM6362_H
-
-#define BCM6362_CLK_GLESS 0
-#define BCM6362_CLK_ADSL_QPROC 1
-#define BCM6362_CLK_ADSL_AFE 2
-#define BCM6362_CLK_ADSL 3
-#define BCM6362_CLK_MIPS 4
-#define BCM6362_CLK_WLAN_OCP 5
-#define BCM6362_CLK_SWPKT_USB 7
-#define BCM6362_CLK_SWPKT_SAR 8
-#define BCM6362_CLK_SAR 9
-#define BCM6362_CLK_ROBOSW 10
-#define BCM6362_CLK_PCM 11
-#define BCM6362_CLK_USBD 12
-#define BCM6362_CLK_USBH 13
-#define BCM6362_CLK_IPSEC 14
-#define BCM6362_CLK_SPI 15
-#define BCM6362_CLK_HSSPI 16
-#define BCM6362_CLK_PCIE 17
-#define BCM6362_CLK_FAP 18
-#define BCM6362_CLK_PHYMIPS 19
-#define BCM6362_CLK_NAND 20
-
-#endif /* __DT_BINDINGS_CLOCK_BCM6362_H */
diff --git a/include/dt-bindings/clock/bcm6368-clock.h b/include/dt-bindings/clock/bcm6368-clock.h
deleted file mode 100644
index 0c85782..0000000
--- a/include/dt-bindings/clock/bcm6368-clock.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
- *
- * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
- */
-
-#ifndef __DT_BINDINGS_CLOCK_BCM6368_H
-#define __DT_BINDINGS_CLOCK_BCM6368_H
-
-#define BCM6368_CLK_VDSL_QPROC 2
-#define BCM6368_CLK_VDSL_AFE 3
-#define BCM6368_CLK_VDSL_BONDING 4
-#define BCM6368_CLK_VDSL 5
-#define BCM6368_CLK_PHYMIPS 6
-#define BCM6368_CLK_SWPKT_USB 7
-#define BCM6368_CLK_SWPKT_SAR 8
-#define BCM6368_CLK_SPI 9
-#define BCM6368_CLK_USBD 10
-#define BCM6368_CLK_SAR 11
-#define BCM6368_CLK_ROBOSW 12
-#define BCM6368_CLK_UTOPIA 13
-#define BCM6368_CLK_PCM 14
-#define BCM6368_CLK_USBH 15
-#define BCM6368_CLK_GLESS 16
-#define BCM6368_CLK_NAND 17
-#define BCM6368_CLK_IPSEC 18
-#define BCM6368_CLK_USBH_IDDQ 19
-
-#endif /* __DT_BINDINGS_CLOCK_BCM6368_H */
diff --git a/include/dt-bindings/clock/boston-clock.h b/include/dt-bindings/clock/boston-clock.h
deleted file mode 100644
index 0b39062..0000000
--- a/include/dt-bindings/clock/boston-clock.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2016 Imagination Technologies
- */
-
-#ifndef __DT_BINDINGS_CLOCK_BOSTON_CLOCK_H__
-#define __DT_BINDINGS_CLOCK_BOSTON_CLOCK_H__
-
-#define BOSTON_CLK_SYS 0
-#define BOSTON_CLK_CPU 1
-
-#endif /* __DT_BINDINGS_CLOCK_BOSTON_CLOCK_H__ */
diff --git a/include/dt-bindings/clock/exynos7420-clk.h b/include/dt-bindings/clock/exynos7420-clk.h
deleted file mode 100644
index 10c5586..0000000
--- a/include/dt-bindings/clock/exynos7420-clk.h
+++ /dev/null
@@ -1,207 +0,0 @@
-/*
- * Copyright (c) 2014 Samsung Electronics Co., Ltd.
- * Author: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef _DT_BINDINGS_CLOCK_EXYNOS7_H
-#define _DT_BINDINGS_CLOCK_EXYNOS7_H
-
-/* TOPC */
-#define DOUT_ACLK_PERIS 1
-#define DOUT_SCLK_BUS0_PLL 2
-#define DOUT_SCLK_BUS1_PLL 3
-#define DOUT_SCLK_CC_PLL 4
-#define DOUT_SCLK_MFC_PLL 5
-#define DOUT_ACLK_CCORE_133 6
-#define DOUT_ACLK_MSCL_532 7
-#define ACLK_MSCL_532 8
-#define DOUT_SCLK_AUD_PLL 9
-#define FOUT_AUD_PLL 10
-#define SCLK_AUD_PLL 11
-#define SCLK_MFC_PLL_B 12
-#define SCLK_MFC_PLL_A 13
-#define SCLK_BUS1_PLL_B 14
-#define SCLK_BUS1_PLL_A 15
-#define SCLK_BUS0_PLL_B 16
-#define SCLK_BUS0_PLL_A 17
-#define SCLK_CC_PLL_B 18
-#define SCLK_CC_PLL_A 19
-#define ACLK_CCORE_133 20
-#define ACLK_PERIS_66 21
-#define TOPC_NR_CLK 22
-
-/* TOP0 */
-#define DOUT_ACLK_PERIC1 1
-#define DOUT_ACLK_PERIC0 2
-#define CLK_SCLK_UART0 3
-#define CLK_SCLK_UART1 4
-#define CLK_SCLK_UART2 5
-#define CLK_SCLK_UART3 6
-#define CLK_SCLK_SPI0 7
-#define CLK_SCLK_SPI1 8
-#define CLK_SCLK_SPI2 9
-#define CLK_SCLK_SPI3 10
-#define CLK_SCLK_SPI4 11
-#define CLK_SCLK_SPDIF 12
-#define CLK_SCLK_PCM1 13
-#define CLK_SCLK_I2S1 14
-#define CLK_ACLK_PERIC0_66 15
-#define CLK_ACLK_PERIC1_66 16
-#define TOP0_NR_CLK 17
-
-/* TOP1 */
-#define DOUT_ACLK_FSYS1_200 1
-#define DOUT_ACLK_FSYS0_200 2
-#define DOUT_SCLK_MMC2 3
-#define DOUT_SCLK_MMC1 4
-#define DOUT_SCLK_MMC0 5
-#define CLK_SCLK_MMC2 6
-#define CLK_SCLK_MMC1 7
-#define CLK_SCLK_MMC0 8
-#define CLK_ACLK_FSYS0_200 9
-#define CLK_ACLK_FSYS1_200 10
-#define CLK_SCLK_PHY_FSYS1 11
-#define CLK_SCLK_PHY_FSYS1_26M 12
-#define MOUT_SCLK_UFSUNIPRO20 13
-#define DOUT_SCLK_UFSUNIPRO20 14
-#define CLK_SCLK_UFSUNIPRO20 15
-#define DOUT_SCLK_PHY_FSYS1 16
-#define DOUT_SCLK_PHY_FSYS1_26M 17
-#define TOP1_NR_CLK 18
-
-/* CCORE */
-#define PCLK_RTC 1
-#define CCORE_NR_CLK 2
-
-/* PERIC0 */
-#define PCLK_UART0 1
-#define SCLK_UART0 2
-#define PCLK_HSI2C0 3
-#define PCLK_HSI2C1 4
-#define PCLK_HSI2C4 5
-#define PCLK_HSI2C5 6
-#define PCLK_HSI2C9 7
-#define PCLK_HSI2C10 8
-#define PCLK_HSI2C11 9
-#define PCLK_PWM 10
-#define SCLK_PWM 11
-#define PCLK_ADCIF 12
-#define PERIC0_NR_CLK 13
-
-/* PERIC1 */
-#define PCLK_UART1 1
-#define PCLK_UART2 2
-#define PCLK_UART3 3
-#define SCLK_UART1 4
-#define SCLK_UART2 5
-#define SCLK_UART3 6
-#define PCLK_HSI2C2 7
-#define PCLK_HSI2C3 8
-#define PCLK_HSI2C6 9
-#define PCLK_HSI2C7 10
-#define PCLK_HSI2C8 11
-#define PCLK_SPI0 12
-#define PCLK_SPI1 13
-#define PCLK_SPI2 14
-#define PCLK_SPI3 15
-#define PCLK_SPI4 16
-#define SCLK_SPI0 17
-#define SCLK_SPI1 18
-#define SCLK_SPI2 19
-#define SCLK_SPI3 20
-#define SCLK_SPI4 21
-#define PCLK_I2S1 22
-#define PCLK_PCM1 23
-#define PCLK_SPDIF 24
-#define SCLK_I2S1 25
-#define SCLK_PCM1 26
-#define SCLK_SPDIF 27
-#define PERIC1_NR_CLK 28
-
-/* PERIS */
-#define PCLK_CHIPID 1
-#define SCLK_CHIPID 2
-#define PCLK_WDT 3
-#define PCLK_TMU 4
-#define SCLK_TMU 5
-#define PERIS_NR_CLK 6
-
-/* FSYS0 */
-#define ACLK_MMC2 1
-#define ACLK_AXIUS_USBDRD30X_FSYS0X 2
-#define ACLK_USBDRD300 3
-#define SCLK_USBDRD300_SUSPENDCLK 4
-#define SCLK_USBDRD300_REFCLK 5
-#define PHYCLK_USBDRD300_UDRD30_PIPE_PCLK_USER 6
-#define PHYCLK_USBDRD300_UDRD30_PHYCLK_USER 7
-#define OSCCLK_PHY_CLKOUT_USB30_PHY 8
-#define ACLK_PDMA0 9
-#define ACLK_PDMA1 10
-#define FSYS0_NR_CLK 11
-
-/* FSYS1 */
-#define ACLK_MMC1 1
-#define ACLK_MMC0 2
-#define PHYCLK_UFS20_TX0_SYMBOL 3
-#define PHYCLK_UFS20_RX0_SYMBOL 4
-#define PHYCLK_UFS20_RX1_SYMBOL 5
-#define ACLK_UFS20_LINK 6
-#define SCLK_UFSUNIPRO20_USER 7
-#define PHYCLK_UFS20_RX1_SYMBOL_USER 8
-#define PHYCLK_UFS20_RX0_SYMBOL_USER 9
-#define PHYCLK_UFS20_TX0_SYMBOL_USER 10
-#define OSCCLK_PHY_CLKOUT_EMBEDDED_COMBO_PHY 11
-#define SCLK_COMBO_PHY_EMBEDDED_26M 12
-#define DOUT_PCLK_FSYS1 13
-#define PCLK_GPIO_FSYS1 14
-#define MOUT_FSYS1_PHYCLK_SEL1 15
-#define FSYS1_NR_CLK 16
-
-/* MSCL */
-#define USERMUX_ACLK_MSCL_532 1
-#define DOUT_PCLK_MSCL 2
-#define ACLK_MSCL_0 3
-#define ACLK_MSCL_1 4
-#define ACLK_JPEG 5
-#define ACLK_G2D 6
-#define ACLK_LH_ASYNC_SI_MSCL_0 7
-#define ACLK_LH_ASYNC_SI_MSCL_1 8
-#define ACLK_AXI2ACEL_BRIDGE 9
-#define ACLK_XIU_MSCLX_0 10
-#define ACLK_XIU_MSCLX_1 11
-#define ACLK_QE_MSCL_0 12
-#define ACLK_QE_MSCL_1 13
-#define ACLK_QE_JPEG 14
-#define ACLK_QE_G2D 15
-#define ACLK_PPMU_MSCL_0 16
-#define ACLK_PPMU_MSCL_1 17
-#define ACLK_MSCLNP_133 18
-#define ACLK_AHB2APB_MSCL0P 19
-#define ACLK_AHB2APB_MSCL1P 20
-
-#define PCLK_MSCL_0 21
-#define PCLK_MSCL_1 22
-#define PCLK_JPEG 23
-#define PCLK_G2D 24
-#define PCLK_QE_MSCL_0 25
-#define PCLK_QE_MSCL_1 26
-#define PCLK_QE_JPEG 27
-#define PCLK_QE_G2D 28
-#define PCLK_PPMU_MSCL_0 29
-#define PCLK_PPMU_MSCL_1 30
-#define PCLK_AXI2ACEL_BRIDGE 31
-#define PCLK_PMU_MSCL 32
-#define MSCL_NR_CLK 33
-
-/* AUD */
-#define SCLK_I2S 1
-#define SCLK_PCM 2
-#define PCLK_I2S 3
-#define PCLK_PCM 4
-#define ACLK_ADMA 5
-#define AUD_NR_CLK 6
-#endif /* _DT_BINDINGS_CLOCK_EXYNOS7_H */
diff --git a/include/dt-bindings/clock/g12a-aoclkc.h b/include/dt-bindings/clock/g12a-aoclkc.h
deleted file mode 100644
index e916e49..0000000
--- a/include/dt-bindings/clock/g12a-aoclkc.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
-/*
- * Copyright (c) 2016 BayLibre, SAS
- * Author: Neil Armstrong <narmstrong@baylibre.com>
- *
- * Copyright (c) 2018 Amlogic, inc.
- * Author: Qiufang Dai <qiufang.dai@amlogic.com>
- */
-
-#ifndef DT_BINDINGS_CLOCK_AMLOGIC_MESON_G12A_AOCLK
-#define DT_BINDINGS_CLOCK_AMLOGIC_MESON_G12A_AOCLK
-
-#define CLKID_AO_AHB 0
-#define CLKID_AO_IR_IN 1
-#define CLKID_AO_I2C_M0 2
-#define CLKID_AO_I2C_S0 3
-#define CLKID_AO_UART 4
-#define CLKID_AO_PROD_I2C 5
-#define CLKID_AO_UART2 6
-#define CLKID_AO_IR_OUT 7
-#define CLKID_AO_SAR_ADC 8
-#define CLKID_AO_MAILBOX 9
-#define CLKID_AO_M3 10
-#define CLKID_AO_AHB_SRAM 11
-#define CLKID_AO_RTI 12
-#define CLKID_AO_M4_FCLK 13
-#define CLKID_AO_M4_HCLK 14
-#define CLKID_AO_CLK81 15
-#define CLKID_AO_SAR_ADC_SEL 16
-#define CLKID_AO_SAR_ADC_CLK 18
-#define CLKID_AO_CTS_OSCIN 19
-#define CLKID_AO_32K 23
-#define CLKID_AO_CEC 27
-#define CLKID_AO_CTS_RTC_OSCIN 28
-
-#endif
diff --git a/include/dt-bindings/clock/g12a-clkc.h b/include/dt-bindings/clock/g12a-clkc.h
deleted file mode 100644
index 0837c1a..0000000
--- a/include/dt-bindings/clock/g12a-clkc.h
+++ /dev/null
@@ -1,147 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ OR MIT */
-/*
- * Meson-G12A clock tree IDs
- *
- * Copyright (c) 2018 Amlogic, Inc. All rights reserved.
- */
-
-#ifndef __G12A_CLKC_H
-#define __G12A_CLKC_H
-
-#define CLKID_SYS_PLL 0
-#define CLKID_FIXED_PLL 1
-#define CLKID_FCLK_DIV2 2
-#define CLKID_FCLK_DIV3 3
-#define CLKID_FCLK_DIV4 4
-#define CLKID_FCLK_DIV5 5
-#define CLKID_FCLK_DIV7 6
-#define CLKID_GP0_PLL 7
-#define CLKID_CLK81 10
-#define CLKID_MPLL0 11
-#define CLKID_MPLL1 12
-#define CLKID_MPLL2 13
-#define CLKID_MPLL3 14
-#define CLKID_DDR 15
-#define CLKID_DOS 16
-#define CLKID_AUDIO_LOCKER 17
-#define CLKID_MIPI_DSI_HOST 18
-#define CLKID_ETH_PHY 19
-#define CLKID_ISA 20
-#define CLKID_PL301 21
-#define CLKID_PERIPHS 22
-#define CLKID_SPICC0 23
-#define CLKID_I2C 24
-#define CLKID_SANA 25
-#define CLKID_SD 26
-#define CLKID_RNG0 27
-#define CLKID_UART0 28
-#define CLKID_SPICC1 29
-#define CLKID_HIU_IFACE 30
-#define CLKID_MIPI_DSI_PHY 31
-#define CLKID_ASSIST_MISC 32
-#define CLKID_SD_EMMC_A 33
-#define CLKID_SD_EMMC_B 34
-#define CLKID_SD_EMMC_C 35
-#define CLKID_AUDIO_CODEC 36
-#define CLKID_AUDIO 37
-#define CLKID_ETH 38
-#define CLKID_DEMUX 39
-#define CLKID_AUDIO_IFIFO 40
-#define CLKID_ADC 41
-#define CLKID_UART1 42
-#define CLKID_G2D 43
-#define CLKID_RESET 44
-#define CLKID_PCIE_COMB 45
-#define CLKID_PARSER 46
-#define CLKID_USB 47
-#define CLKID_PCIE_PHY 48
-#define CLKID_AHB_ARB0 49
-#define CLKID_AHB_DATA_BUS 50
-#define CLKID_AHB_CTRL_BUS 51
-#define CLKID_HTX_HDCP22 52
-#define CLKID_HTX_PCLK 53
-#define CLKID_BT656 54
-#define CLKID_USB1_DDR_BRIDGE 55
-#define CLKID_MMC_PCLK 56
-#define CLKID_UART2 57
-#define CLKID_VPU_INTR 58
-#define CLKID_GIC 59
-#define CLKID_SD_EMMC_A_CLK0 60
-#define CLKID_SD_EMMC_B_CLK0 61
-#define CLKID_SD_EMMC_C_CLK0 62
-#define CLKID_HIFI_PLL 74
-#define CLKID_VCLK2_VENCI0 80
-#define CLKID_VCLK2_VENCI1 81
-#define CLKID_VCLK2_VENCP0 82
-#define CLKID_VCLK2_VENCP1 83
-#define CLKID_VCLK2_VENCT0 84
-#define CLKID_VCLK2_VENCT1 85
-#define CLKID_VCLK2_OTHER 86
-#define CLKID_VCLK2_ENCI 87
-#define CLKID_VCLK2_ENCP 88
-#define CLKID_DAC_CLK 89
-#define CLKID_AOCLK 90
-#define CLKID_IEC958 91
-#define CLKID_ENC480P 92
-#define CLKID_RNG1 93
-#define CLKID_VCLK2_ENCT 94
-#define CLKID_VCLK2_ENCL 95
-#define CLKID_VCLK2_VENCLMMC 96
-#define CLKID_VCLK2_VENCL 97
-#define CLKID_VCLK2_OTHER1 98
-#define CLKID_FCLK_DIV2P5 99
-#define CLKID_DMA 105
-#define CLKID_EFUSE 106
-#define CLKID_ROM_BOOT 107
-#define CLKID_RESET_SEC 108
-#define CLKID_SEC_AHB_APB3 109
-#define CLKID_VPU_0_SEL 110
-#define CLKID_VPU_0 112
-#define CLKID_VPU_1_SEL 113
-#define CLKID_VPU_1 115
-#define CLKID_VPU 116
-#define CLKID_VAPB_0_SEL 117
-#define CLKID_VAPB_0 119
-#define CLKID_VAPB_1_SEL 120
-#define CLKID_VAPB_1 122
-#define CLKID_VAPB_SEL 123
-#define CLKID_VAPB 124
-#define CLKID_HDMI_PLL 128
-#define CLKID_VID_PLL 129
-#define CLKID_VCLK 138
-#define CLKID_VCLK2 139
-#define CLKID_VCLK_DIV1 148
-#define CLKID_VCLK_DIV2 149
-#define CLKID_VCLK_DIV4 150
-#define CLKID_VCLK_DIV6 151
-#define CLKID_VCLK_DIV12 152
-#define CLKID_VCLK2_DIV1 153
-#define CLKID_VCLK2_DIV2 154
-#define CLKID_VCLK2_DIV4 155
-#define CLKID_VCLK2_DIV6 156
-#define CLKID_VCLK2_DIV12 157
-#define CLKID_CTS_ENCI 162
-#define CLKID_CTS_ENCP 163
-#define CLKID_CTS_VDAC 164
-#define CLKID_HDMI_TX 165
-#define CLKID_HDMI 168
-#define CLKID_MALI_0_SEL 169
-#define CLKID_MALI_0 171
-#define CLKID_MALI_1_SEL 172
-#define CLKID_MALI_1 174
-#define CLKID_MALI 175
-#define CLKID_MPLL_50M 177
-#define CLKID_CPU_CLK 187
-#define CLKID_PCIE_PLL 201
-#define CLKID_VDEC_1 204
-#define CLKID_VDEC_HEVC 207
-#define CLKID_VDEC_HEVCF 210
-#define CLKID_TS 212
-#define CLKID_CPUB_CLK 224
-#define CLKID_GP1_PLL 243
-#define CLKID_DSU_CLK 252
-#define CLKID_CPU1_CLK 253
-#define CLKID_CPU2_CLK 254
-#define CLKID_CPU3_CLK 255
-
-#endif /* __G12A_CLKC_H */
diff --git a/include/dt-bindings/clock/gxbb-aoclkc.h b/include/dt-bindings/clock/gxbb-aoclkc.h
deleted file mode 100644
index 9d15e22..0000000
--- a/include/dt-bindings/clock/gxbb-aoclkc.h
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- * This file is provided under a dual BSD/GPLv2 license. When using or
- * redistributing this file, you may do so under either license.
- *
- * GPL LICENSE SUMMARY
- *
- * Copyright (c) 2016 BayLibre, SAS.
- * Author: Neil Armstrong <narmstrong@baylibre.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of version 2 of the GNU General Public License as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- * General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, see <http://www.gnu.org/licenses/>.
- * The full GNU General Public License is included in this distribution
- * in the file called COPYING.
- *
- * BSD LICENSE
- *
- * Copyright (c) 2016 BayLibre, SAS.
- * Author: Neil Armstrong <narmstrong@baylibre.com>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * * Neither the name of Intel Corporation nor the names of its
- * contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef DT_BINDINGS_CLOCK_AMLOGIC_MESON_GXBB_AOCLK
-#define DT_BINDINGS_CLOCK_AMLOGIC_MESON_GXBB_AOCLK
-
-#define CLKID_AO_REMOTE 0
-#define CLKID_AO_I2C_MASTER 1
-#define CLKID_AO_I2C_SLAVE 2
-#define CLKID_AO_UART1 3
-#define CLKID_AO_UART2 4
-#define CLKID_AO_IR_BLASTER 5
-#define CLKID_AO_CEC_32K 6
-
-#endif
diff --git a/include/dt-bindings/clock/gxbb-clkc.h b/include/dt-bindings/clock/gxbb-clkc.h
deleted file mode 100644
index 8ba99a5..0000000
--- a/include/dt-bindings/clock/gxbb-clkc.h
+++ /dev/null
@@ -1,129 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * GXBB clock tree IDs
- */
-
-#ifndef __GXBB_CLKC_H
-#define __GXBB_CLKC_H
-
-#define CLKID_SYS_PLL 0
-#define CLKID_HDMI_PLL 2
-#define CLKID_FIXED_PLL 3
-#define CLKID_FCLK_DIV2 4
-#define CLKID_FCLK_DIV3 5
-#define CLKID_FCLK_DIV4 6
-#define CLKID_FCLK_DIV5 7
-#define CLKID_FCLK_DIV7 8
-#define CLKID_GP0_PLL 9
-#define CLKID_CLK81 12
-#define CLKID_MPLL0 13
-#define CLKID_MPLL1 14
-#define CLKID_MPLL2 15
-#define CLKID_DDR 16
-#define CLKID_DOS 17
-#define CLKID_ISA 18
-#define CLKID_PL301 19
-#define CLKID_PERIPHS 20
-#define CLKID_SPICC 21
-#define CLKID_I2C 22
-#define CLKID_SAR_ADC 23
-#define CLKID_SMART_CARD 24
-#define CLKID_RNG0 25
-#define CLKID_UART0 26
-#define CLKID_SDHC 27
-#define CLKID_STREAM 28
-#define CLKID_ASYNC_FIFO 29
-#define CLKID_SDIO 30
-#define CLKID_ABUF 31
-#define CLKID_HIU_IFACE 32
-#define CLKID_ASSIST_MISC 33
-#define CLKID_SPI 34
-#define CLKID_ETH 36
-#define CLKID_I2S_SPDIF 35
-#define CLKID_DEMUX 37
-#define CLKID_AIU_GLUE 38
-#define CLKID_IEC958 39
-#define CLKID_I2S_OUT 40
-#define CLKID_AMCLK 41
-#define CLKID_AIFIFO2 42
-#define CLKID_MIXER 43
-#define CLKID_MIXER_IFACE 44
-#define CLKID_ADC 45
-#define CLKID_BLKMV 46
-#define CLKID_AIU 47
-#define CLKID_UART1 48
-#define CLKID_G2D 49
-#define CLKID_USB0 50
-#define CLKID_USB1 51
-#define CLKID_RESET 52
-#define CLKID_NAND 53
-#define CLKID_DOS_PARSER 54
-#define CLKID_USB 55
-#define CLKID_VDIN1 56
-#define CLKID_AHB_ARB0 57
-#define CLKID_EFUSE 58
-#define CLKID_BOOT_ROM 59
-#define CLKID_AHB_DATA_BUS 60
-#define CLKID_AHB_CTRL_BUS 61
-#define CLKID_HDMI_INTR_SYNC 62
-#define CLKID_HDMI_PCLK 63
-#define CLKID_USB1_DDR_BRIDGE 64
-#define CLKID_USB0_DDR_BRIDGE 65
-#define CLKID_MMC_PCLK 66
-#define CLKID_DVIN 67
-#define CLKID_UART2 68
-#define CLKID_SANA 69
-#define CLKID_VPU_INTR 70
-#define CLKID_SEC_AHB_AHB3_BRIDGE 71
-#define CLKID_CLK81_A53 72
-#define CLKID_VCLK2_VENCI0 73
-#define CLKID_VCLK2_VENCI1 74
-#define CLKID_VCLK2_VENCP0 75
-#define CLKID_VCLK2_VENCP1 76
-#define CLKID_GCLK_VENCI_INT0 77
-#define CLKID_GCLK_VENCI_INT 78
-#define CLKID_DAC_CLK 79
-#define CLKID_AOCLK_GATE 80
-#define CLKID_IEC958_GATE 81
-#define CLKID_ENC480P 82
-#define CLKID_RNG1 83
-#define CLKID_GCLK_VENCI_INT1 84
-#define CLKID_VCLK2_VENCLMCC 85
-#define CLKID_VCLK2_VENCL 86
-#define CLKID_VCLK_OTHER 87
-#define CLKID_EDP 88
-#define CLKID_AO_MEDIA_CPU 89
-#define CLKID_AO_AHB_SRAM 90
-#define CLKID_AO_AHB_BUS 91
-#define CLKID_AO_IFACE 92
-#define CLKID_AO_I2C 93
-#define CLKID_SD_EMMC_A 94
-#define CLKID_SD_EMMC_B 95
-#define CLKID_SD_EMMC_C 96
-#define CLKID_SAR_ADC_CLK 97
-#define CLKID_SAR_ADC_SEL 98
-#define CLKID_MALI_0_SEL 100
-#define CLKID_MALI_0 102
-#define CLKID_MALI_1_SEL 103
-#define CLKID_MALI_1 105
-#define CLKID_MALI 106
-#define CLKID_CTS_AMCLK 107
-#define CLKID_CTS_MCLK_I958 110
-#define CLKID_CTS_I958 113
-#define CLKID_32K_CLK 114
-#define CLKID_SD_EMMC_A_CLK0 119
-#define CLKID_SD_EMMC_B_CLK0 122
-#define CLKID_SD_EMMC_C_CLK0 125
-#define CLKID_VPU_0_SEL 126
-#define CLKID_VPU_0 128
-#define CLKID_VPU_1_SEL 129
-#define CLKID_VPU_1 131
-#define CLKID_VPU 132
-#define CLKID_VAPB_0_SEL 133
-#define CLKID_VAPB_0 135
-#define CLKID_VAPB_1_SEL 136
-#define CLKID_VAPB_1 138
-#define CLKID_VAPB_SEL 139
-#define CLKID_VAPB 140
-
-#endif /* __GXBB_CLKC_H */
diff --git a/include/dt-bindings/clock/hi3660-clock.h b/include/dt-bindings/clock/hi3660-clock.h
deleted file mode 100644
index e1374e1..0000000
--- a/include/dt-bindings/clock/hi3660-clock.h
+++ /dev/null
@@ -1,214 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/*
- * Copyright (c) 2016-2017 Linaro Ltd.
- * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
- */
-
-#ifndef __DTS_HI3660_CLOCK_H
-#define __DTS_HI3660_CLOCK_H
-
-/* fixed rate clocks */
-#define HI3660_CLKIN_SYS 0
-#define HI3660_CLKIN_REF 1
-#define HI3660_CLK_FLL_SRC 2
-#define HI3660_CLK_PPLL0 3
-#define HI3660_CLK_PPLL1 4
-#define HI3660_CLK_PPLL2 5
-#define HI3660_CLK_PPLL3 6
-#define HI3660_CLK_SCPLL 7
-#define HI3660_PCLK 8
-#define HI3660_CLK_UART0_DBG 9
-#define HI3660_CLK_UART6 10
-#define HI3660_OSC32K 11
-#define HI3660_OSC19M 12
-#define HI3660_CLK_480M 13
-#define HI3660_CLK_INV 14
-
-/* clk in crgctrl */
-#define HI3660_FACTOR_UART3 15
-#define HI3660_CLK_FACTOR_MMC 16
-#define HI3660_CLK_GATE_I2C0 17
-#define HI3660_CLK_GATE_I2C1 18
-#define HI3660_CLK_GATE_I2C2 19
-#define HI3660_CLK_GATE_I2C6 20
-#define HI3660_CLK_DIV_SYSBUS 21
-#define HI3660_CLK_DIV_320M 22
-#define HI3660_CLK_DIV_A53 23
-#define HI3660_CLK_GATE_SPI0 24
-#define HI3660_CLK_GATE_SPI2 25
-#define HI3660_PCIEPHY_REF 26
-#define HI3660_CLK_ABB_USB 27
-#define HI3660_HCLK_GATE_SDIO0 28
-#define HI3660_HCLK_GATE_SD 29
-#define HI3660_CLK_GATE_AOMM 30
-#define HI3660_PCLK_GPIO0 31
-#define HI3660_PCLK_GPIO1 32
-#define HI3660_PCLK_GPIO2 33
-#define HI3660_PCLK_GPIO3 34
-#define HI3660_PCLK_GPIO4 35
-#define HI3660_PCLK_GPIO5 36
-#define HI3660_PCLK_GPIO6 37
-#define HI3660_PCLK_GPIO7 38
-#define HI3660_PCLK_GPIO8 39
-#define HI3660_PCLK_GPIO9 40
-#define HI3660_PCLK_GPIO10 41
-#define HI3660_PCLK_GPIO11 42
-#define HI3660_PCLK_GPIO12 43
-#define HI3660_PCLK_GPIO13 44
-#define HI3660_PCLK_GPIO14 45
-#define HI3660_PCLK_GPIO15 46
-#define HI3660_PCLK_GPIO16 47
-#define HI3660_PCLK_GPIO17 48
-#define HI3660_PCLK_GPIO18 49
-#define HI3660_PCLK_GPIO19 50
-#define HI3660_PCLK_GPIO20 51
-#define HI3660_PCLK_GPIO21 52
-#define HI3660_CLK_GATE_SPI3 53
-#define HI3660_CLK_GATE_I2C7 54
-#define HI3660_CLK_GATE_I2C3 55
-#define HI3660_CLK_GATE_SPI1 56
-#define HI3660_CLK_GATE_UART1 57
-#define HI3660_CLK_GATE_UART2 58
-#define HI3660_CLK_GATE_UART4 59
-#define HI3660_CLK_GATE_UART5 60
-#define HI3660_CLK_GATE_I2C4 61
-#define HI3660_CLK_GATE_DMAC 62
-#define HI3660_PCLK_GATE_DSS 63
-#define HI3660_ACLK_GATE_DSS 64
-#define HI3660_CLK_GATE_LDI1 65
-#define HI3660_CLK_GATE_LDI0 66
-#define HI3660_CLK_GATE_VIVOBUS 67
-#define HI3660_CLK_GATE_EDC0 68
-#define HI3660_CLK_GATE_TXDPHY0_CFG 69
-#define HI3660_CLK_GATE_TXDPHY0_REF 70
-#define HI3660_CLK_GATE_TXDPHY1_CFG 71
-#define HI3660_CLK_GATE_TXDPHY1_REF 72
-#define HI3660_ACLK_GATE_USB3OTG 73
-#define HI3660_CLK_GATE_SPI4 74
-#define HI3660_CLK_GATE_SD 75
-#define HI3660_CLK_GATE_SDIO0 76
-#define HI3660_CLK_GATE_UFS_SUBSYS 77
-#define HI3660_PCLK_GATE_DSI0 78
-#define HI3660_PCLK_GATE_DSI1 79
-#define HI3660_ACLK_GATE_PCIE 80
-#define HI3660_PCLK_GATE_PCIE_SYS 81
-#define HI3660_CLK_GATE_PCIEAUX 82
-#define HI3660_PCLK_GATE_PCIE_PHY 83
-#define HI3660_CLK_ANDGT_LDI0 84
-#define HI3660_CLK_ANDGT_LDI1 85
-#define HI3660_CLK_ANDGT_EDC0 86
-#define HI3660_CLK_GATE_UFSPHY_GT 87
-#define HI3660_CLK_ANDGT_MMC 88
-#define HI3660_CLK_ANDGT_SD 89
-#define HI3660_CLK_A53HPM_ANDGT 90
-#define HI3660_CLK_ANDGT_SDIO 91
-#define HI3660_CLK_ANDGT_UART0 92
-#define HI3660_CLK_ANDGT_UART1 93
-#define HI3660_CLK_ANDGT_UARTH 94
-#define HI3660_CLK_ANDGT_SPI 95
-#define HI3660_CLK_VIVOBUS_ANDGT 96
-#define HI3660_CLK_AOMM_ANDGT 97
-#define HI3660_CLK_320M_PLL_GT 98
-#define HI3660_AUTODIV_EMMC0BUS 99
-#define HI3660_AUTODIV_SYSBUS 100
-#define HI3660_CLK_GATE_UFSPHY_CFG 101
-#define HI3660_CLK_GATE_UFSIO_REF 102
-#define HI3660_CLK_MUX_SYSBUS 103
-#define HI3660_CLK_MUX_UART0 104
-#define HI3660_CLK_MUX_UART1 105
-#define HI3660_CLK_MUX_UARTH 106
-#define HI3660_CLK_MUX_SPI 107
-#define HI3660_CLK_MUX_I2C 108
-#define HI3660_CLK_MUX_MMC_PLL 109
-#define HI3660_CLK_MUX_LDI1 110
-#define HI3660_CLK_MUX_LDI0 111
-#define HI3660_CLK_MUX_SD_PLL 112
-#define HI3660_CLK_MUX_SD_SYS 113
-#define HI3660_CLK_MUX_EDC0 114
-#define HI3660_CLK_MUX_SDIO_SYS 115
-#define HI3660_CLK_MUX_SDIO_PLL 116
-#define HI3660_CLK_MUX_VIVOBUS 117
-#define HI3660_CLK_MUX_A53HPM 118
-#define HI3660_CLK_MUX_320M 119
-#define HI3660_CLK_MUX_IOPERI 120
-#define HI3660_CLK_DIV_UART0 121
-#define HI3660_CLK_DIV_UART1 122
-#define HI3660_CLK_DIV_UARTH 123
-#define HI3660_CLK_DIV_MMC 124
-#define HI3660_CLK_DIV_SD 125
-#define HI3660_CLK_DIV_EDC0 126
-#define HI3660_CLK_DIV_LDI0 127
-#define HI3660_CLK_DIV_SDIO 128
-#define HI3660_CLK_DIV_LDI1 129
-#define HI3660_CLK_DIV_SPI 130
-#define HI3660_CLK_DIV_VIVOBUS 131
-#define HI3660_CLK_DIV_I2C 132
-#define HI3660_CLK_DIV_UFSPHY 133
-#define HI3660_CLK_DIV_CFGBUS 134
-#define HI3660_CLK_DIV_MMC0BUS 135
-#define HI3660_CLK_DIV_MMC1BUS 136
-#define HI3660_CLK_DIV_UFSPERI 137
-#define HI3660_CLK_DIV_AOMM 138
-#define HI3660_CLK_DIV_IOPERI 139
-#define HI3660_VENC_VOLT_HOLD 140
-#define HI3660_PERI_VOLT_HOLD 141
-#define HI3660_CLK_GATE_VENC 142
-#define HI3660_CLK_GATE_VDEC 143
-#define HI3660_CLK_ANDGT_VENC 144
-#define HI3660_CLK_ANDGT_VDEC 145
-#define HI3660_CLK_MUX_VENC 146
-#define HI3660_CLK_MUX_VDEC 147
-#define HI3660_CLK_DIV_VENC 148
-#define HI3660_CLK_DIV_VDEC 149
-#define HI3660_CLK_FAC_ISP_SNCLK 150
-#define HI3660_CLK_GATE_ISP_SNCLK0 151
-#define HI3660_CLK_GATE_ISP_SNCLK1 152
-#define HI3660_CLK_GATE_ISP_SNCLK2 153
-#define HI3660_CLK_ANGT_ISP_SNCLK 154
-#define HI3660_CLK_MUX_ISP_SNCLK 155
-#define HI3660_CLK_DIV_ISP_SNCLK 156
-
-/* clk in pmuctrl */
-#define HI3660_GATE_ABB_192 0
-
-/* clk in pctrl */
-#define HI3660_GATE_UFS_TCXO_EN 0
-#define HI3660_GATE_USB_TCXO_EN 1
-
-/* clk in sctrl */
-#define HI3660_PCLK_AO_GPIO0 0
-#define HI3660_PCLK_AO_GPIO1 1
-#define HI3660_PCLK_AO_GPIO2 2
-#define HI3660_PCLK_AO_GPIO3 3
-#define HI3660_PCLK_AO_GPIO4 4
-#define HI3660_PCLK_AO_GPIO5 5
-#define HI3660_PCLK_AO_GPIO6 6
-#define HI3660_PCLK_GATE_MMBUF 7
-#define HI3660_CLK_GATE_DSS_AXI_MM 8
-#define HI3660_PCLK_MMBUF_ANDGT 9
-#define HI3660_CLK_MMBUF_PLL_ANDGT 10
-#define HI3660_CLK_FLL_MMBUF_ANDGT 11
-#define HI3660_CLK_SYS_MMBUF_ANDGT 12
-#define HI3660_CLK_GATE_PCIEPHY_GT 13
-#define HI3660_ACLK_MUX_MMBUF 14
-#define HI3660_CLK_SW_MMBUF 15
-#define HI3660_CLK_DIV_AOBUS 16
-#define HI3660_PCLK_DIV_MMBUF 17
-#define HI3660_ACLK_DIV_MMBUF 18
-#define HI3660_CLK_DIV_PCIEPHY 19
-
-/* clk in iomcu */
-#define HI3660_CLK_I2C0_IOMCU 0
-#define HI3660_CLK_I2C1_IOMCU 1
-#define HI3660_CLK_I2C2_IOMCU 2
-#define HI3660_CLK_I2C6_IOMCU 3
-#define HI3660_CLK_IOMCU_PERI0 4
-
-/* clk in stub clock */
-#define HI3660_CLK_STUB_CLUSTER0 0
-#define HI3660_CLK_STUB_CLUSTER1 1
-#define HI3660_CLK_STUB_GPU 2
-#define HI3660_CLK_STUB_DDR 3
-#define HI3660_CLK_STUB_NUM 4
-
-#endif /* __DTS_HI3660_CLOCK_H */
diff --git a/include/dt-bindings/clock/hi6220-clock.h b/include/dt-bindings/clock/hi6220-clock.h
deleted file mode 100644
index 70ee383..0000000
--- a/include/dt-bindings/clock/hi6220-clock.h
+++ /dev/null
@@ -1,173 +0,0 @@
-/*
- * Copyright (c) 2015 Hisilicon Limited.
- *
- * Author: Bintian Wang <bintian.wang@huawei.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __DT_BINDINGS_CLOCK_HI6220_H
-#define __DT_BINDINGS_CLOCK_HI6220_H
-
-/* clk in Hi6220 AO (always on) controller */
-#define HI6220_NONE_CLOCK 0
-
-/* fixed rate clocks */
-#define HI6220_REF32K 1
-#define HI6220_CLK_TCXO 2
-#define HI6220_MMC1_PAD 3
-#define HI6220_MMC2_PAD 4
-#define HI6220_MMC0_PAD 5
-#define HI6220_PLL_BBP 6
-#define HI6220_PLL_GPU 7
-#define HI6220_PLL1_DDR 8
-#define HI6220_PLL_SYS 9
-#define HI6220_PLL_SYS_MEDIA 10
-#define HI6220_DDR_SRC 11
-#define HI6220_PLL_MEDIA 12
-#define HI6220_PLL_DDR 13
-
-/* fixed factor clocks */
-#define HI6220_300M 14
-#define HI6220_150M 15
-#define HI6220_PICOPHY_SRC 16
-#define HI6220_MMC0_SRC_SEL 17
-#define HI6220_MMC1_SRC_SEL 18
-#define HI6220_MMC2_SRC_SEL 19
-#define HI6220_VPU_CODEC 20
-#define HI6220_MMC0_SMP 21
-#define HI6220_MMC1_SMP 22
-#define HI6220_MMC2_SMP 23
-
-/* gate clocks */
-#define HI6220_WDT0_PCLK 24
-#define HI6220_WDT1_PCLK 25
-#define HI6220_WDT2_PCLK 26
-#define HI6220_TIMER0_PCLK 27
-#define HI6220_TIMER1_PCLK 28
-#define HI6220_TIMER2_PCLK 29
-#define HI6220_TIMER3_PCLK 30
-#define HI6220_TIMER4_PCLK 31
-#define HI6220_TIMER5_PCLK 32
-#define HI6220_TIMER6_PCLK 33
-#define HI6220_TIMER7_PCLK 34
-#define HI6220_TIMER8_PCLK 35
-#define HI6220_UART0_PCLK 36
-
-#define HI6220_AO_NR_CLKS 37
-
-/* clk in Hi6220 systrl */
-/* gate clock */
-#define HI6220_MMC0_CLK 1
-#define HI6220_MMC0_CIUCLK 2
-#define HI6220_MMC1_CLK 3
-#define HI6220_MMC1_CIUCLK 4
-#define HI6220_MMC2_CLK 5
-#define HI6220_MMC2_CIUCLK 6
-#define HI6220_USBOTG_HCLK 7
-#define HI6220_CLK_PICOPHY 8
-#define HI6220_HIFI 9
-#define HI6220_DACODEC_PCLK 10
-#define HI6220_EDMAC_ACLK 11
-#define HI6220_CS_ATB 12
-#define HI6220_I2C0_CLK 13
-#define HI6220_I2C1_CLK 14
-#define HI6220_I2C2_CLK 15
-#define HI6220_I2C3_CLK 16
-#define HI6220_UART1_PCLK 17
-#define HI6220_UART2_PCLK 18
-#define HI6220_UART3_PCLK 19
-#define HI6220_UART4_PCLK 20
-#define HI6220_SPI_CLK 21
-#define HI6220_TSENSOR_CLK 22
-#define HI6220_MMU_CLK 23
-#define HI6220_HIFI_SEL 24
-#define HI6220_MMC0_SYSPLL 25
-#define HI6220_MMC1_SYSPLL 26
-#define HI6220_MMC2_SYSPLL 27
-#define HI6220_MMC0_SEL 28
-#define HI6220_MMC1_SEL 29
-#define HI6220_BBPPLL_SEL 30
-#define HI6220_MEDIA_PLL_SRC 31
-#define HI6220_MMC2_SEL 32
-#define HI6220_CS_ATB_SYSPLL 33
-
-/* mux clocks */
-#define HI6220_MMC0_SRC 34
-#define HI6220_MMC0_SMP_IN 35
-#define HI6220_MMC1_SRC 36
-#define HI6220_MMC1_SMP_IN 37
-#define HI6220_MMC2_SRC 38
-#define HI6220_MMC2_SMP_IN 39
-#define HI6220_HIFI_SRC 40
-#define HI6220_UART1_SRC 41
-#define HI6220_UART2_SRC 42
-#define HI6220_UART3_SRC 43
-#define HI6220_UART4_SRC 44
-#define HI6220_MMC0_MUX0 45
-#define HI6220_MMC1_MUX0 46
-#define HI6220_MMC2_MUX0 47
-#define HI6220_MMC0_MUX1 48
-#define HI6220_MMC1_MUX1 49
-#define HI6220_MMC2_MUX1 50
-
-/* divider clocks */
-#define HI6220_CLK_BUS 51
-#define HI6220_MMC0_DIV 52
-#define HI6220_MMC1_DIV 53
-#define HI6220_MMC2_DIV 54
-#define HI6220_HIFI_DIV 55
-#define HI6220_BBPPLL0_DIV 56
-#define HI6220_CS_DAPB 57
-#define HI6220_CS_ATB_DIV 58
-
-#define HI6220_SYS_NR_CLKS 59
-
-/* clk in Hi6220 media controller */
-/* gate clocks */
-#define HI6220_DSI_PCLK 1
-#define HI6220_G3D_PCLK 2
-#define HI6220_ACLK_CODEC_VPU 3
-#define HI6220_ISP_SCLK 4
-#define HI6220_ADE_CORE 5
-#define HI6220_MED_MMU 6
-#define HI6220_CFG_CSI4PHY 7
-#define HI6220_CFG_CSI2PHY 8
-#define HI6220_ISP_SCLK_GATE 9
-#define HI6220_ISP_SCLK_GATE1 10
-#define HI6220_ADE_CORE_GATE 11
-#define HI6220_CODEC_VPU_GATE 12
-#define HI6220_MED_SYSPLL 13
-
-/* mux clocks */
-#define HI6220_1440_1200 14
-#define HI6220_1000_1200 15
-#define HI6220_1000_1440 16
-
-/* divider clocks */
-#define HI6220_CODEC_JPEG 17
-#define HI6220_ISP_SCLK_SRC 18
-#define HI6220_ISP_SCLK1 19
-#define HI6220_ADE_CORE_SRC 20
-#define HI6220_ADE_PIX_SRC 21
-#define HI6220_G3D_CLK 22
-#define HI6220_CODEC_VPU_SRC 23
-
-#define HI6220_MEDIA_NR_CLKS 24
-
-/* clk in Hi6220 power controller */
-/* gate clocks */
-#define HI6220_PLL_GPU_GATE 1
-#define HI6220_PLL1_DDR_GATE 2
-#define HI6220_PLL_DDR_GATE 3
-#define HI6220_PLL_MEDIA_GATE 4
-#define HI6220_PLL0_BBP_GATE 5
-
-/* divider clocks */
-#define HI6220_DDRC_SRC 6
-#define HI6220_DDRC_AXI1 7
-
-#define HI6220_POWER_NR_CLKS 8
-#endif
diff --git a/include/dt-bindings/clock/histb-clock.h b/include/dt-bindings/clock/histb-clock.h
deleted file mode 100644
index 136de24..0000000
--- a/include/dt-bindings/clock/histb-clock.h
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- * Copyright (c) 2016 HiSilicon Technologies Co., Ltd.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef __DTS_HISTB_CLOCK_H
-#define __DTS_HISTB_CLOCK_H
-
-/* clocks provided by core CRG */
-#define HISTB_OSC_CLK 0
-#define HISTB_APB_CLK 1
-#define HISTB_AHB_CLK 2
-#define HISTB_UART1_CLK 3
-#define HISTB_UART2_CLK 4
-#define HISTB_UART3_CLK 5
-#define HISTB_I2C0_CLK 6
-#define HISTB_I2C1_CLK 7
-#define HISTB_I2C2_CLK 8
-#define HISTB_I2C3_CLK 9
-#define HISTB_I2C4_CLK 10
-#define HISTB_I2C5_CLK 11
-#define HISTB_SPI0_CLK 12
-#define HISTB_SPI1_CLK 13
-#define HISTB_SPI2_CLK 14
-#define HISTB_SCI_CLK 15
-#define HISTB_FMC_CLK 16
-#define HISTB_MMC_BIU_CLK 17
-#define HISTB_MMC_CIU_CLK 18
-#define HISTB_MMC_DRV_CLK 19
-#define HISTB_MMC_SAMPLE_CLK 20
-#define HISTB_SDIO0_BIU_CLK 21
-#define HISTB_SDIO0_CIU_CLK 22
-#define HISTB_SDIO0_DRV_CLK 23
-#define HISTB_SDIO0_SAMPLE_CLK 24
-#define HISTB_PCIE_AUX_CLK 25
-#define HISTB_PCIE_PIPE_CLK 26
-#define HISTB_PCIE_SYS_CLK 27
-#define HISTB_PCIE_BUS_CLK 28
-#define HISTB_ETH0_MAC_CLK 29
-#define HISTB_ETH0_MACIF_CLK 30
-#define HISTB_ETH1_MAC_CLK 31
-#define HISTB_ETH1_MACIF_CLK 32
-#define HISTB_COMBPHY1_CLK 33
-#define HISTB_USB2_BUS_CLK 34
-#define HISTB_USB2_PHY_CLK 35
-#define HISTB_USB2_UTMI_CLK 36
-#define HISTB_USB2_12M_CLK 37
-#define HISTB_USB2_48M_CLK 38
-#define HISTB_USB2_OTG_UTMI_CLK 39
-#define HISTB_USB2_PHY1_REF_CLK 40
-#define HISTB_USB2_PHY2_REF_CLK 41
-#define HISTB_COMBPHY0_CLK 42
-#define HISTB_USB3_BUS_CLK 43
-#define HISTB_USB3_UTMI_CLK 44
-#define HISTB_USB3_PIPE_CLK 45
-#define HISTB_USB3_SUSPEND_CLK 46
-#define HISTB_USB3_BUS_CLK1 47
-#define HISTB_USB3_UTMI_CLK1 48
-#define HISTB_USB3_PIPE_CLK1 49
-#define HISTB_USB3_SUSPEND_CLK1 50
-
-/* clocks provided by mcu CRG */
-#define HISTB_MCE_CLK 1
-#define HISTB_IR_CLK 2
-#define HISTB_TIMER01_CLK 3
-#define HISTB_LEDC_CLK 4
-#define HISTB_UART0_CLK 5
-#define HISTB_LSADC_CLK 6
-
-#endif /* __DTS_HISTB_CLOCK_H */
diff --git a/include/dt-bindings/clock/imx5-clock.h b/include/dt-bindings/clock/imx5-clock.h
deleted file mode 100644
index d382fc7..0000000
--- a/include/dt-bindings/clock/imx5-clock.h
+++ /dev/null
@@ -1,219 +0,0 @@
-/*
- * Copyright 2013 Lucas Stach, Pengutronix <l.stach@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-#ifndef __DT_BINDINGS_CLOCK_IMX5_H
-#define __DT_BINDINGS_CLOCK_IMX5_H
-
-#define IMX5_CLK_DUMMY 0
-#define IMX5_CLK_CKIL 1
-#define IMX5_CLK_OSC 2
-#define IMX5_CLK_CKIH1 3
-#define IMX5_CLK_CKIH2 4
-#define IMX5_CLK_AHB 5
-#define IMX5_CLK_IPG 6
-#define IMX5_CLK_AXI_A 7
-#define IMX5_CLK_AXI_B 8
-#define IMX5_CLK_UART_PRED 9
-#define IMX5_CLK_UART_ROOT 10
-#define IMX5_CLK_ESDHC_A_PRED 11
-#define IMX5_CLK_ESDHC_B_PRED 12
-#define IMX5_CLK_ESDHC_C_SEL 13
-#define IMX5_CLK_ESDHC_D_SEL 14
-#define IMX5_CLK_EMI_SEL 15
-#define IMX5_CLK_EMI_SLOW_PODF 16
-#define IMX5_CLK_NFC_PODF 17
-#define IMX5_CLK_ECSPI_PRED 18
-#define IMX5_CLK_ECSPI_PODF 19
-#define IMX5_CLK_USBOH3_PRED 20
-#define IMX5_CLK_USBOH3_PODF 21
-#define IMX5_CLK_USB_PHY_PRED 22
-#define IMX5_CLK_USB_PHY_PODF 23
-#define IMX5_CLK_CPU_PODF 24
-#define IMX5_CLK_DI_PRED 25
-#define IMX5_CLK_TVE_SEL 27
-#define IMX5_CLK_UART1_IPG_GATE 28
-#define IMX5_CLK_UART1_PER_GATE 29
-#define IMX5_CLK_UART2_IPG_GATE 30
-#define IMX5_CLK_UART2_PER_GATE 31
-#define IMX5_CLK_UART3_IPG_GATE 32
-#define IMX5_CLK_UART3_PER_GATE 33
-#define IMX5_CLK_I2C1_GATE 34
-#define IMX5_CLK_I2C2_GATE 35
-#define IMX5_CLK_GPT_IPG_GATE 36
-#define IMX5_CLK_PWM1_IPG_GATE 37
-#define IMX5_CLK_PWM1_HF_GATE 38
-#define IMX5_CLK_PWM2_IPG_GATE 39
-#define IMX5_CLK_PWM2_HF_GATE 40
-#define IMX5_CLK_GPT_HF_GATE 41
-#define IMX5_CLK_FEC_GATE 42
-#define IMX5_CLK_USBOH3_PER_GATE 43
-#define IMX5_CLK_ESDHC1_IPG_GATE 44
-#define IMX5_CLK_ESDHC2_IPG_GATE 45
-#define IMX5_CLK_ESDHC3_IPG_GATE 46
-#define IMX5_CLK_ESDHC4_IPG_GATE 47
-#define IMX5_CLK_SSI1_IPG_GATE 48
-#define IMX5_CLK_SSI2_IPG_GATE 49
-#define IMX5_CLK_SSI3_IPG_GATE 50
-#define IMX5_CLK_ECSPI1_IPG_GATE 51
-#define IMX5_CLK_ECSPI1_PER_GATE 52
-#define IMX5_CLK_ECSPI2_IPG_GATE 53
-#define IMX5_CLK_ECSPI2_PER_GATE 54
-#define IMX5_CLK_CSPI_IPG_GATE 55
-#define IMX5_CLK_SDMA_GATE 56
-#define IMX5_CLK_EMI_SLOW_GATE 57
-#define IMX5_CLK_IPU_SEL 58
-#define IMX5_CLK_IPU_GATE 59
-#define IMX5_CLK_NFC_GATE 60
-#define IMX5_CLK_IPU_DI1_GATE 61
-#define IMX5_CLK_VPU_SEL 62
-#define IMX5_CLK_VPU_GATE 63
-#define IMX5_CLK_VPU_REFERENCE_GATE 64
-#define IMX5_CLK_UART4_IPG_GATE 65
-#define IMX5_CLK_UART4_PER_GATE 66
-#define IMX5_CLK_UART5_IPG_GATE 67
-#define IMX5_CLK_UART5_PER_GATE 68
-#define IMX5_CLK_TVE_GATE 69
-#define IMX5_CLK_TVE_PRED 70
-#define IMX5_CLK_ESDHC1_PER_GATE 71
-#define IMX5_CLK_ESDHC2_PER_GATE 72
-#define IMX5_CLK_ESDHC3_PER_GATE 73
-#define IMX5_CLK_ESDHC4_PER_GATE 74
-#define IMX5_CLK_USB_PHY_GATE 75
-#define IMX5_CLK_HSI2C_GATE 76
-#define IMX5_CLK_MIPI_HSC1_GATE 77
-#define IMX5_CLK_MIPI_HSC2_GATE 78
-#define IMX5_CLK_MIPI_ESC_GATE 79
-#define IMX5_CLK_MIPI_HSP_GATE 80
-#define IMX5_CLK_LDB_DI1_DIV_3_5 81
-#define IMX5_CLK_LDB_DI1_DIV 82
-#define IMX5_CLK_LDB_DI0_DIV_3_5 83
-#define IMX5_CLK_LDB_DI0_DIV 84
-#define IMX5_CLK_LDB_DI1_GATE 85
-#define IMX5_CLK_CAN2_SERIAL_GATE 86
-#define IMX5_CLK_CAN2_IPG_GATE 87
-#define IMX5_CLK_I2C3_GATE 88
-#define IMX5_CLK_LP_APM 89
-#define IMX5_CLK_PERIPH_APM 90
-#define IMX5_CLK_MAIN_BUS 91
-#define IMX5_CLK_AHB_MAX 92
-#define IMX5_CLK_AIPS_TZ1 93
-#define IMX5_CLK_AIPS_TZ2 94
-#define IMX5_CLK_TMAX1 95
-#define IMX5_CLK_TMAX2 96
-#define IMX5_CLK_TMAX3 97
-#define IMX5_CLK_SPBA 98
-#define IMX5_CLK_UART_SEL 99
-#define IMX5_CLK_ESDHC_A_SEL 100
-#define IMX5_CLK_ESDHC_B_SEL 101
-#define IMX5_CLK_ESDHC_A_PODF 102
-#define IMX5_CLK_ESDHC_B_PODF 103
-#define IMX5_CLK_ECSPI_SEL 104
-#define IMX5_CLK_USBOH3_SEL 105
-#define IMX5_CLK_USB_PHY_SEL 106
-#define IMX5_CLK_IIM_GATE 107
-#define IMX5_CLK_USBOH3_GATE 108
-#define IMX5_CLK_EMI_FAST_GATE 109
-#define IMX5_CLK_IPU_DI0_GATE 110
-#define IMX5_CLK_GPC_DVFS 111
-#define IMX5_CLK_PLL1_SW 112
-#define IMX5_CLK_PLL2_SW 113
-#define IMX5_CLK_PLL3_SW 114
-#define IMX5_CLK_IPU_DI0_SEL 115
-#define IMX5_CLK_IPU_DI1_SEL 116
-#define IMX5_CLK_TVE_EXT_SEL 117
-#define IMX5_CLK_MX51_MIPI 118
-#define IMX5_CLK_PLL4_SW 119
-#define IMX5_CLK_LDB_DI1_SEL 120
-#define IMX5_CLK_DI_PLL4_PODF 121
-#define IMX5_CLK_LDB_DI0_SEL 122
-#define IMX5_CLK_LDB_DI0_GATE 123
-#define IMX5_CLK_USB_PHY1_GATE 124
-#define IMX5_CLK_USB_PHY2_GATE 125
-#define IMX5_CLK_PER_LP_APM 126
-#define IMX5_CLK_PER_PRED1 127
-#define IMX5_CLK_PER_PRED2 128
-#define IMX5_CLK_PER_PODF 129
-#define IMX5_CLK_PER_ROOT 130
-#define IMX5_CLK_SSI_APM 131
-#define IMX5_CLK_SSI1_ROOT_SEL 132
-#define IMX5_CLK_SSI2_ROOT_SEL 133
-#define IMX5_CLK_SSI3_ROOT_SEL 134
-#define IMX5_CLK_SSI_EXT1_SEL 135
-#define IMX5_CLK_SSI_EXT2_SEL 136
-#define IMX5_CLK_SSI_EXT1_COM_SEL 137
-#define IMX5_CLK_SSI_EXT2_COM_SEL 138
-#define IMX5_CLK_SSI1_ROOT_PRED 139
-#define IMX5_CLK_SSI1_ROOT_PODF 140
-#define IMX5_CLK_SSI2_ROOT_PRED 141
-#define IMX5_CLK_SSI2_ROOT_PODF 142
-#define IMX5_CLK_SSI_EXT1_PRED 143
-#define IMX5_CLK_SSI_EXT1_PODF 144
-#define IMX5_CLK_SSI_EXT2_PRED 145
-#define IMX5_CLK_SSI_EXT2_PODF 146
-#define IMX5_CLK_SSI1_ROOT_GATE 147
-#define IMX5_CLK_SSI2_ROOT_GATE 148
-#define IMX5_CLK_SSI3_ROOT_GATE 149
-#define IMX5_CLK_SSI_EXT1_GATE 150
-#define IMX5_CLK_SSI_EXT2_GATE 151
-#define IMX5_CLK_EPIT1_IPG_GATE 152
-#define IMX5_CLK_EPIT1_HF_GATE 153
-#define IMX5_CLK_EPIT2_IPG_GATE 154
-#define IMX5_CLK_EPIT2_HF_GATE 155
-#define IMX5_CLK_CAN_SEL 156
-#define IMX5_CLK_CAN1_SERIAL_GATE 157
-#define IMX5_CLK_CAN1_IPG_GATE 158
-#define IMX5_CLK_OWIRE_GATE 159
-#define IMX5_CLK_GPU3D_SEL 160
-#define IMX5_CLK_GPU2D_SEL 161
-#define IMX5_CLK_GPU3D_GATE 162
-#define IMX5_CLK_GPU2D_GATE 163
-#define IMX5_CLK_GARB_GATE 164
-#define IMX5_CLK_CKO1_SEL 165
-#define IMX5_CLK_CKO1_PODF 166
-#define IMX5_CLK_CKO1 167
-#define IMX5_CLK_CKO2_SEL 168
-#define IMX5_CLK_CKO2_PODF 169
-#define IMX5_CLK_CKO2 170
-#define IMX5_CLK_SRTC_GATE 171
-#define IMX5_CLK_PATA_GATE 172
-#define IMX5_CLK_SATA_GATE 173
-#define IMX5_CLK_SPDIF_XTAL_SEL 174
-#define IMX5_CLK_SPDIF0_SEL 175
-#define IMX5_CLK_SPDIF1_SEL 176
-#define IMX5_CLK_SPDIF0_PRED 177
-#define IMX5_CLK_SPDIF0_PODF 178
-#define IMX5_CLK_SPDIF1_PRED 179
-#define IMX5_CLK_SPDIF1_PODF 180
-#define IMX5_CLK_SPDIF0_COM_SEL 181
-#define IMX5_CLK_SPDIF1_COM_SEL 182
-#define IMX5_CLK_SPDIF0_GATE 183
-#define IMX5_CLK_SPDIF1_GATE 184
-#define IMX5_CLK_SPDIF_IPG_GATE 185
-#define IMX5_CLK_OCRAM 186
-#define IMX5_CLK_SAHARA_IPG_GATE 187
-#define IMX5_CLK_SATA_REF 188
-#define IMX5_CLK_STEP_SEL 189
-#define IMX5_CLK_CPU_PODF_SEL 190
-#define IMX5_CLK_ARM 191
-#define IMX5_CLK_FIRI_PRED 192
-#define IMX5_CLK_FIRI_SEL 193
-#define IMX5_CLK_FIRI_PODF 194
-#define IMX5_CLK_FIRI_SERIAL_GATE 195
-#define IMX5_CLK_FIRI_IPG_GATE 196
-#define IMX5_CLK_CSI0_MCLK1_PRED 197
-#define IMX5_CLK_CSI0_MCLK1_SEL 198
-#define IMX5_CLK_CSI0_MCLK1_PODF 199
-#define IMX5_CLK_CSI0_MCLK1_GATE 200
-#define IMX5_CLK_IEEE1588_PRED 201
-#define IMX5_CLK_IEEE1588_SEL 202
-#define IMX5_CLK_IEEE1588_PODF 203
-#define IMX5_CLK_IEEE1588_GATE 204
-#define IMX5_CLK_END 205
-
-#endif /* __DT_BINDINGS_CLOCK_IMX5_H */
diff --git a/include/dt-bindings/clock/imx6qdl-clock.h b/include/dt-bindings/clock/imx6qdl-clock.h
deleted file mode 100644
index 2905033..0000000
--- a/include/dt-bindings/clock/imx6qdl-clock.h
+++ /dev/null
@@ -1,274 +0,0 @@
-/*
- * Copyright 2014 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __DT_BINDINGS_CLOCK_IMX6QDL_H
-#define __DT_BINDINGS_CLOCK_IMX6QDL_H
-
-#define IMX6QDL_CLK_DUMMY 0
-#define IMX6QDL_CLK_CKIL 1
-#define IMX6QDL_CLK_CKIH 2
-#define IMX6QDL_CLK_OSC 3
-#define IMX6QDL_CLK_PLL2_PFD0_352M 4
-#define IMX6QDL_CLK_PLL2_PFD1_594M 5
-#define IMX6QDL_CLK_PLL2_PFD2_396M 6
-#define IMX6QDL_CLK_PLL3_PFD0_720M 7
-#define IMX6QDL_CLK_PLL3_PFD1_540M 8
-#define IMX6QDL_CLK_PLL3_PFD2_508M 9
-#define IMX6QDL_CLK_PLL3_PFD3_454M 10
-#define IMX6QDL_CLK_PLL2_198M 11
-#define IMX6QDL_CLK_PLL3_120M 12
-#define IMX6QDL_CLK_PLL3_80M 13
-#define IMX6QDL_CLK_PLL3_60M 14
-#define IMX6QDL_CLK_TWD 15
-#define IMX6QDL_CLK_STEP 16
-#define IMX6QDL_CLK_PLL1_SW 17
-#define IMX6QDL_CLK_PERIPH_PRE 18
-#define IMX6QDL_CLK_PERIPH2_PRE 19
-#define IMX6QDL_CLK_PERIPH_CLK2_SEL 20
-#define IMX6QDL_CLK_PERIPH2_CLK2_SEL 21
-#define IMX6QDL_CLK_AXI_SEL 22
-#define IMX6QDL_CLK_ESAI_SEL 23
-#define IMX6QDL_CLK_ASRC_SEL 24
-#define IMX6QDL_CLK_SPDIF_SEL 25
-#define IMX6QDL_CLK_GPU2D_AXI 26
-#define IMX6QDL_CLK_GPU3D_AXI 27
-#define IMX6QDL_CLK_GPU2D_CORE_SEL 28
-#define IMX6QDL_CLK_GPU3D_CORE_SEL 29
-#define IMX6QDL_CLK_GPU3D_SHADER_SEL 30
-#define IMX6QDL_CLK_IPU1_SEL 31
-#define IMX6QDL_CLK_IPU2_SEL 32
-#define IMX6QDL_CLK_LDB_DI0_SEL 33
-#define IMX6QDL_CLK_LDB_DI1_SEL 34
-#define IMX6QDL_CLK_IPU1_DI0_PRE_SEL 35
-#define IMX6QDL_CLK_IPU1_DI1_PRE_SEL 36
-#define IMX6QDL_CLK_IPU2_DI0_PRE_SEL 37
-#define IMX6QDL_CLK_IPU2_DI1_PRE_SEL 38
-#define IMX6QDL_CLK_IPU1_DI0_SEL 39
-#define IMX6QDL_CLK_IPU1_DI1_SEL 40
-#define IMX6QDL_CLK_IPU2_DI0_SEL 41
-#define IMX6QDL_CLK_IPU2_DI1_SEL 42
-#define IMX6QDL_CLK_HSI_TX_SEL 43
-#define IMX6QDL_CLK_PCIE_AXI_SEL 44
-#define IMX6QDL_CLK_SSI1_SEL 45
-#define IMX6QDL_CLK_SSI2_SEL 46
-#define IMX6QDL_CLK_SSI3_SEL 47
-#define IMX6QDL_CLK_USDHC1_SEL 48
-#define IMX6QDL_CLK_USDHC2_SEL 49
-#define IMX6QDL_CLK_USDHC3_SEL 50
-#define IMX6QDL_CLK_USDHC4_SEL 51
-#define IMX6QDL_CLK_ENFC_SEL 52
-#define IMX6QDL_CLK_EIM_SEL 53
-#define IMX6QDL_CLK_EIM_SLOW_SEL 54
-#define IMX6QDL_CLK_VDO_AXI_SEL 55
-#define IMX6QDL_CLK_VPU_AXI_SEL 56
-#define IMX6QDL_CLK_CKO1_SEL 57
-#define IMX6QDL_CLK_PERIPH 58
-#define IMX6QDL_CLK_PERIPH2 59
-#define IMX6QDL_CLK_PERIPH_CLK2 60
-#define IMX6QDL_CLK_PERIPH2_CLK2 61
-#define IMX6QDL_CLK_IPG 62
-#define IMX6QDL_CLK_IPG_PER 63
-#define IMX6QDL_CLK_ESAI_PRED 64
-#define IMX6QDL_CLK_ESAI_PODF 65
-#define IMX6QDL_CLK_ASRC_PRED 66
-#define IMX6QDL_CLK_ASRC_PODF 67
-#define IMX6QDL_CLK_SPDIF_PRED 68
-#define IMX6QDL_CLK_SPDIF_PODF 69
-#define IMX6QDL_CLK_CAN_ROOT 70
-#define IMX6QDL_CLK_ECSPI_ROOT 71
-#define IMX6QDL_CLK_GPU2D_CORE_PODF 72
-#define IMX6QDL_CLK_GPU3D_CORE_PODF 73
-#define IMX6QDL_CLK_GPU3D_SHADER 74
-#define IMX6QDL_CLK_IPU1_PODF 75
-#define IMX6QDL_CLK_IPU2_PODF 76
-#define IMX6QDL_CLK_LDB_DI0_PODF 77
-#define IMX6QDL_CLK_LDB_DI1_PODF 78
-#define IMX6QDL_CLK_IPU1_DI0_PRE 79
-#define IMX6QDL_CLK_IPU1_DI1_PRE 80
-#define IMX6QDL_CLK_IPU2_DI0_PRE 81
-#define IMX6QDL_CLK_IPU2_DI1_PRE 82
-#define IMX6QDL_CLK_HSI_TX_PODF 83
-#define IMX6QDL_CLK_SSI1_PRED 84
-#define IMX6QDL_CLK_SSI1_PODF 85
-#define IMX6QDL_CLK_SSI2_PRED 86
-#define IMX6QDL_CLK_SSI2_PODF 87
-#define IMX6QDL_CLK_SSI3_PRED 88
-#define IMX6QDL_CLK_SSI3_PODF 89
-#define IMX6QDL_CLK_UART_SERIAL_PODF 90
-#define IMX6QDL_CLK_USDHC1_PODF 91
-#define IMX6QDL_CLK_USDHC2_PODF 92
-#define IMX6QDL_CLK_USDHC3_PODF 93
-#define IMX6QDL_CLK_USDHC4_PODF 94
-#define IMX6QDL_CLK_ENFC_PRED 95
-#define IMX6QDL_CLK_ENFC_PODF 96
-#define IMX6QDL_CLK_EIM_PODF 97
-#define IMX6QDL_CLK_EIM_SLOW_PODF 98
-#define IMX6QDL_CLK_VPU_AXI_PODF 99
-#define IMX6QDL_CLK_CKO1_PODF 100
-#define IMX6QDL_CLK_AXI 101
-#define IMX6QDL_CLK_MMDC_CH0_AXI_PODF 102
-#define IMX6QDL_CLK_MMDC_CH1_AXI_PODF 103
-#define IMX6QDL_CLK_ARM 104
-#define IMX6QDL_CLK_AHB 105
-#define IMX6QDL_CLK_APBH_DMA 106
-#define IMX6QDL_CLK_ASRC 107
-#define IMX6QDL_CLK_CAN1_IPG 108
-#define IMX6QDL_CLK_CAN1_SERIAL 109
-#define IMX6QDL_CLK_CAN2_IPG 110
-#define IMX6QDL_CLK_CAN2_SERIAL 111
-#define IMX6QDL_CLK_ECSPI1 112
-#define IMX6QDL_CLK_ECSPI2 113
-#define IMX6QDL_CLK_ECSPI3 114
-#define IMX6QDL_CLK_ECSPI4 115
-#define IMX6Q_CLK_ECSPI5 116
-#define IMX6DL_CLK_I2C4 116
-#define IMX6QDL_CLK_ENET 117
-#define IMX6QDL_CLK_ESAI_EXTAL 118
-#define IMX6QDL_CLK_GPT_IPG 119
-#define IMX6QDL_CLK_GPT_IPG_PER 120
-#define IMX6QDL_CLK_GPU2D_CORE 121
-#define IMX6QDL_CLK_GPU3D_CORE 122
-#define IMX6QDL_CLK_HDMI_IAHB 123
-#define IMX6QDL_CLK_HDMI_ISFR 124
-#define IMX6QDL_CLK_I2C1 125
-#define IMX6QDL_CLK_I2C2 126
-#define IMX6QDL_CLK_I2C3 127
-#define IMX6QDL_CLK_IIM 128
-#define IMX6QDL_CLK_ENFC 129
-#define IMX6QDL_CLK_IPU1 130
-#define IMX6QDL_CLK_IPU1_DI0 131
-#define IMX6QDL_CLK_IPU1_DI1 132
-#define IMX6QDL_CLK_IPU2 133
-#define IMX6QDL_CLK_IPU2_DI0 134
-#define IMX6QDL_CLK_LDB_DI0 135
-#define IMX6QDL_CLK_LDB_DI1 136
-#define IMX6QDL_CLK_IPU2_DI1 137
-#define IMX6QDL_CLK_HSI_TX 138
-#define IMX6QDL_CLK_MLB 139
-#define IMX6QDL_CLK_MMDC_CH0_AXI 140
-#define IMX6QDL_CLK_MMDC_CH1_AXI 141
-#define IMX6QDL_CLK_OCRAM 142
-#define IMX6QDL_CLK_OPENVG_AXI 143
-#define IMX6QDL_CLK_PCIE_AXI 144
-#define IMX6QDL_CLK_PWM1 145
-#define IMX6QDL_CLK_PWM2 146
-#define IMX6QDL_CLK_PWM3 147
-#define IMX6QDL_CLK_PWM4 148
-#define IMX6QDL_CLK_PER1_BCH 149
-#define IMX6QDL_CLK_GPMI_BCH_APB 150
-#define IMX6QDL_CLK_GPMI_BCH 151
-#define IMX6QDL_CLK_GPMI_IO 152
-#define IMX6QDL_CLK_GPMI_APB 153
-#define IMX6QDL_CLK_SATA 154
-#define IMX6QDL_CLK_SDMA 155
-#define IMX6QDL_CLK_SPBA 156
-#define IMX6QDL_CLK_SSI1 157
-#define IMX6QDL_CLK_SSI2 158
-#define IMX6QDL_CLK_SSI3 159
-#define IMX6QDL_CLK_UART_IPG 160
-#define IMX6QDL_CLK_UART_SERIAL 161
-#define IMX6QDL_CLK_USBOH3 162
-#define IMX6QDL_CLK_USDHC1 163
-#define IMX6QDL_CLK_USDHC2 164
-#define IMX6QDL_CLK_USDHC3 165
-#define IMX6QDL_CLK_USDHC4 166
-#define IMX6QDL_CLK_VDO_AXI 167
-#define IMX6QDL_CLK_VPU_AXI 168
-#define IMX6QDL_CLK_CKO1 169
-#define IMX6QDL_CLK_PLL1_SYS 170
-#define IMX6QDL_CLK_PLL2_BUS 171
-#define IMX6QDL_CLK_PLL3_USB_OTG 172
-#define IMX6QDL_CLK_PLL4_AUDIO 173
-#define IMX6QDL_CLK_PLL5_VIDEO 174
-#define IMX6QDL_CLK_PLL8_MLB 175
-#define IMX6QDL_CLK_PLL7_USB_HOST 176
-#define IMX6QDL_CLK_PLL6_ENET 177
-#define IMX6QDL_CLK_SSI1_IPG 178
-#define IMX6QDL_CLK_SSI2_IPG 179
-#define IMX6QDL_CLK_SSI3_IPG 180
-#define IMX6QDL_CLK_ROM 181
-#define IMX6QDL_CLK_USBPHY1 182
-#define IMX6QDL_CLK_USBPHY2 183
-#define IMX6QDL_CLK_LDB_DI0_DIV_3_5 184
-#define IMX6QDL_CLK_LDB_DI1_DIV_3_5 185
-#define IMX6QDL_CLK_SATA_REF 186
-#define IMX6QDL_CLK_SATA_REF_100M 187
-#define IMX6QDL_CLK_PCIE_REF 188
-#define IMX6QDL_CLK_PCIE_REF_125M 189
-#define IMX6QDL_CLK_ENET_REF 190
-#define IMX6QDL_CLK_USBPHY1_GATE 191
-#define IMX6QDL_CLK_USBPHY2_GATE 192
-#define IMX6QDL_CLK_PLL4_POST_DIV 193
-#define IMX6QDL_CLK_PLL5_POST_DIV 194
-#define IMX6QDL_CLK_PLL5_VIDEO_DIV 195
-#define IMX6QDL_CLK_EIM_SLOW 196
-#define IMX6QDL_CLK_SPDIF 197
-#define IMX6QDL_CLK_CKO2_SEL 198
-#define IMX6QDL_CLK_CKO2_PODF 199
-#define IMX6QDL_CLK_CKO2 200
-#define IMX6QDL_CLK_CKO 201
-#define IMX6QDL_CLK_VDOA 202
-#define IMX6QDL_CLK_PLL4_AUDIO_DIV 203
-#define IMX6QDL_CLK_LVDS1_SEL 204
-#define IMX6QDL_CLK_LVDS2_SEL 205
-#define IMX6QDL_CLK_LVDS1_GATE 206
-#define IMX6QDL_CLK_LVDS2_GATE 207
-#define IMX6QDL_CLK_ESAI_IPG 208
-#define IMX6QDL_CLK_ESAI_MEM 209
-#define IMX6QDL_CLK_ASRC_IPG 210
-#define IMX6QDL_CLK_ASRC_MEM 211
-#define IMX6QDL_CLK_LVDS1_IN 212
-#define IMX6QDL_CLK_LVDS2_IN 213
-#define IMX6QDL_CLK_ANACLK1 214
-#define IMX6QDL_CLK_ANACLK2 215
-#define IMX6QDL_PLL1_BYPASS_SRC 216
-#define IMX6QDL_PLL2_BYPASS_SRC 217
-#define IMX6QDL_PLL3_BYPASS_SRC 218
-#define IMX6QDL_PLL4_BYPASS_SRC 219
-#define IMX6QDL_PLL5_BYPASS_SRC 220
-#define IMX6QDL_PLL6_BYPASS_SRC 221
-#define IMX6QDL_PLL7_BYPASS_SRC 222
-#define IMX6QDL_CLK_PLL1 223
-#define IMX6QDL_CLK_PLL2 224
-#define IMX6QDL_CLK_PLL3 225
-#define IMX6QDL_CLK_PLL4 226
-#define IMX6QDL_CLK_PLL5 227
-#define IMX6QDL_CLK_PLL6 228
-#define IMX6QDL_CLK_PLL7 229
-#define IMX6QDL_PLL1_BYPASS 230
-#define IMX6QDL_PLL2_BYPASS 231
-#define IMX6QDL_PLL3_BYPASS 232
-#define IMX6QDL_PLL4_BYPASS 233
-#define IMX6QDL_PLL5_BYPASS 234
-#define IMX6QDL_PLL6_BYPASS 235
-#define IMX6QDL_PLL7_BYPASS 236
-#define IMX6QDL_CLK_GPT_3M 237
-#define IMX6QDL_CLK_VIDEO_27M 238
-#define IMX6QDL_CLK_MIPI_CORE_CFG 239
-#define IMX6QDL_CLK_MIPI_IPG 240
-#define IMX6QDL_CLK_CAAM_MEM 241
-#define IMX6QDL_CLK_CAAM_ACLK 242
-#define IMX6QDL_CLK_CAAM_IPG 243
-#define IMX6QDL_CLK_SPDIF_GCLK 244
-#define IMX6QDL_CLK_UART_SEL 245
-#define IMX6QDL_CLK_IPG_PER_SEL 246
-#define IMX6QDL_CLK_ECSPI_SEL 247
-#define IMX6QDL_CLK_CAN_SEL 248
-#define IMX6QDL_CLK_MMDC_CH1_AXI_CG 249
-#define IMX6QDL_CLK_PRE0 250
-#define IMX6QDL_CLK_PRE1 251
-#define IMX6QDL_CLK_PRE2 252
-#define IMX6QDL_CLK_PRE3 253
-#define IMX6QDL_CLK_PRG0_AXI 254
-#define IMX6QDL_CLK_PRG1_AXI 255
-#define IMX6QDL_CLK_PRG0_APB 256
-#define IMX6QDL_CLK_PRG1_APB 257
-#define IMX6QDL_CLK_PRE_AXI 258
-#define IMX6QDL_CLK_END 259
-
-#endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */
diff --git a/include/dt-bindings/clock/imx6sl-clock.h b/include/dt-bindings/clock/imx6sl-clock.h
deleted file mode 100644
index e14573e..0000000
--- a/include/dt-bindings/clock/imx6sl-clock.h
+++ /dev/null
@@ -1,180 +0,0 @@
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-#ifndef __DT_BINDINGS_CLOCK_IMX6SL_H
-#define __DT_BINDINGS_CLOCK_IMX6SL_H
-
-#define IMX6SL_CLK_DUMMY 0
-#define IMX6SL_CLK_CKIL 1
-#define IMX6SL_CLK_OSC 2
-#define IMX6SL_CLK_PLL1_SYS 3
-#define IMX6SL_CLK_PLL2_BUS 4
-#define IMX6SL_CLK_PLL3_USB_OTG 5
-#define IMX6SL_CLK_PLL4_AUDIO 6
-#define IMX6SL_CLK_PLL5_VIDEO 7
-#define IMX6SL_CLK_PLL6_ENET 8
-#define IMX6SL_CLK_PLL7_USB_HOST 9
-#define IMX6SL_CLK_USBPHY1 10
-#define IMX6SL_CLK_USBPHY2 11
-#define IMX6SL_CLK_USBPHY1_GATE 12
-#define IMX6SL_CLK_USBPHY2_GATE 13
-#define IMX6SL_CLK_PLL4_POST_DIV 14
-#define IMX6SL_CLK_PLL5_POST_DIV 15
-#define IMX6SL_CLK_PLL5_VIDEO_DIV 16
-#define IMX6SL_CLK_ENET_REF 17
-#define IMX6SL_CLK_PLL2_PFD0 18
-#define IMX6SL_CLK_PLL2_PFD1 19
-#define IMX6SL_CLK_PLL2_PFD2 20
-#define IMX6SL_CLK_PLL3_PFD0 21
-#define IMX6SL_CLK_PLL3_PFD1 22
-#define IMX6SL_CLK_PLL3_PFD2 23
-#define IMX6SL_CLK_PLL3_PFD3 24
-#define IMX6SL_CLK_PLL2_198M 25
-#define IMX6SL_CLK_PLL3_120M 26
-#define IMX6SL_CLK_PLL3_80M 27
-#define IMX6SL_CLK_PLL3_60M 28
-#define IMX6SL_CLK_STEP 29
-#define IMX6SL_CLK_PLL1_SW 30
-#define IMX6SL_CLK_OCRAM_ALT_SEL 31
-#define IMX6SL_CLK_OCRAM_SEL 32
-#define IMX6SL_CLK_PRE_PERIPH2_SEL 33
-#define IMX6SL_CLK_PRE_PERIPH_SEL 34
-#define IMX6SL_CLK_PERIPH2_CLK2_SEL 35
-#define IMX6SL_CLK_PERIPH_CLK2_SEL 36
-#define IMX6SL_CLK_CSI_SEL 37
-#define IMX6SL_CLK_LCDIF_AXI_SEL 38
-#define IMX6SL_CLK_USDHC1_SEL 39
-#define IMX6SL_CLK_USDHC2_SEL 40
-#define IMX6SL_CLK_USDHC3_SEL 41
-#define IMX6SL_CLK_USDHC4_SEL 42
-#define IMX6SL_CLK_SSI1_SEL 43
-#define IMX6SL_CLK_SSI2_SEL 44
-#define IMX6SL_CLK_SSI3_SEL 45
-#define IMX6SL_CLK_PERCLK_SEL 46
-#define IMX6SL_CLK_PXP_AXI_SEL 47
-#define IMX6SL_CLK_EPDC_AXI_SEL 48
-#define IMX6SL_CLK_GPU2D_OVG_SEL 49
-#define IMX6SL_CLK_GPU2D_SEL 50
-#define IMX6SL_CLK_LCDIF_PIX_SEL 51
-#define IMX6SL_CLK_EPDC_PIX_SEL 52
-#define IMX6SL_CLK_SPDIF0_SEL 53
-#define IMX6SL_CLK_SPDIF1_SEL 54
-#define IMX6SL_CLK_EXTERN_AUDIO_SEL 55
-#define IMX6SL_CLK_ECSPI_SEL 56
-#define IMX6SL_CLK_UART_SEL 57
-#define IMX6SL_CLK_PERIPH 58
-#define IMX6SL_CLK_PERIPH2 59
-#define IMX6SL_CLK_OCRAM_PODF 60
-#define IMX6SL_CLK_PERIPH_CLK2_PODF 61
-#define IMX6SL_CLK_PERIPH2_CLK2_PODF 62
-#define IMX6SL_CLK_IPG 63
-#define IMX6SL_CLK_CSI_PODF 64
-#define IMX6SL_CLK_LCDIF_AXI_PODF 65
-#define IMX6SL_CLK_USDHC1_PODF 66
-#define IMX6SL_CLK_USDHC2_PODF 67
-#define IMX6SL_CLK_USDHC3_PODF 68
-#define IMX6SL_CLK_USDHC4_PODF 69
-#define IMX6SL_CLK_SSI1_PRED 70
-#define IMX6SL_CLK_SSI1_PODF 71
-#define IMX6SL_CLK_SSI2_PRED 72
-#define IMX6SL_CLK_SSI2_PODF 73
-#define IMX6SL_CLK_SSI3_PRED 74
-#define IMX6SL_CLK_SSI3_PODF 75
-#define IMX6SL_CLK_PERCLK 76
-#define IMX6SL_CLK_PXP_AXI_PODF 77
-#define IMX6SL_CLK_EPDC_AXI_PODF 78
-#define IMX6SL_CLK_GPU2D_OVG_PODF 79
-#define IMX6SL_CLK_GPU2D_PODF 80
-#define IMX6SL_CLK_LCDIF_PIX_PRED 81
-#define IMX6SL_CLK_EPDC_PIX_PRED 82
-#define IMX6SL_CLK_LCDIF_PIX_PODF 83
-#define IMX6SL_CLK_EPDC_PIX_PODF 84
-#define IMX6SL_CLK_SPDIF0_PRED 85
-#define IMX6SL_CLK_SPDIF0_PODF 86
-#define IMX6SL_CLK_SPDIF1_PRED 87
-#define IMX6SL_CLK_SPDIF1_PODF 88
-#define IMX6SL_CLK_EXTERN_AUDIO_PRED 89
-#define IMX6SL_CLK_EXTERN_AUDIO_PODF 90
-#define IMX6SL_CLK_ECSPI_ROOT 91
-#define IMX6SL_CLK_UART_ROOT 92
-#define IMX6SL_CLK_AHB 93
-#define IMX6SL_CLK_MMDC_ROOT 94
-#define IMX6SL_CLK_ARM 95
-#define IMX6SL_CLK_ECSPI1 96
-#define IMX6SL_CLK_ECSPI2 97
-#define IMX6SL_CLK_ECSPI3 98
-#define IMX6SL_CLK_ECSPI4 99
-#define IMX6SL_CLK_EPIT1 100
-#define IMX6SL_CLK_EPIT2 101
-#define IMX6SL_CLK_EXTERN_AUDIO 102
-#define IMX6SL_CLK_GPT 103
-#define IMX6SL_CLK_GPT_SERIAL 104
-#define IMX6SL_CLK_GPU2D_OVG 105
-#define IMX6SL_CLK_I2C1 106
-#define IMX6SL_CLK_I2C2 107
-#define IMX6SL_CLK_I2C3 108
-#define IMX6SL_CLK_OCOTP 109
-#define IMX6SL_CLK_CSI 110
-#define IMX6SL_CLK_PXP_AXI 111
-#define IMX6SL_CLK_EPDC_AXI 112
-#define IMX6SL_CLK_LCDIF_AXI 113
-#define IMX6SL_CLK_LCDIF_PIX 114
-#define IMX6SL_CLK_EPDC_PIX 115
-#define IMX6SL_CLK_OCRAM 116
-#define IMX6SL_CLK_PWM1 117
-#define IMX6SL_CLK_PWM2 118
-#define IMX6SL_CLK_PWM3 119
-#define IMX6SL_CLK_PWM4 120
-#define IMX6SL_CLK_SDMA 121
-#define IMX6SL_CLK_SPDIF 122
-#define IMX6SL_CLK_SSI1 123
-#define IMX6SL_CLK_SSI2 124
-#define IMX6SL_CLK_SSI3 125
-#define IMX6SL_CLK_UART 126
-#define IMX6SL_CLK_UART_SERIAL 127
-#define IMX6SL_CLK_USBOH3 128
-#define IMX6SL_CLK_USDHC1 129
-#define IMX6SL_CLK_USDHC2 130
-#define IMX6SL_CLK_USDHC3 131
-#define IMX6SL_CLK_USDHC4 132
-#define IMX6SL_CLK_PLL4_AUDIO_DIV 133
-#define IMX6SL_CLK_SPBA 134
-#define IMX6SL_CLK_ENET 135
-#define IMX6SL_CLK_LVDS1_SEL 136
-#define IMX6SL_CLK_LVDS1_OUT 137
-#define IMX6SL_CLK_LVDS1_IN 138
-#define IMX6SL_CLK_ANACLK1 139
-#define IMX6SL_PLL1_BYPASS_SRC 140
-#define IMX6SL_PLL2_BYPASS_SRC 141
-#define IMX6SL_PLL3_BYPASS_SRC 142
-#define IMX6SL_PLL4_BYPASS_SRC 143
-#define IMX6SL_PLL5_BYPASS_SRC 144
-#define IMX6SL_PLL6_BYPASS_SRC 145
-#define IMX6SL_PLL7_BYPASS_SRC 146
-#define IMX6SL_CLK_PLL1 147
-#define IMX6SL_CLK_PLL2 148
-#define IMX6SL_CLK_PLL3 149
-#define IMX6SL_CLK_PLL4 150
-#define IMX6SL_CLK_PLL5 151
-#define IMX6SL_CLK_PLL6 152
-#define IMX6SL_CLK_PLL7 153
-#define IMX6SL_PLL1_BYPASS 154
-#define IMX6SL_PLL2_BYPASS 155
-#define IMX6SL_PLL3_BYPASS 156
-#define IMX6SL_PLL4_BYPASS 157
-#define IMX6SL_PLL5_BYPASS 158
-#define IMX6SL_PLL6_BYPASS 159
-#define IMX6SL_PLL7_BYPASS 160
-#define IMX6SL_CLK_SSI1_IPG 161
-#define IMX6SL_CLK_SSI2_IPG 162
-#define IMX6SL_CLK_SSI3_IPG 163
-#define IMX6SL_CLK_SPDIF_GCLK 164
-#define IMX6SL_CLK_END 165
-
-#endif /* __DT_BINDINGS_CLOCK_IMX6SL_H */
diff --git a/include/dt-bindings/clock/imx6sll-clock.h b/include/dt-bindings/clock/imx6sll-clock.h
deleted file mode 100644
index 39c2567..0000000
--- a/include/dt-bindings/clock/imx6sll-clock.h
+++ /dev/null
@@ -1,204 +0,0 @@
-/*
- * Copyright (C) 2016 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-#ifndef __DT_BINDINGS_CLOCK_IMX6SLL_H
-#define __DT_BINDINGS_CLOCK_IMX6SLL_H
-
-#define IMX6SLL_CLK_DUMMY 0
-#define IMX6SLL_CLK_CKIL 1
-#define IMX6SLL_CLK_OSC 2
-#define IMX6SLL_PLL1_BYPASS_SRC 3
-#define IMX6SLL_PLL2_BYPASS_SRC 4
-#define IMX6SLL_PLL3_BYPASS_SRC 5
-#define IMX6SLL_PLL4_BYPASS_SRC 6
-#define IMX6SLL_PLL5_BYPASS_SRC 7
-#define IMX6SLL_PLL6_BYPASS_SRC 8
-#define IMX6SLL_PLL7_BYPASS_SRC 9
-#define IMX6SLL_CLK_PLL1 10
-#define IMX6SLL_CLK_PLL2 11
-#define IMX6SLL_CLK_PLL3 12
-#define IMX6SLL_CLK_PLL4 13
-#define IMX6SLL_CLK_PLL5 14
-#define IMX6SLL_CLK_PLL6 15
-#define IMX6SLL_CLK_PLL7 16
-#define IMX6SLL_PLL1_BYPASS 17
-#define IMX6SLL_PLL2_BYPASS 18
-#define IMX6SLL_PLL3_BYPASS 19
-#define IMX6SLL_PLL4_BYPASS 20
-#define IMX6SLL_PLL5_BYPASS 21
-#define IMX6SLL_PLL6_BYPASS 22
-#define IMX6SLL_PLL7_BYPASS 23
-#define IMX6SLL_CLK_PLL1_SYS 24
-#define IMX6SLL_CLK_PLL2_BUS 25
-#define IMX6SLL_CLK_PLL3_USB_OTG 26
-#define IMX6SLL_CLK_PLL4_AUDIO 27
-#define IMX6SLL_CLK_PLL5_VIDEO 28
-#define IMX6SLL_CLK_PLL6_ENET 29
-#define IMX6SLL_CLK_PLL7_USB_HOST 30
-#define IMX6SLL_CLK_USBPHY1 31
-#define IMX6SLL_CLK_USBPHY2 32
-#define IMX6SLL_CLK_USBPHY1_GATE 33
-#define IMX6SLL_CLK_USBPHY2_GATE 34
-#define IMX6SLL_CLK_PLL2_PFD0 35
-#define IMX6SLL_CLK_PLL2_PFD1 36
-#define IMX6SLL_CLK_PLL2_PFD2 37
-#define IMX6SLL_CLK_PLL2_PFD3 38
-#define IMX6SLL_CLK_PLL3_PFD0 39
-#define IMX6SLL_CLK_PLL3_PFD1 40
-#define IMX6SLL_CLK_PLL3_PFD2 41
-#define IMX6SLL_CLK_PLL3_PFD3 42
-#define IMX6SLL_CLK_PLL4_POST_DIV 43
-#define IMX6SLL_CLK_PLL4_AUDIO_DIV 44
-#define IMX6SLL_CLK_PLL5_POST_DIV 45
-#define IMX6SLL_CLK_PLL5_VIDEO_DIV 46
-#define IMX6SLL_CLK_PLL2_198M 47
-#define IMX6SLL_CLK_PLL3_120M 48
-#define IMX6SLL_CLK_PLL3_80M 49
-#define IMX6SLL_CLK_PLL3_60M 50
-#define IMX6SLL_CLK_STEP 51
-#define IMX6SLL_CLK_PLL1_SW 52
-#define IMX6SLL_CLK_AXI_ALT_SEL 53
-#define IMX6SLL_CLK_AXI_SEL 54
-#define IMX6SLL_CLK_PERIPH_PRE 55
-#define IMX6SLL_CLK_PERIPH2_PRE 56
-#define IMX6SLL_CLK_PERIPH_CLK2_SEL 57
-#define IMX6SLL_CLK_PERIPH2_CLK2_SEL 58
-#define IMX6SLL_CLK_PERCLK_SEL 59
-#define IMX6SLL_CLK_USDHC1_SEL 60
-#define IMX6SLL_CLK_USDHC2_SEL 61
-#define IMX6SLL_CLK_USDHC3_SEL 62
-#define IMX6SLL_CLK_SSI1_SEL 63
-#define IMX6SLL_CLK_SSI2_SEL 64
-#define IMX6SLL_CLK_SSI3_SEL 65
-#define IMX6SLL_CLK_PXP_SEL 66
-#define IMX6SLL_CLK_LCDIF_PRE_SEL 67
-#define IMX6SLL_CLK_LCDIF_SEL 68
-#define IMX6SLL_CLK_EPDC_PRE_SEL 69
-#define IMX6SLL_CLK_SPDIF_SEL 70
-#define IMX6SLL_CLK_ECSPI_SEL 71
-#define IMX6SLL_CLK_UART_SEL 72
-#define IMX6SLL_CLK_ARM 73
-#define IMX6SLL_CLK_PERIPH 74
-#define IMX6SLL_CLK_PERIPH2 75
-#define IMX6SLL_CLK_PERIPH2_CLK2 76
-#define IMX6SLL_CLK_PERIPH_CLK2 77
-#define IMX6SLL_CLK_MMDC_PODF 78
-#define IMX6SLL_CLK_AXI_PODF 79
-#define IMX6SLL_CLK_AHB 80
-#define IMX6SLL_CLK_IPG 81
-#define IMX6SLL_CLK_PERCLK 82
-#define IMX6SLL_CLK_USDHC1_PODF 83
-#define IMX6SLL_CLK_USDHC2_PODF 84
-#define IMX6SLL_CLK_USDHC3_PODF 85
-#define IMX6SLL_CLK_SSI1_PRED 86
-#define IMX6SLL_CLK_SSI2_PRED 87
-#define IMX6SLL_CLK_SSI3_PRED 88
-#define IMX6SLL_CLK_SSI1_PODF 89
-#define IMX6SLL_CLK_SSI2_PODF 90
-#define IMX6SLL_CLK_SSI3_PODF 91
-#define IMX6SLL_CLK_PXP_PODF 92
-#define IMX6SLL_CLK_LCDIF_PRED 93
-#define IMX6SLL_CLK_LCDIF_PODF 94
-#define IMX6SLL_CLK_EPDC_SEL 95
-#define IMX6SLL_CLK_EPDC_PODF 96
-#define IMX6SLL_CLK_SPDIF_PRED 97
-#define IMX6SLL_CLK_SPDIF_PODF 98
-#define IMX6SLL_CLK_ECSPI_PODF 99
-#define IMX6SLL_CLK_UART_PODF 100
-
-/* CCGR 0 */
-#define IMX6SLL_CLK_AIPSTZ1 101
-#define IMX6SLL_CLK_AIPSTZ2 102
-#define IMX6SLL_CLK_DCP 103
-#define IMX6SLL_CLK_UART2_IPG 104
-#define IMX6SLL_CLK_UART2_SERIAL 105
-
-/* CCGR 1 */
-#define IMX6SLL_CLK_ECSPI1 106
-#define IMX6SLL_CLK_ECSPI2 107
-#define IMX6SLL_CLK_ECSPI3 108
-#define IMX6SLL_CLK_ECSPI4 109
-#define IMX6SLL_CLK_UART3_IPG 110
-#define IMX6SLL_CLK_UART3_SERIAL 111
-#define IMX6SLL_CLK_UART4_IPG 112
-#define IMX6SLL_CLK_UART4_SERIAL 113
-#define IMX6SLL_CLK_EPIT1 114
-#define IMX6SLL_CLK_EPIT2 115
-#define IMX6SLL_CLK_GPT_BUS 116
-#define IMX6SLL_CLK_GPT_SERIAL 117
-
-/* CCGR2 */
-#define IMX6SLL_CLK_CSI 118
-#define IMX6SLL_CLK_I2C1 119
-#define IMX6SLL_CLK_I2C2 120
-#define IMX6SLL_CLK_I2C3 121
-#define IMX6SLL_CLK_OCOTP 122
-#define IMX6SLL_CLK_LCDIF_APB 123
-#define IMX6SLL_CLK_PXP 124
-
-/* CCGR3 */
-#define IMX6SLL_CLK_UART5_IPG 125
-#define IMX6SLL_CLK_UART5_SERIAL 126
-#define IMX6SLL_CLK_EPDC_AXI 127
-#define IMX6SLL_CLK_EPDC_PIX 128
-#define IMX6SLL_CLK_LCDIF_PIX 129
-#define IMX6SLL_CLK_WDOG1 130
-#define IMX6SLL_CLK_MMDC_P0_FAST 131
-#define IMX6SLL_CLK_MMDC_P0_IPG 132
-#define IMX6SLL_CLK_OCRAM 133
-
-/* CCGR4 */
-#define IMX6SLL_CLK_PWM1 134
-#define IMX6SLL_CLK_PWM2 135
-#define IMX6SLL_CLK_PWM3 136
-#define IMX6SLL_CLK_PWM4 137
-
-/* CCGR 5 */
-#define IMX6SLL_CLK_ROM 138
-#define IMX6SLL_CLK_SDMA 139
-#define IMX6SLL_CLK_KPP 140
-#define IMX6SLL_CLK_WDOG2 141
-#define IMX6SLL_CLK_SPBA 142
-#define IMX6SLL_CLK_SPDIF 143
-#define IMX6SLL_CLK_SPDIF_GCLK 144
-#define IMX6SLL_CLK_SSI1 145
-#define IMX6SLL_CLK_SSI1_IPG 146
-#define IMX6SLL_CLK_SSI2 147
-#define IMX6SLL_CLK_SSI2_IPG 148
-#define IMX6SLL_CLK_SSI3 149
-#define IMX6SLL_CLK_SSI3_IPG 150
-#define IMX6SLL_CLK_UART1_IPG 151
-#define IMX6SLL_CLK_UART1_SERIAL 152
-
-/* CCGR 6 */
-#define IMX6SLL_CLK_USBOH3 153
-#define IMX6SLL_CLK_USDHC1 154
-#define IMX6SLL_CLK_USDHC2 155
-#define IMX6SLL_CLK_USDHC3 156
-
-#define IMX6SLL_CLK_IPP_DI0 157
-#define IMX6SLL_CLK_IPP_DI1 158
-#define IMX6SLL_CLK_LDB_DI0_SEL 159
-#define IMX6SLL_CLK_LDB_DI0_DIV_3_5 160
-#define IMX6SLL_CLK_LDB_DI0_DIV_7 161
-#define IMX6SLL_CLK_LDB_DI0_DIV_SEL 162
-#define IMX6SLL_CLK_LDB_DI0 163
-#define IMX6SLL_CLK_LDB_DI1_SEL 164
-#define IMX6SLL_CLK_LDB_DI1_DIV_3_5 165
-#define IMX6SLL_CLK_LDB_DI1_DIV_7 166
-#define IMX6SLL_CLK_LDB_DI1_DIV_SEL 167
-#define IMX6SLL_CLK_LDB_DI1 168
-#define IMX6SLL_CLK_EXTERN_AUDIO_SEL 169
-#define IMX6SLL_CLK_EXTERN_AUDIO_PRED 170
-#define IMX6SLL_CLK_EXTERN_AUDIO_PODF 171
-#define IMX6SLL_CLK_EXTERN_AUDIO 172
-
-#define IMX6SLL_CLK_END 173
-
-#endif /* __DT_BINDINGS_CLOCK_IMX6SLL_H */
diff --git a/include/dt-bindings/clock/imx6sx-clock.h b/include/dt-bindings/clock/imx6sx-clock.h
deleted file mode 100644
index 36f0324..0000000
--- a/include/dt-bindings/clock/imx6sx-clock.h
+++ /dev/null
@@ -1,280 +0,0 @@
-/*
- * Copyright (C) 2014 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-#ifndef __DT_BINDINGS_CLOCK_IMX6SX_H
-#define __DT_BINDINGS_CLOCK_IMX6SX_H
-
-#define IMX6SX_CLK_DUMMY 0
-#define IMX6SX_CLK_CKIL 1
-#define IMX6SX_CLK_CKIH 2
-#define IMX6SX_CLK_OSC 3
-#define IMX6SX_CLK_PLL1_SYS 4
-#define IMX6SX_CLK_PLL2_BUS 5
-#define IMX6SX_CLK_PLL3_USB_OTG 6
-#define IMX6SX_CLK_PLL4_AUDIO 7
-#define IMX6SX_CLK_PLL5_VIDEO 8
-#define IMX6SX_CLK_PLL6_ENET 9
-#define IMX6SX_CLK_PLL7_USB_HOST 10
-#define IMX6SX_CLK_USBPHY1 11
-#define IMX6SX_CLK_USBPHY2 12
-#define IMX6SX_CLK_USBPHY1_GATE 13
-#define IMX6SX_CLK_USBPHY2_GATE 14
-#define IMX6SX_CLK_PCIE_REF 15
-#define IMX6SX_CLK_PCIE_REF_125M 16
-#define IMX6SX_CLK_ENET_REF 17
-#define IMX6SX_CLK_PLL2_PFD0 18
-#define IMX6SX_CLK_PLL2_PFD1 19
-#define IMX6SX_CLK_PLL2_PFD2 20
-#define IMX6SX_CLK_PLL2_PFD3 21
-#define IMX6SX_CLK_PLL3_PFD0 22
-#define IMX6SX_CLK_PLL3_PFD1 23
-#define IMX6SX_CLK_PLL3_PFD2 24
-#define IMX6SX_CLK_PLL3_PFD3 25
-#define IMX6SX_CLK_PLL2_198M 26
-#define IMX6SX_CLK_PLL3_120M 27
-#define IMX6SX_CLK_PLL3_80M 28
-#define IMX6SX_CLK_PLL3_60M 29
-#define IMX6SX_CLK_TWD 30
-#define IMX6SX_CLK_PLL4_POST_DIV 31
-#define IMX6SX_CLK_PLL4_AUDIO_DIV 32
-#define IMX6SX_CLK_PLL5_POST_DIV 33
-#define IMX6SX_CLK_PLL5_VIDEO_DIV 34
-#define IMX6SX_CLK_STEP 35
-#define IMX6SX_CLK_PLL1_SW 36
-#define IMX6SX_CLK_OCRAM_SEL 37
-#define IMX6SX_CLK_PERIPH_PRE 38
-#define IMX6SX_CLK_PERIPH2_PRE 39
-#define IMX6SX_CLK_PERIPH_CLK2_SEL 40
-#define IMX6SX_CLK_PERIPH2_CLK2_SEL 41
-#define IMX6SX_CLK_PCIE_AXI_SEL 42
-#define IMX6SX_CLK_GPU_AXI_SEL 43
-#define IMX6SX_CLK_GPU_CORE_SEL 44
-#define IMX6SX_CLK_EIM_SLOW_SEL 45
-#define IMX6SX_CLK_USDHC1_SEL 46
-#define IMX6SX_CLK_USDHC2_SEL 47
-#define IMX6SX_CLK_USDHC3_SEL 48
-#define IMX6SX_CLK_USDHC4_SEL 49
-#define IMX6SX_CLK_SSI1_SEL 50
-#define IMX6SX_CLK_SSI2_SEL 51
-#define IMX6SX_CLK_SSI3_SEL 52
-#define IMX6SX_CLK_QSPI1_SEL 53
-#define IMX6SX_CLK_PERCLK_SEL 54
-#define IMX6SX_CLK_VID_SEL 55
-#define IMX6SX_CLK_ESAI_SEL 56
-#define IMX6SX_CLK_LDB_DI0_DIV_SEL 57
-#define IMX6SX_CLK_LDB_DI1_DIV_SEL 58
-#define IMX6SX_CLK_CAN_SEL 59
-#define IMX6SX_CLK_UART_SEL 60
-#define IMX6SX_CLK_QSPI2_SEL 61
-#define IMX6SX_CLK_LDB_DI1_SEL 62
-#define IMX6SX_CLK_LDB_DI0_SEL 63
-#define IMX6SX_CLK_SPDIF_SEL 64
-#define IMX6SX_CLK_AUDIO_SEL 65
-#define IMX6SX_CLK_ENET_PRE_SEL 66
-#define IMX6SX_CLK_ENET_SEL 67
-#define IMX6SX_CLK_M4_PRE_SEL 68
-#define IMX6SX_CLK_M4_SEL 69
-#define IMX6SX_CLK_ECSPI_SEL 70
-#define IMX6SX_CLK_LCDIF1_PRE_SEL 71
-#define IMX6SX_CLK_LCDIF2_PRE_SEL 72
-#define IMX6SX_CLK_LCDIF1_SEL 73
-#define IMX6SX_CLK_LCDIF2_SEL 74
-#define IMX6SX_CLK_DISPLAY_SEL 75
-#define IMX6SX_CLK_CSI_SEL 76
-#define IMX6SX_CLK_CKO1_SEL 77
-#define IMX6SX_CLK_CKO2_SEL 78
-#define IMX6SX_CLK_CKO 79
-#define IMX6SX_CLK_PERIPH_CLK2 80
-#define IMX6SX_CLK_PERIPH2_CLK2 81
-#define IMX6SX_CLK_IPG 82
-#define IMX6SX_CLK_GPU_CORE_PODF 83
-#define IMX6SX_CLK_GPU_AXI_PODF 84
-#define IMX6SX_CLK_LCDIF1_PODF 85
-#define IMX6SX_CLK_QSPI1_PODF 86
-#define IMX6SX_CLK_EIM_SLOW_PODF 87
-#define IMX6SX_CLK_LCDIF2_PODF 88
-#define IMX6SX_CLK_PERCLK 89
-#define IMX6SX_CLK_VID_PODF 90
-#define IMX6SX_CLK_CAN_PODF 91
-#define IMX6SX_CLK_USDHC1_PODF 92
-#define IMX6SX_CLK_USDHC2_PODF 93
-#define IMX6SX_CLK_USDHC3_PODF 94
-#define IMX6SX_CLK_USDHC4_PODF 95
-#define IMX6SX_CLK_UART_PODF 96
-#define IMX6SX_CLK_ESAI_PRED 97
-#define IMX6SX_CLK_ESAI_PODF 98
-#define IMX6SX_CLK_SSI3_PRED 99
-#define IMX6SX_CLK_SSI3_PODF 100
-#define IMX6SX_CLK_SSI1_PRED 101
-#define IMX6SX_CLK_SSI1_PODF 102
-#define IMX6SX_CLK_QSPI2_PRED 103
-#define IMX6SX_CLK_QSPI2_PODF 104
-#define IMX6SX_CLK_SSI2_PRED 105
-#define IMX6SX_CLK_SSI2_PODF 106
-#define IMX6SX_CLK_SPDIF_PRED 107
-#define IMX6SX_CLK_SPDIF_PODF 108
-#define IMX6SX_CLK_AUDIO_PRED 109
-#define IMX6SX_CLK_AUDIO_PODF 110
-#define IMX6SX_CLK_ENET_PODF 111
-#define IMX6SX_CLK_M4_PODF 112
-#define IMX6SX_CLK_ECSPI_PODF 113
-#define IMX6SX_CLK_LCDIF1_PRED 114
-#define IMX6SX_CLK_LCDIF2_PRED 115
-#define IMX6SX_CLK_DISPLAY_PODF 116
-#define IMX6SX_CLK_CSI_PODF 117
-#define IMX6SX_CLK_LDB_DI0_DIV_3_5 118
-#define IMX6SX_CLK_LDB_DI0_DIV_7 119
-#define IMX6SX_CLK_LDB_DI1_DIV_3_5 120
-#define IMX6SX_CLK_LDB_DI1_DIV_7 121
-#define IMX6SX_CLK_CKO1_PODF 122
-#define IMX6SX_CLK_CKO2_PODF 123
-#define IMX6SX_CLK_PERIPH 124
-#define IMX6SX_CLK_PERIPH2 125
-#define IMX6SX_CLK_OCRAM 126
-#define IMX6SX_CLK_AHB 127
-#define IMX6SX_CLK_MMDC_PODF 128
-#define IMX6SX_CLK_ARM 129
-#define IMX6SX_CLK_AIPS_TZ1 130
-#define IMX6SX_CLK_AIPS_TZ2 131
-#define IMX6SX_CLK_APBH_DMA 132
-#define IMX6SX_CLK_ASRC_GATE 133
-#define IMX6SX_CLK_CAAM_MEM 134
-#define IMX6SX_CLK_CAAM_ACLK 135
-#define IMX6SX_CLK_CAAM_IPG 136
-#define IMX6SX_CLK_CAN1_IPG 137
-#define IMX6SX_CLK_CAN1_SERIAL 138
-#define IMX6SX_CLK_CAN2_IPG 139
-#define IMX6SX_CLK_CAN2_SERIAL 140
-#define IMX6SX_CLK_CPU_DEBUG 141
-#define IMX6SX_CLK_DCIC1 142
-#define IMX6SX_CLK_DCIC2 143
-#define IMX6SX_CLK_AIPS_TZ3 144
-#define IMX6SX_CLK_ECSPI1 145
-#define IMX6SX_CLK_ECSPI2 146
-#define IMX6SX_CLK_ECSPI3 147
-#define IMX6SX_CLK_ECSPI4 148
-#define IMX6SX_CLK_ECSPI5 149
-#define IMX6SX_CLK_EPIT1 150
-#define IMX6SX_CLK_EPIT2 151
-#define IMX6SX_CLK_ESAI_EXTAL 152
-#define IMX6SX_CLK_WAKEUP 153
-#define IMX6SX_CLK_GPT_BUS 154
-#define IMX6SX_CLK_GPT_SERIAL 155
-#define IMX6SX_CLK_GPU 156
-#define IMX6SX_CLK_OCRAM_S 157
-#define IMX6SX_CLK_CANFD 158
-#define IMX6SX_CLK_CSI 159
-#define IMX6SX_CLK_I2C1 160
-#define IMX6SX_CLK_I2C2 161
-#define IMX6SX_CLK_I2C3 162
-#define IMX6SX_CLK_OCOTP 163
-#define IMX6SX_CLK_IOMUXC 164
-#define IMX6SX_CLK_IPMUX1 165
-#define IMX6SX_CLK_IPMUX2 166
-#define IMX6SX_CLK_IPMUX3 167
-#define IMX6SX_CLK_TZASC1 168
-#define IMX6SX_CLK_LCDIF_APB 169
-#define IMX6SX_CLK_PXP_AXI 170
-#define IMX6SX_CLK_M4 171
-#define IMX6SX_CLK_ENET 172
-#define IMX6SX_CLK_DISPLAY_AXI 173
-#define IMX6SX_CLK_LCDIF2_PIX 174
-#define IMX6SX_CLK_LCDIF1_PIX 175
-#define IMX6SX_CLK_LDB_DI0 176
-#define IMX6SX_CLK_QSPI1 177
-#define IMX6SX_CLK_MLB 178
-#define IMX6SX_CLK_MMDC_P0_FAST 179
-#define IMX6SX_CLK_MMDC_P0_IPG 180
-#define IMX6SX_CLK_AXI 181
-#define IMX6SX_CLK_PCIE_AXI 182
-#define IMX6SX_CLK_QSPI2 183
-#define IMX6SX_CLK_PER1_BCH 184
-#define IMX6SX_CLK_PER2_MAIN 185
-#define IMX6SX_CLK_PWM1 186
-#define IMX6SX_CLK_PWM2 187
-#define IMX6SX_CLK_PWM3 188
-#define IMX6SX_CLK_PWM4 189
-#define IMX6SX_CLK_GPMI_BCH_APB 190
-#define IMX6SX_CLK_GPMI_BCH 191
-#define IMX6SX_CLK_GPMI_IO 192
-#define IMX6SX_CLK_GPMI_APB 193
-#define IMX6SX_CLK_ROM 194
-#define IMX6SX_CLK_SDMA 195
-#define IMX6SX_CLK_SPBA 196
-#define IMX6SX_CLK_SPDIF 197
-#define IMX6SX_CLK_SSI1_IPG 198
-#define IMX6SX_CLK_SSI2_IPG 199
-#define IMX6SX_CLK_SSI3_IPG 200
-#define IMX6SX_CLK_SSI1 201
-#define IMX6SX_CLK_SSI2 202
-#define IMX6SX_CLK_SSI3 203
-#define IMX6SX_CLK_UART_IPG 204
-#define IMX6SX_CLK_UART_SERIAL 205
-#define IMX6SX_CLK_SAI1 206
-#define IMX6SX_CLK_SAI2 207
-#define IMX6SX_CLK_USBOH3 208
-#define IMX6SX_CLK_USDHC1 209
-#define IMX6SX_CLK_USDHC2 210
-#define IMX6SX_CLK_USDHC3 211
-#define IMX6SX_CLK_USDHC4 212
-#define IMX6SX_CLK_EIM_SLOW 213
-#define IMX6SX_CLK_PWM8 214
-#define IMX6SX_CLK_VADC 215
-#define IMX6SX_CLK_GIS 216
-#define IMX6SX_CLK_I2C4 217
-#define IMX6SX_CLK_PWM5 218
-#define IMX6SX_CLK_PWM6 219
-#define IMX6SX_CLK_PWM7 220
-#define IMX6SX_CLK_CKO1 221
-#define IMX6SX_CLK_CKO2 222
-#define IMX6SX_CLK_IPP_DI0 223
-#define IMX6SX_CLK_IPP_DI1 224
-#define IMX6SX_CLK_ENET_AHB 225
-#define IMX6SX_CLK_OCRAM_PODF 226
-#define IMX6SX_CLK_GPT_3M 227
-#define IMX6SX_CLK_ENET_PTP 228
-#define IMX6SX_CLK_ENET_PTP_REF 229
-#define IMX6SX_CLK_ENET2_REF 230
-#define IMX6SX_CLK_ENET2_REF_125M 231
-#define IMX6SX_CLK_AUDIO 232
-#define IMX6SX_CLK_LVDS1_SEL 233
-#define IMX6SX_CLK_LVDS1_OUT 234
-#define IMX6SX_CLK_ASRC_IPG 235
-#define IMX6SX_CLK_ASRC_MEM 236
-#define IMX6SX_CLK_SAI1_IPG 237
-#define IMX6SX_CLK_SAI2_IPG 238
-#define IMX6SX_CLK_ESAI_IPG 239
-#define IMX6SX_CLK_ESAI_MEM 240
-#define IMX6SX_CLK_LVDS1_IN 241
-#define IMX6SX_CLK_ANACLK1 242
-#define IMX6SX_PLL1_BYPASS_SRC 243
-#define IMX6SX_PLL2_BYPASS_SRC 244
-#define IMX6SX_PLL3_BYPASS_SRC 245
-#define IMX6SX_PLL4_BYPASS_SRC 246
-#define IMX6SX_PLL5_BYPASS_SRC 247
-#define IMX6SX_PLL6_BYPASS_SRC 248
-#define IMX6SX_PLL7_BYPASS_SRC 249
-#define IMX6SX_CLK_PLL1 250
-#define IMX6SX_CLK_PLL2 251
-#define IMX6SX_CLK_PLL3 252
-#define IMX6SX_CLK_PLL4 253
-#define IMX6SX_CLK_PLL5 254
-#define IMX6SX_CLK_PLL6 255
-#define IMX6SX_CLK_PLL7 256
-#define IMX6SX_PLL1_BYPASS 257
-#define IMX6SX_PLL2_BYPASS 258
-#define IMX6SX_PLL3_BYPASS 259
-#define IMX6SX_PLL4_BYPASS 260
-#define IMX6SX_PLL5_BYPASS 261
-#define IMX6SX_PLL6_BYPASS 262
-#define IMX6SX_PLL7_BYPASS 263
-#define IMX6SX_CLK_SPDIF_GCLK 264
-#define IMX6SX_CLK_CLK_END 265
-
-#endif /* __DT_BINDINGS_CLOCK_IMX6SX_H */
diff --git a/include/dt-bindings/clock/imx6ul-clock.h b/include/dt-bindings/clock/imx6ul-clock.h
deleted file mode 100644
index 7909433..0000000
--- a/include/dt-bindings/clock/imx6ul-clock.h
+++ /dev/null
@@ -1,262 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (C) 2015 Freescale Semiconductor, Inc.
- */
-
-#ifndef __DT_BINDINGS_CLOCK_IMX6UL_H
-#define __DT_BINDINGS_CLOCK_IMX6UL_H
-
-#define IMX6UL_CLK_DUMMY 0
-#define IMX6UL_CLK_CKIL 1
-#define IMX6UL_CLK_CKIH 2
-#define IMX6UL_CLK_OSC 3
-#define IMX6UL_PLL1_BYPASS_SRC 4
-#define IMX6UL_PLL2_BYPASS_SRC 5
-#define IMX6UL_PLL3_BYPASS_SRC 6
-#define IMX6UL_PLL4_BYPASS_SRC 7
-#define IMX6UL_PLL5_BYPASS_SRC 8
-#define IMX6UL_PLL6_BYPASS_SRC 9
-#define IMX6UL_PLL7_BYPASS_SRC 10
-#define IMX6UL_CLK_PLL1 11
-#define IMX6UL_CLK_PLL2 12
-#define IMX6UL_CLK_PLL3 13
-#define IMX6UL_CLK_PLL4 14
-#define IMX6UL_CLK_PLL5 15
-#define IMX6UL_CLK_PLL6 16
-#define IMX6UL_CLK_PLL7 17
-#define IMX6UL_PLL1_BYPASS 18
-#define IMX6UL_PLL2_BYPASS 19
-#define IMX6UL_PLL3_BYPASS 20
-#define IMX6UL_PLL4_BYPASS 21
-#define IMX6UL_PLL5_BYPASS 22
-#define IMX6UL_PLL6_BYPASS 23
-#define IMX6UL_PLL7_BYPASS 24
-#define IMX6UL_CLK_PLL1_SYS 25
-#define IMX6UL_CLK_PLL2_BUS 26
-#define IMX6UL_CLK_PLL3_USB_OTG 27
-#define IMX6UL_CLK_PLL4_AUDIO 28
-#define IMX6UL_CLK_PLL5_VIDEO 29
-#define IMX6UL_CLK_PLL6_ENET 30
-#define IMX6UL_CLK_PLL7_USB_HOST 31
-#define IMX6UL_CLK_USBPHY1 32
-#define IMX6UL_CLK_USBPHY2 33
-#define IMX6UL_CLK_USBPHY1_GATE 34
-#define IMX6UL_CLK_USBPHY2_GATE 35
-#define IMX6UL_CLK_PLL2_PFD0 36
-#define IMX6UL_CLK_PLL2_PFD1 37
-#define IMX6UL_CLK_PLL2_PFD2 38
-#define IMX6UL_CLK_PLL2_PFD3 39
-#define IMX6UL_CLK_PLL3_PFD0 40
-#define IMX6UL_CLK_PLL3_PFD1 41
-#define IMX6UL_CLK_PLL3_PFD2 42
-#define IMX6UL_CLK_PLL3_PFD3 43
-#define IMX6UL_CLK_ENET_REF 44
-#define IMX6UL_CLK_ENET2_REF 45
-#define IMX6UL_CLK_ENET2_REF_125M 46
-#define IMX6UL_CLK_ENET_PTP_REF 47
-#define IMX6UL_CLK_ENET_PTP 48
-#define IMX6UL_CLK_PLL4_POST_DIV 49
-#define IMX6UL_CLK_PLL4_AUDIO_DIV 50
-#define IMX6UL_CLK_PLL5_POST_DIV 51
-#define IMX6UL_CLK_PLL5_VIDEO_DIV 52
-#define IMX6UL_CLK_PLL2_198M 53
-#define IMX6UL_CLK_PLL3_80M 54
-#define IMX6UL_CLK_PLL3_60M 55
-#define IMX6UL_CLK_STEP 56
-#define IMX6UL_CLK_PLL1_SW 57
-#define IMX6UL_CLK_AXI_ALT_SEL 58
-#define IMX6UL_CLK_AXI_SEL 59
-#define IMX6UL_CLK_PERIPH_PRE 60
-#define IMX6UL_CLK_PERIPH2_PRE 61
-#define IMX6UL_CLK_PERIPH_CLK2_SEL 62
-#define IMX6UL_CLK_PERIPH2_CLK2_SEL 63
-#define IMX6UL_CLK_USDHC1_SEL 64
-#define IMX6UL_CLK_USDHC2_SEL 65
-#define IMX6UL_CLK_BCH_SEL 66
-#define IMX6UL_CLK_GPMI_SEL 67
-#define IMX6UL_CLK_EIM_SLOW_SEL 68
-#define IMX6UL_CLK_SPDIF_SEL 69
-#define IMX6UL_CLK_SAI1_SEL 70
-#define IMX6UL_CLK_SAI2_SEL 71
-#define IMX6UL_CLK_SAI3_SEL 72
-#define IMX6UL_CLK_LCDIF_PRE_SEL 73
-#define IMX6UL_CLK_SIM_PRE_SEL 74
-#define IMX6UL_CLK_LDB_DI0_SEL 75
-#define IMX6UL_CLK_LDB_DI1_SEL 76
-#define IMX6UL_CLK_ENFC_SEL 77
-#define IMX6UL_CLK_CAN_SEL 78
-#define IMX6UL_CLK_ECSPI_SEL 79
-#define IMX6UL_CLK_UART_SEL 80
-#define IMX6UL_CLK_QSPI1_SEL 81
-#define IMX6UL_CLK_PERCLK_SEL 82
-#define IMX6UL_CLK_LCDIF_SEL 83
-#define IMX6UL_CLK_SIM_SEL 84
-#define IMX6UL_CLK_PERIPH 85
-#define IMX6UL_CLK_PERIPH2 86
-#define IMX6UL_CLK_LDB_DI0_DIV_3_5 87
-#define IMX6UL_CLK_LDB_DI0_DIV_7 88
-#define IMX6UL_CLK_LDB_DI1_DIV_3_5 89
-#define IMX6UL_CLK_LDB_DI1_DIV_7 90
-#define IMX6UL_CLK_LDB_DI0_DIV_SEL 91
-#define IMX6UL_CLK_LDB_DI1_DIV_SEL 92
-#define IMX6UL_CLK_ARM 93
-#define IMX6UL_CLK_PERIPH_CLK2 94
-#define IMX6UL_CLK_PERIPH2_CLK2 95
-#define IMX6UL_CLK_AHB 96
-#define IMX6UL_CLK_MMDC_PODF 97
-#define IMX6UL_CLK_AXI_PODF 98
-#define IMX6UL_CLK_PERCLK 99
-#define IMX6UL_CLK_IPG 100
-#define IMX6UL_CLK_USDHC1_PODF 101
-#define IMX6UL_CLK_USDHC2_PODF 102
-#define IMX6UL_CLK_BCH_PODF 103
-#define IMX6UL_CLK_GPMI_PODF 104
-#define IMX6UL_CLK_EIM_SLOW_PODF 105
-#define IMX6UL_CLK_SPDIF_PRED 106
-#define IMX6UL_CLK_SPDIF_PODF 107
-#define IMX6UL_CLK_SAI1_PRED 108
-#define IMX6UL_CLK_SAI1_PODF 109
-#define IMX6UL_CLK_SAI2_PRED 110
-#define IMX6UL_CLK_SAI2_PODF 111
-#define IMX6UL_CLK_SAI3_PRED 112
-#define IMX6UL_CLK_SAI3_PODF 113
-#define IMX6UL_CLK_LCDIF_PRED 114
-#define IMX6UL_CLK_LCDIF_PODF 115
-#define IMX6UL_CLK_SIM_PODF 116
-#define IMX6UL_CLK_QSPI1_PDOF 117
-#define IMX6UL_CLK_ENFC_PRED 118
-#define IMX6UL_CLK_ENFC_PODF 119
-#define IMX6UL_CLK_CAN_PODF 120
-#define IMX6UL_CLK_ECSPI_PODF 121
-#define IMX6UL_CLK_UART_PODF 122
-#define IMX6UL_CLK_ADC1 123
-#define IMX6UL_CLK_ADC2 124
-#define IMX6UL_CLK_AIPSTZ1 125
-#define IMX6UL_CLK_AIPSTZ2 126
-#define IMX6UL_CLK_AIPSTZ3 127
-#define IMX6UL_CLK_APBHDMA 128
-#define IMX6UL_CLK_ASRC_IPG 129
-#define IMX6UL_CLK_ASRC_MEM 130
-#define IMX6UL_CLK_GPMI_BCH_APB 131
-#define IMX6UL_CLK_GPMI_BCH 132
-#define IMX6UL_CLK_GPMI_IO 133
-#define IMX6UL_CLK_GPMI_APB 134
-#define IMX6UL_CLK_CAAM_MEM 135
-#define IMX6UL_CLK_CAAM_ACLK 136
-#define IMX6UL_CLK_CAAM_IPG 137
-#define IMX6UL_CLK_CSI 138
-#define IMX6UL_CLK_ECSPI1 139
-#define IMX6UL_CLK_ECSPI2 140
-#define IMX6UL_CLK_ECSPI3 141
-#define IMX6UL_CLK_ECSPI4 142
-#define IMX6UL_CLK_EIM 143
-#define IMX6UL_CLK_ENET 144
-#define IMX6UL_CLK_ENET_AHB 145
-#define IMX6UL_CLK_EPIT1 146
-#define IMX6UL_CLK_EPIT2 147
-#define IMX6UL_CLK_CAN1_IPG 148
-#define IMX6UL_CLK_CAN1_SERIAL 149
-#define IMX6UL_CLK_CAN2_IPG 150
-#define IMX6UL_CLK_CAN2_SERIAL 151
-#define IMX6UL_CLK_GPT1_BUS 152
-#define IMX6UL_CLK_GPT1_SERIAL 153
-#define IMX6UL_CLK_GPT2_BUS 154
-#define IMX6UL_CLK_GPT2_SERIAL 155
-#define IMX6UL_CLK_I2C1 156
-#define IMX6UL_CLK_I2C2 157
-#define IMX6UL_CLK_I2C3 158
-#define IMX6UL_CLK_I2C4 159
-#define IMX6UL_CLK_IOMUXC 160
-#define IMX6UL_CLK_LCDIF_APB 161
-#define IMX6UL_CLK_LCDIF_PIX 162
-#define IMX6UL_CLK_MMDC_P0_FAST 163
-#define IMX6UL_CLK_MMDC_P0_IPG 164
-#define IMX6UL_CLK_OCOTP 165
-#define IMX6UL_CLK_OCRAM 166
-#define IMX6UL_CLK_PWM1 167
-#define IMX6UL_CLK_PWM2 168
-#define IMX6UL_CLK_PWM3 169
-#define IMX6UL_CLK_PWM4 170
-#define IMX6UL_CLK_PWM5 171
-#define IMX6UL_CLK_PWM6 172
-#define IMX6UL_CLK_PWM7 173
-#define IMX6UL_CLK_PWM8 174
-#define IMX6UL_CLK_PXP 175
-#define IMX6UL_CLK_QSPI 176
-#define IMX6UL_CLK_ROM 177
-#define IMX6UL_CLK_SAI1 178
-#define IMX6UL_CLK_SAI1_IPG 179
-#define IMX6UL_CLK_SAI2 180
-#define IMX6UL_CLK_SAI2_IPG 181
-#define IMX6UL_CLK_SAI3 182
-#define IMX6UL_CLK_SAI3_IPG 183
-#define IMX6UL_CLK_SDMA 184
-#define IMX6UL_CLK_SIM 185
-#define IMX6UL_CLK_SIM_S 186
-#define IMX6UL_CLK_SPBA 187
-#define IMX6UL_CLK_SPDIF 188
-#define IMX6UL_CLK_UART1_IPG 189
-#define IMX6UL_CLK_UART1_SERIAL 190
-#define IMX6UL_CLK_UART2_IPG 191
-#define IMX6UL_CLK_UART2_SERIAL 192
-#define IMX6UL_CLK_UART3_IPG 193
-#define IMX6UL_CLK_UART3_SERIAL 194
-#define IMX6UL_CLK_UART4_IPG 195
-#define IMX6UL_CLK_UART4_SERIAL 196
-#define IMX6UL_CLK_UART5_IPG 197
-#define IMX6UL_CLK_UART5_SERIAL 198
-#define IMX6UL_CLK_UART6_IPG 199
-#define IMX6UL_CLK_UART6_SERIAL 200
-#define IMX6UL_CLK_UART7_IPG 201
-#define IMX6UL_CLK_UART7_SERIAL 202
-#define IMX6UL_CLK_UART8_IPG 203
-#define IMX6UL_CLK_UART8_SERIAL 204
-#define IMX6UL_CLK_USBOH3 205
-#define IMX6UL_CLK_USDHC1 206
-#define IMX6UL_CLK_USDHC2 207
-#define IMX6UL_CLK_WDOG1 208
-#define IMX6UL_CLK_WDOG2 209
-#define IMX6UL_CLK_WDOG3 210
-#define IMX6UL_CLK_LDB_DI0 211
-#define IMX6UL_CLK_AXI 212
-#define IMX6UL_CLK_SPDIF_GCLK 213
-#define IMX6UL_CLK_GPT_3M 214
-#define IMX6UL_CLK_SIM2 215
-#define IMX6UL_CLK_SIM1 216
-#define IMX6UL_CLK_IPP_DI0 217
-#define IMX6UL_CLK_IPP_DI1 218
-#define IMX6UL_CA7_SECONDARY_SEL 219
-#define IMX6UL_CLK_PER_BCH 220
-#define IMX6UL_CLK_CSI_SEL 221
-#define IMX6UL_CLK_CSI_PODF 222
-#define IMX6UL_CLK_PLL3_120M 223
-#define IMX6UL_CLK_KPP 224
-#define IMX6ULL_CLK_ESAI_PRED 225
-#define IMX6ULL_CLK_ESAI_PODF 226
-#define IMX6ULL_CLK_ESAI_EXTAL 227
-#define IMX6ULL_CLK_ESAI_MEM 228
-#define IMX6ULL_CLK_ESAI_IPG 229
-#define IMX6ULL_CLK_DCP_CLK 230
-#define IMX6ULL_CLK_EPDC_PRE_SEL 231
-#define IMX6ULL_CLK_EPDC_SEL 232
-#define IMX6ULL_CLK_EPDC_PODF 233
-#define IMX6ULL_CLK_EPDC_ACLK 234
-#define IMX6ULL_CLK_EPDC_PIX 235
-#define IMX6ULL_CLK_ESAI_SEL 236
-#define IMX6UL_CLK_CKO1_SEL 237
-#define IMX6UL_CLK_CKO1_PODF 238
-#define IMX6UL_CLK_CKO1 239
-#define IMX6UL_CLK_CKO2_SEL 240
-#define IMX6UL_CLK_CKO2_PODF 241
-#define IMX6UL_CLK_CKO2 242
-#define IMX6UL_CLK_CKO 243
-#define IMX6UL_CLK_GPIO1 244
-#define IMX6UL_CLK_GPIO2 245
-#define IMX6UL_CLK_GPIO3 246
-#define IMX6UL_CLK_GPIO4 247
-#define IMX6UL_CLK_GPIO5 248
-#define IMX6UL_CLK_MMDC_P1_IPG 249
-
-#define IMX6UL_CLK_END 250
-
-#endif /* __DT_BINDINGS_CLOCK_IMX6UL_H */
diff --git a/include/dt-bindings/clock/imx7d-clock.h b/include/dt-bindings/clock/imx7d-clock.h
deleted file mode 100644
index b2325d3..0000000
--- a/include/dt-bindings/clock/imx7d-clock.h
+++ /dev/null
@@ -1,459 +0,0 @@
-/*
- * Copyright (C) 2014-2015 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-#ifndef __DT_BINDINGS_CLOCK_IMX7D_H
-#define __DT_BINDINGS_CLOCK_IMX7D_H
-
-#define IMX7D_OSC_24M_CLK 0
-#define IMX7D_PLL_ARM_MAIN 1
-#define IMX7D_PLL_ARM_MAIN_CLK 2
-#define IMX7D_PLL_ARM_MAIN_SRC 3
-#define IMX7D_PLL_ARM_MAIN_BYPASS 4
-#define IMX7D_PLL_SYS_MAIN 5
-#define IMX7D_PLL_SYS_MAIN_CLK 6
-#define IMX7D_PLL_SYS_MAIN_SRC 7
-#define IMX7D_PLL_SYS_MAIN_BYPASS 8
-#define IMX7D_PLL_SYS_MAIN_480M 9
-#define IMX7D_PLL_SYS_MAIN_240M 10
-#define IMX7D_PLL_SYS_MAIN_120M 11
-#define IMX7D_PLL_SYS_MAIN_480M_CLK 12
-#define IMX7D_PLL_SYS_MAIN_240M_CLK 13
-#define IMX7D_PLL_SYS_MAIN_120M_CLK 14
-#define IMX7D_PLL_SYS_PFD0_392M_CLK 15
-#define IMX7D_PLL_SYS_PFD0_196M 16
-#define IMX7D_PLL_SYS_PFD0_196M_CLK 17
-#define IMX7D_PLL_SYS_PFD1_332M_CLK 18
-#define IMX7D_PLL_SYS_PFD1_166M 19
-#define IMX7D_PLL_SYS_PFD1_166M_CLK 20
-#define IMX7D_PLL_SYS_PFD2_270M_CLK 21
-#define IMX7D_PLL_SYS_PFD2_135M 22
-#define IMX7D_PLL_SYS_PFD2_135M_CLK 23
-#define IMX7D_PLL_SYS_PFD3_CLK 24
-#define IMX7D_PLL_SYS_PFD4_CLK 25
-#define IMX7D_PLL_SYS_PFD5_CLK 26
-#define IMX7D_PLL_SYS_PFD6_CLK 27
-#define IMX7D_PLL_SYS_PFD7_CLK 28
-#define IMX7D_PLL_ENET_MAIN 29
-#define IMX7D_PLL_ENET_MAIN_CLK 30
-#define IMX7D_PLL_ENET_MAIN_SRC 31
-#define IMX7D_PLL_ENET_MAIN_BYPASS 32
-#define IMX7D_PLL_ENET_MAIN_500M 33
-#define IMX7D_PLL_ENET_MAIN_250M 34
-#define IMX7D_PLL_ENET_MAIN_125M 35
-#define IMX7D_PLL_ENET_MAIN_100M 36
-#define IMX7D_PLL_ENET_MAIN_50M 37
-#define IMX7D_PLL_ENET_MAIN_40M 38
-#define IMX7D_PLL_ENET_MAIN_25M 39
-#define IMX7D_PLL_ENET_MAIN_500M_CLK 40
-#define IMX7D_PLL_ENET_MAIN_250M_CLK 41
-#define IMX7D_PLL_ENET_MAIN_125M_CLK 42
-#define IMX7D_PLL_ENET_MAIN_100M_CLK 43
-#define IMX7D_PLL_ENET_MAIN_50M_CLK 44
-#define IMX7D_PLL_ENET_MAIN_40M_CLK 45
-#define IMX7D_PLL_ENET_MAIN_25M_CLK 46
-#define IMX7D_PLL_DRAM_MAIN 47
-#define IMX7D_PLL_DRAM_MAIN_CLK 48
-#define IMX7D_PLL_DRAM_MAIN_SRC 49
-#define IMX7D_PLL_DRAM_MAIN_BYPASS 50
-#define IMX7D_PLL_DRAM_MAIN_533M 51
-#define IMX7D_PLL_DRAM_MAIN_533M_CLK 52
-#define IMX7D_PLL_AUDIO_MAIN 53
-#define IMX7D_PLL_AUDIO_MAIN_CLK 54
-#define IMX7D_PLL_AUDIO_MAIN_SRC 55
-#define IMX7D_PLL_AUDIO_MAIN_BYPASS 56
-#define IMX7D_PLL_VIDEO_MAIN_CLK 57
-#define IMX7D_PLL_VIDEO_MAIN 58
-#define IMX7D_PLL_VIDEO_MAIN_SRC 59
-#define IMX7D_PLL_VIDEO_MAIN_BYPASS 60
-#define IMX7D_USB_MAIN_480M_CLK 61
-#define IMX7D_ARM_A7_ROOT_CLK 62
-#define IMX7D_ARM_A7_ROOT_SRC 63
-#define IMX7D_ARM_A7_ROOT_CG 64
-#define IMX7D_ARM_A7_ROOT_DIV 65
-#define IMX7D_ARM_M4_ROOT_CLK 66
-#define IMX7D_ARM_M4_ROOT_SRC 67
-#define IMX7D_ARM_M4_ROOT_CG 68
-#define IMX7D_ARM_M4_ROOT_DIV 69
-#define IMX7D_ARM_M0_ROOT_CLK 70 /* unused */
-#define IMX7D_ARM_M0_ROOT_SRC 71 /* unused */
-#define IMX7D_ARM_M0_ROOT_CG 72 /* unused */
-#define IMX7D_ARM_M0_ROOT_DIV 73 /* unused */
-#define IMX7D_MAIN_AXI_ROOT_CLK 74
-#define IMX7D_MAIN_AXI_ROOT_SRC 75
-#define IMX7D_MAIN_AXI_ROOT_CG 76
-#define IMX7D_MAIN_AXI_ROOT_DIV 77
-#define IMX7D_DISP_AXI_ROOT_CLK 78
-#define IMX7D_DISP_AXI_ROOT_SRC 79
-#define IMX7D_DISP_AXI_ROOT_CG 80
-#define IMX7D_DISP_AXI_ROOT_DIV 81
-#define IMX7D_ENET_AXI_ROOT_CLK 82
-#define IMX7D_ENET_AXI_ROOT_SRC 83
-#define IMX7D_ENET_AXI_ROOT_CG 84
-#define IMX7D_ENET_AXI_ROOT_DIV 85
-#define IMX7D_NAND_USDHC_BUS_ROOT_CLK 86
-#define IMX7D_NAND_USDHC_BUS_ROOT_SRC 87
-#define IMX7D_NAND_USDHC_BUS_ROOT_CG 88
-#define IMX7D_NAND_USDHC_BUS_ROOT_DIV 89
-#define IMX7D_AHB_CHANNEL_ROOT_CLK 90
-#define IMX7D_AHB_CHANNEL_ROOT_SRC 91
-#define IMX7D_AHB_CHANNEL_ROOT_CG 92
-#define IMX7D_AHB_CHANNEL_ROOT_DIV 93
-#define IMX7D_DRAM_PHYM_ROOT_CLK 94
-#define IMX7D_DRAM_PHYM_ROOT_SRC 95
-#define IMX7D_DRAM_PHYM_ROOT_CG 96
-#define IMX7D_DRAM_PHYM_ROOT_DIV 97
-#define IMX7D_DRAM_ROOT_CLK 98
-#define IMX7D_DRAM_ROOT_SRC 99
-#define IMX7D_DRAM_ROOT_CG 100
-#define IMX7D_DRAM_ROOT_DIV 101
-#define IMX7D_DRAM_PHYM_ALT_ROOT_CLK 102
-#define IMX7D_DRAM_PHYM_ALT_ROOT_SRC 103
-#define IMX7D_DRAM_PHYM_ALT_ROOT_CG 104
-#define IMX7D_DRAM_PHYM_ALT_ROOT_DIV 105
-#define IMX7D_DRAM_ALT_ROOT_CLK 106
-#define IMX7D_DRAM_ALT_ROOT_SRC 107
-#define IMX7D_DRAM_ALT_ROOT_CG 108
-#define IMX7D_DRAM_ALT_ROOT_DIV 109
-#define IMX7D_USB_HSIC_ROOT_CLK 110
-#define IMX7D_USB_HSIC_ROOT_SRC 111
-#define IMX7D_USB_HSIC_ROOT_CG 112
-#define IMX7D_USB_HSIC_ROOT_DIV 113
-#define IMX7D_PCIE_CTRL_ROOT_CLK 114
-#define IMX7D_PCIE_CTRL_ROOT_SRC 115
-#define IMX7D_PCIE_CTRL_ROOT_CG 116
-#define IMX7D_PCIE_CTRL_ROOT_DIV 117
-#define IMX7D_PCIE_PHY_ROOT_CLK 118
-#define IMX7D_PCIE_PHY_ROOT_SRC 119
-#define IMX7D_PCIE_PHY_ROOT_CG 120
-#define IMX7D_PCIE_PHY_ROOT_DIV 121
-#define IMX7D_EPDC_PIXEL_ROOT_CLK 122
-#define IMX7D_EPDC_PIXEL_ROOT_SRC 123
-#define IMX7D_EPDC_PIXEL_ROOT_CG 124
-#define IMX7D_EPDC_PIXEL_ROOT_DIV 125
-#define IMX7D_LCDIF_PIXEL_ROOT_CLK 126
-#define IMX7D_LCDIF_PIXEL_ROOT_SRC 127
-#define IMX7D_LCDIF_PIXEL_ROOT_CG 128
-#define IMX7D_LCDIF_PIXEL_ROOT_DIV 129
-#define IMX7D_MIPI_DSI_ROOT_CLK 130
-#define IMX7D_MIPI_DSI_ROOT_SRC 131
-#define IMX7D_MIPI_DSI_ROOT_CG 132
-#define IMX7D_MIPI_DSI_ROOT_DIV 133
-#define IMX7D_MIPI_CSI_ROOT_CLK 134
-#define IMX7D_MIPI_CSI_ROOT_SRC 135
-#define IMX7D_MIPI_CSI_ROOT_CG 136
-#define IMX7D_MIPI_CSI_ROOT_DIV 137
-#define IMX7D_MIPI_DPHY_ROOT_CLK 138
-#define IMX7D_MIPI_DPHY_ROOT_SRC 139
-#define IMX7D_MIPI_DPHY_ROOT_CG 140
-#define IMX7D_MIPI_DPHY_ROOT_DIV 141
-#define IMX7D_SAI1_ROOT_CLK 142
-#define IMX7D_SAI1_ROOT_SRC 143
-#define IMX7D_SAI1_ROOT_CG 144
-#define IMX7D_SAI1_ROOT_DIV 145
-#define IMX7D_SAI2_ROOT_CLK 146
-#define IMX7D_SAI2_ROOT_SRC 147
-#define IMX7D_SAI2_ROOT_CG 148
-#define IMX7D_SAI2_ROOT_DIV 149
-#define IMX7D_SAI3_ROOT_CLK 150
-#define IMX7D_SAI3_ROOT_SRC 151
-#define IMX7D_SAI3_ROOT_CG 152
-#define IMX7D_SAI3_ROOT_DIV 153
-#define IMX7D_SPDIF_ROOT_CLK 154
-#define IMX7D_SPDIF_ROOT_SRC 155
-#define IMX7D_SPDIF_ROOT_CG 156
-#define IMX7D_SPDIF_ROOT_DIV 157
-#define IMX7D_ENET1_REF_ROOT_CLK 158
-#define IMX7D_ENET1_REF_ROOT_SRC 159
-#define IMX7D_ENET1_REF_ROOT_CG 160
-#define IMX7D_ENET1_REF_ROOT_DIV 161
-#define IMX7D_ENET1_TIME_ROOT_CLK 162
-#define IMX7D_ENET1_TIME_ROOT_SRC 163
-#define IMX7D_ENET1_TIME_ROOT_CG 164
-#define IMX7D_ENET1_TIME_ROOT_DIV 165
-#define IMX7D_ENET2_REF_ROOT_CLK 166
-#define IMX7D_ENET2_REF_ROOT_SRC 167
-#define IMX7D_ENET2_REF_ROOT_CG 168
-#define IMX7D_ENET2_REF_ROOT_DIV 169
-#define IMX7D_ENET2_TIME_ROOT_CLK 170
-#define IMX7D_ENET2_TIME_ROOT_SRC 171
-#define IMX7D_ENET2_TIME_ROOT_CG 172
-#define IMX7D_ENET2_TIME_ROOT_DIV 173
-#define IMX7D_ENET_PHY_REF_ROOT_CLK 174
-#define IMX7D_ENET_PHY_REF_ROOT_SRC 175
-#define IMX7D_ENET_PHY_REF_ROOT_CG 176
-#define IMX7D_ENET_PHY_REF_ROOT_DIV 177
-#define IMX7D_EIM_ROOT_CLK 178
-#define IMX7D_EIM_ROOT_SRC 179
-#define IMX7D_EIM_ROOT_CG 180
-#define IMX7D_EIM_ROOT_DIV 181
-#define IMX7D_NAND_ROOT_CLK 182
-#define IMX7D_NAND_ROOT_SRC 183
-#define IMX7D_NAND_ROOT_CG 184
-#define IMX7D_NAND_ROOT_DIV 185
-#define IMX7D_QSPI_ROOT_CLK 186
-#define IMX7D_QSPI_ROOT_SRC 187
-#define IMX7D_QSPI_ROOT_CG 188
-#define IMX7D_QSPI_ROOT_DIV 189
-#define IMX7D_USDHC1_ROOT_CLK 190
-#define IMX7D_USDHC1_ROOT_SRC 191
-#define IMX7D_USDHC1_ROOT_CG 192
-#define IMX7D_USDHC1_ROOT_DIV 193
-#define IMX7D_USDHC2_ROOT_CLK 194
-#define IMX7D_USDHC2_ROOT_SRC 195
-#define IMX7D_USDHC2_ROOT_CG 196
-#define IMX7D_USDHC2_ROOT_DIV 197
-#define IMX7D_USDHC3_ROOT_CLK 198
-#define IMX7D_USDHC3_ROOT_SRC 199
-#define IMX7D_USDHC3_ROOT_CG 200
-#define IMX7D_USDHC3_ROOT_DIV 201
-#define IMX7D_CAN1_ROOT_CLK 202
-#define IMX7D_CAN1_ROOT_SRC 203
-#define IMX7D_CAN1_ROOT_CG 204
-#define IMX7D_CAN1_ROOT_DIV 205
-#define IMX7D_CAN2_ROOT_CLK 206
-#define IMX7D_CAN2_ROOT_SRC 207
-#define IMX7D_CAN2_ROOT_CG 208
-#define IMX7D_CAN2_ROOT_DIV 209
-#define IMX7D_I2C1_ROOT_CLK 210
-#define IMX7D_I2C1_ROOT_SRC 211
-#define IMX7D_I2C1_ROOT_CG 212
-#define IMX7D_I2C1_ROOT_DIV 213
-#define IMX7D_I2C2_ROOT_CLK 214
-#define IMX7D_I2C2_ROOT_SRC 215
-#define IMX7D_I2C2_ROOT_CG 216
-#define IMX7D_I2C2_ROOT_DIV 217
-#define IMX7D_I2C3_ROOT_CLK 218
-#define IMX7D_I2C3_ROOT_SRC 219
-#define IMX7D_I2C3_ROOT_CG 220
-#define IMX7D_I2C3_ROOT_DIV 221
-#define IMX7D_I2C4_ROOT_CLK 222
-#define IMX7D_I2C4_ROOT_SRC 223
-#define IMX7D_I2C4_ROOT_CG 224
-#define IMX7D_I2C4_ROOT_DIV 225
-#define IMX7D_UART1_ROOT_CLK 226
-#define IMX7D_UART1_ROOT_SRC 227
-#define IMX7D_UART1_ROOT_CG 228
-#define IMX7D_UART1_ROOT_DIV 229
-#define IMX7D_UART2_ROOT_CLK 230
-#define IMX7D_UART2_ROOT_SRC 231
-#define IMX7D_UART2_ROOT_CG 232
-#define IMX7D_UART2_ROOT_DIV 233
-#define IMX7D_UART3_ROOT_CLK 234
-#define IMX7D_UART3_ROOT_SRC 235
-#define IMX7D_UART3_ROOT_CG 236
-#define IMX7D_UART3_ROOT_DIV 237
-#define IMX7D_UART4_ROOT_CLK 238
-#define IMX7D_UART4_ROOT_SRC 239
-#define IMX7D_UART4_ROOT_CG 240
-#define IMX7D_UART4_ROOT_DIV 241
-#define IMX7D_UART5_ROOT_CLK 242
-#define IMX7D_UART5_ROOT_SRC 243
-#define IMX7D_UART5_ROOT_CG 244
-#define IMX7D_UART5_ROOT_DIV 245
-#define IMX7D_UART6_ROOT_CLK 246
-#define IMX7D_UART6_ROOT_SRC 247
-#define IMX7D_UART6_ROOT_CG 248
-#define IMX7D_UART6_ROOT_DIV 249
-#define IMX7D_UART7_ROOT_CLK 250
-#define IMX7D_UART7_ROOT_SRC 251
-#define IMX7D_UART7_ROOT_CG 252
-#define IMX7D_UART7_ROOT_DIV 253
-#define IMX7D_ECSPI1_ROOT_CLK 254
-#define IMX7D_ECSPI1_ROOT_SRC 255
-#define IMX7D_ECSPI1_ROOT_CG 256
-#define IMX7D_ECSPI1_ROOT_DIV 257
-#define IMX7D_ECSPI2_ROOT_CLK 258
-#define IMX7D_ECSPI2_ROOT_SRC 259
-#define IMX7D_ECSPI2_ROOT_CG 260
-#define IMX7D_ECSPI2_ROOT_DIV 261
-#define IMX7D_ECSPI3_ROOT_CLK 262
-#define IMX7D_ECSPI3_ROOT_SRC 263
-#define IMX7D_ECSPI3_ROOT_CG 264
-#define IMX7D_ECSPI3_ROOT_DIV 265
-#define IMX7D_ECSPI4_ROOT_CLK 266
-#define IMX7D_ECSPI4_ROOT_SRC 267
-#define IMX7D_ECSPI4_ROOT_CG 268
-#define IMX7D_ECSPI4_ROOT_DIV 269
-#define IMX7D_PWM1_ROOT_CLK 270
-#define IMX7D_PWM1_ROOT_SRC 271
-#define IMX7D_PWM1_ROOT_CG 272
-#define IMX7D_PWM1_ROOT_DIV 273
-#define IMX7D_PWM2_ROOT_CLK 274
-#define IMX7D_PWM2_ROOT_SRC 275
-#define IMX7D_PWM2_ROOT_CG 276
-#define IMX7D_PWM2_ROOT_DIV 277
-#define IMX7D_PWM3_ROOT_CLK 278
-#define IMX7D_PWM3_ROOT_SRC 279
-#define IMX7D_PWM3_ROOT_CG 280
-#define IMX7D_PWM3_ROOT_DIV 281
-#define IMX7D_PWM4_ROOT_CLK 282
-#define IMX7D_PWM4_ROOT_SRC 283
-#define IMX7D_PWM4_ROOT_CG 284
-#define IMX7D_PWM4_ROOT_DIV 285
-#define IMX7D_FLEXTIMER1_ROOT_CLK 286
-#define IMX7D_FLEXTIMER1_ROOT_SRC 287
-#define IMX7D_FLEXTIMER1_ROOT_CG 288
-#define IMX7D_FLEXTIMER1_ROOT_DIV 289
-#define IMX7D_FLEXTIMER2_ROOT_CLK 290
-#define IMX7D_FLEXTIMER2_ROOT_SRC 291
-#define IMX7D_FLEXTIMER2_ROOT_CG 292
-#define IMX7D_FLEXTIMER2_ROOT_DIV 293
-#define IMX7D_SIM1_ROOT_CLK 294
-#define IMX7D_SIM1_ROOT_SRC 295
-#define IMX7D_SIM1_ROOT_CG 296
-#define IMX7D_SIM1_ROOT_DIV 297
-#define IMX7D_SIM2_ROOT_CLK 298
-#define IMX7D_SIM2_ROOT_SRC 299
-#define IMX7D_SIM2_ROOT_CG 300
-#define IMX7D_SIM2_ROOT_DIV 301
-#define IMX7D_GPT1_ROOT_CLK 302
-#define IMX7D_GPT1_ROOT_SRC 303
-#define IMX7D_GPT1_ROOT_CG 304
-#define IMX7D_GPT1_ROOT_DIV 305
-#define IMX7D_GPT2_ROOT_CLK 306
-#define IMX7D_GPT2_ROOT_SRC 307
-#define IMX7D_GPT2_ROOT_CG 308
-#define IMX7D_GPT2_ROOT_DIV 309
-#define IMX7D_GPT3_ROOT_CLK 310
-#define IMX7D_GPT3_ROOT_SRC 311
-#define IMX7D_GPT3_ROOT_CG 312
-#define IMX7D_GPT3_ROOT_DIV 313
-#define IMX7D_GPT4_ROOT_CLK 314
-#define IMX7D_GPT4_ROOT_SRC 315
-#define IMX7D_GPT4_ROOT_CG 316
-#define IMX7D_GPT4_ROOT_DIV 317
-#define IMX7D_TRACE_ROOT_CLK 318
-#define IMX7D_TRACE_ROOT_SRC 319
-#define IMX7D_TRACE_ROOT_CG 320
-#define IMX7D_TRACE_ROOT_DIV 321
-#define IMX7D_WDOG1_ROOT_CLK 322
-#define IMX7D_WDOG_ROOT_SRC 323
-#define IMX7D_WDOG_ROOT_CG 324
-#define IMX7D_WDOG_ROOT_DIV 325
-#define IMX7D_CSI_MCLK_ROOT_CLK 326
-#define IMX7D_CSI_MCLK_ROOT_SRC 327
-#define IMX7D_CSI_MCLK_ROOT_CG 328
-#define IMX7D_CSI_MCLK_ROOT_DIV 329
-#define IMX7D_AUDIO_MCLK_ROOT_CLK 330
-#define IMX7D_AUDIO_MCLK_ROOT_SRC 331
-#define IMX7D_AUDIO_MCLK_ROOT_CG 332
-#define IMX7D_AUDIO_MCLK_ROOT_DIV 333
-#define IMX7D_WRCLK_ROOT_CLK 334
-#define IMX7D_WRCLK_ROOT_SRC 335
-#define IMX7D_WRCLK_ROOT_CG 336
-#define IMX7D_WRCLK_ROOT_DIV 337
-#define IMX7D_CLKO1_ROOT_SRC 338
-#define IMX7D_CLKO1_ROOT_CG 339
-#define IMX7D_CLKO1_ROOT_DIV 340
-#define IMX7D_CLKO2_ROOT_SRC 341
-#define IMX7D_CLKO2_ROOT_CG 342
-#define IMX7D_CLKO2_ROOT_DIV 343
-#define IMX7D_MAIN_AXI_ROOT_PRE_DIV 344
-#define IMX7D_DISP_AXI_ROOT_PRE_DIV 345
-#define IMX7D_ENET_AXI_ROOT_PRE_DIV 346
-#define IMX7D_NAND_USDHC_BUS_ROOT_PRE_DIV 347
-#define IMX7D_AHB_CHANNEL_ROOT_PRE_DIV 348
-#define IMX7D_USB_HSIC_ROOT_PRE_DIV 349
-#define IMX7D_PCIE_CTRL_ROOT_PRE_DIV 350
-#define IMX7D_PCIE_PHY_ROOT_PRE_DIV 351
-#define IMX7D_EPDC_PIXEL_ROOT_PRE_DIV 352
-#define IMX7D_LCDIF_PIXEL_ROOT_PRE_DIV 353
-#define IMX7D_MIPI_DSI_ROOT_PRE_DIV 354
-#define IMX7D_MIPI_CSI_ROOT_PRE_DIV 355
-#define IMX7D_MIPI_DPHY_ROOT_PRE_DIV 356
-#define IMX7D_SAI1_ROOT_PRE_DIV 357
-#define IMX7D_SAI2_ROOT_PRE_DIV 358
-#define IMX7D_SAI3_ROOT_PRE_DIV 359
-#define IMX7D_SPDIF_ROOT_PRE_DIV 360
-#define IMX7D_ENET1_REF_ROOT_PRE_DIV 361
-#define IMX7D_ENET1_TIME_ROOT_PRE_DIV 362
-#define IMX7D_ENET2_REF_ROOT_PRE_DIV 363
-#define IMX7D_ENET2_TIME_ROOT_PRE_DIV 364
-#define IMX7D_ENET_PHY_REF_ROOT_PRE_DIV 365
-#define IMX7D_EIM_ROOT_PRE_DIV 366
-#define IMX7D_NAND_ROOT_PRE_DIV 367
-#define IMX7D_QSPI_ROOT_PRE_DIV 368
-#define IMX7D_USDHC1_ROOT_PRE_DIV 369
-#define IMX7D_USDHC2_ROOT_PRE_DIV 370
-#define IMX7D_USDHC3_ROOT_PRE_DIV 371
-#define IMX7D_CAN1_ROOT_PRE_DIV 372
-#define IMX7D_CAN2_ROOT_PRE_DIV 373
-#define IMX7D_I2C1_ROOT_PRE_DIV 374
-#define IMX7D_I2C2_ROOT_PRE_DIV 375
-#define IMX7D_I2C3_ROOT_PRE_DIV 376
-#define IMX7D_I2C4_ROOT_PRE_DIV 377
-#define IMX7D_UART1_ROOT_PRE_DIV 378
-#define IMX7D_UART2_ROOT_PRE_DIV 379
-#define IMX7D_UART3_ROOT_PRE_DIV 380
-#define IMX7D_UART4_ROOT_PRE_DIV 381
-#define IMX7D_UART5_ROOT_PRE_DIV 382
-#define IMX7D_UART6_ROOT_PRE_DIV 383
-#define IMX7D_UART7_ROOT_PRE_DIV 384
-#define IMX7D_ECSPI1_ROOT_PRE_DIV 385
-#define IMX7D_ECSPI2_ROOT_PRE_DIV 386
-#define IMX7D_ECSPI3_ROOT_PRE_DIV 387
-#define IMX7D_ECSPI4_ROOT_PRE_DIV 388
-#define IMX7D_PWM1_ROOT_PRE_DIV 389
-#define IMX7D_PWM2_ROOT_PRE_DIV 390
-#define IMX7D_PWM3_ROOT_PRE_DIV 391
-#define IMX7D_PWM4_ROOT_PRE_DIV 392
-#define IMX7D_FLEXTIMER1_ROOT_PRE_DIV 393
-#define IMX7D_FLEXTIMER2_ROOT_PRE_DIV 394
-#define IMX7D_SIM1_ROOT_PRE_DIV 395
-#define IMX7D_SIM2_ROOT_PRE_DIV 396
-#define IMX7D_GPT1_ROOT_PRE_DIV 397
-#define IMX7D_GPT2_ROOT_PRE_DIV 398
-#define IMX7D_GPT3_ROOT_PRE_DIV 399
-#define IMX7D_GPT4_ROOT_PRE_DIV 400
-#define IMX7D_TRACE_ROOT_PRE_DIV 401
-#define IMX7D_WDOG_ROOT_PRE_DIV 402
-#define IMX7D_CSI_MCLK_ROOT_PRE_DIV 403
-#define IMX7D_AUDIO_MCLK_ROOT_PRE_DIV 404
-#define IMX7D_WRCLK_ROOT_PRE_DIV 405
-#define IMX7D_CLKO1_ROOT_PRE_DIV 406
-#define IMX7D_CLKO2_ROOT_PRE_DIV 407
-#define IMX7D_DRAM_PHYM_ALT_ROOT_PRE_DIV 408
-#define IMX7D_DRAM_ALT_ROOT_PRE_DIV 409
-#define IMX7D_LVDS1_IN_CLK 410
-#define IMX7D_LVDS1_OUT_SEL 411
-#define IMX7D_LVDS1_OUT_CLK 412
-#define IMX7D_CLK_DUMMY 413
-#define IMX7D_GPT_3M_CLK 414
-#define IMX7D_OCRAM_CLK 415
-#define IMX7D_OCRAM_S_CLK 416
-#define IMX7D_WDOG2_ROOT_CLK 417
-#define IMX7D_WDOG3_ROOT_CLK 418
-#define IMX7D_WDOG4_ROOT_CLK 419
-#define IMX7D_SDMA_CORE_CLK 420
-#define IMX7D_USB1_MAIN_480M_CLK 421
-#define IMX7D_USB_CTRL_CLK 422
-#define IMX7D_USB_PHY1_CLK 423
-#define IMX7D_USB_PHY2_CLK 424
-#define IMX7D_IPG_ROOT_CLK 425
-#define IMX7D_SAI1_IPG_CLK 426
-#define IMX7D_SAI2_IPG_CLK 427
-#define IMX7D_SAI3_IPG_CLK 428
-#define IMX7D_PLL_AUDIO_TEST_DIV 429
-#define IMX7D_PLL_AUDIO_POST_DIV 430
-#define IMX7D_PLL_VIDEO_TEST_DIV 431
-#define IMX7D_PLL_VIDEO_POST_DIV 432
-#define IMX7D_MU_ROOT_CLK 433
-#define IMX7D_SEMA4_HS_ROOT_CLK 434
-#define IMX7D_PLL_DRAM_TEST_DIV 435
-#define IMX7D_ADC_ROOT_CLK 436
-#define IMX7D_CLK_ARM 437
-#define IMX7D_CKIL 438
-#define IMX7D_OCOTP_CLK 439
-#define IMX7D_NAND_RAWNAND_CLK 440
-#define IMX7D_NAND_USDHC_BUS_RAWNAND_CLK 441
-#define IMX7D_SNVS_CLK 442
-#define IMX7D_CAAM_CLK 443
-#define IMX7D_KPP_ROOT_CLK 444
-#define IMX7D_CLK_END 445
-#endif /* __DT_BINDINGS_CLOCK_IMX7D_H */
diff --git a/include/dt-bindings/clock/imx7ulp-clock.h b/include/dt-bindings/clock/imx7ulp-clock.h
deleted file mode 100644
index 0a955df..0000000
--- a/include/dt-bindings/clock/imx7ulp-clock.h
+++ /dev/null
@@ -1,161 +0,0 @@
-/*
- * Copyright (C) 2016 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-#ifndef __DT_BINDINGS_CLOCK_IMX7ULP_H
-#define __DT_BINDINGS_CLOCK_IMX7ULP_H
-
-#define IMX7ULP_CLK_DUMMY 0
-#define IMX7ULP_CLK_CKIL 1
-#define IMX7ULP_CLK_OSC 2
-#define IMX7ULP_CLK_FIRC 3
-
-/* SCG1 */
-#define IMX7ULP_CLK_SPLL_PRE_SEL 4
-#define IMX7ULP_CLK_SPLL_PRE_DIV 5
-#define IMX7ULP_CLK_SPLL 6
-#define IMX7ULP_CLK_SPLL_POST_DIV1 7
-#define IMX7ULP_CLK_SPLL_POST_DIV2 8
-#define IMX7ULP_CLK_SPLL_PFD0 9
-#define IMX7ULP_CLK_SPLL_PFD1 10
-#define IMX7ULP_CLK_SPLL_PFD2 11
-#define IMX7ULP_CLK_SPLL_PFD3 12
-#define IMX7ULP_CLK_SPLL_PFD_SEL 13
-#define IMX7ULP_CLK_SPLL_SEL 14
-#define IMX7ULP_CLK_APLL_PRE_SEL 15
-#define IMX7ULP_CLK_APLL_PRE_DIV 16
-#define IMX7ULP_CLK_APLL 17
-#define IMX7ULP_CLK_APLL_POST_DIV1 18
-#define IMX7ULP_CLK_APLL_POST_DIV2 19
-#define IMX7ULP_CLK_APLL_PFD0 20
-#define IMX7ULP_CLK_APLL_PFD1 21
-#define IMX7ULP_CLK_APLL_PFD2 22
-#define IMX7ULP_CLK_APLL_PFD3 23
-#define IMX7ULP_CLK_APLL_PFD_SEL 24
-#define IMX7ULP_CLK_APLL_SEL 25
-#define IMX7ULP_CLK_UPLL 26
-#define IMX7ULP_CLK_SYS_SEL 27
-#define IMX7ULP_CLK_CORE_DIV 28
-#define IMX7ULP_CLK_BUS_DIV 29
-#define IMX7ULP_CLK_PLAT_DIV 30
-#define IMX7ULP_CLK_DDR_SEL 31
-#define IMX7ULP_CLK_DDR_DIV 32
-#define IMX7ULP_CLK_NIC_SEL 33
-#define IMX7ULP_CLK_NIC0_DIV 34
-#define IMX7ULP_CLK_GPU_DIV 35
-#define IMX7ULP_CLK_NIC1_DIV 36
-#define IMX7ULP_CLK_NIC1_BUS_DIV 37
-#define IMX7ULP_CLK_NIC1_EXT_DIV 38
-
-/* PCG2 */
-#define IMX7ULP_CLK_DMA1 39
-#define IMX7ULP_CLK_RGPIO2P1 40
-#define IMX7ULP_CLK_FLEXBUS 41
-#define IMX7ULP_CLK_SEMA42_1 42
-#define IMX7ULP_CLK_DMA_MUX1 43
-#define IMX7ULP_CLK_SNVS 44
-#define IMX7ULP_CLK_CAAM 45
-#define IMX7ULP_CLK_LPTPM4 46
-#define IMX7ULP_CLK_LPTPM5 47
-#define IMX7ULP_CLK_LPIT1 48
-#define IMX7ULP_CLK_LPSPI2 49
-#define IMX7ULP_CLK_LPSPI3 50
-#define IMX7ULP_CLK_LPI2C4 51
-#define IMX7ULP_CLK_LPI2C5 52
-#define IMX7ULP_CLK_LPUART4 53
-#define IMX7ULP_CLK_LPUART5 54
-#define IMX7ULP_CLK_FLEXIO1 55
-#define IMX7ULP_CLK_USB0 56
-#define IMX7ULP_CLK_USB1 57
-#define IMX7ULP_CLK_USB_PHY 58
-#define IMX7ULP_CLK_USB_PL301 59
-#define IMX7ULP_CLK_USDHC0 60
-#define IMX7ULP_CLK_USDHC1 61
-#define IMX7ULP_CLK_WDG1 62
-#define IMX7ULP_CLK_WDG2 63
-
-/* PCG3 */
-#define IMX7ULP_CLK_LPTPM6 64
-#define IMX7ULP_CLK_LPTPM7 65
-#define IMX7ULP_CLK_LPI2C6 66
-#define IMX7ULP_CLK_LPI2C7 67
-#define IMX7ULP_CLK_LPUART6 68
-#define IMX7ULP_CLK_LPUART7 69
-#define IMX7ULP_CLK_VIU 70
-#define IMX7ULP_CLK_DSI 71
-#define IMX7ULP_CLK_LCDIF 72
-#define IMX7ULP_CLK_MMDC 73
-#define IMX7ULP_CLK_PCTLC 74
-#define IMX7ULP_CLK_PCTLD 75
-#define IMX7ULP_CLK_PCTLE 76
-#define IMX7ULP_CLK_PCTLF 77
-#define IMX7ULP_CLK_GPU3D 78
-#define IMX7ULP_CLK_GPU2D 79
-
-#define IMX7ULP_CLK_MIPI_PLL 80
-#define IMX7ULP_CLK_SIRC 81
-
-#define IMX7ULP_CLK_SCG1_CLKOUT 82
-
-#define IMX7ULP_CLK_END 83
-
-/*cm4 clocks*/
-#define IMX7ULP_CM4_CLK_DUMMY 0
-#define IMX7ULP_CM4_CLK_CKIL 1
-#define IMX7ULP_CM4_CLK_OSC 2
-#define IMX7ULP_CM4_CLK_FIRC 3
-#define IMX7ULP_CM4_CLK_SIRC 4
-
-/* SCG0 */
-#define IMX7ULP_CM4_CLK_SPLL_VCO_PRE_SEL 5
-#define IMX7ULP_CM4_CLK_SPLL_VCO_PRE_DIV 6
-#define IMX7ULP_CM4_CLK_SPLL 7
-#define IMX7ULP_CM4_CLK_SPLL_VCO 8
-#define IMX7ULP_CM4_CLK_SPLL_VCO_POST_DIV1 9
-#define IMX7ULP_CM4_CLK_SPLL_VCO_POST_DIV2 10
-#define IMX7ULP_CM4_CLK_SPLL_PFD0 11
-#define IMX7ULP_CM4_CLK_SPLL_PFD1 12
-#define IMX7ULP_CM4_CLK_SPLL_PFD2 13
-#define IMX7ULP_CM4_CLK_SPLL_PFD3 14
-#define IMX7ULP_CM4_CLK_SPLL_PFD_SEL 15
-#define IMX7ULP_CM4_CLK_SPLL_PFD 16
-#define IMX7ULP_CM4_CLK_SPLL_SEL 17
-#define IMX7ULP_CM4_CLK_APLL_VCO_PRE_SEL 18
-#define IMX7ULP_CM4_CLK_APLL_VCO_PRE_DIV 19
-#define IMX7ULP_CM4_CLK_APLL 20
-#define IMX7ULP_CM4_CLK_APLL_VCO 21
-#define IMX7ULP_CM4_CLK_APLL_VCO_POST_DIV1 22
-#define IMX7ULP_CM4_CLK_APLL_VCO_POST_DIV2 23
-#define IMX7ULP_CM4_CLK_APLL_PFD0 24
-#define IMX7ULP_CM4_CLK_APLL_PFD1 25
-#define IMX7ULP_CM4_CLK_APLL_PFD2 26
-#define IMX7ULP_CM4_CLK_APLL_PFD3 27
-#define IMX7ULP_CM4_CLK_APLL_PFD_SEL 28
-#define IMX7ULP_CM4_CLK_APLL_PFD 29
-#define IMX7ULP_CM4_CLK_APLL_SEL 30
-#define IMX7ULP_CM4_CLK_APLL_PFD0_PRE_DIV 31
-#define IMX7ULP_CM4_CLK_SYS_SEL 32
-#define IMX7ULP_CM4_CLK_CORE_DIV 33
-#define IMX7ULP_CM4_CLK_BUS_DIV 34
-#define IMX7ULP_CM4_CLK_PLAT_DIV 35
-#define IMX7ULP_CM4_CLK_SLOW_DIV 36
-
-#define IMX7ULP_CM4_CLK_SAI0_SEL 37
-#define IMX7ULP_CM4_CLK_SAI0_DIV 38
-#define IMX7ULP_CM4_CLK_SAI0_ROOT 39
-#define IMX7ULP_CM4_CLK_SAI0_IPG 40
-#define IMX7ULP_CM4_CLK_SAI1_SEL 41
-#define IMX7ULP_CM4_CLK_SAI1_DIV 42
-#define IMX7ULP_CM4_CLK_SAI1_ROOT 43
-#define IMX7ULP_CM4_CLK_SAI1_IPG 44
-
-#define IMX7ULP_CLK_SCG0_CLKOUT 45
-
-#define IMX7ULP_CM4_CLK_END 46
-
-#endif /* __DT_BINDINGS_CLOCK_IMX7ULP_H */
diff --git a/include/dt-bindings/clock/imx8mm-clock.h b/include/dt-bindings/clock/imx8mm-clock.h
deleted file mode 100644
index 07e6c68..0000000
--- a/include/dt-bindings/clock/imx8mm-clock.h
+++ /dev/null
@@ -1,253 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright 2017-2018 NXP
- */
-
-#ifndef __DT_BINDINGS_CLOCK_IMX8MM_H
-#define __DT_BINDINGS_CLOCK_IMX8MM_H
-
-#define IMX8MM_CLK_DUMMY 0
-#define IMX8MM_CLK_32K 1
-#define IMX8MM_CLK_24M 2
-#define IMX8MM_OSC_HDMI_CLK 3
-#define IMX8MM_CLK_EXT1 4
-#define IMX8MM_CLK_EXT2 5
-#define IMX8MM_CLK_EXT3 6
-#define IMX8MM_CLK_EXT4 7
-#define IMX8MM_AUDIO_PLL1_REF_SEL 8
-#define IMX8MM_AUDIO_PLL2_REF_SEL 9
-#define IMX8MM_VIDEO_PLL1_REF_SEL 10
-#define IMX8MM_DRAM_PLL_REF_SEL 11
-#define IMX8MM_GPU_PLL_REF_SEL 12
-#define IMX8MM_VPU_PLL_REF_SEL 13
-#define IMX8MM_ARM_PLL_REF_SEL 14
-#define IMX8MM_SYS_PLL1_REF_SEL 15
-#define IMX8MM_SYS_PLL2_REF_SEL 16
-#define IMX8MM_SYS_PLL3_REF_SEL 17
-#define IMX8MM_AUDIO_PLL1 18
-#define IMX8MM_AUDIO_PLL2 19
-#define IMX8MM_VIDEO_PLL1 20
-#define IMX8MM_DRAM_PLL 21
-#define IMX8MM_GPU_PLL 22
-#define IMX8MM_VPU_PLL 23
-#define IMX8MM_ARM_PLL 24
-#define IMX8MM_SYS_PLL1 25
-#define IMX8MM_SYS_PLL2 26
-#define IMX8MM_SYS_PLL3 27
-#define IMX8MM_AUDIO_PLL1_BYPASS 28
-#define IMX8MM_AUDIO_PLL2_BYPASS 29
-#define IMX8MM_VIDEO_PLL1_BYPASS 30
-#define IMX8MM_DRAM_PLL_BYPASS 31
-#define IMX8MM_GPU_PLL_BYPASS 32
-#define IMX8MM_VPU_PLL_BYPASS 33
-#define IMX8MM_ARM_PLL_BYPASS 34
-#define IMX8MM_SYS_PLL1_BYPASS 35
-#define IMX8MM_SYS_PLL2_BYPASS 36
-#define IMX8MM_SYS_PLL3_BYPASS 37
-#define IMX8MM_AUDIO_PLL1_OUT 38
-#define IMX8MM_AUDIO_PLL2_OUT 39
-#define IMX8MM_VIDEO_PLL1_OUT 40
-#define IMX8MM_DRAM_PLL_OUT 41
-#define IMX8MM_GPU_PLL_OUT 42
-#define IMX8MM_VPU_PLL_OUT 43
-#define IMX8MM_ARM_PLL_OUT 44
-#define IMX8MM_SYS_PLL1_OUT 45
-#define IMX8MM_SYS_PLL2_OUT 46
-#define IMX8MM_SYS_PLL3_OUT 47
-#define IMX8MM_SYS_PLL1_40M 48
-#define IMX8MM_SYS_PLL1_80M 49
-#define IMX8MM_SYS_PLL1_100M 50
-#define IMX8MM_SYS_PLL1_133M 51
-#define IMX8MM_SYS_PLL1_160M 52
-#define IMX8MM_SYS_PLL1_200M 53
-#define IMX8MM_SYS_PLL1_266M 54
-#define IMX8MM_SYS_PLL1_400M 55
-#define IMX8MM_SYS_PLL1_800M 56
-#define IMX8MM_SYS_PLL2_50M 57
-#define IMX8MM_SYS_PLL2_100M 58
-#define IMX8MM_SYS_PLL2_125M 59
-#define IMX8MM_SYS_PLL2_166M 60
-#define IMX8MM_SYS_PLL2_200M 61
-#define IMX8MM_SYS_PLL2_250M 62
-#define IMX8MM_SYS_PLL2_333M 63
-#define IMX8MM_SYS_PLL2_500M 64
-#define IMX8MM_SYS_PLL2_1000M 65
-
-/* core */
-#define IMX8MM_CLK_A53_SRC 66
-#define IMX8MM_CLK_M4_SRC 67
-#define IMX8MM_CLK_VPU_SRC 68
-#define IMX8MM_CLK_GPU3D_SRC 69
-#define IMX8MM_CLK_GPU2D_SRC 70
-#define IMX8MM_CLK_A53_CG 71
-#define IMX8MM_CLK_M4_CG 72
-#define IMX8MM_CLK_VPU_CG 73
-#define IMX8MM_CLK_GPU3D_CG 74
-#define IMX8MM_CLK_GPU2D_CG 75
-#define IMX8MM_CLK_A53_DIV 76
-#define IMX8MM_CLK_M4_DIV 77
-#define IMX8MM_CLK_VPU_DIV 78
-#define IMX8MM_CLK_GPU3D_DIV 79
-#define IMX8MM_CLK_GPU2D_DIV 80
-
-/* bus */
-#define IMX8MM_CLK_MAIN_AXI 81
-#define IMX8MM_CLK_ENET_AXI 82
-#define IMX8MM_CLK_NAND_USDHC_BUS 83
-#define IMX8MM_CLK_VPU_BUS 84
-#define IMX8MM_CLK_DISP_AXI 85
-#define IMX8MM_CLK_DISP_APB 86
-#define IMX8MM_CLK_DISP_RTRM 87
-#define IMX8MM_CLK_USB_BUS 88
-#define IMX8MM_CLK_GPU_AXI 89
-#define IMX8MM_CLK_GPU_AHB 90
-#define IMX8MM_CLK_NOC 91
-#define IMX8MM_CLK_NOC_APB 92
-
-#define IMX8MM_CLK_AHB 93
-#define IMX8MM_CLK_AUDIO_AHB 94
-#define IMX8MM_CLK_IPG_ROOT 95
-#define IMX8MM_CLK_IPG_AUDIO_ROOT 96
-
-#define IMX8MM_CLK_DRAM_ALT 97
-#define IMX8MM_CLK_DRAM_APB 98
-#define IMX8MM_CLK_VPU_G1 99
-#define IMX8MM_CLK_VPU_G2 100
-#define IMX8MM_CLK_DISP_DTRC 101
-#define IMX8MM_CLK_DISP_DC8000 102
-#define IMX8MM_CLK_PCIE1_CTRL 103
-#define IMX8MM_CLK_PCIE1_PHY 104
-#define IMX8MM_CLK_PCIE1_AUX 105
-#define IMX8MM_CLK_DC_PIXEL 106
-#define IMX8MM_CLK_LCDIF_PIXEL 107
-#define IMX8MM_CLK_SAI1 108
-#define IMX8MM_CLK_SAI2 109
-#define IMX8MM_CLK_SAI3 110
-#define IMX8MM_CLK_SAI4 111
-#define IMX8MM_CLK_SAI5 112
-#define IMX8MM_CLK_SAI6 113
-#define IMX8MM_CLK_SPDIF1 114
-#define IMX8MM_CLK_SPDIF2 115
-#define IMX8MM_CLK_ENET_REF 116
-#define IMX8MM_CLK_ENET_TIMER 117
-#define IMX8MM_CLK_ENET_PHY_REF 118
-#define IMX8MM_CLK_NAND 119
-#define IMX8MM_CLK_QSPI 120
-#define IMX8MM_CLK_USDHC1 121
-#define IMX8MM_CLK_USDHC2 122
-#define IMX8MM_CLK_I2C1 123
-#define IMX8MM_CLK_I2C2 124
-#define IMX8MM_CLK_I2C3 125
-#define IMX8MM_CLK_I2C4 126
-#define IMX8MM_CLK_UART1 127
-#define IMX8MM_CLK_UART2 128
-#define IMX8MM_CLK_UART3 129
-#define IMX8MM_CLK_UART4 130
-#define IMX8MM_CLK_USB_CORE_REF 131
-#define IMX8MM_CLK_USB_PHY_REF 132
-#define IMX8MM_CLK_ECSPI1 133
-#define IMX8MM_CLK_ECSPI2 134
-#define IMX8MM_CLK_PWM1 135
-#define IMX8MM_CLK_PWM2 136
-#define IMX8MM_CLK_PWM3 137
-#define IMX8MM_CLK_PWM4 138
-#define IMX8MM_CLK_GPT1 139
-#define IMX8MM_CLK_WDOG 140
-#define IMX8MM_CLK_WRCLK 141
-#define IMX8MM_CLK_DSI_CORE 142
-#define IMX8MM_CLK_DSI_PHY_REF 143
-#define IMX8MM_CLK_DSI_DBI 144
-#define IMX8MM_CLK_USDHC3 145
-#define IMX8MM_CLK_CSI1_CORE 146
-#define IMX8MM_CLK_CSI1_PHY_REF 147
-#define IMX8MM_CLK_CSI1_ESC 148
-#define IMX8MM_CLK_CSI2_CORE 149
-#define IMX8MM_CLK_CSI2_PHY_REF 150
-#define IMX8MM_CLK_CSI2_ESC 151
-#define IMX8MM_CLK_PCIE2_CTRL 152
-#define IMX8MM_CLK_PCIE2_PHY 153
-#define IMX8MM_CLK_PCIE2_AUX 154
-#define IMX8MM_CLK_ECSPI3 155
-#define IMX8MM_CLK_PDM 156
-#define IMX8MM_CLK_VPU_H1 157
-#define IMX8MM_CLK_CLKO1 158
-
-#define IMX8MM_CLK_ECSPI1_ROOT 159
-#define IMX8MM_CLK_ECSPI2_ROOT 160
-#define IMX8MM_CLK_ECSPI3_ROOT 161
-#define IMX8MM_CLK_ENET1_ROOT 162
-#define IMX8MM_CLK_GPT1_ROOT 163
-#define IMX8MM_CLK_I2C1_ROOT 164
-#define IMX8MM_CLK_I2C2_ROOT 165
-#define IMX8MM_CLK_I2C3_ROOT 166
-#define IMX8MM_CLK_I2C4_ROOT 167
-#define IMX8MM_CLK_OCOTP_ROOT 168
-#define IMX8MM_CLK_PCIE1_ROOT 169
-#define IMX8MM_CLK_PWM1_ROOT 170
-#define IMX8MM_CLK_PWM2_ROOT 171
-#define IMX8MM_CLK_PWM3_ROOT 172
-#define IMX8MM_CLK_PWM4_ROOT 173
-#define IMX8MM_CLK_QSPI_ROOT 174
-#define IMX8MM_CLK_NAND_ROOT 175
-#define IMX8MM_CLK_SAI1_ROOT 176
-#define IMX8MM_CLK_SAI1_IPG 177
-#define IMX8MM_CLK_SAI2_ROOT 178
-#define IMX8MM_CLK_SAI2_IPG 179
-#define IMX8MM_CLK_SAI3_ROOT 180
-#define IMX8MM_CLK_SAI3_IPG 181
-#define IMX8MM_CLK_SAI4_ROOT 182
-#define IMX8MM_CLK_SAI4_IPG 183
-#define IMX8MM_CLK_SAI5_ROOT 184
-#define IMX8MM_CLK_SAI5_IPG 185
-#define IMX8MM_CLK_SAI6_ROOT 186
-#define IMX8MM_CLK_SAI6_IPG 187
-#define IMX8MM_CLK_UART1_ROOT 188
-#define IMX8MM_CLK_UART2_ROOT 189
-#define IMX8MM_CLK_UART3_ROOT 190
-#define IMX8MM_CLK_UART4_ROOT 191
-#define IMX8MM_CLK_USB1_CTRL_ROOT 192
-#define IMX8MM_CLK_GPU3D_ROOT 193
-#define IMX8MM_CLK_USDHC1_ROOT 194
-#define IMX8MM_CLK_USDHC2_ROOT 195
-#define IMX8MM_CLK_WDOG1_ROOT 196
-#define IMX8MM_CLK_WDOG2_ROOT 197
-#define IMX8MM_CLK_WDOG3_ROOT 198
-#define IMX8MM_CLK_VPU_G1_ROOT 199
-#define IMX8MM_CLK_GPU_BUS_ROOT 200
-#define IMX8MM_CLK_VPU_H1_ROOT 201
-#define IMX8MM_CLK_VPU_G2_ROOT 202
-#define IMX8MM_CLK_PDM_ROOT 203
-#define IMX8MM_CLK_DISP_ROOT 204
-#define IMX8MM_CLK_DISP_AXI_ROOT 205
-#define IMX8MM_CLK_DISP_APB_ROOT 206
-#define IMX8MM_CLK_DISP_RTRM_ROOT 207
-#define IMX8MM_CLK_USDHC3_ROOT 208
-#define IMX8MM_CLK_TMU_ROOT 209
-#define IMX8MM_CLK_VPU_DEC_ROOT 210
-#define IMX8MM_CLK_SDMA1_ROOT 211
-#define IMX8MM_CLK_SDMA2_ROOT 212
-#define IMX8MM_CLK_SDMA3_ROOT 213
-#define IMX8MM_CLK_GPT_3M 214
-#define IMX8MM_CLK_ARM 215
-#define IMX8MM_CLK_PDM_IPG 216
-#define IMX8MM_CLK_GPU2D_ROOT 217
-#define IMX8MM_CLK_MU_ROOT 218
-#define IMX8MM_CLK_CSI1_ROOT 219
-
-#define IMX8MM_CLK_DRAM_CORE 220
-#define IMX8MM_CLK_DRAM_ALT_ROOT 221
-
-#define IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK 222
-
-#define IMX8MM_CLK_GPIO1_ROOT 223
-#define IMX8MM_CLK_GPIO2_ROOT 224
-#define IMX8MM_CLK_GPIO3_ROOT 225
-#define IMX8MM_CLK_GPIO4_ROOT 226
-#define IMX8MM_CLK_GPIO5_ROOT 227
-
-#define IMX8MM_CLK_SNVS_ROOT 228
-#define IMX8MM_CLK_GIC 229
-
-#define IMX8MM_CLK_END 230
-
-#endif
diff --git a/include/dt-bindings/clock/imx8mq-clock.h b/include/dt-bindings/clock/imx8mq-clock.h
deleted file mode 100644
index 11dcafc..0000000
--- a/include/dt-bindings/clock/imx8mq-clock.h
+++ /dev/null
@@ -1,612 +0,0 @@
-/*
- * Copyright 2016 Freescale Semiconductor, Inc.
- * Copyright 2017 NXP
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __DT_BINDINGS_CLOCK_IMX8MQ_H
-#define __DT_BINDINGS_CLOCK_IMX8MQ_H
-
-#define IMX8MQ_CLK_DUMMY 0
-#define IMX8MQ_CLK_32K 1
-#define IMX8MQ_CLK_25M 2
-#define IMX8MQ_CLK_27M 3
-#define IMX8MQ_CLK_EXT1 4
-#define IMX8MQ_CLK_EXT2 5
-#define IMX8MQ_CLK_EXT3 6
-#define IMX8MQ_CLK_EXT4 7
-
-/* ANAMIX PLL clocks */
-/* FRAC PLLs */
-/* ARM PLL */
-#define IMX8MQ_ARM_PLL_REF_SEL 8
-#define IMX8MQ_ARM_PLL_REF_DIV 9
-#define IMX8MQ_ARM_PLL 10
-#define IMX8MQ_ARM_PLL_BYPASS 11
-#define IMX8MQ_ARM_PLL_OUT 12
-
-/* GPU PLL */
-#define IMX8MQ_GPU_PLL_REF_SEL 13
-#define IMX8MQ_GPU_PLL_REF_DIV 14
-#define IMX8MQ_GPU_PLL 15
-#define IMX8MQ_GPU_PLL_BYPASS 16
-#define IMX8MQ_GPU_PLL_OUT 17
-
-/* VPU PLL */
-#define IMX8MQ_VPU_PLL_REF_SEL 18
-#define IMX8MQ_VPU_PLL_REF_DIV 19
-#define IMX8MQ_VPU_PLL 20
-#define IMX8MQ_VPU_PLL_BYPASS 21
-#define IMX8MQ_VPU_PLL_OUT 22
-
-/* AUDIO PLL1 */
-#define IMX8MQ_AUDIO_PLL1_REF_SEL 23
-#define IMX8MQ_AUDIO_PLL1_REF_DIV 24
-#define IMX8MQ_AUDIO_PLL1 25
-#define IMX8MQ_AUDIO_PLL1_BYPASS 26
-#define IMX8MQ_AUDIO_PLL1_OUT 27
-
-/* AUDIO PLL2 */
-#define IMX8MQ_AUDIO_PLL2_REF_SEL 28
-#define IMX8MQ_AUDIO_PLL2_REF_DIV 29
-#define IMX8MQ_AUDIO_PLL2 30
-#define IMX8MQ_AUDIO_PLL2_BYPASS 31
-#define IMX8MQ_AUDIO_PLL2_OUT 32
-
-/* VIDEO PLL1 */
-#define IMX8MQ_VIDEO_PLL1_REF_SEL 33
-#define IMX8MQ_VIDEO_PLL1_REF_DIV 34
-#define IMX8MQ_VIDEO_PLL1 35
-#define IMX8MQ_VIDEO_PLL1_BYPASS 36
-#define IMX8MQ_VIDEO_PLL1_OUT 37
-
-/* SYS1 PLL */
-#define IMX8MQ_SYS1_PLL1_REF_SEL 38
-#define IMX8MQ_SYS1_PLL1_REF_DIV 39
-#define IMX8MQ_SYS1_PLL1 40
-#define IMX8MQ_SYS1_PLL1_OUT 41
-#define IMX8MQ_SYS1_PLL1_OUT_DIV 42
-#define IMX8MQ_SYS1_PLL2 43
-#define IMX8MQ_SYS1_PLL2_DIV 44
-#define IMX8MQ_SYS1_PLL2_OUT 45
-
-/* SYS2 PLL */
-#define IMX8MQ_SYS2_PLL1_REF_SEL 46
-#define IMX8MQ_SYS2_PLL1_REF_DIV 47
-#define IMX8MQ_SYS2_PLL1 48
-#define IMX8MQ_SYS2_PLL1_OUT 49
-#define IMX8MQ_SYS2_PLL1_OUT_DIV 50
-#define IMX8MQ_SYS2_PLL2 51
-#define IMX8MQ_SYS2_PLL2_DIV 52
-#define IMX8MQ_SYS2_PLL2_OUT 53
-
-/* SYS3 PLL */
-#define IMX8MQ_SYS3_PLL1_REF_SEL 54
-#define IMX8MQ_SYS3_PLL1_REF_DIV 55
-#define IMX8MQ_SYS3_PLL1 56
-#define IMX8MQ_SYS3_PLL1_OUT 57
-#define IMX8MQ_SYS3_PLL1_OUT_DIV 58
-#define IMX8MQ_SYS3_PLL2 59
-#define IMX8MQ_SYS3_PLL2_DIV 60
-#define IMX8MQ_SYS3_PLL2_OUT 61
-
-/* DRAM PLL */
-#define IMX8MQ_DRAM_PLL1_REF_SEL 62
-#define IMX8MQ_DRAM_PLL1_REF_DIV 63
-#define IMX8MQ_DRAM_PLL1 64
-#define IMX8MQ_DRAM_PLL1_OUT 65
-#define IMX8MQ_DRAM_PLL1_OUT_DIV 66
-#define IMX8MQ_DRAM_PLL2 67
-#define IMX8MQ_DRAM_PLL2_DIV 68
-#define IMX8MQ_DRAM_PLL2_OUT 69
-
-/* SYS PLL DIV */
-#define IMX8MQ_SYS1_PLL_40M 70
-#define IMX8MQ_SYS1_PLL_80M 71
-#define IMX8MQ_SYS1_PLL_100M 72
-#define IMX8MQ_SYS1_PLL_133M 73
-#define IMX8MQ_SYS1_PLL_160M 74
-#define IMX8MQ_SYS1_PLL_200M 75
-#define IMX8MQ_SYS1_PLL_266M 76
-#define IMX8MQ_SYS1_PLL_400M 77
-#define IMX8MQ_SYS1_PLL_800M 78
-
-#define IMX8MQ_SYS2_PLL_50M 79
-#define IMX8MQ_SYS2_PLL_100M 80
-#define IMX8MQ_SYS2_PLL_125M 81
-#define IMX8MQ_SYS2_PLL_166M 82
-#define IMX8MQ_SYS2_PLL_200M 83
-#define IMX8MQ_SYS2_PLL_250M 84
-#define IMX8MQ_SYS2_PLL_333M 85
-#define IMX8MQ_SYS2_PLL_500M 86
-#define IMX8MQ_SYS2_PLL_1000M 87
-
-/* CCM ROOT clocks */
-/* A53 */
-#define IMX8MQ_CLK_A53_SRC 88
-#define IMX8MQ_CLK_A53_CG 89
-#define IMX8MQ_CLK_A53_DIV 90
-/* M4 */
-#define IMX8MQ_CLK_M4_SRC 91
-#define IMX8MQ_CLK_M4_CG 92
-#define IMX8MQ_CLK_M4_DIV 93
-/* VPU */
-#define IMX8MQ_CLK_VPU_SRC 94
-#define IMX8MQ_CLK_VPU_CG 95
-#define IMX8MQ_CLK_VPU_DIV 96
-/* GPU CORE */
-#define IMX8MQ_CLK_GPU_CORE_SRC 97
-#define IMX8MQ_CLK_GPU_CORE_CG 98
-#define IMX8MQ_CLK_GPU_CORE_DIV 99
-/* GPU SHADER */
-#define IMX8MQ_CLK_GPU_SHADER_SRC 100
-#define IMX8MQ_CLK_GPU_SHADER_CG 101
-#define IMX8MQ_CLK_GPU_SHADER_DIV 102
-
-/* BUS TYPE */
-/* MAIN AXI */
-#define IMX8MQ_CLK_MAIN_AXI_SRC 103
-#define IMX8MQ_CLK_MAIN_AXI_CG 104
-#define IMX8MQ_CLK_MAIN_AXI_PRE_DIV 105
-#define IMX8MQ_CLK_MAIN_AXI_DIV 106
-/* ENET AXI */
-#define IMX8MQ_CLK_ENET_AXI_SRC 107
-#define IMX8MQ_CLK_ENET_AXI_CG 108
-#define IMX8MQ_CLK_ENET_AXI_PRE_DIV 109
-#define IMX8MQ_CLK_ENET_AXI_DIV 110
-/* NAND_USDHC_BUS */
-#define IMX8MQ_CLK_NAND_USDHC_BUS_SRC 111
-#define IMX8MQ_CLK_NAND_USDHC_BUS_CG 112
-#define IMX8MQ_CLK_NAND_USDHC_BUS_PRE_DIV 113
-#define IMX8MQ_CLK_NAND_USDHC_BUS_DIV 114
-/* VPU BUS */
-#define IMX8MQ_CLK_VPU_BUS_SRC 115
-#define IMX8MQ_CLK_VPU_BUS_CG 116
-#define IMX8MQ_CLK_VPU_BUS_PRE_DIV 117
-#define IMX8MQ_CLK_VPU_BUS_DIV 118
-/* DISP_AXI */
-#define IMX8MQ_CLK_DISP_AXI_SRC 119
-#define IMX8MQ_CLK_DISP_AXI_CG 120
-#define IMX8MQ_CLK_DISP_AXI_PRE_DIV 121
-#define IMX8MQ_CLK_DISP_AXI_DIV 122
-/* DISP APB */
-#define IMX8MQ_CLK_DISP_APB_SRC 123
-#define IMX8MQ_CLK_DISP_APB_CG 124
-#define IMX8MQ_CLK_DISP_APB_PRE_DIV 125
-#define IMX8MQ_CLK_DISP_APB_DIV 126
-/* DISP RTRM */
-#define IMX8MQ_CLK_DISP_RTRM_SRC 127
-#define IMX8MQ_CLK_DISP_RTRM_CG 128
-#define IMX8MQ_CLK_DISP_RTRM_PRE_DIV 129
-#define IMX8MQ_CLK_DISP_RTRM_DIV 130
-/* USB_BUS */
-#define IMX8MQ_CLK_USB_BUS_SRC 131
-#define IMX8MQ_CLK_USB_BUS_CG 132
-#define IMX8MQ_CLK_USB_BUS_PRE_DIV 133
-#define IMX8MQ_CLK_USB_BUS_DIV 134
-/* GPU_AXI */
-#define IMX8MQ_CLK_GPU_AXI_SRC 135
-#define IMX8MQ_CLK_GPU_AXI_CG 136
-#define IMX8MQ_CLK_GPU_AXI_PRE_DIV 137
-#define IMX8MQ_CLK_GPU_AXI_DIV 138
-/* GPU_AHB */
-#define IMX8MQ_CLK_GPU_AHB_SRC 139
-#define IMX8MQ_CLK_GPU_AHB_CG 140
-#define IMX8MQ_CLK_GPU_AHB_PRE_DIV 141
-#define IMX8MQ_CLK_GPU_AHB_DIV 142
-/* NOC */
-#define IMX8MQ_CLK_NOC_SRC 143
-#define IMX8MQ_CLK_NOC_CG 144
-#define IMX8MQ_CLK_NOC_PRE_DIV 145
-#define IMX8MQ_CLK_NOC_DIV 146
-/* NOC_APB */
-#define IMX8MQ_CLK_NOC_APB_SRC 147
-#define IMX8MQ_CLK_NOC_APB_CG 148
-#define IMX8MQ_CLK_NOC_APB_PRE_DIV 149
-#define IMX8MQ_CLK_NOC_APB_DIV 150
-
-/* AHB */
-#define IMX8MQ_CLK_AHB_SRC 151
-#define IMX8MQ_CLK_AHB_CG 152
-#define IMX8MQ_CLK_AHB_PRE_DIV 153
-#define IMX8MQ_CLK_AHB_DIV 154
-/* AUDIO AHB */
-#define IMX8MQ_CLK_AUDIO_AHB_SRC 155
-#define IMX8MQ_CLK_AUDIO_AHB_CG 156
-#define IMX8MQ_CLK_AUDIO_AHB_PRE_DIV 157
-#define IMX8MQ_CLK_AUDIO_AHB_DIV 158
-
-/* DRAM_ALT */
-#define IMX8MQ_CLK_DRAM_ALT_SRC 159
-#define IMX8MQ_CLK_DRAM_ALT_CG 160
-#define IMX8MQ_CLK_DRAM_ALT_PRE_DIV 161
-#define IMX8MQ_CLK_DRAM_ALT_DIV 162
-/* DRAM APB */
-#define IMX8MQ_CLK_DRAM_APB_SRC 163
-#define IMX8MQ_CLK_DRAM_APB_CG 164
-#define IMX8MQ_CLK_DRAM_APB_PRE_DIV 165
-#define IMX8MQ_CLK_DRAM_APB_DIV 166
-/* VPU_G1 */
-#define IMX8MQ_CLK_VPU_G1_SRC 167
-#define IMX8MQ_CLK_VPU_G1_CG 168
-#define IMX8MQ_CLK_VPU_G1_PRE_DIV 169
-#define IMX8MQ_CLK_VPU_G1_DIV 170
-/* VPU_G2 */
-#define IMX8MQ_CLK_VPU_G2_SRC 171
-#define IMX8MQ_CLK_VPU_G2_CG 172
-#define IMX8MQ_CLK_VPU_G2_PRE_DIV 173
-#define IMX8MQ_CLK_VPU_G2_DIV 174
-/* DISP_DTRC */
-#define IMX8MQ_CLK_DISP_DTRC_SRC 175
-#define IMX8MQ_CLK_DISP_DTRC_CG 176
-#define IMX8MQ_CLK_DISP_DTRC_PRE_DIV 177
-#define IMX8MQ_CLK_DISP_DTRC_DIV 178
-/* DISP_DC8000 */
-#define IMX8MQ_CLK_DISP_DC8000_SRC 179
-#define IMX8MQ_CLK_DISP_DC8000_CG 180
-#define IMX8MQ_CLK_DISP_DC8000_PRE_DIV 181
-#define IMX8MQ_CLK_DISP_DC8000_DIV 182
-/* PCIE_CTRL */
-#define IMX8MQ_CLK_PCIE1_CTRL_SRC 183
-#define IMX8MQ_CLK_PCIE1_CTRL_CG 184
-#define IMX8MQ_CLK_PCIE1_CTRL_PRE_DIV 185
-#define IMX8MQ_CLK_PCIE1_CTRL_DIV 186
-/* PCIE_PHY */
-#define IMX8MQ_CLK_PCIE1_PHY_SRC 187
-#define IMX8MQ_CLK_PCIE1_PHY_CG 188
-#define IMX8MQ_CLK_PCIE1_PHY_PRE_DIV 189
-#define IMX8MQ_CLK_PCIE1_PHY_DIV 190
-/* PCIE_AUX */
-#define IMX8MQ_CLK_PCIE1_AUX_SRC 191
-#define IMX8MQ_CLK_PCIE1_AUX_CG 192
-#define IMX8MQ_CLK_PCIE1_AUX_PRE_DIV 193
-#define IMX8MQ_CLK_PCIE1_AUX_DIV 194
-/* DC_PIXEL */
-#define IMX8MQ_CLK_DC_PIXEL_SRC 195
-#define IMX8MQ_CLK_DC_PIXEL_CG 196
-#define IMX8MQ_CLK_DC_PIXEL_PRE_DIV 197
-#define IMX8MQ_CLK_DC_PIXEL_DIV 198
-/* LCDIF_PIXEL */
-#define IMX8MQ_CLK_LCDIF_PIXEL_SRC 199
-#define IMX8MQ_CLK_LCDIF_PIXEL_CG 200
-#define IMX8MQ_CLK_LCDIF_PIXEL_PRE_DIV 201
-#define IMX8MQ_CLK_LCDIF_PIXEL_DIV 202
-/* SAI1~6 */
-#define IMX8MQ_CLK_SAI1_SRC 203
-#define IMX8MQ_CLK_SAI1_CG 204
-#define IMX8MQ_CLK_SAI1_PRE_DIV 205
-#define IMX8MQ_CLK_SAI1_DIV 206
-
-#define IMX8MQ_CLK_SAI2_SRC 207
-#define IMX8MQ_CLK_SAI2_CG 208
-#define IMX8MQ_CLK_SAI2_PRE_DIV 209
-#define IMX8MQ_CLK_SAI2_DIV 210
-
-#define IMX8MQ_CLK_SAI3_SRC 211
-#define IMX8MQ_CLK_SAI3_CG 212
-#define IMX8MQ_CLK_SAI3_PRE_DIV 213
-#define IMX8MQ_CLK_SAI3_DIV 214
-
-#define IMX8MQ_CLK_SAI4_SRC 215
-#define IMX8MQ_CLK_SAI4_CG 216
-#define IMX8MQ_CLK_SAI4_PRE_DIV 217
-#define IMX8MQ_CLK_SAI4_DIV 218
-
-#define IMX8MQ_CLK_SAI5_SRC 219
-#define IMX8MQ_CLK_SAI5_CG 220
-#define IMX8MQ_CLK_SAI5_PRE_DIV 221
-#define IMX8MQ_CLK_SAI5_DIV 222
-
-#define IMX8MQ_CLK_SAI6_SRC 223
-#define IMX8MQ_CLK_SAI6_CG 224
-#define IMX8MQ_CLK_SAI6_PRE_DIV 225
-#define IMX8MQ_CLK_SAI6_DIV 226
-/* SPDIF1 */
-#define IMX8MQ_CLK_SPDIF1_SRC 227
-#define IMX8MQ_CLK_SPDIF1_CG 228
-#define IMX8MQ_CLK_SPDIF1_PRE_DIV 229
-#define IMX8MQ_CLK_SPDIF1_DIV 230
-/* SPDIF2 */
-#define IMX8MQ_CLK_SPDIF2_SRC 231
-#define IMX8MQ_CLK_SPDIF2_CG 232
-#define IMX8MQ_CLK_SPDIF2_PRE_DIV 233
-#define IMX8MQ_CLK_SPDIF2_DIV 234
-/* ENET_REF */
-#define IMX8MQ_CLK_ENET_REF_SRC 235
-#define IMX8MQ_CLK_ENET_REF_CG 236
-#define IMX8MQ_CLK_ENET_REF_PRE_DIV 237
-#define IMX8MQ_CLK_ENET_REF_DIV 238
-/* ENET_TIMER */
-#define IMX8MQ_CLK_ENET_TIMER_SRC 239
-#define IMX8MQ_CLK_ENET_TIMER_CG 240
-#define IMX8MQ_CLK_ENET_TIMER_PRE_DIV 241
-#define IMX8MQ_CLK_ENET_TIMER_DIV 242
-/* ENET_PHY */
-#define IMX8MQ_CLK_ENET_PHY_REF_SRC 243
-#define IMX8MQ_CLK_ENET_PHY_REF_CG 244
-#define IMX8MQ_CLK_ENET_PHY_REF_PRE_DIV 245
-#define IMX8MQ_CLK_ENET_PHY_REF_DIV 246
-/* NAND */
-#define IMX8MQ_CLK_NAND_SRC 247
-#define IMX8MQ_CLK_NAND_CG 248
-#define IMX8MQ_CLK_NAND_PRE_DIV 249
-#define IMX8MQ_CLK_NAND_DIV 250
-/* QSPI */
-#define IMX8MQ_CLK_QSPI_SRC 251
-#define IMX8MQ_CLK_QSPI_CG 252
-#define IMX8MQ_CLK_QSPI_PRE_DIV 253
-#define IMX8MQ_CLK_QSPI_DIV 254
-/* USDHC1 */
-#define IMX8MQ_CLK_USDHC1_SRC 255
-#define IMX8MQ_CLK_USDHC1_CG 256
-#define IMX8MQ_CLK_USDHC1_PRE_DIV 257
-#define IMX8MQ_CLK_USDHC1_DIV 258
-/* USDHC2 */
-#define IMX8MQ_CLK_USDHC2_SRC 259
-#define IMX8MQ_CLK_USDHC2_CG 260
-#define IMX8MQ_CLK_USDHC2_PRE_DIV 261
-#define IMX8MQ_CLK_USDHC2_DIV 262
-/* I2C1 */
-#define IMX8MQ_CLK_I2C1_SRC 263
-#define IMX8MQ_CLK_I2C1_CG 264
-#define IMX8MQ_CLK_I2C1_PRE_DIV 265
-#define IMX8MQ_CLK_I2C1_DIV 266
-/* I2C2 */
-#define IMX8MQ_CLK_I2C2_SRC 267
-#define IMX8MQ_CLK_I2C2_CG 268
-#define IMX8MQ_CLK_I2C2_PRE_DIV 269
-#define IMX8MQ_CLK_I2C2_DIV 270
-/* I2C3 */
-#define IMX8MQ_CLK_I2C3_SRC 271
-#define IMX8MQ_CLK_I2C3_CG 272
-#define IMX8MQ_CLK_I2C3_PRE_DIV 273
-#define IMX8MQ_CLK_I2C3_DIV 274
-/* I2C4 */
-#define IMX8MQ_CLK_I2C4_SRC 275
-#define IMX8MQ_CLK_I2C4_CG 276
-#define IMX8MQ_CLK_I2C4_PRE_DIV 277
-#define IMX8MQ_CLK_I2C4_DIV 278
-/* UART1 */
-#define IMX8MQ_CLK_UART1_SRC 279
-#define IMX8MQ_CLK_UART1_CG 280
-#define IMX8MQ_CLK_UART1_PRE_DIV 281
-#define IMX8MQ_CLK_UART1_DIV 282
-/* UART2 */
-#define IMX8MQ_CLK_UART2_SRC 283
-#define IMX8MQ_CLK_UART2_CG 284
-#define IMX8MQ_CLK_UART2_PRE_DIV 285
-#define IMX8MQ_CLK_UART2_DIV 286
-/* UART3 */
-#define IMX8MQ_CLK_UART3_SRC 287
-#define IMX8MQ_CLK_UART3_CG 288
-#define IMX8MQ_CLK_UART3_PRE_DIV 289
-#define IMX8MQ_CLK_UART3_DIV 290
-/* UART4 */
-#define IMX8MQ_CLK_UART4_SRC 291
-#define IMX8MQ_CLK_UART4_CG 292
-#define IMX8MQ_CLK_UART4_PRE_DIV 293
-#define IMX8MQ_CLK_UART4_DIV 294
-/* USB_CORE_REF */
-#define IMX8MQ_CLK_USB_CORE_REF_SRC 295
-#define IMX8MQ_CLK_USB_CORE_REF_CG 296
-#define IMX8MQ_CLK_USB_CORE_REF_PRE_DIV 297
-#define IMX8MQ_CLK_USB_CORE_REF_DIV 298
-/* USB_PHY_REF */
-#define IMX8MQ_CLK_USB_PHY_REF_SRC 299
-#define IMX8MQ_CLK_USB_PHY_REF_CG 300
-#define IMX8MQ_CLK_USB_PHY_REF_PRE_DIV 301
-#define IMX8MQ_CLK_USB_PHY_REF_DIV 302
-/* ECSPI1 */
-#define IMX8MQ_CLK_ECSPI1_SRC 303
-#define IMX8MQ_CLK_ECSPI1_CG 304
-#define IMX8MQ_CLK_ECSPI1_PRE_DIV 305
-#define IMX8MQ_CLK_ECSPI1_DIV 306
-/* ECSPI2 */
-#define IMX8MQ_CLK_ECSPI2_SRC 307
-#define IMX8MQ_CLK_ECSPI2_CG 308
-#define IMX8MQ_CLK_ECSPI2_PRE_DIV 309
-#define IMX8MQ_CLK_ECSPI2_DIV 310
-/* PWM1 */
-#define IMX8MQ_CLK_PWM1_SRC 311
-#define IMX8MQ_CLK_PWM1_CG 312
-#define IMX8MQ_CLK_PWM1_PRE_DIV 313
-#define IMX8MQ_CLK_PWM1_DIV 314
-/* PWM2 */
-#define IMX8MQ_CLK_PWM2_SRC 315
-#define IMX8MQ_CLK_PWM2_CG 316
-#define IMX8MQ_CLK_PWM2_PRE_DIV 317
-#define IMX8MQ_CLK_PWM2_DIV 318
-/* PWM3 */
-#define IMX8MQ_CLK_PWM3_SRC 319
-#define IMX8MQ_CLK_PWM3_CG 320
-#define IMX8MQ_CLK_PWM3_PRE_DIV 321
-#define IMX8MQ_CLK_PWM3_DIV 322
-/* PWM4 */
-#define IMX8MQ_CLK_PWM4_SRC 323
-#define IMX8MQ_CLK_PWM4_CG 324
-#define IMX8MQ_CLK_PWM4_PRE_DIV 325
-#define IMX8MQ_CLK_PWM4_DIV 326
-/* GPT1 */
-#define IMX8MQ_CLK_GPT1_SRC 327
-#define IMX8MQ_CLK_GPT1_CG 328
-#define IMX8MQ_CLK_GPT1_PRE_DIV 329
-#define IMX8MQ_CLK_GPT1_DIV 330
-/* WDOG */
-#define IMX8MQ_CLK_WDOG_SRC 331
-#define IMX8MQ_CLK_WDOG_CG 332
-#define IMX8MQ_CLK_WDOG_PRE_DIV 333
-#define IMX8MQ_CLK_WDOG_DIV 334
-/* WRCLK */
-#define IMX8MQ_CLK_WRCLK_SRC 335
-#define IMX8MQ_CLK_WRCLK_CG 336
-#define IMX8MQ_CLK_WRCLK_PRE_DIV 337
-#define IMX8MQ_CLK_WRCLK_DIV 338
-/* DSI_CORE */
-#define IMX8MQ_CLK_DSI_CORE_SRC 339
-#define IMX8MQ_CLK_DSI_CORE_CG 340
-#define IMX8MQ_CLK_DSI_CORE_PRE_DIV 341
-#define IMX8MQ_CLK_DSI_CORE_DIV 342
-/* DSI_PHY */
-#define IMX8MQ_CLK_DSI_PHY_REF_SRC 343
-#define IMX8MQ_CLK_DSI_PHY_REF_CG 344
-#define IMX8MQ_CLK_DSI_PHY_REF_PRE_DIV 345
-#define IMX8MQ_CLK_DSI_PHY_REF_DIV 346
-/* DSI_DBI */
-#define IMX8MQ_CLK_DSI_DBI_SRC 347
-#define IMX8MQ_CLK_DSI_DBI_CG 348
-#define IMX8MQ_CLK_DSI_DBI_PRE_DIV 349
-#define IMX8MQ_CLK_DSI_DBI_DIV 350
-/*DSI_ESC */
-#define IMX8MQ_CLK_DSI_ESC_SRC 351
-#define IMX8MQ_CLK_DSI_ESC_CG 352
-#define IMX8MQ_CLK_DSI_ESC_PRE_DIV 353
-#define IMX8MQ_CLK_DSI_ESC_DIV 354
-/* CSI1_CORE */
-#define IMX8MQ_CLK_CSI1_CORE_SRC 355
-#define IMX8MQ_CLK_CSI1_CORE_CG 356
-#define IMX8MQ_CLK_CSI1_CORE_PRE_DIV 357
-#define IMX8MQ_CLK_CSI1_CORE_DIV 358
-/* CSI1_PHY */
-#define IMX8MQ_CLK_CSI1_PHY_REF_SRC 359
-#define IMX8MQ_CLK_CSI1_PHY_REF_CG 360
-#define IMX8MQ_CLK_CSI1_PHY_REF_PRE_DIV 361
-#define IMX8MQ_CLK_CSI1_PHY_REF_DIV 362
-/* CSI_ESC */
-#define IMX8MQ_CLK_CSI1_ESC_SRC 363
-#define IMX8MQ_CLK_CSI1_ESC_CG 364
-#define IMX8MQ_CLK_CSI1_ESC_PRE_DIV 365
-#define IMX8MQ_CLK_CSI1_ESC_DIV 366
-/* CSI2_CORE */
-#define IMX8MQ_CLK_CSI2_CORE_SRC 367
-#define IMX8MQ_CLK_CSI2_CORE_CG 368
-#define IMX8MQ_CLK_CSI2_CORE_PRE_DIV 369
-#define IMX8MQ_CLK_CSI2_CORE_DIV 370
-/* CSI2_PHY */
-#define IMX8MQ_CLK_CSI2_PHY_REF_SRC 371
-#define IMX8MQ_CLK_CSI2_PHY_REF_CG 372
-#define IMX8MQ_CLK_CSI2_PHY_REF_PRE_DIV 373
-#define IMX8MQ_CLK_CSI2_PHY_REF_DIV 374
-/* CSI2_ESC */
-#define IMX8MQ_CLK_CSI2_ESC_SRC 375
-#define IMX8MQ_CLK_CSI2_ESC_CG 376
-#define IMX8MQ_CLK_CSI2_ESC_PRE_DIV 377
-#define IMX8MQ_CLK_CSI2_ESC_DIV 378
-/* PCIE2_CTRL */
-#define IMX8MQ_CLK_PCIE2_CTRL_SRC 379
-#define IMX8MQ_CLK_PCIE2_CTRL_CG 380
-#define IMX8MQ_CLK_PCIE2_CTRL_PRE_DIV 381
-#define IMX8MQ_CLK_PCIE2_CTRL_DIV 382
-/* PCIE2_PHY */
-#define IMX8MQ_CLK_PCIE2_PHY_SRC 383
-#define IMX8MQ_CLK_PCIE2_PHY_CG 384
-#define IMX8MQ_CLK_PCIE2_PHY_PRE_DIV 385
-#define IMX8MQ_CLK_PCIE2_PHY_DIV 386
-/* PCIE2_AUX */
-#define IMX8MQ_CLK_PCIE2_AUX_SRC 387
-#define IMX8MQ_CLK_PCIE2_AUX_CG 388
-#define IMX8MQ_CLK_PCIE2_AUX_PRE_DIV 389
-#define IMX8MQ_CLK_PCIE2_AUX_DIV 390
-/* ECSPI3 */
-#define IMX8MQ_CLK_ECSPI3_SRC 391
-#define IMX8MQ_CLK_ECSPI3_CG 392
-#define IMX8MQ_CLK_ECSPI3_PRE_DIV 393
-#define IMX8MQ_CLK_ECSPI3_DIV 394
-
-/* CCGR clocks */
-#define IMX8MQ_CLK_A53_ROOT 395
-#define IMX8MQ_CLK_DRAM_ROOT 396
-#define IMX8MQ_CLK_ECSPI1_ROOT 397
-#define IMX8MQ_CLK_ECSPI2_ROOT 398
-#define IMX8MQ_CLK_ECSPI3_ROOT 399
-#define IMX8MQ_CLK_ENET1_ROOT 400
-#define IMX8MQ_CLK_GPT1_ROOT 401
-#define IMX8MQ_CLK_I2C1_ROOT 402
-#define IMX8MQ_CLK_I2C2_ROOT 403
-#define IMX8MQ_CLK_I2C3_ROOT 404
-#define IMX8MQ_CLK_I2C4_ROOT 405
-#define IMX8MQ_CLK_M4_ROOT 406
-#define IMX8MQ_CLK_PCIE1_ROOT 407
-#define IMX8MQ_CLK_PCIE2_ROOT 408
-#define IMX8MQ_CLK_PWM1_ROOT 409
-#define IMX8MQ_CLK_PWM2_ROOT 410
-#define IMX8MQ_CLK_PWM3_ROOT 411
-#define IMX8MQ_CLK_PWM4_ROOT 412
-#define IMX8MQ_CLK_QSPI_ROOT 413
-#define IMX8MQ_CLK_SAI1_ROOT 414
-#define IMX8MQ_CLK_SAI2_ROOT 415
-#define IMX8MQ_CLK_SAI3_ROOT 416
-#define IMX8MQ_CLK_SAI4_ROOT 417
-#define IMX8MQ_CLK_SAI5_ROOT 418
-#define IMX8MQ_CLK_SAI6_ROOT 419
-#define IMX8MQ_CLK_UART1_ROOT 420
-#define IMX8MQ_CLK_UART2_ROOT 421
-#define IMX8MQ_CLK_UART3_ROOT 422
-#define IMX8MQ_CLK_UART4_ROOT 423
-#define IMX8MQ_CLK_USB1_CTRL_ROOT 424
-#define IMX8MQ_CLK_USB2_CTRL_ROOT 425
-#define IMX8MQ_CLK_USB1_PHY_ROOT 426
-#define IMX8MQ_CLK_USB2_PHY_ROOT 427
-#define IMX8MQ_CLK_USDHC1_ROOT 428
-#define IMX8MQ_CLK_USDHC2_ROOT 429
-#define IMX8MQ_CLK_WDOG1_ROOT 430
-#define IMX8MQ_CLK_WDOG2_ROOT 431
-#define IMX8MQ_CLK_WDOG3_ROOT 432
-#define IMX8MQ_CLK_GPU_ROOT 433
-#define IMX8MQ_CLK_HEVC_ROOT 434
-#define IMX8MQ_CLK_AVC_ROOT 435
-#define IMX8MQ_CLK_VP9_ROOT 436
-#define IMX8MQ_CLK_HEVC_INTER_ROOT 437
-#define IMX8MQ_CLK_DISP_ROOT 438
-#define IMX8MQ_CLK_HDMI_ROOT 439
-#define IMX8MQ_CLK_HDMI_PHY_ROOT 440
-#define IMX8MQ_CLK_VPU_DEC_ROOT 441
-#define IMX8MQ_CLK_CSI1_ROOT 442
-#define IMX8MQ_CLK_CSI2_ROOT 443
-#define IMX8MQ_CLK_RAWNAND_ROOT 444
-#define IMX8MQ_CLK_SDMA1_ROOT 445
-#define IMX8MQ_CLK_SDMA2_ROOT 446
-#define IMX8MQ_CLK_VPU_G1_ROOT 447
-#define IMX8MQ_CLK_VPU_G2_ROOT 448
-
-/* SCCG PLL GATE */
-#define IMX8MQ_SYS1_PLL_OUT 449
-#define IMX8MQ_SYS2_PLL_OUT 450
-#define IMX8MQ_SYS3_PLL_OUT 451
-#define IMX8MQ_DRAM_PLL_OUT 452
-
-#define IMX8MQ_GPT_3M_CLK 453
-
-#define IMX8MQ_CLK_IPG_ROOT 454
-#define IMX8MQ_CLK_IPG_AUDIO_ROOT 455
-#define IMX8MQ_CLK_SAI1_IPG 456
-#define IMX8MQ_CLK_SAI2_IPG 457
-#define IMX8MQ_CLK_SAI3_IPG 458
-#define IMX8MQ_CLK_SAI4_IPG 459
-#define IMX8MQ_CLK_SAI5_IPG 460
-#define IMX8MQ_CLK_SAI6_IPG 461
-
-/* DSI AHB/IPG clocks */
-/* rxesc clock */
-#define IMX8MQ_CLK_DSI_AHB_SRC 462
-#define IMX8MQ_CLK_DSI_AHB_CG 463
-#define IMX8MQ_CLK_DSI_AHB_PRE_DIV 464
-#define IMX8MQ_CLK_DSI_AHB_DIV 465
-/* txesc clock */
-#define IMX8MQ_CLK_DSI_IPG_DIV 466
-
-/* VIDEO2 PLL */
-#define IMX8MQ_VIDEO2_PLL1_REF_SEL 467
-#define IMX8MQ_VIDEO2_PLL1_REF_DIV 468
-#define IMX8MQ_VIDEO2_PLL1 469
-#define IMX8MQ_VIDEO2_PLL1_OUT 470
-#define IMX8MQ_VIDEO2_PLL1_OUT_DIV 471
-#define IMX8MQ_VIDEO2_PLL2 472
-#define IMX8MQ_VIDEO2_PLL2_DIV 473
-#define IMX8MQ_VIDEO2_PLL2_OUT 474
-#define IMX8MQ_CLK_TMU_ROOT 475
-
-#define IMX8MQ_CLK_END 476
-#endif /* __DT_BINDINGS_CLOCK_IMX8MQ_H */
diff --git a/include/dt-bindings/clock/imx8qm-clock.h b/include/dt-bindings/clock/imx8qm-clock.h
deleted file mode 100644
index 58de976..0000000
--- a/include/dt-bindings/clock/imx8qm-clock.h
+++ /dev/null
@@ -1,846 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2018 NXP
- */
-
-#ifndef __DT_BINDINGS_CLOCK_IMX8QM_H
-#define __DT_BINDINGS_CLOCK_IMX8QM_H
-
-#define IMX8QM_CLK_DUMMY 0
-
-#define IMX8QM_A53_DIV 1
-#define IMX8QM_A53_CLK 2
-#define IMX8QM_A72_DIV 3
-#define IMX8QM_A72_CLK 4
-
-/* SC Clocks. */
-#define IMX8QM_SC_I2C_DIV 5
-#define IMX8QM_SC_I2C_CLK 6
-#define IMX8QM_SC_PID0_DIV 7
-#define IMX8QM_SC_PID0_CLK 8
-#define IMX8QM_SC_PIT_DIV 9
-#define IMX8QM_SC_PIT_CLK 10
-#define IMX8QM_SC_TPM_DIV 11
-#define IMX8QM_SC_TPM_CLK 12
-#define IMX8QM_SC_UART_DIV 13
-#define IMX8QM_SC_UART_CLK 14
-
-/* LSIO */
-#define IMX8QM_PWM0_DIV 15
-#define IMX8QM_PWM0_CLK 16
-#define IMX8QM_PWM1_DIV 17
-#define IMX8QM_PWM1_CLK 18
-#define IMX8QM_PWM2_DIV 19
-#define IMX8QM_PWM2_CLK 20
-#define IMX8QM_PWM3_DIV 21
-#define IMX8QM_PWM3_CLK 22
-#define IMX8QM_PWM4_DIV 23
-#define IMX8QM_PWM4_CLK 24
-#define IMX8QM_PWM5_DIV 26
-#define IMX8QM_PWM5_CLK 27
-#define IMX8QM_PWM6_DIV 28
-#define IMX8QM_PWM6_CLK 29
-#define IMX8QM_PWM7_DIV 30
-#define IMX8QM_PWM7_CLK 31
-#define IMX8QM_FSPI0_DIV 32
-#define IMX8QM_FSPI0_CLK 33
-#define IMX8QM_FSPI1_DIV 34
-#define IMX8QM_FSPI1_CLK 35
-#define IMX8QM_GPT0_DIV 36
-#define IMX8QM_GPT0_CLK 37
-#define IMX8QM_GPT1_DIV 38
-#define IMX8QM_GPT1_CLK 39
-#define IMX8QM_GPT2_DIV 40
-#define IMX8QM_GPT2_CLK 41
-#define IMX8QM_GPT3_DIV 42
-#define IMX8QM_GPT3_CLK 43
-#define IMX8QM_GPT4_DIV 44
-#define IMX8QM_GPT4_CLK 45
-
-/* Connectivity */
-#define IMX8QM_APBHDMA_CLK 46
-#define IMX8QM_GPMI_APB_CLK 47
-#define IMX8QM_GPMI_APB_BCH_CLK 48
-#define IMX8QM_GPMI_BCH_IO_DIV 49
-#define IMX8QM_GPMI_BCH_IO_CLK 50
-#define IMX8QM_GPMI_BCH_DIV 51
-#define IMX8QM_GPMI_BCH_CLK 52
-#define IMX8QM_SDHC0_IPG_CLK 53
-#define IMX8QM_SDHC0_DIV 54
-#define IMX8QM_SDHC0_CLK 55
-#define IMX8QM_SDHC1_IPG_CLK 56
-#define IMX8QM_SDHC1_DIV 57
-#define IMX8QM_SDHC1_CLK 58
-#define IMX8QM_SDHC2_IPG_CLK 59
-#define IMX8QM_SDHC2_DIV 60
-#define IMX8QM_SDHC2_CLK 61
-#define IMX8QM_USB2_OH_AHB_CLK 62
-#define IMX8QM_USB2_OH_IPG_S_CLK 63
-#define IMX8QM_USB2_OH_IPG_S_PL301_CLK 64
-#define IMX8QM_USB2_PHY_IPG_CLK 65
-#define IMX8QM_USB3_IPG_CLK 66
-#define IMX8QM_USB3_CORE_PCLK 67
-#define IMX8QM_USB3_PHY_CLK 68
-#define IMX8QM_USB3_ACLK_DIV 69
-#define IMX8QM_USB3_ACLK 70
-#define IMX8QM_USB3_BUS_DIV 71
-#define IMX8QM_USB3_BUS_CLK 72
-#define IMX8QM_USB3_LPM_DIV 73
-#define IMX8QM_USB3_LPM_CLK 74
-#define IMX8QM_ENET0_AHB_CLK 75
-#define IMX8QM_ENET0_IPG_S_CLK 76
-#define IMX8QM_ENET0_IPG_CLK 77
-#define IMX8QM_ENET0_RGMII_DIV 78
-#define IMX8QM_ENET0_RGMII_TX_CLK 79
-#define IMX8QM_ENET0_ROOT_DIV 80
-#define IMX8QM_ENET0_TX_CLK 81
-#define IMX8QM_ENET0_ROOT_CLK 82
-#define IMX8QM_ENET0_PTP_CLK 83
-#define IMX8QM_ENET0_BYPASS_DIV 84
-#define IMX8QM_ENET1_AHB_CLK 85
-#define IMX8QM_ENET1_IPG_S_CLK 86
-#define IMX8QM_ENET1_IPG_CLK 87
-#define IMX8QM_ENET1_RGMII_DIV 88
-#define IMX8QM_ENET1_RGMII_TX_CLK 89
-#define IMX8QM_ENET1_ROOT_DIV 90
-#define IMX8QM_ENET1_TX_CLK 91
-#define IMX8QM_ENET1_ROOT_CLK 92
-#define IMX8QM_ENET1_PTP_CLK 93
-#define IMX8QM_ENET1_BYPASS_DIV 94
-#define IMX8QM_MLB_CLK 95
-#define IMX8QM_MLB_HCLK 96
-#define IMX8QM_MLB_IPG_CLK 97
-#define IMX8QM_EDMA_CLK 98
-#define IMX8QM_EDMA_IPG_CLK 99
-
-/* DMA */
-#define IMX8QM_SPI0_IPG_CLK 100
-#define IMX8QM_SPI0_DIV 101
-#define IMX8QM_SPI0_CLK 102
-#define IMX8QM_SPI1_IPG_CLK 103
-#define IMX8QM_SPI1_DIV 104
-#define IMX8QM_SPI1_CLK 105
-#define IMX8QM_SPI2_IPG_CLK 106
-#define IMX8QM_SPI2_DIV 107
-#define IMX8QM_SPI2_CLK 108
-#define IMX8QM_SPI3_IPG_CLK 109
-#define IMX8QM_SPI3_DIV 110
-#define IMX8QM_SPI3_CLK 111
-#define IMX8QM_UART0_IPG_CLK 112
-#define IMX8QM_UART0_DIV 113
-#define IMX8QM_UART0_CLK 114
-#define IMX8QM_UART1_IPG_CLK 115
-#define IMX8QM_UART1_DIV 116
-#define IMX8QM_UART1_CLK 117
-#define IMX8QM_UART2_IPG_CLK 118
-#define IMX8QM_UART2_DIV 119
-#define IMX8QM_UART2_CLK 120
-#define IMX8QM_UART3_IPG_CLK 121
-#define IMX8QM_UART3_DIV 122
-#define IMX8QM_UART3_CLK 123
-#define IMX8QM_UART4_IPG_CLK 124
-#define IMX8QM_UART4_DIV 125
-#define IMX8QM_EMVSIM0_IPG_CLK 126
-#define IMX8QM_UART4_CLK 127
-#define IMX8QM_EMVSIM0_DIV 128
-#define IMX8QM_EMVSIM0_CLK 129
-#define IMX8QM_EMVSIM1_IPG_CLK 130
-#define IMX8QM_EMVSIM1_DIV 131
-#define IMX8QM_EMVSIM1_CLK 132
-#define IMX8QM_CAN0_IPG_CHI_CLK 133
-#define IMX8QM_CAN0_IPG_CLK 134
-#define IMX8QM_CAN0_DIV 135
-#define IMX8QM_CAN0_CLK 136
-#define IMX8QM_CAN1_IPG_CHI_CLK 137
-#define IMX8QM_CAN1_IPG_CLK 138
-#define IMX8QM_CAN1_DIV 139
-#define IMX8QM_CAN1_CLK 140
-#define IMX8QM_CAN2_IPG_CHI_CLK 141
-#define IMX8QM_CAN2_IPG_CLK 142
-#define IMX8QM_CAN2_DIV 143
-#define IMX8QM_CAN2_CLK 144
-#define IMX8QM_I2C0_IPG_CLK 145
-#define IMX8QM_I2C0_DIV 146
-#define IMX8QM_I2C0_CLK 147
-#define IMX8QM_I2C1_IPG_CLK 148
-#define IMX8QM_I2C1_DIV 149
-#define IMX8QM_I2C1_CLK 150
-#define IMX8QM_I2C2_IPG_CLK 151
-#define IMX8QM_I2C2_DIV 152
-#define IMX8QM_I2C2_CLK 153
-#define IMX8QM_I2C3_IPG_CLK 154
-#define IMX8QM_I2C3_DIV 155
-#define IMX8QM_I2C3_CLK 156
-#define IMX8QM_I2C4_IPG_CLK 157
-#define IMX8QM_I2C4_DIV 158
-#define IMX8QM_I2C4_CLK 159
-#define IMX8QM_FTM0_IPG_CLK 160
-#define IMX8QM_FTM0_DIV 161
-#define IMX8QM_FTM0_CLK 162
-#define IMX8QM_FTM1_IPG_CLK 163
-#define IMX8QM_FTM1_DIV 164
-#define IMX8QM_FTM1_CLK 165
-#define IMX8QM_ADC0_IPG_CLK 166
-#define IMX8QM_ADC0_DIV 167
-#define IMX8QM_ADC0_CLK 168
-#define IMX8QM_ADC1_IPG_CLK 169
-#define IMX8QM_ADC1_DIV 170
-#define IMX8QM_ADC1_CLK 171
-
-/* Audio */
-#define IMX8QM_AUD_PLL0_DIV 172
-#define IMX8QM_AUD_PLL0 173
-#define IMX8QM_AUD_PLL1_DIV 174
-#define IMX8QM_AUD_PLL1 175
-#define IMX8QM_AUD_AMIX_IPG 182
-#define IMX8QM_AUD_ESAI_0_IPG 183
-#define IMX8QM_AUD_ESAI_1_IPG 184
-#define IMX8QM_AUD_ESAI_0_EXTAL_IPG 185
-#define IMX8QM_AUD_ESAI_1_EXTAL_IPG 186
-#define IMX8QM_AUD_SAI_0_IPG 187
-#define IMX8QM_AUD_SAI_0_IPG_S 188
-#define IMX8QM_AUD_SAI_0_MCLK 189
-#define IMX8QM_AUD_SAI_1_IPG 190
-#define IMX8QM_AUD_SAI_1_IPG_S 191
-#define IMX8QM_AUD_SAI_1_MCLK 192
-#define IMX8QM_AUD_SAI_2_IPG 193
-#define IMX8QM_AUD_SAI_2_IPG_S 194
-#define IMX8QM_AUD_SAI_2_MCLK 195
-#define IMX8QM_AUD_SAI_3_IPG 196
-#define IMX8QM_AUD_SAI_3_IPG_S 197
-#define IMX8QM_AUD_SAI_3_MCLK 198
-#define IMX8QM_AUD_SAI_6_IPG 199
-#define IMX8QM_AUD_SAI_6_IPG_S 200
-#define IMX8QM_AUD_SAI_6_MCLK 201
-#define IMX8QM_AUD_SAI_7_IPG 202
-#define IMX8QM_AUD_SAI_7_IPG_S 203
-#define IMX8QM_AUD_SAI_7_MCLK 204
-#define IMX8QM_AUD_SAI_HDMIRX0_IPG 205
-#define IMX8QM_AUD_SAI_HDMIRX0_IPG_S 206
-#define IMX8QM_AUD_SAI_HDMIRX0_MCLK 207
-#define IMX8QM_AUD_SAI_HDMITX0_IPG 208
-#define IMX8QM_AUD_SAI_HDMITX0_IPG_S 209
-#define IMX8QM_AUD_SAI_HDMITX0_MCLK 210
-#define IMX8QM_AUD_MQS_IPG 211
-#define IMX8QM_AUD_MQS_HMCLK 212
-#define IMX8QM_AUD_GPT5_IPG_S 213
-#define IMX8QM_AUD_GPT5_CLKIN 214
-#define IMX8QM_AUD_GPT5_24M_CLK 215
-#define IMX8QM_AUD_GPT6_IPG_S 216
-#define IMX8QM_AUD_GPT6_CLKIN 217
-#define IMX8QM_AUD_GPT6_24M_CLK 218
-#define IMX8QM_AUD_GPT7_IPG_S 219
-#define IMX8QM_AUD_GPT7_CLKIN 220
-#define IMX8QM_AUD_GPT7_24M_CLK 221
-#define IMX8QM_AUD_GPT8_IPG_S 222
-#define IMX8QM_AUD_GPT8_CLKIN 223
-#define IMX8QM_AUD_GPT8_24M_CLK 224
-#define IMX8QM_AUD_GPT9_IPG_S 225
-#define IMX8QM_AUD_GPT9_CLKIN 226
-#define IMX8QM_AUD_GPT9_24M_CLK 227
-#define IMX8QM_AUD_GPT10_IPG_S 228
-#define IMX8QM_AUD_GPT10_CLKIN 229
-#define IMX8QM_AUD_GPT10_24M_CLK 230
-#define IMX8QM_AUD_ACM_AUD_PLL_CLK0_DIV 232
-#define IMX8QM_AUD_ACM_AUD_PLL_CLK0_CLK 233
-#define IMX8QM_AUD_ACM_AUD_PLL_CLK1_DIV 234
-#define IMX8QM_AUD_ACM_AUD_PLL_CLK1_CLK 235
-#define IMX8QM_AUD_ACM_AUD_REC_CLK0_DIV 236
-#define IMX8QM_AUD_ACM_AUD_REC_CLK0_CLK 237
-#define IMX8QM_AUD_ACM_AUD_REC_CLK1_DIV 238
-#define IMX8QM_AUD_ACM_AUD_REC_CLK1_CLK 239
-#define IMX8QM_AUD_MCLKOUT0 240
-#define IMX8QM_AUD_MCLKOUT1 241
-#define IMX8QM_AUD_SPDIF_0_TX_CLK 242
-#define IMX8QM_AUD_SPDIF_0_GCLKW 243
-#define IMX8QM_AUD_SPDIF_0_IPG_S 244
-#define IMX8QM_AUD_SPDIF_1_TX_CLK 245
-#define IMX8QM_AUD_SPDIF_1_GCLKW 246
-#define IMX8QM_AUD_SPDIF_1_IPG_S 247
-#define IMX8QM_AUD_ASRC_0_IPG 248
-#define IMX8QM_AUD_ASRC_0_MEM 249
-#define IMX8QM_AUD_ASRC_1_IPG 250
-#define IMX8QM_AUD_ASRC_1_MEM 251
-
-/* VPU */
-#define IMX8QM_VPU_CORE_DIV 252
-#define IMX8QM_VPU_CORE_CLK 253
-#define IMX8QM_VPU_UART_DIV 254
-#define IMX8QM_VPU_UART_CLK 255
-#define IMX8QM_VPU_DDR_DIV 256
-#define IMX8QM_VPU_DDR_CLK 257
-#define IMX8QM_VPU_SYS_DIV 258
-#define IMX8QM_VPU_SYS_CLK 259
-#define IMX8QM_VPU_XUVI_DIV 260
-#define IMX8QM_VPU_XUVI_CLK 261
-
-/* GPU Clocks. */
-#define IMX8QM_GPU0_CORE_DIV 262
-#define IMX8QM_GPU0_CORE_CLK 263
-#define IMX8QM_GPU0_SHADER_DIV 264
-#define IMX8QM_GPU0_SHADER_CLK 265
-#define IMX8QM_GPU1_CORE_DIV 266
-#define IMX8QM_GPU1_CORE_CLK 267
-#define IMX8QM_GPU1_SHADER_DIV 268
-#define IMX8QM_GPU1_SHADER_CLK 269
-
-/* MIPI CSI */
-#define IMX8QM_CSI0_IPG_CLK_S 270
-#define IMX8QM_CSI0_LIS_IPG_CLK 271
-#define IMX8QM_CSI0_APB_CLK 272
-#define IMX8QM_CSI0_I2C0_DIV 273
-#define IMX8QM_CSI0_I2C0_CLK 274
-#define IMX8QM_CSI0_PWM0_DIV 275
-#define IMX8QM_CSI0_PWM0_CLK 276
-#define IMX8QM_CSI0_CORE_DIV 277
-#define IMX8QM_CSI0_CORE_CLK 278
-#define IMX8QM_CSI0_ESC_DIV 279
-#define IMX8QM_CSI0_ESC_CLK 280
-#define IMX8QM_CSI1_IPG_CLK_S 281
-#define IMX8QM_CSI1_LIS_IPG_CLK 282
-#define IMX8QM_CSI1_APB_CLK 283
-#define IMX8QM_CSI1_I2C0_DIV 284
-#define IMX8QM_CSI1_I2C0_CLK 285
-#define IMX8QM_CSI1_PWM0_DIV 286
-#define IMX8QM_CSI1_PWM0_CLK 287
-#define IMX8QM_CSI1_CORE_DIV 288
-#define IMX8QM_CSI1_CORE_CLK 289
-#define IMX8QM_CSI1_ESC_DIV 290
-#define IMX8QM_CSI1_ESC_CLK 291
-
-/* Display */
-#define IMX8QM_DC0_PLL0_DIV 292
-#define IMX8QM_DC0_PLL0_CLK 293
-#define IMX8QM_DC0_PLL1_DIV 294
-#define IMX8QM_DC0_PLL1_CLK 295
-#define IMX8QM_DC0_DISP0_DIV 296
-#define IMX8QM_DC0_DISP0_CLK 297
-#define IMX8QM_DC0_DISP1_DIV 298
-#define IMX8QM_DC0_DISP1_CLK 299
-#define IMX8QM_DC0_BYPASS_0_DIV 300
-#define IMX8QM_DC0_BYPASS_1_DIV 301
-#define IMX8QM_DC0_IRIS_AXI_CLK 302
-#define IMX8AM_DC0_IRIS_MVPL_CLK 303
-#define IMX8QM_DC0_DISP0_MSI_CLK 304
-#define IMX8QM_DC0_LIS_IPG_CLK 305
-#define IMX8QM_DC0_PXL_CMB_APB_CLK 306
-#define IMX8QM_DC0_PRG0_RTRAM_CLK 307
-#define IMX8QM_DC0_PRG1_RTRAM_CLK 308
-#define IMX8QM_DC0_PRG2_RTRAM_CLK 309
-#define IMX8QM_DC0_PRG3_RTRAM_CLK 310
-#define IMX8QM_DC0_PRG4_RTRAM_CLK 311
-#define IMX8QM_DC0_PRG5_RTRAM_CLK 312
-#define IMX8QM_DC0_PRG6_RTRAM_CLK 313
-#define IMX8QM_DC0_PRG7_RTRAM_CLK 314
-#define IMX8QM_DC0_PRG8_RTRAM_CLK 315
-#define IMX8QM_DC0_PRG0_APB_CLK 316
-#define IMX8QM_DC0_PRG1_APB_CLK 317
-#define IMX8QM_DC0_PRG2_APB_CLK 318
-#define IMX8QM_DC0_PRG3_APB_CLK 319
-#define IMX8QM_DC0_PRG4_APB_CLK 320
-#define IMX8QM_DC0_PRG5_APB_CLK 321
-#define IMX8QM_DC0_PRG6_APB_CLK 322
-#define IMX8QM_DC0_PRG7_APB_CLK 323
-#define IMX8QM_DC0_PRG8_APB_CLK 324
-#define IMX8QM_DC0_DPR0_APB_CLK 325
-#define IMX8QM_DC0_DPR1_APB_CLK 326
-#define IMX8QM_DC0_RTRAM0_CLK 327
-#define IMX8QM_DC0_RTRAM1_CLK 328
-#define IMX8QM_DC1_PLL0_DIV 329
-#define IMX8QM_DC1_PLL0_CLK 330
-#define IMX8QM_DC1_PLL1_DIV 331
-#define IMX8QM_DC1_PLL1_CLK 332
-#define IMX8QM_DC1_DISP0_DIV 333
-#define IMX8QM_DC1_DISP0_CLK 334
-#define IMX8QM_DC1_BYPASS_0_DIV 335
-#define IMX8QM_DC1_BYPASS_1_DIV 336
-#define IMX8QM_DC1_DISP1_DIV 337
-#define IMX8QM_DC1_DISP1_CLK 338
-#define IMX8QM_DC1_IRIS_AXI_CLK 339
-#define IMX8AM_DC1_IRIS_MVPL_CLK 340
-#define IMX8QM_DC1_DISP0_MSI_CLK 341
-#define IMX8QM_DC1_LIS_IPG_CLK 342
-#define IMX8QM_DC1_PXL_CMB_APB_CLK 343
-#define IMX8QM_DC1_PRG0_RTRAM_CLK 344
-#define IMX8QM_DC1_PRG1_RTRAM_CLK 345
-#define IMX8QM_DC1_PRG2_RTRAM_CLK 346
-#define IMX8QM_DC1_PRG3_RTRAM_CLK 347
-#define IMX8QM_DC1_PRG4_RTRAM_CLK 348
-#define IMX8QM_DC1_PRG5_RTRAM_CLK 349
-#define IMX8QM_DC1_PRG6_RTRAM_CLK 350
-#define IMX8QM_DC1_PRG7_RTRAM_CLK 351
-#define IMX8QM_DC1_PRG8_RTRAM_CLK 352
-#define IMX8QM_DC1_PRG0_APB_CLK 353
-#define IMX8QM_DC1_PRG1_APB_CLK 354
-#define IMX8QM_DC1_PRG2_APB_CLK 355
-#define IMX8QM_DC1_PRG3_APB_CLK 356
-#define IMX8QM_DC1_PRG4_APB_CLK 357
-#define IMX8QM_DC1_PRG5_APB_CLK 358
-#define IMX8QM_DC1_PRG6_APB_CLK 359
-#define IMX8QM_DC1_PRG7_APB_CLK 360
-#define IMX8QM_DC1_PRG8_APB_CLK 361
-#define IMX8QM_DC1_DPR0_APB_CLK 362
-#define IMX8QM_DC1_DPR1_APB_CLK 363
-#define IMX8QM_DC1_RTRAM0_CLK 364
-#define IMX8QM_DC1_RTRAM1_CLK 365
-
-/* DRC */
-#define IMX8QM_DRC0_PLL0_DIV 366
-#define IMX8QM_DRC0_PLL0_CLK 367
-#define IMX8QM_DRC0_DIV 368
-#define IMX8QM_DRC0_CLK 369
-#define IMX8QM_DRC1_PLL0_DIV 370
-#define IMX8QM_DRC1_PLL0_CLK 371
-#define IMX8QM_DRC1_DIV 372
-#define IMX8QM_DRC1_CLK 373
-
-/* HDMI */
-#define IMX8QM_HDMI_AV_PLL_DIV 374
-#define IMX8QM_HDMI_AV_PLL_CLK 375
-#define IMX8QM_HDMI_I2S_BYPASS_CLK 376
-#define IMX8QM_HDMI_I2C0_DIV 377
-#define IMX8QM_HDMI_I2C0_CLK 378
-#define IMX8QM_HDMI_PXL_DIV 379
-#define IMX8QM_HDMI_PXL_CLK 380
-#define IMX8QM_HDMI_PXL_LINK_DIV 381
-#define IMX8QM_HDMI_PXL_LINK_CLK 382
-#define IMX8QM_HDMI_PXL_MUX_DIV 383
-#define IMX8QM_HDMI_PXL_MUX_CLK 384
-#define IMX8QM_HDMI_I2S_DIV 385
-#define IMX8QM_HDMI_I2S_CLK 386
-#define IMX8QM_HDMI_HDP_CORE_DIV 387
-#define IMX8QM_HDMI_HDP_CORE_CLK 388
-#define IMX8QM_HDMI_I2C_IPG_S_CLK 389
-#define IMX8QM_HDMI_I2C_IPG_CLK 390
-#define IMX8QM_HDMI_PWM_IPG_S_CLK 391
-#define IMX8QM_HDMI_PWM_IPG_CLK 392
-#define IMX8QM_HDMI_PWM_32K_CLK 393
-#define IMX8QM_HDMI_GPIO_IPG_CLK 394
-#define IMX8QM_HDMI_PXL_LINK_SLV_ODD_CLK 395
-#define IMX8QM_HDMI_PXL_LINK_SLV_EVEN_CLK 396
-#define IMX8QM_HDMI_LIS_IPG_CLK 397
-#define IMX8QM_HDMI_MSI_HCLK 398
-#define IMX8QM_HDMI_PXL_EVEN_CLK 399
-#define IMX8QM_HDMI_HDP_CLK 400
-#define IMX8QM_HDMI_PXL_DBL_CLK 401
-#define IMX8QM_HDMI_APB_CLK 402
-#define IMX8QM_HDMI_PXL_LPCG_CLK 403
-#define IMX8QM_HDMI_HDP_PHY_CLK 404
-#define IMX8QM_HDMI_IPG_DIV 405
-#define IMX8QM_HDMI_VIF_CLK 406
-#define IMX8QM_HDMI_DIG_PLL_DIV 407
-#define IMX8QM_HDMI_DIG_PLL_CLK 408
-#define IMX8QM_HDMI_APB_MUX_CSR_CLK 409
-#define IMX8QM_HDMI_APB_MUX_CTRL_CLK 410
-
-/* RX-HDMI */
-#define IMX8QM_HDMI_RX_I2S_BYPASS_CLK 411
-#define IMX8QM_HDMI_RX_BYPASS_CLK 412
-#define IMX8QM_HDMI_RX_SPDIF_BYPASS_CLK 413
-#define IMX8QM_HDMI_RX_I2C0_DIV 414
-#define IMX8QM_HDMI_RX_I2C0_CLK 415
-#define IMX8QM_HDMI_RX_SPDIF_DIV 416
-#define IMX8QM_HDMI_RX_SPDIF_CLK 417
-#define IMX8QM_HDMI_RX_HD_REF_DIV 418
-#define IMX8QM_HDMI_RX_HD_REF_CLK 419
-#define IMX8QM_HDMI_RX_HD_CORE_DIV 420
-#define IMX8QM_HDMI_RX_HD_CORE_CLK 421
-#define IMX8QM_HDMI_RX_PXL_DIV 422
-#define IMX8QM_HDMI_RX_PXL_CLK 423
-#define IMX8QM_HDMI_RX_I2S_DIV 424
-#define IMX8QM_HDMI_RX_I2S_CLK 425
-#define IMX8QM_HDMI_RX_PWM_DIV 426
-#define IMX8QM_HDMI_RX_PWM_CLK 427
-
-/* LVDS */
-#define IMX8QM_LVDS0_BYPASS_CLK 428
-#define IMX8QM_LVDS0_PIXEL_DIV 429
-#define IMX8QM_LVDS0_PIXEL_CLK 430
-#define IMX8QM_LVDS0_PHY_DIV 431
-#define IMX8QM_LVDS0_PHY_CLK 432
-#define IMX8QM_LVDS0_I2C0_IPG_CLK 433
-#define IMX8QM_LVDS0_I2C0_DIV 434
-#define IMX8QM_LVDS0_I2C0_CLK 435
-#define IMX8QM_LVDS0_I2C1_IPG_CLK 436
-#define IMX8QM_LVDS0_I2C1_DIV 437
-#define IMX8QM_LVDS0_I2C1_CLK 438
-#define IMX8QM_LVDS0_PWM0_IPG_CLK 439
-#define IMX8QM_LVDS0_PWM0_DIV 440
-#define IMX8QM_LVDS0_PWM0_CLK 441
-#define IMX8QM_LVDS0_GPIO_IPG_CLK 444
-#define IMX8QM_LVDS1_BYPASS_DIV 445
-#define IMX8QM_LVDS1_BYPASS_CLK 446
-#define IMX8QM_LVDS1_PIXEL_DIV 447
-#define IMX8QM_LVDS1_PIXEL_CLK 448
-#define IMX8QM_LVDS1_PHY_DIV 449
-#define IMX8QM_LVDS1_PHY_CLK 450
-#define IMX8QM_LVDS1_I2C0_IPG_CLK 451
-#define IMX8QM_LVDS1_I2C0_DIV 452
-#define IMX8QM_LVDS1_I2C0_CLK 453
-#define IMX8QM_LVDS1_I2C1_IPG_CLK 454
-#define IMX8QM_LVDS1_I2C1_DIV 455
-#define IMX8QM_LVDS1_I2C1_CLK 456
-#define IMX8QM_LVDS1_PWM0_IPG_CLK 457
-#define IMX8QM_LVDS1_PWM0_DIV 458
-#define IMX8QM_LVDS1_PWM0_CLK 459
-#define IMX8QM_LVDS1_GPIO_IPG_CLK 462
-
-/* MIPI */
-#define IMX8QM_MIPI0_BYPASS_CLK 465
-#define IMX8QM_MIPI0_I2C0_DIV 466
-#define IMX8QM_MIPI0_I2C0_CLK 467
-#define IMX8QM_MIPI0_I2C1_DIV 468
-#define IMX8QM_MIPI0_I2C1_CLK 469
-#define IMX8QM_MIPI0_PWM0_DIV 470
-#define IMX8QM_MIPI0_PWM0_CLK 471
-#define IMX8QM_MIPI0_DSI_TX_ESC_DIV 472
-#define IMX8QM_MIPI0_DSI_TX_ESC_CLK 473
-#define IMX8QM_MIPI0_DSI_RX_ESC_DIV 474
-#define IMX8QM_MIPI0_DSI_RX_ESC_CLK 475
-#define IMX8QM_MIPI0_PXL_DIV 476
-#define IMX8QM_MIPI0_PXL_CLK 477
-#define IMX8QM_MIPI1_BYPASS_CLK 479
-#define IMX8QM_MIPI1_I2C0_DIV 480
-#define IMX8QM_MIPI1_I2C0_CLK 481
-#define IMX8QM_MIPI1_I2C1_DIV 482
-#define IMX8QM_MIPI1_I2C1_CLK 483
-#define IMX8QM_MIPI1_PWM0_DIV 484
-#define IMX8QM_MIPI1_PWM0_CLK 485
-#define IMX8QM_MIPI1_DSI_TX_ESC_DIV 486
-#define IMX8QM_MIPI1_DSI_TX_ESC_CLK 487
-#define IMX8QM_MIPI1_DSI_RX_ESC_DIV 488
-#define IMX8QM_MIPI1_DSI_RX_ESC_CLK 489
-#define IMX8QM_MIPI1_PXL_DIV 490
-#define IMX8QM_MIPI1_PXL_CLK 491
-
-/* Imaging */
-#define IMX8QM_IMG_JPEG_ENC_IPG_CLK 492
-#define IMX8QM_IMG_JPEG_ENC_CLK 493
-#define IMX8QM_IMG_JPEG_DEC_IPG_CLK 494
-#define IMX8QM_IMG_JPEG_DEC_CLK 495
-#define IMX8QM_IMG_PXL_LINK_DC0_CLK 496
-#define IMX8QM_IMG_PXL_LINK_DC1_CLK 497
-#define IMX8QM_IMG_PXL_LINK_CSI0_CLK 498
-#define IMX8QM_IMG_PXL_LINK_CSI1_CLK 499
-#define IMX8QM_IMG_PXL_LINK_HDMI_IN_CLK 500
-#define IMX8QM_IMG_PDMA_0_CLK 501
-#define IMX8QM_IMG_PDMA_1_CLK 502
-#define IMX8QM_IMG_PDMA_2_CLK 503
-#define IMX8QM_IMG_PDMA_3_CLK 504
-#define IMX8QM_IMG_PDMA_4_CLK 505
-#define IMX8QM_IMG_PDMA_5_CLK 506
-#define IMX8QM_IMG_PDMA_6_CLK 507
-#define IMX8QM_IMG_PDMA_7_CLK 508
-
-/* HSIO */
-#define IMX8QM_HSIO_PCIE_A_MSTR_AXI_CLK 509
-#define IMX8QM_HSIO_PCIE_A_SLV_AXI_CLK 510
-#define IMX8QM_HSIO_PCIE_A_DBI_AXI_CLK 511
-#define IMX8QM_HSIO_PCIE_B_MSTR_AXI_CLK 512
-#define IMX8QM_HSIO_PCIE_B_SLV_AXI_CLK 513
-#define IMX8QM_HSIO_PCIE_B_DBI_AXI_CLK 514
-#define IMX8QM_HSIO_PCIE_X1_PER_CLK 515
-#define IMX8QM_HSIO_PCIE_X2_PER_CLK 516
-#define IMX8QM_HSIO_SATA_PER_CLK 517
-#define IMX8QM_HSIO_PHY_X1_PER_CLK 518
-#define IMX8QM_HSIO_PHY_X2_PER_CLK 519
-#define IMX8QM_HSIO_MISC_PER_CLK 520
-#define IMX8QM_HSIO_PHY_X1_APB_CLK 521
-#define IMX8QM_HSIO_PHY_X2_APB_0_CLK 522
-#define IMX8QM_HSIO_PHY_X2_APB_1_CLK 523
-#define IMX8QM_HSIO_SATA_CLK 524
-#define IMX8QM_HSIO_GPIO_CLK 525
-#define IMX8QM_HSIO_PHY_X1_PCLK 526
-#define IMX8QM_HSIO_PHY_X2_PCLK_0 527
-#define IMX8QM_HSIO_PHY_X2_PCLK_1 528
-#define IMX8QM_HSIO_SATA_EPCS_RX_CLK 529
-#define IMX8QM_HSIO_SATA_EPCS_TX_CLK 530
-
-/* M4 */
-#define IMX8QM_M4_0_CORE_DIV 531
-#define IMX8QM_M4_0_CORE_CLK 532
-#define IMX8QM_M4_0_I2C_DIV 533
-#define IMX8QM_M4_0_I2C_CLK 534
-#define IMX8QM_M4_0_PIT_DIV 535
-#define IMX8QM_M4_0_PIT_CLK 536
-#define IMX8QM_M4_0_TPM_DIV 537
-#define IMX8QM_M4_0_TPM_CLK 538
-#define IMX8QM_M4_0_UART_DIV 539
-#define IMX8QM_M4_0_UART_CLK 540
-#define IMX8QM_M4_0_WDOG_DIV 541
-#define IMX8QM_M4_0_WDOG_CLK 542
-#define IMX8QM_M4_1_CORE_DIV 543
-#define IMX8QM_M4_1_CORE_CLK 544
-#define IMX8QM_M4_1_I2C_DIV 545
-#define IMX8QM_M4_1_I2C_CLK 546
-#define IMX8QM_M4_1_PIT_DIV 547
-#define IMX8QM_M4_1_PIT_CLK 548
-#define IMX8QM_M4_1_TPM_DIV 549
-#define IMX8QM_M4_1_TPM_CLK 550
-#define IMX8QM_M4_1_UART_DIV 551
-#define IMX8QM_M4_1_UART_CLK 552
-#define IMX8QM_M4_1_WDOG_DIV 553
-#define IMX8QM_M4_1_WDOG_CLK 554
-
-/* IPG clocks */
-#define IMX8QM_24MHZ 555
-#define IMX8QM_GPT_3M 556
-#define IMX8QM_IPG_DMA_CLK_ROOT 557
-#define IMX8QM_IPG_AUD_CLK_ROOT 558
-#define IMX8QM_IPG_CONN_CLK_ROOT 559
-#define IMX8QM_AHB_CONN_CLK_ROOT 560
-#define IMX8QM_AXI_CONN_CLK_ROOT 561
-#define IMX8QM_IPG_MIPI_CSI_CLK_ROOT 562
-#define IMX8QM_DC_AXI_EXT_CLK 563
-#define IMX8QM_DC_AXI_INT_CLK 564
-#define IMX8QM_DC_CFG_CLK 565
-#define IMX8QM_HDMI_IPG_CLK 566
-#define IMX8QM_LVDS_IPG_CLK 567
-#define IMX8QM_IMG_AXI_CLK 568
-#define IMX8QM_IMG_IPG_CLK 569
-#define IMX8QM_IMG_PXL_CLK 570
-#define IMX8QM_CSI0_I2C0_IPG_CLK 571
-#define IMX8QM_CSI0_PWM0_IPG_CLK 572
-#define IMX8QM_CSI1_I2C0_IPG_CLK 573
-#define IMX8QM_CSI1_PWM0_IPG_CLK 574
-#define IMX8QM_DC0_DPR0_B_CLK 575
-#define IMX8QM_DC0_DPR1_B_CLK 576
-#define IMX8QM_DC1_DPR0_B_CLK 577
-#define IMX8QM_DC1_DPR1_B_CLK 578
-#define IMX8QM_32KHZ 579
-#define IMX8QM_HSIO_AXI_CLK 580
-#define IMX8QM_HSIO_PER_CLK 581
-#define IMX8QM_HDMI_RX_GPIO_IPG_S_CLK 582
-#define IMX8QM_HDMI_RX_PWM_IPG_S_CLK 583
-#define IMX8QM_HDMI_RX_PWM_IPG_CLK 584
-#define IMX8QM_HDMI_RX_I2C_DIV_CLK 585
-#define IMX8QM_HDMI_RX_I2C_IPG_S_CLK 586
-#define IMX8QM_HDMI_RX_I2C_IPG_CLK 587
-#define IMX8QM_HDMI_RX_SINK_PCLK 588
-#define IMX8QM_HDMI_RX_SINK_SCLK 589
-#define IMX8QM_HDMI_RX_PXL_ENC_CLK 590
-#define IMX8QM_HDMI_RX_IPG_CLK 591
-
-/* ACM */
-#define IMX8QM_HDMI_RX_MCLK 592
-#define IMX8QM_EXT_AUD_MCLK0 593
-#define IMX8QM_EXT_AUD_MCLK1 594
-#define IMX8QM_ESAI0_RX_CLK 595
-#define IMX8QM_ESAI0_RX_HF_CLK 596
-#define IMX8QM_ESAI0_TX_CLK 597
-#define IMX8QM_ESAI0_TX_HF_CLK 598
-#define IMX8QM_ESAI1_RX_CLK 599
-#define IMX8QM_ESAI1_RX_HF_CLK 600
-#define IMX8QM_ESAI1_TX_CLK 601
-#define IMX8QM_ESAI1_TX_HF_CLK 602
-#define IMX8QM_SPDIF0_RX 603
-#define IMX8QM_SPDIF1_RX 604
-#define IMX8QM_SAI0_RX_BCLK 605
-#define IMX8QM_SAI0_TX_BCLK 606
-#define IMX8QM_SAI1_RX_BCLK 607
-#define IMX8QM_SAI1_TX_BCLK 608
-#define IMX8QM_SAI2_RX_BCLK 609
-#define IMX8QM_SAI3_RX_BCLK 610
-#define IMX8QM_HDMI_RX_SAI0_RX_BCLK 611
-#define IMX8QM_SAI6_RX_BCLK 612
-#define IMX8QM_HDMI_TX_SAI0_TX_BCLK 613
-
-#define IMX8QM_ACM_AUD_CLK0_SEL 614
-#define IMX8QM_ACM_AUD_CLK0_CLK 615
-#define IMX8QM_ACM_AUD_CLK1_SEL 616
-#define IMX8QM_ACM_AUD_CLK1_CLK 617
-#define IMX8QM_ACM_MCLKOUT0_SEL 618
-#define IMX8QM_ACM_MCLKOUT0_CLK 619
-#define IMX8QM_ACM_MCLKOUT1_SEL 620
-#define IMX8QM_ACM_MCLKOUT1_CLK 621
-#define IMX8QM_ACM_ASRC0_MUX_CLK_SEL 622
-#define IMX8QM_ACM_ASRC0_MUX_CLK_CLK 623
-#define IMX8QM_ACM_ASRC1_MUX_CLK_SEL 624
-#define IMX8QM_ACM_ASRC1_MUX_CLK_CLK 625
-#define IMX8QM_ACM_ESAI0_MCLK_SEL 626
-#define IMX8QM_ACM_ESAI0_MCLK_CLK 627
-#define IMX8QM_ACM_ESAI1_MCLK_SEL 628
-#define IMX8QM_ACM_ESAI1_MCLK_CLK 629
-#define IMX8QM_ACM_GPT0_MUX_CLK_SEL 630
-#define IMX8QM_ACM_GPT0_MUX_CLK_CLK 631
-#define IMX8QM_ACM_GPT1_MUX_CLK_SEL 632
-#define IMX8QM_ACM_GPT1_MUX_CLK_CLK 633
-#define IMX8QM_ACM_GPT2_MUX_CLK_SEL 634
-#define IMX8QM_ACM_GPT2_MUX_CLK_CLK 635
-#define IMX8QM_ACM_GPT3_MUX_CLK_SEL 636
-#define IMX8QM_ACM_GPT3_MUX_CLK_CLK 637
-#define IMX8QM_ACM_GPT4_MUX_CLK_SEL 638
-#define IMX8QM_ACM_GPT4_MUX_CLK_CLK 639
-#define IMX8QM_ACM_GPT5_MUX_CLK_SEL 640
-#define IMX8QM_ACM_GPT5_MUX_CLK_CLK 641
-#define IMX8QM_ACM_SAI0_MCLK_SEL 642
-#define IMX8QM_ACM_SAI0_MCLK_CLK 643
-#define IMX8QM_ACM_SAI1_MCLK_SEL 644
-#define IMX8QM_ACM_SAI1_MCLK_CLK 645
-#define IMX8QM_ACM_SAI2_MCLK_SEL 646
-#define IMX8QM_ACM_SAI2_MCLK_CLK 647
-#define IMX8QM_ACM_SAI3_MCLK_SEL 648
-#define IMX8QM_ACM_SAI3_MCLK_CLK 649
-#define IMX8QM_ACM_HDMI_RX_SAI0_MCLK_SEL 650
-#define IMX8QM_ACM_HDMI_RX_SAI0_MCLK_CLK 651
-#define IMX8QM_ACM_HDMI_TX_SAI0_MCLK_SEL 652
-#define IMX8QM_ACM_HDMI_TX_SAI0_MCLK_CLK 653
-#define IMX8QM_ACM_SAI6_MCLK_SEL 654
-#define IMX8QM_ACM_SAI6_MCLK_CLK 655
-#define IMX8QM_ACM_SAI7_MCLK_SEL 656
-#define IMX8QM_ACM_SAI7_MCLK_CLK 657
-#define IMX8QM_ACM_SPDIF0_TX_CLK_SEL 658
-#define IMX8QM_ACM_SPDIF0_TX_CLK_CLK 659
-#define IMX8QM_ACM_SPDIF1_TX_CLK_SEL 660
-#define IMX8QM_ACM_SPDIF1_TX_CLK_CLK 661
-#define IMX8QM_ACM_MQS_TX_CLK_SEL 662
-#define IMX8QM_ACM_MQS_TX_CLK_CLK 663
-
-#define IMX8QM_ENET0_REF_25MHZ_125MHZ_SEL 664
-#define IMX8QM_ENET0_REF_25MHZ_125MHZ_CLK 665
-#define IMX8QM_ENET1_REF_25MHZ_125MHZ_SEL 666
-#define IMX8QM_ENET1_REF_25MHZ_125MHZ_CLK 667
-#define IMX8QM_ENET0_REF_50MHZ_CLK 668
-#define IMX8QM_ENET1_REF_50MHZ_CLK 669
-#define IMX8QM_ENET_25MHZ_CLK 670
-#define IMX8QM_ENET_125MHZ_CLK 671
-#define IMX8QM_ENET0_REF_DIV 672
-#define IMX8QM_ENET0_REF_CLK 673
-#define IMX8QM_ENET1_REF_DIV 674
-#define IMX8QM_ENET1_REF_CLK 675
-#define IMX8QM_ENET0_RMII_TX_CLK 676
-#define IMX8QM_ENET1_RMII_TX_CLK 677
-#define IMX8QM_ENET0_RMII_TX_SEL 678
-#define IMX8QM_ENET1_RMII_TX_SEL 679
-#define IMX8QM_ENET0_RMII_RX_CLK 680
-#define IMX8QM_ENET1_RMII_RX_CLK 681
-
-#define IMX8QM_KPP_CLK 683
-#define IMX8QM_GPT0_HF_CLK 684
-#define IMX8QM_GPT0_IPG_S_CLK 685
-#define IMX8QM_GPT0_IPG_SLV_CLK 686
-#define IMX8QM_GPT0_IPG_MSTR_CLK 687
-#define IMX8QM_GPT1_HF_CLK 688
-#define IMX8QM_GPT1_IPG_S_CLK 689
-#define IMX8QM_GPT1_IPG_SLV_CLK 690
-#define IMX8QM_GPT1_IPG_MSTR_CLK 691
-#define IMX8QM_GPT2_HF_CLK 692
-#define IMX8QM_GPT2_IPG_S_CLK 693
-#define IMX8QM_GPT2_IPG_SLV_CLK 694
-#define IMX8QM_GPT2_IPG_MSTR_CLK 695
-#define IMX8QM_GPT3_HF_CLK 696
-#define IMX8QM_GPT3_IPG_S_CLK 697
-#define IMX8QM_GPT3_IPG_SLV_CLK 698
-#define IMX8QM_GPT3_IPG_MSTR_CLK 699
-#define IMX8QM_GPT4_HF_CLK 700
-#define IMX8QM_GPT4_IPG_S_CLK 701
-#define IMX8QM_GPT4_IPG_SLV_CLK 702
-#define IMX8QM_GPT4_IPG_MSTR_CLK 703
-#define IMX8QM_PWM0_HF_CLK 704
-#define IMX8QM_PWM0_IPG_S_CLK 705
-#define IMX8QM_PWM0_IPG_SLV_CLK 706
-#define IMX8QM_PWM0_IPG_MSTR_CLK 707
-#define IMX8QM_PWM1_HF_CLK 708
-#define IMX8QM_PWM1_IPG_S_CLK 709
-#define IMX8QM_PWM1_IPG_SLV_CLK 710
-#define IMX8QM_PWM1_IPG_MSTR_CLK 711
-#define IMX8QM_PWM2_HF_CLK 712
-#define IMX8QM_PWM2_IPG_S_CLK 713
-#define IMX8QM_PWM2_IPG_SLV_CLK 714
-#define IMX8QM_PWM2_IPG_MSTR_CLK 715
-#define IMX8QM_PWM3_HF_CLK 716
-#define IMX8QM_PWM3_IPG_S_CLK 717
-#define IMX8QM_PWM3_IPG_SLV_CLK 718
-#define IMX8QM_PWM3_IPG_MSTR_CLK 719
-#define IMX8QM_PWM4_HF_CLK 720
-#define IMX8QM_PWM4_IPG_S_CLK 721
-#define IMX8QM_PWM4_IPG_SLV_CLK 722
-#define IMX8QM_PWM4_IPG_MSTR_CLK 723
-#define IMX8QM_PWM5_HF_CLK 724
-#define IMX8QM_PWM5_IPG_S_CLK 725
-#define IMX8QM_PWM5_IPG_SLV_CLK 726
-#define IMX8QM_PWM5_IPG_MSTR_CLK 727
-#define IMX8QM_PWM6_HF_CLK 728
-#define IMX8QM_PWM6_IPG_S_CLK 729
-#define IMX8QM_PWM6_IPG_SLV_CLK 730
-#define IMX8QM_PWM6_IPG_MSTR_CLK 731
-#define IMX8QM_PWM7_HF_CLK 732
-#define IMX8QM_PWM7_IPG_S_CLK 733
-#define IMX8QM_PWM7_IPG_SLV_CLK 734
-#define IMX8QM_PWM7_IPG_MSTR_CLK 735
-#define IMX8QM_FSPI0_HCLK 736
-#define IMX8QM_FSPI0_IPG_CLK 737
-#define IMX8QM_FSPI0_IPG_S_CLK 738
-#define IMX8QM_FSPI1_HCLK 736
-#define IMX8QM_FSPI1_IPG_CLK 737
-#define IMX8QM_FSPI1_IPG_S_CLK 738
-#define IMX8QM_GPIO0_IPG_S_CLK 739
-#define IMX8QM_GPIO1_IPG_S_CLK 740
-#define IMX8QM_GPIO2_IPG_S_CLK 741
-#define IMX8QM_GPIO3_IPG_S_CLK 742
-#define IMX8QM_GPIO4_IPG_S_CLK 743
-#define IMX8QM_GPIO5_IPG_S_CLK 744
-#define IMX8QM_GPIO6_IPG_S_CLK 745
-#define IMX8QM_GPIO7_IPG_S_CLK 746
-#define IMX8QM_ROMCP_CLK 747
-#define IMX8QM_ROMCP_REG_CLK 748
-#define IMX8QM_96KROM_CLK 749
-#define IMX8QM_OCRAM_MEM_CLK 750
-#define IMX8QM_OCRAM_CTRL_CLK 751
-#define IMX8QM_LSIO_BUS_CLK 752
-#define IMX8QM_LSIO_MEM_CLK 753
-#define IMX8QM_LVDS0_LIS_IPG_CLK 754
-#define IMX8QM_LVDS1_LIS_IPG_CLK 755
-#define IMX8QM_MIPI0_LIS_IPG_CLK 756
-#define IMX8QM_MIPI0_I2C0_IPG_S_CLK 757
-#define IMX8QM_MIPI0_I2C0_IPG_CLK 758
-#define IMX8QM_MIPI0_I2C1_IPG_S_CLK 759
-#define IMX8QM_MIPI0_I2C1_IPG_CLK 760
-#define IMX8QM_MIPI0_CLK_ROOT 761
-#define IMX8QM_MIPI1_LIS_IPG_CLK 762
-#define IMX8QM_MIPI1_I2C0_IPG_S_CLK 763
-#define IMX8QM_MIPI1_I2C0_IPG_CLK 764
-#define IMX8QM_MIPI1_I2C1_IPG_S_CLK 765
-#define IMX8QM_MIPI1_I2C1_IPG_CLK 766
-#define IMX8QM_MIPI1_CLK_ROOT 767
-#define IMX8QM_DC0_DISP0_SEL 768
-#define IMX8QM_DC0_DISP1_SEL 769
-#define IMX8QM_DC1_DISP0_SEL 770
-#define IMX8QM_DC1_DISP1_SEL 771
-
-/* CM40 */
-#define IMX8QM_CM40_IPG_CLK 772
-#define IMX8QM_CM40_I2C_DIV 773
-#define IMX8QM_CM40_I2C_CLK 774
-#define IMX8QM_CM40_I2C_IPG_CLK 775
-
-/* CM41 */
-#define IMX8QM_CM41_IPG_CLK 776
-#define IMX8QM_CM41_I2C_DIV 777
-#define IMX8QM_CM41_I2C_CLK 778
-#define IMX8QM_CM41_I2C_IPG_CLK 779
-
-#define IMX8QM_HDMI_PXL_SEL 780
-#define IMX8QM_HDMI_PXL_LINK_SEL 781
-#define IMX8QM_HDMI_PXL_MUX_SEL 782
-#define IMX8QM_HDMI_AV_PLL_BYPASS_CLK 783
-
-#define IMX8QM_HDMI_RX_PXL_SEL 784
-#define IMX8QM_HDMI_RX_HD_REF_SEL 785
-#define IMX8QM_HDMI_RX_HD_CORE_SEL 786
-#define IMX8QM_HDMI_RX_DIG_PLL_CLK 787
-
-#define IMX8QM_LSIO_MU5A_IPG_S_CLK 788
-#define IMX8QM_LSIO_MU5A_IPG_CLK 789
-#define IMX8QM_LSIO_MU6A_IPG_S_CLK 790
-#define IMX8QM_LSIO_MU6A_IPG_CLK 791
-
-/* DSP */
-#define IMX8QM_AUD_DSP_ADB_ACLK 792
-#define IMX8QM_AUD_DSP_IPG 793
-#define IMX8QM_AUD_DSP_CORE_CLK 794
-#define IMX8QM_AUD_OCRAM_IPG 795
-
-#define IMX8QM_CLK_END 796
-
-#endif /* __DT_BINDINGS_CLOCK_IMX8QM_H */
diff --git a/include/dt-bindings/clock/imx8qxp-clock.h b/include/dt-bindings/clock/imx8qxp-clock.h
deleted file mode 100644
index d0334ea..0000000
--- a/include/dt-bindings/clock/imx8qxp-clock.h
+++ /dev/null
@@ -1,583 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2018 NXP
- */
-
-#ifndef __DT_BINDINGS_CLOCK_IMX8QXP_H
-#define __DT_BINDINGS_CLOCK_IMX8QXP_H
-
-#define IMX8QXP_CLK_DUMMY 0
-
-#define IMX8QXP_UART0_IPG_CLK 1
-#define IMX8QXP_UART0_DIV 2
-#define IMX8QXP_UART0_CLK 3
-
-#define IMX8QXP_IPG_DMA_CLK_ROOT 4
-
-/* GPU Clocks. */
-#define IMX8QXP_GPU0_CORE_DIV 5
-#define IMX8QXP_GPU0_CORE_CLK 6
-#define IMX8QXP_GPU0_SHADER_DIV 7
-#define IMX8QXP_GPU0_SHADER_CLK 8
-
-#define IMX8QXP_24MHZ 9
-#define IMX8QXP_GPT_3M 10
-#define IMX8QXP_32KHZ 11
-
-/* LSIO SS */
-#define IMX8QXP_LSIO_MEM_CLK 12
-#define IMX8QXP_LSIO_BUS_CLK 13
-#define IMX8QXP_LSIO_PWM0_DIV 14
-#define IMX8QXP_LSIO_PWM0_IPG_S_CLK 15
-#define IMX8QXP_LSIO_PWM0_IPG_SLV_CLK 16
-#define IMX8QXP_LSIO_PWM0_IPG_MSTR_CLK 17
-#define IMX8QXP_LSIO_PWM0_HF_CLK 18
-#define IMX8QXP_LSIO_PWM0_CLK 19
-#define IMX8QXP_LSIO_PWM1_DIV 20
-#define IMX8QXP_LSIO_PWM1_IPG_S_CLK 21
-#define IMX8QXP_LSIO_PWM1_IPG_SLV_CLK 22
-#define IMX8QXP_LSIO_PWM1_IPG_MSTR_CLK 23
-#define IMX8QXP_LSIO_PWM1_HF_CLK 24
-#define IMX8QXP_LSIO_PWM1_CLK 25
-#define IMX8QXP_LSIO_PWM2_DIV 26
-#define IMX8QXP_LSIO_PWM2_IPG_S_CLK 27
-#define IMX8QXP_LSIO_PWM2_IPG_SLV_CLK 28
-#define IMX8QXP_LSIO_PWM2_IPG_MSTR_CLK 29
-#define IMX8QXP_LSIO_PWM2_HF_CLK 30
-#define IMX8QXP_LSIO_PWM2_CLK 31
-#define IMX8QXP_LSIO_PWM3_DIV 32
-#define IMX8QXP_LSIO_PWM3_IPG_S_CLK 33
-#define IMX8QXP_LSIO_PWM3_IPG_SLV_CLK 34
-#define IMX8QXP_LSIO_PWM3_IPG_MSTR_CLK 35
-#define IMX8QXP_LSIO_PWM3_HF_CLK 36
-#define IMX8QXP_LSIO_PWM3_CLK 37
-#define IMX8QXP_LSIO_PWM4_DIV 38
-#define IMX8QXP_LSIO_PWM4_IPG_S_CLK 39
-#define IMX8QXP_LSIO_PWM4_IPG_SLV_CLK 40
-#define IMX8QXP_LSIO_PWM4_IPG_MSTR_CLK 42
-#define IMX8QXP_LSIO_PWM4_HF_CLK 43
-#define IMX8QXP_LSIO_PWM4_CLK 44
-#define IMX8QXP_LSIO_PWM5_DIV 45
-#define IMX8QXP_LSIO_PWM5_IPG_S_CLK 46
-#define IMX8QXP_LSIO_PWM5_IPG_SLV_CLK 47
-#define IMX8QXP_LSIO_PWM5_IPG_MSTR_CLK 48
-#define IMX8QXP_LSIO_PWM5_HF_CLK 49
-#define IMX8QXP_LSIO_PWM5_CLK 50
-#define IMX8QXP_LSIO_PWM6_DIV 51
-#define IMX8QXP_LSIO_PWM6_IPG_S_CLK 52
-#define IMX8QXP_LSIO_PWM6_IPG_SLV_CLK 53
-#define IMX8QXP_LSIO_PWM6_IPG_MSTR_CLK 54
-#define IMX8QXP_LSIO_PWM6_HF_CLK 55
-#define IMX8QXP_LSIO_PWM6_CLK 56
-#define IMX8QXP_LSIO_PWM7_DIV 57
-#define IMX8QXP_LSIO_PWM7_IPG_S_CLK 58
-#define IMX8QXP_LSIO_PWM7_IPG_SLV_CLK 59
-#define IMX8QXP_LSIO_PWM7_IPG_MSTR_CLK 60
-#define IMX8QXP_LSIO_PWM7_HF_CLK 61
-#define IMX8QXP_LSIO_PWM7_CLK 62
-#define IMX8QXP_LSIO_GPT0_DIV 63
-#define IMX8QXP_LSIO_GPT0_IPG_S_CLK 64
-#define IMX8QXP_LSIO_GPT0_IPG_SLV_CLK 65
-#define IMX8QXP_LSIO_GPT0_IPG_MSTR_CLK 66
-#define IMX8QXP_LSIO_GPT0_HF_CLK 67
-#define IMX8QXP_LSIO_GPT0_CLK 68
-#define IMX8QXP_LSIO_GPT1_DIV 69
-#define IMX8QXP_LSIO_GPT1_IPG_S_CLK 70
-#define IMX8QXP_LSIO_GPT1_IPG_SLV_CLK 71
-#define IMX8QXP_LSIO_GPT1_IPG_MSTR_CLK 72
-#define IMX8QXP_LSIO_GPT1_HF_CLK 73
-#define IMX8QXP_LSIO_GPT1_CLK 74
-#define IMX8QXP_LSIO_GPT2_DIV 75
-#define IMX8QXP_LSIO_GPT2_IPG_S_CLK 76
-#define IMX8QXP_LSIO_GPT2_IPG_SLV_CLK 77
-#define IMX8QXP_LSIO_GPT2_IPG_MSTR_CLK 78
-#define IMX8QXP_LSIO_GPT2_HF_CLK 79
-#define IMX8QXP_LSIO_GPT2_CLK 80
-#define IMX8QXP_LSIO_GPT3_DIV 81
-#define IMX8QXP_LSIO_GPT3_IPG_S_CLK 82
-#define IMX8QXP_LSIO_GPT3_IPG_SLV_CLK 83
-#define IMX8QXP_LSIO_GPT3_IPG_MSTR_CLK 84
-#define IMX8QXP_LSIO_GPT3_HF_CLK 85
-#define IMX8QXP_LSIO_GPT3_CLK 86
-#define IMX8QXP_LSIO_GPT4_DIV 87
-#define IMX8QXP_LSIO_GPT4_IPG_S_CLK 88
-#define IMX8QXP_LSIO_GPT4_IPG_SLV_CLK 89
-#define IMX8QXP_LSIO_GPT4_IPG_MSTR_CLK 90
-#define IMX8QXP_LSIO_GPT4_HF_CLK 91
-#define IMX8QXP_LSIO_GPT4_CLK 92
-#define IMX8QXP_LSIO_FSPI0_DIV 93
-#define IMX8QXP_LSIO_FSPI0_HCLK 94
-#define IMX8QXP_LSIO_FSPI0_IPG_S_CLK 95
-#define IMX8QXP_LSIO_FSPI0_IPG_CLK 96
-#define IMX8QXP_LSIO_FSPI0_CLK 97
-#define IMX8QXP_LSIO_FSPI1_DIV 98
-#define IMX8QXP_LSIO_FSPI1_HCLK 99
-#define IMX8QXP_LSIO_FSPI1_IPG_S_CLK 100
-#define IMX8QXP_LSIO_FSPI1_IPG_CLK 101
-#define IMX8QXP_LSIO_FSPI1_CLK 102
-#define IMX8QXP_LSIO_GPIO0_IPG_S_CLK 103
-#define IMX8QXP_LSIO_GPIO1_IPG_S_CLK 104
-#define IMX8QXP_LSIO_GPIO2_IPG_S_CLK 105
-#define IMX8QXP_LSIO_GPIO3_IPG_S_CLK 106
-#define IMX8QXP_LSIO_GPIO4_IPG_S_CLK 107
-#define IMX8QXP_LSIO_GPIO5_IPG_S_CLK 108
-#define IMX8QXP_LSIO_GPIO6_IPG_S_CLK 109
-#define IMX8QXP_LSIO_GPIO7_IPG_S_CLK 110
-#define IMX8QXP_LSIO_ROMCP_REG_CLK 111
-#define IMX8QXP_LSIO_ROMCP_CLK 112
-#define IMX8QXP_LSIO_96KROM_CLK 113
-#define IMX8QXP_LSIO_OCRAM_MEM_CLK 114
-#define IMX8QXP_LSIO_OCRAM_CTRL_CLK 115
-
-/* ADMA SS */
-#define IMX8QXP_UART1_IPG_CLK 116
-#define IMX8QXP_UART2_IPG_CLK 117
-#define IMX8QXP_UART3_IPG_CLK 118
-#define IMX8QXP_UART1_DIV 119
-#define IMX8QXP_UART2_DIV 120
-#define IMX8QXP_UART3_DIV 121
-#define IMX8QXP_UART1_CLK 122
-#define IMX8QXP_UART2_CLK 123
-#define IMX8QXP_UART3_CLK 124
-#define IMX8QXP_SPI0_IPG_CLK 125
-#define IMX8QXP_SPI1_IPG_CLK 126
-#define IMX8QXP_SPI2_IPG_CLK 127
-#define IMX8QXP_SPI3_IPG_CLK 128
-#define IMX8QXP_SPI0_DIV 129
-#define IMX8QXP_SPI1_DIV 130
-#define IMX8QXP_SPI2_DIV 131
-#define IMX8QXP_SPI3_DIV 132
-#define IMX8QXP_SPI0_CLK 133
-#define IMX8QXP_SPI1_CLK 134
-#define IMX8QXP_SPI2_CLK 135
-#define IMX8QXP_SPI3_CLK 136
-#define IMX8QXP_CAN0_IPG_CHI_CLK 137
-#define IMX8QXP_CAN1_IPG_CHI_CLK 138
-#define IMX8QXP_CAN2_IPG_CHI_CLK 139
-#define IMX8QXP_CAN0_IPG_CLK 140
-#define IMX8QXP_CAN1_IPG_CLK 141
-#define IMX8QXP_CAN2_IPG_CLK 142
-#define IMX8QXP_CAN0_DIV 143
-#define IMX8QXP_CAN1_DIV 144
-#define IMX8QXP_CAN2_DIV 145
-#define IMX8QXP_CAN0_CLK 146
-#define IMX8QXP_CAN1_CLK 147
-#define IMX8QXP_CAN2_CLK 148
-#define IMX8QXP_I2C0_IPG_CLK 149
-#define IMX8QXP_I2C1_IPG_CLK 150
-#define IMX8QXP_I2C2_IPG_CLK 151
-#define IMX8QXP_I2C3_IPG_CLK 152
-#define IMX8QXP_I2C0_DIV 153
-#define IMX8QXP_I2C1_DIV 154
-#define IMX8QXP_I2C2_DIV 155
-#define IMX8QXP_I2C3_DIV 156
-#define IMX8QXP_I2C0_CLK 157
-#define IMX8QXP_I2C1_CLK 158
-#define IMX8QXP_I2C2_CLK 159
-#define IMX8QXP_I2C3_CLK 160
-#define IMX8QXP_FTM0_IPG_CLK 161
-#define IMX8QXP_FTM1_IPG_CLK 162
-#define IMX8QXP_FTM0_DIV 163
-#define IMX8QXP_FTM1_DIV 164
-#define IMX8QXP_FTM0_CLK 165
-#define IMX8QXP_FTM1_CLK 166
-#define IMX8QXP_ADC0_IPG_CLK 167
-#define IMX8QXP_ADC0_DIV 168
-#define IMX8QXP_ADC0_CLK 169
-#define IMX8QXP_PWM_IPG_CLK 170
-#define IMX8QXP_PWM_DIV 171
-#define IMX8QXP_PWM_CLK 172
-#define IMX8QXP_LCD_IPG_CLK 173
-#define IMX8QXP_LCD_DIV 174
-#define IMX8QXP_LCD_CLK 175
-
-/* Connectivity SS */
-#define IMX8QXP_AXI_CONN_CLK_ROOT 176
-#define IMX8QXP_AHB_CONN_CLK_ROOT 177
-#define IMX8QXP_IPG_CONN_CLK_ROOT 178
-#define IMX8QXP_SDHC0_IPG_CLK 179
-#define IMX8QXP_SDHC1_IPG_CLK 180
-#define IMX8QXP_SDHC2_IPG_CLK 181
-#define IMX8QXP_SDHC0_DIV 182
-#define IMX8QXP_SDHC1_DIV 183
-#define IMX8QXP_SDHC2_DIV 184
-#define IMX8QXP_SDHC0_CLK 185
-#define IMX8QXP_SDHC1_CLK 186
-#define IMX8QXP_SDHC2_CLK 187
-#define IMX8QXP_ENET0_ROOT_DIV 188
-#define IMX8QXP_ENET0_REF_DIV 189
-#define IMX8QXP_ENET1_REF_DIV 190
-#define IMX8QXP_ENET0_BYPASS_DIV 191
-#define IMX8QXP_ENET0_RGMII_DIV 192
-#define IMX8QXP_ENET1_ROOT_DIV 193
-#define IMX8QXP_ENET1_BYPASS_DIV 194
-#define IMX8QXP_ENET1_RGMII_DIV 195
-#define IMX8QXP_ENET0_AHB_CLK 196
-#define IMX8QXP_ENET0_IPG_S_CLK 197
-#define IMX8QXP_ENET0_IPG_CLK 198
-#define IMX8QXP_ENET1_AHB_CLK 199
-#define IMX8QXP_ENET1_IPG_S_CLK 200
-#define IMX8QXP_ENET1_IPG_CLK 201
-#define IMX8QXP_ENET0_ROOT_CLK 202
-#define IMX8QXP_ENET1_ROOT_CLK 203
-#define IMX8QXP_ENET0_TX_CLK 204
-#define IMX8QXP_ENET1_TX_CLK 205
-#define IMX8QXP_ENET0_PTP_CLK 206
-#define IMX8QXP_ENET1_PTP_CLK 207
-#define IMX8QXP_ENET0_REF_25MHZ_125MHZ_SEL 208
-#define IMX8QXP_ENET1_REF_25MHZ_125MHZ_SEL 209
-#define IMX8QXP_ENET0_RMII_TX_SEL 210
-#define IMX8QXP_ENET1_RMII_TX_SEL 211
-#define IMX8QXP_ENET0_RGMII_TX_CLK 212
-#define IMX8QXP_ENET1_RGMII_TX_CLK 213
-#define IMX8QXP_ENET0_RMII_RX_CLK 214
-#define IMX8QXP_ENET1_RMII_RX_CLK 215
-#define IMX8QXP_ENET0_REF_25MHZ_125MHZ_CLK 216
-#define IMX8QXP_ENET1_REF_25MHZ_125MHZ_CLK 217
-#define IMX8QXP_ENET0_REF_50MHZ_CLK 218
-#define IMX8QXP_ENET1_REF_50MHZ_CLK 219
-#define IMX8QXP_GPMI_BCH_IO_DIV 220
-#define IMX8QXP_GPMI_BCH_DIV 221
-#define IMX8QXP_GPMI_APB_CLK 222
-#define IMX8QXP_GPMI_APB_BCH_CLK 223
-#define IMX8QXP_GPMI_BCH_IO_CLK 224
-#define IMX8QXP_GPMI_BCH_CLK 225
-#define IMX8QXP_APBHDMA_CLK 226
-#define IMX8QXP_USB3_ACLK_DIV 227
-#define IMX8QXP_USB3_BUS_DIV 228
-#define IMX8QXP_USB3_LPM_DIV 229
-#define IMX8QXP_USB3_IPG_CLK 230
-#define IMX8QXP_USB3_CORE_PCLK 231
-#define IMX8QXP_USB3_PHY_CLK 232
-#define IMX8QXP_USB3_ACLK 233
-#define IMX8QXP_USB3_BUS_CLK 234
-#define IMX8QXP_USB3_LPM_CLK 235
-#define IMX8QXP_USB2_OH_AHB_CLK 236
-#define IMX8QXP_USB2_OH_IPG_S_CLK 237
-#define IMX8QXP_USB2_OH_IPG_S_PL301_CLK 238
-#define IMX8QXP_USB2_PHY_IPG_CLK 239
-#define IMX8QXP_EDMA_CLK 240
-#define IMX8QXP_EDMA_IPG_CLK 241
-#define IMX8QXP_MLB_HCLK 242
-#define IMX8QXP_MLB_CLK 243
-#define IMX8QXP_MLB_IPG_CLK 244
-
-/* Display controller SS */
-/* DC part1 */
-#define IMX8QXP_DC_AXI_EXT_CLK 245
-#define IMX8QXP_DC_AXI_INT_CLK 246
-#define IMX8QXP_DC_CFG_CLK 247
-#define IMX8QXP_DC0_DISP0_CLK 248
-#define IMX8QXP_DC0_DISP1_CLK 249
-#define IMX8QXP_DC0_PRG0_RTRAM_CLK 250
-#define IMX8QXP_DC0_PRG0_APB_CLK 251
-#define IMX8QXP_DC0_PRG1_RTRAM_CLK 252
-#define IMX8QXP_DC0_PRG1_APB_CLK 253
-#define IMX8QXP_DC0_PRG2_RTRAM_CLK 254
-#define IMX8QXP_DC0_PRG2_APB_CLK 255
-#define IMX8QXP_DC0_PRG3_RTRAM_CLK 256
-#define IMX8QXP_DC0_PRG3_APB_CLK 257
-#define IMX8QXP_DC0_PRG4_RTRAM_CLK 258
-#define IMX8QXP_DC0_PRG4_APB_CLK 259
-#define IMX8QXP_DC0_PRG5_RTRAM_CLK 260
-#define IMX8QXP_DC0_PRG5_APB_CLK 261
-#define IMX8QXP_DC0_PRG6_RTRAM_CLK 262
-#define IMX8QXP_DC0_PRG6_APB_CLK 263
-#define IMX8QXP_DC0_PRG7_RTRAM_CLK 264
-#define IMX8QXP_DC0_PRG7_APB_CLK 265
-#define IMX8QXP_DC0_PRG8_RTRAM_CLK 266
-#define IMX8QXP_DC0_PRG8_APB_CLK 267
-#define IMX8QXP_DC0_DPR0_APB_CLK 268
-#define IMX8QXP_DC0_DPR0_B_CLK 269
-#define IMX8QXP_DC0_RTRAM0_CLK 270
-#define IMX8QXP_DC0_RTRAM1_CLK 271
-
-/* MIPI-LVDS part1 */
-#define IMX8QXP_MIPI_IPG_CLK 272
-#define IMX8QXP_MIPI0_I2C0_DIV 273
-#define IMX8QXP_MIPI0_I2C1_DIV 274
-#define IMX8QXP_MIPI0_I2C0_CLK 275
-#define IMX8QXP_MIPI0_I2C1_CLK 276
-#define IMX8QXP_MIPI0_I2C0_IPG_S_CLK 277
-#define IMX8QXP_MIPI0_I2C0_IPG_CLK 278
-#define IMX8QXP_MIPI0_I2C1_IPG_S_CLK 279
-#define IMX8QXP_MIPI0_I2C1_IPG_CLK 280
-#define IMX8QXP_MIPI0_PWM_IPG_S_CLK 281
-#define IMX8QXP_MIPI0_PWM_IPG_CLK 282
-#define IMX8QXP_MIPI0_PWM_32K_CLK 283
-#define IMX8QXP_MIPI0_GPIO_IPG_CLK 284
-
-#define IMX8QXP_IMG_JPEG_ENC_IPG_CLK 285
-#define IMX8QXP_IMG_JPEG_ENC_CLK 286
-#define IMX8QXP_IMG_JPEG_DEC_IPG_CLK 287
-#define IMX8QXP_IMG_JPEG_DEC_CLK 288
-#define IMX8QXP_IMG_PXL_LINK_DC0_CLK 289
-#define IMX8QXP_IMG_PXL_LINK_DC1_CLK 290
-#define IMX8QXP_IMG_PXL_LINK_CSI0_CLK 291
-#define IMX8QXP_IMG_PXL_LINK_CSI1_CLK 292
-#define IMX8QXP_IMG_PXL_LINK_HDMI_IN_CLK 293
-#define IMX8QXP_IMG_PDMA_0_CLK 294
-#define IMX8QXP_IMG_PDMA_1_CLK 295
-#define IMX8QXP_IMG_PDMA_2_CLK 296
-#define IMX8QXP_IMG_PDMA_3_CLK 297
-#define IMX8QXP_IMG_PDMA_4_CLK 298
-#define IMX8QXP_IMG_PDMA_5_CLK 299
-#define IMX8QXP_IMG_PDMA_6_CLK 300
-#define IMX8QXP_IMG_PDMA_7_CLK 301
-#define IMX8QXP_IMG_AXI_CLK 302
-#define IMX8QXP_IMG_IPG_CLK 303
-#define IMX8QXP_IMG_PXL_CLK 304
-
-#define IMX8QXP_CSI0_I2C0_DIV 305
-#define IMX8QXP_CSI0_PWM0_DIV 306
-#define IMX8QXP_CSI0_CORE_DIV 307
-#define IMX8QXP_CSI0_ESC_DIV 308
-#define IMX8QXP_CSI0_IPG_CLK_S 309
-#define IMX8QXP_CSI0_IPG_CLK 310
-#define IMX8QXP_CSI0_APB_CLK 311
-#define IMX8QXP_CSI0_I2C0_IPG_CLK 312
-#define IMX8QXP_CSI0_I2C0_CLK 313
-#define IMX8QXP_CSI0_PWM0_IPG_CLK 314
-#define IMX8QXP_CSI0_PWM0_CLK 315
-#define IMX8QXP_CSI0_CORE_CLK 316
-#define IMX8QXP_CSI0_ESC_CLK 317
-
-#define IMX8QXP_HSIO_AXI_CLK 318
-#define IMX8QXP_HSIO_PER_CLK 319
-#define IMX8QXP_HSIO_PCIE_MSTR_AXI_CLK 320
-#define IMX8QXP_HSIO_PCIE_SLV_AXI_CLK 321
-#define IMX8QXP_HSIO_PCIE_DBI_AXI_CLK 322
-#define IMX8QXP_HSIO_PCIE_X1_PER_CLK 323
-#define IMX8QXP_HSIO_PHY_X1_PER_CLK 324
-#define IMX8QXP_HSIO_MISC_PER_CLK 325
-#define IMX8QXP_HSIO_PHY_X1_APB_CLK 326
-#define IMX8QXP_HSIO_GPIO_CLK 327
-#define IMX8QXP_HSIO_PHY_X1_PCLK 328
-
-#define IMX8QXP_A35_DIV 329
-
-/* ACM */
-#define IMX8QXP_EXT_AUD_MCLK0 330
-#define IMX8QXP_EXT_AUD_MCLK1 331
-#define IMX8QXP_ESAI0_RX_CLK 332
-#define IMX8QXP_ESAI0_RX_HF_CLK 333
-#define IMX8QXP_ESAI0_TX_CLK 334
-#define IMX8QXP_ESAI0_TX_HF_CLK 335
-#define IMX8QXP_SPDIF0_RX 336
-#define IMX8QXP_SAI0_RX_BCLK 337
-#define IMX8QXP_SAI0_TX_BCLK 338
-#define IMX8QXP_SAI1_RX_BCLK 339
-#define IMX8QXP_SAI1_TX_BCLK 340
-#define IMX8QXP_SAI2_RX_BCLK 341
-#define IMX8QXP_SAI3_RX_BCLK 342
-#define IMX8QXP_SAI4_RX_BCLK 343
-
-#define IMX8QXP_ACM_AUD_CLK0_SEL 344
-#define IMX8QXP_ACM_AUD_CLK0_CLK 345
-#define IMX8QXP_ACM_AUD_CLK1_SEL 346
-#define IMX8QXP_ACM_AUD_CLK1_CLK 347
-#define IMX8QXP_ACM_MCLKOUT0_SEL 348
-#define IMX8QXP_ACM_MCLKOUT0_CLK 349
-#define IMX8QXP_ACM_MCLKOUT1_SEL 350
-#define IMX8QXP_ACM_MCLKOUT1_CLK 351
-#define IMX8QXP_ACM_ESAI0_MCLK_SEL 352
-#define IMX8QXP_ACM_ESAI0_MCLK_CLK 353
-#define IMX8QXP_ACM_GPT0_MUX_CLK_SEL 354
-#define IMX8QXP_ACM_GPT0_MUX_CLK_CLK 355
-#define IMX8QXP_ACM_GPT1_MUX_CLK_SEL 356
-#define IMX8QXP_ACM_GPT1_MUX_CLK_CLK 357
-#define IMX8QXP_ACM_GPT2_MUX_CLK_SEL 358
-#define IMX8QXP_ACM_GPT2_MUX_CLK_CLK 359
-#define IMX8QXP_ACM_GPT3_MUX_CLK_SEL 360
-#define IMX8QXP_ACM_GPT3_MUX_CLK_CLK 361
-#define IMX8QXP_ACM_GPT4_MUX_CLK_SEL 362
-#define IMX8QXP_ACM_GPT4_MUX_CLK_CLK 363
-#define IMX8QXP_ACM_GPT5_MUX_CLK_SEL 364
-#define IMX8QXP_ACM_GPT5_MUX_CLK_CLK 365
-#define IMX8QXP_ACM_SAI0_MCLK_SEL 366
-#define IMX8QXP_ACM_SAI0_MCLK_CLK 367
-#define IMX8QXP_ACM_SAI1_MCLK_SEL 368
-#define IMX8QXP_ACM_SAI1_MCLK_CLK 369
-#define IMX8QXP_ACM_SAI2_MCLK_SEL 370
-#define IMX8QXP_ACM_SAI2_MCLK_CLK 371
-#define IMX8QXP_ACM_SAI3_MCLK_SEL 372
-#define IMX8QXP_ACM_SAI3_MCLK_CLK 373
-#define IMX8QXP_ACM_SAI4_MCLK_SEL 374
-#define IMX8QXP_ACM_SAI4_MCLK_CLK 375
-#define IMX8QXP_ACM_SAI5_MCLK_SEL 376
-#define IMX8QXP_ACM_SAI5_MCLK_CLK 377
-#define IMX8QXP_ACM_SPDIF0_TX_CLK_SEL 378
-#define IMX8QXP_ACM_SPDIF0_TX_CLK_CLK 379
-#define IMX8QXP_ACM_MQS_TX_CLK_SEL 380
-#define IMX8QXP_ACM_MQS_TX_CLK_CLK 381
-#define IMX8QXP_ACM_ASRC0_MUX_CLK_SEL 382
-#define IMX8QXP_ACM_ASRC1_MUX_CLK_SEL 383
-#define IMX8QXP_ACM_ASRC0_MUX_CLK_CLK 384
-#define IMX8QXP_ACM_ASRC1_MUX_CLK_CLK 385
-
-#define IMX8QXP_IPG_AUD_CLK_ROOT 386
-
-/* Audio */
-#define IMX8QXP_AUD_PLL0_DIV 387
-#define IMX8QXP_AUD_PLL0 388
-#define IMX8QXP_AUD_PLL1_DIV 389
-#define IMX8QXP_AUD_PLL1 390
-#define IMX8QXP_AUD_AMIX_IPG 391
-#define IMX8QXP_AUD_ESAI_0_IPG 392
-#define IMX8QXP_AUD_ESAI_0_EXTAL_IPG 393
-#define IMX8QXP_AUD_SAI_0_IPG 394
-#define IMX8QXP_AUD_SAI_0_MCLK 395
-#define IMX8QXP_AUD_SAI_1_IPG 396
-#define IMX8QXP_AUD_SAI_1_MCLK 397
-#define IMX8QXP_AUD_SAI_2_IPG 398
-#define IMX8QXP_AUD_SAI_2_MCLK 399
-#define IMX8QXP_AUD_SAI_3_IPG 400
-#define IMX8QXP_AUD_SAI_3_MCLK 401
-#define IMX8QXP_AUD_SAI_4_IPG 402
-#define IMX8QXP_AUD_SAI_4_MCLK 403
-#define IMX8QXP_AUD_SAI_5_IPG 404
-#define IMX8QXP_AUD_SAI_5_MCLK 405
-#define IMX8QXP_AUD_MQS_IPG 406
-#define IMX8QXP_AUD_MQS_HMCLK 407
-#define IMX8QXP_AUD_GPT5_IPG 408
-#define IMX8QXP_AUD_GPT5_CLKIN 409
-#define IMX8QXP_AUD_GPT6_IPG 410
-#define IMX8QXP_AUD_GPT6_CLKIN 411
-#define IMX8QXP_AUD_GPT7_IPG 412
-#define IMX8QXP_AUD_GPT7_CLKIN 413
-#define IMX8QXP_AUD_GPT8_IPG 414
-#define IMX8QXP_AUD_GPT8_CLKIN 415
-#define IMX8QXP_AUD_GPT9_IPG 416
-#define IMX8QXP_AUD_GPT9_CLKIN 417
-#define IMX8QXP_AUD_GPT10_IPG 418
-#define IMX8QXP_AUD_GPT10_CLKIN 419
-#define IMX8QXP_AUD_ACM_AUD_PLL_CLK0_DIV 420
-#define IMX8QXP_AUD_ACM_AUD_PLL_CLK0_CLK 421
-#define IMX8QXP_AUD_ACM_AUD_PLL_CLK1_DIV 422
-#define IMX8QXP_AUD_ACM_AUD_PLL_CLK1_CLK 423
-#define IMX8QXP_AUD_ACM_AUD_REC_CLK0_DIV 424
-#define IMX8QXP_AUD_ACM_AUD_REC_CLK0_CLK 425
-#define IMX8QXP_AUD_ACM_AUD_REC_CLK1_DIV 426
-#define IMX8QXP_AUD_ACM_AUD_REC_CLK1_CLK 427
-#define IMX8QXP_AUD_MCLKOUT0 428
-#define IMX8QXP_AUD_MCLKOUT1 429
-#define IMX8QXP_AUD_SPDIF_0_TX_CLK 430
-#define IMX8QXP_AUD_SPDIF_0_GCLKW 431
-#define IMX8QXP_AUD_SPDIF_0_IPG 432
-#define IMX8QXP_AUD_ASRC_0_IPG 433
-#define IMX8QXP_AUD_ASRC_1_IPG 434
-#define IMX8QXP_AUD_DSP_ADB_ACLK 435
-#define IMX8QXP_AUD_DSP_IPG 436
-#define IMX8QXP_AUD_DSP_CORE_CLK 437
-#define IMX8QXP_AUD_OCRAM_IPG 438
-
-/* DC part2 */
-#define IMX8QXP_DC0_DISP0_DIV 439
-#define IMX8QXP_DC0_DISP1_DIV 440
-#define IMX8QXP_DC0_BYPASS_0_DIV 441
-#define IMX8QXP_DC0_BYPASS_1_DIV 442
-#define IMX8QXP_DC0_PLL0_DIV 443
-#define IMX8QXP_DC0_PLL1_DIV 444
-#define IMX8QXP_DC0_PLL0_CLK 445
-#define IMX8QXP_DC0_PLL1_CLK 446
-
-/* MIPI-LVDS part2 */
-#define IMX8QXP_MIPI0_BYPASS_CLK 447
-#define IMX8QXP_MIPI0_PIXEL_DIV 448
-#define IMX8QXP_MIPI0_PIXEL_CLK 449
-#define IMX8QXP_MIPI0_LVDS_PIXEL_DIV 450
-#define IMX8QXP_MIPI0_LVDS_PIXEL_CLK 451
-#define IMX8QXP_MIPI0_LVDS_BYPASS_CLK 452
-#define IMX8QXP_MIPI0_LVDS_PHY_DIV 453
-#define IMX8QXP_MIPI0_LVDS_PHY_CLK 454
-#define IMX8QXP_MIPI0_DSI_TX_ESC_DIV 455
-#define IMX8QXP_MIPI0_DSI_RX_ESC_DIV 456
-#define IMX8QXP_MIPI0_DSI_TX_ESC_CLK 457
-#define IMX8QXP_MIPI0_DSI_RX_ESC_CLK 458
-#define IMX8QXP_MIPI0_LIS_IPG_CLK 459
-#define IMX8QXP_MIPI1_I2C0_DIV 460
-#define IMX8QXP_MIPI1_I2C1_DIV 461
-#define IMX8QXP_MIPI1_I2C0_CLK 462
-#define IMX8QXP_MIPI1_I2C1_CLK 463
-#define IMX8QXP_MIPI1_I2C0_IPG_S_CLK 464
-#define IMX8QXP_MIPI1_I2C0_IPG_CLK 465
-#define IMX8QXP_MIPI1_I2C1_IPG_S_CLK 466
-#define IMX8QXP_MIPI1_I2C1_IPG_CLK 467
-#define IMX8QXP_MIPI1_PWM_IPG_S_CLK 468
-#define IMX8QXP_MIPI1_PWM_IPG_CLK 469
-#define IMX8QXP_MIPI1_PWM_32K_CLK 470
-#define IMX8QXP_MIPI1_GPIO_IPG_CLK 471
-#define IMX8QXP_MIPI1_BYPASS_CLK 472
-#define IMX8QXP_MIPI1_PIXEL_DIV 473
-#define IMX8QXP_MIPI1_PIXEL_CLK 474
-#define IMX8QXP_MIPI1_LVDS_PIXEL_DIV 475
-#define IMX8QXP_MIPI1_LVDS_PIXEL_CLK 476
-#define IMX8QXP_MIPI1_LVDS_BYPASS_CLK 477
-#define IMX8QXP_MIPI1_LVDS_PHY_DIV 478
-#define IMX8QXP_MIPI1_LVDS_PHY_CLK 479
-#define IMX8QXP_MIPI1_DSI_TX_ESC_DIV 480
-#define IMX8QXP_MIPI1_DSI_RX_ESC_DIV 481
-#define IMX8QXP_MIPI1_DSI_TX_ESC_CLK 482
-#define IMX8QXP_MIPI1_DSI_RX_ESC_CLK 483
-
-#define IMX8QXP_MIPI1_LIS_IPG_CLK 484
-
-/* CM40 */
-#define IMX8QXP_CM40_IPG_CLK 485
-#define IMX8QXP_CM40_I2C_DIV 486
-#define IMX8QXP_CM40_I2C_CLK 487
-#define IMX8QXP_CM40_I2C_IPG_CLK 488
-
-/* VPU clocks. */
-#define IMX8QXP_VPU_ENC_CLK 489
-#define IMX8QXP_VPU_DEC_CLK 490
-
-/* MIPI-LVDS part3 */
-#define IMX8QXP_MIPI0_DSI_PLL_CLK 491
-#define IMX8QXP_MIPI0_DSI_PLL_DIV2_CLK 492
-#define IMX8QXP_MIPI0_LVDS_PIXEL_SEL 493
-#define IMX8QXP_MIPI0_LVDS_PHY_SEL 494
-#define IMX8QXP_MIPI0_DSI_TX_ESC_SEL 495
-#define IMX8QXP_MIPI0_DSI_RX_ESC_SEL 496
-#define IMX8QXP_MIPI0_DSI_PHY_SEL 498
-#define IMX8QXP_MIPI0_DSI_PHY_DIV 499
-#define IMX8QXP_MIPI0_DSI_PHY_CLK 500
-#define IMX8QXP_MIPI1_DSI_PLL_CLK 501
-#define IMX8QXP_MIPI1_DSI_PLL_DIV2_CLK 502
-#define IMX8QXP_MIPI1_LVDS_PIXEL_SEL 503
-#define IMX8QXP_MIPI1_LVDS_PHY_SEL 504
-#define IMX8QXP_MIPI1_DSI_TX_ESC_SEL 505
-#define IMX8QXP_MIPI1_DSI_RX_ESC_SEL 506
-#define IMX8QXP_MIPI1_DSI_PHY_SEL 507
-#define IMX8QXP_MIPI1_DSI_PHY_DIV 508
-#define IMX8QXP_MIPI1_DSI_PHY_CLK 509
-
-/* DC part3 */
-#define IMX8QXP_DC0_DPR1_APB_CLK 510
-#define IMX8QXP_DC0_DPR1_B_CLK 511
-
-#define IMX8QXP_CONN_PLL0_CLK 512
-#define IMX8QXP_CONN_PLL1_CLK 513
-#define IMX8QXP_SDHC0_SEL 514
-#define IMX8QXP_SDHC1_SEL 515
-#define IMX8QXP_SDHC2_SEL 516
-
-/* PARALLER CSI */
-#define IMX8QXP_PARALLEL_CSI_CLK_DPLL 517
-#define IMX8QXP_PARALLEL_CSI_CLK_SEL 518
-#define IMX8QXP_PARALLEL_CSI_PER_CLK_DIV 519
-#define IMX8QXP_PARALLEL_CSI_PIXEL_CLK 520
-#define IMX8QXP_PARALLEL_CSI_IPG_CLK 521
-#define IMX8QXP_PARALLEL_CSI_MCLK_DIV 522
-#define IMX8QXP_PARALLEL_CSI_MISC0_CLK 523
-
-#define IMX8QXP_MIPI0_PWM_DIV 524
-#define IMX8QXP_MIPI1_PWM_DIV 525
-#define IMX8QXP_MIPI0_PWM_CLK 526
-#define IMX8QXP_MIPI1_PWM_CLK 527
-
-#define IMX8QXP_LSIO_MU5A_IPG_S_CLK 528
-#define IMX8QXP_LSIO_MU5A_IPG_CLK 529
-
-#define IMX8QXP_CLK_END 530
-#endif /* __DT_BINDINGS_CLOCK_IMX8QXP_H */
diff --git a/include/dt-bindings/clock/jz4780-cgu.h b/include/dt-bindings/clock/jz4780-cgu.h
deleted file mode 100644
index 73214c5..0000000
--- a/include/dt-bindings/clock/jz4780-cgu.h
+++ /dev/null
@@ -1,89 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * This header provides clock numbers for the ingenic,jz4780-cgu DT binding.
- *
- * They are roughly ordered as:
- * - external clocks
- * - PLLs
- * - muxes/dividers in the order they appear in the jz4780 programmers manual
- * - gates in order of their bit in the CLKGR* registers
- */
-
-#ifndef __DT_BINDINGS_CLOCK_JZ4780_CGU_H__
-#define __DT_BINDINGS_CLOCK_JZ4780_CGU_H__
-
-#define JZ4780_CLK_EXCLK 0
-#define JZ4780_CLK_RTCLK 1
-#define JZ4780_CLK_APLL 2
-#define JZ4780_CLK_MPLL 3
-#define JZ4780_CLK_EPLL 4
-#define JZ4780_CLK_VPLL 5
-#define JZ4780_CLK_OTGPHY 6
-#define JZ4780_CLK_SCLKA 7
-#define JZ4780_CLK_CPUMUX 8
-#define JZ4780_CLK_CPU 9
-#define JZ4780_CLK_L2CACHE 10
-#define JZ4780_CLK_AHB0 11
-#define JZ4780_CLK_AHB2PMUX 12
-#define JZ4780_CLK_AHB2 13
-#define JZ4780_CLK_PCLK 14
-#define JZ4780_CLK_DDR 15
-#define JZ4780_CLK_VPU 16
-#define JZ4780_CLK_I2SPLL 17
-#define JZ4780_CLK_I2S 18
-#define JZ4780_CLK_LCD0PIXCLK 19
-#define JZ4780_CLK_LCD1PIXCLK 20
-#define JZ4780_CLK_MSCMUX 21
-#define JZ4780_CLK_MSC0 22
-#define JZ4780_CLK_MSC1 23
-#define JZ4780_CLK_MSC2 24
-#define JZ4780_CLK_UHC 25
-#define JZ4780_CLK_SSIPLL 26
-#define JZ4780_CLK_SSI 27
-#define JZ4780_CLK_CIMMCLK 28
-#define JZ4780_CLK_PCMPLL 29
-#define JZ4780_CLK_PCM 30
-#define JZ4780_CLK_GPU 31
-#define JZ4780_CLK_HDMI 32
-#define JZ4780_CLK_BCH 33
-#define JZ4780_CLK_NEMC 34
-#define JZ4780_CLK_OTG0 35
-#define JZ4780_CLK_SSI0 36
-#define JZ4780_CLK_SMB0 37
-#define JZ4780_CLK_SMB1 38
-#define JZ4780_CLK_SCC 39
-#define JZ4780_CLK_AIC 40
-#define JZ4780_CLK_TSSI0 41
-#define JZ4780_CLK_OWI 42
-#define JZ4780_CLK_KBC 43
-#define JZ4780_CLK_SADC 44
-#define JZ4780_CLK_UART0 45
-#define JZ4780_CLK_UART1 46
-#define JZ4780_CLK_UART2 47
-#define JZ4780_CLK_UART3 48
-#define JZ4780_CLK_SSI1 49
-#define JZ4780_CLK_SSI2 50
-#define JZ4780_CLK_PDMA 51
-#define JZ4780_CLK_GPS 52
-#define JZ4780_CLK_MAC 53
-#define JZ4780_CLK_SMB2 54
-#define JZ4780_CLK_CIM 55
-#define JZ4780_CLK_LCD 56
-#define JZ4780_CLK_TVE 57
-#define JZ4780_CLK_IPU 58
-#define JZ4780_CLK_DDR0 59
-#define JZ4780_CLK_DDR1 60
-#define JZ4780_CLK_SMB3 61
-#define JZ4780_CLK_TSSI1 62
-#define JZ4780_CLK_COMPRESS 63
-#define JZ4780_CLK_AIC1 64
-#define JZ4780_CLK_GPVLC 65
-#define JZ4780_CLK_OTG1 66
-#define JZ4780_CLK_UART4 67
-#define JZ4780_CLK_AHBMON 68
-#define JZ4780_CLK_SMB4 69
-#define JZ4780_CLK_DES 70
-#define JZ4780_CLK_X2D 71
-#define JZ4780_CLK_CORE1 72
-
-#endif /* __DT_BINDINGS_CLOCK_JZ4780_CGU_H__ */
diff --git a/include/dt-bindings/clock/maxim,max77802.h b/include/dt-bindings/clock/maxim,max77802.h
deleted file mode 100644
index 997312e..0000000
--- a/include/dt-bindings/clock/maxim,max77802.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * Copyright (C) 2014 Google, Inc
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * Device Tree binding constants clocks for the Maxim 77802 PMIC.
- */
-
-#ifndef _DT_BINDINGS_CLOCK_MAXIM_MAX77802_CLOCK_H
-#define _DT_BINDINGS_CLOCK_MAXIM_MAX77802_CLOCK_H
-
-/* Fixed rate clocks. */
-
-#define MAX77802_CLK_32K_AP 0
-#define MAX77802_CLK_32K_CP 1
-
-/* Total number of clocks. */
-#define MAX77802_CLKS_NUM (MAX77802_CLK_32K_CP + 1)
-
-#endif /* _DT_BINDINGS_CLOCK_MAXIM_MAX77802_CLOCK_H */
diff --git a/include/dt-bindings/clock/microchip,clock.h b/include/dt-bindings/clock/microchip,clock.h
deleted file mode 100644
index ea6f161..0000000
--- a/include/dt-bindings/clock/microchip,clock.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (c) 2015 Purna Chandra Mandal <purna.mandal@microchip.com>
- *
- */
-
-#ifndef __CLK_MICROCHIP_PIC32
-#define __CLK_MICROCHIP_PIC32
-
-/* clock output indices */
-#define BASECLK 0
-#define PLLCLK 1
-#define MPLL 2
-#define SYSCLK 3
-#define PB1CLK 4
-#define PB2CLK 5
-#define PB3CLK 6
-#define PB4CLK 7
-#define PB5CLK 8
-#define PB6CLK 9
-#define PB7CLK 10
-#define REF1CLK 11
-#define REF2CLK 12
-#define REF3CLK 13
-#define REF4CLK 14
-#define REF5CLK 15
-
-#endif /* __CLK_MICROCHIP_PIC32 */
diff --git a/include/dt-bindings/clock/mt7623-clk.h b/include/dt-bindings/clock/mt7623-clk.h
deleted file mode 100644
index 71ced15..0000000
--- a/include/dt-bindings/clock/mt7623-clk.h
+++ /dev/null
@@ -1,413 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2018 MediaTek Inc.
- */
-
-#ifndef _DT_BINDINGS_CLK_MT2701_H
-#define _DT_BINDINGS_CLK_MT2701_H
-
-/* TOPCKGEN */
-#define CLK_TOP_FCLKS_OFF 0
-
-#define CLK_TOP_DPI 0
-#define CLK_TOP_DMPLL 1
-#define CLK_TOP_VENCPLL 2
-#define CLK_TOP_HDMI_0_PIX340M 3
-#define CLK_TOP_HDMI_0_DEEP340M 4
-#define CLK_TOP_HDMI_0_PLL340M 5
-#define CLK_TOP_HADDS2_FB 6
-#define CLK_TOP_WBG_DIG_416M 7
-#define CLK_TOP_DSI0_LNTC_DSI 8
-#define CLK_TOP_HDMI_SCL_RX 9
-#define CLK_TOP_32K_EXTERNAL 10
-#define CLK_TOP_HDMITX_CLKDIG_CTS 11
-#define CLK_TOP_AUD_EXT1 12
-#define CLK_TOP_AUD_EXT2 13
-#define CLK_TOP_NFI1X_PAD 14
-
-#define CLK_TOP_SYSPLL 15
-#define CLK_TOP_SYSPLL_D2 16
-#define CLK_TOP_SYSPLL_D3 17
-#define CLK_TOP_SYSPLL_D5 18
-#define CLK_TOP_SYSPLL_D7 19
-#define CLK_TOP_SYSPLL1_D2 20
-#define CLK_TOP_SYSPLL1_D4 21
-#define CLK_TOP_SYSPLL1_D8 22
-#define CLK_TOP_SYSPLL1_D16 23
-#define CLK_TOP_SYSPLL2_D2 24
-#define CLK_TOP_SYSPLL2_D4 25
-#define CLK_TOP_SYSPLL2_D8 26
-#define CLK_TOP_SYSPLL3_D2 27
-#define CLK_TOP_SYSPLL3_D4 28
-#define CLK_TOP_SYSPLL4_D2 29
-#define CLK_TOP_SYSPLL4_D4 30
-#define CLK_TOP_UNIVPLL 31
-#define CLK_TOP_UNIVPLL_D2 32
-#define CLK_TOP_UNIVPLL_D3 33
-#define CLK_TOP_UNIVPLL_D5 34
-#define CLK_TOP_UNIVPLL_D7 35
-#define CLK_TOP_UNIVPLL_D26 36
-#define CLK_TOP_UNIVPLL_D52 37
-#define CLK_TOP_UNIVPLL_D108 38
-#define CLK_TOP_USB_PHY48M 39
-#define CLK_TOP_UNIVPLL1_D2 40
-#define CLK_TOP_UNIVPLL1_D4 41
-#define CLK_TOP_UNIVPLL1_D8 42
-#define CLK_TOP_UNIVPLL2_D2 43
-#define CLK_TOP_UNIVPLL2_D4 44
-#define CLK_TOP_UNIVPLL2_D8 45
-#define CLK_TOP_UNIVPLL2_D16 46
-#define CLK_TOP_UNIVPLL2_D32 47
-#define CLK_TOP_UNIVPLL3_D2 48
-#define CLK_TOP_UNIVPLL3_D4 49
-#define CLK_TOP_UNIVPLL3_D8 50
-#define CLK_TOP_MSDCPLL 51
-#define CLK_TOP_MSDCPLL_D2 52
-#define CLK_TOP_MSDCPLL_D4 53
-#define CLK_TOP_MSDCPLL_D8 54
-#define CLK_TOP_MMPLL 55
-#define CLK_TOP_MMPLL_D2 56
-#define CLK_TOP_DMPLL_D2 57
-#define CLK_TOP_DMPLL_D4 58
-#define CLK_TOP_DMPLL_X2 59
-#define CLK_TOP_TVDPLL 60
-#define CLK_TOP_TVDPLL_D2 61
-#define CLK_TOP_TVDPLL_D4 62
-#define CLK_TOP_VDECPLL 63
-#define CLK_TOP_TVD2PLL 64
-#define CLK_TOP_TVD2PLL_D2 65
-#define CLK_TOP_MIPIPLL 66
-#define CLK_TOP_MIPIPLL_D2 67
-#define CLK_TOP_MIPIPLL_D4 68
-#define CLK_TOP_HDMIPLL 69
-#define CLK_TOP_HDMIPLL_D2 70
-#define CLK_TOP_HDMIPLL_D3 71
-#define CLK_TOP_ARMPLL_1P3G 72
-#define CLK_TOP_AUDPLL 73
-#define CLK_TOP_AUDPLL_D4 74
-#define CLK_TOP_AUDPLL_D8 75
-#define CLK_TOP_AUDPLL_D16 76
-#define CLK_TOP_AUDPLL_D24 77
-#define CLK_TOP_AUD1PLL_98M 78
-#define CLK_TOP_AUD2PLL_90M 79
-#define CLK_TOP_HADDS2PLL_98M 80
-#define CLK_TOP_HADDS2PLL_294M 81
-#define CLK_TOP_ETHPLL_500M 82
-#define CLK_TOP_CLK26M_D8 83
-#define CLK_TOP_32K_INTERNAL 84
-#define CLK_TOP_AXISEL_D4 85
-#define CLK_TOP_8BDAC 86
-
-#define CLK_TOP_AXI_SEL 87
-#define CLK_TOP_MEM_SEL 88
-#define CLK_TOP_DDRPHYCFG_SEL 89
-#define CLK_TOP_MM_SEL 90
-#define CLK_TOP_PWM_SEL 91
-#define CLK_TOP_VDEC_SEL 92
-#define CLK_TOP_MFG_SEL 93
-#define CLK_TOP_CAMTG_SEL 94
-#define CLK_TOP_UART_SEL 95
-#define CLK_TOP_SPI0_SEL 96
-#define CLK_TOP_USB20_SEL 97
-#define CLK_TOP_MSDC30_0_SEL 98
-#define CLK_TOP_MSDC30_1_SEL 99
-#define CLK_TOP_MSDC30_2_SEL 100
-#define CLK_TOP_AUDIO_SEL 101
-#define CLK_TOP_AUDINTBUS_SEL 102
-#define CLK_TOP_PMICSPI_SEL 103
-#define CLK_TOP_SCP_SEL 104
-#define CLK_TOP_DPI0_SEL 105
-#define CLK_TOP_DPI1_SEL 106
-#define CLK_TOP_TVE_SEL 107
-#define CLK_TOP_HDMI_SEL 108
-#define CLK_TOP_APLL_SEL 109
-#define CLK_TOP_RTC_SEL 110
-#define CLK_TOP_NFI2X_SEL 111
-#define CLK_TOP_EMMC_HCLK_SEL 112
-#define CLK_TOP_FLASH_SEL 113
-#define CLK_TOP_DI_SEL 114
-#define CLK_TOP_NR_SEL 115
-#define CLK_TOP_OSD_SEL 116
-#define CLK_TOP_HDMIRX_BIST_SEL 117
-#define CLK_TOP_INTDIR_SEL 118
-#define CLK_TOP_ASM_I_SEL 119
-#define CLK_TOP_ASM_M_SEL 120
-#define CLK_TOP_ASM_H_SEL 121
-#define CLK_TOP_MS_CARD_SEL 122
-#define CLK_TOP_ETHIF_SEL 123
-#define CLK_TOP_HDMIRX26_24_SEL 124
-#define CLK_TOP_MSDC30_3_SEL 125
-#define CLK_TOP_CMSYS_SEL 126
-#define CLK_TOP_SPI1_SEL 127
-#define CLK_TOP_SPI2_SEL 128
-#define CLK_TOP_8BDAC_SEL 129
-#define CLK_TOP_AUD2DVD_SEL 130
-#define CLK_TOP_PADMCLK_SEL 131
-#define CLK_TOP_AUD_MUX1_SEL 132
-#define CLK_TOP_AUD_MUX2_SEL 133
-#define CLK_TOP_AUDPLL_MUX_SEL 134
-#define CLK_TOP_AUD_K1_SRC_SEL 135
-#define CLK_TOP_AUD_K2_SRC_SEL 136
-#define CLK_TOP_AUD_K3_SRC_SEL 137
-#define CLK_TOP_AUD_K4_SRC_SEL 138
-#define CLK_TOP_AUD_K5_SRC_SEL 139
-#define CLK_TOP_AUD_K6_SRC_SEL 140
-
-#define CLK_TOP_AUD_EXTCK1_DIV 141
-#define CLK_TOP_AUD_EXTCK2_DIV 142
-#define CLK_TOP_AUD_MUX1_DIV 143
-#define CLK_TOP_AUD_MUX2_DIV 144
-#define CLK_TOP_AUD_K1_SRC_DIV 145
-#define CLK_TOP_AUD_K2_SRC_DIV 146
-#define CLK_TOP_AUD_K3_SRC_DIV 147
-#define CLK_TOP_AUD_K4_SRC_DIV 148
-#define CLK_TOP_AUD_K5_SRC_DIV 149
-#define CLK_TOP_AUD_K6_SRC_DIV 150
-#define CLK_TOP_AUD_48K_TIMING 151
-#define CLK_TOP_AUD_44K_TIMING 152
-#define CLK_TOP_AUD_I2S1_MCLK 153
-#define CLK_TOP_AUD_I2S2_MCLK 154
-#define CLK_TOP_AUD_I2S3_MCLK 155
-#define CLK_TOP_AUD_I2S4_MCLK 156
-#define CLK_TOP_AUD_I2S5_MCLK 157
-#define CLK_TOP_AUD_I2S6_MCLK 158
-#define CLK_TOP_NR 159
-
-/* APMIXEDSYS */
-#define CLK_APMIXED_ARMPLL 0
-#define CLK_APMIXED_MAINPLL 1
-#define CLK_APMIXED_UNIVPLL 2
-#define CLK_APMIXED_MMPLL 3
-#define CLK_APMIXED_MSDCPLL 4
-#define CLK_APMIXED_TVDPLL 5
-#define CLK_APMIXED_AUD1PLL 6
-#define CLK_APMIXED_TRGPLL 7
-#define CLK_APMIXED_ETHPLL 8
-#define CLK_APMIXED_VDECPLL 9
-#define CLK_APMIXED_HADDS2PLL 10
-#define CLK_APMIXED_AUD2PLL 11
-#define CLK_APMIXED_TVD2PLL 12
-#define CLK_APMIXED_NR 13
-
-/* INFRACFG */
-#define CLK_INFRA_DBG 0
-#define CLK_INFRA_SMI 1
-#define CLK_INFRA_QAXI_CM4 2
-#define CLK_INFRA_AUD_SPLIN_B 3
-#define CLK_INFRA_AUDIO 4
-#define CLK_INFRA_EFUSE 5
-#define CLK_INFRA_L2C_SRAM 6
-#define CLK_INFRA_M4U 7
-#define CLK_INFRA_CONNMCU 8
-#define CLK_INFRA_TRNG 9
-#define CLK_INFRA_RAMBUFIF 10
-#define CLK_INFRA_CPUM 11
-#define CLK_INFRA_KP 12
-#define CLK_INFRA_CEC 13
-#define CLK_INFRA_IRRX 14
-#define CLK_INFRA_PMICSPI 15
-#define CLK_INFRA_PMICWRAP 16
-#define CLK_INFRA_DDCCI 17
-#define CLK_INFRA_CPUSEL 18
-#define CLK_INFRA_NR 19
-
-/* PERICFG */
-#define CLK_PERI_NFI 0
-#define CLK_PERI_THERM 1
-#define CLK_PERI_PWM1 2
-#define CLK_PERI_PWM2 3
-#define CLK_PERI_PWM3 4
-#define CLK_PERI_PWM4 5
-#define CLK_PERI_PWM5 6
-#define CLK_PERI_PWM6 7
-#define CLK_PERI_PWM7 8
-#define CLK_PERI_PWM 9
-#define CLK_PERI_USB0 10
-#define CLK_PERI_USB1 11
-#define CLK_PERI_AP_DMA 12
-#define CLK_PERI_MSDC30_0 13
-#define CLK_PERI_MSDC30_1 14
-#define CLK_PERI_MSDC30_2 15
-#define CLK_PERI_MSDC30_3 16
-#define CLK_PERI_MSDC50_3 17
-#define CLK_PERI_NLI 18
-#define CLK_PERI_UART0 19
-#define CLK_PERI_UART1 20
-#define CLK_PERI_UART2 21
-#define CLK_PERI_UART3 22
-#define CLK_PERI_BTIF 23
-#define CLK_PERI_I2C0 24
-#define CLK_PERI_I2C1 25
-#define CLK_PERI_I2C2 26
-#define CLK_PERI_I2C3 27
-#define CLK_PERI_AUXADC 28
-#define CLK_PERI_SPI0 39
-#define CLK_PERI_ETH 30
-#define CLK_PERI_USB0_MCU 31
-
-#define CLK_PERI_USB1_MCU 32
-#define CLK_PERI_USB_SLV 33
-#define CLK_PERI_GCPU 34
-#define CLK_PERI_NFI_ECC 35
-#define CLK_PERI_NFI_PAD 36
-#define CLK_PERI_FLASH 37
-#define CLK_PERI_HOST89_INT 38
-#define CLK_PERI_HOST89_SPI 39
-#define CLK_PERI_HOST89_DVD 40
-#define CLK_PERI_SPI1 41
-#define CLK_PERI_SPI2 42
-#define CLK_PERI_FCI 43
-#define CLK_PERI_NR 44
-
-/* AUDIO */
-#define CLK_AUD_AFE 0
-#define CLK_AUD_LRCK_DETECT 1
-#define CLK_AUD_I2S 2
-#define CLK_AUD_APLL_TUNER 3
-#define CLK_AUD_HDMI 4
-#define CLK_AUD_SPDF 5
-#define CLK_AUD_SPDF2 6
-#define CLK_AUD_APLL 7
-#define CLK_AUD_TML 8
-#define CLK_AUD_AHB_IDLE_EXT 9
-#define CLK_AUD_AHB_IDLE_INT 10
-
-#define CLK_AUD_I2SIN1 11
-#define CLK_AUD_I2SIN2 12
-#define CLK_AUD_I2SIN3 13
-#define CLK_AUD_I2SIN4 14
-#define CLK_AUD_I2SIN5 15
-#define CLK_AUD_I2SIN6 16
-#define CLK_AUD_I2SO1 17
-#define CLK_AUD_I2SO2 18
-#define CLK_AUD_I2SO3 19
-#define CLK_AUD_I2SO4 20
-#define CLK_AUD_I2SO5 21
-#define CLK_AUD_I2SO6 22
-#define CLK_AUD_ASRCI1 23
-#define CLK_AUD_ASRCI2 24
-#define CLK_AUD_ASRCO1 25
-#define CLK_AUD_ASRCO2 26
-#define CLK_AUD_ASRC11 27
-#define CLK_AUD_ASRC12 28
-#define CLK_AUD_HDMIRX 29
-#define CLK_AUD_INTDIR 30
-#define CLK_AUD_A1SYS 31
-#define CLK_AUD_A2SYS 32
-#define CLK_AUD_AFE_CONN 33
-#define CLK_AUD_AFE_PCMIF 34
-#define CLK_AUD_AFE_MRGIF 35
-
-#define CLK_AUD_MMIF_UL1 36
-#define CLK_AUD_MMIF_UL2 37
-#define CLK_AUD_MMIF_UL3 38
-#define CLK_AUD_MMIF_UL4 39
-#define CLK_AUD_MMIF_UL5 40
-#define CLK_AUD_MMIF_UL6 41
-#define CLK_AUD_MMIF_DL1 42
-#define CLK_AUD_MMIF_DL2 43
-#define CLK_AUD_MMIF_DL3 44
-#define CLK_AUD_MMIF_DL4 45
-#define CLK_AUD_MMIF_DL5 46
-#define CLK_AUD_MMIF_DL6 47
-#define CLK_AUD_MMIF_DLMCH 48
-#define CLK_AUD_MMIF_ARB1 49
-#define CLK_AUD_MMIF_AWB1 50
-#define CLK_AUD_MMIF_AWB2 51
-#define CLK_AUD_MMIF_DAI 52
-
-#define CLK_AUD_DMIC1 53
-#define CLK_AUD_DMIC2 54
-#define CLK_AUD_ASRCI3 55
-#define CLK_AUD_ASRCI4 56
-#define CLK_AUD_ASRCI5 57
-#define CLK_AUD_ASRCI6 58
-#define CLK_AUD_ASRCO3 59
-#define CLK_AUD_ASRCO4 60
-#define CLK_AUD_ASRCO5 61
-#define CLK_AUD_ASRCO6 62
-#define CLK_AUD_MEM_ASRC1 63
-#define CLK_AUD_MEM_ASRC2 64
-#define CLK_AUD_MEM_ASRC3 65
-#define CLK_AUD_MEM_ASRC4 66
-#define CLK_AUD_MEM_ASRC5 67
-#define CLK_AUD_DSD_ENC 68
-#define CLK_AUD_ASRC_BRG 60
-#define CLK_AUD_NR 70
-
-/* MMSYS */
-#define CLK_MM_SMI_COMMON 0
-#define CLK_MM_SMI_LARB0 1
-#define CLK_MM_CMDQ 2
-#define CLK_MM_MUTEX 3
-#define CLK_MM_DISP_COLOR 4
-#define CLK_MM_DISP_BLS 5
-#define CLK_MM_DISP_WDMA 6
-#define CLK_MM_DISP_RDMA 7
-#define CLK_MM_DISP_OVL 8
-#define CLK_MM_MDP_TDSHP 9
-#define CLK_MM_MDP_WROT 10
-#define CLK_MM_MDP_WDMA 11
-#define CLK_MM_MDP_RSZ1 12
-#define CLK_MM_MDP_RSZ0 13
-#define CLK_MM_MDP_RDMA 14
-#define CLK_MM_MDP_BLS_26M 15
-#define CLK_MM_CAM_MDP 16
-#define CLK_MM_FAKE_ENG 17
-#define CLK_MM_MUTEX_32K 18
-#define CLK_MM_DISP_RDMA1 19
-#define CLK_MM_DISP_UFOE 20
-
-#define CLK_MM_DSI_ENGINE 21
-#define CLK_MM_DSI_DIG 22
-#define CLK_MM_DPI_DIGL 23
-#define CLK_MM_DPI_ENGINE 24
-#define CLK_MM_DPI1_DIGL 25
-#define CLK_MM_DPI1_ENGINE 26
-#define CLK_MM_TVE_OUTPUT 27
-#define CLK_MM_TVE_INPUT 28
-#define CLK_MM_HDMI_PIXEL 29
-#define CLK_MM_HDMI_PLL 30
-#define CLK_MM_HDMI_AUDIO 31
-#define CLK_MM_HDMI_SPDIF 32
-#define CLK_MM_TVE_FMM 33
-#define CLK_MM_NR 34
-
-/* IMGSYS */
-#define CLK_IMG_SMI_COMM 0
-#define CLK_IMG_RESZ 1
-#define CLK_IMG_JPGDEC_SMI 2
-#define CLK_IMG_JPGDEC 3
-#define CLK_IMG_VENC_LT 4
-#define CLK_IMG_VENC 5
-#define CLK_IMG_NR 6
-
-/* VDEC */
-#define CLK_VDEC_CKGEN 0
-#define CLK_VDEC_LARB 1
-#define CLK_VDEC_NR 2
-
-/* HIFSYS */
-#define CLK_HIFSYS_USB0PHY 0
-#define CLK_HIFSYS_USB1PHY 1
-#define CLK_HIFSYS_PCIE0 2
-#define CLK_HIFSYS_PCIE1 3
-#define CLK_HIFSYS_PCIE2 4
-#define CLK_HIFSYS_NR 5
-
-/* ETHSYS */
-#define CLK_ETHSYS_HSDMA 0
-#define CLK_ETHSYS_ESW 1
-#define CLK_ETHSYS_GP2 2
-#define CLK_ETHSYS_GP1 3
-#define CLK_ETHSYS_PCM 4
-#define CLK_ETHSYS_GDMA 5
-#define CLK_ETHSYS_I2S 6
-#define CLK_ETHSYS_CRYPTO 7
-#define CLK_ETHSYS_NR 8
-
-/* G3DSYS */
-#define CLK_G3DSYS_CORE 0
-#define CLK_G3DSYS_NR 1
-
-#endif /* _DT_BINDINGS_CLK_MT2701_H */
diff --git a/include/dt-bindings/clock/mt7628-clk.h b/include/dt-bindings/clock/mt7628-clk.h
deleted file mode 100644
index b5866fd..0000000
--- a/include/dt-bindings/clock/mt7628-clk.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2019 MediaTek Inc.
- *
- * Author: Weijie Gao <weijie.gao@mediatek.com>
- */
-
-#ifndef _DT_BINDINGS_MT7628_CLK_H_
-#define _DT_BINDINGS_MT7628_CLK_H_
-
-/* Base clocks */
-#define CLK_SYS 34
-#define CLK_CPU 33
-#define CLK_XTAL 32
-
-/* Peripheral clocks */
-#define CLK_PWM 31
-#define CLK_SDXC 30
-#define CLK_CRYPTO 29
-#define CLK_MIPS_CNT 28
-#define CLK_PCIE 26
-#define CLK_UPHY 25
-#define CLK_ETH 23
-#define CLK_UART2 20
-#define CLK_UART1 19
-#define CLK_SPI 18
-#define CLK_I2S 17
-#define CLK_I2C 16
-#define CLK_GDMA 14
-#define CLK_PIO 13
-#define CLK_UART0 12
-#define CLK_PCM 11
-#define CLK_MC 10
-#define CLK_INTC 9
-#define CLK_TIMER 8
-
-#endif /* _DT_BINDINGS_MT7628_CLK_H_ */
diff --git a/include/dt-bindings/clock/mt7629-clk.h b/include/dt-bindings/clock/mt7629-clk.h
deleted file mode 100644
index 0bbfbfa..0000000
--- a/include/dt-bindings/clock/mt7629-clk.h
+++ /dev/null
@@ -1,206 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2018 MediaTek Inc.
- */
-
-#ifndef _DT_BINDINGS_CLK_MT7629_H
-#define _DT_BINDINGS_CLK_MT7629_H
-
-/* TOPCKGEN */
-#define CLK_TOP_FCLKS_OFF 0
-
-#define CLK_TOP_TO_U2_PHY 0
-#define CLK_TOP_TO_U2_PHY_1P 1
-#define CLK_TOP_PCIE0_PIPE_EN 2
-#define CLK_TOP_PCIE1_PIPE_EN 3
-#define CLK_TOP_SSUSB_TX250M 4
-#define CLK_TOP_SSUSB_EQ_RX250M 5
-#define CLK_TOP_SSUSB_CDR_REF 6
-#define CLK_TOP_SSUSB_CDR_FB 7
-#define CLK_TOP_SATA_ASIC 8
-#define CLK_TOP_SATA_RBC 9
-
-#define CLK_TOP_TO_USB3_SYS 10
-#define CLK_TOP_P1_1MHZ 11
-#define CLK_TOP_4MHZ 12
-#define CLK_TOP_P0_1MHZ 13
-#define CLK_TOP_ETH_500M 14
-#define CLK_TOP_TXCLK_SRC_PRE 15
-#define CLK_TOP_RTC 16
-#define CLK_TOP_PWM_QTR_26M 17
-#define CLK_TOP_CPUM_TCK_IN 18
-#define CLK_TOP_TO_USB3_DA_TOP 19
-#define CLK_TOP_MEMPLL 20
-#define CLK_TOP_DMPLL 21
-#define CLK_TOP_DMPLL_D4 22
-#define CLK_TOP_DMPLL_D8 23
-#define CLK_TOP_SYSPLL_D2 24
-#define CLK_TOP_SYSPLL1_D2 25
-#define CLK_TOP_SYSPLL1_D4 26
-#define CLK_TOP_SYSPLL1_D8 27
-#define CLK_TOP_SYSPLL1_D16 28
-#define CLK_TOP_SYSPLL2_D2 29
-#define CLK_TOP_SYSPLL2_D4 30
-#define CLK_TOP_SYSPLL2_D8 31
-#define CLK_TOP_SYSPLL_D5 32
-#define CLK_TOP_SYSPLL3_D2 33
-#define CLK_TOP_SYSPLL3_D4 34
-#define CLK_TOP_SYSPLL_D7 35
-#define CLK_TOP_SYSPLL4_D2 36
-#define CLK_TOP_SYSPLL4_D4 37
-#define CLK_TOP_SYSPLL4_D16 38
-#define CLK_TOP_UNIVPLL 39
-#define CLK_TOP_UNIVPLL1_D2 40
-#define CLK_TOP_UNIVPLL1_D4 41
-#define CLK_TOP_UNIVPLL1_D8 42
-#define CLK_TOP_UNIVPLL_D3 43
-#define CLK_TOP_UNIVPLL2_D2 44
-#define CLK_TOP_UNIVPLL2_D4 45
-#define CLK_TOP_UNIVPLL2_D8 46
-#define CLK_TOP_UNIVPLL2_D16 47
-#define CLK_TOP_UNIVPLL_D5 48
-#define CLK_TOP_UNIVPLL3_D2 49
-#define CLK_TOP_UNIVPLL3_D4 50
-#define CLK_TOP_UNIVPLL3_D16 51
-#define CLK_TOP_UNIVPLL_D7 52
-#define CLK_TOP_UNIVPLL_D80_D4 53
-#define CLK_TOP_UNIV48M 54
-#define CLK_TOP_SGMIIPLL_D2 55
-#define CLK_TOP_CLKXTAL_D4 56
-#define CLK_TOP_HD_FAXI 57
-#define CLK_TOP_FAXI 58
-#define CLK_TOP_F_FAUD_INTBUS 59
-#define CLK_TOP_AP2WBHIF_HCLK 60
-#define CLK_TOP_10M_INFRAO 61
-#define CLK_TOP_MSDC30_1 62
-#define CLK_TOP_SPI 63
-#define CLK_TOP_SF 64
-#define CLK_TOP_FLASH 65
-#define CLK_TOP_TO_USB3_REF 66
-#define CLK_TOP_TO_USB3_MCU 67
-#define CLK_TOP_TO_USB3_DMA 68
-#define CLK_TOP_FROM_TOP_AHB 69
-#define CLK_TOP_FROM_TOP_AXI 70
-#define CLK_TOP_PCIE1_MAC_EN 71
-#define CLK_TOP_PCIE0_MAC_EN 72
-
-#define CLK_TOP_AXI_SEL 73
-#define CLK_TOP_MEM_SEL 74
-#define CLK_TOP_DDRPHYCFG_SEL 75
-#define CLK_TOP_ETH_SEL 76
-#define CLK_TOP_PWM_SEL 77
-#define CLK_TOP_F10M_REF_SEL 78
-#define CLK_TOP_NFI_INFRA_SEL 79
-#define CLK_TOP_FLASH_SEL 80
-#define CLK_TOP_UART_SEL 81
-#define CLK_TOP_SPI0_SEL 82
-#define CLK_TOP_SPI1_SEL 83
-#define CLK_TOP_MSDC50_0_SEL 84
-#define CLK_TOP_MSDC30_0_SEL 85
-#define CLK_TOP_MSDC30_1_SEL 86
-#define CLK_TOP_AP2WBMCU_SEL 87
-#define CLK_TOP_AP2WBHIF_SEL 88
-#define CLK_TOP_AUDIO_SEL 89
-#define CLK_TOP_AUD_INTBUS_SEL 90
-#define CLK_TOP_PMICSPI_SEL 91
-#define CLK_TOP_SCP_SEL 92
-#define CLK_TOP_ATB_SEL 93
-#define CLK_TOP_HIF_SEL 94
-#define CLK_TOP_SATA_SEL 95
-#define CLK_TOP_U2_SEL 96
-#define CLK_TOP_AUD1_SEL 97
-#define CLK_TOP_AUD2_SEL 98
-#define CLK_TOP_IRRX_SEL 99
-#define CLK_TOP_IRTX_SEL 100
-#define CLK_TOP_SATA_MCU_SEL 101
-#define CLK_TOP_PCIE0_MCU_SEL 102
-#define CLK_TOP_PCIE1_MCU_SEL 103
-#define CLK_TOP_SSUSB_MCU_SEL 104
-#define CLK_TOP_CRYPTO_SEL 105
-#define CLK_TOP_SGMII_REF_1_SEL 106
-#define CLK_TOP_10M_SEL 107
-#define CLK_TOP_NR_CLK 108
-
-/* INFRACFG */
-#define CLK_INFRA_MUX1_SEL 0
-#define CLK_INFRA_DBGCLK_PD 1
-#define CLK_INFRA_TRNG_PD 2
-#define CLK_INFRA_DEVAPC_PD 3
-#define CLK_INFRA_APXGPT_PD 4
-#define CLK_INFRA_SEJ_PD 5
-#define CLK_INFRA_NR_CLK 6
-
-/* PERICFG */
-#define CLK_PERIBUS_SEL 0
-#define CLK_PERI_PWM1_PD 1
-#define CLK_PERI_PWM2_PD 2
-#define CLK_PERI_PWM3_PD 3
-#define CLK_PERI_PWM4_PD 4
-#define CLK_PERI_PWM5_PD 5
-#define CLK_PERI_PWM6_PD 6
-#define CLK_PERI_PWM7_PD 7
-#define CLK_PERI_PWM_PD 8
-#define CLK_PERI_AP_DMA_PD 9
-#define CLK_PERI_MSDC30_1_PD 10
-#define CLK_PERI_UART0_PD 11
-#define CLK_PERI_UART1_PD 12
-#define CLK_PERI_UART2_PD 13
-#define CLK_PERI_UART3_PD 14
-#define CLK_PERI_BTIF_PD 15
-#define CLK_PERI_I2C0_PD 16
-#define CLK_PERI_SPI0_PD 17
-#define CLK_PERI_SNFI_PD 18
-#define CLK_PERI_NFI_PD 19
-#define CLK_PERI_NFIECC_PD 20
-#define CLK_PERI_FLASH_PD 21
-#define CLK_PERI_NR_CLK 22
-
-/* APMIXEDSYS */
-#define CLK_APMIXED_ARMPLL 0
-#define CLK_APMIXED_MAINPLL 1
-#define CLK_APMIXED_UNIV2PLL 2
-#define CLK_APMIXED_ETH1PLL 3
-#define CLK_APMIXED_ETH2PLL 4
-#define CLK_APMIXED_SGMIPLL 5
-#define CLK_APMIXED_NR_CLK 6
-
-/* SSUSBSYS */
-#define CLK_SSUSB_U2_PHY_1P_EN 0
-#define CLK_SSUSB_U2_PHY_EN 1
-#define CLK_SSUSB_REF_EN 2
-#define CLK_SSUSB_SYS_EN 3
-#define CLK_SSUSB_MCU_EN 4
-#define CLK_SSUSB_DMA_EN 5
-#define CLK_SSUSB_NR_CLK 6
-
-/* PCIESYS */
-#define CLK_PCIE_P1_AUX_EN 0
-#define CLK_PCIE_P1_OBFF_EN 1
-#define CLK_PCIE_P1_AHB_EN 2
-#define CLK_PCIE_P1_AXI_EN 3
-#define CLK_PCIE_P1_MAC_EN 4
-#define CLK_PCIE_P1_PIPE_EN 5
-#define CLK_PCIE_P0_AUX_EN 6
-#define CLK_PCIE_P0_OBFF_EN 7
-#define CLK_PCIE_P0_AHB_EN 8
-#define CLK_PCIE_P0_AXI_EN 9
-#define CLK_PCIE_P0_MAC_EN 10
-#define CLK_PCIE_P0_PIPE_EN 11
-#define CLK_PCIE_NR_CLK 12
-
-/* ETHSYS */
-#define CLK_ETH_FE_EN 0
-#define CLK_ETH_GP2_EN 1
-#define CLK_ETH_GP1_EN 2
-#define CLK_ETH_GP0_EN 3
-#define CLK_ETH_ESW_EN 4
-#define CLK_ETH_NR_CLK 5
-
-/* SGMIISYS */
-#define CLK_SGMII_TX_EN 0
-#define CLK_SGMII_RX_EN 1
-#define CLK_SGMII_CDR_REF 2
-#define CLK_SGMII_CDR_FB 3
-#define CLK_SGMII_NR_CLK 4
-
-#endif /* _DT_BINDINGS_CLK_MT7629_H */
diff --git a/include/dt-bindings/clock/mt8516-clk.h b/include/dt-bindings/clock/mt8516-clk.h
deleted file mode 100644
index 745b87f..0000000
--- a/include/dt-bindings/clock/mt8516-clk.h
+++ /dev/null
@@ -1,251 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (c) 2018 BayLibre, SAS
- * Copyright (c) 2018 MediaTek Inc.
- * Author: Fabien Parent <fparent@baylibre.com>
- */
-
-#ifndef _DT_BINDINGS_CLK_MT8516_H
-#define _DT_BINDINGS_CLK_MT8516_H
-
-
-/* APMIXEDSYS */
-
-#define CLK_APMIXED_ARMPLL 0
-#define CLK_APMIXED_MAINPLL 1
-#define CLK_APMIXED_UNIVPLL 2
-#define CLK_APMIXED_MMPLL 3
-#define CLK_APMIXED_APLL1 4
-#define CLK_APMIXED_APLL2 5
-#define CLK_APMIXED_NR_CLK 6
-
-/* TOPCKGEN */
-
-#define CLK_TOP_CLK_NULL 0
-#define CLK_TOP_I2S_INFRA_BCK 1
-#define CLK_TOP_MEMPLL 2
-#define CLK_TOP_DMPLL 3
-#define CLK_TOP_MAINPLL_D2 4
-#define CLK_TOP_MAINPLL_D4 5
-#define CLK_TOP_MAINPLL_D8 6
-#define CLK_TOP_MAINPLL_D16 7
-#define CLK_TOP_MAINPLL_D11 8
-#define CLK_TOP_MAINPLL_D22 9
-#define CLK_TOP_MAINPLL_D3 10
-#define CLK_TOP_MAINPLL_D6 11
-#define CLK_TOP_MAINPLL_D12 12
-#define CLK_TOP_MAINPLL_D5 13
-#define CLK_TOP_MAINPLL_D10 14
-#define CLK_TOP_MAINPLL_D20 15
-#define CLK_TOP_MAINPLL_D40 16
-#define CLK_TOP_MAINPLL_D7 17
-#define CLK_TOP_MAINPLL_D14 18
-#define CLK_TOP_UNIVPLL_D2 19
-#define CLK_TOP_UNIVPLL_D4 20
-#define CLK_TOP_UNIVPLL_D8 21
-#define CLK_TOP_UNIVPLL_D16 22
-#define CLK_TOP_UNIVPLL_D3 23
-#define CLK_TOP_UNIVPLL_D6 24
-#define CLK_TOP_UNIVPLL_D12 25
-#define CLK_TOP_UNIVPLL_D24 26
-#define CLK_TOP_UNIVPLL_D5 27
-#define CLK_TOP_UNIVPLL_D20 28
-#define CLK_TOP_MMPLL380M 29
-#define CLK_TOP_MMPLL_D2 30
-#define CLK_TOP_MMPLL_200M 31
-#define CLK_TOP_USB_PHY48M 32
-#define CLK_TOP_APLL1 33
-#define CLK_TOP_APLL1_D2 34
-#define CLK_TOP_APLL1_D4 35
-#define CLK_TOP_APLL1_D8 36
-#define CLK_TOP_APLL2 37
-#define CLK_TOP_APLL2_D2 38
-#define CLK_TOP_APLL2_D4 39
-#define CLK_TOP_APLL2_D8 40
-#define CLK_TOP_CLK26M 41
-#define CLK_TOP_CLK26M_D2 42
-#define CLK_TOP_AHB_INFRA_D2 43
-#define CLK_TOP_NFI1X 44
-#define CLK_TOP_ETH_D2 45
-#define CLK_TOP_UART0_SEL 46
-#define CLK_TOP_GFMUX_EMI1X_SEL 47
-#define CLK_TOP_EMI_DDRPHY_SEL 48
-#define CLK_TOP_AHB_INFRA_SEL 49
-#define CLK_TOP_CSW_MUX_MFG_SEL 50
-#define CLK_TOP_MSDC0_SEL 51
-#define CLK_TOP_PWM_MM_SEL 52
-#define CLK_TOP_UART1_SEL 53
-#define CLK_TOP_MSDC1_SEL 54
-#define CLK_TOP_SPM_52M_SEL 55
-#define CLK_TOP_PMICSPI_SEL 56
-#define CLK_TOP_QAXI_AUD26M_SEL 57
-#define CLK_TOP_AUD_INTBUS_SEL 58
-#define CLK_TOP_NFI2X_PAD_SEL 59
-#define CLK_TOP_NFI1X_PAD_SEL 60
-#define CLK_TOP_MFG_MM_SEL 61
-#define CLK_TOP_DDRPHYCFG_SEL 62
-#define CLK_TOP_USB_78M_SEL 63
-#define CLK_TOP_SPINOR_SEL 64
-#define CLK_TOP_MSDC2_SEL 65
-#define CLK_TOP_ETH_SEL 66
-#define CLK_TOP_AXI_MFG_IN_SEL 67
-#define CLK_TOP_SLOW_MFG_SEL 68
-#define CLK_TOP_AUD1_SEL 69
-#define CLK_TOP_AUD2_SEL 70
-#define CLK_TOP_AUD_ENGEN1_SEL 71
-#define CLK_TOP_AUD_ENGEN2_SEL 72
-#define CLK_TOP_I2C_SEL 73
-#define CLK_TOP_AUD_I2S0_M_SEL 74
-#define CLK_TOP_AUD_I2S1_M_SEL 75
-#define CLK_TOP_AUD_I2S2_M_SEL 76
-#define CLK_TOP_AUD_I2S3_M_SEL 77
-#define CLK_TOP_AUD_I2S4_M_SEL 78
-#define CLK_TOP_AUD_I2S5_M_SEL 79
-#define CLK_TOP_AUD_SPDIF_B_SEL 80
-#define CLK_TOP_PWM_SEL 81
-#define CLK_TOP_SPI_SEL 82
-#define CLK_TOP_AUD_SPDIFIN_SEL 83
-#define CLK_TOP_UART2_SEL 84
-#define CLK_TOP_BSI_SEL 85
-#define CLK_TOP_DBG_ATCLK_SEL 86
-#define CLK_TOP_CSW_NFIECC_SEL 87
-#define CLK_TOP_NFIECC_SEL 88
-#define CLK_TOP_APLL12_CK_DIV0 89
-#define CLK_TOP_APLL12_CK_DIV1 90
-#define CLK_TOP_APLL12_CK_DIV2 91
-#define CLK_TOP_APLL12_CK_DIV3 92
-#define CLK_TOP_APLL12_CK_DIV4 93
-#define CLK_TOP_APLL12_CK_DIV4B 94
-#define CLK_TOP_APLL12_CK_DIV5 95
-#define CLK_TOP_APLL12_CK_DIV5B 96
-#define CLK_TOP_APLL12_CK_DIV6 97
-#define CLK_TOP_NR_CLK 98
-
-/* TOPCKGEN Gates */
-#define CLK_TOP_PWM_MM 0
-#define CLK_TOP_MFG_MM 1
-#define CLK_TOP_SPM_52M 2
-#define CLK_TOP_THEM 3
-#define CLK_TOP_APDMA 4
-#define CLK_TOP_I2C0 5
-#define CLK_TOP_I2C1 6
-#define CLK_TOP_AUXADC1 7
-#define CLK_TOP_NFI 8
-#define CLK_TOP_NFIECC 9
-#define CLK_TOP_DEBUGSYS 10
-#define CLK_TOP_PWM 11
-#define CLK_TOP_UART0 12
-#define CLK_TOP_UART1 13
-#define CLK_TOP_BTIF 14
-#define CLK_TOP_USB 15
-#define CLK_TOP_FLASHIF_26M 16
-#define CLK_TOP_AUXADC2 17
-#define CLK_TOP_I2C2 18
-#define CLK_TOP_MSDC0 19
-#define CLK_TOP_MSDC1 20
-#define CLK_TOP_NFI2X 21
-#define CLK_TOP_PMICWRAP_AP 22
-#define CLK_TOP_SEJ 23
-#define CLK_TOP_MEMSLP_DLYER 24
-#define CLK_TOP_SPI 25
-#define CLK_TOP_APXGPT 26
-#define CLK_TOP_AUDIO 27
-#define CLK_TOP_PMICWRAP_MD 28
-#define CLK_TOP_PMICWRAP_CONN 29
-#define CLK_TOP_PMICWRAP_26M 30
-#define CLK_TOP_AUX_ADC 31
-#define CLK_TOP_AUX_TP 32
-#define CLK_TOP_MSDC2 33
-#define CLK_TOP_RBIST 34
-#define CLK_TOP_NFI_BUS 35
-#define CLK_TOP_GCE 36
-#define CLK_TOP_TRNG 37
-#define CLK_TOP_SEJ_13M 38
-#define CLK_TOP_AES 39
-#define CLK_TOP_PWM_B 40
-#define CLK_TOP_PWM1_FB 41
-#define CLK_TOP_PWM2_FB 42
-#define CLK_TOP_PWM3_FB 43
-#define CLK_TOP_PWM4_FB 44
-#define CLK_TOP_PWM5_FB 45
-#define CLK_TOP_USB_1P 46
-#define CLK_TOP_FLASHIF_FREERUN 47
-#define CLK_TOP_66M_ETH 48
-#define CLK_TOP_133M_ETH 49
-#define CLK_TOP_FETH_25M 50
-#define CLK_TOP_FETH_50M 51
-#define CLK_TOP_FLASHIF_AXI 52
-#define CLK_TOP_USBIF 53
-#define CLK_TOP_UART2 54
-#define CLK_TOP_BSI 55
-#define CLK_TOP_MSDC0_INFRA 56
-#define CLK_TOP_MSDC1_INFRA 57
-#define CLK_TOP_MSDC2_INFRA 58
-#define CLK_TOP_USB_78M 59
-#define CLK_TOP_RG_SPINOR 60
-#define CLK_TOP_RG_MSDC2 61
-#define CLK_TOP_RG_ETH 62
-#define CLK_TOP_RG_AXI_MFG 63
-#define CLK_TOP_RG_SLOW_MFG 64
-#define CLK_TOP_RG_AUD1 65
-#define CLK_TOP_RG_AUD2 66
-#define CLK_TOP_RG_AUD_ENGEN1 67
-#define CLK_TOP_RG_AUD_ENGEN2 68
-#define CLK_TOP_RG_I2C 69
-#define CLK_TOP_RG_PWM_INFRA 70
-#define CLK_TOP_RG_AUD_SPDIF_IN 71
-#define CLK_TOP_RG_UART2 72
-#define CLK_TOP_RG_BSI 73
-#define CLK_TOP_RG_DBG_ATCLK 74
-#define CLK_TOP_RG_NFIECC 75
-#define CLK_TOP_RG_APLL1_D2_EN 76
-#define CLK_TOP_RG_APLL1_D4_EN 77
-#define CLK_TOP_RG_APLL1_D8_EN 78
-#define CLK_TOP_RG_APLL2_D2_EN 79
-#define CLK_TOP_RG_APLL2_D4_EN 80
-#define CLK_TOP_RG_APLL2_D8_EN 81
-#define CLK_TOP_APLL12_DIV0 82
-#define CLK_TOP_APLL12_DIV1 83
-#define CLK_TOP_APLL12_DIV2 84
-#define CLK_TOP_APLL12_DIV3 85
-#define CLK_TOP_APLL12_DIV4 86
-#define CLK_TOP_APLL12_DIV4B 87
-#define CLK_TOP_APLL12_DIV5 88
-#define CLK_TOP_APLL12_DIV5B 89
-#define CLK_TOP_APLL12_DIV6 90
-
-/* INFRACFG */
-
-#define CLK_IFR_MUX1_SEL 0
-#define CLK_IFR_ETH_25M_SEL 1
-#define CLK_IFR_I2C0_SEL 2
-#define CLK_IFR_I2C1_SEL 3
-#define CLK_IFR_I2C2_SEL 4
-#define CLK_IFR_NR_CLK 5
-
-/* AUDIOTOP */
-
-#define CLK_AUD_AFE 0
-#define CLK_AUD_I2S 1
-#define CLK_AUD_22M 2
-#define CLK_AUD_24M 3
-#define CLK_AUD_INTDIR 4
-#define CLK_AUD_APLL2_TUNER 5
-#define CLK_AUD_APLL_TUNER 6
-#define CLK_AUD_HDMI 7
-#define CLK_AUD_SPDF 8
-#define CLK_AUD_ADC 9
-#define CLK_AUD_DAC 10
-#define CLK_AUD_DAC_PREDIS 11
-#define CLK_AUD_TML 12
-#define CLK_AUD_NR_CLK 13
-
-/* MFGCFG */
-
-#define CLK_MFG_BAXI 0
-#define CLK_MFG_BMEM 1
-#define CLK_MFG_BG3D 2
-#define CLK_MFG_B26M 3
-#define CLK_MFG_NR_CLK 4
-
-#endif /* _DT_BINDINGS_CLK_MT8516_H */
diff --git a/include/dt-bindings/clock/r7s72100-clock.h b/include/dt-bindings/clock/r7s72100-clock.h
deleted file mode 100644
index a267ac2..0000000
--- a/include/dt-bindings/clock/r7s72100-clock.h
+++ /dev/null
@@ -1,112 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0
- *
- * Copyright (C) 2014 Renesas Solutions Corp.
- * Copyright (C) 2014 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com>
- */
-
-#ifndef __DT_BINDINGS_CLOCK_R7S72100_H__
-#define __DT_BINDINGS_CLOCK_R7S72100_H__
-
-#define R7S72100_CLK_PLL 0
-#define R7S72100_CLK_I 1
-#define R7S72100_CLK_G 2
-
-/* MSTP2 */
-#define R7S72100_CLK_CORESIGHT 0
-
-/* MSTP3 */
-#define R7S72100_CLK_IEBUS 7
-#define R7S72100_CLK_IRDA 6
-#define R7S72100_CLK_LIN0 5
-#define R7S72100_CLK_LIN1 4
-#define R7S72100_CLK_MTU2 3
-#define R7S72100_CLK_CAN 2
-#define R7S72100_CLK_ADCPWR 1
-#define R7S72100_CLK_PWM 0
-
-/* MSTP4 */
-#define R7S72100_CLK_SCIF0 7
-#define R7S72100_CLK_SCIF1 6
-#define R7S72100_CLK_SCIF2 5
-#define R7S72100_CLK_SCIF3 4
-#define R7S72100_CLK_SCIF4 3
-#define R7S72100_CLK_SCIF5 2
-#define R7S72100_CLK_SCIF6 1
-#define R7S72100_CLK_SCIF7 0
-
-/* MSTP5 */
-#define R7S72100_CLK_SCI0 7
-#define R7S72100_CLK_SCI1 6
-#define R7S72100_CLK_SG0 5
-#define R7S72100_CLK_SG1 4
-#define R7S72100_CLK_SG2 3
-#define R7S72100_CLK_SG3 2
-#define R7S72100_CLK_OSTM0 1
-#define R7S72100_CLK_OSTM1 0
-
-/* MSTP6 */
-#define R7S72100_CLK_ADC 7
-#define R7S72100_CLK_CEU 6
-#define R7S72100_CLK_DOC0 5
-#define R7S72100_CLK_DOC1 4
-#define R7S72100_CLK_DRC0 3
-#define R7S72100_CLK_DRC1 2
-#define R7S72100_CLK_JCU 1
-#define R7S72100_CLK_RTC 0
-
-/* MSTP7 */
-#define R7S72100_CLK_VDEC0 7
-#define R7S72100_CLK_VDEC1 6
-#define R7S72100_CLK_ETHER 4
-#define R7S72100_CLK_NAND 3
-#define R7S72100_CLK_USB0 1
-#define R7S72100_CLK_USB1 0
-
-/* MSTP8 */
-#define R7S72100_CLK_IMR0 7
-#define R7S72100_CLK_IMR1 6
-#define R7S72100_CLK_IMRDISP 5
-#define R7S72100_CLK_MMCIF 4
-#define R7S72100_CLK_MLB 3
-#define R7S72100_CLK_ETHAVB 2
-#define R7S72100_CLK_SCUX 1
-
-/* MSTP9 */
-#define R7S72100_CLK_I2C0 7
-#define R7S72100_CLK_I2C1 6
-#define R7S72100_CLK_I2C2 5
-#define R7S72100_CLK_I2C3 4
-#define R7S72100_CLK_SPIBSC0 3
-#define R7S72100_CLK_SPIBSC1 2
-#define R7S72100_CLK_VDC50 1 /* and LVDS */
-#define R7S72100_CLK_VDC51 0
-
-/* MSTP10 */
-#define R7S72100_CLK_SPI0 7
-#define R7S72100_CLK_SPI1 6
-#define R7S72100_CLK_SPI2 5
-#define R7S72100_CLK_SPI3 4
-#define R7S72100_CLK_SPI4 3
-#define R7S72100_CLK_CDROM 2
-#define R7S72100_CLK_SPDIF 1
-#define R7S72100_CLK_RGPVG2 0
-
-/* MSTP11 */
-#define R7S72100_CLK_SSI0 5
-#define R7S72100_CLK_SSI1 4
-#define R7S72100_CLK_SSI2 3
-#define R7S72100_CLK_SSI3 2
-#define R7S72100_CLK_SSI4 1
-#define R7S72100_CLK_SSI5 0
-
-/* MSTP12 */
-#define R7S72100_CLK_SDHI00 3
-#define R7S72100_CLK_SDHI01 2
-#define R7S72100_CLK_SDHI10 1
-#define R7S72100_CLK_SDHI11 0
-
-/* MSTP13 */
-#define R7S72100_CLK_PIX1 2
-#define R7S72100_CLK_PIX0 1
-
-#endif /* __DT_BINDINGS_CLOCK_R7S72100_H__ */
diff --git a/include/dt-bindings/clock/r8a7790-clock.h b/include/dt-bindings/clock/r8a7790-clock.h
deleted file mode 100644
index 20641fa..0000000
--- a/include/dt-bindings/clock/r8a7790-clock.h
+++ /dev/null
@@ -1,162 +0,0 @@
-/*
- * Copyright 2013 Ideas On Board SPRL
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#ifndef __DT_BINDINGS_CLOCK_R8A7790_H__
-#define __DT_BINDINGS_CLOCK_R8A7790_H__
-
-/* CPG */
-#define R8A7790_CLK_MAIN 0
-#define R8A7790_CLK_PLL0 1
-#define R8A7790_CLK_PLL1 2
-#define R8A7790_CLK_PLL3 3
-#define R8A7790_CLK_LB 4
-#define R8A7790_CLK_QSPI 5
-#define R8A7790_CLK_SDH 6
-#define R8A7790_CLK_SD0 7
-#define R8A7790_CLK_SD1 8
-#define R8A7790_CLK_Z 9
-#define R8A7790_CLK_RCAN 10
-#define R8A7790_CLK_ADSP 11
-
-/* MSTP0 */
-#define R8A7790_CLK_MSIOF0 0
-
-/* MSTP1 */
-#define R8A7790_CLK_VCP1 0
-#define R8A7790_CLK_VCP0 1
-#define R8A7790_CLK_VPC1 2
-#define R8A7790_CLK_VPC0 3
-#define R8A7790_CLK_JPU 6
-#define R8A7790_CLK_SSP1 9
-#define R8A7790_CLK_TMU1 11
-#define R8A7790_CLK_3DG 12
-#define R8A7790_CLK_2DDMAC 15
-#define R8A7790_CLK_FDP1_2 17
-#define R8A7790_CLK_FDP1_1 18
-#define R8A7790_CLK_FDP1_0 19
-#define R8A7790_CLK_TMU3 21
-#define R8A7790_CLK_TMU2 22
-#define R8A7790_CLK_CMT0 24
-#define R8A7790_CLK_TMU0 25
-#define R8A7790_CLK_VSP1_DU1 27
-#define R8A7790_CLK_VSP1_DU0 28
-#define R8A7790_CLK_VSP1_R 30
-#define R8A7790_CLK_VSP1_S 31
-
-/* MSTP2 */
-#define R8A7790_CLK_SCIFA2 2
-#define R8A7790_CLK_SCIFA1 3
-#define R8A7790_CLK_SCIFA0 4
-#define R8A7790_CLK_MSIOF2 5
-#define R8A7790_CLK_SCIFB0 6
-#define R8A7790_CLK_SCIFB1 7
-#define R8A7790_CLK_MSIOF1 8
-#define R8A7790_CLK_MSIOF3 15
-#define R8A7790_CLK_SCIFB2 16
-#define R8A7790_CLK_SYS_DMAC1 18
-#define R8A7790_CLK_SYS_DMAC0 19
-
-/* MSTP3 */
-#define R8A7790_CLK_IIC2 0
-#define R8A7790_CLK_TPU0 4
-#define R8A7790_CLK_MMCIF1 5
-#define R8A7790_CLK_SCIF2 10
-#define R8A7790_CLK_SDHI3 11
-#define R8A7790_CLK_SDHI2 12
-#define R8A7790_CLK_SDHI1 13
-#define R8A7790_CLK_SDHI0 14
-#define R8A7790_CLK_MMCIF0 15
-#define R8A7790_CLK_IIC0 18
-#define R8A7790_CLK_PCIEC 19
-#define R8A7790_CLK_IIC1 23
-#define R8A7790_CLK_SSUSB 28
-#define R8A7790_CLK_CMT1 29
-#define R8A7790_CLK_USBDMAC0 30
-#define R8A7790_CLK_USBDMAC1 31
-
-/* MSTP4 */
-#define R8A7790_CLK_IRQC 7
-#define R8A7790_CLK_INTC_SYS 8
-
-/* MSTP5 */
-#define R8A7790_CLK_AUDIO_DMAC1 1
-#define R8A7790_CLK_AUDIO_DMAC0 2
-#define R8A7790_CLK_ADSP_MOD 6
-#define R8A7790_CLK_THERMAL 22
-#define R8A7790_CLK_PWM 23
-
-/* MSTP7 */
-#define R8A7790_CLK_EHCI 3
-#define R8A7790_CLK_HSUSB 4
-#define R8A7790_CLK_HSCIF1 16
-#define R8A7790_CLK_HSCIF0 17
-#define R8A7790_CLK_SCIF1 20
-#define R8A7790_CLK_SCIF0 21
-#define R8A7790_CLK_DU2 22
-#define R8A7790_CLK_DU1 23
-#define R8A7790_CLK_DU0 24
-#define R8A7790_CLK_LVDS1 25
-#define R8A7790_CLK_LVDS0 26
-
-/* MSTP8 */
-#define R8A7790_CLK_MLB 2
-#define R8A7790_CLK_VIN3 8
-#define R8A7790_CLK_VIN2 9
-#define R8A7790_CLK_VIN1 10
-#define R8A7790_CLK_VIN0 11
-#define R8A7790_CLK_ETHERAVB 12
-#define R8A7790_CLK_ETHER 13
-#define R8A7790_CLK_SATA1 14
-#define R8A7790_CLK_SATA0 15
-
-/* MSTP9 */
-#define R8A7790_CLK_GPIO5 7
-#define R8A7790_CLK_GPIO4 8
-#define R8A7790_CLK_GPIO3 9
-#define R8A7790_CLK_GPIO2 10
-#define R8A7790_CLK_GPIO1 11
-#define R8A7790_CLK_GPIO0 12
-#define R8A7790_CLK_RCAN1 15
-#define R8A7790_CLK_RCAN0 16
-#define R8A7790_CLK_QSPI_MOD 17
-#define R8A7790_CLK_IICDVFS 26
-#define R8A7790_CLK_I2C3 28
-#define R8A7790_CLK_I2C2 29
-#define R8A7790_CLK_I2C1 30
-#define R8A7790_CLK_I2C0 31
-
-/* MSTP10 */
-#define R8A7790_CLK_SSI_ALL 5
-#define R8A7790_CLK_SSI9 6
-#define R8A7790_CLK_SSI8 7
-#define R8A7790_CLK_SSI7 8
-#define R8A7790_CLK_SSI6 9
-#define R8A7790_CLK_SSI5 10
-#define R8A7790_CLK_SSI4 11
-#define R8A7790_CLK_SSI3 12
-#define R8A7790_CLK_SSI2 13
-#define R8A7790_CLK_SSI1 14
-#define R8A7790_CLK_SSI0 15
-#define R8A7790_CLK_SCU_ALL 17
-#define R8A7790_CLK_SCU_DVC1 18
-#define R8A7790_CLK_SCU_DVC0 19
-#define R8A7790_CLK_SCU_CTU1_MIX1 20
-#define R8A7790_CLK_SCU_CTU0_MIX0 21
-#define R8A7790_CLK_SCU_SRC9 22
-#define R8A7790_CLK_SCU_SRC8 23
-#define R8A7790_CLK_SCU_SRC7 24
-#define R8A7790_CLK_SCU_SRC6 25
-#define R8A7790_CLK_SCU_SRC5 26
-#define R8A7790_CLK_SCU_SRC4 27
-#define R8A7790_CLK_SCU_SRC3 28
-#define R8A7790_CLK_SCU_SRC2 29
-#define R8A7790_CLK_SCU_SRC1 30
-#define R8A7790_CLK_SCU_SRC0 31
-
-#endif /* __DT_BINDINGS_CLOCK_R8A7790_H__ */
diff --git a/include/dt-bindings/clock/r8a7790-cpg-mssr.h b/include/dt-bindings/clock/r8a7790-cpg-mssr.h
deleted file mode 100644
index c5955b5..0000000
--- a/include/dt-bindings/clock/r8a7790-cpg-mssr.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+
- *
- * Copyright (C) 2015 Renesas Electronics Corp.
- */
-
-#ifndef __DT_BINDINGS_CLOCK_R8A7790_CPG_MSSR_H__
-#define __DT_BINDINGS_CLOCK_R8A7790_CPG_MSSR_H__
-
-#include <dt-bindings/clock/renesas-cpg-mssr.h>
-
-/* r8a7790 CPG Core Clocks */
-#define R8A7790_CLK_Z 0
-#define R8A7790_CLK_Z2 1
-#define R8A7790_CLK_ZG 2
-#define R8A7790_CLK_ZTR 3
-#define R8A7790_CLK_ZTRD2 4
-#define R8A7790_CLK_ZT 5
-#define R8A7790_CLK_ZX 6
-#define R8A7790_CLK_ZS 7
-#define R8A7790_CLK_HP 8
-#define R8A7790_CLK_I 9
-#define R8A7790_CLK_B 10
-#define R8A7790_CLK_LB 11
-#define R8A7790_CLK_P 12
-#define R8A7790_CLK_CL 13
-#define R8A7790_CLK_M2 14
-#define R8A7790_CLK_ADSP 15
-#define R8A7790_CLK_IMP 16
-#define R8A7790_CLK_ZB3 17
-#define R8A7790_CLK_ZB3D2 18
-#define R8A7790_CLK_DDR 19
-#define R8A7790_CLK_SDH 20
-#define R8A7790_CLK_SD0 21
-#define R8A7790_CLK_SD1 22
-#define R8A7790_CLK_SD2 23
-#define R8A7790_CLK_SD3 24
-#define R8A7790_CLK_MMC0 25
-#define R8A7790_CLK_MMC1 26
-#define R8A7790_CLK_MP 27
-#define R8A7790_CLK_SSP 28
-#define R8A7790_CLK_SSPRS 29
-#define R8A7790_CLK_QSPI 30
-#define R8A7790_CLK_CP 31
-#define R8A7790_CLK_RCAN 32
-#define R8A7790_CLK_R 33
-#define R8A7790_CLK_OSC 34
-
-#endif /* __DT_BINDINGS_CLOCK_R8A7790_CPG_MSSR_H__ */
diff --git a/include/dt-bindings/clock/r8a7791-clock.h b/include/dt-bindings/clock/r8a7791-clock.h
deleted file mode 100644
index ef69213..0000000
--- a/include/dt-bindings/clock/r8a7791-clock.h
+++ /dev/null
@@ -1,165 +0,0 @@
-/*
- * Copyright 2013 Ideas On Board SPRL
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#ifndef __DT_BINDINGS_CLOCK_R8A7791_H__
-#define __DT_BINDINGS_CLOCK_R8A7791_H__
-
-/* CPG */
-#define R8A7791_CLK_MAIN 0
-#define R8A7791_CLK_PLL0 1
-#define R8A7791_CLK_PLL1 2
-#define R8A7791_CLK_PLL3 3
-#define R8A7791_CLK_LB 4
-#define R8A7791_CLK_QSPI 5
-#define R8A7791_CLK_SDH 6
-#define R8A7791_CLK_SD0 7
-#define R8A7791_CLK_Z 8
-#define R8A7791_CLK_RCAN 9
-#define R8A7791_CLK_ADSP 10
-
-/* MSTP0 */
-#define R8A7791_CLK_MSIOF0 0
-
-/* MSTP1 */
-#define R8A7791_CLK_VCP0 1
-#define R8A7791_CLK_VPC0 3
-#define R8A7791_CLK_JPU 6
-#define R8A7791_CLK_SSP1 9
-#define R8A7791_CLK_TMU1 11
-#define R8A7791_CLK_3DG 12
-#define R8A7791_CLK_2DDMAC 15
-#define R8A7791_CLK_FDP1_1 18
-#define R8A7791_CLK_FDP1_0 19
-#define R8A7791_CLK_TMU3 21
-#define R8A7791_CLK_TMU2 22
-#define R8A7791_CLK_CMT0 24
-#define R8A7791_CLK_TMU0 25
-#define R8A7791_CLK_VSP1_DU1 27
-#define R8A7791_CLK_VSP1_DU0 28
-#define R8A7791_CLK_VSP1_S 31
-
-/* MSTP2 */
-#define R8A7791_CLK_SCIFA2 2
-#define R8A7791_CLK_SCIFA1 3
-#define R8A7791_CLK_SCIFA0 4
-#define R8A7791_CLK_MSIOF2 5
-#define R8A7791_CLK_SCIFB0 6
-#define R8A7791_CLK_SCIFB1 7
-#define R8A7791_CLK_MSIOF1 8
-#define R8A7791_CLK_SCIFB2 16
-#define R8A7791_CLK_SYS_DMAC1 18
-#define R8A7791_CLK_SYS_DMAC0 19
-
-/* MSTP3 */
-#define R8A7791_CLK_TPU0 4
-#define R8A7791_CLK_SDHI2 11
-#define R8A7791_CLK_SDHI1 12
-#define R8A7791_CLK_SDHI0 14
-#define R8A7791_CLK_MMCIF0 15
-#define R8A7791_CLK_IIC0 18
-#define R8A7791_CLK_PCIEC 19
-#define R8A7791_CLK_IIC1 23
-#define R8A7791_CLK_SSUSB 28
-#define R8A7791_CLK_CMT1 29
-#define R8A7791_CLK_USBDMAC0 30
-#define R8A7791_CLK_USBDMAC1 31
-
-/* MSTP4 */
-#define R8A7791_CLK_IRQC 7
-#define R8A7791_CLK_INTC_SYS 8
-
-/* MSTP5 */
-#define R8A7791_CLK_AUDIO_DMAC1 1
-#define R8A7791_CLK_AUDIO_DMAC0 2
-#define R8A7791_CLK_ADSP_MOD 6
-#define R8A7791_CLK_THERMAL 22
-#define R8A7791_CLK_PWM 23
-
-/* MSTP7 */
-#define R8A7791_CLK_EHCI 3
-#define R8A7791_CLK_HSUSB 4
-#define R8A7791_CLK_HSCIF2 13
-#define R8A7791_CLK_SCIF5 14
-#define R8A7791_CLK_SCIF4 15
-#define R8A7791_CLK_HSCIF1 16
-#define R8A7791_CLK_HSCIF0 17
-#define R8A7791_CLK_SCIF3 18
-#define R8A7791_CLK_SCIF2 19
-#define R8A7791_CLK_SCIF1 20
-#define R8A7791_CLK_SCIF0 21
-#define R8A7791_CLK_DU1 23
-#define R8A7791_CLK_DU0 24
-#define R8A7791_CLK_LVDS0 26
-
-/* MSTP8 */
-#define R8A7791_CLK_IPMMU_SGX 0
-#define R8A7791_CLK_MLB 2
-#define R8A7791_CLK_VIN2 9
-#define R8A7791_CLK_VIN1 10
-#define R8A7791_CLK_VIN0 11
-#define R8A7791_CLK_ETHERAVB 12
-#define R8A7791_CLK_ETHER 13
-#define R8A7791_CLK_SATA1 14
-#define R8A7791_CLK_SATA0 15
-
-/* MSTP9 */
-#define R8A7791_CLK_GYROADC 1
-#define R8A7791_CLK_GPIO7 4
-#define R8A7791_CLK_GPIO6 5
-#define R8A7791_CLK_GPIO5 7
-#define R8A7791_CLK_GPIO4 8
-#define R8A7791_CLK_GPIO3 9
-#define R8A7791_CLK_GPIO2 10
-#define R8A7791_CLK_GPIO1 11
-#define R8A7791_CLK_GPIO0 12
-#define R8A7791_CLK_RCAN1 15
-#define R8A7791_CLK_RCAN0 16
-#define R8A7791_CLK_QSPI_MOD 17
-#define R8A7791_CLK_I2C5 25
-#define R8A7791_CLK_IICDVFS 26
-#define R8A7791_CLK_I2C4 27
-#define R8A7791_CLK_I2C3 28
-#define R8A7791_CLK_I2C2 29
-#define R8A7791_CLK_I2C1 30
-#define R8A7791_CLK_I2C0 31
-
-/* MSTP10 */
-#define R8A7791_CLK_SSI_ALL 5
-#define R8A7791_CLK_SSI9 6
-#define R8A7791_CLK_SSI8 7
-#define R8A7791_CLK_SSI7 8
-#define R8A7791_CLK_SSI6 9
-#define R8A7791_CLK_SSI5 10
-#define R8A7791_CLK_SSI4 11
-#define R8A7791_CLK_SSI3 12
-#define R8A7791_CLK_SSI2 13
-#define R8A7791_CLK_SSI1 14
-#define R8A7791_CLK_SSI0 15
-#define R8A7791_CLK_SCU_ALL 17
-#define R8A7791_CLK_SCU_DVC1 18
-#define R8A7791_CLK_SCU_DVC0 19
-#define R8A7791_CLK_SCU_CTU1_MIX1 20
-#define R8A7791_CLK_SCU_CTU0_MIX0 21
-#define R8A7791_CLK_SCU_SRC9 22
-#define R8A7791_CLK_SCU_SRC8 23
-#define R8A7791_CLK_SCU_SRC7 24
-#define R8A7791_CLK_SCU_SRC6 25
-#define R8A7791_CLK_SCU_SRC5 26
-#define R8A7791_CLK_SCU_SRC4 27
-#define R8A7791_CLK_SCU_SRC3 28
-#define R8A7791_CLK_SCU_SRC2 29
-#define R8A7791_CLK_SCU_SRC1 30
-#define R8A7791_CLK_SCU_SRC0 31
-
-/* MSTP11 */
-#define R8A7791_CLK_SCIFA3 6
-#define R8A7791_CLK_SCIFA4 7
-#define R8A7791_CLK_SCIFA5 8
-
-#endif /* __DT_BINDINGS_CLOCK_R8A7791_H__ */
diff --git a/include/dt-bindings/clock/r8a7791-cpg-mssr.h b/include/dt-bindings/clock/r8a7791-cpg-mssr.h
deleted file mode 100644
index aadd06c..0000000
--- a/include/dt-bindings/clock/r8a7791-cpg-mssr.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+
- *
- * Copyright (C) 2015 Renesas Electronics Corp.
- */
-
-#ifndef __DT_BINDINGS_CLOCK_R8A7791_CPG_MSSR_H__
-#define __DT_BINDINGS_CLOCK_R8A7791_CPG_MSSR_H__
-
-#include <dt-bindings/clock/renesas-cpg-mssr.h>
-
-/* r8a7791 CPG Core Clocks */
-#define R8A7791_CLK_Z 0
-#define R8A7791_CLK_ZG 1
-#define R8A7791_CLK_ZTR 2
-#define R8A7791_CLK_ZTRD2 3
-#define R8A7791_CLK_ZT 4
-#define R8A7791_CLK_ZX 5
-#define R8A7791_CLK_ZS 6
-#define R8A7791_CLK_HP 7
-#define R8A7791_CLK_I 8
-#define R8A7791_CLK_B 9
-#define R8A7791_CLK_LB 10
-#define R8A7791_CLK_P 11
-#define R8A7791_CLK_CL 12
-#define R8A7791_CLK_M2 13
-#define R8A7791_CLK_ADSP 14
-#define R8A7791_CLK_ZB3 15
-#define R8A7791_CLK_ZB3D2 16
-#define R8A7791_CLK_DDR 17
-#define R8A7791_CLK_SDH 18
-#define R8A7791_CLK_SD0 19
-#define R8A7791_CLK_SD2 20
-#define R8A7791_CLK_SD3 21
-#define R8A7791_CLK_MMC0 22
-#define R8A7791_CLK_MP 23
-#define R8A7791_CLK_SSP 24
-#define R8A7791_CLK_SSPRS 25
-#define R8A7791_CLK_QSPI 26
-#define R8A7791_CLK_CP 27
-#define R8A7791_CLK_RCAN 28
-#define R8A7791_CLK_R 29
-#define R8A7791_CLK_OSC 30
-
-#endif /* __DT_BINDINGS_CLOCK_R8A7791_CPG_MSSR_H__ */
diff --git a/include/dt-bindings/clock/r8a7792-clock.h b/include/dt-bindings/clock/r8a7792-clock.h
deleted file mode 100644
index 5be90bc..0000000
--- a/include/dt-bindings/clock/r8a7792-clock.h
+++ /dev/null
@@ -1,102 +0,0 @@
-/*
- * Copyright (C) 2016 Cogent Embedded, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#ifndef __DT_BINDINGS_CLOCK_R8A7792_H__
-#define __DT_BINDINGS_CLOCK_R8A7792_H__
-
-/* CPG */
-#define R8A7792_CLK_MAIN 0
-#define R8A7792_CLK_PLL0 1
-#define R8A7792_CLK_PLL1 2
-#define R8A7792_CLK_PLL3 3
-#define R8A7792_CLK_LB 4
-#define R8A7792_CLK_QSPI 5
-
-/* MSTP0 */
-#define R8A7792_CLK_MSIOF0 0
-
-/* MSTP1 */
-#define R8A7792_CLK_JPU 6
-#define R8A7792_CLK_TMU1 11
-#define R8A7792_CLK_TMU3 21
-#define R8A7792_CLK_TMU2 22
-#define R8A7792_CLK_CMT0 24
-#define R8A7792_CLK_TMU0 25
-#define R8A7792_CLK_VSP1DU1 27
-#define R8A7792_CLK_VSP1DU0 28
-#define R8A7792_CLK_VSP1_SY 31
-
-/* MSTP2 */
-#define R8A7792_CLK_MSIOF1 8
-#define R8A7792_CLK_SYS_DMAC1 18
-#define R8A7792_CLK_SYS_DMAC0 19
-
-/* MSTP3 */
-#define R8A7792_CLK_TPU0 4
-#define R8A7792_CLK_SDHI0 14
-#define R8A7792_CLK_CMT1 29
-
-/* MSTP4 */
-#define R8A7792_CLK_IRQC 7
-#define R8A7792_CLK_INTC_SYS 8
-
-/* MSTP5 */
-#define R8A7792_CLK_AUDIO_DMAC0 2
-#define R8A7792_CLK_THERMAL 22
-#define R8A7792_CLK_PWM 23
-
-/* MSTP7 */
-#define R8A7792_CLK_HSCIF1 16
-#define R8A7792_CLK_HSCIF0 17
-#define R8A7792_CLK_SCIF3 18
-#define R8A7792_CLK_SCIF2 19
-#define R8A7792_CLK_SCIF1 20
-#define R8A7792_CLK_SCIF0 21
-#define R8A7792_CLK_DU1 23
-#define R8A7792_CLK_DU0 24
-
-/* MSTP8 */
-#define R8A7792_CLK_VIN5 4
-#define R8A7792_CLK_VIN4 5
-#define R8A7792_CLK_VIN3 8
-#define R8A7792_CLK_VIN2 9
-#define R8A7792_CLK_VIN1 10
-#define R8A7792_CLK_VIN0 11
-#define R8A7792_CLK_ETHERAVB 12
-
-/* MSTP9 */
-#define R8A7792_CLK_GPIO7 4
-#define R8A7792_CLK_GPIO6 5
-#define R8A7792_CLK_GPIO5 7
-#define R8A7792_CLK_GPIO4 8
-#define R8A7792_CLK_GPIO3 9
-#define R8A7792_CLK_GPIO2 10
-#define R8A7792_CLK_GPIO1 11
-#define R8A7792_CLK_GPIO0 12
-#define R8A7792_CLK_GPIO11 13
-#define R8A7792_CLK_GPIO10 14
-#define R8A7792_CLK_CAN1 15
-#define R8A7792_CLK_CAN0 16
-#define R8A7792_CLK_QSPI_MOD 17
-#define R8A7792_CLK_GPIO9 19
-#define R8A7792_CLK_GPIO8 21
-#define R8A7792_CLK_I2C5 25
-#define R8A7792_CLK_IICDVFS 26
-#define R8A7792_CLK_I2C4 27
-#define R8A7792_CLK_I2C3 28
-#define R8A7792_CLK_I2C2 29
-#define R8A7792_CLK_I2C1 30
-#define R8A7792_CLK_I2C0 31
-
-/* MSTP10 */
-#define R8A7792_CLK_SSI_ALL 5
-#define R8A7792_CLK_SSI4 11
-#define R8A7792_CLK_SSI3 12
-
-#endif /* __DT_BINDINGS_CLOCK_R8A7792_H__ */
diff --git a/include/dt-bindings/clock/r8a7792-cpg-mssr.h b/include/dt-bindings/clock/r8a7792-cpg-mssr.h
deleted file mode 100644
index 829c44d..0000000
--- a/include/dt-bindings/clock/r8a7792-cpg-mssr.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+
- *
- * Copyright (C) 2015 Renesas Electronics Corp.
- */
-
-#ifndef __DT_BINDINGS_CLOCK_R8A7792_CPG_MSSR_H__
-#define __DT_BINDINGS_CLOCK_R8A7792_CPG_MSSR_H__
-
-#include <dt-bindings/clock/renesas-cpg-mssr.h>
-
-/* r8a7792 CPG Core Clocks */
-#define R8A7792_CLK_Z 0
-#define R8A7792_CLK_ZG 1
-#define R8A7792_CLK_ZTR 2
-#define R8A7792_CLK_ZTRD2 3
-#define R8A7792_CLK_ZT 4
-#define R8A7792_CLK_ZX 5
-#define R8A7792_CLK_ZS 6
-#define R8A7792_CLK_HP 7
-#define R8A7792_CLK_I 8
-#define R8A7792_CLK_B 9
-#define R8A7792_CLK_LB 10
-#define R8A7792_CLK_P 11
-#define R8A7792_CLK_CL 12
-#define R8A7792_CLK_M2 13
-#define R8A7792_CLK_IMP 14
-#define R8A7792_CLK_ZB3 15
-#define R8A7792_CLK_ZB3D2 16
-#define R8A7792_CLK_DDR 17
-#define R8A7792_CLK_SD 18
-#define R8A7792_CLK_MP 19
-#define R8A7792_CLK_QSPI 20
-#define R8A7792_CLK_CP 21
-#define R8A7792_CLK_CPEX 22
-#define R8A7792_CLK_RCAN 23
-#define R8A7792_CLK_R 24
-#define R8A7792_CLK_OSC 25
-
-#endif /* __DT_BINDINGS_CLOCK_R8A7792_CPG_MSSR_H__ */
diff --git a/include/dt-bindings/clock/r8a7793-clock.h b/include/dt-bindings/clock/r8a7793-clock.h
deleted file mode 100644
index 49c66d8..0000000
--- a/include/dt-bindings/clock/r8a7793-clock.h
+++ /dev/null
@@ -1,159 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0
- *
- * r8a7793 clock definition
- *
- * Copyright (C) 2014 Renesas Electronics Corporation
- */
-
-#ifndef __DT_BINDINGS_CLOCK_R8A7793_H__
-#define __DT_BINDINGS_CLOCK_R8A7793_H__
-
-/* CPG */
-#define R8A7793_CLK_MAIN 0
-#define R8A7793_CLK_PLL0 1
-#define R8A7793_CLK_PLL1 2
-#define R8A7793_CLK_PLL3 3
-#define R8A7793_CLK_LB 4
-#define R8A7793_CLK_QSPI 5
-#define R8A7793_CLK_SDH 6
-#define R8A7793_CLK_SD0 7
-#define R8A7793_CLK_Z 8
-#define R8A7793_CLK_RCAN 9
-#define R8A7793_CLK_ADSP 10
-
-/* MSTP0 */
-#define R8A7793_CLK_MSIOF0 0
-
-/* MSTP1 */
-#define R8A7793_CLK_VCP0 1
-#define R8A7793_CLK_VPC0 3
-#define R8A7793_CLK_SSP1 9
-#define R8A7793_CLK_TMU1 11
-#define R8A7793_CLK_3DG 12
-#define R8A7793_CLK_2DDMAC 15
-#define R8A7793_CLK_FDP1_1 18
-#define R8A7793_CLK_FDP1_0 19
-#define R8A7793_CLK_TMU3 21
-#define R8A7793_CLK_TMU2 22
-#define R8A7793_CLK_CMT0 24
-#define R8A7793_CLK_TMU0 25
-#define R8A7793_CLK_VSP1_DU1 27
-#define R8A7793_CLK_VSP1_DU0 28
-#define R8A7793_CLK_VSP1_S 31
-
-/* MSTP2 */
-#define R8A7793_CLK_SCIFA2 2
-#define R8A7793_CLK_SCIFA1 3
-#define R8A7793_CLK_SCIFA0 4
-#define R8A7793_CLK_MSIOF2 5
-#define R8A7793_CLK_SCIFB0 6
-#define R8A7793_CLK_SCIFB1 7
-#define R8A7793_CLK_MSIOF1 8
-#define R8A7793_CLK_SCIFB2 16
-#define R8A7793_CLK_SYS_DMAC1 18
-#define R8A7793_CLK_SYS_DMAC0 19
-
-/* MSTP3 */
-#define R8A7793_CLK_TPU0 4
-#define R8A7793_CLK_SDHI2 11
-#define R8A7793_CLK_SDHI1 12
-#define R8A7793_CLK_SDHI0 14
-#define R8A7793_CLK_MMCIF0 15
-#define R8A7793_CLK_IIC0 18
-#define R8A7793_CLK_PCIEC 19
-#define R8A7793_CLK_IIC1 23
-#define R8A7793_CLK_SSUSB 28
-#define R8A7793_CLK_CMT1 29
-#define R8A7793_CLK_USBDMAC0 30
-#define R8A7793_CLK_USBDMAC1 31
-
-/* MSTP4 */
-#define R8A7793_CLK_IRQC 7
-#define R8A7793_CLK_INTC_SYS 8
-
-/* MSTP5 */
-#define R8A7793_CLK_AUDIO_DMAC1 1
-#define R8A7793_CLK_AUDIO_DMAC0 2
-#define R8A7793_CLK_ADSP_MOD 6
-#define R8A7793_CLK_THERMAL 22
-#define R8A7793_CLK_PWM 23
-
-/* MSTP7 */
-#define R8A7793_CLK_EHCI 3
-#define R8A7793_CLK_HSUSB 4
-#define R8A7793_CLK_HSCIF2 13
-#define R8A7793_CLK_SCIF5 14
-#define R8A7793_CLK_SCIF4 15
-#define R8A7793_CLK_HSCIF1 16
-#define R8A7793_CLK_HSCIF0 17
-#define R8A7793_CLK_SCIF3 18
-#define R8A7793_CLK_SCIF2 19
-#define R8A7793_CLK_SCIF1 20
-#define R8A7793_CLK_SCIF0 21
-#define R8A7793_CLK_DU1 23
-#define R8A7793_CLK_DU0 24
-#define R8A7793_CLK_LVDS0 26
-
-/* MSTP8 */
-#define R8A7793_CLK_IPMMU_SGX 0
-#define R8A7793_CLK_VIN2 9
-#define R8A7793_CLK_VIN1 10
-#define R8A7793_CLK_VIN0 11
-#define R8A7793_CLK_ETHER 13
-#define R8A7793_CLK_SATA1 14
-#define R8A7793_CLK_SATA0 15
-
-/* MSTP9 */
-#define R8A7793_CLK_GPIO7 4
-#define R8A7793_CLK_GPIO6 5
-#define R8A7793_CLK_GPIO5 7
-#define R8A7793_CLK_GPIO4 8
-#define R8A7793_CLK_GPIO3 9
-#define R8A7793_CLK_GPIO2 10
-#define R8A7793_CLK_GPIO1 11
-#define R8A7793_CLK_GPIO0 12
-#define R8A7793_CLK_RCAN1 15
-#define R8A7793_CLK_RCAN0 16
-#define R8A7793_CLK_QSPI_MOD 17
-#define R8A7793_CLK_I2C5 25
-#define R8A7793_CLK_IICDVFS 26
-#define R8A7793_CLK_I2C4 27
-#define R8A7793_CLK_I2C3 28
-#define R8A7793_CLK_I2C2 29
-#define R8A7793_CLK_I2C1 30
-#define R8A7793_CLK_I2C0 31
-
-/* MSTP10 */
-#define R8A7793_CLK_SSI_ALL 5
-#define R8A7793_CLK_SSI9 6
-#define R8A7793_CLK_SSI8 7
-#define R8A7793_CLK_SSI7 8
-#define R8A7793_CLK_SSI6 9
-#define R8A7793_CLK_SSI5 10
-#define R8A7793_CLK_SSI4 11
-#define R8A7793_CLK_SSI3 12
-#define R8A7793_CLK_SSI2 13
-#define R8A7793_CLK_SSI1 14
-#define R8A7793_CLK_SSI0 15
-#define R8A7793_CLK_SCU_ALL 17
-#define R8A7793_CLK_SCU_DVC1 18
-#define R8A7793_CLK_SCU_DVC0 19
-#define R8A7793_CLK_SCU_CTU1_MIX1 20
-#define R8A7793_CLK_SCU_CTU0_MIX0 21
-#define R8A7793_CLK_SCU_SRC9 22
-#define R8A7793_CLK_SCU_SRC8 23
-#define R8A7793_CLK_SCU_SRC7 24
-#define R8A7793_CLK_SCU_SRC6 25
-#define R8A7793_CLK_SCU_SRC5 26
-#define R8A7793_CLK_SCU_SRC4 27
-#define R8A7793_CLK_SCU_SRC3 28
-#define R8A7793_CLK_SCU_SRC2 29
-#define R8A7793_CLK_SCU_SRC1 30
-#define R8A7793_CLK_SCU_SRC0 31
-
-/* MSTP11 */
-#define R8A7793_CLK_SCIFA3 6
-#define R8A7793_CLK_SCIFA4 7
-#define R8A7793_CLK_SCIFA5 8
-
-#endif /* __DT_BINDINGS_CLOCK_R8A7793_H__ */
diff --git a/include/dt-bindings/clock/r8a7793-cpg-mssr.h b/include/dt-bindings/clock/r8a7793-cpg-mssr.h
deleted file mode 100644
index d1ff646..0000000
--- a/include/dt-bindings/clock/r8a7793-cpg-mssr.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+
- *
- * Copyright (C) 2015 Renesas Electronics Corp.
- */
-
-#ifndef __DT_BINDINGS_CLOCK_R8A7793_CPG_MSSR_H__
-#define __DT_BINDINGS_CLOCK_R8A7793_CPG_MSSR_H__
-
-#include <dt-bindings/clock/renesas-cpg-mssr.h>
-
-/* r8a7793 CPG Core Clocks */
-#define R8A7793_CLK_Z 0
-#define R8A7793_CLK_ZG 1
-#define R8A7793_CLK_ZTR 2
-#define R8A7793_CLK_ZTRD2 3
-#define R8A7793_CLK_ZT 4
-#define R8A7793_CLK_ZX 5
-#define R8A7793_CLK_ZS 6
-#define R8A7793_CLK_HP 7
-#define R8A7793_CLK_I 8
-#define R8A7793_CLK_B 9
-#define R8A7793_CLK_LB 10
-#define R8A7793_CLK_P 11
-#define R8A7793_CLK_CL 12
-#define R8A7793_CLK_M2 13
-#define R8A7793_CLK_ADSP 14
-#define R8A7793_CLK_ZB3 15
-#define R8A7793_CLK_ZB3D2 16
-#define R8A7793_CLK_DDR 17
-#define R8A7793_CLK_SDH 18
-#define R8A7793_CLK_SD0 19
-#define R8A7793_CLK_SD2 20
-#define R8A7793_CLK_SD3 21
-#define R8A7793_CLK_MMC0 22
-#define R8A7793_CLK_MP 23
-#define R8A7793_CLK_SSP 24
-#define R8A7793_CLK_SSPRS 25
-#define R8A7793_CLK_QSPI 26
-#define R8A7793_CLK_CP 27
-#define R8A7793_CLK_RCAN 28
-#define R8A7793_CLK_R 29
-#define R8A7793_CLK_OSC 30
-
-#endif /* __DT_BINDINGS_CLOCK_R8A7793_CPG_MSSR_H__ */
diff --git a/include/dt-bindings/clock/r8a7794-clock.h b/include/dt-bindings/clock/r8a7794-clock.h
deleted file mode 100644
index 649f005..0000000
--- a/include/dt-bindings/clock/r8a7794-clock.h
+++ /dev/null
@@ -1,137 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+
- *
- * Copyright (C) 2014 Renesas Electronics Corporation
- * Copyright 2013 Ideas On Board SPRL
- */
-
-#ifndef __DT_BINDINGS_CLOCK_R8A7794_H__
-#define __DT_BINDINGS_CLOCK_R8A7794_H__
-
-/* CPG */
-#define R8A7794_CLK_MAIN 0
-#define R8A7794_CLK_PLL0 1
-#define R8A7794_CLK_PLL1 2
-#define R8A7794_CLK_PLL3 3
-#define R8A7794_CLK_LB 4
-#define R8A7794_CLK_QSPI 5
-#define R8A7794_CLK_SDH 6
-#define R8A7794_CLK_SD0 7
-#define R8A7794_CLK_RCAN 8
-
-/* MSTP0 */
-#define R8A7794_CLK_MSIOF0 0
-
-/* MSTP1 */
-#define R8A7794_CLK_VCP0 1
-#define R8A7794_CLK_VPC0 3
-#define R8A7794_CLK_TMU1 11
-#define R8A7794_CLK_3DG 12
-#define R8A7794_CLK_2DDMAC 15
-#define R8A7794_CLK_FDP1_0 19
-#define R8A7794_CLK_TMU3 21
-#define R8A7794_CLK_TMU2 22
-#define R8A7794_CLK_CMT0 24
-#define R8A7794_CLK_TMU0 25
-#define R8A7794_CLK_VSP1_DU0 28
-#define R8A7794_CLK_VSP1_S 31
-
-/* MSTP2 */
-#define R8A7794_CLK_SCIFA2 2
-#define R8A7794_CLK_SCIFA1 3
-#define R8A7794_CLK_SCIFA0 4
-#define R8A7794_CLK_MSIOF2 5
-#define R8A7794_CLK_SCIFB0 6
-#define R8A7794_CLK_SCIFB1 7
-#define R8A7794_CLK_MSIOF1 8
-#define R8A7794_CLK_SCIFB2 16
-#define R8A7794_CLK_SYS_DMAC1 18
-#define R8A7794_CLK_SYS_DMAC0 19
-
-/* MSTP3 */
-#define R8A7794_CLK_SDHI2 11
-#define R8A7794_CLK_SDHI1 12
-#define R8A7794_CLK_SDHI0 14
-#define R8A7794_CLK_MMCIF0 15
-#define R8A7794_CLK_IIC0 18
-#define R8A7794_CLK_IIC1 23
-#define R8A7794_CLK_CMT1 29
-#define R8A7794_CLK_USBDMAC0 30
-#define R8A7794_CLK_USBDMAC1 31
-
-/* MSTP4 */
-#define R8A7794_CLK_IRQC 7
-#define R8A7794_CLK_INTC_SYS 8
-
-/* MSTP5 */
-#define R8A7794_CLK_AUDIO_DMAC0 2
-#define R8A7794_CLK_PWM 23
-
-/* MSTP7 */
-#define R8A7794_CLK_EHCI 3
-#define R8A7794_CLK_HSUSB 4
-#define R8A7794_CLK_HSCIF2 13
-#define R8A7794_CLK_SCIF5 14
-#define R8A7794_CLK_SCIF4 15
-#define R8A7794_CLK_HSCIF1 16
-#define R8A7794_CLK_HSCIF0 17
-#define R8A7794_CLK_SCIF3 18
-#define R8A7794_CLK_SCIF2 19
-#define R8A7794_CLK_SCIF1 20
-#define R8A7794_CLK_SCIF0 21
-#define R8A7794_CLK_DU1 23
-#define R8A7794_CLK_DU0 24
-
-/* MSTP8 */
-#define R8A7794_CLK_VIN1 10
-#define R8A7794_CLK_VIN0 11
-#define R8A7794_CLK_ETHERAVB 12
-#define R8A7794_CLK_ETHER 13
-
-/* MSTP9 */
-#define R8A7794_CLK_GPIO6 5
-#define R8A7794_CLK_GPIO5 7
-#define R8A7794_CLK_GPIO4 8
-#define R8A7794_CLK_GPIO3 9
-#define R8A7794_CLK_GPIO2 10
-#define R8A7794_CLK_GPIO1 11
-#define R8A7794_CLK_GPIO0 12
-#define R8A7794_CLK_RCAN1 15
-#define R8A7794_CLK_RCAN0 16
-#define R8A7794_CLK_QSPI_MOD 17
-#define R8A7794_CLK_I2C5 25
-#define R8A7794_CLK_I2C4 27
-#define R8A7794_CLK_I2C3 28
-#define R8A7794_CLK_I2C2 29
-#define R8A7794_CLK_I2C1 30
-#define R8A7794_CLK_I2C0 31
-
-/* MSTP10 */
-#define R8A7794_CLK_SSI_ALL 5
-#define R8A7794_CLK_SSI9 6
-#define R8A7794_CLK_SSI8 7
-#define R8A7794_CLK_SSI7 8
-#define R8A7794_CLK_SSI6 9
-#define R8A7794_CLK_SSI5 10
-#define R8A7794_CLK_SSI4 11
-#define R8A7794_CLK_SSI3 12
-#define R8A7794_CLK_SSI2 13
-#define R8A7794_CLK_SSI1 14
-#define R8A7794_CLK_SSI0 15
-#define R8A7794_CLK_SCU_ALL 17
-#define R8A7794_CLK_SCU_DVC1 18
-#define R8A7794_CLK_SCU_DVC0 19
-#define R8A7794_CLK_SCU_CTU1_MIX1 20
-#define R8A7794_CLK_SCU_CTU0_MIX0 21
-#define R8A7794_CLK_SCU_SRC6 25
-#define R8A7794_CLK_SCU_SRC5 26
-#define R8A7794_CLK_SCU_SRC4 27
-#define R8A7794_CLK_SCU_SRC3 28
-#define R8A7794_CLK_SCU_SRC2 29
-#define R8A7794_CLK_SCU_SRC1 30
-
-/* MSTP11 */
-#define R8A7794_CLK_SCIFA3 6
-#define R8A7794_CLK_SCIFA4 7
-#define R8A7794_CLK_SCIFA5 8
-
-#endif /* __DT_BINDINGS_CLOCK_R8A7794_H__ */
diff --git a/include/dt-bindings/clock/r8a7794-cpg-mssr.h b/include/dt-bindings/clock/r8a7794-cpg-mssr.h
deleted file mode 100644
index 6314e23..0000000
--- a/include/dt-bindings/clock/r8a7794-cpg-mssr.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+
- *
- * Copyright (C) 2015 Renesas Electronics Corp.
- */
-
-#ifndef __DT_BINDINGS_CLOCK_R8A7794_CPG_MSSR_H__
-#define __DT_BINDINGS_CLOCK_R8A7794_CPG_MSSR_H__
-
-#include <dt-bindings/clock/renesas-cpg-mssr.h>
-
-/* r8a7794 CPG Core Clocks */
-#define R8A7794_CLK_Z2 0
-#define R8A7794_CLK_ZG 1
-#define R8A7794_CLK_ZTR 2
-#define R8A7794_CLK_ZTRD2 3
-#define R8A7794_CLK_ZT 4
-#define R8A7794_CLK_ZX 5
-#define R8A7794_CLK_ZS 6
-#define R8A7794_CLK_HP 7
-#define R8A7794_CLK_I 8
-#define R8A7794_CLK_B 9
-#define R8A7794_CLK_LB 10
-#define R8A7794_CLK_P 11
-#define R8A7794_CLK_CL 12
-#define R8A7794_CLK_CP 13
-#define R8A7794_CLK_M2 14
-#define R8A7794_CLK_ADSP 15
-#define R8A7794_CLK_ZB3 16
-#define R8A7794_CLK_ZB3D2 17
-#define R8A7794_CLK_DDR 18
-#define R8A7794_CLK_SDH 19
-#define R8A7794_CLK_SD0 20
-#define R8A7794_CLK_SD2 21
-#define R8A7794_CLK_SD3 22
-#define R8A7794_CLK_MMC0 23
-#define R8A7794_CLK_MP 24
-#define R8A7794_CLK_QSPI 25
-#define R8A7794_CLK_CPEX 26
-#define R8A7794_CLK_RCAN 27
-#define R8A7794_CLK_R 28
-#define R8A7794_CLK_OSC 29
-
-#endif /* __DT_BINDINGS_CLOCK_R8A7794_CPG_MSSR_H__ */
diff --git a/include/dt-bindings/clock/r8a7795-cpg-mssr.h b/include/dt-bindings/clock/r8a7795-cpg-mssr.h
deleted file mode 100644
index 92b3e2a..0000000
--- a/include/dt-bindings/clock/r8a7795-cpg-mssr.h
+++ /dev/null
@@ -1,66 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+
- *
- * Copyright (C) 2015 Renesas Electronics Corp.
- */
-#ifndef __DT_BINDINGS_CLOCK_R8A7795_CPG_MSSR_H__
-#define __DT_BINDINGS_CLOCK_R8A7795_CPG_MSSR_H__
-
-#include <dt-bindings/clock/renesas-cpg-mssr.h>
-
-/* r8a7795 CPG Core Clocks */
-#define R8A7795_CLK_Z 0
-#define R8A7795_CLK_Z2 1
-#define R8A7795_CLK_ZR 2
-#define R8A7795_CLK_ZG 3
-#define R8A7795_CLK_ZTR 4
-#define R8A7795_CLK_ZTRD2 5
-#define R8A7795_CLK_ZT 6
-#define R8A7795_CLK_ZX 7
-#define R8A7795_CLK_S0D1 8
-#define R8A7795_CLK_S0D4 9
-#define R8A7795_CLK_S1D1 10
-#define R8A7795_CLK_S1D2 11
-#define R8A7795_CLK_S1D4 12
-#define R8A7795_CLK_S2D1 13
-#define R8A7795_CLK_S2D2 14
-#define R8A7795_CLK_S2D4 15
-#define R8A7795_CLK_S3D1 16
-#define R8A7795_CLK_S3D2 17
-#define R8A7795_CLK_S3D4 18
-#define R8A7795_CLK_LB 19
-#define R8A7795_CLK_CL 20
-#define R8A7795_CLK_ZB3 21
-#define R8A7795_CLK_ZB3D2 22
-#define R8A7795_CLK_CR 23
-#define R8A7795_CLK_CRD2 24
-#define R8A7795_CLK_SD0H 25
-#define R8A7795_CLK_SD0 26
-#define R8A7795_CLK_SD1H 27
-#define R8A7795_CLK_SD1 28
-#define R8A7795_CLK_SD2H 29
-#define R8A7795_CLK_SD2 30
-#define R8A7795_CLK_SD3H 31
-#define R8A7795_CLK_SD3 32
-#define R8A7795_CLK_SSP2 33
-#define R8A7795_CLK_SSP1 34
-#define R8A7795_CLK_SSPRS 35
-#define R8A7795_CLK_RPC 36
-#define R8A7795_CLK_RPCD2 37
-#define R8A7795_CLK_MSO 38
-#define R8A7795_CLK_CANFD 39
-#define R8A7795_CLK_HDMI 40
-#define R8A7795_CLK_CSI0 41
-/* CLK_CSIREF was removed */
-#define R8A7795_CLK_CP 43
-#define R8A7795_CLK_CPEX 44
-#define R8A7795_CLK_R 45
-#define R8A7795_CLK_OSC 46
-
-/* r8a7795 ES2.0 CPG Core Clocks */
-#define R8A7795_CLK_S0D2 47
-#define R8A7795_CLK_S0D3 48
-#define R8A7795_CLK_S0D6 49
-#define R8A7795_CLK_S0D8 50
-#define R8A7795_CLK_S0D12 51
-
-#endif /* __DT_BINDINGS_CLOCK_R8A7795_CPG_MSSR_H__ */
diff --git a/include/dt-bindings/clock/r8a7796-cpg-mssr.h b/include/dt-bindings/clock/r8a7796-cpg-mssr.h
deleted file mode 100644
index c0957cf..0000000
--- a/include/dt-bindings/clock/r8a7796-cpg-mssr.h
+++ /dev/null
@@ -1,65 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+
- *
- * Copyright (C) 2016 Renesas Electronics Corp.
- */
-#ifndef __DT_BINDINGS_CLOCK_R8A7796_CPG_MSSR_H__
-#define __DT_BINDINGS_CLOCK_R8A7796_CPG_MSSR_H__
-
-#include <dt-bindings/clock/renesas-cpg-mssr.h>
-
-/* r8a7796 CPG Core Clocks */
-#define R8A7796_CLK_Z 0
-#define R8A7796_CLK_Z2 1
-#define R8A7796_CLK_ZR 2
-#define R8A7796_CLK_ZG 3
-#define R8A7796_CLK_ZTR 4
-#define R8A7796_CLK_ZTRD2 5
-#define R8A7796_CLK_ZT 6
-#define R8A7796_CLK_ZX 7
-#define R8A7796_CLK_S0D1 8
-#define R8A7796_CLK_S0D2 9
-#define R8A7796_CLK_S0D3 10
-#define R8A7796_CLK_S0D4 11
-#define R8A7796_CLK_S0D6 12
-#define R8A7796_CLK_S0D8 13
-#define R8A7796_CLK_S0D12 14
-#define R8A7796_CLK_S1D1 15
-#define R8A7796_CLK_S1D2 16
-#define R8A7796_CLK_S1D4 17
-#define R8A7796_CLK_S2D1 18
-#define R8A7796_CLK_S2D2 19
-#define R8A7796_CLK_S2D4 20
-#define R8A7796_CLK_S3D1 21
-#define R8A7796_CLK_S3D2 22
-#define R8A7796_CLK_S3D4 23
-#define R8A7796_CLK_LB 24
-#define R8A7796_CLK_CL 25
-#define R8A7796_CLK_ZB3 26
-#define R8A7796_CLK_ZB3D2 27
-#define R8A7796_CLK_ZB3D4 28
-#define R8A7796_CLK_CR 29
-#define R8A7796_CLK_CRD2 30
-#define R8A7796_CLK_SD0H 31
-#define R8A7796_CLK_SD0 32
-#define R8A7796_CLK_SD1H 33
-#define R8A7796_CLK_SD1 34
-#define R8A7796_CLK_SD2H 35
-#define R8A7796_CLK_SD2 36
-#define R8A7796_CLK_SD3H 37
-#define R8A7796_CLK_SD3 38
-#define R8A7796_CLK_SSP2 39
-#define R8A7796_CLK_SSP1 40
-#define R8A7796_CLK_SSPRS 41
-#define R8A7796_CLK_RPC 42
-#define R8A7796_CLK_RPCD2 43
-#define R8A7796_CLK_MSO 44
-#define R8A7796_CLK_CANFD 45
-#define R8A7796_CLK_HDMI 46
-#define R8A7796_CLK_CSI0 47
-/* CLK_CSIREF was removed */
-#define R8A7796_CLK_CP 49
-#define R8A7796_CLK_CPEX 50
-#define R8A7796_CLK_R 51
-#define R8A7796_CLK_OSC 52
-
-#endif /* __DT_BINDINGS_CLOCK_R8A7796_CPG_MSSR_H__ */
diff --git a/include/dt-bindings/clock/r8a77965-cpg-mssr.h b/include/dt-bindings/clock/r8a77965-cpg-mssr.h
deleted file mode 100644
index 6d3b5a9..0000000
--- a/include/dt-bindings/clock/r8a77965-cpg-mssr.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2018 Jacopo Mondi <jacopo+renesas@jmondi.org>
- */
-#ifndef __DT_BINDINGS_CLOCK_R8A77965_CPG_MSSR_H__
-#define __DT_BINDINGS_CLOCK_R8A77965_CPG_MSSR_H__
-
-#include <dt-bindings/clock/renesas-cpg-mssr.h>
-
-/* r8a77965 CPG Core Clocks */
-#define R8A77965_CLK_Z 0
-#define R8A77965_CLK_ZR 1
-#define R8A77965_CLK_ZG 2
-#define R8A77965_CLK_ZTR 3
-#define R8A77965_CLK_ZTRD2 4
-#define R8A77965_CLK_ZT 5
-#define R8A77965_CLK_ZX 6
-#define R8A77965_CLK_S0D1 7
-#define R8A77965_CLK_S0D2 8
-#define R8A77965_CLK_S0D3 9
-#define R8A77965_CLK_S0D4 10
-#define R8A77965_CLK_S0D6 11
-#define R8A77965_CLK_S0D8 12
-#define R8A77965_CLK_S0D12 13
-#define R8A77965_CLK_S1D1 14
-#define R8A77965_CLK_S1D2 15
-#define R8A77965_CLK_S1D4 16
-#define R8A77965_CLK_S2D1 17
-#define R8A77965_CLK_S2D2 18
-#define R8A77965_CLK_S2D4 19
-#define R8A77965_CLK_S3D1 20
-#define R8A77965_CLK_S3D2 21
-#define R8A77965_CLK_S3D4 22
-#define R8A77965_CLK_LB 23
-#define R8A77965_CLK_CL 24
-#define R8A77965_CLK_ZB3 25
-#define R8A77965_CLK_ZB3D2 26
-#define R8A77965_CLK_CR 27
-#define R8A77965_CLK_CRD2 28
-#define R8A77965_CLK_SD0H 29
-#define R8A77965_CLK_SD0 30
-#define R8A77965_CLK_SD1H 31
-#define R8A77965_CLK_SD1 32
-#define R8A77965_CLK_SD2H 33
-#define R8A77965_CLK_SD2 34
-#define R8A77965_CLK_SD3H 35
-#define R8A77965_CLK_SD3 36
-#define R8A77965_CLK_SSP2 37
-#define R8A77965_CLK_SSP1 38
-#define R8A77965_CLK_SSPRS 39
-#define R8A77965_CLK_RPC 40
-#define R8A77965_CLK_RPCD2 41
-#define R8A77965_CLK_MSO 42
-#define R8A77965_CLK_CANFD 43
-#define R8A77965_CLK_HDMI 44
-#define R8A77965_CLK_CSI0 45
-#define R8A77965_CLK_CP 46
-#define R8A77965_CLK_CPEX 47
-#define R8A77965_CLK_R 48
-#define R8A77965_CLK_OSC 49
-
-#endif /* __DT_BINDINGS_CLOCK_R8A77965_CPG_MSSR_H__ */
diff --git a/include/dt-bindings/clock/r8a77970-cpg-mssr.h b/include/dt-bindings/clock/r8a77970-cpg-mssr.h
deleted file mode 100644
index 4146395..0000000
--- a/include/dt-bindings/clock/r8a77970-cpg-mssr.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * Copyright (C) 2016 Renesas Electronics Corp.
- * Copyright (C) 2017 Cogent Embedded, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-#ifndef __DT_BINDINGS_CLOCK_R8A77970_CPG_MSSR_H__
-#define __DT_BINDINGS_CLOCK_R8A77970_CPG_MSSR_H__
-
-#include <dt-bindings/clock/renesas-cpg-mssr.h>
-
-/* r8a77970 CPG Core Clocks */
-#define R8A77970_CLK_Z2 0
-#define R8A77970_CLK_ZR 1
-#define R8A77970_CLK_ZTR 2
-#define R8A77970_CLK_ZTRD2 3
-#define R8A77970_CLK_ZT 4
-#define R8A77970_CLK_ZX 5
-#define R8A77970_CLK_S1D1 6
-#define R8A77970_CLK_S1D2 7
-#define R8A77970_CLK_S1D4 8
-#define R8A77970_CLK_S2D1 9
-#define R8A77970_CLK_S2D2 10
-#define R8A77970_CLK_S2D4 11
-#define R8A77970_CLK_LB 12
-#define R8A77970_CLK_CL 13
-#define R8A77970_CLK_ZB3 14
-#define R8A77970_CLK_ZB3D2 15
-#define R8A77970_CLK_DDR 16
-#define R8A77970_CLK_CR 17
-#define R8A77970_CLK_CRD2 18
-#define R8A77970_CLK_SD0H 19
-#define R8A77970_CLK_SD0 20
-#define R8A77970_CLK_RPC 21
-#define R8A77970_CLK_RPCD2 22
-#define R8A77970_CLK_MSO 23
-#define R8A77970_CLK_CANFD 24
-#define R8A77970_CLK_CSI0 25
-#define R8A77970_CLK_FRAY 26
-#define R8A77970_CLK_CP 27
-#define R8A77970_CLK_CPEX 28
-#define R8A77970_CLK_R 29
-#define R8A77970_CLK_OSC 30
-
-#endif /* __DT_BINDINGS_CLOCK_R8A77970_CPG_MSSR_H__ */
diff --git a/include/dt-bindings/clock/r8a77980-cpg-mssr.h b/include/dt-bindings/clock/r8a77980-cpg-mssr.h
deleted file mode 100644
index a4c0d76..0000000
--- a/include/dt-bindings/clock/r8a77980-cpg-mssr.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2018 Renesas Electronics Corp.
- * Copyright (C) 2018 Cogent Embedded, Inc.
- */
-#ifndef __DT_BINDINGS_CLOCK_R8A77980_CPG_MSSR_H__
-#define __DT_BINDINGS_CLOCK_R8A77980_CPG_MSSR_H__
-
-#include <dt-bindings/clock/renesas-cpg-mssr.h>
-
-/* r8a77980 CPG Core Clocks */
-#define R8A77980_CLK_Z2 0
-#define R8A77980_CLK_ZR 1
-#define R8A77980_CLK_ZTR 2
-#define R8A77980_CLK_ZTRD2 3
-#define R8A77980_CLK_ZT 4
-#define R8A77980_CLK_ZX 5
-#define R8A77980_CLK_S0D1 6
-#define R8A77980_CLK_S0D2 7
-#define R8A77980_CLK_S0D3 8
-#define R8A77980_CLK_S0D4 9
-#define R8A77980_CLK_S0D6 10
-#define R8A77980_CLK_S0D12 11
-#define R8A77980_CLK_S0D24 12
-#define R8A77980_CLK_S1D1 13
-#define R8A77980_CLK_S1D2 14
-#define R8A77980_CLK_S1D4 15
-#define R8A77980_CLK_S2D1 16
-#define R8A77980_CLK_S2D2 17
-#define R8A77980_CLK_S2D4 18
-#define R8A77980_CLK_S3D1 19
-#define R8A77980_CLK_S3D2 20
-#define R8A77980_CLK_S3D4 21
-#define R8A77980_CLK_LB 22
-#define R8A77980_CLK_CL 23
-#define R8A77980_CLK_ZB3 24
-#define R8A77980_CLK_ZB3D2 25
-#define R8A77980_CLK_ZB3D4 26
-#define R8A77980_CLK_SD0H 27
-#define R8A77980_CLK_SD0 28
-#define R8A77980_CLK_RPC 29
-#define R8A77980_CLK_RPCD2 30
-#define R8A77980_CLK_MSO 31
-#define R8A77980_CLK_CANFD 32
-#define R8A77980_CLK_CSI0 33
-#define R8A77980_CLK_CP 34
-#define R8A77980_CLK_CPEX 35
-#define R8A77980_CLK_R 36
-#define R8A77980_CLK_OSC 37
-
-#endif /* __DT_BINDINGS_CLOCK_R8A77980_CPG_MSSR_H__ */
diff --git a/include/dt-bindings/clock/r8a77990-cpg-mssr.h b/include/dt-bindings/clock/r8a77990-cpg-mssr.h
deleted file mode 100644
index a596a48..0000000
--- a/include/dt-bindings/clock/r8a77990-cpg-mssr.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2018 Renesas Electronics Corp.
- */
-#ifndef __DT_BINDINGS_CLOCK_R8A77990_CPG_MSSR_H__
-#define __DT_BINDINGS_CLOCK_R8A77990_CPG_MSSR_H__
-
-#include <dt-bindings/clock/renesas-cpg-mssr.h>
-
-/* r8a77990 CPG Core Clocks */
-#define R8A77990_CLK_Z2 0
-#define R8A77990_CLK_ZR 1
-#define R8A77990_CLK_ZG 2
-#define R8A77990_CLK_ZTR 3
-#define R8A77990_CLK_ZT 4
-#define R8A77990_CLK_ZX 5
-#define R8A77990_CLK_S0D1 6
-#define R8A77990_CLK_S0D3 7
-#define R8A77990_CLK_S0D6 8
-#define R8A77990_CLK_S0D12 9
-#define R8A77990_CLK_S0D24 10
-#define R8A77990_CLK_S1D1 11
-#define R8A77990_CLK_S1D2 12
-#define R8A77990_CLK_S1D4 13
-#define R8A77990_CLK_S2D1 14
-#define R8A77990_CLK_S2D2 15
-#define R8A77990_CLK_S2D4 16
-#define R8A77990_CLK_S3D1 17
-#define R8A77990_CLK_S3D2 18
-#define R8A77990_CLK_S3D4 19
-#define R8A77990_CLK_S0D6C 20
-#define R8A77990_CLK_S3D1C 21
-#define R8A77990_CLK_S3D2C 22
-#define R8A77990_CLK_S3D4C 23
-#define R8A77990_CLK_LB 24
-#define R8A77990_CLK_CL 25
-#define R8A77990_CLK_ZB3 26
-#define R8A77990_CLK_ZB3D2 27
-#define R8A77990_CLK_CR 28
-#define R8A77990_CLK_CRD2 29
-#define R8A77990_CLK_SD0H 30
-#define R8A77990_CLK_SD0 31
-#define R8A77990_CLK_SD1H 32
-#define R8A77990_CLK_SD1 33
-#define R8A77990_CLK_SD3H 34
-#define R8A77990_CLK_SD3 35
-#define R8A77990_CLK_RPC 36
-#define R8A77990_CLK_RPCD2 37
-#define R8A77990_CLK_ZA2 38
-#define R8A77990_CLK_ZA8 39
-#define R8A77990_CLK_Z2D 40
-#define R8A77990_CLK_CANFD 41
-#define R8A77990_CLK_MSO 42
-#define R8A77990_CLK_R 43
-#define R8A77990_CLK_OSC 44
-#define R8A77990_CLK_LV0 45
-#define R8A77990_CLK_LV1 46
-#define R8A77990_CLK_CSI0 47
-#define R8A77990_CLK_CP 48
-#define R8A77990_CLK_CPEX 49
-
-#endif /* __DT_BINDINGS_CLOCK_R8A77990_CPG_MSSR_H__ */
diff --git a/include/dt-bindings/clock/r8a77995-cpg-mssr.h b/include/dt-bindings/clock/r8a77995-cpg-mssr.h
deleted file mode 100644
index fd701c4..0000000
--- a/include/dt-bindings/clock/r8a77995-cpg-mssr.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+
- *
- * Copyright (C) 2017 Glider bvba
- */
-#ifndef __DT_BINDINGS_CLOCK_R8A77995_CPG_MSSR_H__
-#define __DT_BINDINGS_CLOCK_R8A77995_CPG_MSSR_H__
-
-#include <dt-bindings/clock/renesas-cpg-mssr.h>
-
-/* r8a77995 CPG Core Clocks */
-#define R8A77995_CLK_Z2 0
-#define R8A77995_CLK_ZG 1
-#define R8A77995_CLK_ZTR 2
-#define R8A77995_CLK_ZT 3
-#define R8A77995_CLK_ZX 4
-#define R8A77995_CLK_S0D1 5
-#define R8A77995_CLK_S1D1 6
-#define R8A77995_CLK_S1D2 7
-#define R8A77995_CLK_S1D4 8
-#define R8A77995_CLK_S2D1 9
-#define R8A77995_CLK_S2D2 10
-#define R8A77995_CLK_S2D4 11
-#define R8A77995_CLK_S3D1 12
-#define R8A77995_CLK_S3D2 13
-#define R8A77995_CLK_S3D4 14
-#define R8A77995_CLK_S1D4C 15
-#define R8A77995_CLK_S3D1C 16
-#define R8A77995_CLK_S3D2C 17
-#define R8A77995_CLK_S3D4C 18
-#define R8A77995_CLK_LB 19
-#define R8A77995_CLK_CL 20
-#define R8A77995_CLK_ZB3 21
-#define R8A77995_CLK_ZB3D2 22
-#define R8A77995_CLK_CR 23
-#define R8A77995_CLK_CRD2 24
-#define R8A77995_CLK_SD0H 25
-#define R8A77995_CLK_SD0 26
-/* CLK_SSP2 was removed */
-/* CLK_SSP1 was removed */
-#define R8A77995_CLK_RPC 29
-#define R8A77995_CLK_RPCD2 30
-#define R8A77995_CLK_ZA2 31
-#define R8A77995_CLK_ZA8 32
-#define R8A77995_CLK_Z2D 33
-#define R8A77995_CLK_CANFD 34
-#define R8A77995_CLK_MSO 35
-#define R8A77995_CLK_R 36
-#define R8A77995_CLK_OSC 37
-#define R8A77995_CLK_LV0 38
-#define R8A77995_CLK_LV1 39
-#define R8A77995_CLK_CP 40
-#define R8A77995_CLK_CPEX 41
-
-#endif /* __DT_BINDINGS_CLOCK_R8A77995_CPG_MSSR_H__ */
diff --git a/include/dt-bindings/clock/renesas-cpg-mssr.h b/include/dt-bindings/clock/renesas-cpg-mssr.h
deleted file mode 100644
index 569a3cc..0000000
--- a/include/dt-bindings/clock/renesas-cpg-mssr.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/*
- * Copyright (C) 2015 Renesas Electronics Corp.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-#ifndef __DT_BINDINGS_CLOCK_RENESAS_CPG_MSSR_H__
-#define __DT_BINDINGS_CLOCK_RENESAS_CPG_MSSR_H__
-
-#define CPG_CORE 0 /* Core Clock */
-#define CPG_MOD 1 /* Module Clock */
-
-#endif /* __DT_BINDINGS_CLOCK_RENESAS_CPG_MSSR_H__ */
diff --git a/include/dt-bindings/clock/rk3036-cru.h b/include/dt-bindings/clock/rk3036-cru.h
deleted file mode 100644
index 2c0552d..0000000
--- a/include/dt-bindings/clock/rk3036-cru.h
+++ /dev/null
@@ -1,185 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (c) 2014 MundoReader S.L.
- * Author: Heiko Stuebner <heiko@sntech.de>
- */
-
-#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3036_H
-#define _DT_BINDINGS_CLK_ROCKCHIP_RK3036_H
-
-/* core clocks */
-#define PLL_APLL 1
-#define PLL_DPLL 2
-#define PLL_GPLL 3
-#define ARMCLK 4
-
-/* sclk gates (special clocks) */
-#define SCLK_GPU 64
-#define SCLK_SPI 65
-#define SCLK_SDMMC 68
-#define SCLK_SDIO 69
-#define SCLK_EMMC 71
-#define SCLK_NANDC 76
-#define SCLK_UART0 77
-#define SCLK_UART1 78
-#define SCLK_UART2 79
-#define SCLK_I2S 82
-#define SCLK_SPDIF 83
-#define SCLK_TIMER0 85
-#define SCLK_TIMER1 86
-#define SCLK_TIMER2 87
-#define SCLK_TIMER3 88
-#define SCLK_OTGPHY0 93
-#define SCLK_LCDC 100
-#define SCLK_HDMI 109
-#define SCLK_HEVC 111
-#define SCLK_I2S_OUT 113
-#define SCLK_SDMMC_DRV 114
-#define SCLK_SDIO_DRV 115
-#define SCLK_EMMC_DRV 117
-#define SCLK_SDMMC_SAMPLE 118
-#define SCLK_SDIO_SAMPLE 119
-#define SCLK_EMMC_SAMPLE 121
-#define SCLK_PVTM_CORE 123
-#define SCLK_PVTM_GPU 124
-#define SCLK_PVTM_VIDEO 125
-#define SCLK_MAC 151
-#define SCLK_MACREF 152
-#define SCLK_SFC 160
-
-#define DCLK_LCDC 190
-
-/* aclk gates */
-#define ACLK_DMAC2 194
-#define ACLK_LCDC 197
-#define ACLK_VIO 203
-#define ACLK_VCODEC 208
-#define ACLK_CPU 209
-#define ACLK_PERI 210
-
-/* pclk gates */
-#define PCLK_GPIO0 320
-#define PCLK_GPIO1 321
-#define PCLK_GPIO2 322
-#define PCLK_GRF 329
-#define PCLK_I2C0 332
-#define PCLK_I2C1 333
-#define PCLK_I2C2 334
-#define PCLK_SPI 338
-#define PCLK_UART0 341
-#define PCLK_UART1 342
-#define PCLK_UART2 343
-#define PCLK_PWM 350
-#define PCLK_TIMER 353
-#define PCLK_HDMI 360
-#define PCLK_CPU 362
-#define PCLK_PERI 363
-#define PCLK_DDRUPCTL 364
-#define PCLK_WDT 368
-
-/* hclk gates */
-#define HCLK_OTG0 449
-#define HCLK_OTG1 450
-#define HCLK_NANDC 453
-#define HCLK_SDMMC 456
-#define HCLK_SDIO 457
-#define HCLK_EMMC 459
-#define HCLK_I2S 462
-#define HCLK_LCDC 465
-#define HCLK_ROM 467
-#define HCLK_VIO_BUS 472
-#define HCLK_VCODEC 476
-#define HCLK_CPU 477
-#define HCLK_PERI 478
-
-#define CLK_NR_CLKS (HCLK_PERI + 1)
-
-/* soft-reset indices */
-#define SRST_CORE0 0
-#define SRST_CORE1 1
-#define SRST_CORE0_DBG 4
-#define SRST_CORE1_DBG 5
-#define SRST_CORE0_POR 8
-#define SRST_CORE1_POR 9
-#define SRST_L2C 12
-#define SRST_TOPDBG 13
-#define SRST_STRC_SYS_A 14
-#define SRST_PD_CORE_NIU 15
-
-#define SRST_TIMER2 16
-#define SRST_CPUSYS_H 17
-#define SRST_AHB2APB_H 19
-#define SRST_TIMER3 20
-#define SRST_INTMEM 21
-#define SRST_ROM 22
-#define SRST_PERI_NIU 23
-#define SRST_I2S 24
-#define SRST_DDR_PLL 25
-#define SRST_GPU_DLL 26
-#define SRST_TIMER0 27
-#define SRST_TIMER1 28
-#define SRST_CORE_DLL 29
-#define SRST_EFUSE_P 30
-#define SRST_ACODEC_P 31
-
-#define SRST_GPIO0 32
-#define SRST_GPIO1 33
-#define SRST_GPIO2 34
-#define SRST_UART0 39
-#define SRST_UART1 40
-#define SRST_UART2 41
-#define SRST_I2C0 43
-#define SRST_I2C1 44
-#define SRST_I2C2 45
-#define SRST_SFC 47
-
-#define SRST_PWM0 48
-#define SRST_DAP 51
-#define SRST_DAP_SYS 52
-#define SRST_GRF 55
-#define SRST_PERIPHSYS_A 57
-#define SRST_PERIPHSYS_H 58
-#define SRST_PERIPHSYS_P 59
-#define SRST_CPU_PERI 61
-#define SRST_EMEM_PERI 62
-#define SRST_USB_PERI 63
-
-#define SRST_DMA2 64
-#define SRST_MAC 66
-#define SRST_NANDC 68
-#define SRST_USBOTG0 69
-#define SRST_OTGC0 71
-#define SRST_USBOTG1 72
-#define SRST_OTGC1 74
-#define SRST_DDRMSCH 79
-
-#define SRST_MMC0 81
-#define SRST_SDIO 82
-#define SRST_EMMC 83
-#define SRST_SPI0 84
-#define SRST_WDT 86
-#define SRST_DDRPHY 88
-#define SRST_DDRPHY_P 89
-#define SRST_DDRCTRL 90
-#define SRST_DDRCTRL_P 91
-
-#define SRST_HDMI_P 96
-#define SRST_VIO_BUS_H 99
-#define SRST_UTMI0 103
-#define SRST_UTMI1 104
-#define SRST_USBPOR 105
-
-#define SRST_VCODEC_A 112
-#define SRST_VCODEC_H 113
-#define SRST_VIO1_A 114
-#define SRST_HEVC 115
-#define SRST_VCODEC_NIU_A 116
-#define SRST_LCDC1_A 117
-#define SRST_LCDC1_H 118
-#define SRST_LCDC1_D 119
-#define SRST_GPU 120
-#define SRST_GPU_NIU_A 122
-
-#define SRST_DBG_P 131
-
-#endif
diff --git a/include/dt-bindings/clock/rk3066a-cru.h b/include/dt-bindings/clock/rk3066a-cru.h
deleted file mode 100644
index 014eec5..0000000
--- a/include/dt-bindings/clock/rk3066a-cru.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (c) 2014 MundoReader S.L.
- * Author: Heiko Stuebner <heiko@sntech.de>
- */
-
-#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3066A_H
-#define _DT_BINDINGS_CLK_ROCKCHIP_RK3066A_H
-
-#include <dt-bindings/clock/rk3188-cru-common.h>
-
-/* soft-reset indices */
-#define SRST_SRST1 0
-#define SRST_SRST2 1
-
-#define SRST_L2MEM 18
-#define SRST_I2S0 23
-#define SRST_I2S1 24
-#define SRST_I2S2 25
-#define SRST_TIMER2 29
-
-#define SRST_GPIO4 36
-#define SRST_GPIO6 38
-
-#define SRST_TSADC 92
-
-#define SRST_HDMI 96
-#define SRST_HDMI_APB 97
-#define SRST_CIF1 111
-
-#endif
diff --git a/include/dt-bindings/clock/rk3128-cru.h b/include/dt-bindings/clock/rk3128-cru.h
deleted file mode 100644
index cfb3afb..0000000
--- a/include/dt-bindings/clock/rk3128-cru.h
+++ /dev/null
@@ -1,189 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2017 Rockchip Electronics Co., Ltd
- */
-
-#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3128_H
-#define _DT_BINDINGS_CLK_ROCKCHIP_RK3128_H
-
-/* core clocks */
-#define PLL_APLL 1
-#define PLL_DPLL 2
-#define PLL_GPLL 3
-#define ARMCLK 4
-
-/* sclk gates (special clocks) */
-#define SCLK_GPU 64
-#define SCLK_SPI 65
-#define SCLK_SDMMC 68
-#define SCLK_SDIO 69
-#define SCLK_EMMC 71
-#define SCLK_NANDC 76
-#define SCLK_UART0 77
-#define SCLK_UART1 78
-#define SCLK_UART2 79
-#define SCLK_I2S 82
-#define SCLK_SPDIF 83
-#define SCLK_TIMER0 85
-#define SCLK_TIMER1 86
-#define SCLK_TIMER2 87
-#define SCLK_TIMER3 88
-#define SCLK_SARADC 91
-#define SCLK_OTGPHY0 93
-#define SCLK_LCDC 100
-#define SCLK_HDMI 109
-#define SCLK_HEVC 111
-#define SCLK_I2S_OUT 113
-#define SCLK_SDMMC_DRV 114
-#define SCLK_SDIO_DRV 115
-#define SCLK_EMMC_DRV 117
-#define SCLK_SDMMC_SAMPLE 118
-#define SCLK_SDIO_SAMPLE 119
-#define SCLK_EMMC_SAMPLE 121
-#define SCLK_PVTM_CORE 123
-#define SCLK_PVTM_GPU 124
-#define SCLK_PVTM_VIDEO 125
-#define SCLK_MAC 151
-#define SCLK_MACREF 152
-#define SCLK_SFC 160
-
-#define DCLK_LCDC 190
-
-/* aclk gates */
-#define ACLK_DMAC2 194
-#define ACLK_VIO0 197
-#define ACLK_VIO1 203
-#define ACLK_VCODEC 208
-#define ACLK_CPU 209
-#define ACLK_PERI 210
-
-/* pclk gates */
-#define PCLK_SARADC 318
-#define PCLK_GPIO0 320
-#define PCLK_GPIO1 321
-#define PCLK_GPIO2 322
-#define PCLK_GPIO3 323
-#define PCLK_GRF 329
-#define PCLK_I2C0 332
-#define PCLK_I2C1 333
-#define PCLK_I2C2 334
-#define PCLK_I2C3 335
-#define PCLK_SPI 338
-#define PCLK_UART0 341
-#define PCLK_UART1 342
-#define PCLK_UART2 343
-#define PCLK_PWM 350
-#define PCLK_TIMER 353
-#define PCLK_HDMI 360
-#define PCLK_CPU 362
-#define PCLK_PERI 363
-#define PCLK_DDRUPCTL 364
-#define PCLK_WDT 368
-
-/* hclk gates */
-#define HCLK_OTG0 449
-#define HCLK_OTG1 450
-#define HCLK_NANDC 453
-#define HCLK_SDMMC 456
-#define HCLK_SDIO 457
-#define HCLK_EMMC 459
-#define HCLK_I2S 462
-#define HCLK_LCDC 465
-#define HCLK_ROM 467
-#define HCLK_VIO_BUS 472
-#define HCLK_VCODEC 476
-#define HCLK_CPU 477
-#define HCLK_PERI 478
-
-#define CLK_NR_CLKS (HCLK_PERI + 1)
-
-/* soft-reset indices */
-#define SRST_CORE0 0
-#define SRST_CORE1 1
-#define SRST_CORE0_DBG 4
-#define SRST_CORE1_DBG 5
-#define SRST_CORE0_POR 8
-#define SRST_CORE1_POR 9
-#define SRST_L2C 12
-#define SRST_TOPDBG 13
-#define SRST_STRC_SYS_A 14
-#define SRST_PD_CORE_NIU 15
-
-#define SRST_TIMER2 16
-#define SRST_CPUSYS_H 17
-#define SRST_AHB2APB_H 19
-#define SRST_TIMER3 20
-#define SRST_INTMEM 21
-#define SRST_ROM 22
-#define SRST_PERI_NIU 23
-#define SRST_I2S 24
-#define SRST_DDR_PLL 25
-#define SRST_GPU_DLL 26
-#define SRST_TIMER0 27
-#define SRST_TIMER1 28
-#define SRST_CORE_DLL 29
-#define SRST_EFUSE_P 30
-#define SRST_ACODEC_P 31
-
-#define SRST_GPIO0 32
-#define SRST_GPIO1 33
-#define SRST_GPIO2 34
-#define SRST_UART0 39
-#define SRST_UART1 40
-#define SRST_UART2 41
-#define SRST_I2C0 43
-#define SRST_I2C1 44
-#define SRST_I2C2 45
-#define SRST_SFC 47
-
-#define SRST_PWM0 48
-#define SRST_DAP 51
-#define SRST_DAP_SYS 52
-#define SRST_GRF 55
-#define SRST_PERIPHSYS_A 57
-#define SRST_PERIPHSYS_H 58
-#define SRST_PERIPHSYS_P 59
-#define SRST_CPU_PERI 61
-#define SRST_EMEM_PERI 62
-#define SRST_USB_PERI 63
-
-#define SRST_DMA2 64
-#define SRST_MAC 66
-#define SRST_NANDC 68
-#define SRST_USBOTG0 69
-#define SRST_OTGC0 71
-#define SRST_USBOTG1 72
-#define SRST_OTGC1 74
-#define SRST_DDRMSCH 79
-
-#define SRST_MMC0 81
-#define SRST_SDIO 82
-#define SRST_EMMC 83
-#define SRST_SPI0 84
-#define SRST_WDT 86
-#define SRST_SARADC 87
-#define SRST_DDRPHY 88
-#define SRST_DDRPHY_P 89
-#define SRST_DDRCTRL 90
-#define SRST_DDRCTRL_P 91
-
-#define SRST_HDMI_P 96
-#define SRST_VIO_BUS_H 99
-#define SRST_UTMI0 103
-#define SRST_UTMI1 104
-#define SRST_USBPOR 105
-
-#define SRST_VCODEC_A 112
-#define SRST_VCODEC_H 113
-#define SRST_VIO1_A 114
-#define SRST_HEVC 115
-#define SRST_VCODEC_NIU_A 116
-#define SRST_LCDC1_A 117
-#define SRST_LCDC1_H 118
-#define SRST_LCDC1_D 119
-#define SRST_GPU 120
-#define SRST_GPU_NIU_A 122
-
-#define SRST_DBG_P 131
-
-#endif
diff --git a/include/dt-bindings/clock/rk3188-cru-common.h b/include/dt-bindings/clock/rk3188-cru-common.h
deleted file mode 100644
index 1e7931d..0000000
--- a/include/dt-bindings/clock/rk3188-cru-common.h
+++ /dev/null
@@ -1,255 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (c) 2014 MundoReader S.L.
- * Author: Heiko Stuebner <heiko@sntech.de>
- */
-
-#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3188_COMMON_H
-#define _DT_BINDINGS_CLK_ROCKCHIP_RK3188_COMMON_H
-
-/* core clocks from */
-#define PLL_APLL 1
-#define PLL_DPLL 2
-#define PLL_CPLL 3
-#define PLL_GPLL 4
-#define CORE_PERI 5
-#define CORE_L2C 6
-#define ARMCLK 7
-
-/* sclk gates (special clocks) */
-#define SCLK_UART0 64
-#define SCLK_UART1 65
-#define SCLK_UART2 66
-#define SCLK_UART3 67
-#define SCLK_MAC 68
-#define SCLK_SPI0 69
-#define SCLK_SPI1 70
-#define SCLK_SARADC 71
-#define SCLK_SDMMC 72
-#define SCLK_SDIO 73
-#define SCLK_EMMC 74
-#define SCLK_I2S0 75
-#define SCLK_I2S1 76
-#define SCLK_I2S2 77
-#define SCLK_SPDIF 78
-#define SCLK_CIF0 79
-#define SCLK_CIF1 80
-#define SCLK_OTGPHY0 81
-#define SCLK_OTGPHY1 82
-#define SCLK_HSADC 83
-#define SCLK_TIMER0 84
-#define SCLK_TIMER1 85
-#define SCLK_TIMER2 86
-#define SCLK_TIMER3 87
-#define SCLK_TIMER4 88
-#define SCLK_TIMER5 89
-#define SCLK_TIMER6 90
-#define SCLK_JTAG 91
-#define SCLK_SMC 92
-#define SCLK_TSADC 93
-
-#define DCLK_LCDC0 190
-#define DCLK_LCDC1 191
-
-/* aclk gates */
-#define ACLK_DMA1 192
-#define ACLK_DMA2 193
-#define ACLK_GPS 194
-#define ACLK_LCDC0 195
-#define ACLK_LCDC1 196
-#define ACLK_GPU 197
-#define ACLK_SMC 198
-#define ACLK_CIF 199
-#define ACLK_IPP 200
-#define ACLK_RGA 201
-#define ACLK_CIF0 202
-#define ACLK_CPU 203
-#define ACLK_PERI 204
-
-/* pclk gates */
-#define PCLK_GRF 320
-#define PCLK_PMU 321
-#define PCLK_TIMER0 322
-#define PCLK_TIMER1 323
-#define PCLK_TIMER2 324
-#define PCLK_TIMER3 325
-#define PCLK_PWM01 326
-#define PCLK_PWM23 327
-#define PCLK_SPI0 328
-#define PCLK_SPI1 329
-#define PCLK_SARADC 330
-#define PCLK_WDT 331
-#define PCLK_UART0 332
-#define PCLK_UART1 333
-#define PCLK_UART2 334
-#define PCLK_UART3 335
-#define PCLK_I2C0 336
-#define PCLK_I2C1 337
-#define PCLK_I2C2 338
-#define PCLK_I2C3 339
-#define PCLK_I2C4 340
-#define PCLK_GPIO0 341
-#define PCLK_GPIO1 342
-#define PCLK_GPIO2 343
-#define PCLK_GPIO3 344
-#define PCLK_GPIO4 345
-#define PCLK_GPIO6 346
-#define PCLK_EFUSE 347
-#define PCLK_TZPC 348
-#define PCLK_TSADC 349
-#define PCLK_CPU 350
-#define PCLK_PERI 351
-#define PCLK_DDRUPCTL 352
-#define PCLK_PUBL 353
-
-/* hclk gates */
-#define HCLK_SDMMC 448
-#define HCLK_SDIO 449
-#define HCLK_EMMC 450
-#define HCLK_OTG0 451
-#define HCLK_EMAC 452
-#define HCLK_SPDIF 453
-#define HCLK_I2S0 454
-#define HCLK_I2S1 455
-#define HCLK_I2S2 456
-#define HCLK_OTG1 457
-#define HCLK_HSIC 458
-#define HCLK_HSADC 459
-#define HCLK_PIDF 460
-#define HCLK_LCDC0 461
-#define HCLK_LCDC1 462
-#define HCLK_ROM 463
-#define HCLK_CIF0 464
-#define HCLK_IPP 465
-#define HCLK_RGA 466
-#define HCLK_NANDC0 467
-#define HCLK_CPU 468
-#define HCLK_PERI 469
-
-#define CLK_NR_CLKS (HCLK_PERI + 1)
-
-/* soft-reset indices */
-#define SRST_MCORE 2
-#define SRST_CORE0 3
-#define SRST_CORE1 4
-#define SRST_MCORE_DBG 7
-#define SRST_CORE0_DBG 8
-#define SRST_CORE1_DBG 9
-#define SRST_CORE0_WDT 12
-#define SRST_CORE1_WDT 13
-#define SRST_STRC_SYS 14
-#define SRST_L2C 15
-
-#define SRST_CPU_AHB 17
-#define SRST_AHB2APB 19
-#define SRST_DMA1 20
-#define SRST_INTMEM 21
-#define SRST_ROM 22
-#define SRST_SPDIF 26
-#define SRST_TIMER0 27
-#define SRST_TIMER1 28
-#define SRST_EFUSE 30
-
-#define SRST_GPIO0 32
-#define SRST_GPIO1 33
-#define SRST_GPIO2 34
-#define SRST_GPIO3 35
-
-#define SRST_UART0 39
-#define SRST_UART1 40
-#define SRST_UART2 41
-#define SRST_UART3 42
-#define SRST_I2C0 43
-#define SRST_I2C1 44
-#define SRST_I2C2 45
-#define SRST_I2C3 46
-#define SRST_I2C4 47
-
-#define SRST_PWM0 48
-#define SRST_PWM1 49
-#define SRST_DAP_PO 50
-#define SRST_DAP 51
-#define SRST_DAP_SYS 52
-#define SRST_TPIU_ATB 53
-#define SRST_PMU_APB 54
-#define SRST_GRF 55
-#define SRST_PMU 56
-#define SRST_PERI_AXI 57
-#define SRST_PERI_AHB 58
-#define SRST_PERI_APB 59
-#define SRST_PERI_NIU 60
-#define SRST_CPU_PERI 61
-#define SRST_EMEM_PERI 62
-#define SRST_USB_PERI 63
-
-#define SRST_DMA2 64
-#define SRST_SMC 65
-#define SRST_MAC 66
-#define SRST_NANC0 68
-#define SRST_USBOTG0 69
-#define SRST_USBPHY0 70
-#define SRST_OTGC0 71
-#define SRST_USBOTG1 72
-#define SRST_USBPHY1 73
-#define SRST_OTGC1 74
-#define SRST_HSADC 76
-#define SRST_PIDFILTER 77
-#define SRST_DDR_MSCH 79
-
-#define SRST_TZPC 80
-#define SRST_SDMMC 81
-#define SRST_SDIO 82
-#define SRST_EMMC 83
-#define SRST_SPI0 84
-#define SRST_SPI1 85
-#define SRST_WDT 86
-#define SRST_SARADC 87
-#define SRST_DDRPHY 88
-#define SRST_DDRPHY_APB 89
-#define SRST_DDRCTL 90
-#define SRST_DDRCTL_APB 91
-#define SRST_DDRPUB 93
-
-#define SRST_VIO0_AXI 98
-#define SRST_VIO0_AHB 99
-#define SRST_LCDC0_AXI 100
-#define SRST_LCDC0_AHB 101
-#define SRST_LCDC0_DCLK 102
-#define SRST_LCDC1_AXI 103
-#define SRST_LCDC1_AHB 104
-#define SRST_LCDC1_DCLK 105
-#define SRST_IPP_AXI 106
-#define SRST_IPP_AHB 107
-#define SRST_RGA_AXI 108
-#define SRST_RGA_AHB 109
-#define SRST_CIF0 110
-
-#define SRST_VCODEC_AXI 112
-#define SRST_VCODEC_AHB 113
-#define SRST_VIO1_AXI 114
-#define SRST_VCODEC_CPU 115
-#define SRST_VCODEC_NIU 116
-#define SRST_GPU 120
-#define SRST_GPU_NIU 122
-#define SRST_TFUN_ATB 125
-#define SRST_TFUN_APB 126
-#define SRST_CTI4_APB 127
-
-#define SRST_TPIU_APB 128
-#define SRST_TRACE 129
-#define SRST_CORE_DBG 130
-#define SRST_DBG_APB 131
-#define SRST_CTI0 132
-#define SRST_CTI0_APB 133
-#define SRST_CTI1 134
-#define SRST_CTI1_APB 135
-#define SRST_PTM_CORE0 136
-#define SRST_PTM_CORE1 137
-#define SRST_PTM0 138
-#define SRST_PTM0_ATB 139
-#define SRST_PTM1 140
-#define SRST_PTM1_ATB 141
-#define SRST_CTM 142
-#define SRST_TS 143
-
-#endif
diff --git a/include/dt-bindings/clock/rk3188-cru.h b/include/dt-bindings/clock/rk3188-cru.h
deleted file mode 100644
index 1da306e..0000000
--- a/include/dt-bindings/clock/rk3188-cru.h
+++ /dev/null
@@ -1,47 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (c) 2014 MundoReader S.L.
- * Author: Heiko Stuebner <heiko@sntech.de>
- */
-
-#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3188_H
-#define _DT_BINDINGS_CLK_ROCKCHIP_RK3188_H
-
-#include <dt-bindings/clock/rk3188-cru-common.h>
-
-/* soft-reset indices */
-#define SRST_PTM_CORE2 0
-#define SRST_PTM_CORE3 1
-#define SRST_CORE2 5
-#define SRST_CORE3 6
-#define SRST_CORE2_DBG 10
-#define SRST_CORE3_DBG 11
-
-#define SRST_TIMER2 16
-#define SRST_TIMER4 23
-#define SRST_I2S0 24
-#define SRST_TIMER5 25
-#define SRST_TIMER3 29
-#define SRST_TIMER6 31
-
-#define SRST_PTM3 36
-#define SRST_PTM3_ATB 37
-
-#define SRST_GPS 67
-#define SRST_HSICPHY 75
-#define SRST_TIMER 78
-
-#define SRST_PTM2 92
-#define SRST_CORE2_WDT 94
-#define SRST_CORE3_WDT 95
-
-#define SRST_PTM2_ATB 111
-
-#define SRST_HSIC 117
-#define SRST_CTI2 118
-#define SRST_CTI2_APB 119
-#define SRST_GPU_BRIDGE 121
-#define SRST_CTI3 123
-#define SRST_CTI3_APB 124
-
-#endif
diff --git a/include/dt-bindings/clock/rk3228-cru.h b/include/dt-bindings/clock/rk3228-cru.h
deleted file mode 100644
index 1217d52..0000000
--- a/include/dt-bindings/clock/rk3228-cru.h
+++ /dev/null
@@ -1,237 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2017 Rockchip Electronics Co., Ltd.
- */
-
-#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3228_H
-#define _DT_BINDINGS_CLK_ROCKCHIP_RK3228_H
-
-/* core clocks */
-#define PLL_APLL 1
-#define PLL_DPLL 2
-#define PLL_CPLL 3
-#define PLL_GPLL 4
-#define ARMCLK 5
-
-/* sclk gates (special clocks) */
-#define SCLK_SPI0 65
-#define SCLK_NANDC 67
-#define SCLK_SDMMC 68
-#define SCLK_SDIO 69
-#define SCLK_EMMC 71
-#define SCLK_TSADC 72
-#define SCLK_UART0 77
-#define SCLK_UART1 78
-#define SCLK_UART2 79
-#define SCLK_I2S0 80
-#define SCLK_I2S1 81
-#define SCLK_I2S2 82
-#define SCLK_SPDIF 83
-#define SCLK_TIMER0 85
-#define SCLK_TIMER1 86
-#define SCLK_TIMER2 87
-#define SCLK_TIMER3 88
-#define SCLK_TIMER4 89
-#define SCLK_TIMER5 90
-#define SCLK_I2S_OUT 113
-#define SCLK_SDMMC_DRV 114
-#define SCLK_SDIO_DRV 115
-#define SCLK_EMMC_DRV 117
-#define SCLK_SDMMC_SAMPLE 118
-#define SCLK_SDIO_SAMPLE 119
-#define SCLK_EMMC_SAMPLE 121
-#define SCLK_VOP 122
-#define SCLK_HDMI_HDCP 123
-#define SCLK_MAC_SRC 124
-#define SCLK_MAC_EXTCLK 125
-#define SCLK_MAC 126
-#define SCLK_MAC_REFOUT 127
-#define SCLK_MAC_REF 128
-#define SCLK_MAC_RX 129
-#define SCLK_MAC_TX 130
-#define SCLK_MAC_PHY 131
-#define SCLK_MAC_OUT 132
-
-/* dclk gates */
-#define DCLK_VOP 190
-#define DCLK_HDMI_PHY 191
-
-/* aclk gates */
-#define ACLK_DMAC 194
-#define ACLK_PERI 210
-#define ACLK_VOP 211
-#define ACLK_GMAC 212
-
-/* pclk gates */
-#define PCLK_GPIO0 320
-#define PCLK_GPIO1 321
-#define PCLK_GPIO2 322
-#define PCLK_GPIO3 323
-#define PCLK_GRF 329
-#define PCLK_I2C0 332
-#define PCLK_I2C1 333
-#define PCLK_I2C2 334
-#define PCLK_I2C3 335
-#define PCLK_SPI0 338
-#define PCLK_UART0 341
-#define PCLK_UART1 342
-#define PCLK_UART2 343
-#define PCLK_TSADC 344
-#define PCLK_PWM 350
-#define PCLK_TIMER 353
-#define PCLK_PERI 363
-#define PCLK_HDMI_CTRL 364
-#define PCLK_HDMI_PHY 365
-#define PCLK_GMAC 367
-
-/* hclk gates */
-#define HCLK_I2S0_8CH 442
-#define HCLK_I2S1_8CH 443
-#define HCLK_I2S2_2CH 444
-#define HCLK_SPDIF_8CH 445
-#define HCLK_VOP 452
-#define HCLK_NANDC 453
-#define HCLK_SDMMC 456
-#define HCLK_SDIO 457
-#define HCLK_EMMC 459
-#define HCLK_PERI 478
-
-#define CLK_NR_CLKS (HCLK_PERI + 1)
-
-/* soft-reset indices */
-#define SRST_CORE0_PO 0
-#define SRST_CORE1_PO 1
-#define SRST_CORE2_PO 2
-#define SRST_CORE3_PO 3
-#define SRST_CORE0 4
-#define SRST_CORE1 5
-#define SRST_CORE2 6
-#define SRST_CORE3 7
-#define SRST_CORE0_DBG 8
-#define SRST_CORE1_DBG 9
-#define SRST_CORE2_DBG 10
-#define SRST_CORE3_DBG 11
-#define SRST_TOPDBG 12
-#define SRST_ACLK_CORE 13
-#define SRST_NOC 14
-#define SRST_L2C 15
-
-#define SRST_CPUSYS_H 18
-#define SRST_BUSSYS_H 19
-#define SRST_SPDIF 20
-#define SRST_INTMEM 21
-#define SRST_ROM 22
-#define SRST_OTG_ADP 23
-#define SRST_I2S0 24
-#define SRST_I2S1 25
-#define SRST_I2S2 26
-#define SRST_ACODEC_P 27
-#define SRST_DFIMON 28
-#define SRST_MSCH 29
-#define SRST_EFUSE1024 30
-#define SRST_EFUSE256 31
-
-#define SRST_GPIO0 32
-#define SRST_GPIO1 33
-#define SRST_GPIO2 34
-#define SRST_GPIO3 35
-#define SRST_PERIPH_NOC_A 36
-#define SRST_PERIPH_NOC_BUS_H 37
-#define SRST_PERIPH_NOC_P 38
-#define SRST_UART0 39
-#define SRST_UART1 40
-#define SRST_UART2 41
-#define SRST_PHYNOC 42
-#define SRST_I2C0 43
-#define SRST_I2C1 44
-#define SRST_I2C2 45
-#define SRST_I2C3 46
-
-#define SRST_PWM 48
-#define SRST_A53_GIC 49
-#define SRST_DAP 51
-#define SRST_DAP_NOC 52
-#define SRST_CRYPTO 53
-#define SRST_SGRF 54
-#define SRST_GRF 55
-#define SRST_GMAC 56
-#define SRST_PERIPH_NOC_H 58
-#define SRST_MACPHY 63
-
-#define SRST_DMA 64
-#define SRST_NANDC 68
-#define SRST_USBOTG 69
-#define SRST_OTGC 70
-#define SRST_USBHOST0 71
-#define SRST_HOST_CTRL0 72
-#define SRST_USBHOST1 73
-#define SRST_HOST_CTRL1 74
-#define SRST_USBHOST2 75
-#define SRST_HOST_CTRL2 76
-#define SRST_USBPOR0 77
-#define SRST_USBPOR1 78
-#define SRST_DDRMSCH 79
-
-#define SRST_SMART_CARD 80
-#define SRST_SDMMC 81
-#define SRST_SDIO 82
-#define SRST_EMMC 83
-#define SRST_SPI 84
-#define SRST_TSP_H 85
-#define SRST_TSP 86
-#define SRST_TSADC 87
-#define SRST_DDRPHY 88
-#define SRST_DDRPHY_P 89
-#define SRST_DDRCTRL 90
-#define SRST_DDRCTRL_P 91
-#define SRST_HOST0_ECHI 92
-#define SRST_HOST1_ECHI 93
-#define SRST_HOST2_ECHI 94
-#define SRST_VOP_NOC_A 95
-
-#define SRST_HDMI_P 96
-#define SRST_VIO_ARBI_H 97
-#define SRST_IEP_NOC_A 98
-#define SRST_VIO_NOC_H 99
-#define SRST_VOP_A 100
-#define SRST_VOP_H 101
-#define SRST_VOP_D 102
-#define SRST_UTMI0 103
-#define SRST_UTMI1 104
-#define SRST_UTMI2 105
-#define SRST_UTMI3 106
-#define SRST_RGA 107
-#define SRST_RGA_NOC_A 108
-#define SRST_RGA_A 109
-#define SRST_RGA_H 110
-#define SRST_HDCP_A 111
-
-#define SRST_VPU_A 112
-#define SRST_VPU_H 113
-#define SRST_VPU_NOC_A 116
-#define SRST_VPU_NOC_H 117
-#define SRST_RKVDEC_A 118
-#define SRST_RKVDEC_NOC_A 119
-#define SRST_RKVDEC_H 120
-#define SRST_RKVDEC_NOC_H 121
-#define SRST_RKVDEC_CORE 122
-#define SRST_RKVDEC_CABAC 123
-#define SRST_IEP_A 124
-#define SRST_IEP_H 125
-#define SRST_GPU_A 126
-#define SRST_GPU_NOC_A 127
-
-#define SRST_CORE_DBG 128
-#define SRST_DBG_P 129
-#define SRST_TIMER0 130
-#define SRST_TIMER1 131
-#define SRST_TIMER2 132
-#define SRST_TIMER3 133
-#define SRST_TIMER4 134
-#define SRST_TIMER5 135
-#define SRST_VIO_H2P 136
-#define SRST_HDMIPHY 139
-#define SRST_VDAC 140
-#define SRST_TIMER_6CH_P 141
-
-#endif
diff --git a/include/dt-bindings/clock/rk3288-cru.h b/include/dt-bindings/clock/rk3288-cru.h
deleted file mode 100644
index e368d76..0000000
--- a/include/dt-bindings/clock/rk3288-cru.h
+++ /dev/null
@@ -1,370 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (c) 2014 MundoReader S.L.
- * Author: Heiko Stuebner <heiko@sntech.de>
- */
-
-/* core clocks */
-#define PLL_APLL 1
-#define PLL_DPLL 2
-#define PLL_CPLL 3
-#define PLL_GPLL 4
-#define PLL_NPLL 5
-#define ARMCLK 6
-
-/* sclk gates (special clocks) */
-#define SCLK_GPU 64
-#define SCLK_SPI0 65
-#define SCLK_SPI1 66
-#define SCLK_SPI2 67
-#define SCLK_SDMMC 68
-#define SCLK_SDIO0 69
-#define SCLK_SDIO1 70
-#define SCLK_EMMC 71
-#define SCLK_TSADC 72
-#define SCLK_SARADC 73
-#define SCLK_PS2C 74
-#define SCLK_NANDC0 75
-#define SCLK_NANDC1 76
-#define SCLK_UART0 77
-#define SCLK_UART1 78
-#define SCLK_UART2 79
-#define SCLK_UART3 80
-#define SCLK_UART4 81
-#define SCLK_I2S0 82
-#define SCLK_SPDIF 83
-#define SCLK_SPDIF8CH 84
-#define SCLK_TIMER0 85
-#define SCLK_TIMER1 86
-#define SCLK_TIMER2 87
-#define SCLK_TIMER3 88
-#define SCLK_TIMER4 89
-#define SCLK_TIMER5 90
-#define SCLK_TIMER6 91
-#define SCLK_HSADC 92
-#define SCLK_OTGPHY0 93
-#define SCLK_OTGPHY1 94
-#define SCLK_OTGPHY2 95
-#define SCLK_OTG_ADP 96
-#define SCLK_HSICPHY480M 97
-#define SCLK_HSICPHY12M 98
-#define SCLK_MACREF 99
-#define SCLK_LCDC_PWM0 100
-#define SCLK_LCDC_PWM1 101
-#define SCLK_MAC_RX 102
-#define SCLK_MAC_TX 103
-#define SCLK_EDP_24M 104
-#define SCLK_EDP 105
-#define SCLK_RGA 106
-#define SCLK_ISP 107
-#define SCLK_ISP_JPE 108
-#define SCLK_HDMI_HDCP 109
-#define SCLK_HDMI_CEC 110
-#define SCLK_HEVC_CABAC 111
-#define SCLK_HEVC_CORE 112
-#define SCLK_I2S0_OUT 113
-#define SCLK_SDMMC_DRV 114
-#define SCLK_SDIO0_DRV 115
-#define SCLK_SDIO1_DRV 116
-#define SCLK_EMMC_DRV 117
-#define SCLK_SDMMC_SAMPLE 118
-#define SCLK_SDIO0_SAMPLE 119
-#define SCLK_SDIO1_SAMPLE 120
-#define SCLK_EMMC_SAMPLE 121
-#define SCLK_USBPHY480M_SRC 122
-#define SCLK_PVTM_CORE 123
-#define SCLK_PVTM_GPU 124
-
-#define SCLK_MAC_PLL 150
-#define SCLK_MAC 151
-#define SCLK_MACREF_OUT 152
-
-#define DCLK_VOP0 190
-#define DCLK_VOP1 191
-
-/* aclk gates */
-#define ACLK_GPU 192
-#define ACLK_DMAC1 193
-#define ACLK_DMAC2 194
-#define ACLK_MMU 195
-#define ACLK_GMAC 196
-#define ACLK_VOP0 197
-#define ACLK_VOP1 198
-#define ACLK_CRYPTO 199
-#define ACLK_RGA 200
-#define ACLK_RGA_NIU 201
-#define ACLK_IEP 202
-#define ACLK_VIO0_NIU 203
-#define ACLK_VIP 204
-#define ACLK_ISP 205
-#define ACLK_VIO1_NIU 206
-#define ACLK_HEVC 207
-#define ACLK_VCODEC 208
-#define ACLK_CPU 209
-#define ACLK_PERI 210
-
-/* pclk gates */
-#define PCLK_GPIO0 320
-#define PCLK_GPIO1 321
-#define PCLK_GPIO2 322
-#define PCLK_GPIO3 323
-#define PCLK_GPIO4 324
-#define PCLK_GPIO5 325
-#define PCLK_GPIO6 326
-#define PCLK_GPIO7 327
-#define PCLK_GPIO8 328
-#define PCLK_GRF 329
-#define PCLK_SGRF 330
-#define PCLK_PMU 331
-#define PCLK_I2C0 332
-#define PCLK_I2C1 333
-#define PCLK_I2C2 334
-#define PCLK_I2C3 335
-#define PCLK_I2C4 336
-#define PCLK_I2C5 337
-#define PCLK_SPI0 338
-#define PCLK_SPI1 339
-#define PCLK_SPI2 340
-#define PCLK_UART0 341
-#define PCLK_UART1 342
-#define PCLK_UART2 343
-#define PCLK_UART3 344
-#define PCLK_UART4 345
-#define PCLK_TSADC 346
-#define PCLK_SARADC 347
-#define PCLK_SIM 348
-#define PCLK_GMAC 349
-#define PCLK_PWM 350
-#define PCLK_RKPWM 351
-#define PCLK_PS2C 352
-#define PCLK_TIMER 353
-#define PCLK_TZPC 354
-#define PCLK_EDP_CTRL 355
-#define PCLK_MIPI_DSI0 356
-#define PCLK_MIPI_DSI1 357
-#define PCLK_MIPI_CSI 358
-#define PCLK_LVDS_PHY 359
-#define PCLK_HDMI_CTRL 360
-#define PCLK_VIO2_H2P 361
-#define PCLK_CPU 362
-#define PCLK_PERI 363
-#define PCLK_DDRUPCTL0 364
-#define PCLK_PUBL0 365
-#define PCLK_DDRUPCTL1 366
-#define PCLK_PUBL1 367
-#define PCLK_WDT 368
-
-/* hclk gates */
-#define HCLK_GPS 448
-#define HCLK_OTG0 449
-#define HCLK_USBHOST0 450
-#define HCLK_USBHOST1 451
-#define HCLK_HSIC 452
-#define HCLK_NANDC0 453
-#define HCLK_NANDC1 454
-#define HCLK_TSP 455
-#define HCLK_SDMMC 456
-#define HCLK_SDIO0 457
-#define HCLK_SDIO1 458
-#define HCLK_EMMC 459
-#define HCLK_HSADC 460
-#define HCLK_CRYPTO 461
-#define HCLK_I2S0 462
-#define HCLK_SPDIF 463
-#define HCLK_SPDIF8CH 464
-#define HCLK_VOP0 465
-#define HCLK_VOP1 466
-#define HCLK_ROM 467
-#define HCLK_IEP 468
-#define HCLK_ISP 469
-#define HCLK_RGA 470
-#define HCLK_VIO_AHB_ARBI 471
-#define HCLK_VIO_NIU 472
-#define HCLK_VIP 473
-#define HCLK_VIO2_H2P 474
-#define HCLK_HEVC 475
-#define HCLK_VCODEC 476
-#define HCLK_CPU 477
-#define HCLK_PERI 478
-
-#define CLK_NR_CLKS (HCLK_PERI + 1)
-
-/* soft-reset indices */
-#define SRST_CORE0 0
-#define SRST_CORE1 1
-#define SRST_CORE2 2
-#define SRST_CORE3 3
-#define SRST_CORE0_PO 4
-#define SRST_CORE1_PO 5
-#define SRST_CORE2_PO 6
-#define SRST_CORE3_PO 7
-#define SRST_PDCORE_STRSYS 8
-#define SRST_PDBUS_STRSYS 9
-#define SRST_L2C 10
-#define SRST_TOPDBG 11
-#define SRST_CORE0_DBG 12
-#define SRST_CORE1_DBG 13
-#define SRST_CORE2_DBG 14
-#define SRST_CORE3_DBG 15
-
-#define SRST_PDBUG_AHB_ARBITOR 16
-#define SRST_EFUSE256 17
-#define SRST_DMAC1 18
-#define SRST_INTMEM 19
-#define SRST_ROM 20
-#define SRST_SPDIF8CH 21
-#define SRST_TIMER 22
-#define SRST_I2S0 23
-#define SRST_SPDIF 24
-#define SRST_TIMER0 25
-#define SRST_TIMER1 26
-#define SRST_TIMER2 27
-#define SRST_TIMER3 28
-#define SRST_TIMER4 29
-#define SRST_TIMER5 30
-#define SRST_EFUSE 31
-
-#define SRST_GPIO0 32
-#define SRST_GPIO1 33
-#define SRST_GPIO2 34
-#define SRST_GPIO3 35
-#define SRST_GPIO4 36
-#define SRST_GPIO5 37
-#define SRST_GPIO6 38
-#define SRST_GPIO7 39
-#define SRST_GPIO8 40
-#define SRST_I2C0 42
-#define SRST_I2C1 43
-#define SRST_I2C2 44
-#define SRST_I2C3 45
-#define SRST_I2C4 46
-#define SRST_I2C5 47
-
-#define SRST_DWPWM 48
-#define SRST_MMC_PERI 49
-#define SRST_PERIPH_MMU 50
-#define SRST_DAP 51
-#define SRST_DAP_SYS 52
-#define SRST_TPIU 53
-#define SRST_PMU_APB 54
-#define SRST_GRF 55
-#define SRST_PMU 56
-#define SRST_PERIPH_AXI 57
-#define SRST_PERIPH_AHB 58
-#define SRST_PERIPH_APB 59
-#define SRST_PERIPH_NIU 60
-#define SRST_PDPERI_AHB_ARBI 61
-#define SRST_EMEM 62
-#define SRST_USB_PERI 63
-
-#define SRST_DMAC2 64
-#define SRST_MAC 66
-#define SRST_GPS 67
-#define SRST_RKPWM 69
-#define SRST_CCP 71
-#define SRST_USBHOST0 72
-#define SRST_HSIC 73
-#define SRST_HSIC_AUX 74
-#define SRST_HSIC_PHY 75
-#define SRST_HSADC 76
-#define SRST_NANDC0 77
-#define SRST_NANDC1 78
-
-#define SRST_TZPC 80
-#define SRST_SPI0 83
-#define SRST_SPI1 84
-#define SRST_SPI2 85
-#define SRST_SARADC 87
-#define SRST_PDALIVE_NIU 88
-#define SRST_PDPMU_INTMEM 89
-#define SRST_PDPMU_NIU 90
-#define SRST_SGRF 91
-
-#define SRST_VIO_ARBI 96
-#define SRST_RGA_NIU 97
-#define SRST_VIO0_NIU_AXI 98
-#define SRST_VIO_NIU_AHB 99
-#define SRST_LCDC0_AXI 100
-#define SRST_LCDC0_AHB 101
-#define SRST_LCDC0_DCLK 102
-#define SRST_VIO1_NIU_AXI 103
-#define SRST_VIP 104
-#define SRST_RGA_CORE 105
-#define SRST_IEP_AXI 106
-#define SRST_IEP_AHB 107
-#define SRST_RGA_AXI 108
-#define SRST_RGA_AHB 109
-#define SRST_ISP 110
-#define SRST_EDP 111
-
-#define SRST_VCODEC_AXI 112
-#define SRST_VCODEC_AHB 113
-#define SRST_VIO_H2P 114
-#define SRST_MIPIDSI0 115
-#define SRST_MIPIDSI1 116
-#define SRST_MIPICSI 117
-#define SRST_LVDS_PHY 118
-#define SRST_LVDS_CON 119
-#define SRST_GPU 120
-#define SRST_HDMI 121
-#define SRST_CORE_PVTM 124
-#define SRST_GPU_PVTM 125
-
-#define SRST_MMC0 128
-#define SRST_SDIO0 129
-#define SRST_SDIO1 130
-#define SRST_EMMC 131
-#define SRST_USBOTG_AHB 132
-#define SRST_USBOTG_PHY 133
-#define SRST_USBOTG_CON 134
-#define SRST_USBHOST0_AHB 135
-#define SRST_USBHOST0_PHY 136
-#define SRST_USBHOST0_CON 137
-#define SRST_USBHOST1_AHB 138
-#define SRST_USBHOST1_PHY 139
-#define SRST_USBHOST1_CON 140
-#define SRST_USB_ADP 141
-#define SRST_ACC_EFUSE 142
-
-#define SRST_CORESIGHT 144
-#define SRST_PD_CORE_AHB_NOC 145
-#define SRST_PD_CORE_APB_NOC 146
-#define SRST_PD_CORE_MP_AXI 147
-#define SRST_GIC 148
-#define SRST_LCDC_PWM0 149
-#define SRST_LCDC_PWM1 150
-#define SRST_VIO0_H2P_BRG 151
-#define SRST_VIO1_H2P_BRG 152
-#define SRST_RGA_H2P_BRG 153
-#define SRST_HEVC 154
-#define SRST_TSADC 159
-
-#define SRST_DDRPHY0 160
-#define SRST_DDRPHY0_APB 161
-#define SRST_DDRCTRL0 162
-#define SRST_DDRCTRL0_APB 163
-#define SRST_DDRPHY0_CTRL 164
-#define SRST_DDRPHY1 165
-#define SRST_DDRPHY1_APB 166
-#define SRST_DDRCTRL1 167
-#define SRST_DDRCTRL1_APB 168
-#define SRST_DDRPHY1_CTRL 169
-#define SRST_DDRMSCH0 170
-#define SRST_DDRMSCH1 171
-#define SRST_CRYPTO 174
-#define SRST_C2C_HOST 175
-
-#define SRST_LCDC1_AXI 176
-#define SRST_LCDC1_AHB 177
-#define SRST_LCDC1_DCLK 178
-#define SRST_UART0 179
-#define SRST_UART1 180
-#define SRST_UART2 181
-#define SRST_UART3 182
-#define SRST_UART4 183
-#define SRST_SIMC 186
-#define SRST_PS2C 187
-#define SRST_TSP 188
-#define SRST_TSP_CLKIN0 189
-#define SRST_TSP_CLKIN1 190
-#define SRST_TSP_27M 191
diff --git a/include/dt-bindings/clock/rk3328-cru.h b/include/dt-bindings/clock/rk3328-cru.h
deleted file mode 100644
index cde61ed..0000000
--- a/include/dt-bindings/clock/rk3328-cru.h
+++ /dev/null
@@ -1,393 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2016 Rockchip Electronics Co., Ltd
- */
-
-#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3328_H
-#define _DT_BINDINGS_CLK_ROCKCHIP_RK3328_H
-
-/* core clocks */
-#define PLL_APLL 1
-#define PLL_DPLL 2
-#define PLL_CPLL 3
-#define PLL_GPLL 4
-#define PLL_NPLL 5
-#define ARMCLK 6
-
-/* sclk gates (special clocks) */
-#define SCLK_RTC32K 30
-#define SCLK_SDMMC_EXT 31
-#define SCLK_SPI 32
-#define SCLK_SDMMC 33
-#define SCLK_SDIO 34
-#define SCLK_EMMC 35
-#define SCLK_TSADC 36
-#define SCLK_SARADC 37
-#define SCLK_UART0 38
-#define SCLK_UART1 39
-#define SCLK_UART2 40
-#define SCLK_I2S0 41
-#define SCLK_I2S1 42
-#define SCLK_I2S2 43
-#define SCLK_I2S1_OUT 44
-#define SCLK_I2S2_OUT 45
-#define SCLK_SPDIF 46
-#define SCLK_TIMER0 47
-#define SCLK_TIMER1 48
-#define SCLK_TIMER2 49
-#define SCLK_TIMER3 50
-#define SCLK_TIMER4 51
-#define SCLK_TIMER5 52
-#define SCLK_WIFI 53
-#define SCLK_CIF_OUT 54
-#define SCLK_I2C0 55
-#define SCLK_I2C1 56
-#define SCLK_I2C2 57
-#define SCLK_I2C3 58
-#define SCLK_CRYPTO 59
-#define SCLK_PWM 60
-#define SCLK_PDM 61
-#define SCLK_EFUSE 62
-#define SCLK_OTP 63
-#define SCLK_DDRCLK 64
-#define SCLK_VDEC_CABAC 65
-#define SCLK_VDEC_CORE 66
-#define SCLK_VENC_DSP 67
-#define SCLK_VENC_CORE 68
-#define SCLK_RGA 69
-#define SCLK_HDMI_SFC 70
-#define SCLK_HDMI_CEC 71
-#define SCLK_USB3_REF 72
-#define SCLK_USB3_SUSPEND 73
-#define SCLK_SDMMC_DRV 74
-#define SCLK_SDIO_DRV 75
-#define SCLK_EMMC_DRV 76
-#define SCLK_SDMMC_EXT_DRV 77
-#define SCLK_SDMMC_SAMPLE 78
-#define SCLK_SDIO_SAMPLE 79
-#define SCLK_EMMC_SAMPLE 80
-#define SCLK_SDMMC_EXT_SAMPLE 81
-#define SCLK_VOP 82
-#define SCLK_MAC2PHY_RXTX 83
-#define SCLK_MAC2PHY_SRC 84
-#define SCLK_MAC2PHY_REF 85
-#define SCLK_MAC2PHY_OUT 86
-#define SCLK_MAC2IO_RX 87
-#define SCLK_MAC2IO_TX 88
-#define SCLK_MAC2IO_REFOUT 89
-#define SCLK_MAC2IO_REF 90
-#define SCLK_MAC2IO_OUT 91
-#define SCLK_TSP 92
-#define SCLK_HSADC_TSP 93
-#define SCLK_USB3PHY_REF 94
-#define SCLK_REF_USB3OTG 95
-#define SCLK_USB3OTG_REF 96
-#define SCLK_USB3OTG_SUSPEND 97
-#define SCLK_REF_USB3OTG_SRC 98
-#define SCLK_MAC2IO_SRC 99
-#define SCLK_MAC2IO 100
-#define SCLK_MAC2PHY 101
-#define SCLK_MAC2IO_EXT 102
-
-/* dclk gates */
-#define DCLK_LCDC 180
-#define DCLK_HDMIPHY 181
-#define HDMIPHY 182
-#define USB480M 183
-#define DCLK_LCDC_SRC 184
-
-/* aclk gates */
-#define ACLK_AXISRAM 190
-#define ACLK_VOP_PRE 191
-#define ACLK_USB3OTG 192
-#define ACLK_RGA_PRE 193
-#define ACLK_DMAC 194
-#define ACLK_GPU 195
-#define ACLK_BUS_PRE 196
-#define ACLK_PERI_PRE 197
-#define ACLK_RKVDEC_PRE 198
-#define ACLK_RKVDEC 199
-#define ACLK_RKVENC 200
-#define ACLK_VPU_PRE 201
-#define ACLK_VIO_PRE 202
-#define ACLK_VPU 203
-#define ACLK_VIO 204
-#define ACLK_VOP 205
-#define ACLK_GMAC 206
-#define ACLK_H265 207
-#define ACLK_H264 208
-#define ACLK_MAC2PHY 209
-#define ACLK_MAC2IO 210
-#define ACLK_DCF 211
-#define ACLK_TSP 212
-#define ACLK_PERI 213
-#define ACLK_RGA 214
-#define ACLK_IEP 215
-#define ACLK_CIF 216
-#define ACLK_HDCP 217
-
-/* pclk gates */
-#define PCLK_GPIO0 300
-#define PCLK_GPIO1 301
-#define PCLK_GPIO2 302
-#define PCLK_GPIO3 303
-#define PCLK_GRF 304
-#define PCLK_I2C0 305
-#define PCLK_I2C1 306
-#define PCLK_I2C2 307
-#define PCLK_I2C3 308
-#define PCLK_SPI 309
-#define PCLK_UART0 310
-#define PCLK_UART1 311
-#define PCLK_UART2 312
-#define PCLK_TSADC 313
-#define PCLK_PWM 314
-#define PCLK_TIMER 315
-#define PCLK_BUS_PRE 316
-#define PCLK_PERI_PRE 317
-#define PCLK_HDMI_CTRL 318
-#define PCLK_HDMI_PHY 319
-#define PCLK_GMAC 320
-#define PCLK_H265 321
-#define PCLK_MAC2PHY 322
-#define PCLK_MAC2IO 323
-#define PCLK_USB3PHY_OTG 324
-#define PCLK_USB3PHY_PIPE 325
-#define PCLK_USB3_GRF 326
-#define PCLK_USB2_GRF 327
-#define PCLK_HDMIPHY 328
-#define PCLK_DDR 329
-#define PCLK_PERI 330
-#define PCLK_HDMI 331
-#define PCLK_HDCP 332
-#define PCLK_DCF 333
-#define PCLK_SARADC 334
-
-/* hclk gates */
-#define HCLK_PERI 408
-#define HCLK_TSP 409
-#define HCLK_GMAC 410
-#define HCLK_I2S0_8CH 411
-#define HCLK_I2S1_8CH 413
-#define HCLK_I2S2_2CH 413
-#define HCLK_SPDIF_8CH 414
-#define HCLK_VOP 415
-#define HCLK_NANDC 416
-#define HCLK_SDMMC 417
-#define HCLK_SDIO 418
-#define HCLK_EMMC 419
-#define HCLK_SDMMC_EXT 420
-#define HCLK_RKVDEC_PRE 421
-#define HCLK_RKVDEC 422
-#define HCLK_RKVENC 423
-#define HCLK_VPU_PRE 424
-#define HCLK_VIO_PRE 425
-#define HCLK_VPU 426
-#define HCLK_VIO 427
-#define HCLK_BUS_PRE 428
-#define HCLK_PERI_PRE 429
-#define HCLK_H264 430
-#define HCLK_CIF 431
-#define HCLK_OTG_PMU 432
-#define HCLK_OTG 433
-#define HCLK_HOST0 434
-#define HCLK_HOST0_ARB 435
-#define HCLK_CRYPTO_MST 436
-#define HCLK_CRYPTO_SLV 437
-#define HCLK_PDM 438
-#define HCLK_IEP 439
-#define HCLK_RGA 440
-#define HCLK_HDCP 441
-
-#define CLK_NR_CLKS (HCLK_HDCP + 1)
-
-#define CLKGRF_NR_CLKS (SCLK_MAC2PHY + 1)
-
-/* soft-reset indices */
-#define SRST_CORE0_PO 0
-#define SRST_CORE1_PO 1
-#define SRST_CORE2_PO 2
-#define SRST_CORE3_PO 3
-#define SRST_CORE0 4
-#define SRST_CORE1 5
-#define SRST_CORE2 6
-#define SRST_CORE3 7
-#define SRST_CORE0_DBG 8
-#define SRST_CORE1_DBG 9
-#define SRST_CORE2_DBG 10
-#define SRST_CORE3_DBG 11
-#define SRST_TOPDBG 12
-#define SRST_CORE_NIU 13
-#define SRST_STRC_A 14
-#define SRST_L2C 15
-
-#define SRST_A53_GIC 18
-#define SRST_DAP 19
-#define SRST_PMU_P 21
-#define SRST_EFUSE 22
-#define SRST_BUSSYS_H 23
-#define SRST_BUSSYS_P 24
-#define SRST_SPDIF 25
-#define SRST_INTMEM 26
-#define SRST_ROM 27
-#define SRST_GPIO0 28
-#define SRST_GPIO1 29
-#define SRST_GPIO2 30
-#define SRST_GPIO3 31
-
-#define SRST_I2S0 32
-#define SRST_I2S1 33
-#define SRST_I2S2 34
-#define SRST_I2S0_H 35
-#define SRST_I2S1_H 36
-#define SRST_I2S2_H 37
-#define SRST_UART0 38
-#define SRST_UART1 39
-#define SRST_UART2 40
-#define SRST_UART0_P 41
-#define SRST_UART1_P 42
-#define SRST_UART2_P 43
-#define SRST_I2C0 44
-#define SRST_I2C1 45
-#define SRST_I2C2 46
-#define SRST_I2C3 47
-
-#define SRST_I2C0_P 48
-#define SRST_I2C1_P 49
-#define SRST_I2C2_P 50
-#define SRST_I2C3_P 51
-#define SRST_EFUSE_SE_P 52
-#define SRST_EFUSE_NS_P 53
-#define SRST_PWM0 54
-#define SRST_PWM0_P 55
-#define SRST_DMA 56
-#define SRST_TSP_A 57
-#define SRST_TSP_H 58
-#define SRST_TSP 59
-#define SRST_TSP_HSADC 60
-#define SRST_DCF_A 61
-#define SRST_DCF_P 62
-
-#define SRST_SCR 64
-#define SRST_SPI 65
-#define SRST_TSADC 66
-#define SRST_TSADC_P 67
-#define SRST_CRYPTO 68
-#define SRST_SGRF 69
-#define SRST_GRF 70
-#define SRST_USB_GRF 71
-#define SRST_TIMER_6CH_P 72
-#define SRST_TIMER0 73
-#define SRST_TIMER1 74
-#define SRST_TIMER2 75
-#define SRST_TIMER3 76
-#define SRST_TIMER4 77
-#define SRST_TIMER5 78
-#define SRST_USB3GRF 79
-
-#define SRST_PHYNIU 80
-#define SRST_HDMIPHY 81
-#define SRST_VDAC 82
-#define SRST_ACODEC_p 83
-#define SRST_SARADC 85
-#define SRST_SARADC_P 86
-#define SRST_GRF_DDR 87
-#define SRST_DFIMON 88
-#define SRST_MSCH 89
-#define SRST_DDRMSCH 91
-#define SRST_DDRCTRL 92
-#define SRST_DDRCTRL_P 93
-#define SRST_DDRPHY 94
-#define SRST_DDRPHY_P 95
-
-#define SRST_GMAC_NIU_A 96
-#define SRST_GMAC_NIU_P 97
-#define SRST_GMAC2PHY_A 98
-#define SRST_GMAC2IO_A 99
-#define SRST_MACPHY 100
-#define SRST_OTP_PHY 101
-#define SRST_GPU_A 102
-#define SRST_GPU_NIU_A 103
-#define SRST_SDMMCEXT 104
-#define SRST_PERIPH_NIU_A 105
-#define SRST_PERIHP_NIU_H 106
-#define SRST_PERIHP_P 107
-#define SRST_PERIPHSYS_H 108
-#define SRST_MMC0 109
-#define SRST_SDIO 110
-#define SRST_EMMC 111
-
-#define SRST_USB2OTG_H 112
-#define SRST_USB2OTG 113
-#define SRST_USB2OTG_ADP 114
-#define SRST_USB2HOST_H 115
-#define SRST_USB2HOST_ARB 116
-#define SRST_USB2HOST_AUX 117
-#define SRST_USB2HOST_EHCIPHY 118
-#define SRST_USB2HOST_UTMI 119
-#define SRST_USB3OTG 120
-#define SRST_USBPOR 121
-#define SRST_USB2OTG_UTMI 122
-#define SRST_USB2HOST_PHY_UTMI 123
-#define SRST_USB3OTG_UTMI 124
-#define SRST_USB3PHY_U2 125
-#define SRST_USB3PHY_U3 126
-#define SRST_USB3PHY_PIPE 127
-
-#define SRST_VIO_A 128
-#define SRST_VIO_BUS_H 129
-#define SRST_VIO_H2P_H 130
-#define SRST_VIO_ARBI_H 131
-#define SRST_VOP_NIU_A 132
-#define SRST_VOP_A 133
-#define SRST_VOP_H 134
-#define SRST_VOP_D 135
-#define SRST_RGA 136
-#define SRST_RGA_NIU_A 137
-#define SRST_RGA_A 138
-#define SRST_RGA_H 139
-#define SRST_IEP_A 140
-#define SRST_IEP_H 141
-#define SRST_HDMI 142
-#define SRST_HDMI_P 143
-
-#define SRST_HDCP_A 144
-#define SRST_HDCP 145
-#define SRST_HDCP_H 146
-#define SRST_CIF_A 147
-#define SRST_CIF_H 148
-#define SRST_CIF_P 149
-#define SRST_OTP_P 150
-#define SRST_OTP_SBPI 151
-#define SRST_OTP_USER 152
-#define SRST_DDRCTRL_A 153
-#define SRST_DDRSTDY_P 154
-#define SRST_DDRSTDY 155
-#define SRST_PDM_H 156
-#define SRST_PDM 157
-#define SRST_USB3PHY_OTG_P 158
-#define SRST_USB3PHY_PIPE_P 159
-
-#define SRST_VCODEC_A 160
-#define SRST_VCODEC_NIU_A 161
-#define SRST_VCODEC_H 162
-#define SRST_VCODEC_NIU_H 163
-#define SRST_VDEC_A 164
-#define SRST_VDEC_NIU_A 165
-#define SRST_VDEC_H 166
-#define SRST_VDEC_NIU_H 167
-#define SRST_VDEC_CORE 168
-#define SRST_VDEC_CABAC 169
-#define SRST_DDRPHYDIV 175
-
-#define SRST_RKVENC_NIU_A 176
-#define SRST_RKVENC_NIU_H 177
-#define SRST_RKVENC_H265_A 178
-#define SRST_RKVENC_H265_P 179
-#define SRST_RKVENC_H265_CORE 180
-#define SRST_RKVENC_H265_DSP 181
-#define SRST_RKVENC_H264_A 182
-#define SRST_RKVENC_H264_H 183
-#define SRST_RKVENC_INTMEM 184
-
-#endif
diff --git a/include/dt-bindings/clock/rk3368-cru.h b/include/dt-bindings/clock/rk3368-cru.h
deleted file mode 100644
index 9c5dd9b..0000000
--- a/include/dt-bindings/clock/rk3368-cru.h
+++ /dev/null
@@ -1,384 +0,0 @@
-/*
- * Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3368_H
-#define _DT_BINDINGS_CLK_ROCKCHIP_RK3368_H
-
-/* core clocks */
-#define PLL_APLLB 1
-#define PLL_APLLL 2
-#define PLL_DPLL 3
-#define PLL_CPLL 4
-#define PLL_GPLL 5
-#define PLL_NPLL 6
-#define ARMCLKB 7
-#define ARMCLKL 8
-
-/* sclk gates (special clocks) */
-#define SCLK_GPU_CORE 64
-#define SCLK_SPI0 65
-#define SCLK_SPI1 66
-#define SCLK_SPI2 67
-#define SCLK_SDMMC 68
-#define SCLK_SDIO0 69
-#define SCLK_EMMC 71
-#define SCLK_TSADC 72
-#define SCLK_SARADC 73
-#define SCLK_NANDC0 75
-#define SCLK_UART0 77
-#define SCLK_UART1 78
-#define SCLK_UART2 79
-#define SCLK_UART3 80
-#define SCLK_UART4 81
-#define SCLK_I2S_8CH 82
-#define SCLK_SPDIF_8CH 83
-#define SCLK_I2S_2CH 84
-#define SCLK_TIMER0 85
-#define SCLK_TIMER1 86
-#define SCLK_TIMER2 87
-#define SCLK_TIMER3 88
-#define SCLK_TIMER4 89
-#define SCLK_TIMER5 90
-#define SCLK_TIMER6 91
-#define SCLK_OTGPHY0 93
-#define SCLK_OTG_ADP 96
-#define SCLK_HSICPHY480M 97
-#define SCLK_HSICPHY12M 98
-#define SCLK_MACREF 99
-#define SCLK_VOP0_PWM 100
-#define SCLK_MAC_RX 102
-#define SCLK_MAC_TX 103
-#define SCLK_EDP_24M 104
-#define SCLK_EDP 105
-#define SCLK_RGA 106
-#define SCLK_ISP 107
-#define SCLK_HDCP 108
-#define SCLK_HDMI_HDCP 109
-#define SCLK_HDMI_CEC 110
-#define SCLK_HEVC_CABAC 111
-#define SCLK_HEVC_CORE 112
-#define SCLK_I2S_8CH_OUT 113
-#define SCLK_SDMMC_DRV 114
-#define SCLK_SDIO0_DRV 115
-#define SCLK_EMMC_DRV 117
-#define SCLK_SDMMC_SAMPLE 118
-#define SCLK_SDIO0_SAMPLE 119
-#define SCLK_EMMC_SAMPLE 121
-#define SCLK_USBPHY480M 122
-#define SCLK_PVTM_CORE 123
-#define SCLK_PVTM_GPU 124
-#define SCLK_PVTM_PMU 125
-#define SCLK_SFC 126
-#define SCLK_MAC 127
-#define SCLK_MACREF_OUT 128
-
-#define DCLK_VOP 190
-#define MCLK_CRYPTO 191
-
-/* aclk gates */
-#define ACLK_GPU_MEM 192
-#define ACLK_GPU_CFG 193
-#define ACLK_DMAC_BUS 194
-#define ACLK_DMAC_PERI 195
-#define ACLK_PERI_MMU 196
-#define ACLK_GMAC 197
-#define ACLK_VOP 198
-#define ACLK_VOP_IEP 199
-#define ACLK_RGA 200
-#define ACLK_HDCP 201
-#define ACLK_IEP 202
-#define ACLK_VIO0_NOC 203
-#define ACLK_VIP 204
-#define ACLK_ISP 205
-#define ACLK_VIO1_NOC 206
-#define ACLK_VIDEO 208
-#define ACLK_BUS 209
-#define ACLK_PERI 210
-
-/* pclk gates */
-#define PCLK_GPIO0 320
-#define PCLK_GPIO1 321
-#define PCLK_GPIO2 322
-#define PCLK_GPIO3 323
-#define PCLK_PMUGRF 324
-#define PCLK_MAILBOX 325
-#define PCLK_GRF 329
-#define PCLK_SGRF 330
-#define PCLK_PMU 331
-#define PCLK_I2C0 332
-#define PCLK_I2C1 333
-#define PCLK_I2C2 334
-#define PCLK_I2C3 335
-#define PCLK_I2C4 336
-#define PCLK_I2C5 337
-#define PCLK_SPI0 338
-#define PCLK_SPI1 339
-#define PCLK_SPI2 340
-#define PCLK_UART0 341
-#define PCLK_UART1 342
-#define PCLK_UART2 343
-#define PCLK_UART3 344
-#define PCLK_UART4 345
-#define PCLK_TSADC 346
-#define PCLK_SARADC 347
-#define PCLK_SIM 348
-#define PCLK_GMAC 349
-#define PCLK_PWM0 350
-#define PCLK_PWM1 351
-#define PCLK_TIMER0 353
-#define PCLK_TIMER1 354
-#define PCLK_EDP_CTRL 355
-#define PCLK_MIPI_DSI0 356
-#define PCLK_MIPI_CSI 358
-#define PCLK_HDCP 359
-#define PCLK_HDMI_CTRL 360
-#define PCLK_VIO_H2P 361
-#define PCLK_BUS 362
-#define PCLK_PERI 363
-#define PCLK_DDRUPCTL 364
-#define PCLK_DDRPHY 365
-#define PCLK_ISP 366
-#define PCLK_VIP 367
-#define PCLK_WDT 368
-
-/* hclk gates */
-#define HCLK_SFC 448
-#define HCLK_OTG0 449
-#define HCLK_HOST0 450
-#define HCLK_HOST1 451
-#define HCLK_HSIC 452
-#define HCLK_NANDC0 453
-#define HCLK_TSP 455
-#define HCLK_SDMMC 456
-#define HCLK_SDIO0 457
-#define HCLK_EMMC 459
-#define HCLK_HSADC 460
-#define HCLK_CRYPTO 461
-#define HCLK_I2S_2CH 462
-#define HCLK_I2S_8CH 463
-#define HCLK_SPDIF 464
-#define HCLK_VOP 465
-#define HCLK_ROM 467
-#define HCLK_IEP 468
-#define HCLK_ISP 469
-#define HCLK_RGA 470
-#define HCLK_VIO_AHB_ARBI 471
-#define HCLK_VIO_NOC 472
-#define HCLK_VIP 473
-#define HCLK_VIO_H2P 474
-#define HCLK_VIO_HDCPMMU 475
-#define HCLK_VIDEO 476
-#define HCLK_BUS 477
-#define HCLK_PERI 478
-
-#define CLK_NR_CLKS (HCLK_PERI + 1)
-
-/* soft-reset indices */
-#define SRST_CORE_B0 0
-#define SRST_CORE_B1 1
-#define SRST_CORE_B2 2
-#define SRST_CORE_B3 3
-#define SRST_CORE_B0_PO 4
-#define SRST_CORE_B1_PO 5
-#define SRST_CORE_B2_PO 6
-#define SRST_CORE_B3_PO 7
-#define SRST_L2_B 8
-#define SRST_ADB_B 9
-#define SRST_PD_CORE_B_NIU 10
-#define SRST_PDBUS_STRSYS 11
-#define SRST_SOCDBG_B 14
-#define SRST_CORE_B_DBG 15
-
-#define SRST_DMAC1 18
-#define SRST_INTMEM 19
-#define SRST_ROM 20
-#define SRST_SPDIF8CH 21
-#define SRST_I2S8CH 23
-#define SRST_MAILBOX 24
-#define SRST_I2S2CH 25
-#define SRST_EFUSE_256 26
-#define SRST_MCU_SYS 28
-#define SRST_MCU_PO 29
-#define SRST_MCU_NOC 30
-#define SRST_EFUSE 31
-
-#define SRST_GPIO0 32
-#define SRST_GPIO1 33
-#define SRST_GPIO2 34
-#define SRST_GPIO3 35
-#define SRST_GPIO4 36
-#define SRST_PMUGRF 41
-#define SRST_I2C0 42
-#define SRST_I2C1 43
-#define SRST_I2C2 44
-#define SRST_I2C3 45
-#define SRST_I2C4 46
-#define SRST_I2C5 47
-
-#define SRST_DWPWM 48
-#define SRST_MMC_PERI 49
-#define SRST_PERIPH_MMU 50
-#define SRST_GRF 55
-#define SRST_PMU 56
-#define SRST_PERIPH_AXI 57
-#define SRST_PERIPH_AHB 58
-#define SRST_PERIPH_APB 59
-#define SRST_PERIPH_NIU 60
-#define SRST_PDPERI_AHB_ARBI 61
-#define SRST_EMEM 62
-#define SRST_USB_PERI 63
-
-#define SRST_DMAC2 64
-#define SRST_MAC 66
-#define SRST_GPS 67
-#define SRST_RKPWM 69
-#define SRST_USBHOST0 72
-#define SRST_HSIC 73
-#define SRST_HSIC_AUX 74
-#define SRST_HSIC_PHY 75
-#define SRST_HSADC 76
-#define SRST_NANDC0 77
-#define SRST_SFC 79
-
-#define SRST_SPI0 83
-#define SRST_SPI1 84
-#define SRST_SPI2 85
-#define SRST_SARADC 87
-#define SRST_PDALIVE_NIU 88
-#define SRST_PDPMU_INTMEM 89
-#define SRST_PDPMU_NIU 90
-#define SRST_SGRF 91
-
-#define SRST_VIO_ARBI 96
-#define SRST_RGA_NIU 97
-#define SRST_VIO0_NIU_AXI 98
-#define SRST_VIO_NIU_AHB 99
-#define SRST_LCDC0_AXI 100
-#define SRST_LCDC0_AHB 101
-#define SRST_LCDC0_DCLK 102
-#define SRST_VIP 104
-#define SRST_RGA_CORE 105
-#define SRST_IEP_AXI 106
-#define SRST_IEP_AHB 107
-#define SRST_RGA_AXI 108
-#define SRST_RGA_AHB 109
-#define SRST_ISP 110
-#define SRST_EDP_24M 111
-
-#define SRST_VIDEO_AXI 112
-#define SRST_VIDEO_AHB 113
-#define SRST_MIPIDPHYTX 114
-#define SRST_MIPIDSI0 115
-#define SRST_MIPIDPHYRX 116
-#define SRST_MIPICSI 117
-#define SRST_GPU 120
-#define SRST_HDMI 121
-#define SRST_EDP 122
-#define SRST_PMU_PVTM 123
-#define SRST_CORE_PVTM 124
-#define SRST_GPU_PVTM 125
-#define SRST_GPU_SYS 126
-#define SRST_GPU_MEM_NIU 127
-
-#define SRST_MMC0 128
-#define SRST_SDIO0 129
-#define SRST_EMMC 131
-#define SRST_USBOTG_AHB 132
-#define SRST_USBOTG_PHY 133
-#define SRST_USBOTG_CON 134
-#define SRST_USBHOST0_AHB 135
-#define SRST_USBHOST0_PHY 136
-#define SRST_USBHOST0_CON 137
-#define SRST_USBOTG_UTMI 138
-#define SRST_USBHOST1_UTMI 139
-#define SRST_USB_ADP 141
-
-#define SRST_CORESIGHT 144
-#define SRST_PD_CORE_AHB_NOC 145
-#define SRST_PD_CORE_APB_NOC 146
-#define SRST_GIC 148
-#define SRST_LCDC_PWM0 149
-#define SRST_RGA_H2P_BRG 153
-#define SRST_VIDEO 154
-#define SRST_GPU_CFG_NIU 157
-#define SRST_TSADC 159
-
-#define SRST_DDRPHY0 160
-#define SRST_DDRPHY0_APB 161
-#define SRST_DDRCTRL0 162
-#define SRST_DDRCTRL0_APB 163
-#define SRST_VIDEO_NIU 165
-#define SRST_VIDEO_NIU_AHB 167
-#define SRST_DDRMSCH0 170
-#define SRST_PDBUS_AHB 173
-#define SRST_CRYPTO 174
-
-#define SRST_UART0 179
-#define SRST_UART1 180
-#define SRST_UART2 181
-#define SRST_UART3 182
-#define SRST_UART4 183
-#define SRST_SIMC 186
-#define SRST_TSP 188
-#define SRST_TSP_CLKIN0 189
-
-#define SRST_CORE_L0 192
-#define SRST_CORE_L1 193
-#define SRST_CORE_L2 194
-#define SRST_CORE_L3 195
-#define SRST_CORE_L0_PO 195
-#define SRST_CORE_L1_PO 197
-#define SRST_CORE_L2_PO 198
-#define SRST_CORE_L3_PO 199
-#define SRST_L2_L 200
-#define SRST_ADB_L 201
-#define SRST_PD_CORE_L_NIU 202
-#define SRST_CCI_SYS 203
-#define SRST_CCI_DDR 204
-#define SRST_CCI 205
-#define SRST_SOCDBG_L 206
-#define SRST_CORE_L_DBG 207
-
-#define SRST_CORE_B0_NC 208
-#define SRST_CORE_B0_PO_NC 209
-#define SRST_L2_B_NC 210
-#define SRST_ADB_B_NC 211
-#define SRST_PD_CORE_B_NIU_NC 212
-#define SRST_PDBUS_STRSYS_NC 213
-#define SRST_CORE_L0_NC 214
-#define SRST_CORE_L0_PO_NC 215
-#define SRST_L2_L_NC 216
-#define SRST_ADB_L_NC 217
-#define SRST_PD_CORE_L_NIU_NC 218
-#define SRST_CCI_SYS_NC 219
-#define SRST_CCI_DDR_NC 220
-#define SRST_CCI_NC 221
-#define SRST_TRACE_NC 222
-
-#define SRST_TIMER00 224
-#define SRST_TIMER01 225
-#define SRST_TIMER02 226
-#define SRST_TIMER03 227
-#define SRST_TIMER04 228
-#define SRST_TIMER05 229
-#define SRST_TIMER10 230
-#define SRST_TIMER11 231
-#define SRST_TIMER12 232
-#define SRST_TIMER13 233
-#define SRST_TIMER14 234
-#define SRST_TIMER15 235
-#define SRST_TIMER0_APB 236
-#define SRST_TIMER1_APB 237
-
-#endif
diff --git a/include/dt-bindings/clock/rk3399-cru.h b/include/dt-bindings/clock/rk3399-cru.h
deleted file mode 100644
index 211faf8..0000000
--- a/include/dt-bindings/clock/rk3399-cru.h
+++ /dev/null
@@ -1,749 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (c) 2016 Rockchip Electronics Co. Ltd.
- */
-
-#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3399_H
-#define _DT_BINDINGS_CLK_ROCKCHIP_RK3399_H
-
-/* core clocks */
-#define PLL_APLLL 1
-#define PLL_APLLB 2
-#define PLL_DPLL 3
-#define PLL_CPLL 4
-#define PLL_GPLL 5
-#define PLL_NPLL 6
-#define PLL_VPLL 7
-#define ARMCLKL 8
-#define ARMCLKB 9
-
-/* sclk gates (special clocks) */
-#define SCLK_I2C1 65
-#define SCLK_I2C2 66
-#define SCLK_I2C3 67
-#define SCLK_I2C5 68
-#define SCLK_I2C6 69
-#define SCLK_I2C7 70
-#define SCLK_SPI0 71
-#define SCLK_SPI1 72
-#define SCLK_SPI2 73
-#define SCLK_SPI4 74
-#define SCLK_SPI5 75
-#define SCLK_SDMMC 76
-#define SCLK_SDIO 77
-#define SCLK_EMMC 78
-#define SCLK_TSADC 79
-#define SCLK_SARADC 80
-#define SCLK_UART0 81
-#define SCLK_UART1 82
-#define SCLK_UART2 83
-#define SCLK_UART3 84
-#define SCLK_SPDIF_8CH 85
-#define SCLK_I2S0_8CH 86
-#define SCLK_I2S1_8CH 87
-#define SCLK_I2S2_8CH 88
-#define SCLK_I2S_8CH_OUT 89
-#define SCLK_TIMER00 90
-#define SCLK_TIMER01 91
-#define SCLK_TIMER02 92
-#define SCLK_TIMER03 93
-#define SCLK_TIMER04 94
-#define SCLK_TIMER05 95
-#define SCLK_TIMER06 96
-#define SCLK_TIMER07 97
-#define SCLK_TIMER08 98
-#define SCLK_TIMER09 99
-#define SCLK_TIMER10 100
-#define SCLK_TIMER11 101
-#define SCLK_MACREF 102
-#define SCLK_MAC_RX 103
-#define SCLK_MAC_TX 104
-#define SCLK_MAC 105
-#define SCLK_MACREF_OUT 106
-#define SCLK_VOP0_PWM 107
-#define SCLK_VOP1_PWM 108
-#define SCLK_RGA_CORE 109
-#define SCLK_ISP0 110
-#define SCLK_ISP1 111
-#define SCLK_HDMI_CEC 112
-#define SCLK_HDMI_SFR 113
-#define SCLK_DP_CORE 114
-#define SCLK_PVTM_CORE_L 115
-#define SCLK_PVTM_CORE_B 116
-#define SCLK_PVTM_GPU 117
-#define SCLK_PVTM_DDR 118
-#define SCLK_MIPIDPHY_REF 119
-#define SCLK_MIPIDPHY_CFG 120
-#define SCLK_HSICPHY 121
-#define SCLK_USBPHY480M 122
-#define SCLK_USB2PHY0_REF 123
-#define SCLK_USB2PHY1_REF 124
-#define SCLK_UPHY0_TCPDPHY_REF 125
-#define SCLK_UPHY0_TCPDCORE 126
-#define SCLK_UPHY1_TCPDPHY_REF 127
-#define SCLK_UPHY1_TCPDCORE 128
-#define SCLK_USB3OTG0_REF 129
-#define SCLK_USB3OTG1_REF 130
-#define SCLK_USB3OTG0_SUSPEND 131
-#define SCLK_USB3OTG1_SUSPEND 132
-#define SCLK_CRYPTO0 133
-#define SCLK_CRYPTO1 134
-#define SCLK_CCI_TRACE 135
-#define SCLK_CS 136
-#define SCLK_CIF_OUT 137
-#define SCLK_PCIEPHY_REF 138
-#define SCLK_PCIE_CORE 139
-#define SCLK_M0_PERILP 140
-#define SCLK_M0_PERILP_DEC 141
-#define SCLK_CM0S 142
-#define SCLK_DBG_NOC 143
-#define SCLK_DBG_PD_CORE_B 144
-#define SCLK_DBG_PD_CORE_L 145
-#define SCLK_DFIMON0_TIMER 146
-#define SCLK_DFIMON1_TIMER 147
-#define SCLK_INTMEM0 148
-#define SCLK_INTMEM1 149
-#define SCLK_INTMEM2 150
-#define SCLK_INTMEM3 151
-#define SCLK_INTMEM4 152
-#define SCLK_INTMEM5 153
-#define SCLK_SDMMC_DRV 154
-#define SCLK_SDMMC_SAMPLE 155
-#define SCLK_SDIO_DRV 156
-#define SCLK_SDIO_SAMPLE 157
-#define SCLK_VDU_CORE 158
-#define SCLK_VDU_CA 159
-#define SCLK_PCIE_PM 160
-#define SCLK_SPDIF_REC_DPTX 161
-#define SCLK_DPHY_PLL 162
-#define SCLK_DPHY_TX0_CFG 163
-#define SCLK_DPHY_TX1RX1_CFG 164
-#define SCLK_DPHY_RX0_CFG 165
-#define SCLK_RMII_SRC 166
-#define SCLK_PCIEPHY_REF100M 167
-#define SCLK_USBPHY0_480M_SRC 168
-#define SCLK_USBPHY1_480M_SRC 169
-#define SCLK_DDRCLK 170
-#define SCLK_TESTOUT2 171
-
-#define DCLK_VOP0 180
-#define DCLK_VOP1 181
-#define DCLK_VOP0_DIV 182
-#define DCLK_VOP1_DIV 183
-#define DCLK_M0_PERILP 184
-
-#define FCLK_CM0S 190
-
-/* aclk gates */
-#define ACLK_PERIHP 192
-#define ACLK_PERIHP_NOC 193
-#define ACLK_PERILP0 194
-#define ACLK_PERILP0_NOC 195
-#define ACLK_PERF_PCIE 196
-#define ACLK_PCIE 197
-#define ACLK_INTMEM 198
-#define ACLK_TZMA 199
-#define ACLK_DCF 200
-#define ACLK_CCI 201
-#define ACLK_CCI_NOC0 202
-#define ACLK_CCI_NOC1 203
-#define ACLK_CCI_GRF 204
-#define ACLK_CENTER 205
-#define ACLK_CENTER_MAIN_NOC 206
-#define ACLK_CENTER_PERI_NOC 207
-#define ACLK_GPU 208
-#define ACLK_PERF_GPU 209
-#define ACLK_GPU_GRF 210
-#define ACLK_DMAC0_PERILP 211
-#define ACLK_DMAC1_PERILP 212
-#define ACLK_GMAC 213
-#define ACLK_GMAC_NOC 214
-#define ACLK_PERF_GMAC 215
-#define ACLK_VOP0_NOC 216
-#define ACLK_VOP0 217
-#define ACLK_VOP1_NOC 218
-#define ACLK_VOP1 219
-#define ACLK_RGA 220
-#define ACLK_RGA_NOC 221
-#define ACLK_HDCP 222
-#define ACLK_HDCP_NOC 223
-#define ACLK_HDCP22 224
-#define ACLK_IEP 225
-#define ACLK_IEP_NOC 226
-#define ACLK_VIO 227
-#define ACLK_VIO_NOC 228
-#define ACLK_ISP0 229
-#define ACLK_ISP1 230
-#define ACLK_ISP0_NOC 231
-#define ACLK_ISP1_NOC 232
-#define ACLK_ISP0_WRAPPER 233
-#define ACLK_ISP1_WRAPPER 234
-#define ACLK_VCODEC 235
-#define ACLK_VCODEC_NOC 236
-#define ACLK_VDU 237
-#define ACLK_VDU_NOC 238
-#define ACLK_PERI 239
-#define ACLK_EMMC 240
-#define ACLK_EMMC_CORE 241
-#define ACLK_EMMC_NOC 242
-#define ACLK_EMMC_GRF 243
-#define ACLK_USB3 244
-#define ACLK_USB3_NOC 245
-#define ACLK_USB3OTG0 246
-#define ACLK_USB3OTG1 247
-#define ACLK_USB3_RKSOC_AXI_PERF 248
-#define ACLK_USB3_GRF 249
-#define ACLK_GIC 250
-#define ACLK_GIC_NOC 251
-#define ACLK_GIC_ADB400_CORE_L_2_GIC 252
-#define ACLK_GIC_ADB400_CORE_B_2_GIC 253
-#define ACLK_GIC_ADB400_GIC_2_CORE_L 254
-#define ACLK_GIC_ADB400_GIC_2_CORE_B 255
-#define ACLK_CORE_ADB400_CORE_L_2_CCI500 256
-#define ACLK_CORE_ADB400_CORE_B_2_CCI500 257
-#define ACLK_ADB400M_PD_CORE_L 258
-#define ACLK_ADB400M_PD_CORE_B 259
-#define ACLK_PERF_CORE_L 260
-#define ACLK_PERF_CORE_B 261
-#define ACLK_GIC_PRE 262
-#define ACLK_VOP0_PRE 263
-#define ACLK_VOP1_PRE 264
-
-/* pclk gates */
-#define PCLK_PERIHP 320
-#define PCLK_PERIHP_NOC 321
-#define PCLK_PERILP0 322
-#define PCLK_PERILP1 323
-#define PCLK_PERILP1_NOC 324
-#define PCLK_PERILP_SGRF 325
-#define PCLK_PERIHP_GRF 326
-#define PCLK_PCIE 327
-#define PCLK_SGRF 328
-#define PCLK_INTR_ARB 329
-#define PCLK_CENTER_MAIN_NOC 330
-#define PCLK_CIC 331
-#define PCLK_COREDBG_B 332
-#define PCLK_COREDBG_L 333
-#define PCLK_DBG_CXCS_PD_CORE_B 334
-#define PCLK_DCF 335
-#define PCLK_GPIO2 336
-#define PCLK_GPIO3 337
-#define PCLK_GPIO4 338
-#define PCLK_GRF 339
-#define PCLK_HSICPHY 340
-#define PCLK_I2C1 341
-#define PCLK_I2C2 342
-#define PCLK_I2C3 343
-#define PCLK_I2C5 344
-#define PCLK_I2C6 345
-#define PCLK_I2C7 346
-#define PCLK_SPI0 347
-#define PCLK_SPI1 348
-#define PCLK_SPI2 349
-#define PCLK_SPI4 350
-#define PCLK_SPI5 351
-#define PCLK_UART0 352
-#define PCLK_UART1 353
-#define PCLK_UART2 354
-#define PCLK_UART3 355
-#define PCLK_TSADC 356
-#define PCLK_SARADC 357
-#define PCLK_GMAC 358
-#define PCLK_GMAC_NOC 359
-#define PCLK_TIMER0 360
-#define PCLK_TIMER1 361
-#define PCLK_EDP 362
-#define PCLK_EDP_NOC 363
-#define PCLK_EDP_CTRL 364
-#define PCLK_VIO 365
-#define PCLK_VIO_NOC 366
-#define PCLK_VIO_GRF 367
-#define PCLK_MIPI_DSI0 368
-#define PCLK_MIPI_DSI1 369
-#define PCLK_HDCP 370
-#define PCLK_HDCP_NOC 371
-#define PCLK_HDMI_CTRL 372
-#define PCLK_DP_CTRL 373
-#define PCLK_HDCP22 374
-#define PCLK_GASKET 375
-#define PCLK_DDR 376
-#define PCLK_DDR_MON 377
-#define PCLK_DDR_SGRF 378
-#define PCLK_ISP1_WRAPPER 379
-#define PCLK_WDT 380
-#define PCLK_EFUSE1024NS 381
-#define PCLK_EFUSE1024S 382
-#define PCLK_PMU_INTR_ARB 383
-#define PCLK_MAILBOX0 384
-#define PCLK_USBPHY_MUX_G 385
-#define PCLK_UPHY0_TCPHY_G 386
-#define PCLK_UPHY0_TCPD_G 387
-#define PCLK_UPHY1_TCPHY_G 388
-#define PCLK_UPHY1_TCPD_G 389
-#define PCLK_ALIVE 390
-
-/* hclk gates */
-#define HCLK_PERIHP 448
-#define HCLK_PERILP0 449
-#define HCLK_PERILP1 450
-#define HCLK_PERILP0_NOC 451
-#define HCLK_PERILP1_NOC 452
-#define HCLK_M0_PERILP 453
-#define HCLK_M0_PERILP_NOC 454
-#define HCLK_AHB1TOM 455
-#define HCLK_HOST0 456
-#define HCLK_HOST0_ARB 457
-#define HCLK_HOST1 458
-#define HCLK_HOST1_ARB 459
-#define HCLK_HSIC 460
-#define HCLK_SD 461
-#define HCLK_SDMMC 462
-#define HCLK_SDMMC_NOC 463
-#define HCLK_M_CRYPTO0 464
-#define HCLK_M_CRYPTO1 465
-#define HCLK_S_CRYPTO0 466
-#define HCLK_S_CRYPTO1 467
-#define HCLK_I2S0_8CH 468
-#define HCLK_I2S1_8CH 469
-#define HCLK_I2S2_8CH 470
-#define HCLK_SPDIF 471
-#define HCLK_VOP0_NOC 472
-#define HCLK_VOP0 473
-#define HCLK_VOP1_NOC 474
-#define HCLK_VOP1 475
-#define HCLK_ROM 476
-#define HCLK_IEP 477
-#define HCLK_IEP_NOC 478
-#define HCLK_ISP0 479
-#define HCLK_ISP1 480
-#define HCLK_ISP0_NOC 481
-#define HCLK_ISP1_NOC 482
-#define HCLK_ISP0_WRAPPER 483
-#define HCLK_ISP1_WRAPPER 484
-#define HCLK_RGA 485
-#define HCLK_RGA_NOC 486
-#define HCLK_HDCP 487
-#define HCLK_HDCP_NOC 488
-#define HCLK_HDCP22 489
-#define HCLK_VCODEC 490
-#define HCLK_VCODEC_NOC 491
-#define HCLK_VDU 492
-#define HCLK_VDU_NOC 493
-#define HCLK_SDIO 494
-#define HCLK_SDIO_NOC 495
-#define HCLK_SDIOAUDIO_NOC 496
-
-#define CLK_NR_CLKS (HCLK_SDIOAUDIO_NOC + 1)
-
-/* pmu-clocks indices */
-
-#define PLL_PPLL 1
-
-#define SCLK_32K_SUSPEND_PMU 2
-#define SCLK_SPI3_PMU 3
-#define SCLK_TIMER12_PMU 4
-#define SCLK_TIMER13_PMU 5
-#define SCLK_UART4_PMU 6
-#define SCLK_PVTM_PMU 7
-#define SCLK_WIFI_PMU 8
-#define SCLK_I2C0_PMU 9
-#define SCLK_I2C4_PMU 10
-#define SCLK_I2C8_PMU 11
-
-#define PCLK_SRC_PMU 19
-#define PCLK_PMU 20
-#define PCLK_PMUGRF_PMU 21
-#define PCLK_INTMEM1_PMU 22
-#define PCLK_GPIO0_PMU 23
-#define PCLK_GPIO1_PMU 24
-#define PCLK_SGRF_PMU 25
-#define PCLK_NOC_PMU 26
-#define PCLK_I2C0_PMU 27
-#define PCLK_I2C4_PMU 28
-#define PCLK_I2C8_PMU 29
-#define PCLK_RKPWM_PMU 30
-#define PCLK_SPI3_PMU 31
-#define PCLK_TIMER_PMU 32
-#define PCLK_MAILBOX_PMU 33
-#define PCLK_UART4_PMU 34
-#define PCLK_WDT_M0_PMU 35
-
-#define FCLK_CM0S_SRC_PMU 44
-#define FCLK_CM0S_PMU 45
-#define SCLK_CM0S_PMU 46
-#define HCLK_CM0S_PMU 47
-#define DCLK_CM0S_PMU 48
-#define PCLK_INTR_ARB_PMU 49
-#define HCLK_NOC_PMU 50
-
-#define CLKPMU_NR_CLKS (HCLK_NOC_PMU + 1)
-
-/* soft-reset indices */
-
-/* cru_softrst_con0 */
-#define SRST_CORE_L0 0
-#define SRST_CORE_B0 1
-#define SRST_CORE_PO_L0 2
-#define SRST_CORE_PO_B0 3
-#define SRST_L2_L 4
-#define SRST_L2_B 5
-#define SRST_ADB_L 6
-#define SRST_ADB_B 7
-#define SRST_A_CCI 8
-#define SRST_A_CCIM0_NOC 9
-#define SRST_A_CCIM1_NOC 10
-#define SRST_DBG_NOC 11
-
-/* cru_softrst_con1 */
-#define SRST_CORE_L0_T 16
-#define SRST_CORE_L1 17
-#define SRST_CORE_L2 18
-#define SRST_CORE_L3 19
-#define SRST_CORE_PO_L0_T 20
-#define SRST_CORE_PO_L1 21
-#define SRST_CORE_PO_L2 22
-#define SRST_CORE_PO_L3 23
-#define SRST_A_ADB400_GIC2COREL 24
-#define SRST_A_ADB400_COREL2GIC 25
-#define SRST_P_DBG_L 26
-#define SRST_L2_L_T 28
-#define SRST_ADB_L_T 29
-#define SRST_A_RKPERF_L 30
-#define SRST_PVTM_CORE_L 31
-
-/* cru_softrst_con2 */
-#define SRST_CORE_B0_T 32
-#define SRST_CORE_B1 33
-#define SRST_CORE_PO_B0_T 36
-#define SRST_CORE_PO_B1 37
-#define SRST_A_ADB400_GIC2COREB 40
-#define SRST_A_ADB400_COREB2GIC 41
-#define SRST_P_DBG_B 42
-#define SRST_L2_B_T 43
-#define SRST_ADB_B_T 45
-#define SRST_A_RKPERF_B 46
-#define SRST_PVTM_CORE_B 47
-
-/* cru_softrst_con3 */
-#define SRST_A_CCI_T 50
-#define SRST_A_CCIM0_NOC_T 51
-#define SRST_A_CCIM1_NOC_T 52
-#define SRST_A_ADB400M_PD_CORE_B_T 53
-#define SRST_A_ADB400M_PD_CORE_L_T 54
-#define SRST_DBG_NOC_T 55
-#define SRST_DBG_CXCS 56
-#define SRST_CCI_TRACE 57
-#define SRST_P_CCI_GRF 58
-
-/* cru_softrst_con4 */
-#define SRST_A_CENTER_MAIN_NOC 64
-#define SRST_A_CENTER_PERI_NOC 65
-#define SRST_P_CENTER_MAIN 66
-#define SRST_P_DDRMON 67
-#define SRST_P_CIC 68
-#define SRST_P_CENTER_SGRF 69
-#define SRST_DDR0_MSCH 70
-#define SRST_DDRCFG0_MSCH 71
-#define SRST_DDR0 72
-#define SRST_DDRPHY0 73
-#define SRST_DDR1_MSCH 74
-#define SRST_DDRCFG1_MSCH 75
-#define SRST_DDR1 76
-#define SRST_DDRPHY1 77
-#define SRST_DDR_CIC 78
-#define SRST_PVTM_DDR 79
-
-/* cru_softrst_con5 */
-#define SRST_A_VCODEC_NOC 80
-#define SRST_A_VCODEC 81
-#define SRST_H_VCODEC_NOC 82
-#define SRST_H_VCODEC 83
-#define SRST_A_VDU_NOC 88
-#define SRST_A_VDU 89
-#define SRST_H_VDU_NOC 90
-#define SRST_H_VDU 91
-#define SRST_VDU_CORE 92
-#define SRST_VDU_CA 93
-
-/* cru_softrst_con6 */
-#define SRST_A_IEP_NOC 96
-#define SRST_A_VOP_IEP 97
-#define SRST_A_IEP 98
-#define SRST_H_IEP_NOC 99
-#define SRST_H_IEP 100
-#define SRST_A_RGA_NOC 102
-#define SRST_A_RGA 103
-#define SRST_H_RGA_NOC 104
-#define SRST_H_RGA 105
-#define SRST_RGA_CORE 106
-#define SRST_EMMC_NOC 108
-#define SRST_EMMC 109
-#define SRST_EMMC_GRF 110
-
-/* cru_softrst_con7 */
-#define SRST_A_PERIHP_NOC 112
-#define SRST_P_PERIHP_GRF 113
-#define SRST_H_PERIHP_NOC 114
-#define SRST_USBHOST0 115
-#define SRST_HOSTC0_AUX 116
-#define SRST_HOST0_ARB 117
-#define SRST_USBHOST1 118
-#define SRST_HOSTC1_AUX 119
-#define SRST_HOST1_ARB 120
-#define SRST_SDIO0 121
-#define SRST_SDMMC 122
-#define SRST_HSIC 123
-#define SRST_HSIC_AUX 124
-#define SRST_AHB1TOM 125
-#define SRST_P_PERIHP_NOC 126
-#define SRST_HSICPHY 127
-
-/* cru_softrst_con8 */
-#define SRST_A_PCIE 128
-#define SRST_P_PCIE 129
-#define SRST_PCIE_CORE 130
-#define SRST_PCIE_MGMT 131
-#define SRST_PCIE_MGMT_STICKY 132
-#define SRST_PCIE_PIPE 133
-#define SRST_PCIE_PM 134
-#define SRST_PCIEPHY 135
-#define SRST_A_GMAC_NOC 136
-#define SRST_A_GMAC 137
-#define SRST_P_GMAC_NOC 138
-#define SRST_P_GMAC_GRF 140
-#define SRST_HSICPHY_POR 142
-#define SRST_HSICPHY_UTMI 143
-
-/* cru_softrst_con9 */
-#define SRST_USB2PHY0_POR 144
-#define SRST_USB2PHY0_UTMI_PORT0 145
-#define SRST_USB2PHY0_UTMI_PORT1 146
-#define SRST_USB2PHY0_EHCIPHY 147
-#define SRST_UPHY0_PIPE_L00 148
-#define SRST_UPHY0 149
-#define SRST_UPHY0_TCPDPWRUP 150
-#define SRST_USB2PHY1_POR 152
-#define SRST_USB2PHY1_UTMI_PORT0 153
-#define SRST_USB2PHY1_UTMI_PORT1 154
-#define SRST_USB2PHY1_EHCIPHY 155
-#define SRST_UPHY1_PIPE_L00 156
-#define SRST_UPHY1 157
-#define SRST_UPHY1_TCPDPWRUP 158
-
-/* cru_softrst_con10 */
-#define SRST_A_PERILP0_NOC 160
-#define SRST_A_DCF 161
-#define SRST_GIC500 162
-#define SRST_DMAC0_PERILP0 163
-#define SRST_DMAC1_PERILP0 164
-#define SRST_TZMA 165
-#define SRST_INTMEM 166
-#define SRST_ADB400_MST0 167
-#define SRST_ADB400_MST1 168
-#define SRST_ADB400_SLV0 169
-#define SRST_ADB400_SLV1 170
-#define SRST_H_PERILP0 171
-#define SRST_H_PERILP0_NOC 172
-#define SRST_ROM 173
-#define SRST_CRYPTO_S 174
-#define SRST_CRYPTO_M 175
-
-/* cru_softrst_con11 */
-#define SRST_P_DCF 176
-#define SRST_CM0S_NOC 177
-#define SRST_CM0S 178
-#define SRST_CM0S_DBG 179
-#define SRST_CM0S_PO 180
-#define SRST_CRYPTO 181
-#define SRST_P_PERILP1_SGRF 182
-#define SRST_P_PERILP1_GRF 183
-#define SRST_CRYPTO1_S 184
-#define SRST_CRYPTO1_M 185
-#define SRST_CRYPTO1 186
-#define SRST_GIC_NOC 188
-#define SRST_SD_NOC 189
-#define SRST_SDIOAUDIO_BRG 190
-
-/* cru_softrst_con12 */
-#define SRST_H_PERILP1 192
-#define SRST_H_PERILP1_NOC 193
-#define SRST_H_I2S0_8CH 194
-#define SRST_H_I2S1_8CH 195
-#define SRST_H_I2S2_8CH 196
-#define SRST_H_SPDIF_8CH 197
-#define SRST_P_PERILP1_NOC 198
-#define SRST_P_EFUSE_1024 199
-#define SRST_P_EFUSE_1024S 200
-#define SRST_P_I2C0 201
-#define SRST_P_I2C1 202
-#define SRST_P_I2C2 203
-#define SRST_P_I2C3 204
-#define SRST_P_I2C4 205
-#define SRST_P_I2C5 206
-#define SRST_P_MAILBOX0 207
-
-/* cru_softrst_con13 */
-#define SRST_P_UART0 208
-#define SRST_P_UART1 209
-#define SRST_P_UART2 210
-#define SRST_P_UART3 211
-#define SRST_P_SARADC 212
-#define SRST_P_TSADC 213
-#define SRST_P_SPI0 214
-#define SRST_P_SPI1 215
-#define SRST_P_SPI2 216
-#define SRST_P_SPI4 217
-#define SRST_P_SPI5 218
-#define SRST_SPI0 219
-#define SRST_SPI1 220
-#define SRST_SPI2 221
-#define SRST_SPI4 222
-#define SRST_SPI5 223
-
-/* cru_softrst_con14 */
-#define SRST_I2S0_8CH 224
-#define SRST_I2S1_8CH 225
-#define SRST_I2S2_8CH 226
-#define SRST_SPDIF_8CH 227
-#define SRST_UART0 228
-#define SRST_UART1 229
-#define SRST_UART2 230
-#define SRST_UART3 231
-#define SRST_TSADC 232
-#define SRST_I2C0 233
-#define SRST_I2C1 234
-#define SRST_I2C2 235
-#define SRST_I2C3 236
-#define SRST_I2C4 237
-#define SRST_I2C5 238
-#define SRST_SDIOAUDIO_NOC 239
-
-/* cru_softrst_con15 */
-#define SRST_A_VIO_NOC 240
-#define SRST_A_HDCP_NOC 241
-#define SRST_A_HDCP 242
-#define SRST_H_HDCP_NOC 243
-#define SRST_H_HDCP 244
-#define SRST_P_HDCP_NOC 245
-#define SRST_P_HDCP 246
-#define SRST_P_HDMI_CTRL 247
-#define SRST_P_DP_CTRL 248
-#define SRST_S_DP_CTRL 249
-#define SRST_C_DP_CTRL 250
-#define SRST_P_MIPI_DSI0 251
-#define SRST_P_MIPI_DSI1 252
-#define SRST_DP_CORE 253
-#define SRST_DP_I2S 254
-
-/* cru_softrst_con16 */
-#define SRST_GASKET 256
-#define SRST_VIO_GRF 258
-#define SRST_DPTX_SPDIF_REC 259
-#define SRST_HDMI_CTRL 260
-#define SRST_HDCP_CTRL 261
-#define SRST_A_ISP0_NOC 262
-#define SRST_A_ISP1_NOC 263
-#define SRST_H_ISP0_NOC 266
-#define SRST_H_ISP1_NOC 267
-#define SRST_H_ISP0 268
-#define SRST_H_ISP1 269
-#define SRST_ISP0 270
-#define SRST_ISP1 271
-
-/* cru_softrst_con17 */
-#define SRST_A_VOP0_NOC 272
-#define SRST_A_VOP1_NOC 273
-#define SRST_A_VOP0 274
-#define SRST_A_VOP1 275
-#define SRST_H_VOP0_NOC 276
-#define SRST_H_VOP1_NOC 277
-#define SRST_H_VOP0 278
-#define SRST_H_VOP1 279
-#define SRST_D_VOP0 280
-#define SRST_D_VOP1 281
-#define SRST_VOP0_PWM 282
-#define SRST_VOP1_PWM 283
-#define SRST_P_EDP_NOC 284
-#define SRST_P_EDP_CTRL 285
-
-/* cru_softrst_con18 */
-#define SRST_A_GPU 288
-#define SRST_A_GPU_NOC 289
-#define SRST_A_GPU_GRF 290
-#define SRST_PVTM_GPU 291
-#define SRST_A_USB3_NOC 292
-#define SRST_A_USB3_OTG0 293
-#define SRST_A_USB3_OTG1 294
-#define SRST_A_USB3_GRF 295
-#define SRST_PMU 296
-
-/* cru_softrst_con19 */
-#define SRST_P_TIMER0_5 304
-#define SRST_TIMER0 305
-#define SRST_TIMER1 306
-#define SRST_TIMER2 307
-#define SRST_TIMER3 308
-#define SRST_TIMER4 309
-#define SRST_TIMER5 310
-#define SRST_P_TIMER6_11 311
-#define SRST_TIMER6 312
-#define SRST_TIMER7 313
-#define SRST_TIMER8 314
-#define SRST_TIMER9 315
-#define SRST_TIMER10 316
-#define SRST_TIMER11 317
-#define SRST_P_INTR_ARB_PMU 318
-#define SRST_P_ALIVE_SGRF 319
-
-/* cru_softrst_con20 */
-#define SRST_P_GPIO2 320
-#define SRST_P_GPIO3 321
-#define SRST_P_GPIO4 322
-#define SRST_P_GRF 323
-#define SRST_P_ALIVE_NOC 324
-#define SRST_P_WDT0 325
-#define SRST_P_WDT1 326
-#define SRST_P_INTR_ARB 327
-#define SRST_P_UPHY0_DPTX 328
-#define SRST_P_UPHY0_APB 330
-#define SRST_P_UPHY0_TCPHY 332
-#define SRST_P_UPHY1_TCPHY 333
-#define SRST_P_UPHY0_TCPDCTRL 334
-#define SRST_P_UPHY1_TCPDCTRL 335
-
-/* pmu soft-reset indices */
-
-/* pmu_cru_softrst_con0 */
-#define SRST_P_NOC 0
-#define SRST_P_INTMEM 1
-#define SRST_H_CM0S 2
-#define SRST_H_CM0S_NOC 3
-#define SRST_DBG_CM0S 4
-#define SRST_PO_CM0S 5
-#define SRST_P_SPI3 6
-#define SRST_SPI3 7
-#define SRST_P_TIMER_0_1 8
-#define SRST_P_TIMER_0 9
-#define SRST_P_TIMER_1 10
-#define SRST_P_UART4 11
-#define SRST_UART4 12
-#define SRST_P_WDT 13
-
-/* pmu_cru_softrst_con1 */
-#define SRST_P_I2C6 16
-#define SRST_P_I2C7 17
-#define SRST_P_I2C8 18
-#define SRST_P_MAILBOX 19
-#define SRST_P_RKPWM 20
-#define SRST_P_PMUGRF 21
-#define SRST_P_SGRF 22
-#define SRST_P_GPIO0 23
-#define SRST_P_GPIO1 24
-#define SRST_P_CRU 25
-#define SRST_P_INTR 26
-#define SRST_PVTM 27
-#define SRST_I2C6 28
-#define SRST_I2C7 29
-#define SRST_I2C8 30
-
-#endif
diff --git a/include/dt-bindings/clock/rockchip,rk808.h b/include/dt-bindings/clock/rockchip,rk808.h
deleted file mode 100644
index 1a87343..0000000
--- a/include/dt-bindings/clock/rockchip,rk808.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/*
- * This header provides constants clk index RK808 pmic clkout
- */
-#ifndef _CLK_ROCKCHIP_RK808
-#define _CLK_ROCKCHIP_RK808
-
-/* CLOCKOUT index */
-#define RK808_CLKOUT0 0
-#define RK808_CLKOUT1 1
-
-#endif
diff --git a/include/dt-bindings/clock/rv1108-cru.h b/include/dt-bindings/clock/rv1108-cru.h
deleted file mode 100644
index 10ed9d1..0000000
--- a/include/dt-bindings/clock/rv1108-cru.h
+++ /dev/null
@@ -1,356 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (c) 2017 Rockchip Electronics Co. Ltd.
- * Author: Shawn Lin <shawn.lin@rock-chips.com>
- */
-
-#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RV1108_H
-#define _DT_BINDINGS_CLK_ROCKCHIP_RV1108_H
-
-/* pll id */
-#define PLL_APLL 0
-#define PLL_DPLL 1
-#define PLL_GPLL 2
-#define ARMCLK 3
-
-/* sclk gates (special clocks) */
-#define SCLK_SPI0 65
-#define SCLK_NANDC 67
-#define SCLK_SDMMC 68
-#define SCLK_SDIO 69
-#define SCLK_EMMC 71
-#define SCLK_UART0 72
-#define SCLK_UART1 73
-#define SCLK_UART2 74
-#define SCLK_I2S0 75
-#define SCLK_I2S1 76
-#define SCLK_I2S2 77
-#define SCLK_TIMER0 78
-#define SCLK_TIMER1 79
-#define SCLK_SFC 80
-#define SCLK_SDMMC_DRV 81
-#define SCLK_SDIO_DRV 82
-#define SCLK_EMMC_DRV 83
-#define SCLK_SDMMC_SAMPLE 84
-#define SCLK_SDIO_SAMPLE 85
-#define SCLK_EMMC_SAMPLE 86
-#define SCLK_VENC_CORE 87
-#define SCLK_HEVC_CORE 88
-#define SCLK_HEVC_CABAC 89
-#define SCLK_PWM0_PMU 90
-#define SCLK_I2C0_PMU 91
-#define SCLK_WIFI 92
-#define SCLK_CIFOUT 93
-#define SCLK_MIPI_CSI_OUT 94
-#define SCLK_CIF0 95
-#define SCLK_CIF1 96
-#define SCLK_CIF2 97
-#define SCLK_CIF3 98
-#define SCLK_DSP 99
-#define SCLK_DSP_IOP 100
-#define SCLK_DSP_EPP 101
-#define SCLK_DSP_EDP 102
-#define SCLK_DSP_EDAP 103
-#define SCLK_CVBS_HOST 104
-#define SCLK_HDMI_SFR 105
-#define SCLK_HDMI_CEC 106
-#define SCLK_CRYPTO 107
-#define SCLK_SPI 108
-#define SCLK_SARADC 109
-#define SCLK_TSADC 110
-#define SCLK_MAC_PRE 111
-#define SCLK_MAC 112
-#define SCLK_MAC_RX 113
-#define SCLK_MAC_REF 114
-#define SCLK_MAC_REFOUT 115
-#define SCLK_DSP_PFM 116
-#define SCLK_RGA 117
-#define SCLK_I2C1 118
-#define SCLK_I2C2 119
-#define SCLK_I2C3 120
-#define SCLK_PWM 121
-#define SCLK_ISP 122
-#define SCLK_USBPHY 123
-#define SCLK_I2S0_SRC 124
-#define SCLK_I2S1_SRC 125
-#define SCLK_I2S2_SRC 126
-#define SCLK_UART0_SRC 127
-#define SCLK_UART1_SRC 128
-#define SCLK_UART2_SRC 129
-#define SCLK_MAC_TX 130
-#define SCLK_MACREF 131
-#define SCLK_MACREF_OUT 132
-
-#define DCLK_VOP_SRC 185
-#define DCLK_HDMIPHY 186
-#define DCLK_VOP 187
-
-/* aclk gates */
-#define ACLK_DMAC 192
-#define ACLK_PRE 193
-#define ACLK_CORE 194
-#define ACLK_ENMCORE 195
-#define ACLK_RKVENC 196
-#define ACLK_RKVDEC 197
-#define ACLK_VPU 198
-#define ACLK_CIF0 199
-#define ACLK_VIO0 200
-#define ACLK_VIO1 201
-#define ACLK_VOP 202
-#define ACLK_IEP 203
-#define ACLK_RGA 204
-#define ACLK_ISP 205
-#define ACLK_CIF1 206
-#define ACLK_CIF2 207
-#define ACLK_CIF3 208
-#define ACLK_PERI 209
-#define ACLK_GMAC 210
-
-/* pclk gates */
-#define PCLK_GPIO1 256
-#define PCLK_GPIO2 257
-#define PCLK_GPIO3 258
-#define PCLK_GRF 259
-#define PCLK_I2C1 260
-#define PCLK_I2C2 261
-#define PCLK_I2C3 262
-#define PCLK_SPI 263
-#define PCLK_SFC 264
-#define PCLK_UART0 265
-#define PCLK_UART1 266
-#define PCLK_UART2 267
-#define PCLK_TSADC 268
-#define PCLK_PWM 269
-#define PCLK_TIMER 270
-#define PCLK_PERI 271
-#define PCLK_GPIO0_PMU 272
-#define PCLK_I2C0_PMU 273
-#define PCLK_PWM0_PMU 274
-#define PCLK_ISP 275
-#define PCLK_VIO 276
-#define PCLK_MIPI_DSI 277
-#define PCLK_HDMI_CTRL 278
-#define PCLK_SARADC 279
-#define PCLK_DSP_CFG 280
-#define PCLK_BUS 281
-#define PCLK_EFUSE0 282
-#define PCLK_EFUSE1 283
-#define PCLK_WDT 284
-#define PCLK_GMAC 285
-
-/* hclk gates */
-#define HCLK_I2S0_8CH 320
-#define HCLK_I2S1_2CH 321
-#define HCLK_I2S2_2CH 322
-#define HCLK_NANDC 323
-#define HCLK_SDMMC 324
-#define HCLK_SDIO 325
-#define HCLK_EMMC 326
-#define HCLK_PERI 327
-#define HCLK_SFC 328
-#define HCLK_RKVENC 329
-#define HCLK_RKVDEC 330
-#define HCLK_CIF0 331
-#define HCLK_VIO 332
-#define HCLK_VOP 333
-#define HCLK_IEP 334
-#define HCLK_RGA 335
-#define HCLK_ISP 336
-#define HCLK_CRYPTO_MST 337
-#define HCLK_CRYPTO_SLV 338
-#define HCLK_HOST0 339
-#define HCLK_OTG 340
-#define HCLK_CIF1 341
-#define HCLK_CIF2 342
-#define HCLK_CIF3 343
-#define HCLK_BUS 344
-#define HCLK_VPU 345
-
-#define CLK_NR_CLKS (HCLK_VPU + 1)
-
-/* reset id */
-#define SRST_CORE_PO_AD 0
-#define SRST_CORE_AD 1
-#define SRST_L2_AD 2
-#define SRST_CPU_NIU_AD 3
-#define SRST_CORE_PO 4
-#define SRST_CORE 5
-#define SRST_L2 6
-#define SRST_CORE_DBG 8
-#define PRST_DBG 9
-#define RST_DAP 10
-#define PRST_DBG_NIU 11
-#define ARST_STRC_SYS_AD 15
-
-#define SRST_DDRPHY_CLKDIV 16
-#define SRST_DDRPHY 17
-#define PRST_DDRPHY 18
-#define PRST_HDMIPHY 19
-#define PRST_VDACPHY 20
-#define PRST_VADCPHY 21
-#define PRST_MIPI_CSI_PHY 22
-#define PRST_MIPI_DSI_PHY 23
-#define PRST_ACODEC 24
-#define ARST_BUS_NIU 25
-#define PRST_TOP_NIU 26
-#define ARST_INTMEM 27
-#define HRST_ROM 28
-#define ARST_DMAC 29
-#define SRST_MSCH_NIU 30
-#define PRST_MSCH_NIU 31
-
-#define PRST_DDRUPCTL 32
-#define NRST_DDRUPCTL 33
-#define PRST_DDRMON 34
-#define HRST_I2S0_8CH 35
-#define MRST_I2S0_8CH 36
-#define HRST_I2S1_2CH 37
-#define MRST_IS21_2CH 38
-#define HRST_I2S2_2CH 39
-#define MRST_I2S2_2CH 40
-#define HRST_CRYPTO 41
-#define SRST_CRYPTO 42
-#define PRST_SPI 43
-#define SRST_SPI 44
-#define PRST_UART0 45
-#define PRST_UART1 46
-#define PRST_UART2 47
-
-#define SRST_UART0 48
-#define SRST_UART1 49
-#define SRST_UART2 50
-#define PRST_I2C1 51
-#define PRST_I2C2 52
-#define PRST_I2C3 53
-#define SRST_I2C1 54
-#define SRST_I2C2 55
-#define SRST_I2C3 56
-#define PRST_PWM1 58
-#define SRST_PWM1 60
-#define PRST_WDT 61
-#define PRST_GPIO1 62
-#define PRST_GPIO2 63
-
-#define PRST_GPIO3 64
-#define PRST_GRF 65
-#define PRST_EFUSE 66
-#define PRST_EFUSE512 67
-#define PRST_TIMER0 68
-#define SRST_TIMER0 69
-#define SRST_TIMER1 70
-#define PRST_TSADC 71
-#define SRST_TSADC 72
-#define PRST_SARADC 73
-#define SRST_SARADC 74
-#define HRST_SYSBUS 75
-#define PRST_USBGRF 76
-
-#define ARST_PERIPH_NIU 80
-#define HRST_PERIPH_NIU 81
-#define PRST_PERIPH_NIU 82
-#define HRST_PERIPH 83
-#define HRST_SDMMC 84
-#define HRST_SDIO 85
-#define HRST_EMMC 86
-#define HRST_NANDC 87
-#define NRST_NANDC 88
-#define HRST_SFC 89
-#define SRST_SFC 90
-#define ARST_GMAC 91
-#define HRST_OTG 92
-#define SRST_OTG 93
-#define SRST_OTG_ADP 94
-#define HRST_HOST0 95
-
-#define HRST_HOST0_AUX 96
-#define HRST_HOST0_ARB 97
-#define SRST_HOST0_EHCIPHY 98
-#define SRST_HOST0_UTMI 99
-#define SRST_USBPOR 100
-#define SRST_UTMI0 101
-#define SRST_UTMI1 102
-
-#define ARST_VIO0_NIU 102
-#define ARST_VIO1_NIU 103
-#define HRST_VIO_NIU 104
-#define PRST_VIO_NIU 105
-#define ARST_VOP 106
-#define HRST_VOP 107
-#define DRST_VOP 108
-#define ARST_IEP 109
-#define HRST_IEP 110
-#define ARST_RGA 111
-#define HRST_RGA 112
-#define SRST_RGA 113
-#define PRST_CVBS 114
-#define PRST_HDMI 115
-#define SRST_HDMI 116
-#define PRST_MIPI_DSI 117
-
-#define ARST_ISP_NIU 118
-#define HRST_ISP_NIU 119
-#define HRST_ISP 120
-#define SRST_ISP 121
-#define ARST_VIP0 122
-#define HRST_VIP0 123
-#define PRST_VIP0 124
-#define ARST_VIP1 125
-#define HRST_VIP1 126
-#define PRST_VIP1 127
-#define ARST_VIP2 128
-#define HRST_VIP2 129
-#define PRST_VIP2 120
-#define ARST_VIP3 121
-#define HRST_VIP3 122
-#define PRST_VIP4 123
-
-#define PRST_CIF1TO4 124
-#define SRST_CVBS_CLK 125
-#define HRST_CVBS 126
-
-#define ARST_VPU_NIU 140
-#define HRST_VPU_NIU 141
-#define ARST_VPU 142
-#define HRST_VPU 143
-#define ARST_RKVDEC_NIU 144
-#define HRST_RKVDEC_NIU 145
-#define ARST_RKVDEC 146
-#define HRST_RKVDEC 147
-#define SRST_RKVDEC_CABAC 148
-#define SRST_RKVDEC_CORE 149
-#define ARST_RKVENC_NIU 150
-#define HRST_RKVENC_NIU 151
-#define ARST_RKVENC 152
-#define HRST_RKVENC 153
-#define SRST_RKVENC_CORE 154
-
-#define SRST_DSP_CORE 156
-#define SRST_DSP_SYS 157
-#define SRST_DSP_GLOBAL 158
-#define SRST_DSP_OECM 159
-#define PRST_DSP_IOP_NIU 160
-#define ARST_DSP_EPP_NIU 161
-#define ARST_DSP_EDP_NIU 162
-#define PRST_DSP_DBG_NIU 163
-#define PRST_DSP_CFG_NIU 164
-#define PRST_DSP_GRF 165
-#define PRST_DSP_MAILBOX 166
-#define PRST_DSP_INTC 167
-#define PRST_DSP_PFM_MON 169
-#define SRST_DSP_PFM_MON 170
-#define ARST_DSP_EDAP_NIU 171
-
-#define SRST_PMU 172
-#define SRST_PMU_I2C0 173
-#define PRST_PMU_I2C0 174
-#define PRST_PMU_GPIO0 175
-#define PRST_PMU_INTMEM 176
-#define PRST_PMU_PWM0 177
-#define SRST_PMU_PWM0 178
-#define PRST_PMU_GRF 179
-#define SRST_PMU_NIU 180
-#define SRST_PMU_PVTM 181
-#define ARST_DSP_EDP_PERF 184
-#define ARST_DSP_EPP_PERF 185
-
-#endif /* _DT_BINDINGS_CLK_ROCKCHIP_RV1108_H */
diff --git a/include/dt-bindings/clock/s900_cmu.h b/include/dt-bindings/clock/s900_cmu.h
deleted file mode 100644
index 2685a6d..0000000
--- a/include/dt-bindings/clock/s900_cmu.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2015 Actions Semi Co., Ltd.
- * Copyright (C) 2018 Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
- *
- */
-
-#ifndef _DT_BINDINGS_CLOCK_S900_CMU_H_
-#define _DT_BINDINGS_CLOCK_S900_CMU_H_
-
-/* Module Clock ID */
-#define CLOCK_DDRCH1 0
-#define CLOCK_DMAC 1
-#define CLOCK_DDRCH0 2
-#define CLOCK_BROM 3
-#define CLOCK_NANDC0 4
-#define CLOCK_SD0 5
-#define CLOCK_SD1 6
-#define CLOCK_SD2 7
-#define CLOCK_DE 8
-#define CLOCK_LVDS 9
-#define CLOCK_EDP 10
-#define CLOCK_NANDC1 11
-#define CLOCK_DSI 12
-#define CLOCK_CSI0 13
-#define CLOCK_BISP 14
-#define CLOCK_CSI1 15
-#define CLOCK_SD3 16
-#define CLOCK_I2C4 17
-#define CLOCK_GPIO 18
-#define CLOCK_DMM 19
-#define CLOCK_I2STX 20
-#define CLOCK_I2SRX 21
-#define CLOCK_HDMIA 22
-#define CLOCK_SPDIF 23
-#define CLOCK_PCM0 24
-#define CLOCK_VDE 25
-#define CLOCK_VCE 26
-#define CLOCK_HDE 27
-#define CLOCK_SHARESRAM 28
-#define CLOCK_CMU_DDR1 29
-#define CLOCK_GPU3D 30
-#define CLOCK_CMUDDR0 31
-#define CLOCK_SPEED 32
-#define CLOCK_I2C5 33
-#define CLOCK_THERMAL 34
-#define CLOCK_HDMI 35
-#define CLOCK_PWM4 36
-#define CLOCK_PWM5 37
-#define CLOCK_UART0 38
-#define CLOCK_UART1 39
-#define CLOCK_UART2 40
-#define CLOCK_IRC 41
-#define CLOCK_SPI0 42
-#define CLOCK_SPI1 43
-#define CLOCK_SPI2 44
-#define CLOCK_SPI3 45
-#define CLOCK_I2C0 46
-#define CLOCK_I2C1 47
-#define CLOCK_PCM1 48
-#define CLOCK_IMX 49
-#define CLOCK_UART6 50
-#define CLOCK_UART3 51
-#define CLOCK_UART4 52
-#define CLOCK_UART5 53
-#define CLOCK_ETHERNET 54
-#define CLOCK_PWM0 55
-#define CLOCK_PWM1 56
-#define CLOCK_PWM2 57
-#define CLOCK_PWM3 58
-#define CLOCK_TIMER 59
-#define CLOCK_SE 60
-#define CLOCK_HDCP2TX 61
-#define CLOCK_I2C2 62
-#define CLOCK_I2C3 63
-
-#endif
diff --git a/include/dt-bindings/clock/sifive-fu540-prci.h b/include/dt-bindings/clock/sifive-fu540-prci.h
deleted file mode 100644
index 6a0b70a..0000000
--- a/include/dt-bindings/clock/sifive-fu540-prci.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2018-2019 SiFive, Inc.
- * Wesley Terpstra
- * Paul Walmsley
- */
-
-#ifndef __DT_BINDINGS_CLOCK_SIFIVE_FU540_PRCI_H
-#define __DT_BINDINGS_CLOCK_SIFIVE_FU540_PRCI_H
-
-/* Clock indexes for use by Device Tree data and the PRCI driver */
-
-#define PRCI_CLK_COREPLL 0
-#define PRCI_CLK_DDRPLL 1
-#define PRCI_CLK_GEMGXLPLL 2
-#define PRCI_CLK_TLCLK 3
-
-#endif
diff --git a/include/dt-bindings/clock/snps,hsdk-cgu.h b/include/dt-bindings/clock/snps,hsdk-cgu.h
deleted file mode 100644
index 2cfe34e..0000000
--- a/include/dt-bindings/clock/snps,hsdk-cgu.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * Synopsys HSDK SDP CGU clock driver dts bindings
- *
- * Copyright (C) 2017 Synopsys
- * Author: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __DT_BINDINGS_CLK_HSDK_CGU_H_
-#define __DT_BINDINGS_CLK_HSDK_CGU_H_
-
-#define CLK_ARC_PLL 0
-#define CLK_ARC 1
-#define CLK_DDR_PLL 2
-#define CLK_SYS_PLL 3
-#define CLK_SYS_APB 4
-#define CLK_SYS_AXI 5
-#define CLK_SYS_ETH 6
-#define CLK_SYS_USB 7
-#define CLK_SYS_SDIO 8
-#define CLK_SYS_HDMI 9
-#define CLK_SYS_GFX_CORE 10
-#define CLK_SYS_GFX_DMA 11
-#define CLK_SYS_GFX_CFG 12
-#define CLK_SYS_DMAC_CORE 13
-#define CLK_SYS_DMAC_CFG 14
-#define CLK_SYS_SDIO_REF 15
-#define CLK_SYS_SPI_REF 16
-#define CLK_SYS_I2C_REF 17
-#define CLK_SYS_UART_REF 18
-#define CLK_SYS_EBI_REF 19
-#define CLK_TUN_PLL 20
-#define CLK_TUN_TUN 21
-#define CLK_TUN_ROM 22
-#define CLK_TUN_PWM 23
-#define CLK_HDMI_PLL 24
-#define CLK_HDMI 25
-
-#endif /* __DT_BINDINGS_CLK_HSDK_CGU_H_ */
diff --git a/include/dt-bindings/clock/stih407-clks.h b/include/dt-bindings/clock/stih407-clks.h
deleted file mode 100644
index 082edd9..0000000
--- a/include/dt-bindings/clock/stih407-clks.h
+++ /dev/null
@@ -1,90 +0,0 @@
-/*
- * This header provides constants clk index STMicroelectronics
- * STiH407 SoC.
- */
-#ifndef _DT_BINDINGS_CLK_STIH407
-#define _DT_BINDINGS_CLK_STIH407
-
-/* CLOCKGEN A0 */
-#define CLK_IC_LMI0 0
-#define CLK_IC_LMI1 1
-
-/* CLOCKGEN C0 */
-#define CLK_ICN_GPU 0
-#define CLK_FDMA 1
-#define CLK_NAND 2
-#define CLK_HVA 3
-#define CLK_PROC_STFE 4
-#define CLK_PROC_TP 5
-#define CLK_RX_ICN_DMU 6
-#define CLK_RX_ICN_DISP_0 6
-#define CLK_RX_ICN_DISP_1 6
-#define CLK_RX_ICN_HVA 7
-#define CLK_RX_ICN_TS 7
-#define CLK_ICN_CPU 8
-#define CLK_TX_ICN_DMU 9
-#define CLK_TX_ICN_HVA 9
-#define CLK_TX_ICN_TS 9
-#define CLK_ICN_COMPO 9
-#define CLK_MMC_0 10
-#define CLK_MMC_1 11
-#define CLK_JPEGDEC 12
-#define CLK_ICN_REG 13
-#define CLK_TRACE_A9 13
-#define CLK_PTI_STM 13
-#define CLK_EXT2F_A9 13
-#define CLK_IC_BDISP_0 14
-#define CLK_IC_BDISP_1 15
-#define CLK_PP_DMU 16
-#define CLK_VID_DMU 17
-#define CLK_DSS_LPC 18
-#define CLK_ST231_AUD_0 19
-#define CLK_ST231_GP_0 19
-#define CLK_ST231_GP_1 20
-#define CLK_ST231_DMU 21
-#define CLK_ICN_LMI 22
-#define CLK_TX_ICN_DISP_0 23
-#define CLK_TX_ICN_DISP_1 23
-#define CLK_ICN_SBC 24
-#define CLK_STFE_FRC2 25
-#define CLK_ETH_PHY 26
-#define CLK_ETH_REF_PHYCLK 27
-#define CLK_FLASH_PROMIP 28
-#define CLK_MAIN_DISP 29
-#define CLK_AUX_DISP 30
-#define CLK_COMPO_DVP 31
-
-/* CLOCKGEN D0 */
-#define CLK_PCM_0 0
-#define CLK_PCM_1 1
-#define CLK_PCM_2 2
-#define CLK_SPDIFF 3
-
-/* CLOCKGEN D2 */
-#define CLK_PIX_MAIN_DISP 0
-#define CLK_PIX_PIP 1
-#define CLK_PIX_GDP1 2
-#define CLK_PIX_GDP2 3
-#define CLK_PIX_GDP3 4
-#define CLK_PIX_GDP4 5
-#define CLK_PIX_AUX_DISP 6
-#define CLK_DENC 7
-#define CLK_PIX_HDDAC 8
-#define CLK_HDDAC 9
-#define CLK_SDDAC 10
-#define CLK_PIX_DVO 11
-#define CLK_DVO 12
-#define CLK_PIX_HDMI 13
-#define CLK_TMDS_HDMI 14
-#define CLK_REF_HDMIPHY 15
-
-/* CLOCKGEN D3 */
-#define CLK_STFE_FRC1 0
-#define CLK_TSOUT_0 1
-#define CLK_TSOUT_1 2
-#define CLK_MCHI 3
-#define CLK_VSENS_COMPO 4
-#define CLK_FRC1_REMOTE 5
-#define CLK_LPC_0 6
-#define CLK_LPC_1 7
-#endif
diff --git a/include/dt-bindings/clock/stih410-clks.h b/include/dt-bindings/clock/stih410-clks.h
deleted file mode 100644
index 2097a4b..0000000
--- a/include/dt-bindings/clock/stih410-clks.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * This header provides constants clk index STMicroelectronics
- * STiH410 SoC.
- */
-#ifndef _DT_BINDINGS_CLK_STIH410
-#define _DT_BINDINGS_CLK_STIH410
-
-#include "stih407-clks.h"
-
-/* STiH410 introduces new clock outputs compared to STiH407 */
-
-/* CLOCKGEN C0 */
-#define CLK_TX_ICN_HADES 32
-#define CLK_RX_ICN_HADES 33
-#define CLK_ICN_REG_16 34
-#define CLK_PP_HADES 35
-#define CLK_CLUST_HADES 36
-#define CLK_HWPE_HADES 37
-#define CLK_FC_HADES 38
-
-/* CLOCKGEN D0 */
-#define CLK_PCMR10_MASTER 4
-#define CLK_USB2_PHY 5
-
-#endif
diff --git a/include/dt-bindings/clock/stm32fx-clock.h b/include/dt-bindings/clock/stm32fx-clock.h
deleted file mode 100644
index 58d8b51..0000000
--- a/include/dt-bindings/clock/stm32fx-clock.h
+++ /dev/null
@@ -1,60 +0,0 @@
-/*
- * stm32fx-clock.h
- *
- * Copyright (C) 2016 STMicroelectronics
- * Author: Gabriel Fernandez for STMicroelectronics.
- * License terms: GNU General Public License (GPL), version 2
- */
-
-/*
- * List of clocks wich are not derived from system clock (SYSCLOCK)
- *
- * The index of these clocks is the secondary index of DT bindings
- * (see Documentatoin/devicetree/bindings/clock/st,stm32-rcc.txt)
- *
- * e.g:
- <assigned-clocks = <&rcc 1 CLK_LSE>;
-*/
-
-#ifndef _DT_BINDINGS_CLK_STMFX_H
-#define _DT_BINDINGS_CLK_STMFX_H
-
-#define SYSTICK 0
-#define FCLK 1
-#define CLK_LSI 2
-#define CLK_LSE 3
-#define CLK_HSE_RTC 4
-#define CLK_RTC 5
-#define PLL_VCO_I2S 6
-#define PLL_VCO_SAI 7
-#define CLK_LCD 8
-#define CLK_I2S 9
-#define CLK_SAI1 10
-#define CLK_SAI2 11
-#define CLK_I2SQ_PDIV 12
-#define CLK_SAIQ_PDIV 13
-#define CLK_HSI 14
-#define CLK_SYSCLK 15
-#define CLK_F469_DSI 16
-
-#define END_PRIMARY_CLK 17
-
-#define CLK_HDMI_CEC 16
-#define CLK_SPDIF 17
-#define CLK_USART1 18
-#define CLK_USART2 19
-#define CLK_USART3 20
-#define CLK_UART4 21
-#define CLK_UART5 22
-#define CLK_USART6 23
-#define CLK_UART7 24
-#define CLK_UART8 25
-#define CLK_I2C1 26
-#define CLK_I2C2 27
-#define CLK_I2C3 28
-#define CLK_I2C4 29
-#define CLK_LPTIMER 30
-
-#define END_PRIMARY_CLK_F7 31
-
-#endif
diff --git a/include/dt-bindings/clock/stm32h7-clks.h b/include/dt-bindings/clock/stm32h7-clks.h
deleted file mode 100644
index 4d87e7e..0000000
--- a/include/dt-bindings/clock/stm32h7-clks.h
+++ /dev/null
@@ -1,167 +0,0 @@
-/* SYS, CORE AND BUS CLOCKS */
-#define SYS_D1CPRE 0
-#define HCLK 1
-#define PCLK1 2
-#define PCLK2 3
-#define PCLK3 4
-#define PCLK4 5
-#define HSI_DIV 6
-#define HSE_1M 7
-#define I2S_CKIN 8
-#define CK_DSI_PHY 9
-#define HSE_CK 10
-#define LSE_CK 11
-#define CSI_KER_DIV122 12
-#define RTC_CK 13
-#define CPU_SYSTICK 14
-
-/* OSCILLATOR BANK */
-#define OSC_BANK 18
-#define HSI_CK 18
-#define HSI_KER_CK 19
-#define CSI_CK 20
-#define CSI_KER_CK 21
-#define RC48_CK 22
-#define LSI_CK 23
-
-/* MCLOCK BANK */
-#define MCLK_BANK 28
-#define PER_CK 28
-#define PLLSRC 29
-#define SYS_CK 30
-#define TRACEIN_CK 31
-
-/* ODF BANK */
-#define ODF_BANK 32
-#define PLL1_P 32
-#define PLL1_Q 33
-#define PLL1_R 34
-#define PLL2_P 35
-#define PLL2_Q 36
-#define PLL2_R 37
-#define PLL3_P 38
-#define PLL3_Q 39
-#define PLL3_R 40
-
-/* MCO BANK */
-#define MCO_BANK 41
-#define MCO1 41
-#define MCO2 42
-
-/* PERIF BANK */
-#define PERIF_BANK 50
-#define D1SRAM1_CK 50
-#define ITCM_CK 51
-#define DTCM2_CK 52
-#define DTCM1_CK 53
-#define FLITF_CK 54
-#define JPGDEC_CK 55
-#define DMA2D_CK 56
-#define MDMA_CK 57
-#define USB2ULPI_CK 58
-#define USB1ULPI_CK 59
-#define ETH1RX_CK 60
-#define ETH1TX_CK 61
-#define ETH1MAC_CK 62
-#define ART_CK 63
-#define DMA2_CK 64
-#define DMA1_CK 65
-#define D2SRAM3_CK 66
-#define D2SRAM2_CK 67
-#define D2SRAM1_CK 68
-#define HASH_CK 69
-#define CRYPT_CK 70
-#define CAMITF_CK 71
-#define BKPRAM_CK 72
-#define HSEM_CK 73
-#define BDMA_CK 74
-#define CRC_CK 75
-#define GPIOK_CK 76
-#define GPIOJ_CK 77
-#define GPIOI_CK 78
-#define GPIOH_CK 79
-#define GPIOG_CK 80
-#define GPIOF_CK 81
-#define GPIOE_CK 82
-#define GPIOD_CK 83
-#define GPIOC_CK 84
-#define GPIOB_CK 85
-#define GPIOA_CK 86
-#define WWDG1_CK 87
-#define DAC12_CK 88
-#define WWDG2_CK 89
-#define TIM14_CK 90
-#define TIM13_CK 91
-#define TIM12_CK 92
-#define TIM7_CK 93
-#define TIM6_CK 94
-#define TIM5_CK 95
-#define TIM4_CK 96
-#define TIM3_CK 97
-#define TIM2_CK 98
-#define MDIOS_CK 99
-#define OPAMP_CK 100
-#define CRS_CK 101
-#define TIM17_CK 102
-#define TIM16_CK 103
-#define TIM15_CK 104
-#define TIM8_CK 105
-#define TIM1_CK 106
-#define TMPSENS_CK 107
-#define RTCAPB_CK 108
-#define VREF_CK 109
-#define COMP12_CK 110
-#define SYSCFG_CK 111
-/* must be equal to last peripheral clock index */
-#define LAST_PERIF_BANK SYSCFG_CK
-
-/* KERNEL BANK */
-#define KERN_BANK 120
-#define SDMMC1_CK 120
-#define QUADSPI_CK 121
-#define FMC_CK 122
-#define USB2OTG_CK 123
-#define USB1OTG_CK 124
-#define ADC12_CK 125
-#define SDMMC2_CK 126
-#define RNG_CK 127
-#define ADC3_CK 128
-#define DSI_CK 129
-#define LTDC_CK 130
-#define USART8_CK 131
-#define USART7_CK 132
-#define HDMICEC_CK 133
-#define I2C3_CK 134
-#define I2C2_CK 135
-#define I2C1_CK 136
-#define UART5_CK 137
-#define UART4_CK 138
-#define USART3_CK 139
-#define USART2_CK 140
-#define SPDIFRX_CK 141
-#define SPI3_CK 142
-#define SPI2_CK 143
-#define LPTIM1_CK 144
-#define FDCAN_CK 145
-#define SWP_CK 146
-#define HRTIM_CK 147
-#define DFSDM1_CK 148
-#define SAI3_CK 149
-#define SAI2_CK 150
-#define SAI1_CK 151
-#define SPI5_CK 152
-#define SPI4_CK 153
-#define SPI1_CK 154
-#define USART6_CK 155
-#define USART1_CK 156
-#define SAI4B_CK 157
-#define SAI4A_CK 158
-#define LPTIM5_CK 159
-#define LPTIM4_CK 160
-#define LPTIM3_CK 161
-#define LPTIM2_CK 162
-#define I2C4_CK 163
-#define SPI6_CK 164
-#define LPUART1_CK 165
-
-#define STM32H7_MAX_CLKS 166
diff --git a/include/dt-bindings/clock/stm32mp1-clks.h b/include/dt-bindings/clock/stm32mp1-clks.h
deleted file mode 100644
index 4cdaf13..0000000
--- a/include/dt-bindings/clock/stm32mp1-clks.h
+++ /dev/null
@@ -1,251 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */
-/*
- * Copyright (C) STMicroelectronics 2018 - All Rights Reserved
- * Author: Gabriel Fernandez <gabriel.fernandez@st.com> for STMicroelectronics.
- */
-
-#ifndef _DT_BINDINGS_STM32MP1_CLKS_H_
-#define _DT_BINDINGS_STM32MP1_CLKS_H_
-
-/* OSCILLATOR clocks */
-#define CK_HSE 0
-#define CK_CSI 1
-#define CK_LSI 2
-#define CK_LSE 3
-#define CK_HSI 4
-#define CK_HSE_DIV2 5
-
-/* Bus clocks */
-#define TIM2 6
-#define TIM3 7
-#define TIM4 8
-#define TIM5 9
-#define TIM6 10
-#define TIM7 11
-#define TIM12 12
-#define TIM13 13
-#define TIM14 14
-#define LPTIM1 15
-#define SPI2 16
-#define SPI3 17
-#define USART2 18
-#define USART3 19
-#define UART4 20
-#define UART5 21
-#define UART7 22
-#define UART8 23
-#define I2C1 24
-#define I2C2 25
-#define I2C3 26
-#define I2C5 27
-#define SPDIF 28
-#define CEC 29
-#define DAC12 30
-#define MDIO 31
-#define TIM1 32
-#define TIM8 33
-#define TIM15 34
-#define TIM16 35
-#define TIM17 36
-#define SPI1 37
-#define SPI4 38
-#define SPI5 39
-#define USART6 40
-#define SAI1 41
-#define SAI2 42
-#define SAI3 43
-#define DFSDM 44
-#define FDCAN 45
-#define LPTIM2 46
-#define LPTIM3 47
-#define LPTIM4 48
-#define LPTIM5 49
-#define SAI4 50
-#define SYSCFG 51
-#define VREF 52
-#define TMPSENS 53
-#define PMBCTRL 54
-#define HDP 55
-#define LTDC 56
-#define DSI 57
-#define IWDG2 58
-#define USBPHY 59
-#define STGENRO 60
-#define SPI6 61
-#define I2C4 62
-#define I2C6 63
-#define USART1 64
-#define RTCAPB 65
-#define TZC1 66
-#define TZPC 67
-#define IWDG1 68
-#define BSEC 69
-#define STGEN 70
-#define DMA1 71
-#define DMA2 72
-#define DMAMUX 73
-#define ADC12 74
-#define USBO 75
-#define SDMMC3 76
-#define DCMI 77
-#define CRYP2 78
-#define HASH2 79
-#define RNG2 80
-#define CRC2 81
-#define HSEM 82
-#define IPCC 83
-#define GPIOA 84
-#define GPIOB 85
-#define GPIOC 86
-#define GPIOD 87
-#define GPIOE 88
-#define GPIOF 89
-#define GPIOG 90
-#define GPIOH 91
-#define GPIOI 92
-#define GPIOJ 93
-#define GPIOK 94
-#define GPIOZ 95
-#define CRYP1 96
-#define HASH1 97
-#define RNG1 98
-#define BKPSRAM 99
-#define MDMA 100
-#define GPU 101
-#define ETHCK 102
-#define ETHTX 103
-#define ETHRX 104
-#define ETHMAC 105
-#define FMC 106
-#define QSPI 107
-#define SDMMC1 108
-#define SDMMC2 109
-#define CRC1 110
-#define USBH 111
-#define ETHSTP 112
-#define TZC2 113
-
-/* Kernel clocks */
-#define SDMMC1_K 118
-#define SDMMC2_K 119
-#define SDMMC3_K 120
-#define FMC_K 121
-#define QSPI_K 122
-#define ETHCK_K 123
-#define RNG1_K 124
-#define RNG2_K 125
-#define GPU_K 126
-#define USBPHY_K 127
-#define STGEN_K 128
-#define SPDIF_K 129
-#define SPI1_K 130
-#define SPI2_K 131
-#define SPI3_K 132
-#define SPI4_K 133
-#define SPI5_K 134
-#define SPI6_K 135
-#define CEC_K 136
-#define I2C1_K 137
-#define I2C2_K 138
-#define I2C3_K 139
-#define I2C4_K 140
-#define I2C5_K 141
-#define I2C6_K 142
-#define LPTIM1_K 143
-#define LPTIM2_K 144
-#define LPTIM3_K 145
-#define LPTIM4_K 146
-#define LPTIM5_K 147
-#define USART1_K 148
-#define USART2_K 149
-#define USART3_K 150
-#define UART4_K 151
-#define UART5_K 152
-#define USART6_K 153
-#define UART7_K 154
-#define UART8_K 155
-#define DFSDM_K 156
-#define FDCAN_K 157
-#define SAI1_K 158
-#define SAI2_K 159
-#define SAI3_K 160
-#define SAI4_K 161
-#define ADC12_K 162
-#define DSI_K 163
-#define DSI_PX 164
-#define ADFSDM_K 165
-#define USBO_K 166
-#define LTDC_PX 167
-#define DAC12_K 168
-#define ETHPTP_K 169
-
-/* PLL */
-#define PLL1 176
-#define PLL2 177
-#define PLL3 178
-#define PLL4 179
-
-/* ODF */
-#define PLL1_P 180
-#define PLL1_Q 181
-#define PLL1_R 182
-#define PLL2_P 183
-#define PLL2_Q 184
-#define PLL2_R 185
-#define PLL3_P 186
-#define PLL3_Q 187
-#define PLL3_R 188
-#define PLL4_P 189
-#define PLL4_Q 190
-#define PLL4_R 191
-
-/* AUX */
-#define RTC 192
-
-/* MCLK */
-#define CK_PER 193
-#define CK_MPU 194
-#define CK_AXI 195
-#define CK_MCU 196
-
-/* Time base */
-#define TIM2_K 197
-#define TIM3_K 198
-#define TIM4_K 199
-#define TIM5_K 200
-#define TIM6_K 201
-#define TIM7_K 202
-#define TIM12_K 203
-#define TIM13_K 204
-#define TIM14_K 205
-#define TIM1_K 206
-#define TIM8_K 207
-#define TIM15_K 208
-#define TIM16_K 209
-#define TIM17_K 210
-
-/* MCO clocks */
-#define CK_MCO1 211
-#define CK_MCO2 212
-
-/* TRACE & DEBUG clocks */
-#define CK_DBG 214
-#define CK_TRACE 215
-
-/* DDR */
-#define DDRC1 220
-#define DDRC1LP 221
-#define DDRC2 222
-#define DDRC2LP 223
-#define DDRPHYC 224
-#define DDRPHYCLP 225
-#define DDRCAPB 226
-#define DDRCAPBLP 227
-#define AXIDCG 228
-#define DDRPHYCAPB 229
-#define DDRPHYCAPBLP 230
-#define DDRPERFM 231
-
-#define STM32MP1_LAST_CLK 232
-
-#endif /* _DT_BINDINGS_STM32MP1_CLKS_H_ */
diff --git a/include/dt-bindings/clock/stm32mp1-clksrc.h b/include/dt-bindings/clock/stm32mp1-clksrc.h
deleted file mode 100644
index 002ad53..0000000
--- a/include/dt-bindings/clock/stm32mp1-clksrc.h
+++ /dev/null
@@ -1,284 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
-/*
- * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
- *
- */
-
-#ifndef _DT_BINDINGS_CLOCK_STM32MP1_CLKSRC_H_
-#define _DT_BINDINGS_CLOCK_STM32MP1_CLKSRC_H_
-
-/* PLL output is enable when x=1, with x=p,q or r */
-#define PQR(p, q, r) (((p) & 1) | (((q) & 1) << 1) | (((r) & 1) << 2))
-
-/* st,clksrc: mandatory clock source */
-
-#define CLK_MPU_HSI 0x00000200
-#define CLK_MPU_HSE 0x00000201
-#define CLK_MPU_PLL1P 0x00000202
-#define CLK_MPU_PLL1P_DIV 0x00000203
-
-#define CLK_AXI_HSI 0x00000240
-#define CLK_AXI_HSE 0x00000241
-#define CLK_AXI_PLL2P 0x00000242
-
-#define CLK_MCU_HSI 0x00000480
-#define CLK_MCU_HSE 0x00000481
-#define CLK_MCU_CSI 0x00000482
-#define CLK_MCU_PLL3P 0x00000483
-
-#define CLK_PLL12_HSI 0x00000280
-#define CLK_PLL12_HSE 0x00000281
-
-#define CLK_PLL3_HSI 0x00008200
-#define CLK_PLL3_HSE 0x00008201
-#define CLK_PLL3_CSI 0x00008202
-
-#define CLK_PLL4_HSI 0x00008240
-#define CLK_PLL4_HSE 0x00008241
-#define CLK_PLL4_CSI 0x00008242
-#define CLK_PLL4_I2SCKIN 0x00008243
-
-#define CLK_RTC_DISABLED 0x00001400
-#define CLK_RTC_LSE 0x00001401
-#define CLK_RTC_LSI 0x00001402
-#define CLK_RTC_HSE 0x00001403
-
-#define CLK_MCO1_HSI 0x00008000
-#define CLK_MCO1_HSE 0x00008001
-#define CLK_MCO1_CSI 0x00008002
-#define CLK_MCO1_LSI 0x00008003
-#define CLK_MCO1_LSE 0x00008004
-#define CLK_MCO1_DISABLED 0x0000800F
-
-#define CLK_MCO2_MPU 0x00008040
-#define CLK_MCO2_AXI 0x00008041
-#define CLK_MCO2_MCU 0x00008042
-#define CLK_MCO2_PLL4P 0x00008043
-#define CLK_MCO2_HSE 0x00008044
-#define CLK_MCO2_HSI 0x00008045
-#define CLK_MCO2_DISABLED 0x0000804F
-
-/* st,pkcs: peripheral kernel clock source */
-
-#define CLK_I2C12_PCLK1 0x00008C00
-#define CLK_I2C12_PLL4R 0x00008C01
-#define CLK_I2C12_HSI 0x00008C02
-#define CLK_I2C12_CSI 0x00008C03
-#define CLK_I2C12_DISABLED 0x00008C07
-
-#define CLK_I2C35_PCLK1 0x00008C40
-#define CLK_I2C35_PLL4R 0x00008C41
-#define CLK_I2C35_HSI 0x00008C42
-#define CLK_I2C35_CSI 0x00008C43
-#define CLK_I2C35_DISABLED 0x00008C47
-
-#define CLK_I2C46_PCLK5 0x00000C00
-#define CLK_I2C46_PLL3Q 0x00000C01
-#define CLK_I2C46_HSI 0x00000C02
-#define CLK_I2C46_CSI 0x00000C03
-#define CLK_I2C46_DISABLED 0x00000C07
-
-#define CLK_SAI1_PLL4Q 0x00008C80
-#define CLK_SAI1_PLL3Q 0x00008C81
-#define CLK_SAI1_I2SCKIN 0x00008C82
-#define CLK_SAI1_CKPER 0x00008C83
-#define CLK_SAI1_PLL3R 0x00008C84
-#define CLK_SAI1_DISABLED 0x00008C87
-
-#define CLK_SAI2_PLL4Q 0x00008CC0
-#define CLK_SAI2_PLL3Q 0x00008CC1
-#define CLK_SAI2_I2SCKIN 0x00008CC2
-#define CLK_SAI2_CKPER 0x00008CC3
-#define CLK_SAI2_SPDIF 0x00008CC4
-#define CLK_SAI2_PLL3R 0x00008CC5
-#define CLK_SAI2_DISABLED 0x00008CC7
-
-#define CLK_SAI3_PLL4Q 0x00008D00
-#define CLK_SAI3_PLL3Q 0x00008D01
-#define CLK_SAI3_I2SCKIN 0x00008D02
-#define CLK_SAI3_CKPER 0x00008D03
-#define CLK_SAI3_PLL3R 0x00008D04
-#define CLK_SAI3_DISABLED 0x00008D07
-
-#define CLK_SAI4_PLL4Q 0x00008D40
-#define CLK_SAI4_PLL3Q 0x00008D41
-#define CLK_SAI4_I2SCKIN 0x00008D42
-#define CLK_SAI4_CKPER 0x00008D43
-#define CLK_SAI4_PLL3R 0x00008D44
-#define CLK_SAI4_DISABLED 0x00008D47
-
-#define CLK_SPI2S1_PLL4P 0x00008D80
-#define CLK_SPI2S1_PLL3Q 0x00008D81
-#define CLK_SPI2S1_I2SCKIN 0x00008D82
-#define CLK_SPI2S1_CKPER 0x00008D83
-#define CLK_SPI2S1_PLL3R 0x00008D84
-#define CLK_SPI2S1_DISABLED 0x00008D87
-
-#define CLK_SPI2S23_PLL4P 0x00008DC0
-#define CLK_SPI2S23_PLL3Q 0x00008DC1
-#define CLK_SPI2S23_I2SCKIN 0x00008DC2
-#define CLK_SPI2S23_CKPER 0x00008DC3
-#define CLK_SPI2S23_PLL3R 0x00008DC4
-#define CLK_SPI2S23_DISABLED 0x00008DC7
-
-#define CLK_SPI45_PCLK2 0x00008E00
-#define CLK_SPI45_PLL4Q 0x00008E01
-#define CLK_SPI45_HSI 0x00008E02
-#define CLK_SPI45_CSI 0x00008E03
-#define CLK_SPI45_HSE 0x00008E04
-#define CLK_SPI45_DISABLED 0x00008E07
-
-#define CLK_SPI6_PCLK5 0x00000C40
-#define CLK_SPI6_PLL4Q 0x00000C41
-#define CLK_SPI6_HSI 0x00000C42
-#define CLK_SPI6_CSI 0x00000C43
-#define CLK_SPI6_HSE 0x00000C44
-#define CLK_SPI6_PLL3Q 0x00000C45
-#define CLK_SPI6_DISABLED 0x00000C47
-
-#define CLK_UART6_PCLK2 0x00008E40
-#define CLK_UART6_PLL4Q 0x00008E41
-#define CLK_UART6_HSI 0x00008E42
-#define CLK_UART6_CSI 0x00008E43
-#define CLK_UART6_HSE 0x00008E44
-#define CLK_UART6_DISABLED 0x00008E47
-
-#define CLK_UART24_PCLK1 0x00008E80
-#define CLK_UART24_PLL4Q 0x00008E81
-#define CLK_UART24_HSI 0x00008E82
-#define CLK_UART24_CSI 0x00008E83
-#define CLK_UART24_HSE 0x00008E84
-#define CLK_UART24_DISABLED 0x00008E87
-
-#define CLK_UART35_PCLK1 0x00008EC0
-#define CLK_UART35_PLL4Q 0x00008EC1
-#define CLK_UART35_HSI 0x00008EC2
-#define CLK_UART35_CSI 0x00008EC3
-#define CLK_UART35_HSE 0x00008EC4
-#define CLK_UART35_DISABLED 0x00008EC7
-
-#define CLK_UART78_PCLK1 0x00008F00
-#define CLK_UART78_PLL4Q 0x00008F01
-#define CLK_UART78_HSI 0x00008F02
-#define CLK_UART78_CSI 0x00008F03
-#define CLK_UART78_HSE 0x00008F04
-#define CLK_UART78_DISABLED 0x00008F07
-
-#define CLK_UART1_PCLK5 0x00000C80
-#define CLK_UART1_PLL3Q 0x00000C81
-#define CLK_UART1_HSI 0x00000C82
-#define CLK_UART1_CSI 0x00000C83
-#define CLK_UART1_PLL4Q 0x00000C84
-#define CLK_UART1_HSE 0x00000C85
-#define CLK_UART1_DISABLED 0x00000C87
-
-#define CLK_SDMMC12_HCLK6 0x00008F40
-#define CLK_SDMMC12_PLL3R 0x00008F41
-#define CLK_SDMMC12_PLL4P 0x00008F42
-#define CLK_SDMMC12_HSI 0x00008F43
-#define CLK_SDMMC12_DISABLED 0x00008F47
-
-#define CLK_SDMMC3_HCLK2 0x00008F80
-#define CLK_SDMMC3_PLL3R 0x00008F81
-#define CLK_SDMMC3_PLL4P 0x00008F82
-#define CLK_SDMMC3_HSI 0x00008F83
-#define CLK_SDMMC3_DISABLED 0x00008F87
-
-#define CLK_ETH_PLL4P 0x00008FC0
-#define CLK_ETH_PLL3Q 0x00008FC1
-#define CLK_ETH_DISABLED 0x00008FC3
-
-#define CLK_QSPI_ACLK 0x00009000
-#define CLK_QSPI_PLL3R 0x00009001
-#define CLK_QSPI_PLL4P 0x00009002
-#define CLK_QSPI_CKPER 0x00009003
-
-#define CLK_FMC_ACLK 0x00009040
-#define CLK_FMC_PLL3R 0x00009041
-#define CLK_FMC_PLL4P 0x00009042
-#define CLK_FMC_CKPER 0x00009043
-
-#define CLK_FDCAN_HSE 0x000090C0
-#define CLK_FDCAN_PLL3Q 0x000090C1
-#define CLK_FDCAN_PLL4Q 0x000090C2
-#define CLK_FDCAN_PLL4R 0x000090C3
-
-#define CLK_SPDIF_PLL4P 0x00009140
-#define CLK_SPDIF_PLL3Q 0x00009141
-#define CLK_SPDIF_HSI 0x00009142
-#define CLK_SPDIF_DISABLED 0x00009143
-
-#define CLK_CEC_LSE 0x00009180
-#define CLK_CEC_LSI 0x00009181
-#define CLK_CEC_CSI_DIV122 0x00009182
-#define CLK_CEC_DISABLED 0x00009183
-
-#define CLK_USBPHY_HSE 0x000091C0
-#define CLK_USBPHY_PLL4R 0x000091C1
-#define CLK_USBPHY_HSE_DIV2 0x000091C2
-#define CLK_USBPHY_DISABLED 0x000091C3
-
-#define CLK_USBO_PLL4R 0x800091C0
-#define CLK_USBO_USBPHY 0x800091C1
-
-#define CLK_RNG1_CSI 0x00000CC0
-#define CLK_RNG1_PLL4R 0x00000CC1
-#define CLK_RNG1_LSE 0x00000CC2
-#define CLK_RNG1_LSI 0x00000CC3
-
-#define CLK_RNG2_CSI 0x00009200
-#define CLK_RNG2_PLL4R 0x00009201
-#define CLK_RNG2_LSE 0x00009202
-#define CLK_RNG2_LSI 0x00009203
-
-#define CLK_CKPER_HSI 0x00000D00
-#define CLK_CKPER_CSI 0x00000D01
-#define CLK_CKPER_HSE 0x00000D02
-#define CLK_CKPER_DISABLED 0x00000D03
-
-#define CLK_STGEN_HSI 0x00000D40
-#define CLK_STGEN_HSE 0x00000D41
-#define CLK_STGEN_DISABLED 0x00000D43
-
-#define CLK_DSI_DSIPLL 0x00009240
-#define CLK_DSI_PLL4P 0x00009241
-
-#define CLK_ADC_PLL4R 0x00009280
-#define CLK_ADC_CKPER 0x00009281
-#define CLK_ADC_PLL3Q 0x00009282
-#define CLK_ADC_DISABLED 0x00009283
-
-#define CLK_LPTIM45_PCLK3 0x000092C0
-#define CLK_LPTIM45_PLL4P 0x000092C1
-#define CLK_LPTIM45_PLL3Q 0x000092C2
-#define CLK_LPTIM45_LSE 0x000092C3
-#define CLK_LPTIM45_LSI 0x000092C4
-#define CLK_LPTIM45_CKPER 0x000092C5
-#define CLK_LPTIM45_DISABLED 0x000092C7
-
-#define CLK_LPTIM23_PCLK3 0x00009300
-#define CLK_LPTIM23_PLL4Q 0x00009301
-#define CLK_LPTIM23_CKPER 0x00009302
-#define CLK_LPTIM23_LSE 0x00009303
-#define CLK_LPTIM23_LSI 0x00009304
-#define CLK_LPTIM23_DISABLED 0x00009307
-
-#define CLK_LPTIM1_PCLK1 0x00009340
-#define CLK_LPTIM1_PLL4P 0x00009341
-#define CLK_LPTIM1_PLL3Q 0x00009342
-#define CLK_LPTIM1_LSE 0x00009343
-#define CLK_LPTIM1_LSI 0x00009344
-#define CLK_LPTIM1_CKPER 0x00009345
-#define CLK_LPTIM1_DISABLED 0x00009347
-
-/* define for st,pll /csg */
-#define SSCG_MODE_CENTER_SPREAD 0
-#define SSCG_MODE_DOWN_SPREAD 1
-
-/* define for st,drive */
-#define LSEDRV_LOWEST 0
-#define LSEDRV_MEDIUM_LOW 1
-#define LSEDRV_MEDIUM_HIGH 2
-#define LSEDRV_HIGHEST 3
-
-#endif
diff --git a/include/dt-bindings/clock/sun4i-a10-ccu.h b/include/dt-bindings/clock/sun4i-a10-ccu.h
deleted file mode 100644
index e4fa61b..0000000
--- a/include/dt-bindings/clock/sun4i-a10-ccu.h
+++ /dev/null
@@ -1,202 +0,0 @@
-/*
- * Copyright (C) 2017 Priit Laes <plaes@plaes.org>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef _DT_BINDINGS_CLK_SUN4I_A10_H_
-#define _DT_BINDINGS_CLK_SUN4I_A10_H_
-
-#define CLK_HOSC 1
-#define CLK_PLL_VIDEO0_2X 9
-#define CLK_PLL_VIDEO1_2X 18
-#define CLK_CPU 20
-
-/* AHB Gates */
-#define CLK_AHB_OTG 26
-#define CLK_AHB_EHCI0 27
-#define CLK_AHB_OHCI0 28
-#define CLK_AHB_EHCI1 29
-#define CLK_AHB_OHCI1 30
-#define CLK_AHB_SS 31
-#define CLK_AHB_DMA 32
-#define CLK_AHB_BIST 33
-#define CLK_AHB_MMC0 34
-#define CLK_AHB_MMC1 35
-#define CLK_AHB_MMC2 36
-#define CLK_AHB_MMC3 37
-#define CLK_AHB_MS 38
-#define CLK_AHB_NAND 39
-#define CLK_AHB_SDRAM 40
-#define CLK_AHB_ACE 41
-#define CLK_AHB_EMAC 42
-#define CLK_AHB_TS 43
-#define CLK_AHB_SPI0 44
-#define CLK_AHB_SPI1 45
-#define CLK_AHB_SPI2 46
-#define CLK_AHB_SPI3 47
-#define CLK_AHB_PATA 48
-#define CLK_AHB_SATA 49
-#define CLK_AHB_GPS 50
-#define CLK_AHB_HSTIMER 51
-#define CLK_AHB_VE 52
-#define CLK_AHB_TVD 53
-#define CLK_AHB_TVE0 54
-#define CLK_AHB_TVE1 55
-#define CLK_AHB_LCD0 56
-#define CLK_AHB_LCD1 57
-#define CLK_AHB_CSI0 58
-#define CLK_AHB_CSI1 59
-#define CLK_AHB_HDMI0 60
-#define CLK_AHB_HDMI1 61
-#define CLK_AHB_DE_BE0 62
-#define CLK_AHB_DE_BE1 63
-#define CLK_AHB_DE_FE0 64
-#define CLK_AHB_DE_FE1 65
-#define CLK_AHB_GMAC 66
-#define CLK_AHB_MP 67
-#define CLK_AHB_GPU 68
-
-/* APB0 Gates */
-#define CLK_APB0_CODEC 69
-#define CLK_APB0_SPDIF 70
-#define CLK_APB0_I2S0 71
-#define CLK_APB0_AC97 72
-#define CLK_APB0_I2S1 73
-#define CLK_APB0_PIO 74
-#define CLK_APB0_IR0 75
-#define CLK_APB0_IR1 76
-#define CLK_APB0_I2S2 77
-#define CLK_APB0_KEYPAD 78
-
-/* APB1 Gates */
-#define CLK_APB1_I2C0 79
-#define CLK_APB1_I2C1 80
-#define CLK_APB1_I2C2 81
-#define CLK_APB1_I2C3 82
-#define CLK_APB1_CAN 83
-#define CLK_APB1_SCR 84
-#define CLK_APB1_PS20 85
-#define CLK_APB1_PS21 86
-#define CLK_APB1_I2C4 87
-#define CLK_APB1_UART0 88
-#define CLK_APB1_UART1 89
-#define CLK_APB1_UART2 90
-#define CLK_APB1_UART3 91
-#define CLK_APB1_UART4 92
-#define CLK_APB1_UART5 93
-#define CLK_APB1_UART6 94
-#define CLK_APB1_UART7 95
-
-/* IP clocks */
-#define CLK_NAND 96
-#define CLK_MS 97
-#define CLK_MMC0 98
-#define CLK_MMC0_OUTPUT 99
-#define CLK_MMC0_SAMPLE 100
-#define CLK_MMC1 101
-#define CLK_MMC1_OUTPUT 102
-#define CLK_MMC1_SAMPLE 103
-#define CLK_MMC2 104
-#define CLK_MMC2_OUTPUT 105
-#define CLK_MMC2_SAMPLE 106
-#define CLK_MMC3 107
-#define CLK_MMC3_OUTPUT 108
-#define CLK_MMC3_SAMPLE 109
-#define CLK_TS 110
-#define CLK_SS 111
-#define CLK_SPI0 112
-#define CLK_SPI1 113
-#define CLK_SPI2 114
-#define CLK_PATA 115
-#define CLK_IR0 116
-#define CLK_IR1 117
-#define CLK_I2S0 118
-#define CLK_AC97 119
-#define CLK_SPDIF 120
-#define CLK_KEYPAD 121
-#define CLK_SATA 122
-#define CLK_USB_OHCI0 123
-#define CLK_USB_OHCI1 124
-#define CLK_USB_PHY 125
-#define CLK_GPS 126
-#define CLK_SPI3 127
-#define CLK_I2S1 128
-#define CLK_I2S2 129
-
-/* DRAM Gates */
-#define CLK_DRAM_VE 130
-#define CLK_DRAM_CSI0 131
-#define CLK_DRAM_CSI1 132
-#define CLK_DRAM_TS 133
-#define CLK_DRAM_TVD 134
-#define CLK_DRAM_TVE0 135
-#define CLK_DRAM_TVE1 136
-#define CLK_DRAM_OUT 137
-#define CLK_DRAM_DE_FE1 138
-#define CLK_DRAM_DE_FE0 139
-#define CLK_DRAM_DE_BE0 140
-#define CLK_DRAM_DE_BE1 141
-#define CLK_DRAM_MP 142
-#define CLK_DRAM_ACE 143
-
-/* Display Engine Clocks */
-#define CLK_DE_BE0 144
-#define CLK_DE_BE1 145
-#define CLK_DE_FE0 146
-#define CLK_DE_FE1 147
-#define CLK_DE_MP 148
-#define CLK_TCON0_CH0 149
-#define CLK_TCON1_CH0 150
-#define CLK_CSI_SCLK 151
-#define CLK_TVD_SCLK2 152
-#define CLK_TVD 153
-#define CLK_TCON0_CH1_SCLK2 154
-#define CLK_TCON0_CH1 155
-#define CLK_TCON1_CH1_SCLK2 156
-#define CLK_TCON1_CH1 157
-#define CLK_CSI0 158
-#define CLK_CSI1 159
-#define CLK_CODEC 160
-#define CLK_VE 161
-#define CLK_AVS 162
-#define CLK_ACE 163
-#define CLK_HDMI 164
-#define CLK_GPU 165
-
-#endif /* _DT_BINDINGS_CLK_SUN4I_A10_H_ */
diff --git a/include/dt-bindings/clock/sun4i-a10-pll2.h b/include/dt-bindings/clock/sun4i-a10-pll2.h
deleted file mode 100644
index 071c811..0000000
--- a/include/dt-bindings/clock/sun4i-a10-pll2.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * Copyright 2015 Maxime Ripard
- *
- * Maxime Ripard <maxime.ripard@free-electrons.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef __DT_BINDINGS_CLOCK_SUN4I_A10_PLL2_H_
-#define __DT_BINDINGS_CLOCK_SUN4I_A10_PLL2_H_
-
-#define SUN4I_A10_PLL2_1X 0
-#define SUN4I_A10_PLL2_2X 1
-#define SUN4I_A10_PLL2_4X 2
-#define SUN4I_A10_PLL2_8X 3
-
-#endif /* __DT_BINDINGS_CLOCK_SUN4I_A10_PLL2_H_ */
diff --git a/include/dt-bindings/clock/sun50i-a64-ccu.h b/include/dt-bindings/clock/sun50i-a64-ccu.h
deleted file mode 100644
index d66432c..0000000
--- a/include/dt-bindings/clock/sun50i-a64-ccu.h
+++ /dev/null
@@ -1,136 +0,0 @@
-/*
- * Copyright (C) 2016 Maxime Ripard <maxime.ripard@free-electrons.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef _DT_BINDINGS_CLK_SUN50I_A64_H_
-#define _DT_BINDINGS_CLK_SUN50I_A64_H_
-
-#define CLK_PLL_PERIPH0 11
-
-#define CLK_BUS_MIPI_DSI 28
-#define CLK_BUS_CE 29
-#define CLK_BUS_DMA 30
-#define CLK_BUS_MMC0 31
-#define CLK_BUS_MMC1 32
-#define CLK_BUS_MMC2 33
-#define CLK_BUS_NAND 34
-#define CLK_BUS_DRAM 35
-#define CLK_BUS_EMAC 36
-#define CLK_BUS_TS 37
-#define CLK_BUS_HSTIMER 38
-#define CLK_BUS_SPI0 39
-#define CLK_BUS_SPI1 40
-#define CLK_BUS_OTG 41
-#define CLK_BUS_EHCI0 42
-#define CLK_BUS_EHCI1 43
-#define CLK_BUS_OHCI0 44
-#define CLK_BUS_OHCI1 45
-#define CLK_BUS_VE 46
-#define CLK_BUS_TCON0 47
-#define CLK_BUS_TCON1 48
-#define CLK_BUS_DEINTERLACE 49
-#define CLK_BUS_CSI 50
-#define CLK_BUS_HDMI 51
-#define CLK_BUS_DE 52
-#define CLK_BUS_GPU 53
-#define CLK_BUS_MSGBOX 54
-#define CLK_BUS_SPINLOCK 55
-#define CLK_BUS_CODEC 56
-#define CLK_BUS_SPDIF 57
-#define CLK_BUS_PIO 58
-#define CLK_BUS_THS 59
-#define CLK_BUS_I2S0 60
-#define CLK_BUS_I2S1 61
-#define CLK_BUS_I2S2 62
-#define CLK_BUS_I2C0 63
-#define CLK_BUS_I2C1 64
-#define CLK_BUS_I2C2 65
-#define CLK_BUS_SCR 66
-#define CLK_BUS_UART0 67
-#define CLK_BUS_UART1 68
-#define CLK_BUS_UART2 69
-#define CLK_BUS_UART3 70
-#define CLK_BUS_UART4 71
-#define CLK_BUS_DBG 72
-#define CLK_THS 73
-#define CLK_NAND 74
-#define CLK_MMC0 75
-#define CLK_MMC1 76
-#define CLK_MMC2 77
-#define CLK_TS 78
-#define CLK_CE 79
-#define CLK_SPI0 80
-#define CLK_SPI1 81
-#define CLK_I2S0 82
-#define CLK_I2S1 83
-#define CLK_I2S2 84
-#define CLK_SPDIF 85
-#define CLK_USB_PHY0 86
-#define CLK_USB_PHY1 87
-#define CLK_USB_HSIC 88
-#define CLK_USB_HSIC_12M 89
-
-#define CLK_USB_OHCI0 91
-
-#define CLK_USB_OHCI1 93
-
-#define CLK_DRAM_VE 95
-#define CLK_DRAM_CSI 96
-#define CLK_DRAM_DEINTERLACE 97
-#define CLK_DRAM_TS 98
-#define CLK_DE 99
-#define CLK_TCON0 100
-#define CLK_TCON1 101
-#define CLK_DEINTERLACE 102
-#define CLK_CSI_MISC 103
-#define CLK_CSI_SCLK 104
-#define CLK_CSI_MCLK 105
-#define CLK_VE 106
-#define CLK_AC_DIG 107
-#define CLK_AC_DIG_4X 108
-#define CLK_AVS 109
-#define CLK_HDMI 110
-#define CLK_HDMI_DDC 111
-
-#define CLK_DSI_DPHY 113
-#define CLK_GPU 114
-
-#endif /* _DT_BINDINGS_CLK_SUN50I_H_ */
diff --git a/include/dt-bindings/clock/sun50i-h6-ccu.h b/include/dt-bindings/clock/sun50i-h6-ccu.h
deleted file mode 100644
index a1545cd..0000000
--- a/include/dt-bindings/clock/sun50i-h6-ccu.h
+++ /dev/null
@@ -1,125 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ or MIT)
-/*
- * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
- */
-
-#ifndef _DT_BINDINGS_CLK_SUN50I_H6_H_
-#define _DT_BINDINGS_CLK_SUN50I_H6_H_
-
-#define CLK_PLL_PERIPH0 3
-
-#define CLK_CPUX 21
-
-#define CLK_APB1 26
-
-#define CLK_DE 29
-#define CLK_BUS_DE 30
-#define CLK_DEINTERLACE 31
-#define CLK_BUS_DEINTERLACE 32
-#define CLK_GPU 33
-#define CLK_BUS_GPU 34
-#define CLK_CE 35
-#define CLK_BUS_CE 36
-#define CLK_VE 37
-#define CLK_BUS_VE 38
-#define CLK_EMCE 39
-#define CLK_BUS_EMCE 40
-#define CLK_VP9 41
-#define CLK_BUS_VP9 42
-#define CLK_BUS_DMA 43
-#define CLK_BUS_MSGBOX 44
-#define CLK_BUS_SPINLOCK 45
-#define CLK_BUS_HSTIMER 46
-#define CLK_AVS 47
-#define CLK_BUS_DBG 48
-#define CLK_BUS_PSI 49
-#define CLK_BUS_PWM 50
-#define CLK_BUS_IOMMU 51
-
-#define CLK_MBUS_DMA 53
-#define CLK_MBUS_VE 54
-#define CLK_MBUS_CE 55
-#define CLK_MBUS_TS 56
-#define CLK_MBUS_NAND 57
-#define CLK_MBUS_CSI 58
-#define CLK_MBUS_DEINTERLACE 59
-
-#define CLK_NAND0 61
-#define CLK_NAND1 62
-#define CLK_BUS_NAND 63
-#define CLK_MMC0 64
-#define CLK_MMC1 65
-#define CLK_MMC2 66
-#define CLK_BUS_MMC0 67
-#define CLK_BUS_MMC1 68
-#define CLK_BUS_MMC2 69
-#define CLK_BUS_UART0 70
-#define CLK_BUS_UART1 71
-#define CLK_BUS_UART2 72
-#define CLK_BUS_UART3 73
-#define CLK_BUS_I2C0 74
-#define CLK_BUS_I2C1 75
-#define CLK_BUS_I2C2 76
-#define CLK_BUS_I2C3 77
-#define CLK_BUS_SCR0 78
-#define CLK_BUS_SCR1 79
-#define CLK_SPI0 80
-#define CLK_SPI1 81
-#define CLK_BUS_SPI0 82
-#define CLK_BUS_SPI1 83
-#define CLK_BUS_EMAC 84
-#define CLK_TS 85
-#define CLK_BUS_TS 86
-#define CLK_IR_TX 87
-#define CLK_BUS_IR_TX 88
-#define CLK_BUS_THS 89
-#define CLK_I2S3 90
-#define CLK_I2S0 91
-#define CLK_I2S1 92
-#define CLK_I2S2 93
-#define CLK_BUS_I2S0 94
-#define CLK_BUS_I2S1 95
-#define CLK_BUS_I2S2 96
-#define CLK_BUS_I2S3 97
-#define CLK_SPDIF 98
-#define CLK_BUS_SPDIF 99
-#define CLK_DMIC 100
-#define CLK_BUS_DMIC 101
-#define CLK_AUDIO_HUB 102
-#define CLK_BUS_AUDIO_HUB 103
-#define CLK_USB_OHCI0 104
-#define CLK_USB_PHY0 105
-#define CLK_USB_PHY1 106
-#define CLK_USB_OHCI3 107
-#define CLK_USB_PHY3 108
-#define CLK_USB_HSIC_12M 109
-#define CLK_USB_HSIC 110
-#define CLK_BUS_OHCI0 111
-#define CLK_BUS_OHCI3 112
-#define CLK_BUS_EHCI0 113
-#define CLK_BUS_XHCI 114
-#define CLK_BUS_EHCI3 115
-#define CLK_BUS_OTG 116
-#define CLK_PCIE_REF_100M 117
-#define CLK_PCIE_REF 118
-#define CLK_PCIE_REF_OUT 119
-#define CLK_PCIE_MAXI 120
-#define CLK_PCIE_AUX 121
-#define CLK_BUS_PCIE 122
-#define CLK_HDMI 123
-#define CLK_HDMI_SLOW 124
-#define CLK_HDMI_CEC 125
-#define CLK_BUS_HDMI 126
-#define CLK_BUS_TCON_TOP 127
-#define CLK_TCON_LCD0 128
-#define CLK_BUS_TCON_LCD0 129
-#define CLK_TCON_TV0 130
-#define CLK_BUS_TCON_TV0 131
-#define CLK_CSI_CCI 132
-#define CLK_CSI_TOP 133
-#define CLK_CSI_MCLK 134
-#define CLK_BUS_CSI 135
-#define CLK_HDCP 136
-#define CLK_BUS_HDCP 137
-
-#endif /* _DT_BINDINGS_CLK_SUN50I_H6_H_ */
diff --git a/include/dt-bindings/clock/sun50i-h6-r-ccu.h b/include/dt-bindings/clock/sun50i-h6-r-ccu.h
deleted file mode 100644
index 7613613..0000000
--- a/include/dt-bindings/clock/sun50i-h6-r-ccu.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (c) 2017 Icenowy Zheng <icenowy@aosc.xyz>
- */
-
-#ifndef _DT_BINDINGS_CLK_SUN50I_H6_R_CCU_H_
-#define _DT_BINDINGS_CLK_SUN50I_H6_R_CCU_H_
-
-#define CLK_AR100 0
-
-#define CLK_R_APB1 2
-
-#define CLK_R_APB1_TIMER 4
-#define CLK_R_APB1_TWD 5
-#define CLK_R_APB1_PWM 6
-#define CLK_R_APB2_UART 7
-#define CLK_R_APB2_I2C 8
-#define CLK_R_APB1_IR 9
-#define CLK_R_APB1_W1 10
-
-#define CLK_IR 11
-#define CLK_W1 12
-
-#endif /* _DT_BINDINGS_CLK_SUN50I_H6_R_CCU_H_ */
diff --git a/include/dt-bindings/clock/sun5i-ccu.h b/include/dt-bindings/clock/sun5i-ccu.h
deleted file mode 100644
index 81f34d4..0000000
--- a/include/dt-bindings/clock/sun5i-ccu.h
+++ /dev/null
@@ -1,106 +0,0 @@
-/*
- * Copyright 2016 Maxime Ripard
- *
- * Maxime Ripard <maxime.ripard@free-electrons.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef _DT_BINDINGS_CLK_SUN5I_H_
-#define _DT_BINDINGS_CLK_SUN5I_H_
-
-#define CLK_HOSC 1
-
-#define CLK_PLL_VIDEO0_2X 9
-
-#define CLK_PLL_VIDEO1_2X 16
-#define CLK_CPU 17
-
-#define CLK_AHB_OTG 23
-#define CLK_AHB_EHCI 24
-#define CLK_AHB_OHCI 25
-#define CLK_AHB_SS 26
-#define CLK_AHB_DMA 27
-#define CLK_AHB_BIST 28
-#define CLK_AHB_MMC0 29
-#define CLK_AHB_MMC1 30
-#define CLK_AHB_MMC2 31
-#define CLK_AHB_NAND 32
-#define CLK_AHB_SDRAM 33
-#define CLK_AHB_EMAC 34
-#define CLK_AHB_TS 35
-#define CLK_AHB_SPI0 36
-#define CLK_AHB_SPI1 37
-#define CLK_AHB_SPI2 38
-#define CLK_AHB_GPS 39
-#define CLK_AHB_HSTIMER 40
-#define CLK_AHB_VE 41
-#define CLK_AHB_TVE 42
-#define CLK_AHB_LCD 43
-#define CLK_AHB_CSI 44
-#define CLK_AHB_HDMI 45
-#define CLK_AHB_DE_BE 46
-#define CLK_AHB_DE_FE 47
-#define CLK_AHB_IEP 48
-#define CLK_AHB_GPU 49
-#define CLK_APB0_CODEC 50
-#define CLK_APB0_SPDIF 51
-#define CLK_APB0_I2S 52
-#define CLK_APB0_PIO 53
-#define CLK_APB0_IR 54
-#define CLK_APB0_KEYPAD 55
-#define CLK_APB1_I2C0 56
-#define CLK_APB1_I2C1 57
-#define CLK_APB1_I2C2 58
-#define CLK_APB1_UART0 59
-#define CLK_APB1_UART1 60
-#define CLK_APB1_UART2 61
-#define CLK_APB1_UART3 62
-#define CLK_NAND 63
-#define CLK_MMC0 64
-#define CLK_MMC1 65
-#define CLK_MMC2 66
-#define CLK_TS 67
-#define CLK_SS 68
-#define CLK_SPI0 69
-#define CLK_SPI1 70
-#define CLK_SPI2 71
-#define CLK_IR 72
-#define CLK_I2S 73
-#define CLK_SPDIF 74
-#define CLK_KEYPAD 75
-#define CLK_USB_OHCI 76
-#define CLK_USB_PHY0 77
-#define CLK_USB_PHY1 78
-#define CLK_GPS 79
-#define CLK_DRAM_VE 80
-#define CLK_DRAM_CSI 81
-#define CLK_DRAM_TS 82
-#define CLK_DRAM_TVE 83
-#define CLK_DRAM_DE_FE 84
-#define CLK_DRAM_DE_BE 85
-#define CLK_DRAM_ACE 86
-#define CLK_DRAM_IEP 87
-#define CLK_DE_BE 88
-#define CLK_DE_FE 89
-#define CLK_TCON_CH0 90
-
-#define CLK_TCON_CH1 92
-#define CLK_CSI 93
-#define CLK_VE 94
-#define CLK_CODEC 95
-#define CLK_AVS 96
-#define CLK_HDMI 97
-#define CLK_GPU 98
-
-#define CLK_IEP 100
-
-#endif /* _DT_BINDINGS_CLK_SUN5I_H_ */
diff --git a/include/dt-bindings/clock/sun6i-a31-ccu.h b/include/dt-bindings/clock/sun6i-a31-ccu.h
deleted file mode 100644
index c5d1334..0000000
--- a/include/dt-bindings/clock/sun6i-a31-ccu.h
+++ /dev/null
@@ -1,191 +0,0 @@
-/*
- * Copyright (C) 2016 Chen-Yu Tsai <wens@csie.org>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef _DT_BINDINGS_CLK_SUN6I_A31_H_
-#define _DT_BINDINGS_CLK_SUN6I_A31_H_
-
-#define CLK_PLL_VIDEO0_2X 7
-
-#define CLK_PLL_PERIPH 10
-
-#define CLK_PLL_VIDEO1_2X 13
-
-#define CLK_CPU 18
-
-#define CLK_AHB1_MIPIDSI 23
-#define CLK_AHB1_SS 24
-#define CLK_AHB1_DMA 25
-#define CLK_AHB1_MMC0 26
-#define CLK_AHB1_MMC1 27
-#define CLK_AHB1_MMC2 28
-#define CLK_AHB1_MMC3 29
-#define CLK_AHB1_NAND1 30
-#define CLK_AHB1_NAND0 31
-#define CLK_AHB1_SDRAM 32
-#define CLK_AHB1_EMAC 33
-#define CLK_AHB1_TS 34
-#define CLK_AHB1_HSTIMER 35
-#define CLK_AHB1_SPI0 36
-#define CLK_AHB1_SPI1 37
-#define CLK_AHB1_SPI2 38
-#define CLK_AHB1_SPI3 39
-#define CLK_AHB1_OTG 40
-#define CLK_AHB1_EHCI0 41
-#define CLK_AHB1_EHCI1 42
-#define CLK_AHB1_OHCI0 43
-#define CLK_AHB1_OHCI1 44
-#define CLK_AHB1_OHCI2 45
-#define CLK_AHB1_VE 46
-#define CLK_AHB1_LCD0 47
-#define CLK_AHB1_LCD1 48
-#define CLK_AHB1_CSI 49
-#define CLK_AHB1_HDMI 50
-#define CLK_AHB1_BE0 51
-#define CLK_AHB1_BE1 52
-#define CLK_AHB1_FE0 53
-#define CLK_AHB1_FE1 54
-#define CLK_AHB1_MP 55
-#define CLK_AHB1_GPU 56
-#define CLK_AHB1_DEU0 57
-#define CLK_AHB1_DEU1 58
-#define CLK_AHB1_DRC0 59
-#define CLK_AHB1_DRC1 60
-
-#define CLK_APB1_CODEC 61
-#define CLK_APB1_SPDIF 62
-#define CLK_APB1_DIGITAL_MIC 63
-#define CLK_APB1_PIO 64
-#define CLK_APB1_DAUDIO0 65
-#define CLK_APB1_DAUDIO1 66
-
-#define CLK_APB2_I2C0 67
-#define CLK_APB2_I2C1 68
-#define CLK_APB2_I2C2 69
-#define CLK_APB2_I2C3 70
-#define CLK_APB2_UART0 71
-#define CLK_APB2_UART1 72
-#define CLK_APB2_UART2 73
-#define CLK_APB2_UART3 74
-#define CLK_APB2_UART4 75
-#define CLK_APB2_UART5 76
-
-#define CLK_NAND0 77
-#define CLK_NAND1 78
-#define CLK_MMC0 79
-#define CLK_MMC0_SAMPLE 80
-#define CLK_MMC0_OUTPUT 81
-#define CLK_MMC1 82
-#define CLK_MMC1_SAMPLE 83
-#define CLK_MMC1_OUTPUT 84
-#define CLK_MMC2 85
-#define CLK_MMC2_SAMPLE 86
-#define CLK_MMC2_OUTPUT 87
-#define CLK_MMC3 88
-#define CLK_MMC3_SAMPLE 89
-#define CLK_MMC3_OUTPUT 90
-#define CLK_TS 91
-#define CLK_SS 92
-#define CLK_SPI0 93
-#define CLK_SPI1 94
-#define CLK_SPI2 95
-#define CLK_SPI3 96
-#define CLK_DAUDIO0 97
-#define CLK_DAUDIO1 98
-#define CLK_SPDIF 99
-#define CLK_USB_PHY0 100
-#define CLK_USB_PHY1 101
-#define CLK_USB_PHY2 102
-#define CLK_USB_OHCI0 103
-#define CLK_USB_OHCI1 104
-#define CLK_USB_OHCI2 105
-
-#define CLK_DRAM_VE 110
-#define CLK_DRAM_CSI_ISP 111
-#define CLK_DRAM_TS 112
-#define CLK_DRAM_DRC0 113
-#define CLK_DRAM_DRC1 114
-#define CLK_DRAM_DEU0 115
-#define CLK_DRAM_DEU1 116
-#define CLK_DRAM_FE0 117
-#define CLK_DRAM_FE1 118
-#define CLK_DRAM_BE0 119
-#define CLK_DRAM_BE1 120
-#define CLK_DRAM_MP 121
-
-#define CLK_BE0 122
-#define CLK_BE1 123
-#define CLK_FE0 124
-#define CLK_FE1 125
-#define CLK_MP 126
-#define CLK_LCD0_CH0 127
-#define CLK_LCD1_CH0 128
-#define CLK_LCD0_CH1 129
-#define CLK_LCD1_CH1 130
-#define CLK_CSI0_SCLK 131
-#define CLK_CSI0_MCLK 132
-#define CLK_CSI1_MCLK 133
-#define CLK_VE 134
-#define CLK_CODEC 135
-#define CLK_AVS 136
-#define CLK_DIGITAL_MIC 137
-#define CLK_HDMI 138
-#define CLK_HDMI_DDC 139
-#define CLK_PS 140
-
-#define CLK_MIPI_DSI 143
-#define CLK_MIPI_DSI_DPHY 144
-#define CLK_MIPI_CSI_DPHY 145
-#define CLK_IEP_DRC0 146
-#define CLK_IEP_DRC1 147
-#define CLK_IEP_DEU0 148
-#define CLK_IEP_DEU1 149
-#define CLK_GPU_CORE 150
-#define CLK_GPU_MEMORY 151
-#define CLK_GPU_HYD 152
-#define CLK_ATS 153
-#define CLK_TRACE 154
-
-#define CLK_OUT_A 155
-#define CLK_OUT_B 156
-#define CLK_OUT_C 157
-
-#endif /* _DT_BINDINGS_CLK_SUN6I_A31_H_ */
diff --git a/include/dt-bindings/clock/sun7i-a20-ccu.h b/include/dt-bindings/clock/sun7i-a20-ccu.h
deleted file mode 100644
index 045a517..0000000
--- a/include/dt-bindings/clock/sun7i-a20-ccu.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * Copyright (C) 2017 Priit Laes <plaes@plaes.org>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef _DT_BINDINGS_CLK_SUN7I_A20_H_
-#define _DT_BINDINGS_CLK_SUN7I_A20_H_
-
-#include <dt-bindings/clock/sun4i-a10-ccu.h>
-
-#define CLK_MBUS 166
-#define CLK_HDMI1_SLOW 167
-#define CLK_HDMI1 168
-#define CLK_OUT_A 169
-#define CLK_OUT_B 170
-
-#endif /* _DT_BINDINGS_CLK_SUN7I_A20_H_ */
diff --git a/include/dt-bindings/clock/sun8i-a23-a33-ccu.h b/include/dt-bindings/clock/sun8i-a23-a33-ccu.h
deleted file mode 100644
index f8222b6..0000000
--- a/include/dt-bindings/clock/sun8i-a23-a33-ccu.h
+++ /dev/null
@@ -1,127 +0,0 @@
-/*
- * Copyright (C) 2016 Maxime Ripard <maxime.ripard@free-electrons.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef _DT_BINDINGS_CLK_SUN8I_A23_A33_H_
-#define _DT_BINDINGS_CLK_SUN8I_A23_A33_H_
-
-#define CLK_CPUX 18
-
-#define CLK_BUS_MIPI_DSI 23
-#define CLK_BUS_SS 24
-#define CLK_BUS_DMA 25
-#define CLK_BUS_MMC0 26
-#define CLK_BUS_MMC1 27
-#define CLK_BUS_MMC2 28
-#define CLK_BUS_NAND 29
-#define CLK_BUS_DRAM 30
-#define CLK_BUS_HSTIMER 31
-#define CLK_BUS_SPI0 32
-#define CLK_BUS_SPI1 33
-#define CLK_BUS_OTG 34
-#define CLK_BUS_EHCI 35
-#define CLK_BUS_OHCI 36
-#define CLK_BUS_VE 37
-#define CLK_BUS_LCD 38
-#define CLK_BUS_CSI 39
-#define CLK_BUS_DE_BE 40
-#define CLK_BUS_DE_FE 41
-#define CLK_BUS_GPU 42
-#define CLK_BUS_MSGBOX 43
-#define CLK_BUS_SPINLOCK 44
-#define CLK_BUS_DRC 45
-#define CLK_BUS_SAT 46
-#define CLK_BUS_CODEC 47
-#define CLK_BUS_PIO 48
-#define CLK_BUS_I2S0 49
-#define CLK_BUS_I2S1 50
-#define CLK_BUS_I2C0 51
-#define CLK_BUS_I2C1 52
-#define CLK_BUS_I2C2 53
-#define CLK_BUS_UART0 54
-#define CLK_BUS_UART1 55
-#define CLK_BUS_UART2 56
-#define CLK_BUS_UART3 57
-#define CLK_BUS_UART4 58
-#define CLK_NAND 59
-#define CLK_MMC0 60
-#define CLK_MMC0_SAMPLE 61
-#define CLK_MMC0_OUTPUT 62
-#define CLK_MMC1 63
-#define CLK_MMC1_SAMPLE 64
-#define CLK_MMC1_OUTPUT 65
-#define CLK_MMC2 66
-#define CLK_MMC2_SAMPLE 67
-#define CLK_MMC2_OUTPUT 68
-#define CLK_SS 69
-#define CLK_SPI0 70
-#define CLK_SPI1 71
-#define CLK_I2S0 72
-#define CLK_I2S1 73
-#define CLK_USB_PHY0 74
-#define CLK_USB_PHY1 75
-#define CLK_USB_HSIC 76
-#define CLK_USB_HSIC_12M 77
-#define CLK_USB_OHCI 78
-
-#define CLK_DRAM_VE 80
-#define CLK_DRAM_CSI 81
-#define CLK_DRAM_DRC 82
-#define CLK_DRAM_DE_FE 83
-#define CLK_DRAM_DE_BE 84
-#define CLK_DE_BE 85
-#define CLK_DE_FE 86
-#define CLK_LCD_CH0 87
-#define CLK_LCD_CH1 88
-#define CLK_CSI_SCLK 89
-#define CLK_CSI_MCLK 90
-#define CLK_VE 91
-#define CLK_AC_DIG 92
-#define CLK_AC_DIG_4X 93
-#define CLK_AVS 94
-
-#define CLK_DSI_SCLK 96
-#define CLK_DSI_DPHY 97
-#define CLK_DRC 98
-#define CLK_GPU 99
-#define CLK_ATS 100
-
-#endif /* _DT_BINDINGS_CLK_SUN8I_A23_A33_H_ */
diff --git a/include/dt-bindings/clock/sun8i-a83t-ccu.h b/include/dt-bindings/clock/sun8i-a83t-ccu.h
deleted file mode 100644
index 78af508..0000000
--- a/include/dt-bindings/clock/sun8i-a83t-ccu.h
+++ /dev/null
@@ -1,140 +0,0 @@
-/*
- * Copyright (C) 2017 Chen-Yu Tsai <wens@csie.org>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef _DT_BINDINGS_CLOCK_SUN8I_A83T_CCU_H_
-#define _DT_BINDINGS_CLOCK_SUN8I_A83T_CCU_H_
-
-#define CLK_PLL_PERIPH 6
-
-#define CLK_PLL_DE 9
-
-#define CLK_C0CPUX 11
-#define CLK_C1CPUX 12
-
-#define CLK_BUS_MIPI_DSI 19
-#define CLK_BUS_SS 20
-#define CLK_BUS_DMA 21
-#define CLK_BUS_MMC0 22
-#define CLK_BUS_MMC1 23
-#define CLK_BUS_MMC2 24
-#define CLK_BUS_NAND 25
-#define CLK_BUS_DRAM 26
-#define CLK_BUS_EMAC 27
-#define CLK_BUS_HSTIMER 28
-#define CLK_BUS_SPI0 29
-#define CLK_BUS_SPI1 30
-#define CLK_BUS_OTG 31
-#define CLK_BUS_EHCI0 32
-#define CLK_BUS_EHCI1 33
-#define CLK_BUS_OHCI0 34
-
-#define CLK_BUS_VE 35
-#define CLK_BUS_TCON0 36
-#define CLK_BUS_TCON1 37
-#define CLK_BUS_CSI 38
-#define CLK_BUS_HDMI 39
-#define CLK_BUS_DE 40
-#define CLK_BUS_GPU 41
-#define CLK_BUS_MSGBOX 42
-#define CLK_BUS_SPINLOCK 43
-
-#define CLK_BUS_SPDIF 44
-#define CLK_BUS_PIO 45
-#define CLK_BUS_I2S0 46
-#define CLK_BUS_I2S1 47
-#define CLK_BUS_I2S2 48
-#define CLK_BUS_TDM 49
-
-#define CLK_BUS_I2C0 50
-#define CLK_BUS_I2C1 51
-#define CLK_BUS_I2C2 52
-#define CLK_BUS_UART0 53
-#define CLK_BUS_UART1 54
-#define CLK_BUS_UART2 55
-#define CLK_BUS_UART3 56
-#define CLK_BUS_UART4 57
-
-#define CLK_NAND 59
-#define CLK_MMC0 60
-#define CLK_MMC0_SAMPLE 61
-#define CLK_MMC0_OUTPUT 62
-#define CLK_MMC1 63
-#define CLK_MMC1_SAMPLE 64
-#define CLK_MMC1_OUTPUT 65
-#define CLK_MMC2 66
-#define CLK_MMC2_SAMPLE 67
-#define CLK_MMC2_OUTPUT 68
-#define CLK_SS 69
-#define CLK_SPI0 70
-#define CLK_SPI1 71
-#define CLK_I2S0 72
-#define CLK_I2S1 73
-#define CLK_I2S2 74
-#define CLK_TDM 75
-#define CLK_SPDIF 76
-#define CLK_USB_PHY0 77
-#define CLK_USB_PHY1 78
-#define CLK_USB_HSIC 79
-#define CLK_USB_HSIC_12M 80
-#define CLK_USB_OHCI0 81
-
-#define CLK_DRAM_VE 83
-#define CLK_DRAM_CSI 84
-
-#define CLK_TCON0 85
-#define CLK_TCON1 86
-#define CLK_CSI_MISC 87
-#define CLK_MIPI_CSI 88
-#define CLK_CSI_MCLK 89
-#define CLK_CSI_SCLK 90
-#define CLK_VE 91
-#define CLK_AVS 92
-#define CLK_HDMI 93
-#define CLK_HDMI_SLOW 94
-
-#define CLK_MIPI_DSI0 96
-#define CLK_MIPI_DSI1 97
-#define CLK_GPU_CORE 98
-#define CLK_GPU_MEMORY 99
-#define CLK_GPU_HYD 100
-
-#endif /* _DT_BINDINGS_CLOCK_SUN8I_A83T_CCU_H_ */
diff --git a/include/dt-bindings/clock/sun8i-de2.h b/include/dt-bindings/clock/sun8i-de2.h
deleted file mode 100644
index 3bed63b..0000000
--- a/include/dt-bindings/clock/sun8i-de2.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- * Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.io>
- *
- * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- */
-
-#ifndef _DT_BINDINGS_CLOCK_SUN8I_DE2_H_
-#define _DT_BINDINGS_CLOCK_SUN8I_DE2_H_
-
-#define CLK_BUS_MIXER0 0
-#define CLK_BUS_MIXER1 1
-#define CLK_BUS_WB 2
-
-#define CLK_MIXER0 6
-#define CLK_MIXER1 7
-#define CLK_WB 8
-
-#endif /* _DT_BINDINGS_CLOCK_SUN8I_DE2_H_ */
diff --git a/include/dt-bindings/clock/sun8i-h3-ccu.h b/include/dt-bindings/clock/sun8i-h3-ccu.h
deleted file mode 100644
index efb7ba2..0000000
--- a/include/dt-bindings/clock/sun8i-h3-ccu.h
+++ /dev/null
@@ -1,145 +0,0 @@
-/*
- * Copyright (C) 2016 Maxime Ripard <maxime.ripard@free-electrons.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef _DT_BINDINGS_CLK_SUN8I_H3_H_
-#define _DT_BINDINGS_CLK_SUN8I_H3_H_
-
-#define CLK_CPUX 14
-
-#define CLK_BUS_CE 20
-#define CLK_BUS_DMA 21
-#define CLK_BUS_MMC0 22
-#define CLK_BUS_MMC1 23
-#define CLK_BUS_MMC2 24
-#define CLK_BUS_NAND 25
-#define CLK_BUS_DRAM 26
-#define CLK_BUS_EMAC 27
-#define CLK_BUS_TS 28
-#define CLK_BUS_HSTIMER 29
-#define CLK_BUS_SPI0 30
-#define CLK_BUS_SPI1 31
-#define CLK_BUS_OTG 32
-#define CLK_BUS_EHCI0 33
-#define CLK_BUS_EHCI1 34
-#define CLK_BUS_EHCI2 35
-#define CLK_BUS_EHCI3 36
-#define CLK_BUS_OHCI0 37
-#define CLK_BUS_OHCI1 38
-#define CLK_BUS_OHCI2 39
-#define CLK_BUS_OHCI3 40
-#define CLK_BUS_VE 41
-#define CLK_BUS_TCON0 42
-#define CLK_BUS_TCON1 43
-#define CLK_BUS_DEINTERLACE 44
-#define CLK_BUS_CSI 45
-#define CLK_BUS_TVE 46
-#define CLK_BUS_HDMI 47
-#define CLK_BUS_DE 48
-#define CLK_BUS_GPU 49
-#define CLK_BUS_MSGBOX 50
-#define CLK_BUS_SPINLOCK 51
-#define CLK_BUS_CODEC 52
-#define CLK_BUS_SPDIF 53
-#define CLK_BUS_PIO 54
-#define CLK_BUS_THS 55
-#define CLK_BUS_I2S0 56
-#define CLK_BUS_I2S1 57
-#define CLK_BUS_I2S2 58
-#define CLK_BUS_I2C0 59
-#define CLK_BUS_I2C1 60
-#define CLK_BUS_I2C2 61
-#define CLK_BUS_UART0 62
-#define CLK_BUS_UART1 63
-#define CLK_BUS_UART2 64
-#define CLK_BUS_UART3 65
-#define CLK_BUS_SCR 66
-#define CLK_BUS_EPHY 67
-#define CLK_BUS_DBG 68
-
-#define CLK_THS 69
-#define CLK_NAND 70
-#define CLK_MMC0 71
-#define CLK_MMC0_SAMPLE 72
-#define CLK_MMC0_OUTPUT 73
-#define CLK_MMC1 74
-#define CLK_MMC1_SAMPLE 75
-#define CLK_MMC1_OUTPUT 76
-#define CLK_MMC2 77
-#define CLK_MMC2_SAMPLE 78
-#define CLK_MMC2_OUTPUT 79
-#define CLK_TS 80
-#define CLK_CE 81
-#define CLK_SPI0 82
-#define CLK_SPI1 83
-#define CLK_I2S0 84
-#define CLK_I2S1 85
-#define CLK_I2S2 86
-#define CLK_SPDIF 87
-#define CLK_USB_PHY0 88
-#define CLK_USB_PHY1 89
-#define CLK_USB_PHY2 90
-#define CLK_USB_PHY3 91
-#define CLK_USB_OHCI0 92
-#define CLK_USB_OHCI1 93
-#define CLK_USB_OHCI2 94
-#define CLK_USB_OHCI3 95
-
-#define CLK_DRAM_VE 97
-#define CLK_DRAM_CSI 98
-#define CLK_DRAM_DEINTERLACE 99
-#define CLK_DRAM_TS 100
-#define CLK_DE 101
-#define CLK_TCON0 102
-#define CLK_TVE 103
-#define CLK_DEINTERLACE 104
-#define CLK_CSI_MISC 105
-#define CLK_CSI_SCLK 106
-#define CLK_CSI_MCLK 107
-#define CLK_VE 108
-#define CLK_AC_DIG 109
-#define CLK_AVS 110
-#define CLK_HDMI 111
-#define CLK_HDMI_DDC 112
-
-#define CLK_GPU 114
-
-#endif /* _DT_BINDINGS_CLK_SUN8I_H3_H_ */
diff --git a/include/dt-bindings/clock/sun8i-r-ccu.h b/include/dt-bindings/clock/sun8i-r-ccu.h
deleted file mode 100644
index 779d20a..0000000
--- a/include/dt-bindings/clock/sun8i-r-ccu.h
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * Copyright (c) 2016 Icenowy Zheng <icenowy@aosc.xyz>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef _DT_BINDINGS_CLK_SUN8I_R_CCU_H_
-#define _DT_BINDINGS_CLK_SUN8I_R_CCU_H_
-
-#define CLK_AR100 0
-
-#define CLK_APB0_PIO 3
-#define CLK_APB0_IR 4
-#define CLK_APB0_TIMER 5
-#define CLK_APB0_RSB 6
-#define CLK_APB0_UART 7
-/* 8 is reserved for CLK_APB0_W1 on A31 */
-#define CLK_APB0_I2C 9
-#define CLK_APB0_TWD 10
-
-#define CLK_IR 11
-
-#endif /* _DT_BINDINGS_CLK_SUN8I_R_CCU_H_ */
diff --git a/include/dt-bindings/clock/sun8i-r40-ccu.h b/include/dt-bindings/clock/sun8i-r40-ccu.h
deleted file mode 100644
index 4fa5f69..0000000
--- a/include/dt-bindings/clock/sun8i-r40-ccu.h
+++ /dev/null
@@ -1,187 +0,0 @@
-/*
- * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef _DT_BINDINGS_CLK_SUN8I_R40_H_
-#define _DT_BINDINGS_CLK_SUN8I_R40_H_
-
-#define CLK_CPU 24
-
-#define CLK_BUS_MIPI_DSI 29
-#define CLK_BUS_CE 30
-#define CLK_BUS_DMA 31
-#define CLK_BUS_MMC0 32
-#define CLK_BUS_MMC1 33
-#define CLK_BUS_MMC2 34
-#define CLK_BUS_MMC3 35
-#define CLK_BUS_NAND 36
-#define CLK_BUS_DRAM 37
-#define CLK_BUS_EMAC 38
-#define CLK_BUS_TS 39
-#define CLK_BUS_HSTIMER 40
-#define CLK_BUS_SPI0 41
-#define CLK_BUS_SPI1 42
-#define CLK_BUS_SPI2 43
-#define CLK_BUS_SPI3 44
-#define CLK_BUS_SATA 45
-#define CLK_BUS_OTG 46
-#define CLK_BUS_EHCI0 47
-#define CLK_BUS_EHCI1 48
-#define CLK_BUS_EHCI2 49
-#define CLK_BUS_OHCI0 50
-#define CLK_BUS_OHCI1 51
-#define CLK_BUS_OHCI2 52
-#define CLK_BUS_VE 53
-#define CLK_BUS_MP 54
-#define CLK_BUS_DEINTERLACE 55
-#define CLK_BUS_CSI0 56
-#define CLK_BUS_CSI1 57
-#define CLK_BUS_HDMI1 58
-#define CLK_BUS_HDMI0 59
-#define CLK_BUS_DE 60
-#define CLK_BUS_TVE0 61
-#define CLK_BUS_TVE1 62
-#define CLK_BUS_TVE_TOP 63
-#define CLK_BUS_GMAC 64
-#define CLK_BUS_GPU 65
-#define CLK_BUS_TVD0 66
-#define CLK_BUS_TVD1 67
-#define CLK_BUS_TVD2 68
-#define CLK_BUS_TVD3 69
-#define CLK_BUS_TVD_TOP 70
-#define CLK_BUS_TCON_LCD0 71
-#define CLK_BUS_TCON_LCD1 72
-#define CLK_BUS_TCON_TV0 73
-#define CLK_BUS_TCON_TV1 74
-#define CLK_BUS_TCON_TOP 75
-#define CLK_BUS_CODEC 76
-#define CLK_BUS_SPDIF 77
-#define CLK_BUS_AC97 78
-#define CLK_BUS_PIO 79
-#define CLK_BUS_IR0 80
-#define CLK_BUS_IR1 81
-#define CLK_BUS_THS 82
-#define CLK_BUS_KEYPAD 83
-#define CLK_BUS_I2S0 84
-#define CLK_BUS_I2S1 85
-#define CLK_BUS_I2S2 86
-#define CLK_BUS_I2C0 87
-#define CLK_BUS_I2C1 88
-#define CLK_BUS_I2C2 89
-#define CLK_BUS_I2C3 90
-#define CLK_BUS_CAN 91
-#define CLK_BUS_SCR 92
-#define CLK_BUS_PS20 93
-#define CLK_BUS_PS21 94
-#define CLK_BUS_I2C4 95
-#define CLK_BUS_UART0 96
-#define CLK_BUS_UART1 97
-#define CLK_BUS_UART2 98
-#define CLK_BUS_UART3 99
-#define CLK_BUS_UART4 100
-#define CLK_BUS_UART5 101
-#define CLK_BUS_UART6 102
-#define CLK_BUS_UART7 103
-#define CLK_BUS_DBG 104
-
-#define CLK_THS 105
-#define CLK_NAND 106
-#define CLK_MMC0 107
-#define CLK_MMC1 108
-#define CLK_MMC2 109
-#define CLK_MMC3 110
-#define CLK_TS 111
-#define CLK_CE 112
-#define CLK_SPI0 113
-#define CLK_SPI1 114
-#define CLK_SPI2 115
-#define CLK_SPI3 116
-#define CLK_I2S0 117
-#define CLK_I2S1 118
-#define CLK_I2S2 119
-#define CLK_AC97 120
-#define CLK_SPDIF 121
-#define CLK_KEYPAD 122
-#define CLK_SATA 123
-#define CLK_USB_PHY0 124
-#define CLK_USB_PHY1 125
-#define CLK_USB_PHY2 126
-#define CLK_USB_OHCI0 127
-#define CLK_USB_OHCI1 128
-#define CLK_USB_OHCI2 129
-#define CLK_IR0 130
-#define CLK_IR1 131
-
-#define CLK_DRAM_VE 133
-#define CLK_DRAM_CSI0 134
-#define CLK_DRAM_CSI1 135
-#define CLK_DRAM_TS 136
-#define CLK_DRAM_TVD 137
-#define CLK_DRAM_MP 138
-#define CLK_DRAM_DEINTERLACE 139
-#define CLK_DE 140
-#define CLK_MP 141
-#define CLK_TCON_LCD0 142
-#define CLK_TCON_LCD1 143
-#define CLK_TCON_TV0 144
-#define CLK_TCON_TV1 145
-#define CLK_DEINTERLACE 146
-#define CLK_CSI1_MCLK 147
-#define CLK_CSI_SCLK 148
-#define CLK_CSI0_MCLK 149
-#define CLK_VE 150
-#define CLK_CODEC 151
-#define CLK_AVS 152
-#define CLK_HDMI 153
-#define CLK_HDMI_SLOW 154
-
-#define CLK_DSI_DPHY 156
-#define CLK_TVE0 157
-#define CLK_TVE1 158
-#define CLK_TVD0 159
-#define CLK_TVD1 160
-#define CLK_TVD2 161
-#define CLK_TVD3 162
-#define CLK_GPU 163
-#define CLK_OUTA 164
-#define CLK_OUTB 165
-
-#endif /* _DT_BINDINGS_CLK_SUN8I_R40_H_ */
diff --git a/include/dt-bindings/clock/sun8i-tcon-top.h b/include/dt-bindings/clock/sun8i-tcon-top.h
deleted file mode 100644
index 25164d7..0000000
--- a/include/dt-bindings/clock/sun8i-tcon-top.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
-/* Copyright (C) 2018 Jernej Skrabec <jernej.skrabec@siol.net> */
-
-#ifndef _DT_BINDINGS_CLOCK_SUN8I_TCON_TOP_H_
-#define _DT_BINDINGS_CLOCK_SUN8I_TCON_TOP_H_
-
-#define CLK_TCON_TOP_TV0 0
-#define CLK_TCON_TOP_TV1 1
-#define CLK_TCON_TOP_DSI 2
-
-#endif /* _DT_BINDINGS_CLOCK_SUN8I_TCON_TOP_H_ */
diff --git a/include/dt-bindings/clock/sun8i-v3s-ccu.h b/include/dt-bindings/clock/sun8i-v3s-ccu.h
deleted file mode 100644
index c0d5d55..0000000
--- a/include/dt-bindings/clock/sun8i-v3s-ccu.h
+++ /dev/null
@@ -1,107 +0,0 @@
-/*
- * Copyright (c) 2016 Icenowy Zheng <icenowy@aosc.xyz>
- *
- * Based on sun8i-h3-ccu.h, which is:
- * Copyright (C) 2016 Maxime Ripard <maxime.ripard@free-electrons.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef _DT_BINDINGS_CLK_SUN8I_V3S_H_
-#define _DT_BINDINGS_CLK_SUN8I_V3S_H_
-
-#define CLK_CPU 14
-
-#define CLK_BUS_CE 20
-#define CLK_BUS_DMA 21
-#define CLK_BUS_MMC0 22
-#define CLK_BUS_MMC1 23
-#define CLK_BUS_MMC2 24
-#define CLK_BUS_DRAM 25
-#define CLK_BUS_EMAC 26
-#define CLK_BUS_HSTIMER 27
-#define CLK_BUS_SPI0 28
-#define CLK_BUS_OTG 29
-#define CLK_BUS_EHCI0 30
-#define CLK_BUS_OHCI0 31
-#define CLK_BUS_VE 32
-#define CLK_BUS_TCON0 33
-#define CLK_BUS_CSI 34
-#define CLK_BUS_DE 35
-#define CLK_BUS_CODEC 36
-#define CLK_BUS_PIO 37
-#define CLK_BUS_I2C0 38
-#define CLK_BUS_I2C1 39
-#define CLK_BUS_UART0 40
-#define CLK_BUS_UART1 41
-#define CLK_BUS_UART2 42
-#define CLK_BUS_EPHY 43
-#define CLK_BUS_DBG 44
-
-#define CLK_MMC0 45
-#define CLK_MMC0_SAMPLE 46
-#define CLK_MMC0_OUTPUT 47
-#define CLK_MMC1 48
-#define CLK_MMC1_SAMPLE 49
-#define CLK_MMC1_OUTPUT 50
-#define CLK_MMC2 51
-#define CLK_MMC2_SAMPLE 52
-#define CLK_MMC2_OUTPUT 53
-#define CLK_CE 54
-#define CLK_SPI0 55
-#define CLK_USB_PHY0 56
-#define CLK_USB_OHCI0 57
-
-#define CLK_DRAM_VE 59
-#define CLK_DRAM_CSI 60
-#define CLK_DRAM_EHCI 61
-#define CLK_DRAM_OHCI 62
-#define CLK_DE 63
-#define CLK_TCON0 64
-#define CLK_CSI_MISC 65
-#define CLK_CSI0_MCLK 66
-#define CLK_CSI1_SCLK 67
-#define CLK_CSI1_MCLK 68
-#define CLK_VE 69
-#define CLK_AC_DIG 70
-#define CLK_AVS 71
-
-#define CLK_MIPI_CSI 73
-
-#endif /* _DT_BINDINGS_CLK_SUN8I_V3S_H_ */
diff --git a/include/dt-bindings/clock/sun9i-a80-ccu.h b/include/dt-bindings/clock/sun9i-a80-ccu.h
deleted file mode 100644
index 6ea1492..0000000
--- a/include/dt-bindings/clock/sun9i-a80-ccu.h
+++ /dev/null
@@ -1,162 +0,0 @@
-/*
- * Copyright (C) 2016 Chen-Yu Tsai <wens@csie.org>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef _DT_BINDINGS_CLOCK_SUN9I_A80_CCU_H_
-#define _DT_BINDINGS_CLOCK_SUN9I_A80_CCU_H_
-
-#define CLK_PLL_AUDIO 2
-#define CLK_PLL_PERIPH0 3
-
-#define CLK_C0CPUX 12
-#define CLK_C1CPUX 13
-
-#define CLK_OUT_A 27
-#define CLK_OUT_B 28
-
-#define CLK_NAND0_0 29
-#define CLK_NAND0_1 30
-#define CLK_NAND1_0 31
-#define CLK_NAND1_1 32
-#define CLK_MMC0 33
-#define CLK_MMC0_SAMPLE 34
-#define CLK_MMC0_OUTPUT 35
-#define CLK_MMC1 36
-#define CLK_MMC1_SAMPLE 37
-#define CLK_MMC1_OUTPUT 38
-#define CLK_MMC2 39
-#define CLK_MMC2_SAMPLE 40
-#define CLK_MMC2_OUTPUT 41
-#define CLK_MMC3 42
-#define CLK_MMC3_SAMPLE 43
-#define CLK_MMC3_OUTPUT 44
-#define CLK_TS 45
-#define CLK_SS 46
-#define CLK_SPI0 47
-#define CLK_SPI1 48
-#define CLK_SPI2 49
-#define CLK_SPI3 50
-#define CLK_I2S0 51
-#define CLK_I2S1 52
-#define CLK_SPDIF 53
-#define CLK_SDRAM 54
-#define CLK_DE 55
-#define CLK_EDP 56
-#define CLK_MP 57
-#define CLK_LCD0 58
-#define CLK_LCD1 59
-#define CLK_MIPI_DSI0 60
-#define CLK_MIPI_DSI1 61
-#define CLK_HDMI 62
-#define CLK_HDMI_SLOW 63
-#define CLK_MIPI_CSI 64
-#define CLK_CSI_ISP 65
-#define CLK_CSI_MISC 66
-#define CLK_CSI0_MCLK 67
-#define CLK_CSI1_MCLK 68
-#define CLK_FD 69
-#define CLK_VE 70
-#define CLK_AVS 71
-#define CLK_GPU_CORE 72
-#define CLK_GPU_MEMORY 73
-#define CLK_GPU_AXI 74
-#define CLK_SATA 75
-#define CLK_AC97 76
-#define CLK_MIPI_HSI 77
-#define CLK_GPADC 78
-#define CLK_CIR_TX 79
-
-#define CLK_BUS_FD 80
-#define CLK_BUS_VE 81
-#define CLK_BUS_GPU_CTRL 82
-#define CLK_BUS_SS 83
-#define CLK_BUS_MMC 84
-#define CLK_BUS_NAND0 85
-#define CLK_BUS_NAND1 86
-#define CLK_BUS_SDRAM 87
-#define CLK_BUS_MIPI_HSI 88
-#define CLK_BUS_SATA 89
-#define CLK_BUS_TS 90
-#define CLK_BUS_SPI0 91
-#define CLK_BUS_SPI1 92
-#define CLK_BUS_SPI2 93
-#define CLK_BUS_SPI3 94
-
-#define CLK_BUS_OTG 95
-#define CLK_BUS_USB 96
-#define CLK_BUS_GMAC 97
-#define CLK_BUS_MSGBOX 98
-#define CLK_BUS_SPINLOCK 99
-#define CLK_BUS_HSTIMER 100
-#define CLK_BUS_DMA 101
-
-#define CLK_BUS_LCD0 102
-#define CLK_BUS_LCD1 103
-#define CLK_BUS_EDP 104
-#define CLK_BUS_CSI 105
-#define CLK_BUS_HDMI 106
-#define CLK_BUS_DE 107
-#define CLK_BUS_MP 108
-#define CLK_BUS_MIPI_DSI 109
-
-#define CLK_BUS_SPDIF 110
-#define CLK_BUS_PIO 111
-#define CLK_BUS_AC97 112
-#define CLK_BUS_I2S0 113
-#define CLK_BUS_I2S1 114
-#define CLK_BUS_LRADC 115
-#define CLK_BUS_GPADC 116
-#define CLK_BUS_TWD 117
-#define CLK_BUS_CIR_TX 118
-
-#define CLK_BUS_I2C0 119
-#define CLK_BUS_I2C1 120
-#define CLK_BUS_I2C2 121
-#define CLK_BUS_I2C3 122
-#define CLK_BUS_I2C4 123
-#define CLK_BUS_UART0 124
-#define CLK_BUS_UART1 125
-#define CLK_BUS_UART2 126
-#define CLK_BUS_UART3 127
-#define CLK_BUS_UART4 128
-#define CLK_BUS_UART5 129
-
-#endif /* _DT_BINDINGS_CLOCK_SUN9I_A80_CCU_H_ */
diff --git a/include/dt-bindings/clock/sun9i-a80-de.h b/include/dt-bindings/clock/sun9i-a80-de.h
deleted file mode 100644
index 3dad6c3..0000000
--- a/include/dt-bindings/clock/sun9i-a80-de.h
+++ /dev/null
@@ -1,80 +0,0 @@
-/*
- * Copyright (C) 2016 Chen-Yu Tsai <wens@csie.org>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef _DT_BINDINGS_CLOCK_SUN9I_A80_DE_H_
-#define _DT_BINDINGS_CLOCK_SUN9I_A80_DE_H_
-
-#define CLK_FE0 0
-#define CLK_FE1 1
-#define CLK_FE2 2
-#define CLK_IEP_DEU0 3
-#define CLK_IEP_DEU1 4
-#define CLK_BE0 5
-#define CLK_BE1 6
-#define CLK_BE2 7
-#define CLK_IEP_DRC0 8
-#define CLK_IEP_DRC1 9
-#define CLK_MERGE 10
-
-#define CLK_DRAM_FE0 11
-#define CLK_DRAM_FE1 12
-#define CLK_DRAM_FE2 13
-#define CLK_DRAM_DEU0 14
-#define CLK_DRAM_DEU1 15
-#define CLK_DRAM_BE0 16
-#define CLK_DRAM_BE1 17
-#define CLK_DRAM_BE2 18
-#define CLK_DRAM_DRC0 19
-#define CLK_DRAM_DRC1 20
-
-#define CLK_BUS_FE0 21
-#define CLK_BUS_FE1 22
-#define CLK_BUS_FE2 23
-#define CLK_BUS_DEU0 24
-#define CLK_BUS_DEU1 25
-#define CLK_BUS_BE0 26
-#define CLK_BUS_BE1 27
-#define CLK_BUS_BE2 28
-#define CLK_BUS_DRC0 29
-#define CLK_BUS_DRC1 30
-
-#endif /* _DT_BINDINGS_CLOCK_SUN9I_A80_DE_H_ */
diff --git a/include/dt-bindings/clock/sun9i-a80-usb.h b/include/dt-bindings/clock/sun9i-a80-usb.h
deleted file mode 100644
index 783a60d..0000000
--- a/include/dt-bindings/clock/sun9i-a80-usb.h
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * Copyright (C) 2016 Chen-Yu Tsai <wens@csie.org>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef _DT_BINDINGS_CLOCK_SUN9I_A80_USB_H_
-#define _DT_BINDINGS_CLOCK_SUN9I_A80_USB_H_
-
-#define CLK_BUS_HCI0 0
-#define CLK_USB_OHCI0 1
-#define CLK_BUS_HCI1 2
-#define CLK_BUS_HCI2 3
-#define CLK_USB_OHCI2 4
-
-#define CLK_USB0_PHY 5
-#define CLK_USB1_HSIC 6
-#define CLK_USB1_PHY 7
-#define CLK_USB2_HSIC 8
-#define CLK_USB2_PHY 9
-#define CLK_USB_HSIC 10
-
-#endif /* _DT_BINDINGS_CLOCK_SUN9I_A80_USB_H_ */
diff --git a/include/dt-bindings/clock/tegra114-car.h b/include/dt-bindings/clock/tegra114-car.h
deleted file mode 100644
index 534c03f..0000000
--- a/include/dt-bindings/clock/tegra114-car.h
+++ /dev/null
@@ -1,343 +0,0 @@
-/*
- * This header provides constants for binding nvidia,tegra114-car.
- *
- * The first 160 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
- * registers. These IDs often match those in the CAR's RST_DEVICES registers,
- * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
- * this case, those clocks are assigned IDs above 160 in order to highlight
- * this issue. Implementations that interpret these clock IDs as bit values
- * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
- * explicitly handle these special cases.
- *
- * The balance of the clocks controlled by the CAR are assigned IDs of 160 and
- * above.
- */
-
-#ifndef _DT_BINDINGS_CLOCK_TEGRA114_CAR_H
-#define _DT_BINDINGS_CLOCK_TEGRA114_CAR_H
-
-/* 0 */
-/* 1 */
-/* 2 */
-/* 3 */
-#define TEGRA114_CLK_RTC 4
-#define TEGRA114_CLK_TIMER 5
-#define TEGRA114_CLK_UARTA 6
-/* 7 (register bit affects uartb and vfir) */
-/* 8 */
-#define TEGRA114_CLK_SDMMC2 9
-/* 10 (register bit affects spdif_in and spdif_out) */
-#define TEGRA114_CLK_I2S1 11
-#define TEGRA114_CLK_I2C1 12
-#define TEGRA114_CLK_NDFLASH 13
-#define TEGRA114_CLK_SDMMC1 14
-#define TEGRA114_CLK_SDMMC4 15
-/* 16 */
-#define TEGRA114_CLK_PWM 17
-#define TEGRA114_CLK_I2S2 18
-#define TEGRA114_CLK_EPP 19
-/* 20 (register bit affects vi and vi_sensor) */
-#define TEGRA114_CLK_GR2D 21
-#define TEGRA114_CLK_USBD 22
-#define TEGRA114_CLK_ISP 23
-#define TEGRA114_CLK_GR3D 24
-/* 25 */
-#define TEGRA114_CLK_DISP2 26
-#define TEGRA114_CLK_DISP1 27
-#define TEGRA114_CLK_HOST1X 28
-#define TEGRA114_CLK_VCP 29
-#define TEGRA114_CLK_I2S0 30
-/* 31 */
-
-#define TEGRA114_CLK_MC 32
-/* 33 */
-#define TEGRA114_CLK_APBDMA 34
-/* 35 */
-#define TEGRA114_CLK_KBC 36
-/* 37 */
-/* 38 */
-/* 39 (register bit affects fuse and fuse_burn) */
-#define TEGRA114_CLK_KFUSE 40
-#define TEGRA114_CLK_SBC1 41
-#define TEGRA114_CLK_NOR 42
-/* 43 */
-#define TEGRA114_CLK_SBC2 44
-/* 45 */
-#define TEGRA114_CLK_SBC3 46
-#define TEGRA114_CLK_I2C5 47
-#define TEGRA114_CLK_DSIA 48
-/* 49 */
-#define TEGRA114_CLK_MIPI 50
-#define TEGRA114_CLK_HDMI 51
-#define TEGRA114_CLK_CSI 52
-/* 53 */
-#define TEGRA114_CLK_I2C2 54
-#define TEGRA114_CLK_UARTC 55
-#define TEGRA114_CLK_MIPI_CAL 56
-#define TEGRA114_CLK_EMC 57
-#define TEGRA114_CLK_USB2 58
-#define TEGRA114_CLK_USB3 59
-/* 60 */
-#define TEGRA114_CLK_VDE 61
-#define TEGRA114_CLK_BSEA 62
-#define TEGRA114_CLK_BSEV 63
-
-/* 64 */
-#define TEGRA114_CLK_UARTD 65
-/* 66 */
-#define TEGRA114_CLK_I2C3 67
-#define TEGRA114_CLK_SBC4 68
-#define TEGRA114_CLK_SDMMC3 69
-/* 70 */
-#define TEGRA114_CLK_OWR 71
-/* 72 */
-#define TEGRA114_CLK_CSITE 73
-/* 74 */
-/* 75 */
-#define TEGRA114_CLK_LA 76
-#define TEGRA114_CLK_TRACE 77
-#define TEGRA114_CLK_SOC_THERM 78
-#define TEGRA114_CLK_DTV 79
-#define TEGRA114_CLK_NDSPEED 80
-#define TEGRA114_CLK_I2CSLOW 81
-#define TEGRA114_CLK_DSIB 82
-#define TEGRA114_CLK_TSEC 83
-/* 84 */
-/* 85 */
-/* 86 */
-/* 87 */
-/* 88 */
-#define TEGRA114_CLK_XUSB_HOST 89
-/* 90 */
-#define TEGRA114_CLK_MSENC 91
-#define TEGRA114_CLK_CSUS 92
-/* 93 */
-/* 94 */
-/* 95 (bit affects xusb_dev and xusb_dev_src) */
-
-/* 96 */
-/* 97 */
-/* 98 */
-#define TEGRA114_CLK_MSELECT 99
-#define TEGRA114_CLK_TSENSOR 100
-#define TEGRA114_CLK_I2S3 101
-#define TEGRA114_CLK_I2S4 102
-#define TEGRA114_CLK_I2C4 103
-#define TEGRA114_CLK_SBC5 104
-#define TEGRA114_CLK_SBC6 105
-#define TEGRA114_CLK_D_AUDIO 106
-#define TEGRA114_CLK_APBIF 107
-#define TEGRA114_CLK_DAM0 108
-#define TEGRA114_CLK_DAM1 109
-#define TEGRA114_CLK_DAM2 110
-#define TEGRA114_CLK_HDA2CODEC_2X 111
-/* 112 */
-#define TEGRA114_CLK_AUDIO0_2X 113
-#define TEGRA114_CLK_AUDIO1_2X 114
-#define TEGRA114_CLK_AUDIO2_2X 115
-#define TEGRA114_CLK_AUDIO3_2X 116
-#define TEGRA114_CLK_AUDIO4_2X 117
-#define TEGRA114_CLK_SPDIF_2X 118
-#define TEGRA114_CLK_ACTMON 119
-#define TEGRA114_CLK_EXTERN1 120
-#define TEGRA114_CLK_EXTERN2 121
-#define TEGRA114_CLK_EXTERN3 122
-/* 123 */
-/* 124 */
-#define TEGRA114_CLK_HDA 125
-/* 126 */
-#define TEGRA114_CLK_SE 127
-
-#define TEGRA114_CLK_HDA2HDMI 128
-/* 129 */
-/* 130 */
-/* 131 */
-/* 132 */
-/* 133 */
-/* 134 */
-/* 135 */
-/* 136 */
-/* 137 */
-/* 138 */
-/* 139 */
-/* 140 */
-/* 141 */
-/* 142 */
-/* 143 (bit affects xusb_falcon_src, xusb_fs_src, */
-/* xusb_host_src and xusb_ss_src) */
-#define TEGRA114_CLK_CILAB 144
-#define TEGRA114_CLK_CILCD 145
-#define TEGRA114_CLK_CILE 146
-#define TEGRA114_CLK_DSIALP 147
-#define TEGRA114_CLK_DSIBLP 148
-/* 149 */
-#define TEGRA114_CLK_DDS 150
-/* 151 */
-#define TEGRA114_CLK_DP2 152
-#define TEGRA114_CLK_AMX 153
-#define TEGRA114_CLK_ADX 154
-/* 155 (bit affects dfll_ref and dfll_soc) */
-#define TEGRA114_CLK_XUSB_SS 156
-/* 157 */
-/* 158 */
-/* 159 */
-
-/* 160 */
-/* 161 */
-/* 162 */
-/* 163 */
-/* 164 */
-/* 165 */
-/* 166 */
-/* 167 */
-/* 168 */
-/* 169 */
-/* 170 */
-/* 171 */
-/* 172 */
-/* 173 */
-/* 174 */
-/* 175 */
-/* 176 */
-/* 177 */
-/* 178 */
-/* 179 */
-/* 180 */
-/* 181 */
-/* 182 */
-/* 183 */
-/* 184 */
-/* 185 */
-/* 186 */
-/* 187 */
-/* 188 */
-/* 189 */
-/* 190 */
-/* 191 */
-
-#define TEGRA114_CLK_UARTB 192
-#define TEGRA114_CLK_VFIR 193
-#define TEGRA114_CLK_SPDIF_IN 194
-#define TEGRA114_CLK_SPDIF_OUT 195
-#define TEGRA114_CLK_VI 196
-#define TEGRA114_CLK_VI_SENSOR 197
-#define TEGRA114_CLK_FUSE 198
-#define TEGRA114_CLK_FUSE_BURN 199
-#define TEGRA114_CLK_CLK_32K 200
-#define TEGRA114_CLK_CLK_M 201
-#define TEGRA114_CLK_CLK_M_DIV2 202
-#define TEGRA114_CLK_CLK_M_DIV4 203
-#define TEGRA114_CLK_PLL_REF 204
-#define TEGRA114_CLK_PLL_C 205
-#define TEGRA114_CLK_PLL_C_OUT1 206
-#define TEGRA114_CLK_PLL_C2 207
-#define TEGRA114_CLK_PLL_C3 208
-#define TEGRA114_CLK_PLL_M 209
-#define TEGRA114_CLK_PLL_M_OUT1 210
-#define TEGRA114_CLK_PLL_P 211
-#define TEGRA114_CLK_PLL_P_OUT1 212
-#define TEGRA114_CLK_PLL_P_OUT2 213
-#define TEGRA114_CLK_PLL_P_OUT3 214
-#define TEGRA114_CLK_PLL_P_OUT4 215
-#define TEGRA114_CLK_PLL_A 216
-#define TEGRA114_CLK_PLL_A_OUT0 217
-#define TEGRA114_CLK_PLL_D 218
-#define TEGRA114_CLK_PLL_D_OUT0 219
-#define TEGRA114_CLK_PLL_D2 220
-#define TEGRA114_CLK_PLL_D2_OUT0 221
-#define TEGRA114_CLK_PLL_U 222
-#define TEGRA114_CLK_PLL_U_480M 223
-
-#define TEGRA114_CLK_PLL_U_60M 224
-#define TEGRA114_CLK_PLL_U_48M 225
-#define TEGRA114_CLK_PLL_U_12M 226
-#define TEGRA114_CLK_PLL_X 227
-#define TEGRA114_CLK_PLL_X_OUT0 228
-#define TEGRA114_CLK_PLL_RE_VCO 229
-#define TEGRA114_CLK_PLL_RE_OUT 230
-#define TEGRA114_CLK_PLL_E_OUT0 231
-#define TEGRA114_CLK_SPDIF_IN_SYNC 232
-#define TEGRA114_CLK_I2S0_SYNC 233
-#define TEGRA114_CLK_I2S1_SYNC 234
-#define TEGRA114_CLK_I2S2_SYNC 235
-#define TEGRA114_CLK_I2S3_SYNC 236
-#define TEGRA114_CLK_I2S4_SYNC 237
-#define TEGRA114_CLK_VIMCLK_SYNC 238
-#define TEGRA114_CLK_AUDIO0 239
-#define TEGRA114_CLK_AUDIO1 240
-#define TEGRA114_CLK_AUDIO2 241
-#define TEGRA114_CLK_AUDIO3 242
-#define TEGRA114_CLK_AUDIO4 243
-#define TEGRA114_CLK_SPDIF 244
-#define TEGRA114_CLK_CLK_OUT_1 245
-#define TEGRA114_CLK_CLK_OUT_2 246
-#define TEGRA114_CLK_CLK_OUT_3 247
-#define TEGRA114_CLK_BLINK 248
-/* 249 */
-/* 250 */
-/* 251 */
-#define TEGRA114_CLK_XUSB_HOST_SRC 252
-#define TEGRA114_CLK_XUSB_FALCON_SRC 253
-#define TEGRA114_CLK_XUSB_FS_SRC 254
-#define TEGRA114_CLK_XUSB_SS_SRC 255
-
-#define TEGRA114_CLK_XUSB_DEV_SRC 256
-#define TEGRA114_CLK_XUSB_DEV 257
-#define TEGRA114_CLK_XUSB_HS_SRC 258
-#define TEGRA114_CLK_SCLK 259
-#define TEGRA114_CLK_HCLK 260
-#define TEGRA114_CLK_PCLK 261
-#define TEGRA114_CLK_CCLK_G 262
-#define TEGRA114_CLK_CCLK_LP 263
-#define TEGRA114_CLK_DFLL_REF 264
-#define TEGRA114_CLK_DFLL_SOC 265
-/* 266 */
-/* 267 */
-/* 268 */
-/* 269 */
-/* 270 */
-/* 271 */
-/* 272 */
-/* 273 */
-/* 274 */
-/* 275 */
-/* 276 */
-/* 277 */
-/* 278 */
-/* 279 */
-/* 280 */
-/* 281 */
-/* 282 */
-/* 283 */
-/* 284 */
-/* 285 */
-/* 286 */
-/* 287 */
-
-/* 288 */
-/* 289 */
-/* 290 */
-/* 291 */
-/* 292 */
-/* 293 */
-/* 294 */
-/* 295 */
-/* 296 */
-/* 297 */
-/* 298 */
-/* 299 */
-#define TEGRA114_CLK_AUDIO0_MUX 300
-#define TEGRA114_CLK_AUDIO1_MUX 301
-#define TEGRA114_CLK_AUDIO2_MUX 302
-#define TEGRA114_CLK_AUDIO3_MUX 303
-#define TEGRA114_CLK_AUDIO4_MUX 304
-#define TEGRA114_CLK_SPDIF_MUX 305
-#define TEGRA114_CLK_CLK_OUT_1_MUX 306
-#define TEGRA114_CLK_CLK_OUT_2_MUX 307
-#define TEGRA114_CLK_CLK_OUT_3_MUX 308
-#define TEGRA114_CLK_DSIA_MUX 309
-#define TEGRA114_CLK_DSIB_MUX 310
-#define TEGRA114_CLK_XUSB_SS_DIV2 311
-#define TEGRA114_CLK_CLK_MAX 312
-
-#endif /* _DT_BINDINGS_CLOCK_TEGRA114_CAR_H */
diff --git a/include/dt-bindings/clock/tegra124-car-common.h b/include/dt-bindings/clock/tegra124-car-common.h
deleted file mode 100644
index a215609..0000000
--- a/include/dt-bindings/clock/tegra124-car-common.h
+++ /dev/null
@@ -1,345 +0,0 @@
-/*
- * This header provides constants for binding nvidia,tegra124-car or
- * nvidia,tegra132-car.
- *
- * The first 192 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
- * registers. These IDs often match those in the CAR's RST_DEVICES registers,
- * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
- * this case, those clocks are assigned IDs above 185 in order to highlight
- * this issue. Implementations that interpret these clock IDs as bit values
- * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
- * explicitly handle these special cases.
- *
- * The balance of the clocks controlled by the CAR are assigned IDs of 185 and
- * above.
- */
-
-#ifndef _DT_BINDINGS_CLOCK_TEGRA124_CAR_COMMON_H
-#define _DT_BINDINGS_CLOCK_TEGRA124_CAR_COMMON_H
-
-/* 0 */
-/* 1 */
-/* 2 */
-#define TEGRA124_CLK_ISPB 3
-#define TEGRA124_CLK_RTC 4
-#define TEGRA124_CLK_TIMER 5
-#define TEGRA124_CLK_UARTA 6
-/* 7 (register bit affects uartb and vfir) */
-/* 8 */
-#define TEGRA124_CLK_SDMMC2 9
-/* 10 (register bit affects spdif_in and spdif_out) */
-#define TEGRA124_CLK_I2S1 11
-#define TEGRA124_CLK_I2C1 12
-/* 13 */
-#define TEGRA124_CLK_SDMMC1 14
-#define TEGRA124_CLK_SDMMC4 15
-/* 16 */
-#define TEGRA124_CLK_PWM 17
-#define TEGRA124_CLK_I2S2 18
-/* 20 (register bit affects vi and vi_sensor) */
-/* 21 */
-#define TEGRA124_CLK_USBD 22
-#define TEGRA124_CLK_ISP 23
-/* 26 */
-/* 25 */
-#define TEGRA124_CLK_DISP2 26
-#define TEGRA124_CLK_DISP1 27
-#define TEGRA124_CLK_HOST1X 28
-#define TEGRA124_CLK_VCP 29
-#define TEGRA124_CLK_I2S0 30
-/* 31 */
-
-#define TEGRA124_CLK_MC 32
-/* 33 */
-#define TEGRA124_CLK_APBDMA 34
-/* 35 */
-#define TEGRA124_CLK_KBC 36
-/* 37 */
-/* 38 */
-/* 39 (register bit affects fuse and fuse_burn) */
-#define TEGRA124_CLK_KFUSE 40
-#define TEGRA124_CLK_SBC1 41
-#define TEGRA124_CLK_NOR 42
-/* 43 */
-#define TEGRA124_CLK_SBC2 44
-/* 45 */
-#define TEGRA124_CLK_SBC3 46
-#define TEGRA124_CLK_I2C5 47
-#define TEGRA124_CLK_DSIA 48
-/* 49 */
-#define TEGRA124_CLK_MIPI 50
-#define TEGRA124_CLK_HDMI 51
-#define TEGRA124_CLK_CSI 52
-/* 53 */
-#define TEGRA124_CLK_I2C2 54
-#define TEGRA124_CLK_UARTC 55
-#define TEGRA124_CLK_MIPI_CAL 56
-#define TEGRA124_CLK_EMC 57
-#define TEGRA124_CLK_USB2 58
-#define TEGRA124_CLK_USB3 59
-/* 60 */
-#define TEGRA124_CLK_VDE 61
-#define TEGRA124_CLK_BSEA 62
-#define TEGRA124_CLK_BSEV 63
-
-/* 64 */
-#define TEGRA124_CLK_UARTD 65
-/* 66 */
-#define TEGRA124_CLK_I2C3 67
-#define TEGRA124_CLK_SBC4 68
-#define TEGRA124_CLK_SDMMC3 69
-#define TEGRA124_CLK_PCIE 70
-#define TEGRA124_CLK_OWR 71
-#define TEGRA124_CLK_AFI 72
-#define TEGRA124_CLK_CSITE 73
-/* 74 */
-/* 75 */
-#define TEGRA124_CLK_LA 76
-#define TEGRA124_CLK_TRACE 77
-#define TEGRA124_CLK_SOC_THERM 78
-#define TEGRA124_CLK_DTV 79
-/* 80 */
-#define TEGRA124_CLK_I2CSLOW 81
-#define TEGRA124_CLK_DSIB 82
-#define TEGRA124_CLK_TSEC 83
-/* 84 */
-/* 85 */
-/* 86 */
-/* 87 */
-/* 88 */
-#define TEGRA124_CLK_XUSB_HOST 89
-/* 90 */
-#define TEGRA124_CLK_MSENC 91
-#define TEGRA124_CLK_CSUS 92
-/* 93 */
-/* 94 */
-/* 95 (bit affects xusb_dev and xusb_dev_src) */
-
-/* 96 */
-/* 97 */
-/* 98 */
-#define TEGRA124_CLK_MSELECT 99
-#define TEGRA124_CLK_TSENSOR 100
-#define TEGRA124_CLK_I2S3 101
-#define TEGRA124_CLK_I2S4 102
-#define TEGRA124_CLK_I2C4 103
-#define TEGRA124_CLK_SBC5 104
-#define TEGRA124_CLK_SBC6 105
-#define TEGRA124_CLK_D_AUDIO 106
-#define TEGRA124_CLK_APBIF 107
-#define TEGRA124_CLK_DAM0 108
-#define TEGRA124_CLK_DAM1 109
-#define TEGRA124_CLK_DAM2 110
-#define TEGRA124_CLK_HDA2CODEC_2X 111
-/* 112 */
-#define TEGRA124_CLK_AUDIO0_2X 113
-#define TEGRA124_CLK_AUDIO1_2X 114
-#define TEGRA124_CLK_AUDIO2_2X 115
-#define TEGRA124_CLK_AUDIO3_2X 116
-#define TEGRA124_CLK_AUDIO4_2X 117
-#define TEGRA124_CLK_SPDIF_2X 118
-#define TEGRA124_CLK_ACTMON 119
-#define TEGRA124_CLK_EXTERN1 120
-#define TEGRA124_CLK_EXTERN2 121
-#define TEGRA124_CLK_EXTERN3 122
-#define TEGRA124_CLK_SATA_OOB 123
-#define TEGRA124_CLK_SATA 124
-#define TEGRA124_CLK_HDA 125
-/* 126 */
-#define TEGRA124_CLK_SE 127
-
-#define TEGRA124_CLK_HDA2HDMI 128
-#define TEGRA124_CLK_SATA_COLD 129
-/* 130 */
-/* 131 */
-/* 132 */
-/* 133 */
-/* 134 */
-/* 135 */
-/* 136 */
-/* 137 */
-/* 138 */
-/* 139 */
-/* 140 */
-/* 141 */
-/* 142 */
-/* 143 (bit affects xusb_falcon_src, xusb_fs_src, */
-/* xusb_host_src and xusb_ss_src) */
-#define TEGRA124_CLK_CILAB 144
-#define TEGRA124_CLK_CILCD 145
-#define TEGRA124_CLK_CILE 146
-#define TEGRA124_CLK_DSIALP 147
-#define TEGRA124_CLK_DSIBLP 148
-#define TEGRA124_CLK_ENTROPY 149
-#define TEGRA124_CLK_DDS 150
-/* 151 */
-#define TEGRA124_CLK_DP2 152
-#define TEGRA124_CLK_AMX 153
-#define TEGRA124_CLK_ADX 154
-/* 155 (bit affects dfll_ref and dfll_soc) */
-#define TEGRA124_CLK_XUSB_SS 156
-/* 157 */
-/* 158 */
-/* 159 */
-
-/* 160 */
-/* 161 */
-/* 162 */
-/* 163 */
-/* 164 */
-/* 165 */
-#define TEGRA124_CLK_I2C6 166
-/* 167 */
-/* 168 */
-/* 169 */
-/* 170 */
-#define TEGRA124_CLK_VIM2_CLK 171
-/* 172 */
-/* 173 */
-/* 174 */
-/* 175 */
-#define TEGRA124_CLK_HDMI_AUDIO 176
-#define TEGRA124_CLK_CLK72MHZ 177
-#define TEGRA124_CLK_VIC03 178
-/* 179 */
-#define TEGRA124_CLK_ADX1 180
-#define TEGRA124_CLK_DPAUX 181
-#define TEGRA124_CLK_SOR0 182
-/* 183 */
-#define TEGRA124_CLK_GPU 184
-#define TEGRA124_CLK_AMX1 185
-/* 186 */
-/* 187 */
-/* 188 */
-/* 189 */
-/* 190 */
-/* 191 */
-#define TEGRA124_CLK_UARTB 192
-#define TEGRA124_CLK_VFIR 193
-#define TEGRA124_CLK_SPDIF_IN 194
-#define TEGRA124_CLK_SPDIF_OUT 195
-#define TEGRA124_CLK_VI 196
-#define TEGRA124_CLK_VI_SENSOR 197
-#define TEGRA124_CLK_FUSE 198
-#define TEGRA124_CLK_FUSE_BURN 199
-#define TEGRA124_CLK_CLK_32K 200
-#define TEGRA124_CLK_CLK_M 201
-#define TEGRA124_CLK_CLK_M_DIV2 202
-#define TEGRA124_CLK_CLK_M_DIV4 203
-#define TEGRA124_CLK_PLL_REF 204
-#define TEGRA124_CLK_PLL_C 205
-#define TEGRA124_CLK_PLL_C_OUT1 206
-#define TEGRA124_CLK_PLL_C2 207
-#define TEGRA124_CLK_PLL_C3 208
-#define TEGRA124_CLK_PLL_M 209
-#define TEGRA124_CLK_PLL_M_OUT1 210
-#define TEGRA124_CLK_PLL_P 211
-#define TEGRA124_CLK_PLL_P_OUT1 212
-#define TEGRA124_CLK_PLL_P_OUT2 213
-#define TEGRA124_CLK_PLL_P_OUT3 214
-#define TEGRA124_CLK_PLL_P_OUT4 215
-#define TEGRA124_CLK_PLL_A 216
-#define TEGRA124_CLK_PLL_A_OUT0 217
-#define TEGRA124_CLK_PLL_D 218
-#define TEGRA124_CLK_PLL_D_OUT0 219
-#define TEGRA124_CLK_PLL_D2 220
-#define TEGRA124_CLK_PLL_D2_OUT0 221
-#define TEGRA124_CLK_PLL_U 222
-#define TEGRA124_CLK_PLL_U_480M 223
-
-#define TEGRA124_CLK_PLL_U_60M 224
-#define TEGRA124_CLK_PLL_U_48M 225
-#define TEGRA124_CLK_PLL_U_12M 226
-/* 227 */
-/* 228 */
-#define TEGRA124_CLK_PLL_RE_VCO 229
-#define TEGRA124_CLK_PLL_RE_OUT 230
-#define TEGRA124_CLK_PLL_E 231
-#define TEGRA124_CLK_SPDIF_IN_SYNC 232
-#define TEGRA124_CLK_I2S0_SYNC 233
-#define TEGRA124_CLK_I2S1_SYNC 234
-#define TEGRA124_CLK_I2S2_SYNC 235
-#define TEGRA124_CLK_I2S3_SYNC 236
-#define TEGRA124_CLK_I2S4_SYNC 237
-#define TEGRA124_CLK_VIMCLK_SYNC 238
-#define TEGRA124_CLK_AUDIO0 239
-#define TEGRA124_CLK_AUDIO1 240
-#define TEGRA124_CLK_AUDIO2 241
-#define TEGRA124_CLK_AUDIO3 242
-#define TEGRA124_CLK_AUDIO4 243
-#define TEGRA124_CLK_SPDIF 244
-#define TEGRA124_CLK_CLK_OUT_1 245
-#define TEGRA124_CLK_CLK_OUT_2 246
-#define TEGRA124_CLK_CLK_OUT_3 247
-#define TEGRA124_CLK_BLINK 248
-/* 249 */
-/* 250 */
-/* 251 */
-#define TEGRA124_CLK_XUSB_HOST_SRC 252
-#define TEGRA124_CLK_XUSB_FALCON_SRC 253
-#define TEGRA124_CLK_XUSB_FS_SRC 254
-#define TEGRA124_CLK_XUSB_SS_SRC 255
-
-#define TEGRA124_CLK_XUSB_DEV_SRC 256
-#define TEGRA124_CLK_XUSB_DEV 257
-#define TEGRA124_CLK_XUSB_HS_SRC 258
-#define TEGRA124_CLK_SCLK 259
-#define TEGRA124_CLK_HCLK 260
-#define TEGRA124_CLK_PCLK 261
-/* 262 */
-/* 263 */
-#define TEGRA124_CLK_DFLL_REF 264
-#define TEGRA124_CLK_DFLL_SOC 265
-#define TEGRA124_CLK_VI_SENSOR2 266
-#define TEGRA124_CLK_PLL_P_OUT5 267
-#define TEGRA124_CLK_CML0 268
-#define TEGRA124_CLK_CML1 269
-#define TEGRA124_CLK_PLL_C4 270
-#define TEGRA124_CLK_PLL_DP 271
-#define TEGRA124_CLK_PLL_E_MUX 272
-#define TEGRA124_CLK_PLL_D_DSI_OUT 273
-/* 274 */
-/* 275 */
-/* 276 */
-/* 277 */
-/* 278 */
-/* 279 */
-/* 280 */
-/* 281 */
-/* 282 */
-/* 283 */
-/* 284 */
-/* 285 */
-/* 286 */
-/* 287 */
-
-/* 288 */
-/* 289 */
-/* 290 */
-/* 291 */
-/* 292 */
-/* 293 */
-/* 294 */
-/* 295 */
-/* 296 */
-/* 297 */
-/* 298 */
-/* 299 */
-#define TEGRA124_CLK_AUDIO0_MUX 300
-#define TEGRA124_CLK_AUDIO1_MUX 301
-#define TEGRA124_CLK_AUDIO2_MUX 302
-#define TEGRA124_CLK_AUDIO3_MUX 303
-#define TEGRA124_CLK_AUDIO4_MUX 304
-#define TEGRA124_CLK_SPDIF_MUX 305
-#define TEGRA124_CLK_CLK_OUT_1_MUX 306
-#define TEGRA124_CLK_CLK_OUT_2_MUX 307
-#define TEGRA124_CLK_CLK_OUT_3_MUX 308
-/* 309 */
-/* 310 */
-#define TEGRA124_CLK_SOR0_LVDS 311
-#define TEGRA124_CLK_XUSB_SS_DIV2 312
-
-#define TEGRA124_CLK_PLL_M_UD 313
-#define TEGRA124_CLK_PLL_C_UD 314
-
-#endif /* _DT_BINDINGS_CLOCK_TEGRA124_CAR_COMMON_H */
diff --git a/include/dt-bindings/clock/tegra124-car.h b/include/dt-bindings/clock/tegra124-car.h
deleted file mode 100644
index 2860737..0000000
--- a/include/dt-bindings/clock/tegra124-car.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * This header provides Tegra124-specific constants for binding
- * nvidia,tegra124-car.
- */
-
-#include <dt-bindings/clock/tegra124-car-common.h>
-
-#ifndef _DT_BINDINGS_CLOCK_TEGRA124_CAR_H
-#define _DT_BINDINGS_CLOCK_TEGRA124_CAR_H
-
-#define TEGRA124_CLK_PLL_X 227
-#define TEGRA124_CLK_PLL_X_OUT0 228
-
-#define TEGRA124_CLK_CCLK_G 262
-#define TEGRA124_CLK_CCLK_LP 263
-
-#define TEGRA124_CLK_CLK_MAX 315
-
-#endif /* _DT_BINDINGS_CLOCK_TEGRA124_CAR_H */
diff --git a/include/dt-bindings/clock/tegra186-clock.h b/include/dt-bindings/clock/tegra186-clock.h
deleted file mode 100644
index f73d320..0000000
--- a/include/dt-bindings/clock/tegra186-clock.h
+++ /dev/null
@@ -1,940 +0,0 @@
-/** @file */
-
-#ifndef _MACH_T186_CLK_T186_H
-#define _MACH_T186_CLK_T186_H
-
-/**
- * @defgroup clock_ids Clock Identifiers
- * @{
- * @defgroup extern_input external input clocks
- * @{
- * @def TEGRA186_CLK_OSC
- * @def TEGRA186_CLK_CLK_32K
- * @def TEGRA186_CLK_DTV_INPUT
- * @def TEGRA186_CLK_SOR0_PAD_CLKOUT
- * @def TEGRA186_CLK_SOR1_PAD_CLKOUT
- * @def TEGRA186_CLK_I2S1_SYNC_INPUT
- * @def TEGRA186_CLK_I2S2_SYNC_INPUT
- * @def TEGRA186_CLK_I2S3_SYNC_INPUT
- * @def TEGRA186_CLK_I2S4_SYNC_INPUT
- * @def TEGRA186_CLK_I2S5_SYNC_INPUT
- * @def TEGRA186_CLK_I2S6_SYNC_INPUT
- * @def TEGRA186_CLK_SPDIFIN_SYNC_INPUT
- * @}
- *
- * @defgroup extern_output external output clocks
- * @{
- * @def TEGRA186_CLK_EXTPERIPH1
- * @def TEGRA186_CLK_EXTPERIPH2
- * @def TEGRA186_CLK_EXTPERIPH3
- * @def TEGRA186_CLK_EXTPERIPH4
- * @}
- *
- * @defgroup display_clks display related clocks
- * @{
- * @def TEGRA186_CLK_CEC
- * @def TEGRA186_CLK_DSIC
- * @def TEGRA186_CLK_DSIC_LP
- * @def TEGRA186_CLK_DSID
- * @def TEGRA186_CLK_DSID_LP
- * @def TEGRA186_CLK_DPAUX1
- * @def TEGRA186_CLK_DPAUX
- * @def TEGRA186_CLK_HDA2HDMICODEC
- * @def TEGRA186_CLK_NVDISPLAY_DISP
- * @def TEGRA186_CLK_NVDISPLAY_DSC
- * @def TEGRA186_CLK_NVDISPLAY_P0
- * @def TEGRA186_CLK_NVDISPLAY_P1
- * @def TEGRA186_CLK_NVDISPLAY_P2
- * @def TEGRA186_CLK_NVDISPLAYHUB
- * @def TEGRA186_CLK_SOR_SAFE
- * @def TEGRA186_CLK_SOR0
- * @def TEGRA186_CLK_SOR0_OUT
- * @def TEGRA186_CLK_SOR1
- * @def TEGRA186_CLK_SOR1_OUT
- * @def TEGRA186_CLK_DSI
- * @def TEGRA186_CLK_MIPI_CAL
- * @def TEGRA186_CLK_DSIA_LP
- * @def TEGRA186_CLK_DSIB
- * @def TEGRA186_CLK_DSIB_LP
- * @}
- *
- * @defgroup camera_clks camera related clocks
- * @{
- * @def TEGRA186_CLK_NVCSI
- * @def TEGRA186_CLK_NVCSILP
- * @def TEGRA186_CLK_VI
- * @}
- *
- * @defgroup audio_clks audio related clocks
- * @{
- * @def TEGRA186_CLK_ACLK
- * @def TEGRA186_CLK_ADSP
- * @def TEGRA186_CLK_ADSPNEON
- * @def TEGRA186_CLK_AHUB
- * @def TEGRA186_CLK_APE
- * @def TEGRA186_CLK_APB2APE
- * @def TEGRA186_CLK_AUD_MCLK
- * @def TEGRA186_CLK_DMIC1
- * @def TEGRA186_CLK_DMIC2
- * @def TEGRA186_CLK_DMIC3
- * @def TEGRA186_CLK_DMIC4
- * @def TEGRA186_CLK_DSPK1
- * @def TEGRA186_CLK_DSPK2
- * @def TEGRA186_CLK_HDA
- * @def TEGRA186_CLK_HDA2CODEC_2X
- * @def TEGRA186_CLK_I2S1
- * @def TEGRA186_CLK_I2S2
- * @def TEGRA186_CLK_I2S3
- * @def TEGRA186_CLK_I2S4
- * @def TEGRA186_CLK_I2S5
- * @def TEGRA186_CLK_I2S6
- * @def TEGRA186_CLK_MAUD
- * @def TEGRA186_CLK_PLL_A_OUT0
- * @def TEGRA186_CLK_SPDIF_DOUBLER
- * @def TEGRA186_CLK_SPDIF_IN
- * @def TEGRA186_CLK_SPDIF_OUT
- * @def TEGRA186_CLK_SYNC_DMIC1
- * @def TEGRA186_CLK_SYNC_DMIC2
- * @def TEGRA186_CLK_SYNC_DMIC3
- * @def TEGRA186_CLK_SYNC_DMIC4
- * @def TEGRA186_CLK_SYNC_DMIC5
- * @def TEGRA186_CLK_SYNC_DSPK1
- * @def TEGRA186_CLK_SYNC_DSPK2
- * @def TEGRA186_CLK_SYNC_I2S1
- * @def TEGRA186_CLK_SYNC_I2S2
- * @def TEGRA186_CLK_SYNC_I2S3
- * @def TEGRA186_CLK_SYNC_I2S4
- * @def TEGRA186_CLK_SYNC_I2S5
- * @def TEGRA186_CLK_SYNC_I2S6
- * @def TEGRA186_CLK_SYNC_SPDIF
- * @}
- *
- * @defgroup uart_clks UART clocks
- * @{
- * @def TEGRA186_CLK_AON_UART_FST_MIPI_CAL
- * @def TEGRA186_CLK_UARTA
- * @def TEGRA186_CLK_UARTB
- * @def TEGRA186_CLK_UARTC
- * @def TEGRA186_CLK_UARTD
- * @def TEGRA186_CLK_UARTE
- * @def TEGRA186_CLK_UARTF
- * @def TEGRA186_CLK_UARTG
- * @def TEGRA186_CLK_UART_FST_MIPI_CAL
- * @}
- *
- * @defgroup i2c_clks I2C clocks
- * @{
- * @def TEGRA186_CLK_AON_I2C_SLOW
- * @def TEGRA186_CLK_I2C1
- * @def TEGRA186_CLK_I2C2
- * @def TEGRA186_CLK_I2C3
- * @def TEGRA186_CLK_I2C4
- * @def TEGRA186_CLK_I2C5
- * @def TEGRA186_CLK_I2C6
- * @def TEGRA186_CLK_I2C8
- * @def TEGRA186_CLK_I2C9
- * @def TEGRA186_CLK_I2C1
- * @def TEGRA186_CLK_I2C12
- * @def TEGRA186_CLK_I2C13
- * @def TEGRA186_CLK_I2C14
- * @def TEGRA186_CLK_I2C_SLOW
- * @def TEGRA186_CLK_VI_I2C
- * @}
- *
- * @defgroup spi_clks SPI clocks
- * @{
- * @def TEGRA186_CLK_SPI1
- * @def TEGRA186_CLK_SPI2
- * @def TEGRA186_CLK_SPI3
- * @def TEGRA186_CLK_SPI4
- * @}
- *
- * @defgroup storage storage related clocks
- * @{
- * @def TEGRA186_CLK_SATA
- * @def TEGRA186_CLK_SATA_OOB
- * @def TEGRA186_CLK_SATA_IOBIST
- * @def TEGRA186_CLK_SDMMC_LEGACY_TM
- * @def TEGRA186_CLK_SDMMC1
- * @def TEGRA186_CLK_SDMMC2
- * @def TEGRA186_CLK_SDMMC3
- * @def TEGRA186_CLK_SDMMC4
- * @def TEGRA186_CLK_QSPI
- * @def TEGRA186_CLK_QSPI_OUT
- * @def TEGRA186_CLK_UFSDEV_REF
- * @def TEGRA186_CLK_UFSHC
- * @}
- *
- * @defgroup pwm_clks PWM clocks
- * @{
- * @def TEGRA186_CLK_PWM1
- * @def TEGRA186_CLK_PWM2
- * @def TEGRA186_CLK_PWM3
- * @def TEGRA186_CLK_PWM4
- * @def TEGRA186_CLK_PWM5
- * @def TEGRA186_CLK_PWM6
- * @def TEGRA186_CLK_PWM7
- * @def TEGRA186_CLK_PWM8
- * @}
- *
- * @defgroup plls PLLs and related clocks
- * @{
- * @def TEGRA186_CLK_PLLREFE_OUT_GATED
- * @def TEGRA186_CLK_PLLREFE_OUT1
- * @def TEGRA186_CLK_PLLD_OUT1
- * @def TEGRA186_CLK_PLLP_OUT0
- * @def TEGRA186_CLK_PLLP_OUT5
- * @def TEGRA186_CLK_PLLA
- * @def TEGRA186_CLK_PLLE_PWRSEQ
- * @def TEGRA186_CLK_PLLA_OUT1
- * @def TEGRA186_CLK_PLLREFE_REF
- * @def TEGRA186_CLK_UPHY_PLL0_PWRSEQ
- * @def TEGRA186_CLK_UPHY_PLL1_PWRSEQ
- * @def TEGRA186_CLK_PLLREFE_PLLE_PASSTHROUGH
- * @def TEGRA186_CLK_PLLREFE_PEX
- * @def TEGRA186_CLK_PLLREFE_IDDQ
- * @def TEGRA186_CLK_PLLC_OUT_AON
- * @def TEGRA186_CLK_PLLC_OUT_ISP
- * @def TEGRA186_CLK_PLLC_OUT_VE
- * @def TEGRA186_CLK_PLLC4_OUT
- * @def TEGRA186_CLK_PLLREFE_OUT
- * @def TEGRA186_CLK_PLLREFE_PLL_REF
- * @def TEGRA186_CLK_PLLE
- * @def TEGRA186_CLK_PLLC
- * @def TEGRA186_CLK_PLLP
- * @def TEGRA186_CLK_PLLD
- * @def TEGRA186_CLK_PLLD2
- * @def TEGRA186_CLK_PLLREFE_VCO
- * @def TEGRA186_CLK_PLLC2
- * @def TEGRA186_CLK_PLLC3
- * @def TEGRA186_CLK_PLLDP
- * @def TEGRA186_CLK_PLLC4_VCO
- * @def TEGRA186_CLK_PLLA1
- * @def TEGRA186_CLK_PLLNVCSI
- * @def TEGRA186_CLK_PLLDISPHUB
- * @def TEGRA186_CLK_PLLD3
- * @def TEGRA186_CLK_PLLBPMPCAM
- * @def TEGRA186_CLK_PLLAON
- * @def TEGRA186_CLK_PLLU
- * @def TEGRA186_CLK_PLLC4_VCO_DIV2
- * @def TEGRA186_CLK_PLL_REF
- * @def TEGRA186_CLK_PLLREFE_OUT1_DIV5
- * @def TEGRA186_CLK_UTMIP_PLL_PWRSEQ
- * @def TEGRA186_CLK_PLL_U_48M
- * @def TEGRA186_CLK_PLL_U_480M
- * @def TEGRA186_CLK_PLLC4_OUT0
- * @def TEGRA186_CLK_PLLC4_OUT1
- * @def TEGRA186_CLK_PLLC4_OUT2
- * @def TEGRA186_CLK_PLLC4_OUT_MUX
- * @def TEGRA186_CLK_DFLLDISP_DIV
- * @def TEGRA186_CLK_PLLDISPHUB_DIV
- * @def TEGRA186_CLK_PLLP_DIV8
- * @}
- *
- * @defgroup nafll_clks NAFLL clock sources
- * @{
- * @def TEGRA186_CLK_NAFLL_AXI_CBB
- * @def TEGRA186_CLK_NAFLL_BCPU
- * @def TEGRA186_CLK_NAFLL_BPMP
- * @def TEGRA186_CLK_NAFLL_DISP
- * @def TEGRA186_CLK_NAFLL_GPU
- * @def TEGRA186_CLK_NAFLL_ISP
- * @def TEGRA186_CLK_NAFLL_MCPU
- * @def TEGRA186_CLK_NAFLL_NVDEC
- * @def TEGRA186_CLK_NAFLL_NVENC
- * @def TEGRA186_CLK_NAFLL_NVJPG
- * @def TEGRA186_CLK_NAFLL_SCE
- * @def TEGRA186_CLK_NAFLL_SE
- * @def TEGRA186_CLK_NAFLL_TSEC
- * @def TEGRA186_CLK_NAFLL_TSECB
- * @def TEGRA186_CLK_NAFLL_VI
- * @def TEGRA186_CLK_NAFLL_VIC
- * @}
- *
- * @defgroup mphy MPHY related clocks
- * @{
- * @def TEGRA186_CLK_MPHY_L0_RX_SYMB
- * @def TEGRA186_CLK_MPHY_L0_RX_LS_BIT
- * @def TEGRA186_CLK_MPHY_L0_TX_SYMB
- * @def TEGRA186_CLK_MPHY_L0_TX_LS_3XBIT
- * @def TEGRA186_CLK_MPHY_L0_RX_ANA
- * @def TEGRA186_CLK_MPHY_L1_RX_ANA
- * @def TEGRA186_CLK_MPHY_IOBIST
- * @def TEGRA186_CLK_MPHY_TX_1MHZ_REF
- * @def TEGRA186_CLK_MPHY_CORE_PLL_FIXED
- * @}
- *
- * @defgroup eavb EAVB related clocks
- * @{
- * @def TEGRA186_CLK_EQOS_AXI
- * @def TEGRA186_CLK_EQOS_PTP_REF
- * @def TEGRA186_CLK_EQOS_RX
- * @def TEGRA186_CLK_EQOS_RX_INPUT
- * @def TEGRA186_CLK_EQOS_TX
- * @}
- *
- * @defgroup usb USB related clocks
- * @{
- * @def TEGRA186_CLK_PEX_USB_PAD0_MGMT
- * @def TEGRA186_CLK_PEX_USB_PAD1_MGMT
- * @def TEGRA186_CLK_HSIC_TRK
- * @def TEGRA186_CLK_USB2_TRK
- * @def TEGRA186_CLK_USB2_HSIC_TRK
- * @def TEGRA186_CLK_XUSB_CORE_SS
- * @def TEGRA186_CLK_XUSB_CORE_DEV
- * @def TEGRA186_CLK_XUSB_FALCON
- * @def TEGRA186_CLK_XUSB_FS
- * @def TEGRA186_CLK_XUSB
- * @def TEGRA186_CLK_XUSB_DEV
- * @def TEGRA186_CLK_XUSB_HOST
- * @def TEGRA186_CLK_XUSB_SS
- * @}
- *
- * @defgroup bigblock compute block related clocks
- * @{
- * @def TEGRA186_CLK_GPCCLK
- * @def TEGRA186_CLK_GPC2CLK
- * @def TEGRA186_CLK_GPU
- * @def TEGRA186_CLK_HOST1X
- * @def TEGRA186_CLK_ISP
- * @def TEGRA186_CLK_NVDEC
- * @def TEGRA186_CLK_NVENC
- * @def TEGRA186_CLK_NVJPG
- * @def TEGRA186_CLK_SE
- * @def TEGRA186_CLK_TSEC
- * @def TEGRA186_CLK_TSECB
- * @def TEGRA186_CLK_VIC
- * @}
- *
- * @defgroup can CAN bus related clocks
- * @{
- * @def TEGRA186_CLK_CAN1
- * @def TEGRA186_CLK_CAN1_HOST
- * @def TEGRA186_CLK_CAN2
- * @def TEGRA186_CLK_CAN2_HOST
- * @}
- *
- * @defgroup system basic system clocks
- * @{
- * @def TEGRA186_CLK_ACTMON
- * @def TEGRA186_CLK_AON_APB
- * @def TEGRA186_CLK_AON_CPU_NIC
- * @def TEGRA186_CLK_AON_NIC
- * @def TEGRA186_CLK_AXI_CBB
- * @def TEGRA186_CLK_BPMP_APB
- * @def TEGRA186_CLK_BPMP_CPU_NIC
- * @def TEGRA186_CLK_BPMP_NIC_RATE
- * @def TEGRA186_CLK_CLK_M
- * @def TEGRA186_CLK_EMC
- * @def TEGRA186_CLK_MSS_ENCRYPT
- * @def TEGRA186_CLK_SCE_APB
- * @def TEGRA186_CLK_SCE_CPU_NIC
- * @def TEGRA186_CLK_SCE_NIC
- * @def TEGRA186_CLK_TSC
- * @}
- *
- * @defgroup pcie_clks PCIe related clocks
- * @{
- * @def TEGRA186_CLK_AFI
- * @def TEGRA186_CLK_PCIE
- * @def TEGRA186_CLK_PCIE2_IOBIST
- * @def TEGRA186_CLK_PCIERX0
- * @def TEGRA186_CLK_PCIERX1
- * @def TEGRA186_CLK_PCIERX2
- * @def TEGRA186_CLK_PCIERX3
- * @def TEGRA186_CLK_PCIERX4
- * @}
- */
-
-/** @brief output of gate CLK_ENB_FUSE */
-#define TEGRA186_CLK_FUSE 0
-/**
- * @brief It's not what you think
- * @details output of gate CLK_ENB_GPU. This output connects to the GPU
- * pwrclk. @warning: This is almost certainly not the clock you think
- * it is. If you're looking for the clock of the graphics engine, see
- * TEGRA186_GPCCLK
- */
-#define TEGRA186_CLK_GPU 1
-/** @brief output of gate CLK_ENB_PCIE */
-#define TEGRA186_CLK_PCIE 3
-/** @brief output of the divider IPFS_CLK_DIVISOR */
-#define TEGRA186_CLK_AFI 4
-/** @brief output of gate CLK_ENB_PCIE2_IOBIST */
-#define TEGRA186_CLK_PCIE2_IOBIST 5
-/** @brief output of gate CLK_ENB_PCIERX0*/
-#define TEGRA186_CLK_PCIERX0 6
-/** @brief output of gate CLK_ENB_PCIERX1*/
-#define TEGRA186_CLK_PCIERX1 7
-/** @brief output of gate CLK_ENB_PCIERX2*/
-#define TEGRA186_CLK_PCIERX2 8
-/** @brief output of gate CLK_ENB_PCIERX3*/
-#define TEGRA186_CLK_PCIERX3 9
-/** @brief output of gate CLK_ENB_PCIERX4*/
-#define TEGRA186_CLK_PCIERX4 10
-/** @brief output branch of PLL_C for ISP, controlled by gate CLK_ENB_PLLC_OUT_ISP */
-#define TEGRA186_CLK_PLLC_OUT_ISP 11
-/** @brief output branch of PLL_C for VI, controlled by gate CLK_ENB_PLLC_OUT_VE */
-#define TEGRA186_CLK_PLLC_OUT_VE 12
-/** @brief output branch of PLL_C for AON domain, controlled by gate CLK_ENB_PLLC_OUT_AON */
-#define TEGRA186_CLK_PLLC_OUT_AON 13
-/** @brief output of gate CLK_ENB_SOR_SAFE */
-#define TEGRA186_CLK_SOR_SAFE 39
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S2 */
-#define TEGRA186_CLK_I2S2 42
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S3 */
-#define TEGRA186_CLK_I2S3 43
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPDF_IN */
-#define TEGRA186_CLK_SPDIF_IN 44
-/** @brief output of gate CLK_ENB_SPDIF_DOUBLER */
-#define TEGRA186_CLK_SPDIF_DOUBLER 45
-/** @clkdesc{spi_clks, out, mux, CLK_RST_CONTROLLER_CLK_SOURCE_SPI3} */
-#define TEGRA186_CLK_SPI3 46
-/** @clkdesc{i2c_clks, out, mux, CLK_RST_CONTROLLER_CLK_SOURCE_I2C1} */
-#define TEGRA186_CLK_I2C1 47
-/** @clkdesc{i2c_clks, out, mux, CLK_RST_CONTROLLER_CLK_SOURCE_I2C5} */
-#define TEGRA186_CLK_I2C5 48
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPI1 */
-#define TEGRA186_CLK_SPI1 49
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_ISP */
-#define TEGRA186_CLK_ISP 50
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_VI */
-#define TEGRA186_CLK_VI 51
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1 */
-#define TEGRA186_CLK_SDMMC1 52
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2 */
-#define TEGRA186_CLK_SDMMC2 53
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4 */
-#define TEGRA186_CLK_SDMMC4 54
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTA */
-#define TEGRA186_CLK_UARTA 55
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTB */
-#define TEGRA186_CLK_UARTB 56
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X */
-#define TEGRA186_CLK_HOST1X 57
-/**
- * @brief controls the EMC clock frequency.
- * @details Doing a clk_set_rate on this clock will select the
- * appropriate clock source, program the source rate and execute a
- * specific sequence to switch to the new clock source for both memory
- * controllers. This can be used to control the balance between memory
- * throughput and memory controller power.
- */
-#define TEGRA186_CLK_EMC 58
-/* @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH4 */
-#define TEGRA186_CLK_EXTPERIPH4 73
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPI4 */
-#define TEGRA186_CLK_SPI4 74
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C3 */
-#define TEGRA186_CLK_I2C3 75
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3 */
-#define TEGRA186_CLK_SDMMC3 76
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTD */
-#define TEGRA186_CLK_UARTD 77
-/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S1 */
-#define TEGRA186_CLK_I2S1 79
-/** output of gate CLK_ENB_DTV */
-#define TEGRA186_CLK_DTV 80
-/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TSEC */
-#define TEGRA186_CLK_TSEC 81
-/** @brief output of gate CLK_ENB_DP2 */
-#define TEGRA186_CLK_DP2 82
-/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S4 */
-#define TEGRA186_CLK_I2S4 84
-/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S5 */
-#define TEGRA186_CLK_I2S5 85
-/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C4 */
-#define TEGRA186_CLK_I2C4 86
-/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AHUB */
-#define TEGRA186_CLK_AHUB 87
-/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_HDA2CODEC_2X */
-#define TEGRA186_CLK_HDA2CODEC_2X 88
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH1 */
-#define TEGRA186_CLK_EXTPERIPH1 89
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH2 */
-#define TEGRA186_CLK_EXTPERIPH2 90
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH3 */
-#define TEGRA186_CLK_EXTPERIPH3 91
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C_SLOW */
-#define TEGRA186_CLK_I2C_SLOW 92
-/** @brief output of the SOR1_CLK_SRC mux in CLK_RST_CONTROLLER_CLK_SOURCE_SOR1 */
-#define TEGRA186_CLK_SOR1 93
-/** @brief output of gate CLK_ENB_CEC */
-#define TEGRA186_CLK_CEC 94
-/** @brief output of gate CLK_ENB_DPAUX1 */
-#define TEGRA186_CLK_DPAUX1 95
-/** @brief output of gate CLK_ENB_DPAUX */
-#define TEGRA186_CLK_DPAUX 96
-/** @brief output of the SOR0_CLK_SRC mux in CLK_RST_CONTROLLER_CLK_SOURCE_SOR0 */
-#define TEGRA186_CLK_SOR0 97
-/** @brief output of gate CLK_ENB_HDA2HDMICODEC */
-#define TEGRA186_CLK_HDA2HDMICODEC 98
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SATA */
-#define TEGRA186_CLK_SATA 99
-/** @brief output of gate CLK_ENB_SATA_OOB */
-#define TEGRA186_CLK_SATA_OOB 100
-/** @brief output of gate CLK_ENB_SATA_IOBIST */
-#define TEGRA186_CLK_SATA_IOBIST 101
-/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_HDA */
-#define TEGRA186_CLK_HDA 102
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SE */
-#define TEGRA186_CLK_SE 103
-/** @brief output of gate CLK_ENB_APB2APE */
-#define TEGRA186_CLK_APB2APE 104
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_APE */
-#define TEGRA186_CLK_APE 105
-/** @brief output of gate CLK_ENB_IQC1 */
-#define TEGRA186_CLK_IQC1 106
-/** @brief output of gate CLK_ENB_IQC2 */
-#define TEGRA186_CLK_IQC2 107
-/** divide by 2 version of TEGRA186_CLK_PLLREFE_VCO */
-#define TEGRA186_CLK_PLLREFE_OUT 108
-/** @brief output of gate CLK_ENB_PLLREFE_PLL_REF */
-#define TEGRA186_CLK_PLLREFE_PLL_REF 109
-/** @brief output of gate CLK_ENB_PLLC4_OUT */
-#define TEGRA186_CLK_PLLC4_OUT 110
-/** @brief output of mux xusb_core_clk_switch on page 67 of T186_Clocks_IAS.doc */
-#define TEGRA186_CLK_XUSB 111
-/** controls xusb_dev_ce signal on page 66 and 67 of T186_Clocks_IAS.doc */
-#define TEGRA186_CLK_XUSB_DEV 112
-/** controls xusb_host_ce signal on page 67 of T186_Clocks_IAS.doc */
-#define TEGRA186_CLK_XUSB_HOST 113
-/** controls xusb_ss_ce signal on page 67 of T186_Clocks_IAS.doc */
-#define TEGRA186_CLK_XUSB_SS 114
-/** @brief output of gate CLK_ENB_DSI */
-#define TEGRA186_CLK_DSI 115
-/** @brief output of gate CLK_ENB_MIPI_CAL */
-#define TEGRA186_CLK_MIPI_CAL 116
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSIA_LP */
-#define TEGRA186_CLK_DSIA_LP 117
-/** @brief output of gate CLK_ENB_DSIB */
-#define TEGRA186_CLK_DSIB 118
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSIB_LP */
-#define TEGRA186_CLK_DSIB_LP 119
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1 */
-#define TEGRA186_CLK_DMIC1 122
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2 */
-#define TEGRA186_CLK_DMIC2 123
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK */
-#define TEGRA186_CLK_AUD_MCLK 124
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C6 */
-#define TEGRA186_CLK_I2C6 125
-/**output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL */
-#define TEGRA186_CLK_UART_FST_MIPI_CAL 126
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_VIC */
-#define TEGRA186_CLK_VIC 127
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM */
-#define TEGRA186_CLK_SDMMC_LEGACY_TM 128
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC */
-#define TEGRA186_CLK_NVDEC 129
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG */
-#define TEGRA186_CLK_NVJPG 130
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVENC */
-#define TEGRA186_CLK_NVENC 131
-/** @brief output of the QSPI_CLK_SRC mux in CLK_RST_CONTROLLER_CLK_SOURCE_QSPI */
-#define TEGRA186_CLK_QSPI 132
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_VI_I2C */
-#define TEGRA186_CLK_VI_I2C 133
-/** @brief output of gate CLK_ENB_HSIC_TRK */
-#define TEGRA186_CLK_HSIC_TRK 134
-/** @brief output of gate CLK_ENB_USB2_TRK */
-#define TEGRA186_CLK_USB2_TRK 135
-/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_MAUD */
-#define TEGRA186_CLK_MAUD 136
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TSECB */
-#define TEGRA186_CLK_TSECB 137
-/** @brief output of gate CLK_ENB_ADSP */
-#define TEGRA186_CLK_ADSP 138
-/** @brief output of gate CLK_ENB_ADSPNEON */
-#define TEGRA186_CLK_ADSPNEON 139
-/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_RX_LS_SYMB */
-#define TEGRA186_CLK_MPHY_L0_RX_SYMB 140
-/** @brief output of gate CLK_ENB_MPHY_L0_RX_LS_BIT */
-#define TEGRA186_CLK_MPHY_L0_RX_LS_BIT 141
-/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_TX_LS_SYMB */
-#define TEGRA186_CLK_MPHY_L0_TX_SYMB 142
-/** @brief output of gate CLK_ENB_MPHY_L0_TX_LS_3XBIT */
-#define TEGRA186_CLK_MPHY_L0_TX_LS_3XBIT 143
-/** @brief output of gate CLK_ENB_MPHY_L0_RX_ANA */
-#define TEGRA186_CLK_MPHY_L0_RX_ANA 144
-/** @brief output of gate CLK_ENB_MPHY_L1_RX_ANA */
-#define TEGRA186_CLK_MPHY_L1_RX_ANA 145
-/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_IOBIST */
-#define TEGRA186_CLK_MPHY_IOBIST 146
-/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_TX_1MHZ_REF */
-#define TEGRA186_CLK_MPHY_TX_1MHZ_REF 147
-/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_CORE_PLL_FIXED */
-#define TEGRA186_CLK_MPHY_CORE_PLL_FIXED 148
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AXI_CBB */
-#define TEGRA186_CLK_AXI_CBB 149
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3 */
-#define TEGRA186_CLK_DMIC3 150
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4 */
-#define TEGRA186_CLK_DMIC4 151
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1 */
-#define TEGRA186_CLK_DSPK1 152
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2 */
-#define TEGRA186_CLK_DSPK2 153
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C6 */
-#define TEGRA186_CLK_I2S6 154
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P0 */
-#define TEGRA186_CLK_NVDISPLAY_P0 155
-/** @brief output of the NVDISPLAY_DISP_CLK_SRC mux in CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP */
-#define TEGRA186_CLK_NVDISPLAY_DISP 156
-/** @brief output of gate CLK_ENB_NVDISPLAY_DSC */
-#define TEGRA186_CLK_NVDISPLAY_DSC 157
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAYHUB */
-#define TEGRA186_CLK_NVDISPLAYHUB 158
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P1 */
-#define TEGRA186_CLK_NVDISPLAY_P1 159
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P2 */
-#define TEGRA186_CLK_NVDISPLAY_P2 160
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TACH */
-#define TEGRA186_CLK_TACH 166
-/** @brief output of gate CLK_ENB_EQOS */
-#define TEGRA186_CLK_EQOS_AXI 167
-/** @brief output of gate CLK_ENB_EQOS_RX */
-#define TEGRA186_CLK_EQOS_RX 168
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UFSHC_CG_SYS */
-#define TEGRA186_CLK_UFSHC 178
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF */
-#define TEGRA186_CLK_UFSDEV_REF 179
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI */
-#define TEGRA186_CLK_NVCSI 180
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVCSILP */
-#define TEGRA186_CLK_NVCSILP 181
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C7 */
-#define TEGRA186_CLK_I2C7 182
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C9 */
-#define TEGRA186_CLK_I2C9 183
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C12 */
-#define TEGRA186_CLK_I2C12 184
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C13 */
-#define TEGRA186_CLK_I2C13 185
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C14 */
-#define TEGRA186_CLK_I2C14 186
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM1 */
-#define TEGRA186_CLK_PWM1 187
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM2 */
-#define TEGRA186_CLK_PWM2 188
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM3 */
-#define TEGRA186_CLK_PWM3 189
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM5 */
-#define TEGRA186_CLK_PWM5 190
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM6 */
-#define TEGRA186_CLK_PWM6 191
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM7 */
-#define TEGRA186_CLK_PWM7 192
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM8 */
-#define TEGRA186_CLK_PWM8 193
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTE */
-#define TEGRA186_CLK_UARTE 194
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTF */
-#define TEGRA186_CLK_UARTF 195
-/** @deprecated */
-#define TEGRA186_CLK_DBGAPB 196
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC */
-#define TEGRA186_CLK_BPMP_CPU_NIC 197
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB */
-#define TEGRA186_CLK_BPMP_APB 199
-/** @brief output of mux controlled by TEGRA186_CLK_SOC_ACTMON */
-#define TEGRA186_CLK_ACTMON 201
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC */
-#define TEGRA186_CLK_AON_CPU_NIC 208
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_CAN1 */
-#define TEGRA186_CLK_CAN1 210
-/** @brief output of gate CLK_ENB_CAN1_HOST */
-#define TEGRA186_CLK_CAN1_HOST 211
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_CAN2 */
-#define TEGRA186_CLK_CAN2 212
-/** @brief output of gate CLK_ENB_CAN2_HOST */
-#define TEGRA186_CLK_CAN2_HOST 213
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB */
-#define TEGRA186_CLK_AON_APB 214
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTC */
-#define TEGRA186_CLK_UARTC 215
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTG */
-#define TEGRA186_CLK_UARTG 216
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_UART_FST_MIPI_CAL */
-#define TEGRA186_CLK_AON_UART_FST_MIPI_CAL 217
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C2 */
-#define TEGRA186_CLK_I2C2 218
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C8 */
-#define TEGRA186_CLK_I2C8 219
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C10 */
-#define TEGRA186_CLK_I2C10 220
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_I2C_SLOW */
-#define TEGRA186_CLK_AON_I2C_SLOW 221
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPI2 */
-#define TEGRA186_CLK_SPI2 222
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC5 */
-#define TEGRA186_CLK_DMIC5 223
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_TOUCH */
-#define TEGRA186_CLK_AON_TOUCH 224
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM4 */
-#define TEGRA186_CLK_PWM4 225
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TSC. This clock object is read only and is used for all timers in the system. */
-#define TEGRA186_CLK_TSC 226
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_MSS_ENCRYPT */
-#define TEGRA186_CLK_MSS_ENCRYPT 227
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC */
-#define TEGRA186_CLK_SCE_CPU_NIC 228
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB */
-#define TEGRA186_CLK_SCE_APB 230
-/** @brief output of gate CLK_ENB_DSIC */
-#define TEGRA186_CLK_DSIC 231
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSIC_LP */
-#define TEGRA186_CLK_DSIC_LP 232
-/** @brief output of gate CLK_ENB_DSID */
-#define TEGRA186_CLK_DSID 233
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSID_LP */
-#define TEGRA186_CLK_DSID_LP 234
-/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_PEX_SATA_USB_RX_BYP */
-#define TEGRA186_CLK_PEX_SATA_USB_RX_BYP 236
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT */
-#define TEGRA186_CLK_SPDIF_OUT 238
-/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_PTP_REF_CLK_0 */
-#define TEGRA186_CLK_EQOS_PTP_REF 239
-/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_TX_CLK */
-#define TEGRA186_CLK_EQOS_TX 240
-/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_USB2_HSIC_TRK */
-#define TEGRA186_CLK_USB2_HSIC_TRK 241
-/** @brief output of mux xusb_ss_clk_switch on page 66 of T186_Clocks_IAS.doc */
-#define TEGRA186_CLK_XUSB_CORE_SS 242
-/** @brief output of mux xusb_core_dev_clk_switch on page 67 of T186_Clocks_IAS.doc */
-#define TEGRA186_CLK_XUSB_CORE_DEV 243
-/** @brief output of mux xusb_core_falcon_clk_switch on page 67 of T186_Clocks_IAS.doc */
-#define TEGRA186_CLK_XUSB_FALCON 244
-/** @brief output of mux xusb_fs_clk_switch on page 66 of T186_Clocks_IAS.doc */
-#define TEGRA186_CLK_XUSB_FS 245
-/** @brief output of the divider CLK_RST_CONTROLLER_PLLA_OUT */
-#define TEGRA186_CLK_PLL_A_OUT0 246
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1 */
-#define TEGRA186_CLK_SYNC_I2S1 247
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2 */
-#define TEGRA186_CLK_SYNC_I2S2 248
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3 */
-#define TEGRA186_CLK_SYNC_I2S3 249
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4 */
-#define TEGRA186_CLK_SYNC_I2S4 250
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5 */
-#define TEGRA186_CLK_SYNC_I2S5 251
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6 */
-#define TEGRA186_CLK_SYNC_I2S6 252
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1 */
-#define TEGRA186_CLK_SYNC_DSPK1 253
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2 */
-#define TEGRA186_CLK_SYNC_DSPK2 254
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1 */
-#define TEGRA186_CLK_SYNC_DMIC1 255
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2 */
-#define TEGRA186_CLK_SYNC_DMIC2 256
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3 */
-#define TEGRA186_CLK_SYNC_DMIC3 257
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4 */
-#define TEGRA186_CLK_SYNC_DMIC4 259
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_SPDIF */
-#define TEGRA186_CLK_SYNC_SPDIF 260
-/** @brief output of gate CLK_ENB_PLLREFE_OUT */
-#define TEGRA186_CLK_PLLREFE_OUT_GATED 261
-/** @brief output of the divider PLLREFE_DIVP in CLK_RST_CONTROLLER_PLLREFE_BASE. PLLREFE has 2 outputs:
- * * VCO/pdiv defined by this clock object
- * * VCO/2 defined by TEGRA186_CLK_PLLREFE_OUT
- */
-#define TEGRA186_CLK_PLLREFE_OUT1 262
-#define TEGRA186_CLK_PLLD_OUT1 267
-/** @brief output of the divider PLLP_DIVP in CLK_RST_CONTROLLER_PLLP_BASE */
-#define TEGRA186_CLK_PLLP_OUT0 269
-/** @brief output of the divider CLK_RST_CONTROLLER_PLLP_OUTC */
-#define TEGRA186_CLK_PLLP_OUT5 270
-/** PLL controlled by CLK_RST_CONTROLLER_PLLA_BASE for use by audio clocks */
-#define TEGRA186_CLK_PLLA 271
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_ACLK_BURST_POLICY divided by the divider controlled by ACLK_CLK_DIVISOR in CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER */
-#define TEGRA186_CLK_ACLK 273
-/** fixed 48MHz clock divided down from TEGRA186_CLK_PLL_U */
-#define TEGRA186_CLK_PLL_U_48M 274
-/** fixed 480MHz clock divided down from TEGRA186_CLK_PLL_U */
-#define TEGRA186_CLK_PLL_U_480M 275
-/** @brief output of the divider PLLC4_DIVP in CLK_RST_CONTROLLER_PLLC4_BASE. Output frequency is TEGRA186_CLK_PLLC4_VCO/PLLC4_DIVP */
-#define TEGRA186_CLK_PLLC4_OUT0 276
-/** fixed /3 divider. Output frequency of this clock is TEGRA186_CLK_PLLC4_VCO/3 */
-#define TEGRA186_CLK_PLLC4_OUT1 277
-/** fixed /5 divider. Output frequency of this clock is TEGRA186_CLK_PLLC4_VCO/5 */
-#define TEGRA186_CLK_PLLC4_OUT2 278
-/** @brief output of mux controlled by PLLC4_CLK_SEL in CLK_RST_CONTROLLER_PLLC4_MISC1 */
-#define TEGRA186_CLK_PLLC4_OUT_MUX 279
-/** @brief output of divider NVDISPLAY_DISP_CLK_DIVISOR in CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP when DFLLDISP_DIV is selected in NVDISPLAY_DISP_CLK_SRC */
-#define TEGRA186_CLK_DFLLDISP_DIV 284
-/** @brief output of divider NVDISPLAY_DISP_CLK_DIVISOR in CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP when PLLDISPHUB_DIV is selected in NVDISPLAY_DISP_CLK_SRC */
-#define TEGRA186_CLK_PLLDISPHUB_DIV 285
-/** fixed /8 divider which is used as the input for TEGRA186_CLK_SOR_SAFE */
-#define TEGRA186_CLK_PLLP_DIV8 286
-/** @brief output of divider CLK_RST_CONTROLLER_BPMP_NIC_RATE */
-#define TEGRA186_CLK_BPMP_NIC 287
-/** @brief output of the divider CLK_RST_CONTROLLER_PLLA1_OUT1 */
-#define TEGRA186_CLK_PLL_A_OUT1 288
-/** @deprecated */
-#define TEGRA186_CLK_GPC2CLK 289
-/** A fake clock which must be enabled during KFUSE read operations to ensure adequate VDD_CORE voltage. */
-#define TEGRA186_CLK_KFUSE 293
-/**
- * @brief controls the PLLE hardware sequencer.
- * @details This clock only has enable and disable methods. When the
- * PLLE hw sequencer is enabled, PLLE, will be enabled or disabled by
- * hw based on the control signals from the PCIe, SATA and XUSB
- * clocks. When the PLLE hw sequencer is disabled, the state of PLLE
- * is controlled by sw using clk_enable/clk_disable on
- * TEGRA186_CLK_PLLE.
- */
-#define TEGRA186_CLK_PLLE_PWRSEQ 294
-/** fixed 60MHz clock divided down from, TEGRA186_CLK_PLL_U */
-#define TEGRA186_CLK_PLLREFE_REF 295
-/** @brief output of mux controlled by SOR0_CLK_SEL0 and SOR0_CLK_SEL1 in CLK_RST_CONTROLLER_CLK_SOURCE_SOR0 */
-#define TEGRA186_CLK_SOR0_OUT 296
-/** @brief output of mux controlled by SOR1_CLK_SEL0 and SOR1_CLK_SEL1 in CLK_RST_CONTROLLER_CLK_SOURCE_SOR1 */
-#define TEGRA186_CLK_SOR1_OUT 297
-/** @brief fixed /5 divider. Output frequency of this clock is TEGRA186_CLK_PLLREFE_OUT1/5. Used as input for TEGRA186_CLK_EQOS_AXI */
-#define TEGRA186_CLK_PLLREFE_OUT1_DIV5 298
-/** @brief controls the UTMIP_PLL (aka PLLU) hardware sqeuencer */
-#define TEGRA186_CLK_UTMIP_PLL_PWRSEQ 301
-/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL0_MGMT */
-#define TEGRA186_CLK_PEX_USB_PAD0_MGMT 302
-/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL1_MGMT */
-#define TEGRA186_CLK_PEX_USB_PAD1_MGMT 303
-/** @brief controls the UPHY_PLL0 hardware sqeuencer */
-#define TEGRA186_CLK_UPHY_PLL0_PWRSEQ 304
-/** @brief controls the UPHY_PLL1 hardware sqeuencer */
-#define TEGRA186_CLK_UPHY_PLL1_PWRSEQ 305
-/** @brief control for PLLREFE_IDDQ in CLK_RST_CONTROLLER_PLLREFE_MISC so the bypass output even be used when the PLL is disabled */
-#define TEGRA186_CLK_PLLREFE_PLLE_PASSTHROUGH 306
-/** @brief output of the mux controlled by PLLREFE_SEL_CLKIN_PEX in CLK_RST_CONTROLLER_PLLREFE_MISC */
-#define TEGRA186_CLK_PLLREFE_PEX 307
-/** @brief control for PLLREFE_IDDQ in CLK_RST_CONTROLLER_PLLREFE_MISC to turn on the PLL when enabled */
-#define TEGRA186_CLK_PLLREFE_IDDQ 308
-/** @brief output of the divider QSPI_CLK_DIV2_SEL in CLK_RST_CONTROLLER_CLK_SOURCE_QSPI */
-#define TEGRA186_CLK_QSPI_OUT 309
-/**
- * @brief GPC2CLK-div-2
- * @details fixed /2 divider. Output frequency is
- * TEGRA186_CLK_GPC2CLK/2. The frequency of this clock is the
- * frequency at which the GPU graphics engine runs. */
-#define TEGRA186_CLK_GPCCLK 310
-/** @brief output of divider CLK_RST_CONTROLLER_AON_NIC_RATE */
-#define TEGRA186_CLK_AON_NIC 450
-/** @brief output of divider CLK_RST_CONTROLLER_SCE_NIC_RATE */
-#define TEGRA186_CLK_SCE_NIC 451
-/** Fixed 100MHz PLL for PCIe, SATA and superspeed USB */
-#define TEGRA186_CLK_PLLE 512
-/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC_BASE */
-#define TEGRA186_CLK_PLLC 513
-/** Fixed 408MHz PLL for use by peripheral clocks */
-#define TEGRA186_CLK_PLLP 516
-/** @deprecated */
-#define TEGRA186_CLK_PLL_P TEGRA186_CLK_PLLP
-/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLD_BASE for use by DSI */
-#define TEGRA186_CLK_PLLD 518
-/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLD2_BASE for use by HDMI or DP */
-#define TEGRA186_CLK_PLLD2 519
-/**
- * @brief PLL controlled by CLK_RST_CONTROLLER_PLLREFE_BASE.
- * @details Note that this clock only controls the VCO output, before
- * the post-divider. See TEGRA186_CLK_PLLREFE_OUT1 for more
- * information.
- */
-#define TEGRA186_CLK_PLLREFE_VCO 520
-/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC2_BASE */
-#define TEGRA186_CLK_PLLC2 521
-/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC3_BASE */
-#define TEGRA186_CLK_PLLC3 522
-/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLDP_BASE for use as the DP link clock */
-#define TEGRA186_CLK_PLLDP 523
-/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC4_BASE */
-#define TEGRA186_CLK_PLLC4_VCO 524
-/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLA1_BASE for use by audio clocks */
-#define TEGRA186_CLK_PLLA1 525
-/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLNVCSI_BASE */
-#define TEGRA186_CLK_PLLNVCSI 526
-/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLDISPHUB_BASE */
-#define TEGRA186_CLK_PLLDISPHUB 527
-/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLD3_BASE for use by HDMI or DP */
-#define TEGRA186_CLK_PLLD3 528
-/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLBPMPCAM_BASE */
-#define TEGRA186_CLK_PLLBPMPCAM 531
-/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLAON_BASE for use by IP blocks in the AON domain */
-#define TEGRA186_CLK_PLLAON 532
-/** Fixed frequency 960MHz PLL for USB and EAVB */
-#define TEGRA186_CLK_PLLU 533
-/** fixed /2 divider. Output frequency is TEGRA186_CLK_PLLC4_VCO/2 */
-#define TEGRA186_CLK_PLLC4_VCO_DIV2 535
-/** @brief NAFLL clock source for AXI_CBB */
-#define TEGRA186_CLK_NAFLL_AXI_CBB 564
-/** @brief NAFLL clock source for BPMP */
-#define TEGRA186_CLK_NAFLL_BPMP 565
-/** @brief NAFLL clock source for ISP */
-#define TEGRA186_CLK_NAFLL_ISP 566
-/** @brief NAFLL clock source for NVDEC */
-#define TEGRA186_CLK_NAFLL_NVDEC 567
-/** @brief NAFLL clock source for NVENC */
-#define TEGRA186_CLK_NAFLL_NVENC 568
-/** @brief NAFLL clock source for NVJPG */
-#define TEGRA186_CLK_NAFLL_NVJPG 569
-/** @brief NAFLL clock source for SCE */
-#define TEGRA186_CLK_NAFLL_SCE 570
-/** @brief NAFLL clock source for SE */
-#define TEGRA186_CLK_NAFLL_SE 571
-/** @brief NAFLL clock source for TSEC */
-#define TEGRA186_CLK_NAFLL_TSEC 572
-/** @brief NAFLL clock source for TSECB */
-#define TEGRA186_CLK_NAFLL_TSECB 573
-/** @brief NAFLL clock source for VI */
-#define TEGRA186_CLK_NAFLL_VI 574
-/** @brief NAFLL clock source for VIC */
-#define TEGRA186_CLK_NAFLL_VIC 575
-/** @brief NAFLL clock source for DISP */
-#define TEGRA186_CLK_NAFLL_DISP 576
-/** @brief NAFLL clock source for GPU */
-#define TEGRA186_CLK_NAFLL_GPU 577
-/** @brief NAFLL clock source for M-CPU cluster */
-#define TEGRA186_CLK_NAFLL_MCPU 578
-/** @brief NAFLL clock source for B-CPU cluster */
-#define TEGRA186_CLK_NAFLL_BCPU 579
-/** @brief input from Tegra's CLK_32K_IN pad */
-#define TEGRA186_CLK_CLK_32K 608
-/** @brief output of divider CLK_RST_CONTROLLER_CLK_M_DIVIDE */
-#define TEGRA186_CLK_CLK_M 609
-/** @brief output of divider PLL_REF_DIV in CLK_RST_CONTROLLER_OSC_CTRL */
-#define TEGRA186_CLK_PLL_REF 610
-/** @brief input from Tegra's XTAL_IN */
-#define TEGRA186_CLK_OSC 612
-/** @brief clock recovered from EAVB input */
-#define TEGRA186_CLK_EQOS_RX_INPUT 613
-/** @brief clock recovered from DTV input */
-#define TEGRA186_CLK_DTV_INPUT 614
-/** @brief SOR0 brick output which feeds into SOR0_CLK_SEL mux in CLK_RST_CONTROLLER_CLK_SOURCE_SOR0*/
-#define TEGRA186_CLK_SOR0_PAD_CLKOUT 615
-/** @brief SOR1 brick output which feeds into SOR1_CLK_SEL mux in CLK_RST_CONTROLLER_CLK_SOURCE_SOR1*/
-#define TEGRA186_CLK_SOR1_PAD_CLKOUT 616
-/** @brief clock recovered from I2S1 input */
-#define TEGRA186_CLK_I2S1_SYNC_INPUT 617
-/** @brief clock recovered from I2S2 input */
-#define TEGRA186_CLK_I2S2_SYNC_INPUT 618
-/** @brief clock recovered from I2S3 input */
-#define TEGRA186_CLK_I2S3_SYNC_INPUT 619
-/** @brief clock recovered from I2S4 input */
-#define TEGRA186_CLK_I2S4_SYNC_INPUT 620
-/** @brief clock recovered from I2S5 input */
-#define TEGRA186_CLK_I2S5_SYNC_INPUT 621
-/** @brief clock recovered from I2S6 input */
-#define TEGRA186_CLK_I2S6_SYNC_INPUT 622
-/** @brief clock recovered from SPDIFIN input */
-#define TEGRA186_CLK_SPDIFIN_SYNC_INPUT 623
-
-/**
- * @brief subject to change
- * @details maximum clock identifier value plus one.
- */
-#define TEGRA186_CLK_CLK_MAX 624
-
-/** @} */
-
-#endif
diff --git a/include/dt-bindings/clock/tegra20-car.h b/include/dt-bindings/clock/tegra20-car.h
deleted file mode 100644
index 04500b2..0000000
--- a/include/dt-bindings/clock/tegra20-car.h
+++ /dev/null
@@ -1,158 +0,0 @@
-/*
- * This header provides constants for binding nvidia,tegra20-car.
- *
- * The first 96 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
- * registers. These IDs often match those in the CAR's RST_DEVICES registers,
- * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
- * this case, those clocks are assigned IDs above 95 in order to highlight
- * this issue. Implementations that interpret these clock IDs as bit values
- * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
- * explicitly handle these special cases.
- *
- * The balance of the clocks controlled by the CAR are assigned IDs of 96 and
- * above.
- */
-
-#ifndef _DT_BINDINGS_CLOCK_TEGRA20_CAR_H
-#define _DT_BINDINGS_CLOCK_TEGRA20_CAR_H
-
-#define TEGRA20_CLK_CPU 0
-/* 1 */
-/* 2 */
-#define TEGRA20_CLK_AC97 3
-#define TEGRA20_CLK_RTC 4
-#define TEGRA20_CLK_TIMER 5
-#define TEGRA20_CLK_UARTA 6
-/* 7 (register bit affects uart2 and vfir) */
-#define TEGRA20_CLK_GPIO 8
-#define TEGRA20_CLK_SDMMC2 9
-/* 10 (register bit affects spdif_in and spdif_out) */
-#define TEGRA20_CLK_I2S1 11
-#define TEGRA20_CLK_I2C1 12
-#define TEGRA20_CLK_NDFLASH 13
-#define TEGRA20_CLK_SDMMC1 14
-#define TEGRA20_CLK_SDMMC4 15
-#define TEGRA20_CLK_TWC 16
-#define TEGRA20_CLK_PWM 17
-#define TEGRA20_CLK_I2S2 18
-#define TEGRA20_CLK_EPP 19
-/* 20 (register bit affects vi and vi_sensor) */
-#define TEGRA20_CLK_GR2D 21
-#define TEGRA20_CLK_USBD 22
-#define TEGRA20_CLK_ISP 23
-#define TEGRA20_CLK_GR3D 24
-#define TEGRA20_CLK_IDE 25
-#define TEGRA20_CLK_DISP2 26
-#define TEGRA20_CLK_DISP1 27
-#define TEGRA20_CLK_HOST1X 28
-#define TEGRA20_CLK_VCP 29
-/* 30 */
-#define TEGRA20_CLK_CACHE2 31
-
-#define TEGRA20_CLK_MC 32
-#define TEGRA20_CLK_AHBDMA 33
-#define TEGRA20_CLK_APBDMA 34
-/* 35 */
-#define TEGRA20_CLK_KBC 36
-#define TEGRA20_CLK_STAT_MON 37
-#define TEGRA20_CLK_PMC 38
-#define TEGRA20_CLK_FUSE 39
-#define TEGRA20_CLK_KFUSE 40
-#define TEGRA20_CLK_SBC1 41
-#define TEGRA20_CLK_NOR 42
-#define TEGRA20_CLK_SPI 43
-#define TEGRA20_CLK_SBC2 44
-#define TEGRA20_CLK_XIO 45
-#define TEGRA20_CLK_SBC3 46
-#define TEGRA20_CLK_DVC 47
-#define TEGRA20_CLK_DSI 48
-/* 49 (register bit affects tvo and cve) */
-#define TEGRA20_CLK_MIPI 50
-#define TEGRA20_CLK_HDMI 51
-#define TEGRA20_CLK_CSI 52
-#define TEGRA20_CLK_TVDAC 53
-#define TEGRA20_CLK_I2C2 54
-#define TEGRA20_CLK_UARTC 55
-/* 56 */
-#define TEGRA20_CLK_EMC 57
-#define TEGRA20_CLK_USB2 58
-#define TEGRA20_CLK_USB3 59
-#define TEGRA20_CLK_MPE 60
-#define TEGRA20_CLK_VDE 61
-#define TEGRA20_CLK_BSEA 62
-#define TEGRA20_CLK_BSEV 63
-
-#define TEGRA20_CLK_SPEEDO 64
-#define TEGRA20_CLK_UARTD 65
-#define TEGRA20_CLK_UARTE 66
-#define TEGRA20_CLK_I2C3 67
-#define TEGRA20_CLK_SBC4 68
-#define TEGRA20_CLK_SDMMC3 69
-#define TEGRA20_CLK_PEX 70
-#define TEGRA20_CLK_OWR 71
-#define TEGRA20_CLK_AFI 72
-#define TEGRA20_CLK_CSITE 73
-/* 74 */
-#define TEGRA20_CLK_AVPUCQ 75
-#define TEGRA20_CLK_LA 76
-/* 77 */
-/* 78 */
-/* 79 */
-/* 80 */
-/* 81 */
-/* 82 */
-/* 83 */
-#define TEGRA20_CLK_IRAMA 84
-#define TEGRA20_CLK_IRAMB 85
-#define TEGRA20_CLK_IRAMC 86
-#define TEGRA20_CLK_IRAMD 87
-#define TEGRA20_CLK_CRAM2 88
-#define TEGRA20_CLK_AUDIO_2X 89 /* a/k/a audio_2x_sync_clk */
-#define TEGRA20_CLK_CLK_D 90
-/* 91 */
-#define TEGRA20_CLK_CSUS 92
-#define TEGRA20_CLK_CDEV2 93
-#define TEGRA20_CLK_CDEV1 94
-/* 95 */
-
-#define TEGRA20_CLK_UARTB 96
-#define TEGRA20_CLK_VFIR 97
-#define TEGRA20_CLK_SPDIF_IN 98
-#define TEGRA20_CLK_SPDIF_OUT 99
-#define TEGRA20_CLK_VI 100
-#define TEGRA20_CLK_VI_SENSOR 101
-#define TEGRA20_CLK_TVO 102
-#define TEGRA20_CLK_CVE 103
-#define TEGRA20_CLK_OSC 104
-#define TEGRA20_CLK_CLK_32K 105 /* a/k/a clk_s */
-#define TEGRA20_CLK_CLK_M 106
-#define TEGRA20_CLK_SCLK 107
-#define TEGRA20_CLK_CCLK 108
-#define TEGRA20_CLK_HCLK 109
-#define TEGRA20_CLK_PCLK 110
-#define TEGRA20_CLK_BLINK 111
-#define TEGRA20_CLK_PLL_A 112
-#define TEGRA20_CLK_PLL_A_OUT0 113
-#define TEGRA20_CLK_PLL_C 114
-#define TEGRA20_CLK_PLL_C_OUT1 115
-#define TEGRA20_CLK_PLL_D 116
-#define TEGRA20_CLK_PLL_D_OUT0 117
-#define TEGRA20_CLK_PLL_E 118
-#define TEGRA20_CLK_PLL_M 119
-#define TEGRA20_CLK_PLL_M_OUT1 120
-#define TEGRA20_CLK_PLL_P 121
-#define TEGRA20_CLK_PLL_P_OUT1 122
-#define TEGRA20_CLK_PLL_P_OUT2 123
-#define TEGRA20_CLK_PLL_P_OUT3 124
-#define TEGRA20_CLK_PLL_P_OUT4 125
-#define TEGRA20_CLK_PLL_S 126
-#define TEGRA20_CLK_PLL_U 127
-
-#define TEGRA20_CLK_PLL_X 128
-#define TEGRA20_CLK_COP 129 /* a/k/a avp */
-#define TEGRA20_CLK_AUDIO 130 /* a/k/a audio_sync_clk */
-#define TEGRA20_CLK_PLL_REF 131
-#define TEGRA20_CLK_TWD 132
-#define TEGRA20_CLK_CLK_MAX 133
-
-#endif /* _DT_BINDINGS_CLOCK_TEGRA20_CAR_H */
diff --git a/include/dt-bindings/clock/tegra210-car.h b/include/dt-bindings/clock/tegra210-car.h
deleted file mode 100644
index bd3530e..0000000
--- a/include/dt-bindings/clock/tegra210-car.h
+++ /dev/null
@@ -1,401 +0,0 @@
-/*
- * This header provides constants for binding nvidia,tegra210-car.
- *
- * The first 224 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
- * registers. These IDs often match those in the CAR's RST_DEVICES registers,
- * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
- * this case, those clocks are assigned IDs above 224 in order to highlight
- * this issue. Implementations that interpret these clock IDs as bit values
- * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
- * explicitly handle these special cases.
- *
- * The balance of the clocks controlled by the CAR are assigned IDs of 224 and
- * above.
- */
-
-#ifndef _DT_BINDINGS_CLOCK_TEGRA210_CAR_H
-#define _DT_BINDINGS_CLOCK_TEGRA210_CAR_H
-
-/* 0 */
-/* 1 */
-/* 2 */
-#define TEGRA210_CLK_ISPB 3
-#define TEGRA210_CLK_RTC 4
-#define TEGRA210_CLK_TIMER 5
-#define TEGRA210_CLK_UARTA 6
-/* 7 (register bit affects uartb and vfir) */
-#define TEGRA210_CLK_GPIO 8
-#define TEGRA210_CLK_SDMMC2 9
-/* 10 (register bit affects spdif_in and spdif_out) */
-#define TEGRA210_CLK_I2S1 11
-#define TEGRA210_CLK_I2C1 12
-/* 13 */
-#define TEGRA210_CLK_SDMMC1 14
-#define TEGRA210_CLK_SDMMC4 15
-/* 16 */
-#define TEGRA210_CLK_PWM 17
-#define TEGRA210_CLK_I2S2 18
-/* 19 */
-/* 20 (register bit affects vi and vi_sensor) */
-/* 21 */
-#define TEGRA210_CLK_USBD 22
-#define TEGRA210_CLK_ISP 23
-/* 24 */
-/* 25 */
-#define TEGRA210_CLK_DISP2 26
-#define TEGRA210_CLK_DISP1 27
-#define TEGRA210_CLK_HOST1X 28
-/* 29 */
-#define TEGRA210_CLK_I2S0 30
-/* 31 */
-
-#define TEGRA210_CLK_MC 32
-#define TEGRA210_CLK_AHBDMA 33
-#define TEGRA210_CLK_APBDMA 34
-/* 35 */
-/* 36 */
-/* 37 */
-#define TEGRA210_CLK_PMC 38
-/* 39 (register bit affects fuse and fuse_burn) */
-#define TEGRA210_CLK_KFUSE 40
-#define TEGRA210_CLK_SBC1 41
-/* 42 */
-/* 43 */
-#define TEGRA210_CLK_SBC2 44
-/* 45 */
-#define TEGRA210_CLK_SBC3 46
-#define TEGRA210_CLK_I2C5 47
-#define TEGRA210_CLK_DSIA 48
-/* 49 */
-/* 50 */
-/* 51 */
-#define TEGRA210_CLK_CSI 52
-/* 53 */
-#define TEGRA210_CLK_I2C2 54
-#define TEGRA210_CLK_UARTC 55
-#define TEGRA210_CLK_MIPI_CAL 56
-#define TEGRA210_CLK_EMC 57
-#define TEGRA210_CLK_USB2 58
-/* 59 */
-/* 60 */
-/* 61 */
-/* 62 */
-#define TEGRA210_CLK_BSEV 63
-
-/* 64 */
-#define TEGRA210_CLK_UARTD 65
-/* 66 */
-#define TEGRA210_CLK_I2C3 67
-#define TEGRA210_CLK_SBC4 68
-#define TEGRA210_CLK_SDMMC3 69
-#define TEGRA210_CLK_PCIE 70
-#define TEGRA210_CLK_OWR 71
-#define TEGRA210_CLK_AFI 72
-#define TEGRA210_CLK_CSITE 73
-/* 74 */
-/* 75 */
-/* 76 */
-/* 77 */
-#define TEGRA210_CLK_SOC_THERM 78
-#define TEGRA210_CLK_DTV 79
-/* 80 */
-#define TEGRA210_CLK_I2CSLOW 81
-#define TEGRA210_CLK_DSIB 82
-#define TEGRA210_CLK_TSEC 83
-/* 84 */
-/* 85 */
-/* 86 */
-/* 87 */
-/* 88 */
-#define TEGRA210_CLK_XUSB_HOST 89
-/* 90 */
-/* 91 */
-#define TEGRA210_CLK_CSUS 92
-/* 93 */
-/* 94 */
-/* 95 (bit affects xusb_dev and xusb_dev_src) */
-
-/* 96 */
-/* 97 */
-/* 98 */
-#define TEGRA210_CLK_MSELECT 99
-#define TEGRA210_CLK_TSENSOR 100
-#define TEGRA210_CLK_I2S3 101
-#define TEGRA210_CLK_I2S4 102
-#define TEGRA210_CLK_I2C4 103
-/* 104 */
-/* 105 */
-#define TEGRA210_CLK_D_AUDIO 106
-#define TEGRA210_CLK_APB2APE 107
-/* 108 */
-/* 109 */
-/* 110 */
-#define TEGRA210_CLK_HDA2CODEC_2X 111
-/* 112 */
-/* 113 */
-/* 114 */
-/* 115 */
-/* 116 */
-/* 117 */
-#define TEGRA210_CLK_SPDIF_2X 118
-#define TEGRA210_CLK_ACTMON 119
-#define TEGRA210_CLK_EXTERN1 120
-#define TEGRA210_CLK_EXTERN2 121
-#define TEGRA210_CLK_EXTERN3 122
-#define TEGRA210_CLK_SATA_OOB 123
-#define TEGRA210_CLK_SATA 124
-#define TEGRA210_CLK_HDA 125
-/* 126 */
-/* 127 */
-
-#define TEGRA210_CLK_HDA2HDMI 128
-/* 129 */
-/* 130 */
-/* 131 */
-/* 132 */
-/* 133 */
-/* 134 */
-/* 135 */
-/* 136 */
-/* 137 */
-/* 138 */
-/* 139 */
-/* 140 */
-/* 141 */
-/* 142 */
-/* (bit affects xusb_falcon_src, xusb_fs_src, xusb_host_src and xusb_ss_src) */
-#define TEGRA210_CLK_XUSB_GATE 143
-#define TEGRA210_CLK_CILAB 144
-#define TEGRA210_CLK_CILCD 145
-#define TEGRA210_CLK_CILE 146
-#define TEGRA210_CLK_DSIALP 147
-#define TEGRA210_CLK_DSIBLP 148
-#define TEGRA210_CLK_ENTROPY 149
-/* 150 */
-/* 151 */
-/* 152 */
-/* 153 */
-/* 154 */
-/* 155 (bit affects dfll_ref and dfll_soc) */
-#define TEGRA210_CLK_XUSB_SS 156
-/* 157 */
-/* 158 */
-/* 159 */
-
-/* 160 */
-#define TEGRA210_CLK_DMIC1 161
-#define TEGRA210_CLK_DMIC2 162
-/* 163 */
-/* 164 */
-/* 165 */
-#define TEGRA210_CLK_I2C6 166
-/* 167 */
-/* 168 */
-/* 169 */
-/* 170 */
-#define TEGRA210_CLK_VIM2_CLK 171
-/* 172 */
-#define TEGRA210_CLK_MIPIBIF 173
-/* 174 */
-/* 175 */
-/* 176 */
-#define TEGRA210_CLK_CLK72MHZ 177
-#define TEGRA210_CLK_VIC03 178
-/* 179 */
-/* 180 */
-#define TEGRA210_CLK_DPAUX 181
-#define TEGRA210_CLK_SOR0 182
-#define TEGRA210_CLK_SOR1 183
-#define TEGRA210_CLK_GPU 184
-#define TEGRA210_CLK_DBGAPB 185
-/* 186 */
-#define TEGRA210_CLK_PLL_P_OUT_ADSP 187
-/* 188 */
-#define TEGRA210_CLK_PLL_G_REF 189
-/* 190 */
-/* 191 */
-
-/* 192 */
-#define TEGRA210_CLK_SDMMC_LEGACY 193
-#define TEGRA210_CLK_NVDEC 194
-#define TEGRA210_CLK_NVJPG 195
-/* 196 */
-#define TEGRA210_CLK_DMIC3 197
-#define TEGRA210_CLK_APE 198
-/* 199 */
-/* 200 */
-/* 201 */
-#define TEGRA210_CLK_MAUD 202
-/* 203 */
-/* 204 */
-/* 205 */
-#define TEGRA210_CLK_TSECB 206
-#define TEGRA210_CLK_DPAUX1 207
-#define TEGRA210_CLK_VI_I2C 208
-#define TEGRA210_CLK_HSIC_TRK 209
-#define TEGRA210_CLK_USB2_TRK 210
-#define TEGRA210_CLK_QSPI 211
-#define TEGRA210_CLK_UARTAPE 212
-/* 213 */
-/* 214 */
-/* 215 */
-/* 216 */
-/* 217 */
-/* 218 */
-#define TEGRA210_CLK_NVENC 219
-/* 220 */
-/* 221 */
-#define TEGRA210_CLK_SOR_SAFE 222
-#define TEGRA210_CLK_PLL_P_OUT_CPU 223
-
-
-#define TEGRA210_CLK_UARTB 224
-#define TEGRA210_CLK_VFIR 225
-#define TEGRA210_CLK_SPDIF_IN 226
-#define TEGRA210_CLK_SPDIF_OUT 227
-#define TEGRA210_CLK_VI 228
-#define TEGRA210_CLK_VI_SENSOR 229
-#define TEGRA210_CLK_FUSE 230
-#define TEGRA210_CLK_FUSE_BURN 231
-#define TEGRA210_CLK_CLK_32K 232
-#define TEGRA210_CLK_CLK_M 233
-#define TEGRA210_CLK_CLK_M_DIV2 234
-#define TEGRA210_CLK_CLK_M_DIV4 235
-#define TEGRA210_CLK_PLL_REF 236
-#define TEGRA210_CLK_PLL_C 237
-#define TEGRA210_CLK_PLL_C_OUT1 238
-#define TEGRA210_CLK_PLL_C2 239
-#define TEGRA210_CLK_PLL_C3 240
-#define TEGRA210_CLK_PLL_M 241
-#define TEGRA210_CLK_PLL_M_OUT1 242
-#define TEGRA210_CLK_PLL_P 243
-#define TEGRA210_CLK_PLL_P_OUT1 244
-#define TEGRA210_CLK_PLL_P_OUT2 245
-#define TEGRA210_CLK_PLL_P_OUT3 246
-#define TEGRA210_CLK_PLL_P_OUT4 247
-#define TEGRA210_CLK_PLL_A 248
-#define TEGRA210_CLK_PLL_A_OUT0 249
-#define TEGRA210_CLK_PLL_D 250
-#define TEGRA210_CLK_PLL_D_OUT0 251
-#define TEGRA210_CLK_PLL_D2 252
-#define TEGRA210_CLK_PLL_D2_OUT0 253
-#define TEGRA210_CLK_PLL_U 254
-#define TEGRA210_CLK_PLL_U_480M 255
-
-#define TEGRA210_CLK_PLL_U_60M 256
-#define TEGRA210_CLK_PLL_U_48M 257
-/* 258 */
-#define TEGRA210_CLK_PLL_X 259
-#define TEGRA210_CLK_PLL_X_OUT0 260
-#define TEGRA210_CLK_PLL_RE_VCO 261
-#define TEGRA210_CLK_PLL_RE_OUT 262
-#define TEGRA210_CLK_PLL_E 263
-#define TEGRA210_CLK_SPDIF_IN_SYNC 264
-#define TEGRA210_CLK_I2S0_SYNC 265
-#define TEGRA210_CLK_I2S1_SYNC 266
-#define TEGRA210_CLK_I2S2_SYNC 267
-#define TEGRA210_CLK_I2S3_SYNC 268
-#define TEGRA210_CLK_I2S4_SYNC 269
-#define TEGRA210_CLK_VIMCLK_SYNC 270
-#define TEGRA210_CLK_AUDIO0 271
-#define TEGRA210_CLK_AUDIO1 272
-#define TEGRA210_CLK_AUDIO2 273
-#define TEGRA210_CLK_AUDIO3 274
-#define TEGRA210_CLK_AUDIO4 275
-#define TEGRA210_CLK_SPDIF 276
-#define TEGRA210_CLK_CLK_OUT_1 277
-#define TEGRA210_CLK_CLK_OUT_2 278
-#define TEGRA210_CLK_CLK_OUT_3 279
-#define TEGRA210_CLK_BLINK 280
-/* 281 */
-/* 282 */
-/* 283 */
-#define TEGRA210_CLK_XUSB_HOST_SRC 284
-#define TEGRA210_CLK_XUSB_FALCON_SRC 285
-#define TEGRA210_CLK_XUSB_FS_SRC 286
-#define TEGRA210_CLK_XUSB_SS_SRC 287
-
-#define TEGRA210_CLK_XUSB_DEV_SRC 288
-#define TEGRA210_CLK_XUSB_DEV 289
-#define TEGRA210_CLK_XUSB_HS_SRC 290
-#define TEGRA210_CLK_SCLK 291
-#define TEGRA210_CLK_HCLK 292
-#define TEGRA210_CLK_PCLK 293
-#define TEGRA210_CLK_CCLK_G 294
-#define TEGRA210_CLK_CCLK_LP 295
-#define TEGRA210_CLK_DFLL_REF 296
-#define TEGRA210_CLK_DFLL_SOC 297
-#define TEGRA210_CLK_VI_SENSOR2 298
-#define TEGRA210_CLK_PLL_P_OUT5 299
-#define TEGRA210_CLK_CML0 300
-#define TEGRA210_CLK_CML1 301
-#define TEGRA210_CLK_PLL_C4 302
-#define TEGRA210_CLK_PLL_DP 303
-#define TEGRA210_CLK_PLL_E_MUX 304
-#define TEGRA210_CLK_PLL_MB 305
-#define TEGRA210_CLK_PLL_A1 306
-#define TEGRA210_CLK_PLL_D_DSI_OUT 307
-#define TEGRA210_CLK_PLL_C4_OUT0 308
-#define TEGRA210_CLK_PLL_C4_OUT1 309
-#define TEGRA210_CLK_PLL_C4_OUT2 310
-#define TEGRA210_CLK_PLL_C4_OUT3 311
-#define TEGRA210_CLK_PLL_U_OUT 312
-#define TEGRA210_CLK_PLL_U_OUT1 313
-#define TEGRA210_CLK_PLL_U_OUT2 314
-#define TEGRA210_CLK_USB2_HSIC_TRK 315
-#define TEGRA210_CLK_PLL_P_OUT_HSIO 316
-#define TEGRA210_CLK_PLL_P_OUT_XUSB 317
-#define TEGRA210_CLK_XUSB_SSP_SRC 318
-#define TEGRA210_CLK_PLL_RE_OUT1 319
-/* 320 */
-/* 321 */
-/* 322 */
-/* 323 */
-/* 324 */
-/* 325 */
-/* 326 */
-/* 327 */
-/* 328 */
-/* 329 */
-/* 330 */
-/* 331 */
-/* 332 */
-/* 333 */
-/* 334 */
-/* 335 */
-/* 336 */
-/* 337 */
-/* 338 */
-/* 339 */
-/* 340 */
-/* 341 */
-/* 342 */
-/* 343 */
-/* 344 */
-/* 345 */
-/* 346 */
-/* 347 */
-/* 348 */
-/* 349 */
-
-#define TEGRA210_CLK_AUDIO0_MUX 350
-#define TEGRA210_CLK_AUDIO1_MUX 351
-#define TEGRA210_CLK_AUDIO2_MUX 352
-#define TEGRA210_CLK_AUDIO3_MUX 353
-#define TEGRA210_CLK_AUDIO4_MUX 354
-#define TEGRA210_CLK_SPDIF_MUX 355
-#define TEGRA210_CLK_CLK_OUT_1_MUX 356
-#define TEGRA210_CLK_CLK_OUT_2_MUX 357
-#define TEGRA210_CLK_CLK_OUT_3_MUX 358
-#define TEGRA210_CLK_DSIA_MUX 359
-#define TEGRA210_CLK_DSIB_MUX 360
-#define TEGRA210_CLK_SOR0_LVDS 361
-#define TEGRA210_CLK_XUSB_SS_DIV2 362
-
-#define TEGRA210_CLK_PLL_M_UD 363
-#define TEGRA210_CLK_PLL_C_UD 364
-#define TEGRA210_CLK_SCLK_MUX 365
-
-#define TEGRA210_CLK_CLK_MAX 366
-
-#endif /* _DT_BINDINGS_CLOCK_TEGRA210_CAR_H */
diff --git a/include/dt-bindings/clock/tegra30-car.h b/include/dt-bindings/clock/tegra30-car.h
deleted file mode 100644
index 889e49b..0000000
--- a/include/dt-bindings/clock/tegra30-car.h
+++ /dev/null
@@ -1,273 +0,0 @@
-/*
- * This header provides constants for binding nvidia,tegra30-car.
- *
- * The first 130 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
- * registers. These IDs often match those in the CAR's RST_DEVICES registers,
- * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
- * this case, those clocks are assigned IDs above 160 in order to highlight
- * this issue. Implementations that interpret these clock IDs as bit values
- * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
- * explicitly handle these special cases.
- *
- * The balance of the clocks controlled by the CAR are assigned IDs of 160 and
- * above.
- */
-
-#ifndef _DT_BINDINGS_CLOCK_TEGRA30_CAR_H
-#define _DT_BINDINGS_CLOCK_TEGRA30_CAR_H
-
-#define TEGRA30_CLK_CPU 0
-/* 1 */
-/* 2 */
-/* 3 */
-#define TEGRA30_CLK_RTC 4
-#define TEGRA30_CLK_TIMER 5
-#define TEGRA30_CLK_UARTA 6
-/* 7 (register bit affects uartb and vfir) */
-#define TEGRA30_CLK_GPIO 8
-#define TEGRA30_CLK_SDMMC2 9
-/* 10 (register bit affects spdif_in and spdif_out) */
-#define TEGRA30_CLK_I2S1 11
-#define TEGRA30_CLK_I2C1 12
-#define TEGRA30_CLK_NDFLASH 13
-#define TEGRA30_CLK_SDMMC1 14
-#define TEGRA30_CLK_SDMMC4 15
-/* 16 */
-#define TEGRA30_CLK_PWM 17
-#define TEGRA30_CLK_I2S2 18
-#define TEGRA30_CLK_EPP 19
-/* 20 (register bit affects vi and vi_sensor) */
-#define TEGRA30_CLK_GR2D 21
-#define TEGRA30_CLK_USBD 22
-#define TEGRA30_CLK_ISP 23
-#define TEGRA30_CLK_GR3D 24
-/* 25 */
-#define TEGRA30_CLK_DISP2 26
-#define TEGRA30_CLK_DISP1 27
-#define TEGRA30_CLK_HOST1X 28
-#define TEGRA30_CLK_VCP 29
-#define TEGRA30_CLK_I2S0 30
-#define TEGRA30_CLK_COP_CACHE 31
-
-#define TEGRA30_CLK_MC 32
-#define TEGRA30_CLK_AHBDMA 33
-#define TEGRA30_CLK_APBDMA 34
-/* 35 */
-#define TEGRA30_CLK_KBC 36
-#define TEGRA30_CLK_STATMON 37
-#define TEGRA30_CLK_PMC 38
-/* 39 (register bit affects fuse and fuse_burn) */
-#define TEGRA30_CLK_KFUSE 40
-#define TEGRA30_CLK_SBC1 41
-#define TEGRA30_CLK_NOR 42
-/* 43 */
-#define TEGRA30_CLK_SBC2 44
-/* 45 */
-#define TEGRA30_CLK_SBC3 46
-#define TEGRA30_CLK_I2C5 47
-#define TEGRA30_CLK_DSIA 48
-/* 49 (register bit affects cve and tvo) */
-#define TEGRA30_CLK_MIPI 50
-#define TEGRA30_CLK_HDMI 51
-#define TEGRA30_CLK_CSI 52
-#define TEGRA30_CLK_TVDAC 53
-#define TEGRA30_CLK_I2C2 54
-#define TEGRA30_CLK_UARTC 55
-/* 56 */
-#define TEGRA30_CLK_EMC 57
-#define TEGRA30_CLK_USB2 58
-#define TEGRA30_CLK_USB3 59
-#define TEGRA30_CLK_MPE 60
-#define TEGRA30_CLK_VDE 61
-#define TEGRA30_CLK_BSEA 62
-#define TEGRA30_CLK_BSEV 63
-
-#define TEGRA30_CLK_SPEEDO 64
-#define TEGRA30_CLK_UARTD 65
-#define TEGRA30_CLK_UARTE 66
-#define TEGRA30_CLK_I2C3 67
-#define TEGRA30_CLK_SBC4 68
-#define TEGRA30_CLK_SDMMC3 69
-#define TEGRA30_CLK_PCIE 70
-#define TEGRA30_CLK_OWR 71
-#define TEGRA30_CLK_AFI 72
-#define TEGRA30_CLK_CSITE 73
-/* 74 */
-#define TEGRA30_CLK_AVPUCQ 75
-#define TEGRA30_CLK_LA 76
-/* 77 */
-/* 78 */
-#define TEGRA30_CLK_DTV 79
-#define TEGRA30_CLK_NDSPEED 80
-#define TEGRA30_CLK_I2CSLOW 81
-#define TEGRA30_CLK_DSIB 82
-/* 83 */
-#define TEGRA30_CLK_IRAMA 84
-#define TEGRA30_CLK_IRAMB 85
-#define TEGRA30_CLK_IRAMC 86
-#define TEGRA30_CLK_IRAMD 87
-#define TEGRA30_CLK_CRAM2 88
-/* 89 */
-#define TEGRA30_CLK_AUDIO_2X 90 /* a/k/a audio_2x_sync_clk */
-/* 91 */
-#define TEGRA30_CLK_CSUS 92
-#define TEGRA30_CLK_CDEV2 93
-#define TEGRA30_CLK_CDEV1 94
-/* 95 */
-
-#define TEGRA30_CLK_CPU_G 96
-#define TEGRA30_CLK_CPU_LP 97
-#define TEGRA30_CLK_GR3D2 98
-#define TEGRA30_CLK_MSELECT 99
-#define TEGRA30_CLK_TSENSOR 100
-#define TEGRA30_CLK_I2S3 101
-#define TEGRA30_CLK_I2S4 102
-#define TEGRA30_CLK_I2C4 103
-#define TEGRA30_CLK_SBC5 104
-#define TEGRA30_CLK_SBC6 105
-#define TEGRA30_CLK_D_AUDIO 106
-#define TEGRA30_CLK_APBIF 107
-#define TEGRA30_CLK_DAM0 108
-#define TEGRA30_CLK_DAM1 109
-#define TEGRA30_CLK_DAM2 110
-#define TEGRA30_CLK_HDA2CODEC_2X 111
-#define TEGRA30_CLK_ATOMICS 112
-#define TEGRA30_CLK_AUDIO0_2X 113
-#define TEGRA30_CLK_AUDIO1_2X 114
-#define TEGRA30_CLK_AUDIO2_2X 115
-#define TEGRA30_CLK_AUDIO3_2X 116
-#define TEGRA30_CLK_AUDIO4_2X 117
-#define TEGRA30_CLK_SPDIF_2X 118
-#define TEGRA30_CLK_ACTMON 119
-#define TEGRA30_CLK_EXTERN1 120
-#define TEGRA30_CLK_EXTERN2 121
-#define TEGRA30_CLK_EXTERN3 122
-#define TEGRA30_CLK_SATA_OOB 123
-#define TEGRA30_CLK_SATA 124
-#define TEGRA30_CLK_HDA 125
-/* 126 */
-#define TEGRA30_CLK_SE 127
-
-#define TEGRA30_CLK_HDA2HDMI 128
-#define TEGRA30_CLK_SATA_COLD 129
-/* 130 */
-/* 131 */
-/* 132 */
-/* 133 */
-/* 134 */
-/* 135 */
-/* 136 */
-/* 137 */
-/* 138 */
-/* 139 */
-/* 140 */
-/* 141 */
-/* 142 */
-/* 143 */
-/* 144 */
-/* 145 */
-/* 146 */
-/* 147 */
-/* 148 */
-/* 149 */
-/* 150 */
-/* 151 */
-/* 152 */
-/* 153 */
-/* 154 */
-/* 155 */
-/* 156 */
-/* 157 */
-/* 158 */
-/* 159 */
-
-#define TEGRA30_CLK_UARTB 160
-#define TEGRA30_CLK_VFIR 161
-#define TEGRA30_CLK_SPDIF_IN 162
-#define TEGRA30_CLK_SPDIF_OUT 163
-#define TEGRA30_CLK_VI 164
-#define TEGRA30_CLK_VI_SENSOR 165
-#define TEGRA30_CLK_FUSE 166
-#define TEGRA30_CLK_FUSE_BURN 167
-#define TEGRA30_CLK_CVE 168
-#define TEGRA30_CLK_TVO 169
-#define TEGRA30_CLK_CLK_32K 170
-#define TEGRA30_CLK_CLK_M 171
-#define TEGRA30_CLK_CLK_M_DIV2 172
-#define TEGRA30_CLK_CLK_M_DIV4 173
-#define TEGRA30_CLK_PLL_REF 174
-#define TEGRA30_CLK_PLL_C 175
-#define TEGRA30_CLK_PLL_C_OUT1 176
-#define TEGRA30_CLK_PLL_M 177
-#define TEGRA30_CLK_PLL_M_OUT1 178
-#define TEGRA30_CLK_PLL_P 179
-#define TEGRA30_CLK_PLL_P_OUT1 180
-#define TEGRA30_CLK_PLL_P_OUT2 181
-#define TEGRA30_CLK_PLL_P_OUT3 182
-#define TEGRA30_CLK_PLL_P_OUT4 183
-#define TEGRA30_CLK_PLL_A 184
-#define TEGRA30_CLK_PLL_A_OUT0 185
-#define TEGRA30_CLK_PLL_D 186
-#define TEGRA30_CLK_PLL_D_OUT0 187
-#define TEGRA30_CLK_PLL_D2 188
-#define TEGRA30_CLK_PLL_D2_OUT0 189
-#define TEGRA30_CLK_PLL_U 190
-#define TEGRA30_CLK_PLL_X 191
-
-#define TEGRA30_CLK_PLL_X_OUT0 192
-#define TEGRA30_CLK_PLL_E 193
-#define TEGRA30_CLK_SPDIF_IN_SYNC 194
-#define TEGRA30_CLK_I2S0_SYNC 195
-#define TEGRA30_CLK_I2S1_SYNC 196
-#define TEGRA30_CLK_I2S2_SYNC 197
-#define TEGRA30_CLK_I2S3_SYNC 198
-#define TEGRA30_CLK_I2S4_SYNC 199
-#define TEGRA30_CLK_VIMCLK_SYNC 200
-#define TEGRA30_CLK_AUDIO0 201
-#define TEGRA30_CLK_AUDIO1 202
-#define TEGRA30_CLK_AUDIO2 203
-#define TEGRA30_CLK_AUDIO3 204
-#define TEGRA30_CLK_AUDIO4 205
-#define TEGRA30_CLK_SPDIF 206
-#define TEGRA30_CLK_CLK_OUT_1 207 /* (extern1) */
-#define TEGRA30_CLK_CLK_OUT_2 208 /* (extern2) */
-#define TEGRA30_CLK_CLK_OUT_3 209 /* (extern3) */
-#define TEGRA30_CLK_SCLK 210
-#define TEGRA30_CLK_BLINK 211
-#define TEGRA30_CLK_CCLK_G 212
-#define TEGRA30_CLK_CCLK_LP 213
-#define TEGRA30_CLK_TWD 214
-#define TEGRA30_CLK_CML0 215
-#define TEGRA30_CLK_CML1 216
-#define TEGRA30_CLK_HCLK 217
-#define TEGRA30_CLK_PCLK 218
-/* 219 */
-/* 220 */
-/* 221 */
-/* 222 */
-/* 223 */
-
-/* 288 */
-/* 289 */
-/* 290 */
-/* 291 */
-/* 292 */
-/* 293 */
-/* 294 */
-/* 295 */
-/* 296 */
-/* 297 */
-/* 298 */
-/* 299 */
-#define TEGRA30_CLK_CLK_OUT_1_MUX 300
-#define TEGRA30_CLK_CLK_OUT_2_MUX 301
-#define TEGRA30_CLK_CLK_OUT_3_MUX 302
-#define TEGRA30_CLK_AUDIO0_MUX 303
-#define TEGRA30_CLK_AUDIO1_MUX 304
-#define TEGRA30_CLK_AUDIO2_MUX 305
-#define TEGRA30_CLK_AUDIO3_MUX 306
-#define TEGRA30_CLK_AUDIO4_MUX 307
-#define TEGRA30_CLK_SPDIF_MUX 308
-#define TEGRA30_CLK_CLK_MAX 309
-
-#endif /* _DT_BINDINGS_CLOCK_TEGRA30_CAR_H */
diff --git a/include/dt-bindings/clock/xlnx-zynqmp-clk.h b/include/dt-bindings/clock/xlnx-zynqmp-clk.h
deleted file mode 100644
index cdc4c0b..0000000
--- a/include/dt-bindings/clock/xlnx-zynqmp-clk.h
+++ /dev/null
@@ -1,126 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Xilinx Zynq MPSoC Firmware layer
- *
- * Copyright (C) 2014-2018 Xilinx, Inc.
- *
- */
-
-#ifndef _DT_BINDINGS_CLK_ZYNQMP_H
-#define _DT_BINDINGS_CLK_ZYNQMP_H
-
-#define IOPLL 0
-#define RPLL 1
-#define APLL 2
-#define DPLL 3
-#define VPLL 4
-#define IOPLL_TO_FPD 5
-#define RPLL_TO_FPD 6
-#define APLL_TO_LPD 7
-#define DPLL_TO_LPD 8
-#define VPLL_TO_LPD 9
-#define ACPU 10
-#define ACPU_HALF 11
-#define DBF_FPD 12
-#define DBF_LPD 13
-#define DBG_TRACE 14
-#define DBG_TSTMP 15
-#define DP_VIDEO_REF 16
-#define DP_AUDIO_REF 17
-#define DP_STC_REF 18
-#define GDMA_REF 19
-#define DPDMA_REF 20
-#define DDR_REF 21
-#define SATA_REF 22
-#define PCIE_REF 23
-#define GPU_REF 24
-#define GPU_PP0_REF 25
-#define GPU_PP1_REF 26
-#define TOPSW_MAIN 27
-#define TOPSW_LSBUS 28
-#define GTGREF0_REF 29
-#define LPD_SWITCH 30
-#define LPD_LSBUS 31
-#define USB0_BUS_REF 32
-#define USB1_BUS_REF 33
-#define USB3_DUAL_REF 34
-#define USB0 35
-#define USB1 36
-#define CPU_R5 37
-#define CPU_R5_CORE 38
-#define CSU_SPB 39
-#define CSU_PLL 40
-#define PCAP 41
-#define IOU_SWITCH 42
-#define GEM_TSU_REF 43
-#define GEM_TSU 44
-#define GEM0_TX 45
-#define GEM1_TX 46
-#define GEM2_TX 47
-#define GEM3_TX 48
-#define GEM0_RX 49
-#define GEM1_RX 50
-#define GEM2_RX 51
-#define GEM3_RX 52
-#define QSPI_REF 53
-#define SDIO0_REF 54
-#define SDIO1_REF 55
-#define UART0_REF 56
-#define UART1_REF 57
-#define SPI0_REF 58
-#define SPI1_REF 59
-#define NAND_REF 60
-#define I2C0_REF 61
-#define I2C1_REF 62
-#define CAN0_REF 63
-#define CAN1_REF 64
-#define CAN0 65
-#define CAN1 66
-#define DLL_REF 67
-#define ADMA_REF 68
-#define TIMESTAMP_REF 69
-#define AMS_REF 70
-#define PL0_REF 71
-#define PL1_REF 72
-#define PL2_REF 73
-#define PL3_REF 74
-#define WDT 75
-#define IOPLL_INT 76
-#define IOPLL_PRE_SRC 77
-#define IOPLL_HALF 78
-#define IOPLL_INT_MUX 79
-#define IOPLL_POST_SRC 80
-#define RPLL_INT 81
-#define RPLL_PRE_SRC 82
-#define RPLL_HALF 83
-#define RPLL_INT_MUX 84
-#define RPLL_POST_SRC 85
-#define APLL_INT 86
-#define APLL_PRE_SRC 87
-#define APLL_HALF 88
-#define APLL_INT_MUX 89
-#define APLL_POST_SRC 90
-#define DPLL_INT 91
-#define DPLL_PRE_SRC 92
-#define DPLL_HALF 93
-#define DPLL_INT_MUX 94
-#define DPLL_POST_SRC 95
-#define VPLL_INT 96
-#define VPLL_PRE_SRC 97
-#define VPLL_HALF 98
-#define VPLL_INT_MUX 99
-#define VPLL_POST_SRC 100
-#define CAN0_MIO 101
-#define CAN1_MIO 102
-#define ACPU_FULL 103
-#define GEM0_REF 104
-#define GEM1_REF 105
-#define GEM2_REF 106
-#define GEM3_REF 107
-#define GEM0_REF_UNG 108
-#define GEM1_REF_UNG 109
-#define GEM2_REF_UNG 110
-#define GEM3_REF_UNG 111
-#define LPD_WDT 112
-
-#endif
diff --git a/include/dt-bindings/comphy/comphy_data.h b/include/dt-bindings/comphy/comphy_data.h
deleted file mode 100644
index 4f7e282..0000000
--- a/include/dt-bindings/comphy/comphy_data.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2015-2016 Marvell International Ltd.
- */
-
-#ifndef _COMPHY_DATA_H_
-#define _COMPHY_DATA_H_
-
-#define PHY_SPEED_1_25G 0
-#define PHY_SPEED_1_5G 1
-#define PHY_SPEED_2_5G 2
-#define PHY_SPEED_3G 3
-#define PHY_SPEED_3_125G 4
-#define PHY_SPEED_5G 5
-#define PHY_SPEED_5_15625G 6
-#define PHY_SPEED_6G 7
-#define PHY_SPEED_6_25G 8
-#define PHY_SPEED_10_3125G 9
-#define PHY_SPEED_MAX 10
-#define PHY_SPEED_INVALID 0xff
-
-#define PHY_TYPE_UNCONNECTED 0
-#define PHY_TYPE_PEX0 1
-#define PHY_TYPE_PEX1 2
-#define PHY_TYPE_PEX2 3
-#define PHY_TYPE_PEX3 4
-#define PHY_TYPE_SATA0 5
-#define PHY_TYPE_SATA1 6
-#define PHY_TYPE_SATA2 7
-#define PHY_TYPE_SATA3 8
-#define PHY_TYPE_SGMII0 9
-#define PHY_TYPE_SGMII1 10
-#define PHY_TYPE_SGMII2 11
-#define PHY_TYPE_SGMII3 12
-#define PHY_TYPE_QSGMII 13
-#define PHY_TYPE_USB3_HOST0 14
-#define PHY_TYPE_USB3_HOST1 15
-#define PHY_TYPE_USB3_DEVICE 16
-#define PHY_TYPE_XAUI0 17
-#define PHY_TYPE_XAUI1 18
-#define PHY_TYPE_XAUI2 19
-#define PHY_TYPE_XAUI3 20
-#define PHY_TYPE_RXAUI0 21
-#define PHY_TYPE_RXAUI1 22
-#define PHY_TYPE_SFI 23
-#define PHY_TYPE_IGNORE 24
-#define PHY_TYPE_MAX 25
-#define PHY_TYPE_INVALID 0xff
-
-#define PHY_POLARITY_NO_INVERT 0
-#define PHY_POLARITY_TXD_INVERT 1
-#define PHY_POLARITY_RXD_INVERT 2
-#define PHY_POLARITY_ALL_INVERT \
- (PHY_POLARITY_TXD_INVERT | PHY_POLARITY_RXD_INVERT)
-
-#define UTMI_PHY_TO_USB3_HOST0 0
-#define UTMI_PHY_TO_USB3_HOST1 1
-#define UTMI_PHY_TO_USB3_DEVICE0 2
-#define UTMI_PHY_INVALID 0xff
-
-#endif /* _COMPHY_DATA_H_ */
-
diff --git a/include/dt-bindings/dma/at91.h b/include/dt-bindings/dma/at91.h
deleted file mode 100644
index ab6cbba..0000000
--- a/include/dt-bindings/dma/at91.h
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * This header provides macros for at91 dma bindings.
- *
- * Copyright (C) 2013 Ludovic Desroches <ludovic.desroches@atmel.com>
- *
- * GPLv2 only
- */
-
-#ifndef __DT_BINDINGS_AT91_DMA_H__
-#define __DT_BINDINGS_AT91_DMA_H__
-
-/* ---------- HDMAC ---------- */
-
-/*
- * Source and/or destination peripheral ID
- */
-#define AT91_DMA_CFG_PER_ID_MASK (0xff)
-#define AT91_DMA_CFG_PER_ID(id) (id & AT91_DMA_CFG_PER_ID_MASK)
-
-/*
- * FIFO configuration: it defines when a request is serviced.
- */
-#define AT91_DMA_CFG_FIFOCFG_OFFSET (8)
-#define AT91_DMA_CFG_FIFOCFG_MASK (0xf << AT91_DMA_CFG_FIFOCFG_OFFSET)
-#define AT91_DMA_CFG_FIFOCFG_HALF (0x0 << AT91_DMA_CFG_FIFOCFG_OFFSET) /* half FIFO (default behavior) */
-#define AT91_DMA_CFG_FIFOCFG_ALAP (0x1 << AT91_DMA_CFG_FIFOCFG_OFFSET) /* largest defined AHB burst */
-#define AT91_DMA_CFG_FIFOCFG_ASAP (0x2 << AT91_DMA_CFG_FIFOCFG_OFFSET) /* single AHB access */
-
-
-/* ---------- XDMAC ---------- */
-#define AT91_XDMAC_DT_MEM_IF_MASK (0x1)
-#define AT91_XDMAC_DT_MEM_IF_OFFSET (13)
-#define AT91_XDMAC_DT_MEM_IF(mem_if) (((mem_if) & AT91_XDMAC_DT_MEM_IF_MASK) \
- << AT91_XDMAC_DT_MEM_IF_OFFSET)
-#define AT91_XDMAC_DT_GET_MEM_IF(cfg) (((cfg) >> AT91_XDMAC_DT_MEM_IF_OFFSET) \
- & AT91_XDMAC_DT_MEM_IF_MASK)
-
-#define AT91_XDMAC_DT_PER_IF_MASK (0x1)
-#define AT91_XDMAC_DT_PER_IF_OFFSET (14)
-#define AT91_XDMAC_DT_PER_IF(per_if) (((per_if) & AT91_XDMAC_DT_PER_IF_MASK) \
- << AT91_XDMAC_DT_PER_IF_OFFSET)
-#define AT91_XDMAC_DT_GET_PER_IF(cfg) (((cfg) >> AT91_XDMAC_DT_PER_IF_OFFSET) \
- & AT91_XDMAC_DT_PER_IF_MASK)
-
-#define AT91_XDMAC_DT_PERID_MASK (0x7f)
-#define AT91_XDMAC_DT_PERID_OFFSET (24)
-#define AT91_XDMAC_DT_PERID(perid) (((perid) & AT91_XDMAC_DT_PERID_MASK) \
- << AT91_XDMAC_DT_PERID_OFFSET)
-#define AT91_XDMAC_DT_GET_PERID(cfg) (((cfg) >> AT91_XDMAC_DT_PERID_OFFSET) \
- & AT91_XDMAC_DT_PERID_MASK)
-
-#endif /* __DT_BINDINGS_AT91_DMA_H__ */
diff --git a/include/dt-bindings/dma/bcm6318-dma.h b/include/dt-bindings/dma/bcm6318-dma.h
deleted file mode 100644
index ad7c5ac..0000000
--- a/include/dt-bindings/dma/bcm6318-dma.h
+++ /dev/null
@@ -1,14 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2018 Álvaro Fernández Rojas <noltari@gmail.com>
- *
- * Derived from linux/drivers/net/ethernet/broadcom/bcm63xx_enet.c
- */
-
-#ifndef __DT_BINDINGS_DMA_BCM6318_H
-#define __DT_BINDINGS_DMA_BCM6318_H
-
-#define BCM6318_DMA_ENETSW_RX 0
-#define BCM6318_DMA_ENETSW_TX 1
-
-#endif /* __DT_BINDINGS_DMA_BCM6318_H */
diff --git a/include/dt-bindings/dma/bcm63268-dma.h b/include/dt-bindings/dma/bcm63268-dma.h
deleted file mode 100644
index 7d02711..0000000
--- a/include/dt-bindings/dma/bcm63268-dma.h
+++ /dev/null
@@ -1,14 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2018 Álvaro Fernández Rojas <noltari@gmail.com>
- *
- * Derived from linux/drivers/net/ethernet/broadcom/bcm63xx_enet.c
- */
-
-#ifndef __DT_BINDINGS_DMA_BCM63268_H
-#define __DT_BINDINGS_DMA_BCM63268_H
-
-#define BCM63268_DMA_ENETSW_RX 0
-#define BCM63268_DMA_ENETSW_TX 1
-
-#endif /* __DT_BINDINGS_DMA_BCM63268_H */
diff --git a/include/dt-bindings/dma/bcm6328-dma.h b/include/dt-bindings/dma/bcm6328-dma.h
deleted file mode 100644
index 7494df2..0000000
--- a/include/dt-bindings/dma/bcm6328-dma.h
+++ /dev/null
@@ -1,14 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2018 Álvaro Fernández Rojas <noltari@gmail.com>
- *
- * Derived from linux/drivers/net/ethernet/broadcom/bcm63xx_enet.c
- */
-
-#ifndef __DT_BINDINGS_DMA_BCM6328_H
-#define __DT_BINDINGS_DMA_BCM6328_H
-
-#define BCM6328_DMA_ENETSW_RX 0
-#define BCM6328_DMA_ENETSW_TX 1
-
-#endif /* __DT_BINDINGS_DMA_BCM6328_H */
diff --git a/include/dt-bindings/dma/bcm6338-dma.h b/include/dt-bindings/dma/bcm6338-dma.h
deleted file mode 100644
index f2e0b20..0000000
--- a/include/dt-bindings/dma/bcm6338-dma.h
+++ /dev/null
@@ -1,14 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2018 Álvaro Fernández Rojas <noltari@gmail.com>
- *
- * Derived from linux/drivers/net/ethernet/broadcom/bcm63xx_enet.c
- */
-
-#ifndef __DT_BINDINGS_DMA_BCM6338_H
-#define __DT_BINDINGS_DMA_BCM6338_H
-
-#define BCM6338_DMA_ENET_RX 0
-#define BCM6338_DMA_ENET_TX 1
-
-#endif /* __DT_BINDINGS_DMA_BCM6338_H */
diff --git a/include/dt-bindings/dma/bcm6348-dma.h b/include/dt-bindings/dma/bcm6348-dma.h
deleted file mode 100644
index 36c2ffd..0000000
--- a/include/dt-bindings/dma/bcm6348-dma.h
+++ /dev/null
@@ -1,16 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2018 Álvaro Fernández Rojas <noltari@gmail.com>
- *
- * Derived from linux/drivers/net/ethernet/broadcom/bcm63xx_enet.c
- */
-
-#ifndef __DT_BINDINGS_DMA_BCM6348_H
-#define __DT_BINDINGS_DMA_BCM6348_H
-
-#define BCM6348_DMA_ENET0_RX 0
-#define BCM6348_DMA_ENET0_TX 1
-#define BCM6348_DMA_ENET1_RX 2
-#define BCM6348_DMA_ENET1_TX 3
-
-#endif /* __DT_BINDINGS_DMA_BCM6348_H */
diff --git a/include/dt-bindings/dma/bcm6358-dma.h b/include/dt-bindings/dma/bcm6358-dma.h
deleted file mode 100644
index 3118b9d..0000000
--- a/include/dt-bindings/dma/bcm6358-dma.h
+++ /dev/null
@@ -1,16 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2018 Álvaro Fernández Rojas <noltari@gmail.com>
- *
- * Derived from linux/drivers/net/ethernet/broadcom/bcm63xx_enet.c
- */
-
-#ifndef __DT_BINDINGS_DMA_BCM6358_H
-#define __DT_BINDINGS_DMA_BCM6358_H
-
-#define BCM6358_DMA_ENET0_RX 0
-#define BCM6358_DMA_ENET0_TX 1
-#define BCM6358_DMA_ENET1_RX 2
-#define BCM6358_DMA_ENET1_TX 3
-
-#endif /* __DT_BINDINGS_DMA_BCM6358_H */
diff --git a/include/dt-bindings/dma/bcm6362-dma.h b/include/dt-bindings/dma/bcm6362-dma.h
deleted file mode 100644
index 1e62236..0000000
--- a/include/dt-bindings/dma/bcm6362-dma.h
+++ /dev/null
@@ -1,14 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2018 Álvaro Fernández Rojas <noltari@gmail.com>
- *
- * Derived from linux/drivers/net/ethernet/broadcom/bcm63xx_enet.c
- */
-
-#ifndef __DT_BINDINGS_DMA_BCM6362_H
-#define __DT_BINDINGS_DMA_BCM6362_H
-
-#define BCM6362_DMA_ENETSW_RX 0
-#define BCM6362_DMA_ENETSW_TX 1
-
-#endif /* __DT_BINDINGS_DMA_BCM6362_H */
diff --git a/include/dt-bindings/dma/bcm6368-dma.h b/include/dt-bindings/dma/bcm6368-dma.h
deleted file mode 100644
index 36c6caa..0000000
--- a/include/dt-bindings/dma/bcm6368-dma.h
+++ /dev/null
@@ -1,14 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2018 Álvaro Fernández Rojas <noltari@gmail.com>
- *
- * Derived from linux/drivers/net/ethernet/broadcom/bcm63xx_enet.c
- */
-
-#ifndef __DT_BINDINGS_DMA_BCM6368_H
-#define __DT_BINDINGS_DMA_BCM6368_H
-
-#define BCM6368_DMA_ENETSW_RX 0
-#define BCM6368_DMA_ENETSW_TX 1
-
-#endif /* __DT_BINDINGS_DMA_BCM6368_H */
diff --git a/include/dt-bindings/dma/k3-udma.h b/include/dt-bindings/dma/k3-udma.h
deleted file mode 100644
index 670e123..0000000
--- a/include/dt-bindings/dma/k3-udma.h
+++ /dev/null
@@ -1,31 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com
- */
-
-#ifndef __DT_TI_UDMA_H
-#define __DT_TI_UDMA_H
-
-#define UDMA_TR_MODE 0
-#define UDMA_PKT_MODE 1
-
-#define UDMA_DIR_TX 0
-#define UDMA_DIR_RX 1
-
-#define PSIL_STATIC_TR_NONE 0
-#define PSIL_STATIC_TR_XY 1
-#define PSIL_STATIC_TR_MCAN 2
-
-#define UDMA_PDMA_TR_XY(id) \
- ti,psil-config##id { \
- linux,udma-mode = <UDMA_TR_MODE>; \
- statictr-type = <PSIL_STATIC_TR_XY>; \
- }
-
-#define UDMA_PDMA_PKT_XY(id) \
- ti,psil-config##id { \
- linux,udma-mode = <UDMA_PKT_MODE>; \
- statictr-type = <PSIL_STATIC_TR_XY>; \
- }
-
-#endif /* __DT_TI_UDMA_H */
diff --git a/include/dt-bindings/dma/sun4i-a10.h b/include/dt-bindings/dma/sun4i-a10.h
deleted file mode 100644
index 8caba9e..0000000
--- a/include/dt-bindings/dma/sun4i-a10.h
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
- * Copyright 2014 Maxime Ripard
- *
- * Maxime Ripard <maxime.ripard@free-electrons.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public
- * License along with this file; if not, write to the Free
- * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef __DT_BINDINGS_DMA_SUN4I_A10_H_
-#define __DT_BINDINGS_DMA_SUN4I_A10_H_
-
-#define SUN4I_DMA_NORMAL 0
-#define SUN4I_DMA_DEDICATED 1
-
-#endif /* __DT_BINDINGS_DMA_SUN4I_A10_H_ */
diff --git a/include/dt-bindings/gpio/gpio.h b/include/dt-bindings/gpio/gpio.h
deleted file mode 100644
index 2cc10ae..0000000
--- a/include/dt-bindings/gpio/gpio.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * This header provides constants for most GPIO bindings.
- *
- * Most GPIO bindings include a flags cell as part of the GPIO specifier.
- * In most cases, the format of the flags cell uses the standard values
- * defined in this header.
- */
-
-#ifndef _DT_BINDINGS_GPIO_GPIO_H
-#define _DT_BINDINGS_GPIO_GPIO_H
-
-/* Bit 0 express polarity */
-#define GPIO_ACTIVE_HIGH 0
-#define GPIO_ACTIVE_LOW 1
-
-/* Bit 1 express single-endedness */
-#define GPIO_PUSH_PULL 0
-#define GPIO_SINGLE_ENDED 2
-
-/* Bit 2 express Open drain or open source */
-#define GPIO_LINE_OPEN_SOURCE 0
-#define GPIO_LINE_OPEN_DRAIN 4
-
-/*
- * Open Drain/Collector is the combination of single-ended open drain interface.
- * Open Source/Emitter is the combination of single-ended open source interface.
- */
-#define GPIO_OPEN_DRAIN (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_DRAIN)
-#define GPIO_OPEN_SOURCE (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_SOURCE)
-
-/* Bit 3 express GPIO suspend/resume and reset persistence */
-#define GPIO_PERSISTENT 0
-#define GPIO_TRANSITORY 8
-
-#endif
diff --git a/include/dt-bindings/gpio/meson-axg-gpio.h b/include/dt-bindings/gpio/meson-axg-gpio.h
deleted file mode 100644
index 25bb1ff..0000000
--- a/include/dt-bindings/gpio/meson-axg-gpio.h
+++ /dev/null
@@ -1,116 +0,0 @@
-/*
- * Copyright (c) 2017 Amlogic, Inc. All rights reserved.
- * Author: Xingyu Chen <xingyu.chen@amlogic.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _DT_BINDINGS_MESON_AXG_GPIO_H
-#define _DT_BINDINGS_MESON_AXG_GPIO_H
-
-/* First GPIO chip */
-#define GPIOAO_0 0
-#define GPIOAO_1 1
-#define GPIOAO_2 2
-#define GPIOAO_3 3
-#define GPIOAO_4 4
-#define GPIOAO_5 5
-#define GPIOAO_6 6
-#define GPIOAO_7 7
-#define GPIOAO_8 8
-#define GPIOAO_9 9
-#define GPIOAO_10 10
-#define GPIOAO_11 11
-#define GPIOAO_12 12
-#define GPIOAO_13 13
-#define GPIO_TEST_N 14
-
-/* Second GPIO chip */
-#define GPIOZ_0 0
-#define GPIOZ_1 1
-#define GPIOZ_2 2
-#define GPIOZ_3 3
-#define GPIOZ_4 4
-#define GPIOZ_5 5
-#define GPIOZ_6 6
-#define GPIOZ_7 7
-#define GPIOZ_8 8
-#define GPIOZ_9 9
-#define GPIOZ_10 10
-#define BOOT_0 11
-#define BOOT_1 12
-#define BOOT_2 13
-#define BOOT_3 14
-#define BOOT_4 15
-#define BOOT_5 16
-#define BOOT_6 17
-#define BOOT_7 18
-#define BOOT_8 19
-#define BOOT_9 20
-#define BOOT_10 21
-#define BOOT_11 22
-#define BOOT_12 23
-#define BOOT_13 24
-#define BOOT_14 25
-#define GPIOA_0 26
-#define GPIOA_1 27
-#define GPIOA_2 28
-#define GPIOA_3 29
-#define GPIOA_4 30
-#define GPIOA_5 31
-#define GPIOA_6 32
-#define GPIOA_7 33
-#define GPIOA_8 34
-#define GPIOA_9 35
-#define GPIOA_10 36
-#define GPIOA_11 37
-#define GPIOA_12 38
-#define GPIOA_13 39
-#define GPIOA_14 40
-#define GPIOA_15 41
-#define GPIOA_16 42
-#define GPIOA_17 43
-#define GPIOA_18 44
-#define GPIOA_19 45
-#define GPIOA_20 46
-#define GPIOX_0 47
-#define GPIOX_1 48
-#define GPIOX_2 49
-#define GPIOX_3 50
-#define GPIOX_4 51
-#define GPIOX_5 52
-#define GPIOX_6 53
-#define GPIOX_7 54
-#define GPIOX_8 55
-#define GPIOX_9 56
-#define GPIOX_10 57
-#define GPIOX_11 58
-#define GPIOX_12 59
-#define GPIOX_13 60
-#define GPIOX_14 61
-#define GPIOX_15 62
-#define GPIOX_16 63
-#define GPIOX_17 64
-#define GPIOX_18 65
-#define GPIOX_19 66
-#define GPIOX_20 67
-#define GPIOX_21 68
-#define GPIOX_22 69
-#define GPIOY_0 70
-#define GPIOY_1 71
-#define GPIOY_2 72
-#define GPIOY_3 73
-#define GPIOY_4 74
-#define GPIOY_5 75
-#define GPIOY_6 76
-#define GPIOY_7 77
-#define GPIOY_8 78
-#define GPIOY_9 79
-#define GPIOY_10 80
-#define GPIOY_11 81
-#define GPIOY_12 82
-#define GPIOY_13 83
-#define GPIOY_14 84
-#define GPIOY_15 85
-
-#endif /* _DT_BINDINGS_MESON_AXG_GPIO_H */
diff --git a/include/dt-bindings/gpio/meson-g12a-gpio.h b/include/dt-bindings/gpio/meson-g12a-gpio.h
deleted file mode 100644
index f7bd693..0000000
--- a/include/dt-bindings/gpio/meson-g12a-gpio.h
+++ /dev/null
@@ -1,114 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
-/*
- * Copyright (c) 2018 Amlogic, Inc. All rights reserved.
- * Author: Xingyu Chen <xingyu.chen@amlogic.com>
- */
-
-#ifndef _DT_BINDINGS_MESON_G12A_GPIO_H
-#define _DT_BINDINGS_MESON_G12A_GPIO_H
-
-/* First GPIO chip */
-#define GPIOAO_0 0
-#define GPIOAO_1 1
-#define GPIOAO_2 2
-#define GPIOAO_3 3
-#define GPIOAO_4 4
-#define GPIOAO_5 5
-#define GPIOAO_6 6
-#define GPIOAO_7 7
-#define GPIOAO_8 8
-#define GPIOAO_9 9
-#define GPIOAO_10 10
-#define GPIOAO_11 11
-#define GPIOE_0 12
-#define GPIOE_1 13
-#define GPIOE_2 14
-
-/* Second GPIO chip */
-#define GPIOZ_0 0
-#define GPIOZ_1 1
-#define GPIOZ_2 2
-#define GPIOZ_3 3
-#define GPIOZ_4 4
-#define GPIOZ_5 5
-#define GPIOZ_6 6
-#define GPIOZ_7 7
-#define GPIOZ_8 8
-#define GPIOZ_9 9
-#define GPIOZ_10 10
-#define GPIOZ_11 11
-#define GPIOZ_12 12
-#define GPIOZ_13 13
-#define GPIOZ_14 14
-#define GPIOZ_15 15
-#define GPIOH_0 16
-#define GPIOH_1 17
-#define GPIOH_2 18
-#define GPIOH_3 19
-#define GPIOH_4 20
-#define GPIOH_5 21
-#define GPIOH_6 22
-#define GPIOH_7 23
-#define GPIOH_8 24
-#define BOOT_0 25
-#define BOOT_1 26
-#define BOOT_2 27
-#define BOOT_3 28
-#define BOOT_4 29
-#define BOOT_5 30
-#define BOOT_6 31
-#define BOOT_7 32
-#define BOOT_8 33
-#define BOOT_9 34
-#define BOOT_10 35
-#define BOOT_11 36
-#define BOOT_12 37
-#define BOOT_13 38
-#define BOOT_14 39
-#define BOOT_15 40
-#define GPIOC_0 41
-#define GPIOC_1 42
-#define GPIOC_2 43
-#define GPIOC_3 44
-#define GPIOC_4 45
-#define GPIOC_5 46
-#define GPIOC_6 47
-#define GPIOC_7 48
-#define GPIOA_0 49
-#define GPIOA_1 50
-#define GPIOA_2 51
-#define GPIOA_3 52
-#define GPIOA_4 53
-#define GPIOA_5 54
-#define GPIOA_6 55
-#define GPIOA_7 56
-#define GPIOA_8 57
-#define GPIOA_9 58
-#define GPIOA_10 59
-#define GPIOA_11 60
-#define GPIOA_12 61
-#define GPIOA_13 62
-#define GPIOA_14 63
-#define GPIOA_15 64
-#define GPIOX_0 65
-#define GPIOX_1 66
-#define GPIOX_2 67
-#define GPIOX_3 68
-#define GPIOX_4 69
-#define GPIOX_5 70
-#define GPIOX_6 71
-#define GPIOX_7 72
-#define GPIOX_8 73
-#define GPIOX_9 74
-#define GPIOX_10 75
-#define GPIOX_11 76
-#define GPIOX_12 77
-#define GPIOX_13 78
-#define GPIOX_14 79
-#define GPIOX_15 80
-#define GPIOX_16 81
-#define GPIOX_17 82
-#define GPIOX_18 83
-#define GPIOX_19 84
-
-#endif /* _DT_BINDINGS_MESON_G12A_GPIO_H */
diff --git a/include/dt-bindings/gpio/meson-gxbb-gpio.h b/include/dt-bindings/gpio/meson-gxbb-gpio.h
deleted file mode 100644
index 43a68a1..0000000
--- a/include/dt-bindings/gpio/meson-gxbb-gpio.h
+++ /dev/null
@@ -1,154 +0,0 @@
-/*
- * GPIO definitions for Amlogic Meson GXBB SoCs
- *
- * Copyright (C) 2016 Endless Mobile, Inc.
- * Author: Carlo Caione <carlo@endlessm.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 as published by the Free Software Foundation.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef _DT_BINDINGS_MESON_GXBB_GPIO_H
-#define _DT_BINDINGS_MESON_GXBB_GPIO_H
-
-#define GPIOAO_0 0
-#define GPIOAO_1 1
-#define GPIOAO_2 2
-#define GPIOAO_3 3
-#define GPIOAO_4 4
-#define GPIOAO_5 5
-#define GPIOAO_6 6
-#define GPIOAO_7 7
-#define GPIOAO_8 8
-#define GPIOAO_9 9
-#define GPIOAO_10 10
-#define GPIOAO_11 11
-#define GPIOAO_12 12
-#define GPIOAO_13 13
-#define GPIO_TEST_N 14
-
-#define GPIOZ_0 0
-#define GPIOZ_1 1
-#define GPIOZ_2 2
-#define GPIOZ_3 3
-#define GPIOZ_4 4
-#define GPIOZ_5 5
-#define GPIOZ_6 6
-#define GPIOZ_7 7
-#define GPIOZ_8 8
-#define GPIOZ_9 9
-#define GPIOZ_10 10
-#define GPIOZ_11 11
-#define GPIOZ_12 12
-#define GPIOZ_13 13
-#define GPIOZ_14 14
-#define GPIOZ_15 15
-#define GPIOH_0 16
-#define GPIOH_1 17
-#define GPIOH_2 18
-#define GPIOH_3 19
-#define BOOT_0 20
-#define BOOT_1 21
-#define BOOT_2 22
-#define BOOT_3 23
-#define BOOT_4 24
-#define BOOT_5 25
-#define BOOT_6 26
-#define BOOT_7 27
-#define BOOT_8 28
-#define BOOT_9 29
-#define BOOT_10 30
-#define BOOT_11 31
-#define BOOT_12 32
-#define BOOT_13 33
-#define BOOT_14 34
-#define BOOT_15 35
-#define BOOT_16 36
-#define BOOT_17 37
-#define CARD_0 38
-#define CARD_1 39
-#define CARD_2 40
-#define CARD_3 41
-#define CARD_4 42
-#define CARD_5 43
-#define CARD_6 44
-#define GPIODV_0 45
-#define GPIODV_1 46
-#define GPIODV_2 47
-#define GPIODV_3 48
-#define GPIODV_4 49
-#define GPIODV_5 50
-#define GPIODV_6 51
-#define GPIODV_7 52
-#define GPIODV_8 53
-#define GPIODV_9 54
-#define GPIODV_10 55
-#define GPIODV_11 56
-#define GPIODV_12 57
-#define GPIODV_13 58
-#define GPIODV_14 59
-#define GPIODV_15 60
-#define GPIODV_16 61
-#define GPIODV_17 62
-#define GPIODV_18 63
-#define GPIODV_19 64
-#define GPIODV_20 65
-#define GPIODV_21 66
-#define GPIODV_22 67
-#define GPIODV_23 68
-#define GPIODV_24 69
-#define GPIODV_25 70
-#define GPIODV_26 71
-#define GPIODV_27 72
-#define GPIODV_28 73
-#define GPIODV_29 74
-#define GPIOY_0 75
-#define GPIOY_1 76
-#define GPIOY_2 77
-#define GPIOY_3 78
-#define GPIOY_4 79
-#define GPIOY_5 80
-#define GPIOY_6 81
-#define GPIOY_7 82
-#define GPIOY_8 83
-#define GPIOY_9 84
-#define GPIOY_10 85
-#define GPIOY_11 86
-#define GPIOY_12 87
-#define GPIOY_13 88
-#define GPIOY_14 89
-#define GPIOY_15 90
-#define GPIOY_16 91
-#define GPIOX_0 92
-#define GPIOX_1 93
-#define GPIOX_2 94
-#define GPIOX_3 95
-#define GPIOX_4 96
-#define GPIOX_5 97
-#define GPIOX_6 98
-#define GPIOX_7 99
-#define GPIOX_8 100
-#define GPIOX_9 101
-#define GPIOX_10 102
-#define GPIOX_11 103
-#define GPIOX_12 104
-#define GPIOX_13 105
-#define GPIOX_14 106
-#define GPIOX_15 107
-#define GPIOX_16 108
-#define GPIOX_17 109
-#define GPIOX_18 110
-#define GPIOX_19 111
-#define GPIOX_20 112
-#define GPIOX_21 113
-#define GPIOX_22 114
-#define GPIOCLK_0 115
-#define GPIOCLK_1 116
-#define GPIOCLK_2 117
-#define GPIOCLK_3 118
-
-#endif
diff --git a/include/dt-bindings/gpio/meson-gxl-gpio.h b/include/dt-bindings/gpio/meson-gxl-gpio.h
deleted file mode 100644
index 01f2a2a..0000000
--- a/include/dt-bindings/gpio/meson-gxl-gpio.h
+++ /dev/null
@@ -1,131 +0,0 @@
-/*
- * GPIO definitions for Amlogic Meson GXL SoCs
- *
- * Copyright (C) 2016 Endless Mobile, Inc.
- * Author: Carlo Caione <carlo@endlessm.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 as published by the Free Software Foundation.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef _DT_BINDINGS_MESON_GXL_GPIO_H
-#define _DT_BINDINGS_MESON_GXL_GPIO_H
-
-#define GPIOAO_0 0
-#define GPIOAO_1 1
-#define GPIOAO_2 2
-#define GPIOAO_3 3
-#define GPIOAO_4 4
-#define GPIOAO_5 5
-#define GPIOAO_6 6
-#define GPIOAO_7 7
-#define GPIOAO_8 8
-#define GPIOAO_9 9
-#define GPIO_TEST_N 10
-
-#define GPIOZ_0 0
-#define GPIOZ_1 1
-#define GPIOZ_2 2
-#define GPIOZ_3 3
-#define GPIOZ_4 4
-#define GPIOZ_5 5
-#define GPIOZ_6 6
-#define GPIOZ_7 7
-#define GPIOZ_8 8
-#define GPIOZ_9 9
-#define GPIOZ_10 10
-#define GPIOZ_11 11
-#define GPIOZ_12 12
-#define GPIOZ_13 13
-#define GPIOZ_14 14
-#define GPIOZ_15 15
-#define GPIOH_0 16
-#define GPIOH_1 17
-#define GPIOH_2 18
-#define GPIOH_3 19
-#define GPIOH_4 20
-#define GPIOH_5 21
-#define GPIOH_6 22
-#define GPIOH_7 23
-#define GPIOH_8 24
-#define GPIOH_9 25
-#define BOOT_0 26
-#define BOOT_1 27
-#define BOOT_2 28
-#define BOOT_3 29
-#define BOOT_4 30
-#define BOOT_5 31
-#define BOOT_6 32
-#define BOOT_7 33
-#define BOOT_8 34
-#define BOOT_9 35
-#define BOOT_10 36
-#define BOOT_11 37
-#define BOOT_12 38
-#define BOOT_13 39
-#define BOOT_14 40
-#define BOOT_15 41
-#define CARD_0 42
-#define CARD_1 43
-#define CARD_2 44
-#define CARD_3 45
-#define CARD_4 46
-#define CARD_5 47
-#define CARD_6 48
-#define GPIODV_0 49
-#define GPIODV_1 50
-#define GPIODV_2 51
-#define GPIODV_3 52
-#define GPIODV_4 53
-#define GPIODV_5 54
-#define GPIODV_6 55
-#define GPIODV_7 56
-#define GPIODV_8 57
-#define GPIODV_9 58
-#define GPIODV_10 59
-#define GPIODV_11 60
-#define GPIODV_12 61
-#define GPIODV_13 62
-#define GPIODV_14 63
-#define GPIODV_15 64
-#define GPIODV_16 65
-#define GPIODV_17 66
-#define GPIODV_18 67
-#define GPIODV_19 68
-#define GPIODV_20 69
-#define GPIODV_21 70
-#define GPIODV_22 71
-#define GPIODV_23 72
-#define GPIODV_24 73
-#define GPIODV_25 74
-#define GPIODV_26 75
-#define GPIODV_27 76
-#define GPIODV_28 77
-#define GPIODV_29 78
-#define GPIOX_0 79
-#define GPIOX_1 80
-#define GPIOX_2 81
-#define GPIOX_3 82
-#define GPIOX_4 83
-#define GPIOX_5 84
-#define GPIOX_6 85
-#define GPIOX_7 86
-#define GPIOX_8 87
-#define GPIOX_9 88
-#define GPIOX_10 89
-#define GPIOX_11 90
-#define GPIOX_12 91
-#define GPIOX_13 92
-#define GPIOX_14 93
-#define GPIOX_15 94
-#define GPIOX_16 95
-#define GPIOX_17 96
-#define GPIOX_18 97
-#define GPIOCLK_0 98
-#define GPIOCLK_1 99
-
-#endif
diff --git a/include/dt-bindings/gpio/tegra-gpio.h b/include/dt-bindings/gpio/tegra-gpio.h
deleted file mode 100644
index a1c09e8..0000000
--- a/include/dt-bindings/gpio/tegra-gpio.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * This header provides constants for binding nvidia,tegra*-gpio.
- *
- * The first cell in Tegra's GPIO specifier is the GPIO ID. The macros below
- * provide names for this.
- *
- * The second cell contains standard flag values specified in gpio.h.
- */
-
-#ifndef _DT_BINDINGS_GPIO_TEGRA_GPIO_H
-#define _DT_BINDINGS_GPIO_TEGRA_GPIO_H
-
-#include <dt-bindings/gpio/gpio.h>
-
-#define TEGRA_GPIO_PORT_A 0
-#define TEGRA_GPIO_PORT_B 1
-#define TEGRA_GPIO_PORT_C 2
-#define TEGRA_GPIO_PORT_D 3
-#define TEGRA_GPIO_PORT_E 4
-#define TEGRA_GPIO_PORT_F 5
-#define TEGRA_GPIO_PORT_G 6
-#define TEGRA_GPIO_PORT_H 7
-#define TEGRA_GPIO_PORT_I 8
-#define TEGRA_GPIO_PORT_J 9
-#define TEGRA_GPIO_PORT_K 10
-#define TEGRA_GPIO_PORT_L 11
-#define TEGRA_GPIO_PORT_M 12
-#define TEGRA_GPIO_PORT_N 13
-#define TEGRA_GPIO_PORT_O 14
-#define TEGRA_GPIO_PORT_P 15
-#define TEGRA_GPIO_PORT_Q 16
-#define TEGRA_GPIO_PORT_R 17
-#define TEGRA_GPIO_PORT_S 18
-#define TEGRA_GPIO_PORT_T 19
-#define TEGRA_GPIO_PORT_U 20
-#define TEGRA_GPIO_PORT_V 21
-#define TEGRA_GPIO_PORT_W 22
-#define TEGRA_GPIO_PORT_X 23
-#define TEGRA_GPIO_PORT_Y 24
-#define TEGRA_GPIO_PORT_Z 25
-#define TEGRA_GPIO_PORT_AA 26
-#define TEGRA_GPIO_PORT_BB 27
-#define TEGRA_GPIO_PORT_CC 28
-#define TEGRA_GPIO_PORT_DD 29
-#define TEGRA_GPIO_PORT_EE 30
-#define TEGRA_GPIO_PORT_FF 31
-
-#define TEGRA_GPIO(port, offset) \
- ((TEGRA_GPIO_PORT_##port * 8) + offset)
-
-#endif
diff --git a/include/dt-bindings/gpio/tegra186-gpio.h b/include/dt-bindings/gpio/tegra186-gpio.h
deleted file mode 100644
index 83a19dc..0000000
--- a/include/dt-bindings/gpio/tegra186-gpio.h
+++ /dev/null
@@ -1,59 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (c) 2016, NVIDIA CORPORATION.
- *
- * This header provides constants for binding nvidia,tegra186-gpio*.
- *
- * The first cell in Tegra's GPIO specifier is the GPIO ID. The macros below
- * provide names for this.
- *
- * The second cell contains standard flag values specified in gpio.h.
- */
-
-#ifndef _DT_BINDINGS_GPIO_TEGRA186_GPIO_H
-#define _DT_BINDINGS_GPIO_TEGRA186_GPIO_H
-
-#include <dt-bindings/gpio/gpio.h>
-
-/* GPIOs implemented by main GPIO controller */
-#define TEGRA_MAIN_GPIO_PORT_A 0
-#define TEGRA_MAIN_GPIO_PORT_B 1
-#define TEGRA_MAIN_GPIO_PORT_C 2
-#define TEGRA_MAIN_GPIO_PORT_D 3
-#define TEGRA_MAIN_GPIO_PORT_E 4
-#define TEGRA_MAIN_GPIO_PORT_F 5
-#define TEGRA_MAIN_GPIO_PORT_G 6
-#define TEGRA_MAIN_GPIO_PORT_H 7
-#define TEGRA_MAIN_GPIO_PORT_I 8
-#define TEGRA_MAIN_GPIO_PORT_J 9
-#define TEGRA_MAIN_GPIO_PORT_K 10
-#define TEGRA_MAIN_GPIO_PORT_L 11
-#define TEGRA_MAIN_GPIO_PORT_M 12
-#define TEGRA_MAIN_GPIO_PORT_N 13
-#define TEGRA_MAIN_GPIO_PORT_O 14
-#define TEGRA_MAIN_GPIO_PORT_P 15
-#define TEGRA_MAIN_GPIO_PORT_Q 16
-#define TEGRA_MAIN_GPIO_PORT_R 17
-#define TEGRA_MAIN_GPIO_PORT_T 18
-#define TEGRA_MAIN_GPIO_PORT_X 19
-#define TEGRA_MAIN_GPIO_PORT_Y 20
-#define TEGRA_MAIN_GPIO_PORT_BB 21
-#define TEGRA_MAIN_GPIO_PORT_CC 22
-
-#define TEGRA_MAIN_GPIO(port, offset) \
- ((TEGRA_MAIN_GPIO_PORT_##port * 8) + offset)
-
-/* GPIOs implemented by AON GPIO controller */
-#define TEGRA_AON_GPIO_PORT_S 0
-#define TEGRA_AON_GPIO_PORT_U 1
-#define TEGRA_AON_GPIO_PORT_V 2
-#define TEGRA_AON_GPIO_PORT_W 3
-#define TEGRA_AON_GPIO_PORT_Z 4
-#define TEGRA_AON_GPIO_PORT_AA 5
-#define TEGRA_AON_GPIO_PORT_EE 6
-#define TEGRA_AON_GPIO_PORT_FF 7
-
-#define TEGRA_AON_GPIO(port, offset) \
- ((TEGRA_AON_GPIO_PORT_##port * 8) + offset)
-
-#endif
diff --git a/include/dt-bindings/gpio/uniphier-gpio.h b/include/dt-bindings/gpio/uniphier-gpio.h
deleted file mode 100644
index 9f0ad17..0000000
--- a/include/dt-bindings/gpio/uniphier-gpio.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- * Copyright (C) 2017 Socionext Inc.
- * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
- */
-
-#ifndef _DT_BINDINGS_GPIO_UNIPHIER_H
-#define _DT_BINDINGS_GPIO_UNIPHIER_H
-
-#define UNIPHIER_GPIO_LINES_PER_BANK 8
-
-#define UNIPHIER_GPIO_IRQ_OFFSET ((UNIPHIER_GPIO_LINES_PER_BANK) * 15)
-
-#define UNIPHIER_GPIO_PORT(bank, line) \
- ((UNIPHIER_GPIO_LINES_PER_BANK) * (bank) + (line))
-
-#define UNIPHIER_GPIO_IRQ(n) ((UNIPHIER_GPIO_IRQ_OFFSET) + (n))
-
-#endif /* _DT_BINDINGS_GPIO_UNIPHIER_H */
diff --git a/include/dt-bindings/gpio/x86-gpio.h b/include/dt-bindings/gpio/x86-gpio.h
deleted file mode 100644
index 3998a8e..0000000
--- a/include/dt-bindings/gpio/x86-gpio.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * This header provides constants for binding intel,x86-pinctrl.
- */
-
-#ifndef _DT_BINDINGS_GPIO_X86_GPIO_H
-#define _DT_BINDINGS_GPIO_X86_GPIO_H
-
-#include <dt-bindings/gpio/gpio.h>
-
-#define GPIO_MODE_NATIVE 0
-#define GPIO_MODE_GPIO 1
-
-#define GPIO_MODE_FUNC0 0
-#define GPIO_MODE_FUNC1 1
-#define GPIO_MODE_FUNC2 2
-#define GPIO_MODE_FUNC3 3
-#define GPIO_MODE_FUNC4 4
-#define GPIO_MODE_FUNC5 5
-#define GPIO_MODE_FUNC6 6
-
-#define PIN_INPUT 0
-#define PIN_OUTPUT 1
-
-#define PIN_INPUT_NOPULL 0
-#define PIN_INPUT_PULLUP 1
-#define PIN_INPUT_PULLDOWN 2
-
-#define PULL_STR_2K 0
-#define PULL_STR_20K 2
-
-#define ROUTE_SCI 0
-#define ROUTE_SMI 1
-
-#define OWNER_ACPI 0
-#define OWNER_GPIO 1
-
-#define PIRQ_APIC_MASK 0
-#define PIRQ_APIC_ROUTE 1
-
-#define TRIGGER_EDGE 0
-#define TRIGGER_LEVEL 1
-
-#endif
diff --git a/include/dt-bindings/input/input.h b/include/dt-bindings/input/input.h
deleted file mode 100644
index a214133..0000000
--- a/include/dt-bindings/input/input.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/*
- * This header provides constants for most input bindings.
- *
- * Most input bindings include key code, matrix key code format.
- * In most cases, key code and matrix key code format uses
- * the standard values/macro defined in this header.
- */
-
-#ifndef _DT_BINDINGS_INPUT_INPUT_H
-#define _DT_BINDINGS_INPUT_INPUT_H
-
-#include "linux-event-codes.h"
-
-#define MATRIX_KEY(row, col, code) \
- ((((row) & 0xFF) << 24) | (((col) & 0xFF) << 16) | ((code) & 0xFFFF))
-
-#endif /* _DT_BINDINGS_INPUT_INPUT_H */
diff --git a/include/dt-bindings/input/linux-event-codes.h b/include/dt-bindings/input/linux-event-codes.h
deleted file mode 100644
index 87cf351..0000000
--- a/include/dt-bindings/input/linux-event-codes.h
+++ /dev/null
@@ -1,805 +0,0 @@
-/*
- * Input event codes
- *
- * *** IMPORTANT ***
- * This file is not only included from C-code but also from devicetree source
- * files. As such this file MUST only contain comments and defines.
- *
- * Copyright (c) 1999-2002 Vojtech Pavlik
- * Copyright (c) 2015 Hans de Goede <hdegoede@redhat.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published by
- * the Free Software Foundation.
- */
-#ifndef _UAPI_INPUT_EVENT_CODES_H
-#define _UAPI_INPUT_EVENT_CODES_H
-
-/*
- * Device properties and quirks
- */
-
-#define INPUT_PROP_POINTER 0x00 /* needs a pointer */
-#define INPUT_PROP_DIRECT 0x01 /* direct input devices */
-#define INPUT_PROP_BUTTONPAD 0x02 /* has button(s) under pad */
-#define INPUT_PROP_SEMI_MT 0x03 /* touch rectangle only */
-#define INPUT_PROP_TOPBUTTONPAD 0x04 /* softbuttons at top of pad */
-#define INPUT_PROP_POINTING_STICK 0x05 /* is a pointing stick */
-#define INPUT_PROP_ACCELEROMETER 0x06 /* has accelerometer */
-
-#define INPUT_PROP_MAX 0x1f
-#define INPUT_PROP_CNT (INPUT_PROP_MAX + 1)
-
-/*
- * Event types
- */
-
-#define EV_SYN 0x00
-#define EV_KEY 0x01
-#define EV_REL 0x02
-#define EV_ABS 0x03
-#define EV_MSC 0x04
-#define EV_SW 0x05
-#define EV_LED 0x11
-#define EV_SND 0x12
-#define EV_REP 0x14
-#define EV_FF 0x15
-#define EV_PWR 0x16
-#define EV_FF_STATUS 0x17
-#define EV_MAX 0x1f
-#define EV_CNT (EV_MAX+1)
-
-/*
- * Synchronization events.
- */
-
-#define SYN_REPORT 0
-#define SYN_CONFIG 1
-#define SYN_MT_REPORT 2
-#define SYN_DROPPED 3
-#define SYN_MAX 0xf
-#define SYN_CNT (SYN_MAX+1)
-
-/*
- * Keys and buttons
- *
- * Most of the keys/buttons are modeled after USB HUT 1.12
- * (see http://www.usb.org/developers/hidpage).
- * Abbreviations in the comments:
- * AC - Application Control
- * AL - Application Launch Button
- * SC - System Control
- */
-
-#define KEY_RESERVED 0
-#define KEY_ESC 1
-#define KEY_1 2
-#define KEY_2 3
-#define KEY_3 4
-#define KEY_4 5
-#define KEY_5 6
-#define KEY_6 7
-#define KEY_7 8
-#define KEY_8 9
-#define KEY_9 10
-#define KEY_0 11
-#define KEY_MINUS 12
-#define KEY_EQUAL 13
-#define KEY_BACKSPACE 14
-#define KEY_TAB 15
-#define KEY_Q 16
-#define KEY_W 17
-#define KEY_E 18
-#define KEY_R 19
-#define KEY_T 20
-#define KEY_Y 21
-#define KEY_U 22
-#define KEY_I 23
-#define KEY_O 24
-#define KEY_P 25
-#define KEY_LEFTBRACE 26
-#define KEY_RIGHTBRACE 27
-#define KEY_ENTER 28
-#define KEY_LEFTCTRL 29
-#define KEY_A 30
-#define KEY_S 31
-#define KEY_D 32
-#define KEY_F 33
-#define KEY_G 34
-#define KEY_H 35
-#define KEY_J 36
-#define KEY_K 37
-#define KEY_L 38
-#define KEY_SEMICOLON 39
-#define KEY_APOSTROPHE 40
-#define KEY_GRAVE 41
-#define KEY_LEFTSHIFT 42
-#define KEY_BACKSLASH 43
-#define KEY_Z 44
-#define KEY_X 45
-#define KEY_C 46
-#define KEY_V 47
-#define KEY_B 48
-#define KEY_N 49
-#define KEY_M 50
-#define KEY_COMMA 51
-#define KEY_DOT 52
-#define KEY_SLASH 53
-#define KEY_RIGHTSHIFT 54
-#define KEY_KPASTERISK 55
-#define KEY_LEFTALT 56
-#define KEY_SPACE 57
-#define KEY_CAPSLOCK 58
-#define KEY_F1 59
-#define KEY_F2 60
-#define KEY_F3 61
-#define KEY_F4 62
-#define KEY_F5 63
-#define KEY_F6 64
-#define KEY_F7 65
-#define KEY_F8 66
-#define KEY_F9 67
-#define KEY_F10 68
-#define KEY_NUMLOCK 69
-#define KEY_SCROLLLOCK 70
-#define KEY_KP7 71
-#define KEY_KP8 72
-#define KEY_KP9 73
-#define KEY_KPMINUS 74
-#define KEY_KP4 75
-#define KEY_KP5 76
-#define KEY_KP6 77
-#define KEY_KPPLUS 78
-#define KEY_KP1 79
-#define KEY_KP2 80
-#define KEY_KP3 81
-#define KEY_KP0 82
-#define KEY_KPDOT 83
-
-#define KEY_ZENKAKUHANKAKU 85
-#define KEY_102ND 86
-#define KEY_F11 87
-#define KEY_F12 88
-#define KEY_RO 89
-#define KEY_KATAKANA 90
-#define KEY_HIRAGANA 91
-#define KEY_HENKAN 92
-#define KEY_KATAKANAHIRAGANA 93
-#define KEY_MUHENKAN 94
-#define KEY_KPJPCOMMA 95
-#define KEY_KPENTER 96
-#define KEY_RIGHTCTRL 97
-#define KEY_KPSLASH 98
-#define KEY_SYSRQ 99
-#define KEY_RIGHTALT 100
-#define KEY_LINEFEED 101
-#define KEY_HOME 102
-#define KEY_UP 103
-#define KEY_PAGEUP 104
-#define KEY_LEFT 105
-#define KEY_RIGHT 106
-#define KEY_END 107
-#define KEY_DOWN 108
-#define KEY_PAGEDOWN 109
-#define KEY_INSERT 110
-#define KEY_DELETE 111
-#define KEY_MACRO 112
-#define KEY_MUTE 113
-#define KEY_VOLUMEDOWN 114
-#define KEY_VOLUMEUP 115
-#define KEY_POWER 116 /* SC System Power Down */
-#define KEY_KPEQUAL 117
-#define KEY_KPPLUSMINUS 118
-#define KEY_PAUSE 119
-#define KEY_SCALE 120 /* AL Compiz Scale (Expose) */
-
-#define KEY_KPCOMMA 121
-#define KEY_HANGEUL 122
-#define KEY_HANGUEL KEY_HANGEUL
-#define KEY_HANJA 123
-#define KEY_YEN 124
-#define KEY_LEFTMETA 125
-#define KEY_RIGHTMETA 126
-#define KEY_COMPOSE 127
-
-#define KEY_STOP 128 /* AC Stop */
-#define KEY_AGAIN 129
-#define KEY_PROPS 130 /* AC Properties */
-#define KEY_UNDO 131 /* AC Undo */
-#define KEY_FRONT 132
-#define KEY_COPY 133 /* AC Copy */
-#define KEY_OPEN 134 /* AC Open */
-#define KEY_PASTE 135 /* AC Paste */
-#define KEY_FIND 136 /* AC Search */
-#define KEY_CUT 137 /* AC Cut */
-#define KEY_HELP 138 /* AL Integrated Help Center */
-#define KEY_MENU 139 /* Menu (show menu) */
-#define KEY_CALC 140 /* AL Calculator */
-#define KEY_SETUP 141
-#define KEY_SLEEP 142 /* SC System Sleep */
-#define KEY_WAKEUP 143 /* System Wake Up */
-#define KEY_FILE 144 /* AL Local Machine Browser */
-#define KEY_SENDFILE 145
-#define KEY_DELETEFILE 146
-#define KEY_XFER 147
-#define KEY_PROG1 148
-#define KEY_PROG2 149
-#define KEY_WWW 150 /* AL Internet Browser */
-#define KEY_MSDOS 151
-#define KEY_COFFEE 152 /* AL Terminal Lock/Screensaver */
-#define KEY_SCREENLOCK KEY_COFFEE
-#define KEY_ROTATE_DISPLAY 153 /* Display orientation for e.g. tablets */
-#define KEY_DIRECTION KEY_ROTATE_DISPLAY
-#define KEY_CYCLEWINDOWS 154
-#define KEY_MAIL 155
-#define KEY_BOOKMARKS 156 /* AC Bookmarks */
-#define KEY_COMPUTER 157
-#define KEY_BACK 158 /* AC Back */
-#define KEY_FORWARD 159 /* AC Forward */
-#define KEY_CLOSECD 160
-#define KEY_EJECTCD 161
-#define KEY_EJECTCLOSECD 162
-#define KEY_NEXTSONG 163
-#define KEY_PLAYPAUSE 164
-#define KEY_PREVIOUSSONG 165
-#define KEY_STOPCD 166
-#define KEY_RECORD 167
-#define KEY_REWIND 168
-#define KEY_PHONE 169 /* Media Select Telephone */
-#define KEY_ISO 170
-#define KEY_CONFIG 171 /* AL Consumer Control Configuration */
-#define KEY_HOMEPAGE 172 /* AC Home */
-#define KEY_REFRESH 173 /* AC Refresh */
-#define KEY_EXIT 174 /* AC Exit */
-#define KEY_MOVE 175
-#define KEY_EDIT 176
-#define KEY_SCROLLUP 177
-#define KEY_SCROLLDOWN 178
-#define KEY_KPLEFTPAREN 179
-#define KEY_KPRIGHTPAREN 180
-#define KEY_NEW 181 /* AC New */
-#define KEY_REDO 182 /* AC Redo/Repeat */
-
-#define KEY_F13 183
-#define KEY_F14 184
-#define KEY_F15 185
-#define KEY_F16 186
-#define KEY_F17 187
-#define KEY_F18 188
-#define KEY_F19 189
-#define KEY_F20 190
-#define KEY_F21 191
-#define KEY_F22 192
-#define KEY_F23 193
-#define KEY_F24 194
-
-#define KEY_PLAYCD 200
-#define KEY_PAUSECD 201
-#define KEY_PROG3 202
-#define KEY_PROG4 203
-#define KEY_DASHBOARD 204 /* AL Dashboard */
-#define KEY_SUSPEND 205
-#define KEY_CLOSE 206 /* AC Close */
-#define KEY_PLAY 207
-#define KEY_FASTFORWARD 208
-#define KEY_BASSBOOST 209
-#define KEY_PRINT 210 /* AC Print */
-#define KEY_HP 211
-#define KEY_CAMERA 212
-#define KEY_SOUND 213
-#define KEY_QUESTION 214
-#define KEY_EMAIL 215
-#define KEY_CHAT 216
-#define KEY_SEARCH 217
-#define KEY_CONNECT 218
-#define KEY_FINANCE 219 /* AL Checkbook/Finance */
-#define KEY_SPORT 220
-#define KEY_SHOP 221
-#define KEY_ALTERASE 222
-#define KEY_CANCEL 223 /* AC Cancel */
-#define KEY_BRIGHTNESSDOWN 224
-#define KEY_BRIGHTNESSUP 225
-#define KEY_MEDIA 226
-
-#define KEY_SWITCHVIDEOMODE 227 /* Cycle between available video
- outputs (Monitor/LCD/TV-out/etc) */
-#define KEY_KBDILLUMTOGGLE 228
-#define KEY_KBDILLUMDOWN 229
-#define KEY_KBDILLUMUP 230
-
-#define KEY_SEND 231 /* AC Send */
-#define KEY_REPLY 232 /* AC Reply */
-#define KEY_FORWARDMAIL 233 /* AC Forward Msg */
-#define KEY_SAVE 234 /* AC Save */
-#define KEY_DOCUMENTS 235
-
-#define KEY_BATTERY 236
-
-#define KEY_BLUETOOTH 237
-#define KEY_WLAN 238
-#define KEY_UWB 239
-
-#define KEY_UNKNOWN 240
-
-#define KEY_VIDEO_NEXT 241 /* drive next video source */
-#define KEY_VIDEO_PREV 242 /* drive previous video source */
-#define KEY_BRIGHTNESS_CYCLE 243 /* brightness up, after max is min */
-#define KEY_BRIGHTNESS_AUTO 244 /* Set Auto Brightness: manual
- brightness control is off,
- rely on ambient */
-#define KEY_BRIGHTNESS_ZERO KEY_BRIGHTNESS_AUTO
-#define KEY_DISPLAY_OFF 245 /* display device to off state */
-
-#define KEY_WWAN 246 /* Wireless WAN (LTE, UMTS, GSM, etc.) */
-#define KEY_WIMAX KEY_WWAN
-#define KEY_RFKILL 247 /* Key that controls all radios */
-
-#define KEY_MICMUTE 248 /* Mute / unmute the microphone */
-
-/* Code 255 is reserved for special needs of AT keyboard driver */
-
-#define BTN_MISC 0x100
-#define BTN_0 0x100
-#define BTN_1 0x101
-#define BTN_2 0x102
-#define BTN_3 0x103
-#define BTN_4 0x104
-#define BTN_5 0x105
-#define BTN_6 0x106
-#define BTN_7 0x107
-#define BTN_8 0x108
-#define BTN_9 0x109
-
-#define BTN_MOUSE 0x110
-#define BTN_LEFT 0x110
-#define BTN_RIGHT 0x111
-#define BTN_MIDDLE 0x112
-#define BTN_SIDE 0x113
-#define BTN_EXTRA 0x114
-#define BTN_FORWARD 0x115
-#define BTN_BACK 0x116
-#define BTN_TASK 0x117
-
-#define BTN_JOYSTICK 0x120
-#define BTN_TRIGGER 0x120
-#define BTN_THUMB 0x121
-#define BTN_THUMB2 0x122
-#define BTN_TOP 0x123
-#define BTN_TOP2 0x124
-#define BTN_PINKIE 0x125
-#define BTN_BASE 0x126
-#define BTN_BASE2 0x127
-#define BTN_BASE3 0x128
-#define BTN_BASE4 0x129
-#define BTN_BASE5 0x12a
-#define BTN_BASE6 0x12b
-#define BTN_DEAD 0x12f
-
-#define BTN_GAMEPAD 0x130
-#define BTN_SOUTH 0x130
-#define BTN_A BTN_SOUTH
-#define BTN_EAST 0x131
-#define BTN_B BTN_EAST
-#define BTN_C 0x132
-#define BTN_NORTH 0x133
-#define BTN_X BTN_NORTH
-#define BTN_WEST 0x134
-#define BTN_Y BTN_WEST
-#define BTN_Z 0x135
-#define BTN_TL 0x136
-#define BTN_TR 0x137
-#define BTN_TL2 0x138
-#define BTN_TR2 0x139
-#define BTN_SELECT 0x13a
-#define BTN_START 0x13b
-#define BTN_MODE 0x13c
-#define BTN_THUMBL 0x13d
-#define BTN_THUMBR 0x13e
-
-#define BTN_DIGI 0x140
-#define BTN_TOOL_PEN 0x140
-#define BTN_TOOL_RUBBER 0x141
-#define BTN_TOOL_BRUSH 0x142
-#define BTN_TOOL_PENCIL 0x143
-#define BTN_TOOL_AIRBRUSH 0x144
-#define BTN_TOOL_FINGER 0x145
-#define BTN_TOOL_MOUSE 0x146
-#define BTN_TOOL_LENS 0x147
-#define BTN_TOOL_QUINTTAP 0x148 /* Five fingers on trackpad */
-#define BTN_TOUCH 0x14a
-#define BTN_STYLUS 0x14b
-#define BTN_STYLUS2 0x14c
-#define BTN_TOOL_DOUBLETAP 0x14d
-#define BTN_TOOL_TRIPLETAP 0x14e
-#define BTN_TOOL_QUADTAP 0x14f /* Four fingers on trackpad */
-
-#define BTN_WHEEL 0x150
-#define BTN_GEAR_DOWN 0x150
-#define BTN_GEAR_UP 0x151
-
-#define KEY_OK 0x160
-#define KEY_SELECT 0x161
-#define KEY_GOTO 0x162
-#define KEY_CLEAR 0x163
-#define KEY_POWER2 0x164
-#define KEY_OPTION 0x165
-#define KEY_INFO 0x166 /* AL OEM Features/Tips/Tutorial */
-#define KEY_TIME 0x167
-#define KEY_VENDOR 0x168
-#define KEY_ARCHIVE 0x169
-#define KEY_PROGRAM 0x16a /* Media Select Program Guide */
-#define KEY_CHANNEL 0x16b
-#define KEY_FAVORITES 0x16c
-#define KEY_EPG 0x16d
-#define KEY_PVR 0x16e /* Media Select Home */
-#define KEY_MHP 0x16f
-#define KEY_LANGUAGE 0x170
-#define KEY_TITLE 0x171
-#define KEY_SUBTITLE 0x172
-#define KEY_ANGLE 0x173
-#define KEY_ZOOM 0x174
-#define KEY_MODE 0x175
-#define KEY_KEYBOARD 0x176
-#define KEY_SCREEN 0x177
-#define KEY_PC 0x178 /* Media Select Computer */
-#define KEY_TV 0x179 /* Media Select TV */
-#define KEY_TV2 0x17a /* Media Select Cable */
-#define KEY_VCR 0x17b /* Media Select VCR */
-#define KEY_VCR2 0x17c /* VCR Plus */
-#define KEY_SAT 0x17d /* Media Select Satellite */
-#define KEY_SAT2 0x17e
-#define KEY_CD 0x17f /* Media Select CD */
-#define KEY_TAPE 0x180 /* Media Select Tape */
-#define KEY_RADIO 0x181
-#define KEY_TUNER 0x182 /* Media Select Tuner */
-#define KEY_PLAYER 0x183
-#define KEY_TEXT 0x184
-#define KEY_DVD 0x185 /* Media Select DVD */
-#define KEY_AUX 0x186
-#define KEY_MP3 0x187
-#define KEY_AUDIO 0x188 /* AL Audio Browser */
-#define KEY_VIDEO 0x189 /* AL Movie Browser */
-#define KEY_DIRECTORY 0x18a
-#define KEY_LIST 0x18b
-#define KEY_MEMO 0x18c /* Media Select Messages */
-#define KEY_CALENDAR 0x18d
-#define KEY_RED 0x18e
-#define KEY_GREEN 0x18f
-#define KEY_YELLOW 0x190
-#define KEY_BLUE 0x191
-#define KEY_CHANNELUP 0x192 /* Channel Increment */
-#define KEY_CHANNELDOWN 0x193 /* Channel Decrement */
-#define KEY_FIRST 0x194
-#define KEY_LAST 0x195 /* Recall Last */
-#define KEY_AB 0x196
-#define KEY_NEXT 0x197
-#define KEY_RESTART 0x198
-#define KEY_SLOW 0x199
-#define KEY_SHUFFLE 0x19a
-#define KEY_BREAK 0x19b
-#define KEY_PREVIOUS 0x19c
-#define KEY_DIGITS 0x19d
-#define KEY_TEEN 0x19e
-#define KEY_TWEN 0x19f
-#define KEY_VIDEOPHONE 0x1a0 /* Media Select Video Phone */
-#define KEY_GAMES 0x1a1 /* Media Select Games */
-#define KEY_ZOOMIN 0x1a2 /* AC Zoom In */
-#define KEY_ZOOMOUT 0x1a3 /* AC Zoom Out */
-#define KEY_ZOOMRESET 0x1a4 /* AC Zoom */
-#define KEY_WORDPROCESSOR 0x1a5 /* AL Word Processor */
-#define KEY_EDITOR 0x1a6 /* AL Text Editor */
-#define KEY_SPREADSHEET 0x1a7 /* AL Spreadsheet */
-#define KEY_GRAPHICSEDITOR 0x1a8 /* AL Graphics Editor */
-#define KEY_PRESENTATION 0x1a9 /* AL Presentation App */
-#define KEY_DATABASE 0x1aa /* AL Database App */
-#define KEY_NEWS 0x1ab /* AL Newsreader */
-#define KEY_VOICEMAIL 0x1ac /* AL Voicemail */
-#define KEY_ADDRESSBOOK 0x1ad /* AL Contacts/Address Book */
-#define KEY_MESSENGER 0x1ae /* AL Instant Messaging */
-#define KEY_DISPLAYTOGGLE 0x1af /* Turn display (LCD) on and off */
-#define KEY_BRIGHTNESS_TOGGLE KEY_DISPLAYTOGGLE
-#define KEY_SPELLCHECK 0x1b0 /* AL Spell Check */
-#define KEY_LOGOFF 0x1b1 /* AL Logoff */
-
-#define KEY_DOLLAR 0x1b2
-#define KEY_EURO 0x1b3
-
-#define KEY_FRAMEBACK 0x1b4 /* Consumer - transport controls */
-#define KEY_FRAMEFORWARD 0x1b5
-#define KEY_CONTEXT_MENU 0x1b6 /* GenDesc - system context menu */
-#define KEY_MEDIA_REPEAT 0x1b7 /* Consumer - transport control */
-#define KEY_10CHANNELSUP 0x1b8 /* 10 channels up (10+) */
-#define KEY_10CHANNELSDOWN 0x1b9 /* 10 channels down (10-) */
-#define KEY_IMAGES 0x1ba /* AL Image Browser */
-
-#define KEY_DEL_EOL 0x1c0
-#define KEY_DEL_EOS 0x1c1
-#define KEY_INS_LINE 0x1c2
-#define KEY_DEL_LINE 0x1c3
-
-#define KEY_FN 0x1d0
-#define KEY_FN_ESC 0x1d1
-#define KEY_FN_F1 0x1d2
-#define KEY_FN_F2 0x1d3
-#define KEY_FN_F3 0x1d4
-#define KEY_FN_F4 0x1d5
-#define KEY_FN_F5 0x1d6
-#define KEY_FN_F6 0x1d7
-#define KEY_FN_F7 0x1d8
-#define KEY_FN_F8 0x1d9
-#define KEY_FN_F9 0x1da
-#define KEY_FN_F10 0x1db
-#define KEY_FN_F11 0x1dc
-#define KEY_FN_F12 0x1dd
-#define KEY_FN_1 0x1de
-#define KEY_FN_2 0x1df
-#define KEY_FN_D 0x1e0
-#define KEY_FN_E 0x1e1
-#define KEY_FN_F 0x1e2
-#define KEY_FN_S 0x1e3
-#define KEY_FN_B 0x1e4
-
-#define KEY_BRL_DOT1 0x1f1
-#define KEY_BRL_DOT2 0x1f2
-#define KEY_BRL_DOT3 0x1f3
-#define KEY_BRL_DOT4 0x1f4
-#define KEY_BRL_DOT5 0x1f5
-#define KEY_BRL_DOT6 0x1f6
-#define KEY_BRL_DOT7 0x1f7
-#define KEY_BRL_DOT8 0x1f8
-#define KEY_BRL_DOT9 0x1f9
-#define KEY_BRL_DOT10 0x1fa
-
-#define KEY_NUMERIC_0 0x200 /* used by phones, remote controls, */
-#define KEY_NUMERIC_1 0x201 /* and other keypads */
-#define KEY_NUMERIC_2 0x202
-#define KEY_NUMERIC_3 0x203
-#define KEY_NUMERIC_4 0x204
-#define KEY_NUMERIC_5 0x205
-#define KEY_NUMERIC_6 0x206
-#define KEY_NUMERIC_7 0x207
-#define KEY_NUMERIC_8 0x208
-#define KEY_NUMERIC_9 0x209
-#define KEY_NUMERIC_STAR 0x20a
-#define KEY_NUMERIC_POUND 0x20b
-#define KEY_NUMERIC_A 0x20c /* Phone key A - HUT Telephony 0xb9 */
-#define KEY_NUMERIC_B 0x20d
-#define KEY_NUMERIC_C 0x20e
-#define KEY_NUMERIC_D 0x20f
-
-#define KEY_CAMERA_FOCUS 0x210
-#define KEY_WPS_BUTTON 0x211 /* WiFi Protected Setup key */
-
-#define KEY_TOUCHPAD_TOGGLE 0x212 /* Request switch touchpad on or off */
-#define KEY_TOUCHPAD_ON 0x213
-#define KEY_TOUCHPAD_OFF 0x214
-
-#define KEY_CAMERA_ZOOMIN 0x215
-#define KEY_CAMERA_ZOOMOUT 0x216
-#define KEY_CAMERA_UP 0x217
-#define KEY_CAMERA_DOWN 0x218
-#define KEY_CAMERA_LEFT 0x219
-#define KEY_CAMERA_RIGHT 0x21a
-
-#define KEY_ATTENDANT_ON 0x21b
-#define KEY_ATTENDANT_OFF 0x21c
-#define KEY_ATTENDANT_TOGGLE 0x21d /* Attendant call on or off */
-#define KEY_LIGHTS_TOGGLE 0x21e /* Reading light on or off */
-
-#define BTN_DPAD_UP 0x220
-#define BTN_DPAD_DOWN 0x221
-#define BTN_DPAD_LEFT 0x222
-#define BTN_DPAD_RIGHT 0x223
-
-#define KEY_ALS_TOGGLE 0x230 /* Ambient light sensor */
-
-#define KEY_BUTTONCONFIG 0x240 /* AL Button Configuration */
-#define KEY_TASKMANAGER 0x241 /* AL Task/Project Manager */
-#define KEY_JOURNAL 0x242 /* AL Log/Journal/Timecard */
-#define KEY_CONTROLPANEL 0x243 /* AL Control Panel */
-#define KEY_APPSELECT 0x244 /* AL Select Task/Application */
-#define KEY_SCREENSAVER 0x245 /* AL Screen Saver */
-#define KEY_VOICECOMMAND 0x246 /* Listening Voice Command */
-
-#define KEY_BRIGHTNESS_MIN 0x250 /* Set Brightness to Minimum */
-#define KEY_BRIGHTNESS_MAX 0x251 /* Set Brightness to Maximum */
-
-#define KEY_KBDINPUTASSIST_PREV 0x260
-#define KEY_KBDINPUTASSIST_NEXT 0x261
-#define KEY_KBDINPUTASSIST_PREVGROUP 0x262
-#define KEY_KBDINPUTASSIST_NEXTGROUP 0x263
-#define KEY_KBDINPUTASSIST_ACCEPT 0x264
-#define KEY_KBDINPUTASSIST_CANCEL 0x265
-
-#define BTN_TRIGGER_HAPPY 0x2c0
-#define BTN_TRIGGER_HAPPY1 0x2c0
-#define BTN_TRIGGER_HAPPY2 0x2c1
-#define BTN_TRIGGER_HAPPY3 0x2c2
-#define BTN_TRIGGER_HAPPY4 0x2c3
-#define BTN_TRIGGER_HAPPY5 0x2c4
-#define BTN_TRIGGER_HAPPY6 0x2c5
-#define BTN_TRIGGER_HAPPY7 0x2c6
-#define BTN_TRIGGER_HAPPY8 0x2c7
-#define BTN_TRIGGER_HAPPY9 0x2c8
-#define BTN_TRIGGER_HAPPY10 0x2c9
-#define BTN_TRIGGER_HAPPY11 0x2ca
-#define BTN_TRIGGER_HAPPY12 0x2cb
-#define BTN_TRIGGER_HAPPY13 0x2cc
-#define BTN_TRIGGER_HAPPY14 0x2cd
-#define BTN_TRIGGER_HAPPY15 0x2ce
-#define BTN_TRIGGER_HAPPY16 0x2cf
-#define BTN_TRIGGER_HAPPY17 0x2d0
-#define BTN_TRIGGER_HAPPY18 0x2d1
-#define BTN_TRIGGER_HAPPY19 0x2d2
-#define BTN_TRIGGER_HAPPY20 0x2d3
-#define BTN_TRIGGER_HAPPY21 0x2d4
-#define BTN_TRIGGER_HAPPY22 0x2d5
-#define BTN_TRIGGER_HAPPY23 0x2d6
-#define BTN_TRIGGER_HAPPY24 0x2d7
-#define BTN_TRIGGER_HAPPY25 0x2d8
-#define BTN_TRIGGER_HAPPY26 0x2d9
-#define BTN_TRIGGER_HAPPY27 0x2da
-#define BTN_TRIGGER_HAPPY28 0x2db
-#define BTN_TRIGGER_HAPPY29 0x2dc
-#define BTN_TRIGGER_HAPPY30 0x2dd
-#define BTN_TRIGGER_HAPPY31 0x2de
-#define BTN_TRIGGER_HAPPY32 0x2df
-#define BTN_TRIGGER_HAPPY33 0x2e0
-#define BTN_TRIGGER_HAPPY34 0x2e1
-#define BTN_TRIGGER_HAPPY35 0x2e2
-#define BTN_TRIGGER_HAPPY36 0x2e3
-#define BTN_TRIGGER_HAPPY37 0x2e4
-#define BTN_TRIGGER_HAPPY38 0x2e5
-#define BTN_TRIGGER_HAPPY39 0x2e6
-#define BTN_TRIGGER_HAPPY40 0x2e7
-
-/* We avoid low common keys in module aliases so they don't get huge. */
-#define KEY_MIN_INTERESTING KEY_MUTE
-#define KEY_MAX 0x2ff
-#define KEY_CNT (KEY_MAX+1)
-
-/*
- * Relative axes
- */
-
-#define REL_X 0x00
-#define REL_Y 0x01
-#define REL_Z 0x02
-#define REL_RX 0x03
-#define REL_RY 0x04
-#define REL_RZ 0x05
-#define REL_HWHEEL 0x06
-#define REL_DIAL 0x07
-#define REL_WHEEL 0x08
-#define REL_MISC 0x09
-#define REL_MAX 0x0f
-#define REL_CNT (REL_MAX+1)
-
-/*
- * Absolute axes
- */
-
-#define ABS_X 0x00
-#define ABS_Y 0x01
-#define ABS_Z 0x02
-#define ABS_RX 0x03
-#define ABS_RY 0x04
-#define ABS_RZ 0x05
-#define ABS_THROTTLE 0x06
-#define ABS_RUDDER 0x07
-#define ABS_WHEEL 0x08
-#define ABS_GAS 0x09
-#define ABS_BRAKE 0x0a
-#define ABS_HAT0X 0x10
-#define ABS_HAT0Y 0x11
-#define ABS_HAT1X 0x12
-#define ABS_HAT1Y 0x13
-#define ABS_HAT2X 0x14
-#define ABS_HAT2Y 0x15
-#define ABS_HAT3X 0x16
-#define ABS_HAT3Y 0x17
-#define ABS_PRESSURE 0x18
-#define ABS_DISTANCE 0x19
-#define ABS_TILT_X 0x1a
-#define ABS_TILT_Y 0x1b
-#define ABS_TOOL_WIDTH 0x1c
-
-#define ABS_VOLUME 0x20
-
-#define ABS_MISC 0x28
-
-#define ABS_MT_SLOT 0x2f /* MT slot being modified */
-#define ABS_MT_TOUCH_MAJOR 0x30 /* Major axis of touching ellipse */
-#define ABS_MT_TOUCH_MINOR 0x31 /* Minor axis (omit if circular) */
-#define ABS_MT_WIDTH_MAJOR 0x32 /* Major axis of approaching ellipse */
-#define ABS_MT_WIDTH_MINOR 0x33 /* Minor axis (omit if circular) */
-#define ABS_MT_ORIENTATION 0x34 /* Ellipse orientation */
-#define ABS_MT_POSITION_X 0x35 /* Center X touch position */
-#define ABS_MT_POSITION_Y 0x36 /* Center Y touch position */
-#define ABS_MT_TOOL_TYPE 0x37 /* Type of touching device */
-#define ABS_MT_BLOB_ID 0x38 /* Group a set of packets as a blob */
-#define ABS_MT_TRACKING_ID 0x39 /* Unique ID of initiated contact */
-#define ABS_MT_PRESSURE 0x3a /* Pressure on contact area */
-#define ABS_MT_DISTANCE 0x3b /* Contact hover distance */
-#define ABS_MT_TOOL_X 0x3c /* Center X tool position */
-#define ABS_MT_TOOL_Y 0x3d /* Center Y tool position */
-
-
-#define ABS_MAX 0x3f
-#define ABS_CNT (ABS_MAX+1)
-
-/*
- * Switch events
- */
-
-#define SW_LID 0x00 /* set = lid shut */
-#define SW_TABLET_MODE 0x01 /* set = tablet mode */
-#define SW_HEADPHONE_INSERT 0x02 /* set = inserted */
-#define SW_RFKILL_ALL 0x03 /* rfkill master switch, type "any"
- set = radio enabled */
-#define SW_RADIO SW_RFKILL_ALL /* deprecated */
-#define SW_MICROPHONE_INSERT 0x04 /* set = inserted */
-#define SW_DOCK 0x05 /* set = plugged into dock */
-#define SW_LINEOUT_INSERT 0x06 /* set = inserted */
-#define SW_JACK_PHYSICAL_INSERT 0x07 /* set = mechanical switch set */
-#define SW_VIDEOOUT_INSERT 0x08 /* set = inserted */
-#define SW_CAMERA_LENS_COVER 0x09 /* set = lens covered */
-#define SW_KEYPAD_SLIDE 0x0a /* set = keypad slide out */
-#define SW_FRONT_PROXIMITY 0x0b /* set = front proximity sensor active */
-#define SW_ROTATE_LOCK 0x0c /* set = rotate locked/disabled */
-#define SW_LINEIN_INSERT 0x0d /* set = inserted */
-#define SW_MUTE_DEVICE 0x0e /* set = device disabled */
-#define SW_MAX 0x0f
-#define SW_CNT (SW_MAX+1)
-
-/*
- * Misc events
- */
-
-#define MSC_SERIAL 0x00
-#define MSC_PULSELED 0x01
-#define MSC_GESTURE 0x02
-#define MSC_RAW 0x03
-#define MSC_SCAN 0x04
-#define MSC_TIMESTAMP 0x05
-#define MSC_MAX 0x07
-#define MSC_CNT (MSC_MAX+1)
-
-/*
- * LEDs
- */
-
-#define LED_NUML 0x00
-#define LED_CAPSL 0x01
-#define LED_SCROLLL 0x02
-#define LED_COMPOSE 0x03
-#define LED_KANA 0x04
-#define LED_SLEEP 0x05
-#define LED_SUSPEND 0x06
-#define LED_MUTE 0x07
-#define LED_MISC 0x08
-#define LED_MAIL 0x09
-#define LED_CHARGING 0x0a
-#define LED_MAX 0x0f
-#define LED_CNT (LED_MAX+1)
-
-/*
- * Autorepeat values
- */
-
-#define REP_DELAY 0x00
-#define REP_PERIOD 0x01
-#define REP_MAX 0x01
-#define REP_CNT (REP_MAX+1)
-
-/*
- * Sounds
- */
-
-#define SND_CLICK 0x00
-#define SND_BELL 0x01
-#define SND_TONE 0x02
-#define SND_MAX 0x07
-#define SND_CNT (SND_MAX+1)
-
-#endif
diff --git a/include/dt-bindings/interrupt-controller/arm-gic.h b/include/dt-bindings/interrupt-controller/arm-gic.h
deleted file mode 100644
index 1ea1b70..0000000
--- a/include/dt-bindings/interrupt-controller/arm-gic.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * This header provides constants for the ARM GIC.
- */
-
-#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_ARM_GIC_H
-#define _DT_BINDINGS_INTERRUPT_CONTROLLER_ARM_GIC_H
-
-#include <dt-bindings/interrupt-controller/irq.h>
-
-/* interrupt specific cell 0 */
-
-#define GIC_SPI 0
-#define GIC_PPI 1
-
-/*
- * Interrupt specifier cell 2.
- * The flaggs in irq.h are valid, plus those below.
- */
-#define GIC_CPU_MASK_RAW(x) ((x) << 8)
-#define GIC_CPU_MASK_SIMPLE(num) GIC_CPU_MASK_RAW((1 << (num)) - 1)
-
-#endif
diff --git a/include/dt-bindings/interrupt-controller/irq-st.h b/include/dt-bindings/interrupt-controller/irq-st.h
deleted file mode 100644
index 6baa9ad..0000000
--- a/include/dt-bindings/interrupt-controller/irq-st.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * include/linux/irqchip/irq-st.h
- *
- * Copyright (C) 2014 STMicroelectronics All Rights Reserved
- *
- * Author: Lee Jones <lee.jones@linaro.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_ST_H
-#define _DT_BINDINGS_INTERRUPT_CONTROLLER_ST_H
-
-#define ST_IRQ_SYSCFG_EXT_0 0
-#define ST_IRQ_SYSCFG_EXT_1 1
-#define ST_IRQ_SYSCFG_EXT_2 2
-#define ST_IRQ_SYSCFG_CTI_0 3
-#define ST_IRQ_SYSCFG_CTI_1 4
-#define ST_IRQ_SYSCFG_PMU_0 5
-#define ST_IRQ_SYSCFG_PMU_1 6
-#define ST_IRQ_SYSCFG_pl310_L2 7
-#define ST_IRQ_SYSCFG_DISABLED 0xFFFFFFFF
-
-#define ST_IRQ_SYSCFG_EXT_1_INV 0x1
-#define ST_IRQ_SYSCFG_EXT_2_INV 0x2
-#define ST_IRQ_SYSCFG_EXT_3_INV 0x4
-
-#endif
diff --git a/include/dt-bindings/interrupt-controller/irq.h b/include/dt-bindings/interrupt-controller/irq.h
deleted file mode 100644
index 33a1003..0000000
--- a/include/dt-bindings/interrupt-controller/irq.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * This header provides constants for most IRQ bindings.
- *
- * Most IRQ bindings include a flags cell as part of the IRQ specifier.
- * In most cases, the format of the flags cell uses the standard values
- * defined in this header.
- */
-
-#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H
-#define _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H
-
-#define IRQ_TYPE_NONE 0
-#define IRQ_TYPE_EDGE_RISING 1
-#define IRQ_TYPE_EDGE_FALLING 2
-#define IRQ_TYPE_EDGE_BOTH (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)
-#define IRQ_TYPE_LEVEL_HIGH 4
-#define IRQ_TYPE_LEVEL_LOW 8
-
-#endif
diff --git a/include/dt-bindings/interrupt-controller/mips-gic.h b/include/dt-bindings/interrupt-controller/mips-gic.h
deleted file mode 100644
index cf35a57..0000000
--- a/include/dt-bindings/interrupt-controller/mips-gic.h
+++ /dev/null
@@ -1,9 +0,0 @@
-#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_MIPS_GIC_H
-#define _DT_BINDINGS_INTERRUPT_CONTROLLER_MIPS_GIC_H
-
-#include <dt-bindings/interrupt-controller/irq.h>
-
-#define GIC_SHARED 0
-#define GIC_LOCAL 1
-
-#endif
diff --git a/include/dt-bindings/interrupt-router/intel-irq.h b/include/dt-bindings/interrupt-router/intel-irq.h
deleted file mode 100644
index 2d1e671..0000000
--- a/include/dt-bindings/interrupt-router/intel-irq.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
- */
-
-#ifndef _DT_BINDINGS_INTEL_IRQ_H_
-#define _DT_BINDINGS_INTEL_IRQ_H_
-
-/* PCI interrupt pin */
-#define INTA 1
-#define INTB 2
-#define INTC 3
-#define INTD 4
-
-/* PIRQs */
-#define PIRQA 0
-#define PIRQB 1
-#define PIRQC 2
-#define PIRQD 3
-#define PIRQE 4
-#define PIRQF 5
-#define PIRQG 6
-#define PIRQH 7
-
-/* PCI bdf encoding */
-#ifndef PCI_BDF
-#define PCI_BDF(b, d, f) ((b) << 16 | (d) << 11 | (f) << 8)
-#endif
-
-#endif /* _DT_BINDINGS_INTEL_IRQ_H_ */
diff --git a/include/dt-bindings/leds/leds-netxbig.h b/include/dt-bindings/leds/leds-netxbig.h
deleted file mode 100644
index 92658b0..0000000
--- a/include/dt-bindings/leds/leds-netxbig.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- * This header provides constants for netxbig LED bindings.
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef _DT_BINDINGS_LEDS_NETXBIG_H
-#define _DT_BINDINGS_LEDS_NETXBIG_H
-
-#define NETXBIG_LED_OFF 0
-#define NETXBIG_LED_ON 1
-#define NETXBIG_LED_SATA 2
-#define NETXBIG_LED_TIMER1 3
-#define NETXBIG_LED_TIMER2 4
-
-#endif /* _DT_BINDINGS_LEDS_NETXBIG_H */
diff --git a/include/dt-bindings/leds/leds-ns2.h b/include/dt-bindings/leds/leds-ns2.h
deleted file mode 100644
index fd61574..0000000
--- a/include/dt-bindings/leds/leds-ns2.h
+++ /dev/null
@@ -1,9 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _DT_BINDINGS_LEDS_NS2_H
-#define _DT_BINDINGS_LEDS_NS2_H
-
-#define NS_V2_LED_OFF 0
-#define NS_V2_LED_ON 1
-#define NS_V2_LED_SATA 2
-
-#endif
diff --git a/include/dt-bindings/leds/leds-pca9532.h b/include/dt-bindings/leds/leds-pca9532.h
deleted file mode 100644
index 4d917aa..0000000
--- a/include/dt-bindings/leds/leds-pca9532.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- * This header provides constants for pca9532 LED bindings.
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef _DT_BINDINGS_LEDS_PCA9532_H
-#define _DT_BINDINGS_LEDS_PCA9532_H
-
-#define PCA9532_TYPE_NONE 0
-#define PCA9532_TYPE_LED 1
-#define PCA9532_TYPE_N2100_BEEP 2
-#define PCA9532_TYPE_GPIO 3
-#define PCA9532_LED_TIMER2 4
-
-#endif /* _DT_BINDINGS_LEDS_PCA9532_H */
diff --git a/include/dt-bindings/mailbox/tegra186-hsp.h b/include/dt-bindings/mailbox/tegra186-hsp.h
deleted file mode 100644
index b486432..0000000
--- a/include/dt-bindings/mailbox/tegra186-hsp.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * This header provides constants for binding nvidia,tegra186-hsp.
- *
- * The number with HSP_DB_MASTER prefix indicates the bit that is
- * associated with a master ID in the doorbell registers.
- */
-
-#ifndef _DT_BINDINGS_MAILBOX_TEGRA186_HSP_H
-#define _DT_BINDINGS_MAILBOX_TEGRA186_HSP_H
-
-#define HSP_MBOX_TYPE_DB 0x0
-#define HSP_MBOX_TYPE_SM 0x1
-#define HSP_MBOX_TYPE_SS 0x2
-#define HSP_MBOX_TYPE_AS 0x3
-
-#define HSP_DB_MASTER_CCPLEX 17
-#define HSP_DB_MASTER_BPMP 19
-
-#endif
diff --git a/include/dt-bindings/media/omap3-isp.h b/include/dt-bindings/media/omap3-isp.h
deleted file mode 100644
index 4e42084..0000000
--- a/include/dt-bindings/media/omap3-isp.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * include/dt-bindings/media/omap3-isp.h
- *
- * Copyright (C) 2015 Sakari Ailus
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- * General Public License for more details.
- */
-
-#ifndef __DT_BINDINGS_OMAP3_ISP_H__
-#define __DT_BINDINGS_OMAP3_ISP_H__
-
-#define OMAP3ISP_PHY_TYPE_COMPLEX_IO 0
-#define OMAP3ISP_PHY_TYPE_CSIPHY 1
-
-#endif /* __DT_BINDINGS_OMAP3_ISP_H__ */
diff --git a/include/dt-bindings/memory/mpc83xx-sdram.h b/include/dt-bindings/memory/mpc83xx-sdram.h
deleted file mode 100644
index 7d4ce01..0000000
--- a/include/dt-bindings/memory/mpc83xx-sdram.h
+++ /dev/null
@@ -1,161 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2018
- * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
- */
-
-#ifndef DT_BINDINGS_MPC83XX_SDRAM_H
-#define DT_BINDINGS_MPC83XX_SDRAM_H
-
-/* DDR Control Driver register */
-
-#define DSO_DISABLE 0
-#define DSO_ENABLE 1
-
-#define DSO_P_IMPEDANCE_HIGHEST_Z 0x0
-#define DSO_P_IMPEDANCE_MUCH_HIGHER_Z 0x8
-#define DSO_P_IMPEDANCE_HIGHER_Z 0xC
-#define DSO_P_IMPEDANCE_NOMINAL 0xE
-#define DSO_P_IMPEDANCE_LOWER_Z 0xF
-
-#define DSO_N_IMPEDANCE_HIGHEST_Z 0x0
-#define DSO_N_IMPEDANCE_MUCH_HIGHER_Z 0x8
-#define DSO_N_IMPEDANCE_HIGHER_Z 0xC
-#define DSO_N_IMPEDANCE_NOMINAL 0xE
-#define DSO_N_IMPEDANCE_LOWER_Z 0xF
-
-#define ODT_TERMINATION_75_OHM 0
-#define ODT_TERMINATION_150_OHM 1
-
-#define DDR_TYPE_DDR2_1_8_VOLT 0
-#define DDR_TYPE_DDR1_2_5_VOLT 1
-
-#define MVREF_SEL_EXTERNAL 0
-#define MVREF_SEL_INTERNAL_GVDD 1
-
-#define M_ODR_ENABLE 0
-#define M_ODR_DISABLE 1
-
-/* CS config register */
-
-#define AUTO_PRECHARGE_ENABLE 0x00800000
-#define AUTO_PRECHARGE_DISABLE 0x00000000
-
-#define ODT_RD_NEVER 0x00000000
-#define ODT_RD_ONLY_CURRENT 0x00100000
-#define ODT_RD_ONLY_OTHER_CS 0x00200000
-#define ODT_RD_ONLY_OTHER_DIMM 0x00300000
-#define ODT_RD_ALL 0x00400000
-
-#define ODT_WR_NEVER 0x00000000
-#define ODT_WR_ONLY_CURRENT 0x00010000
-#define ODT_WR_ONLY_OTHER_CS 0x00020000
-#define ODT_WR_ONLY_OTHER_DIMM 0x00030000
-#define ODT_WR_ALL 0x00040000
-
-/* DDR SDRAM Clock Control register */
-
-#define CLOCK_ADJUST_025 0x01000000
-#define CLOCK_ADJUST_05 0x02000000
-#define CLOCK_ADJUST_075 0x03000000
-#define CLOCK_ADJUST_1 0x04000000
-
-#define CASLAT_20 0x3 /* CAS latency = 2.0 */
-#define CASLAT_25 0x4 /* CAS latency = 2.5 */
-#define CASLAT_30 0x5 /* CAS latency = 3.0 */
-#define CASLAT_35 0x6 /* CAS latency = 3.5 */
-#define CASLAT_40 0x7 /* CAS latency = 4.0 */
-#define CASLAT_45 0x8 /* CAS latency = 4.5 */
-#define CASLAT_50 0x9 /* CAS latency = 5.0 */
-#define CASLAT_55 0xa /* CAS latency = 5.5 */
-#define CASLAT_60 0xb /* CAS latency = 6.0 */
-#define CASLAT_65 0xc /* CAS latency = 6.5 */
-#define CASLAT_70 0xd /* CAS latency = 7.0 */
-#define CASLAT_75 0xe /* CAS latency = 7.5 */
-#define CASLAT_80 0xf /* CAS latency = 8.0 */
-
-/* DDR SDRAM Timing Configuration 2 register */
-
-#define READ_LAT_PLUS_1 0x0
-#define READ_LAT 0x2
-#define READ_LAT_PLUS_1_4 0x3
-#define READ_LAT_PLUS_1_2 0x4
-#define READ_LAT_PLUS_3_4 0x5
-#define READ_LAT_PLUS_5_4 0x7
-#define READ_LAT_PLUS_3_2 0x8
-#define READ_LAT_PLUS_7_4 0x9
-#define READ_LAT_PLUS_2 0xA
-#define READ_LAT_PLUS_9_4 0xB
-#define READ_LAT_PLUS_5_2 0xC
-#define READ_LAT_PLUS_11_4 0xD
-#define READ_LAT_PLUS_3 0xE
-#define READ_LAT_PLUS_13_4 0xF
-#define READ_LAT_PLUS_7_2 0x10
-#define READ_LAT_PLUS_15_4 0x11
-#define READ_LAT_PLUS_4 0x12
-#define READ_LAT_PLUS_17_4 0x13
-#define READ_LAT_PLUS_9_2 0x14
-#define READ_LAT_PLUS_19_4 0x15
-
-#define CLOCK_DELAY_0 0x0
-#define CLOCK_DELAY_1_4 0x1
-#define CLOCK_DELAY_1_2 0x2
-#define CLOCK_DELAY_3_4 0x3
-#define CLOCK_DELAY_1 0x4
-#define CLOCK_DELAY_5_4 0x5
-#define CLOCK_DELAY_3_2 0x6
-
-/* DDR SDRAM Control Configuration */
-
-#define SREN_DISABLE 0x0
-#define SREN_ENABLE 0x1
-
-#define ECC_DISABLE 0x0
-#define ECC_ENABLE 0x1
-
-#define RD_DISABLE 0x0
-#define RD_ENABLE 0x1
-
-#define TYPE_DDR1 0x2
-#define TYPE_DDR2 0x3
-
-#define DYN_PWR_DISABLE 0x0
-#define DYN_PWR_ENABLE 0x1
-
-#define DATA_BUS_WIDTH_16 0x1
-#define DATA_BUS_WIDTH_32 0x2
-
-#define NCAP_DISABLE 0x0
-#define NCAP_ENABLE 0x1
-
-#define TIMING_1T 0x0
-#define TIMING_2T 0x1
-
-#define INTERLEAVE_NONE 0x0
-#define INTERLEAVE_1_AND_2 0x1
-
-#define PRECHARGE_MA_10 0x0
-#define PRECHARGE_MA_8 0x1
-
-#define STRENGTH_FULL 0x0
-#define STRENGTH_HALF 0x1
-
-#define INITIALIZATION_DONT_BYPASS 0x0
-#define INITIALIZATION_BYPASS 0x1
-
-/* DDR SDRAM Control Configuration 2 register */
-
-#define MODE_NORMAL 0x0
-#define MODE_REFRESH 0x1
-
-#define DLL_RESET_ENABLE 0x0
-#define DLL_RESET_DISABLE 0x1
-
-#define DQS_TRUE 0x0
-
-#define ODT_ASSERT_NEVER 0x0
-#define ODT_ASSERT_WRITES 0x1
-#define ODT_ASSERT_READS 0x2
-#define ODT_ASSERT_ALWAYS 0x3
-
-#endif
diff --git a/include/dt-bindings/memory/rk3368-dmc.h b/include/dt-bindings/memory/rk3368-dmc.h
deleted file mode 100644
index b06ffde..0000000
--- a/include/dt-bindings/memory/rk3368-dmc.h
+++ /dev/null
@@ -1,30 +0,0 @@
-#ifndef DT_BINDINGS_RK3368_DMC_H
-#define DT_BINDINGS_RK3368_DMC_H
-
-#define DMC_MSCH_CBDR 0x0
-#define DMC_MSCH_CBRD 0x1
-#define DMC_MSCH_CRBD 0x2
-
-#define DDR3_800D 0
-#define DDR3_800E 1
-#define DDR3_1066E 2
-#define DDR3_1066F 3
-#define DDR3_1066G 4
-#define DDR3_1333F 5
-#define DDR3_1333G 6
-#define DDR3_1333H 7
-#define DDR3_1333J 8
-#define DDR3_1600G 9
-#define DDR3_1600H 10
-#define DDR3_1600J 11
-#define DDR3_1600K 12
-#define DDR3_1866J 13
-#define DDR3_1866K 14
-#define DDR3_1866L 15
-#define DDR3_1866M 16
-#define DDR3_2133K 17
-#define DDR3_2133L 18
-#define DDR3_2133M 19
-#define DDR3_2133N 20
-
-#endif
diff --git a/include/dt-bindings/memory/stm32-sdram.h b/include/dt-bindings/memory/stm32-sdram.h
deleted file mode 100644
index ab91d2b..0000000
--- a/include/dt-bindings/memory/stm32-sdram.h
+++ /dev/null
@@ -1,46 +0,0 @@
-#ifndef DT_BINDINGS_STM32_SDRAM_H
-#define DT_BINDINGS_STM32_SDRAM_H
-
-#define NO_COL_8 0x0
-#define NO_COL_9 0x1
-#define NO_COL_10 0x2
-#define NO_COL_11 0x3
-
-#define NO_ROW_11 0x0
-#define NO_ROW_12 0x1
-#define NO_ROW_13 0x2
-
-#define MWIDTH_8 0x0
-#define MWIDTH_16 0x1
-#define MWIDTH_32 0x2
-#define BANKS_2 0x0
-#define BANKS_4 0x1
-#define CAS_1 0x1
-#define CAS_2 0x2
-#define CAS_3 0x3
-#define SDCLK_DIS 0x0
-#define SDCLK_2 0x2
-#define SDCLK_3 0x3
-#define RD_BURST_EN 0x1
-#define RD_BURST_DIS 0x0
-#define RD_PIPE_DL_0 0x0
-#define RD_PIPE_DL_1 0x1
-#define RD_PIPE_DL_2 0x2
-
-/* Timing = value +1 cycles */
-#define TMRD_1 (1 - 1)
-#define TMRD_2 (2 - 1)
-#define TMRD_3 (3 - 1)
-#define TXSR_1 (1 - 1)
-#define TXSR_6 (6 - 1)
-#define TXSR_7 (7 - 1)
-#define TRAS_1 (1 - 1)
-#define TRAS_4 (4 - 1)
-#define TRC_6 (6 - 1)
-#define TWR_1 (1 - 1)
-#define TWR_2 (2 - 1)
-#define TRP_2 (2 - 1)
-#define TRCD_1 (1 - 1)
-#define TRCD_2 (2 - 1)
-
-#endif
diff --git a/include/dt-bindings/memory/tegra114-mc.h b/include/dt-bindings/memory/tegra114-mc.h
deleted file mode 100644
index 8f48985..0000000
--- a/include/dt-bindings/memory/tegra114-mc.h
+++ /dev/null
@@ -1,25 +0,0 @@
-#ifndef DT_BINDINGS_MEMORY_TEGRA114_MC_H
-#define DT_BINDINGS_MEMORY_TEGRA114_MC_H
-
-#define TEGRA_SWGROUP_PTC 0
-#define TEGRA_SWGROUP_DC 1
-#define TEGRA_SWGROUP_DCB 2
-#define TEGRA_SWGROUP_EPP 3
-#define TEGRA_SWGROUP_G2 4
-#define TEGRA_SWGROUP_AVPC 5
-#define TEGRA_SWGROUP_NV 6
-#define TEGRA_SWGROUP_HDA 7
-#define TEGRA_SWGROUP_HC 8
-#define TEGRA_SWGROUP_MSENC 9
-#define TEGRA_SWGROUP_PPCS 10
-#define TEGRA_SWGROUP_VDE 11
-#define TEGRA_SWGROUP_MPCORELP 12
-#define TEGRA_SWGROUP_MPCORE 13
-#define TEGRA_SWGROUP_VI 14
-#define TEGRA_SWGROUP_ISP 15
-#define TEGRA_SWGROUP_XUSB_HOST 16
-#define TEGRA_SWGROUP_XUSB_DEV 17
-#define TEGRA_SWGROUP_EMUCIF 18
-#define TEGRA_SWGROUP_TSEC 19
-
-#endif
diff --git a/include/dt-bindings/memory/tegra124-mc.h b/include/dt-bindings/memory/tegra124-mc.h
deleted file mode 100644
index 7d8ee79..0000000
--- a/include/dt-bindings/memory/tegra124-mc.h
+++ /dev/null
@@ -1,31 +0,0 @@
-#ifndef DT_BINDINGS_MEMORY_TEGRA124_MC_H
-#define DT_BINDINGS_MEMORY_TEGRA124_MC_H
-
-#define TEGRA_SWGROUP_PTC 0
-#define TEGRA_SWGROUP_DC 1
-#define TEGRA_SWGROUP_DCB 2
-#define TEGRA_SWGROUP_AFI 3
-#define TEGRA_SWGROUP_AVPC 4
-#define TEGRA_SWGROUP_HDA 5
-#define TEGRA_SWGROUP_HC 6
-#define TEGRA_SWGROUP_MSENC 7
-#define TEGRA_SWGROUP_PPCS 8
-#define TEGRA_SWGROUP_SATA 9
-#define TEGRA_SWGROUP_VDE 10
-#define TEGRA_SWGROUP_MPCORELP 11
-#define TEGRA_SWGROUP_MPCORE 12
-#define TEGRA_SWGROUP_ISP2 13
-#define TEGRA_SWGROUP_XUSB_HOST 14
-#define TEGRA_SWGROUP_XUSB_DEV 15
-#define TEGRA_SWGROUP_ISP2B 16
-#define TEGRA_SWGROUP_TSEC 17
-#define TEGRA_SWGROUP_A9AVP 18
-#define TEGRA_SWGROUP_GPU 19
-#define TEGRA_SWGROUP_SDMMC1A 20
-#define TEGRA_SWGROUP_SDMMC2A 21
-#define TEGRA_SWGROUP_SDMMC3A 22
-#define TEGRA_SWGROUP_SDMMC4A 23
-#define TEGRA_SWGROUP_VIC 24
-#define TEGRA_SWGROUP_VI 25
-
-#endif
diff --git a/include/dt-bindings/memory/tegra210-mc.h b/include/dt-bindings/memory/tegra210-mc.h
deleted file mode 100644
index d1731bc..0000000
--- a/include/dt-bindings/memory/tegra210-mc.h
+++ /dev/null
@@ -1,36 +0,0 @@
-#ifndef DT_BINDINGS_MEMORY_TEGRA210_MC_H
-#define DT_BINDINGS_MEMORY_TEGRA210_MC_H
-
-#define TEGRA_SWGROUP_PTC 0
-#define TEGRA_SWGROUP_DC 1
-#define TEGRA_SWGROUP_DCB 2
-#define TEGRA_SWGROUP_AFI 3
-#define TEGRA_SWGROUP_AVPC 4
-#define TEGRA_SWGROUP_HDA 5
-#define TEGRA_SWGROUP_HC 6
-#define TEGRA_SWGROUP_NVENC 7
-#define TEGRA_SWGROUP_PPCS 8
-#define TEGRA_SWGROUP_SATA 9
-#define TEGRA_SWGROUP_MPCORE 10
-#define TEGRA_SWGROUP_ISP2 11
-#define TEGRA_SWGROUP_XUSB_HOST 12
-#define TEGRA_SWGROUP_XUSB_DEV 13
-#define TEGRA_SWGROUP_ISP2B 14
-#define TEGRA_SWGROUP_TSEC 15
-#define TEGRA_SWGROUP_A9AVP 16
-#define TEGRA_SWGROUP_GPU 17
-#define TEGRA_SWGROUP_SDMMC1A 18
-#define TEGRA_SWGROUP_SDMMC2A 19
-#define TEGRA_SWGROUP_SDMMC3A 20
-#define TEGRA_SWGROUP_SDMMC4A 21
-#define TEGRA_SWGROUP_VIC 22
-#define TEGRA_SWGROUP_VI 23
-#define TEGRA_SWGROUP_NVDEC 24
-#define TEGRA_SWGROUP_APE 25
-#define TEGRA_SWGROUP_NVJPG 26
-#define TEGRA_SWGROUP_SE 27
-#define TEGRA_SWGROUP_AXIAP 28
-#define TEGRA_SWGROUP_ETR 29
-#define TEGRA_SWGROUP_TSECB 30
-
-#endif
diff --git a/include/dt-bindings/memory/tegra30-mc.h b/include/dt-bindings/memory/tegra30-mc.h
deleted file mode 100644
index 502beb0..0000000
--- a/include/dt-bindings/memory/tegra30-mc.h
+++ /dev/null
@@ -1,24 +0,0 @@
-#ifndef DT_BINDINGS_MEMORY_TEGRA30_MC_H
-#define DT_BINDINGS_MEMORY_TEGRA30_MC_H
-
-#define TEGRA_SWGROUP_PTC 0
-#define TEGRA_SWGROUP_DC 1
-#define TEGRA_SWGROUP_DCB 2
-#define TEGRA_SWGROUP_EPP 3
-#define TEGRA_SWGROUP_G2 4
-#define TEGRA_SWGROUP_MPE 5
-#define TEGRA_SWGROUP_VI 6
-#define TEGRA_SWGROUP_AFI 7
-#define TEGRA_SWGROUP_AVPC 8
-#define TEGRA_SWGROUP_NV 9
-#define TEGRA_SWGROUP_NV2 10
-#define TEGRA_SWGROUP_HDA 11
-#define TEGRA_SWGROUP_HC 12
-#define TEGRA_SWGROUP_PPCS 13
-#define TEGRA_SWGROUP_SATA 14
-#define TEGRA_SWGROUP_VDE 15
-#define TEGRA_SWGROUP_MPCORELP 16
-#define TEGRA_SWGROUP_MPCORE 17
-#define TEGRA_SWGROUP_ISP 18
-
-#endif
diff --git a/include/dt-bindings/mfd/st,stpmic1.h b/include/dt-bindings/mfd/st,stpmic1.h
deleted file mode 100644
index b2d6c83..0000000
--- a/include/dt-bindings/mfd/st,stpmic1.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) STMicroelectronics 2018 - All Rights Reserved
- * Author: Philippe Peurichard <philippe.peurichard@st.com>,
- * Pascal Paillet <p.paillet@st.com> for STMicroelectronics.
- */
-
-#ifndef __DT_BINDINGS_STPMIC1_H__
-#define __DT_BINDINGS_STPMIC1_H__
-
-/* IRQ definitions */
-#define IT_PONKEY_F 0
-#define IT_PONKEY_R 1
-#define IT_WAKEUP_F 2
-#define IT_WAKEUP_R 3
-#define IT_VBUS_OTG_F 4
-#define IT_VBUS_OTG_R 5
-#define IT_SWOUT_F 6
-#define IT_SWOUT_R 7
-
-#define IT_CURLIM_BUCK1 8
-#define IT_CURLIM_BUCK2 9
-#define IT_CURLIM_BUCK3 10
-#define IT_CURLIM_BUCK4 11
-#define IT_OCP_OTG 12
-#define IT_OCP_SWOUT 13
-#define IT_OCP_BOOST 14
-#define IT_OVP_BOOST 15
-
-#define IT_CURLIM_LDO1 16
-#define IT_CURLIM_LDO2 17
-#define IT_CURLIM_LDO3 18
-#define IT_CURLIM_LDO4 19
-#define IT_CURLIM_LDO5 20
-#define IT_CURLIM_LDO6 21
-#define IT_SHORT_SWOTG 22
-#define IT_SHORT_SWOUT 23
-
-#define IT_TWARN_F 24
-#define IT_TWARN_R 25
-#define IT_VINLOW_F 26
-#define IT_VINLOW_R 27
-#define IT_SWIN_F 30
-#define IT_SWIN_R 31
-
-#endif /* __DT_BINDINGS_STPMIC1_H__ */
diff --git a/include/dt-bindings/mfd/st-lpc.h b/include/dt-bindings/mfd/st-lpc.h
deleted file mode 100644
index d05894a..0000000
--- a/include/dt-bindings/mfd/st-lpc.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/*
- * This header provides shared DT/Driver defines for ST's LPC device
- *
- * Copyright (C) 2014 STMicroelectronics -- All Rights Reserved
- *
- * Author: Lee Jones <lee.jones@linaro.org> for STMicroelectronics
- */
-
-#ifndef __DT_BINDINGS_ST_LPC_H__
-#define __DT_BINDINGS_ST_LPC_H__
-
-#define ST_LPC_MODE_RTC 0
-#define ST_LPC_MODE_WDT 1
-#define ST_LPC_MODE_CLKSRC 2
-
-#endif /* __DT_BINDINGS_ST_LPC_H__ */
diff --git a/include/dt-bindings/mfd/stm32f4-rcc.h b/include/dt-bindings/mfd/stm32f4-rcc.h
deleted file mode 100644
index 36448a5..0000000
--- a/include/dt-bindings/mfd/stm32f4-rcc.h
+++ /dev/null
@@ -1,108 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * This header provides constants for the STM32F4 RCC IP
- */
-
-#ifndef _DT_BINDINGS_MFD_STM32F4_RCC_H
-#define _DT_BINDINGS_MFD_STM32F4_RCC_H
-
-/* AHB1 */
-#define STM32F4_RCC_AHB1_GPIOA 0
-#define STM32F4_RCC_AHB1_GPIOB 1
-#define STM32F4_RCC_AHB1_GPIOC 2
-#define STM32F4_RCC_AHB1_GPIOD 3
-#define STM32F4_RCC_AHB1_GPIOE 4
-#define STM32F4_RCC_AHB1_GPIOF 5
-#define STM32F4_RCC_AHB1_GPIOG 6
-#define STM32F4_RCC_AHB1_GPIOH 7
-#define STM32F4_RCC_AHB1_GPIOI 8
-#define STM32F4_RCC_AHB1_GPIOJ 9
-#define STM32F4_RCC_AHB1_GPIOK 10
-#define STM32F4_RCC_AHB1_CRC 12
-#define STM32F4_RCC_AHB1_BKPSRAM 18
-#define STM32F4_RCC_AHB1_CCMDATARAM 20
-#define STM32F4_RCC_AHB1_DMA1 21
-#define STM32F4_RCC_AHB1_DMA2 22
-#define STM32F4_RCC_AHB1_DMA2D 23
-#define STM32F4_RCC_AHB1_ETHMAC 25
-#define STM32F4_RCC_AHB1_ETHMACTX 26
-#define STM32F4_RCC_AHB1_ETHMACRX 27
-#define STM32F4_RCC_AHB1_ETHMACPTP 28
-#define STM32F4_RCC_AHB1_OTGHS 29
-#define STM32F4_RCC_AHB1_OTGHSULPI 30
-
-#define STM32F4_AHB1_RESET(bit) (STM32F4_RCC_AHB1_##bit + (0x10 * 8))
-#define STM32F4_AHB1_CLOCK(bit) (STM32F4_RCC_AHB1_##bit)
-
-/* AHB2 */
-#define STM32F4_RCC_AHB2_DCMI 0
-#define STM32F4_RCC_AHB2_CRYP 4
-#define STM32F4_RCC_AHB2_HASH 5
-#define STM32F4_RCC_AHB2_RNG 6
-#define STM32F4_RCC_AHB2_OTGFS 7
-
-#define STM32F4_AHB2_RESET(bit) (STM32F4_RCC_AHB2_##bit + (0x14 * 8))
-#define STM32F4_AHB2_CLOCK(bit) (STM32F4_RCC_AHB2_##bit + 0x20)
-
-/* AHB3 */
-#define STM32F4_RCC_AHB3_FMC 0
-#define STM32F4_RCC_AHB3_QSPI 1
-
-#define STM32F4_AHB3_RESET(bit) (STM32F4_RCC_AHB3_##bit + (0x18 * 8))
-#define STM32F4_AHB3_CLOCK(bit) (STM32F4_RCC_AHB3_##bit + 0x40)
-
-/* APB1 */
-#define STM32F4_RCC_APB1_TIM2 0
-#define STM32F4_RCC_APB1_TIM3 1
-#define STM32F4_RCC_APB1_TIM4 2
-#define STM32F4_RCC_APB1_TIM5 3
-#define STM32F4_RCC_APB1_TIM6 4
-#define STM32F4_RCC_APB1_TIM7 5
-#define STM32F4_RCC_APB1_TIM12 6
-#define STM32F4_RCC_APB1_TIM13 7
-#define STM32F4_RCC_APB1_TIM14 8
-#define STM32F4_RCC_APB1_WWDG 11
-#define STM32F4_RCC_APB1_SPI2 14
-#define STM32F4_RCC_APB1_SPI3 15
-#define STM32F4_RCC_APB1_UART2 17
-#define STM32F4_RCC_APB1_UART3 18
-#define STM32F4_RCC_APB1_UART4 19
-#define STM32F4_RCC_APB1_UART5 20
-#define STM32F4_RCC_APB1_I2C1 21
-#define STM32F4_RCC_APB1_I2C2 22
-#define STM32F4_RCC_APB1_I2C3 23
-#define STM32F4_RCC_APB1_CAN1 25
-#define STM32F4_RCC_APB1_CAN2 26
-#define STM32F4_RCC_APB1_PWR 28
-#define STM32F4_RCC_APB1_DAC 29
-#define STM32F4_RCC_APB1_UART7 30
-#define STM32F4_RCC_APB1_UART8 31
-
-#define STM32F4_APB1_RESET(bit) (STM32F4_RCC_APB1_##bit + (0x20 * 8))
-#define STM32F4_APB1_CLOCK(bit) (STM32F4_RCC_APB1_##bit + 0x80)
-
-/* APB2 */
-#define STM32F4_RCC_APB2_TIM1 0
-#define STM32F4_RCC_APB2_TIM8 1
-#define STM32F4_RCC_APB2_USART1 4
-#define STM32F4_RCC_APB2_USART6 5
-#define STM32F4_RCC_APB2_ADC1 8
-#define STM32F4_RCC_APB2_ADC2 9
-#define STM32F4_RCC_APB2_ADC3 10
-#define STM32F4_RCC_APB2_SDIO 11
-#define STM32F4_RCC_APB2_SPI1 12
-#define STM32F4_RCC_APB2_SPI4 13
-#define STM32F4_RCC_APB2_SYSCFG 14
-#define STM32F4_RCC_APB2_TIM9 16
-#define STM32F4_RCC_APB2_TIM10 17
-#define STM32F4_RCC_APB2_TIM11 18
-#define STM32F4_RCC_APB2_SPI5 20
-#define STM32F4_RCC_APB2_SPI6 21
-#define STM32F4_RCC_APB2_SAI1 22
-#define STM32F4_RCC_APB2_LTDC 26
-#define STM32F4_RCC_APB2_DSI 27
-
-#define STM32F4_APB2_RESET(bit) (STM32F4_RCC_APB2_##bit + (0x24 * 8))
-#define STM32F4_APB2_CLOCK(bit) (STM32F4_RCC_APB2_##bit + 0xA0)
-
-#endif /* _DT_BINDINGS_MFD_STM32F4_RCC_H */
diff --git a/include/dt-bindings/mfd/stm32f7-rcc.h b/include/dt-bindings/mfd/stm32f7-rcc.h
deleted file mode 100644
index c9087f5..0000000
--- a/include/dt-bindings/mfd/stm32f7-rcc.h
+++ /dev/null
@@ -1,114 +0,0 @@
-/*
- * This header provides constants for the STM32F7 RCC IP
- */
-
-#ifndef _DT_BINDINGS_MFD_STM32F7_RCC_H
-#define _DT_BINDINGS_MFD_STM32F7_RCC_H
-
-/* AHB1 */
-#define STM32F7_RCC_AHB1_GPIOA 0
-#define STM32F7_RCC_AHB1_GPIOB 1
-#define STM32F7_RCC_AHB1_GPIOC 2
-#define STM32F7_RCC_AHB1_GPIOD 3
-#define STM32F7_RCC_AHB1_GPIOE 4
-#define STM32F7_RCC_AHB1_GPIOF 5
-#define STM32F7_RCC_AHB1_GPIOG 6
-#define STM32F7_RCC_AHB1_GPIOH 7
-#define STM32F7_RCC_AHB1_GPIOI 8
-#define STM32F7_RCC_AHB1_GPIOJ 9
-#define STM32F7_RCC_AHB1_GPIOK 10
-#define STM32F7_RCC_AHB1_CRC 12
-#define STM32F7_RCC_AHB1_BKPSRAM 18
-#define STM32F7_RCC_AHB1_DTCMRAM 20
-#define STM32F7_RCC_AHB1_DMA1 21
-#define STM32F7_RCC_AHB1_DMA2 22
-#define STM32F7_RCC_AHB1_DMA2D 23
-#define STM32F7_RCC_AHB1_ETHMAC 25
-#define STM32F7_RCC_AHB1_ETHMACTX 26
-#define STM32F7_RCC_AHB1_ETHMACRX 27
-#define STM32FF_RCC_AHB1_ETHMACPTP 28
-#define STM32F7_RCC_AHB1_OTGHS 29
-#define STM32F7_RCC_AHB1_OTGHSULPI 30
-
-#define STM32F7_AHB1_RESET(bit) (STM32F7_RCC_AHB1_##bit + (0x10 * 8))
-#define STM32F7_AHB1_CLOCK(bit) (STM32F7_RCC_AHB1_##bit)
-
-
-/* AHB2 */
-#define STM32F7_RCC_AHB2_DCMI 0
-#define STM32F7_RCC_AHB2_CRYP 4
-#define STM32F7_RCC_AHB2_HASH 5
-#define STM32F7_RCC_AHB2_RNG 6
-#define STM32F7_RCC_AHB2_OTGFS 7
-
-#define STM32F7_AHB2_RESET(bit) (STM32F7_RCC_AHB2_##bit + (0x14 * 8))
-#define STM32F7_AHB2_CLOCK(bit) (STM32F7_RCC_AHB2_##bit + 0x20)
-
-/* AHB3 */
-#define STM32F7_RCC_AHB3_FMC 0
-#define STM32F7_RCC_AHB3_QSPI 1
-
-#define STM32F7_AHB3_RESET(bit) (STM32F7_RCC_AHB3_##bit + (0x18 * 8))
-#define STM32F7_AHB3_CLOCK(bit) (STM32F7_RCC_AHB3_##bit + 0x40)
-
-/* APB1 */
-#define STM32F7_RCC_APB1_TIM2 0
-#define STM32F7_RCC_APB1_TIM3 1
-#define STM32F7_RCC_APB1_TIM4 2
-#define STM32F7_RCC_APB1_TIM5 3
-#define STM32F7_RCC_APB1_TIM6 4
-#define STM32F7_RCC_APB1_TIM7 5
-#define STM32F7_RCC_APB1_TIM12 6
-#define STM32F7_RCC_APB1_TIM13 7
-#define STM32F7_RCC_APB1_TIM14 8
-#define STM32F7_RCC_APB1_LPTIM1 9
-#define STM32F7_RCC_APB1_WWDG 11
-#define STM32F7_RCC_APB1_SPI2 14
-#define STM32F7_RCC_APB1_SPI3 15
-#define STM32F7_RCC_APB1_SPDIFRX 16
-#define STM32F7_RCC_APB1_UART2 17
-#define STM32F7_RCC_APB1_UART3 18
-#define STM32F7_RCC_APB1_UART4 19
-#define STM32F7_RCC_APB1_UART5 20
-#define STM32F7_RCC_APB1_I2C1 21
-#define STM32F7_RCC_APB1_I2C2 22
-#define STM32F7_RCC_APB1_I2C3 23
-#define STM32F7_RCC_APB1_I2C4 24
-#define STM32F7_RCC_APB1_CAN1 25
-#define STM32F7_RCC_APB1_CAN2 26
-#define STM32F7_RCC_APB1_CEC 27
-#define STM32F7_RCC_APB1_PWR 28
-#define STM32F7_RCC_APB1_DAC 29
-#define STM32F7_RCC_APB1_UART7 30
-#define STM32F7_RCC_APB1_UART8 31
-
-#define STM32F7_APB1_RESET(bit) (STM32F7_RCC_APB1_##bit + (0x20 * 8))
-#define STM32F7_APB1_CLOCK(bit) (STM32F7_RCC_APB1_##bit + 0x80)
-
-/* APB2 */
-#define STM32F7_RCC_APB2_TIM1 0
-#define STM32F7_RCC_APB2_TIM8 1
-#define STM32F7_RCC_APB2_USART1 4
-#define STM32F7_RCC_APB2_USART6 5
-#define STM32F7_RCC_APB2_SDMMC2 7
-#define STM32F7_RCC_APB2_ADC1 8
-#define STM32F7_RCC_APB2_ADC2 9
-#define STM32F7_RCC_APB2_ADC3 10
-#define STM32F7_RCC_APB2_SDMMC1 11
-#define STM32F7_RCC_APB2_SPI1 12
-#define STM32F7_RCC_APB2_SPI4 13
-#define STM32F7_RCC_APB2_SYSCFG 14
-#define STM32F7_RCC_APB2_TIM9 16
-#define STM32F7_RCC_APB2_TIM10 17
-#define STM32F7_RCC_APB2_TIM11 18
-#define STM32F7_RCC_APB2_SPI5 20
-#define STM32F7_RCC_APB2_SPI6 21
-#define STM32F7_RCC_APB2_SAI1 22
-#define STM32F7_RCC_APB2_SAI2 23
-#define STM32F7_RCC_APB2_LTDC 26
-#define STM32F7_RCC_APB2_DSI 27
-
-#define STM32F7_APB2_RESET(bit) (STM32F7_RCC_APB2_##bit + (0x24 * 8))
-#define STM32F7_APB2_CLOCK(bit) (STM32F7_RCC_APB2_##bit + 0xA0)
-
-#endif /* _DT_BINDINGS_MFD_STM32F7_RCC_H */
diff --git a/include/dt-bindings/mfd/stm32h7-rcc.h b/include/dt-bindings/mfd/stm32h7-rcc.h
deleted file mode 100644
index b96b3c3..0000000
--- a/include/dt-bindings/mfd/stm32h7-rcc.h
+++ /dev/null
@@ -1,138 +0,0 @@
-/*
- * This header provides constants for the STM32H7 RCC IP
- */
-
-#ifndef _DT_BINDINGS_MFD_STM32H7_RCC_H
-#define _DT_BINDINGS_MFD_STM32H7_RCC_H
-
-/* AHB3 */
-#define STM32H7_RCC_AHB3_MDMA 0
-#define STM32H7_RCC_AHB3_DMA2D 4
-#define STM32H7_RCC_AHB3_JPGDEC 5
-#define STM32H7_RCC_AHB3_FMC 12
-#define STM32H7_RCC_AHB3_QUADSPI 14
-#define STM32H7_RCC_AHB3_SDMMC1 16
-#define STM32H7_RCC_AHB3_CPU1 31
-
-#define STM32H7_AHB3_RESET(bit) (STM32H7_RCC_AHB3_##bit + (0x7C * 8))
-
-/* AHB1 */
-#define STM32H7_RCC_AHB1_DMA1 0
-#define STM32H7_RCC_AHB1_DMA2 1
-#define STM32H7_RCC_AHB1_ADC12 5
-#define STM32H7_RCC_AHB1_ART 14
-#define STM32H7_RCC_AHB1_ETH1MAC 15
-#define STM32H7_RCC_AHB1_USB1OTG 25
-#define STM32H7_RCC_AHB1_USB2OTG 27
-#define STM32H7_RCC_AHB1_CPU2 31
-
-#define STM32H7_AHB1_RESET(bit) (STM32H7_RCC_AHB1_##bit + (0x80 * 8))
-
-/* AHB2 */
-#define STM32H7_RCC_AHB2_CAMITF 0
-#define STM32H7_RCC_AHB2_CRYPT 4
-#define STM32H7_RCC_AHB2_HASH 5
-#define STM32H7_RCC_AHB2_RNG 6
-#define STM32H7_RCC_AHB2_SDMMC2 9
-
-#define STM32H7_AHB2_RESET(bit) (STM32H7_RCC_AHB2_##bit + (0x84 * 8))
-
-/* AHB4 */
-#define STM32H7_RCC_AHB4_GPIOA 0
-#define STM32H7_RCC_AHB4_GPIOB 1
-#define STM32H7_RCC_AHB4_GPIOC 2
-#define STM32H7_RCC_AHB4_GPIOD 3
-#define STM32H7_RCC_AHB4_GPIOE 4
-#define STM32H7_RCC_AHB4_GPIOF 5
-#define STM32H7_RCC_AHB4_GPIOG 6
-#define STM32H7_RCC_AHB4_GPIOH 7
-#define STM32H7_RCC_AHB4_GPIOI 8
-#define STM32H7_RCC_AHB4_GPIOJ 9
-#define STM32H7_RCC_AHB4_GPIOK 10
-#define STM32H7_RCC_AHB4_CRC 19
-#define STM32H7_RCC_AHB4_BDMA 21
-#define STM32H7_RCC_AHB4_ADC3 24
-#define STM32H7_RCC_AHB4_HSEM 25
-
-#define STM32H7_AHB4_RESET(bit) (STM32H7_RCC_AHB4_##bit + (0x88 * 8))
-
-
-/* APB3 */
-#define STM32H7_RCC_APB3_LTDC 3
-#define STM32H7_RCC_APB3_DSI 4
-
-#define STM32H7_APB3_RESET(bit) (STM32H7_RCC_APB3_##bit + (0x8C * 8))
-
-/* APB1L */
-#define STM32H7_RCC_APB1L_TIM2 0
-#define STM32H7_RCC_APB1L_TIM3 1
-#define STM32H7_RCC_APB1L_TIM4 2
-#define STM32H7_RCC_APB1L_TIM5 3
-#define STM32H7_RCC_APB1L_TIM6 4
-#define STM32H7_RCC_APB1L_TIM7 5
-#define STM32H7_RCC_APB1L_TIM12 6
-#define STM32H7_RCC_APB1L_TIM13 7
-#define STM32H7_RCC_APB1L_TIM14 8
-#define STM32H7_RCC_APB1L_LPTIM1 9
-#define STM32H7_RCC_APB1L_SPI2 14
-#define STM32H7_RCC_APB1L_SPI3 15
-#define STM32H7_RCC_APB1L_SPDIF_RX 16
-#define STM32H7_RCC_APB1L_USART2 17
-#define STM32H7_RCC_APB1L_USART3 18
-#define STM32H7_RCC_APB1L_UART4 19
-#define STM32H7_RCC_APB1L_UART5 20
-#define STM32H7_RCC_APB1L_I2C1 21
-#define STM32H7_RCC_APB1L_I2C2 22
-#define STM32H7_RCC_APB1L_I2C3 23
-#define STM32H7_RCC_APB1L_HDMICEC 27
-#define STM32H7_RCC_APB1L_DAC12 29
-#define STM32H7_RCC_APB1L_USART7 30
-#define STM32H7_RCC_APB1L_USART8 31
-
-#define STM32H7_APB1L_RESET(bit) (STM32H7_RCC_APB1L_##bit + (0x90 * 8))
-
-/* APB1H */
-#define STM32H7_RCC_APB1H_CRS 1
-#define STM32H7_RCC_APB1H_SWP 2
-#define STM32H7_RCC_APB1H_OPAMP 4
-#define STM32H7_RCC_APB1H_MDIOS 5
-#define STM32H7_RCC_APB1H_FDCAN 8
-
-#define STM32H7_APB1H_RESET(bit) (STM32H7_RCC_APB1H_##bit + (0x94 * 8))
-
-/* APB2 */
-#define STM32H7_RCC_APB2_TIM1 0
-#define STM32H7_RCC_APB2_TIM8 1
-#define STM32H7_RCC_APB2_USART1 4
-#define STM32H7_RCC_APB2_USART6 5
-#define STM32H7_RCC_APB2_SPI1 12
-#define STM32H7_RCC_APB2_SPI4 13
-#define STM32H7_RCC_APB2_TIM15 16
-#define STM32H7_RCC_APB2_TIM16 17
-#define STM32H7_RCC_APB2_TIM17 18
-#define STM32H7_RCC_APB2_SPI5 20
-#define STM32H7_RCC_APB2_SAI1 22
-#define STM32H7_RCC_APB2_SAI2 23
-#define STM32H7_RCC_APB2_SAI3 24
-#define STM32H7_RCC_APB2_DFSDM1 28
-#define STM32H7_RCC_APB2_HRTIM 29
-
-#define STM32H7_APB2_RESET(bit) (STM32H7_RCC_APB2_##bit + (0x98 * 8))
-
-/* APB4 */
-#define STM32H7_RCC_APB4_SYSCFG 1
-#define STM32H7_RCC_APB4_LPUART1 3
-#define STM32H7_RCC_APB4_SPI6 5
-#define STM32H7_RCC_APB4_I2C4 7
-#define STM32H7_RCC_APB4_LPTIM2 9
-#define STM32H7_RCC_APB4_LPTIM3 10
-#define STM32H7_RCC_APB4_LPTIM4 11
-#define STM32H7_RCC_APB4_LPTIM5 12
-#define STM32H7_RCC_APB4_COMP12 14
-#define STM32H7_RCC_APB4_VREF 15
-#define STM32H7_RCC_APB4_SAI4 21
-#define STM32H7_RCC_APB4_TMPSENS 26
-
-#define STM32H7_APB4_RESET(bit) (STM32H7_RCC_APB4_##bit + (0x9C * 8))
-
-#endif /* _DT_BINDINGS_MFD_STM32H7_RCC_H */
diff --git a/include/dt-bindings/mrc/quark.h b/include/dt-bindings/mrc/quark.h
deleted file mode 100644
index c763e74..0000000
--- a/include/dt-bindings/mrc/quark.h
+++ /dev/null
@@ -1,82 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
- *
- * Intel Quark MRC bindings include several properties
- * as part of an Intel Quark MRC node. In most cases,
- * the value of these properties uses the standard values
- * defined in this header.
- */
-
-#ifndef _DT_BINDINGS_QRK_MRC_H_
-#define _DT_BINDINGS_QRK_MRC_H_
-
-/* MRC platform data flags */
-#define MRC_FLAG_ECC_EN 0x00000001
-#define MRC_FLAG_SCRAMBLE_EN 0x00000002
-#define MRC_FLAG_MEMTEST_EN 0x00000004
-/* 0b DDR "fly-by" topology else 1b DDR "tree" topology */
-#define MRC_FLAG_TOP_TREE_EN 0x00000008
-/* If set ODR signal is asserted to DRAM devices on writes */
-#define MRC_FLAG_WR_ODT_EN 0x00000010
-
-/* DRAM width */
-#define DRAM_WIDTH_X8 0
-#define DRAM_WIDTH_X16 1
-#define DRAM_WIDTH_X32 2
-
-/* DRAM speed */
-#define DRAM_FREQ_800 0
-#define DRAM_FREQ_1066 1
-
-/* DRAM type */
-#define DRAM_TYPE_DDR3 0
-#define DRAM_TYPE_DDR3L 1
-
-/* DRAM rank mask */
-#define DRAM_RANK(n) (1 << (n))
-
-/* DRAM channel mask */
-#define DRAM_CHANNEL(n) (1 << (n))
-
-/* DRAM channel width */
-#define DRAM_CHANNEL_WIDTH_X8 0
-#define DRAM_CHANNEL_WIDTH_X16 1
-#define DRAM_CHANNEL_WIDTH_X32 2
-
-/* DRAM address mode */
-#define DRAM_ADDR_MODE0 0
-#define DRAM_ADDR_MODE1 1
-#define DRAM_ADDR_MODE2 2
-
-/* DRAM refresh rate */
-#define DRAM_REFRESH_RATE_195US 1
-#define DRAM_REFRESH_RATE_39US 2
-#define DRAM_REFRESH_RATE_785US 3
-
-/* DRAM SR temprature range */
-#define DRAM_SRT_RANGE_NORMAL 0
-#define DRAM_SRT_RANGE_EXTENDED 1
-
-/* DRAM ron value */
-#define DRAM_RON_34OHM 0
-#define DRAM_RON_40OHM 1
-
-/* DRAM rtt nom value */
-#define DRAM_RTT_NOM_40OHM 0
-#define DRAM_RTT_NOM_60OHM 1
-#define DRAM_RTT_NOM_120OHM 2
-
-/* DRAM rd odt value */
-#define DRAM_RD_ODT_OFF 0
-#define DRAM_RD_ODT_60OHM 1
-#define DRAM_RD_ODT_120OHM 2
-#define DRAM_RD_ODT_180OHM 3
-
-/* DRAM density */
-#define DRAM_DENSITY_512M 0
-#define DRAM_DENSITY_1G 1
-#define DRAM_DENSITY_2G 2
-#define DRAM_DENSITY_4G 3
-
-#endif /* _DT_BINDINGS_QRK_MRC_H_ */
diff --git a/include/dt-bindings/mscc/jr2_data.h b/include/dt-bindings/mscc/jr2_data.h
deleted file mode 100644
index 2f06fc5..0000000
--- a/include/dt-bindings/mscc/jr2_data.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
-/*
- * Copyright (c) 2018 Microsemi Corporation
- */
-
-#ifndef _JR2_DATA_H_
-#define _JR2_DATA_H_
-
-#define SERDES1G(x) (x)
-#define SERDES1G_MAX SERDES1G(10)
-#define SERDES6G(x) (SERDES1G_MAX + 1 + (x))
-#define SERDES6G_MAX SERDES6G(17)
-#define SERDES_MAX (SERDES6G_MAX + 1)
-
-/* similar with phy_interface_t */
-#define PHY_MODE_SGMII 2
-#define PHY_MODE_QSGMII 4
-
-#endif
diff --git a/include/dt-bindings/mscc/luton_data.h b/include/dt-bindings/mscc/luton_data.h
deleted file mode 100644
index e488567..0000000
--- a/include/dt-bindings/mscc/luton_data.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
-/*
- * Copyright (c) 2019 Microsemi Corporation
- */
-
-#ifndef _LUTON_DATA_H_
-#define _LUTON_DATA_H_
-
-#define SERDES6G(x) (x)
-#define SERDES6G_MAX SERDES6G(5)
-#define SERDES_MAX (SERDES6G_MAX)
-
-/* similar with phy_interface_t */
-#define PHY_MODE_SGMII 2
-#define PHY_MODE_QSGMII 4
-
-#endif
diff --git a/include/dt-bindings/mscc/ocelot_data.h b/include/dt-bindings/mscc/ocelot_data.h
deleted file mode 100644
index 7a5a1bf..0000000
--- a/include/dt-bindings/mscc/ocelot_data.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
-/*
- * Copyright (c) 2019 Microsemi Corporation
- */
-
-#ifndef _OCELOT_DATA_H_
-#define _OCELOT_DATA_H_
-
-#define SERDES1G(x) (x)
-#define SERDES1G_MAX SERDES1G(7)
-#define SERDES6G(x) (SERDES1G_MAX + 1 + (x))
-#define SERDES6G_MAX SERDES6G(11)
-#define SERDES_MAX (SERDES6G_MAX + 1)
-
-/* similar with phy_interface_t */
-#define PHY_MODE_SGMII 2
-#define PHY_MODE_QSGMII 4
-
-#endif
diff --git a/include/dt-bindings/mscc/serval_data.h b/include/dt-bindings/mscc/serval_data.h
deleted file mode 100644
index b374fda..0000000
--- a/include/dt-bindings/mscc/serval_data.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
-/*
- * Copyright (c) 2018 Microsemi Corporation
- */
-
-#ifndef _SERVAL_DATA_H_
-#define _SERVAL_DATA_H_
-
-#define SERDES1G(x) (x)
-#define SERDES1G_MAX SERDES1G(9)
-#define SERDES6G(x) (SERDES1G_MAX + 1 + (x))
-#define SERDES6G_MAX SERDES6G(11)
-#define SERDES_MAX (SERDES6G_MAX + 1)
-
-/* similar with phy_interface_t */
-#define PHY_MODE_SGMII 2
-#define PHY_MODE_QSGMII 4
-
-#endif
diff --git a/include/dt-bindings/net/microchip-lan78xx.h b/include/dt-bindings/net/microchip-lan78xx.h
deleted file mode 100644
index 0742ff0..0000000
--- a/include/dt-bindings/net/microchip-lan78xx.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _DT_BINDINGS_MICROCHIP_LAN78XX_H
-#define _DT_BINDINGS_MICROCHIP_LAN78XX_H
-
-/* LED modes for LAN7800/LAN7850 embedded PHY */
-
-#define LAN78XX_LINK_ACTIVITY 0
-#define LAN78XX_LINK_1000_ACTIVITY 1
-#define LAN78XX_LINK_100_ACTIVITY 2
-#define LAN78XX_LINK_10_ACTIVITY 3
-#define LAN78XX_LINK_100_1000_ACTIVITY 4
-#define LAN78XX_LINK_10_1000_ACTIVITY 5
-#define LAN78XX_LINK_10_100_ACTIVITY 6
-#define LAN78XX_DUPLEX_COLLISION 8
-#define LAN78XX_COLLISION 9
-#define LAN78XX_ACTIVITY 10
-#define LAN78XX_AUTONEG_FAULT 12
-#define LAN78XX_FORCE_LED_OFF 14
-#define LAN78XX_FORCE_LED_ON 15
-
-#endif
diff --git a/include/dt-bindings/net/ti-dp83867.h b/include/dt-bindings/net/ti-dp83867.h
deleted file mode 100644
index 85d08f6..0000000
--- a/include/dt-bindings/net/ti-dp83867.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * TI DP83867 PHY drivers
- *
- */
-
-#ifndef _DT_BINDINGS_TI_DP83867_H
-#define _DT_BINDINGS_TI_DP83867_H
-
-/* PHY CTRL bits */
-#define DP83867_PHYCR_FIFO_DEPTH_3_B_NIB 0x00
-#define DP83867_PHYCR_FIFO_DEPTH_4_B_NIB 0x01
-#define DP83867_PHYCR_FIFO_DEPTH_6_B_NIB 0x02
-#define DP83867_PHYCR_FIFO_DEPTH_8_B_NIB 0x03
-
-/* RGMIIDCTL internal delay for rx and tx */
-#define DP83867_RGMIIDCTL_250_PS 0x0
-#define DP83867_RGMIIDCTL_500_PS 0x1
-#define DP83867_RGMIIDCTL_750_PS 0x2
-#define DP83867_RGMIIDCTL_1_NS 0x3
-#define DP83867_RGMIIDCTL_1_25_NS 0x4
-#define DP83867_RGMIIDCTL_1_50_NS 0x5
-#define DP83867_RGMIIDCTL_1_75_NS 0x6
-#define DP83867_RGMIIDCTL_2_00_NS 0x7
-#define DP83867_RGMIIDCTL_2_25_NS 0x8
-#define DP83867_RGMIIDCTL_2_50_NS 0x9
-#define DP83867_RGMIIDCTL_2_75_NS 0xa
-#define DP83867_RGMIIDCTL_3_00_NS 0xb
-#define DP83867_RGMIIDCTL_3_25_NS 0xc
-#define DP83867_RGMIIDCTL_3_50_NS 0xd
-#define DP83867_RGMIIDCTL_3_75_NS 0xe
-#define DP83867_RGMIIDCTL_4_00_NS 0xf
-
-/* IO_MUX_CFG - Clock output selection */
-#define DP83867_CLK_O_SEL_CHN_A_RCLK 0x0
-#define DP83867_CLK_O_SEL_CHN_B_RCLK 0x1
-#define DP83867_CLK_O_SEL_CHN_C_RCLK 0x2
-#define DP83867_CLK_O_SEL_CHN_D_RCLK 0x3
-#define DP83867_CLK_O_SEL_CHN_A_RCLK_DIV5 0x4
-#define DP83867_CLK_O_SEL_CHN_B_RCLK_DIV5 0x5
-#define DP83867_CLK_O_SEL_CHN_C_RCLK_DIV5 0x6
-#define DP83867_CLK_O_SEL_CHN_D_RCLK_DIV5 0x7
-#define DP83867_CLK_O_SEL_CHN_A_TCLK 0x8
-#define DP83867_CLK_O_SEL_CHN_B_TCLK 0x9
-#define DP83867_CLK_O_SEL_CHN_C_TCLK 0xA
-#define DP83867_CLK_O_SEL_CHN_D_TCLK 0xB
-#define DP83867_CLK_O_SEL_REF_CLK 0xC
-
-#endif
diff --git a/include/dt-bindings/phy/phy-am654-serdes.h b/include/dt-bindings/phy/phy-am654-serdes.h
deleted file mode 100644
index e8d9017..0000000
--- a/include/dt-bindings/phy/phy-am654-serdes.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * This header provides constants for AM654 SERDES.
- */
-
-#ifndef _DT_BINDINGS_AM654_SERDES
-#define _DT_BINDINGS_AM654_SERDES
-
-#define AM654_SERDES_CMU_REFCLK 0
-#define AM654_SERDES_LO_REFCLK 1
-#define AM654_SERDES_RO_REFCLK 2
-
-#endif /* _DT_BINDINGS_AM654_SERDES */
diff --git a/include/dt-bindings/phy/phy.h b/include/dt-bindings/phy/phy.h
deleted file mode 100644
index 6c90193..0000000
--- a/include/dt-bindings/phy/phy.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- *
- * This header provides constants for the phy framework
- *
- * Copyright (C) 2014 STMicroelectronics
- * Author: Gabriel Fernandez <gabriel.fernandez@st.com>
- * License terms: GNU General Public License (GPL), version 2
- */
-
-#ifndef _DT_BINDINGS_PHY
-#define _DT_BINDINGS_PHY
-
-#define PHY_NONE 0
-#define PHY_TYPE_SATA 1
-#define PHY_TYPE_PCIE 2
-#define PHY_TYPE_USB2 3
-#define PHY_TYPE_USB3 4
-
-#endif /* _DT_BINDINGS_PHY */
diff --git a/include/dt-bindings/pinctrl/am33xx.h b/include/dt-bindings/pinctrl/am33xx.h
deleted file mode 100644
index 226f772..0000000
--- a/include/dt-bindings/pinctrl/am33xx.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * This header provides constants specific to AM33XX pinctrl bindings.
- */
-
-#ifndef _DT_BINDINGS_PINCTRL_AM33XX_H
-#define _DT_BINDINGS_PINCTRL_AM33XX_H
-
-#include <dt-bindings/pinctrl/omap.h>
-
-/* am33xx specific mux bit defines */
-#undef PULL_ENA
-#undef INPUT_EN
-
-#define PULL_DISABLE (1 << 3)
-#define INPUT_EN (1 << 5)
-#define SLEWCTRL_SLOW (1 << 6)
-#define SLEWCTRL_FAST 0
-
-/* update macro depending on INPUT_EN and PULL_ENA */
-#undef PIN_OUTPUT
-#undef PIN_OUTPUT_PULLUP
-#undef PIN_OUTPUT_PULLDOWN
-#undef PIN_INPUT
-#undef PIN_INPUT_PULLUP
-#undef PIN_INPUT_PULLDOWN
-
-#define PIN_OUTPUT (PULL_DISABLE)
-#define PIN_OUTPUT_PULLUP (PULL_UP)
-#define PIN_OUTPUT_PULLDOWN 0
-#define PIN_INPUT (INPUT_EN | PULL_DISABLE)
-#define PIN_INPUT_PULLUP (INPUT_EN | PULL_UP)
-#define PIN_INPUT_PULLDOWN (INPUT_EN)
-
-/* undef non-existing modes */
-#undef PIN_OFF_NONE
-#undef PIN_OFF_OUTPUT_HIGH
-#undef PIN_OFF_OUTPUT_LOW
-#undef PIN_OFF_INPUT_PULLUP
-#undef PIN_OFF_INPUT_PULLDOWN
-#undef PIN_OFF_WAKEUPENABLE
-
-#endif
-
diff --git a/include/dt-bindings/pinctrl/am43xx.h b/include/dt-bindings/pinctrl/am43xx.h
deleted file mode 100644
index 292c2eb..0000000
--- a/include/dt-bindings/pinctrl/am43xx.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * This header provides constants specific to AM43XX pinctrl bindings.
- */
-
-#ifndef _DT_BINDINGS_PINCTRL_AM43XX_H
-#define _DT_BINDINGS_PINCTRL_AM43XX_H
-
-#define MUX_MODE0 0
-#define MUX_MODE1 1
-#define MUX_MODE2 2
-#define MUX_MODE3 3
-#define MUX_MODE4 4
-#define MUX_MODE5 5
-#define MUX_MODE6 6
-#define MUX_MODE7 7
-#define MUX_MODE8 8
-
-#define PULL_DISABLE (1 << 16)
-#define PULL_UP (1 << 17)
-#define INPUT_EN (1 << 18)
-#define SLEWCTRL_SLOW (1 << 19)
-#define SLEWCTRL_FAST 0
-#define DS0_PULL_UP_DOWN_EN (1 << 27)
-#define WAKEUP_ENABLE (1 << 29)
-
-#define PIN_OUTPUT (PULL_DISABLE)
-#define PIN_OUTPUT_PULLUP (PULL_UP)
-#define PIN_OUTPUT_PULLDOWN 0
-#define PIN_INPUT (INPUT_EN | PULL_DISABLE)
-#define PIN_INPUT_PULLUP (INPUT_EN | PULL_UP)
-#define PIN_INPUT_PULLDOWN (INPUT_EN)
-
-/*
- * Macro to allow using the absolute physical address instead of the
- * padconf registers instead of the offset from padconf base.
- */
-#define AM4372_IOPAD(pa, val) (((pa) & 0xffff) - 0x0800) (val)
-
-#endif
diff --git a/include/dt-bindings/pinctrl/at91.h b/include/dt-bindings/pinctrl/at91.h
deleted file mode 100644
index 616f5ce..0000000
--- a/include/dt-bindings/pinctrl/at91.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * This header provides constants for most at91 pinctrl bindings.
- *
- * Copyright (C) 2013 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
- *
- * GPLv2 only
- */
-
-#ifndef __DT_BINDINGS_AT91_PINCTRL_H__
-#define __DT_BINDINGS_AT91_PINCTRL_H__
-
-#define AT91_PINCTRL_NONE (0 << 0)
-#define AT91_PINCTRL_PULL_UP (1 << 0)
-#define AT91_PINCTRL_MULTI_DRIVE (1 << 1)
-#define AT91_PINCTRL_DEGLITCH (1 << 2)
-#define AT91_PINCTRL_PULL_DOWN (1 << 3)
-#define AT91_PINCTRL_DIS_SCHMIT (1 << 4)
-#define AT91_PINCTRL_OUTPUT (1 << 7)
-#define AT91_PINCTRL_OUTPUT_VAL(x) ((x & 0x1) << 8)
-#define AT91_PINCTRL_SLEWRATE (1 << 9)
-#define AT91_PINCTRL_DEBOUNCE (1 << 16)
-#define AT91_PINCTRL_DEBOUNCE_VAL(x) (x << 17)
-
-#define AT91_PINCTRL_PULL_UP_DEGLITCH (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DEGLITCH)
-
-#define AT91_PINCTRL_DRIVE_STRENGTH_DEFAULT (0x0 << 5)
-#define AT91_PINCTRL_DRIVE_STRENGTH_LOW (0x1 << 5)
-#define AT91_PINCTRL_DRIVE_STRENGTH_MED (0x2 << 5)
-#define AT91_PINCTRL_DRIVE_STRENGTH_HI (0x3 << 5)
-
-#define AT91_PINCTRL_SLEWRATE_DIS (0x0 << 9)
-#define AT91_PINCTRL_SLEWRATE_ENA (0x1 << 9)
-
-#define AT91_PIOA 0
-#define AT91_PIOB 1
-#define AT91_PIOC 2
-#define AT91_PIOD 3
-#define AT91_PIOE 4
-
-#define AT91_PERIPH_GPIO 0
-#define AT91_PERIPH_A 1
-#define AT91_PERIPH_B 2
-#define AT91_PERIPH_C 3
-#define AT91_PERIPH_D 4
-
-#endif /* __DT_BINDINGS_AT91_PINCTRL_H__ */
diff --git a/include/dt-bindings/pinctrl/bcm2835.h b/include/dt-bindings/pinctrl/bcm2835.h
deleted file mode 100644
index b5b2654..0000000
--- a/include/dt-bindings/pinctrl/bcm2835.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Header providing constants for bcm2835 pinctrl bindings.
- *
- * Copyright (C) 2015 Stefan Wahren <stefan.wahren@i2se.com>
- */
-
-#ifndef __DT_BINDINGS_PINCTRL_BCM2835_H__
-#define __DT_BINDINGS_PINCTRL_BCM2835_H__
-
-/* brcm,function property */
-#define BCM2835_FSEL_GPIO_IN 0
-#define BCM2835_FSEL_GPIO_OUT 1
-#define BCM2835_FSEL_ALT5 2
-#define BCM2835_FSEL_ALT4 3
-#define BCM2835_FSEL_ALT0 4
-#define BCM2835_FSEL_ALT1 5
-#define BCM2835_FSEL_ALT2 6
-#define BCM2835_FSEL_ALT3 7
-
-/* brcm,pull property */
-#define BCM2835_PUD_OFF 0
-#define BCM2835_PUD_DOWN 1
-#define BCM2835_PUD_UP 2
-
-#endif /* __DT_BINDINGS_PINCTRL_BCM2835_H__ */
diff --git a/include/dt-bindings/pinctrl/dra.h b/include/dt-bindings/pinctrl/dra.h
deleted file mode 100644
index 18ec5df..0000000
--- a/include/dt-bindings/pinctrl/dra.h
+++ /dev/null
@@ -1,80 +0,0 @@
-/*
- * This header provides constants for DRA pinctrl bindings.
- *
- * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
- * Author: Rajendra Nayak <rnayak@ti.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef _DT_BINDINGS_PINCTRL_DRA_H
-#define _DT_BINDINGS_PINCTRL_DRA_H
-
-/* DRA7 mux mode options for each pin. See TRM for options */
-#define MUX_MODE0 0x0
-#define MUX_MODE1 0x1
-#define MUX_MODE2 0x2
-#define MUX_MODE3 0x3
-#define MUX_MODE4 0x4
-#define MUX_MODE5 0x5
-#define MUX_MODE6 0x6
-#define MUX_MODE7 0x7
-#define MUX_MODE8 0x8
-#define MUX_MODE9 0x9
-#define MUX_MODE10 0xa
-#define MUX_MODE11 0xb
-#define MUX_MODE12 0xc
-#define MUX_MODE13 0xd
-#define MUX_MODE14 0xe
-#define MUX_MODE15 0xf
-
-/* Certain pins need virtual mode, but note: they may glitch */
-#define MUX_VIRTUAL_MODE0 (MODE_SELECT | (0x0 << 4))
-#define MUX_VIRTUAL_MODE1 (MODE_SELECT | (0x1 << 4))
-#define MUX_VIRTUAL_MODE2 (MODE_SELECT | (0x2 << 4))
-#define MUX_VIRTUAL_MODE3 (MODE_SELECT | (0x3 << 4))
-#define MUX_VIRTUAL_MODE4 (MODE_SELECT | (0x4 << 4))
-#define MUX_VIRTUAL_MODE5 (MODE_SELECT | (0x5 << 4))
-#define MUX_VIRTUAL_MODE6 (MODE_SELECT | (0x6 << 4))
-#define MUX_VIRTUAL_MODE7 (MODE_SELECT | (0x7 << 4))
-#define MUX_VIRTUAL_MODE8 (MODE_SELECT | (0x8 << 4))
-#define MUX_VIRTUAL_MODE9 (MODE_SELECT | (0x9 << 4))
-#define MUX_VIRTUAL_MODE10 (MODE_SELECT | (0xa << 4))
-#define MUX_VIRTUAL_MODE11 (MODE_SELECT | (0xb << 4))
-#define MUX_VIRTUAL_MODE12 (MODE_SELECT | (0xc << 4))
-#define MUX_VIRTUAL_MODE13 (MODE_SELECT | (0xd << 4))
-#define MUX_VIRTUAL_MODE14 (MODE_SELECT | (0xe << 4))
-#define MUX_VIRTUAL_MODE15 (MODE_SELECT | (0xf << 4))
-
-#define MODE_SELECT (1 << 8)
-
-#define PULL_ENA (0 << 16)
-#define PULL_DIS (1 << 16)
-#define PULL_UP (1 << 17)
-#define INPUT_EN (1 << 18)
-#define SLEWCONTROL (1 << 19)
-#define WAKEUP_EN (1 << 24)
-#define WAKEUP_EVENT (1 << 25)
-
-/* Active pin states */
-#define PIN_OUTPUT (0 | PULL_DIS)
-#define PIN_OUTPUT_PULLUP (PULL_UP)
-#define PIN_OUTPUT_PULLDOWN (0)
-#define PIN_INPUT (INPUT_EN | PULL_DIS)
-#define PIN_INPUT_SLEW (INPUT_EN | SLEWCONTROL)
-#define PIN_INPUT_PULLUP (PULL_ENA | INPUT_EN | PULL_UP)
-#define PIN_INPUT_PULLDOWN (PULL_ENA | INPUT_EN)
-
-/*
- * Macro to allow using the absolute physical address instead of the
- * padconf registers instead of the offset from padconf base.
- */
-#define DRA7XX_CORE_IOPAD(pa, val) (((pa) & 0xffff) - 0x3400) (val)
-
-/* DRA7 IODELAY configuration parameters */
-#define A_DELAY_PS(val) ((val) & 0xffff)
-#define G_DELAY_PS(val) ((val) & 0xffff)
-#endif
-
diff --git a/include/dt-bindings/pinctrl/hisi.h b/include/dt-bindings/pinctrl/hisi.h
deleted file mode 100644
index 0359bfd..0000000
--- a/include/dt-bindings/pinctrl/hisi.h
+++ /dev/null
@@ -1,74 +0,0 @@
-/*
- * This header provides constants for hisilicon pinctrl bindings.
- *
- * Copyright (c) 2015 Hisilicon Limited.
- * Copyright (c) 2015 Linaro Limited.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef _DT_BINDINGS_PINCTRL_HISI_H
-#define _DT_BINDINGS_PINCTRL_HISI_H
-
-/* iomg bit definition */
-#define MUX_M0 0
-#define MUX_M1 1
-#define MUX_M2 2
-#define MUX_M3 3
-#define MUX_M4 4
-#define MUX_M5 5
-#define MUX_M6 6
-#define MUX_M7 7
-
-/* iocg bit definition */
-#define PULL_MASK (3)
-#define PULL_DIS (0)
-#define PULL_UP (1 << 0)
-#define PULL_DOWN (1 << 1)
-
-/* drive strength definition */
-#define DRIVE_MASK (7 << 4)
-#define DRIVE1_02MA (0 << 4)
-#define DRIVE1_04MA (1 << 4)
-#define DRIVE1_08MA (2 << 4)
-#define DRIVE1_10MA (3 << 4)
-#define DRIVE2_02MA (0 << 4)
-#define DRIVE2_04MA (1 << 4)
-#define DRIVE2_08MA (2 << 4)
-#define DRIVE2_10MA (3 << 4)
-#define DRIVE3_04MA (0 << 4)
-#define DRIVE3_08MA (1 << 4)
-#define DRIVE3_12MA (2 << 4)
-#define DRIVE3_16MA (3 << 4)
-#define DRIVE3_20MA (4 << 4)
-#define DRIVE3_24MA (5 << 4)
-#define DRIVE3_32MA (6 << 4)
-#define DRIVE3_40MA (7 << 4)
-#define DRIVE4_02MA (0 << 4)
-#define DRIVE4_04MA (2 << 4)
-#define DRIVE4_08MA (4 << 4)
-#define DRIVE4_10MA (6 << 4)
-
-/* drive strength definition for hi3660 */
-#define DRIVE6_MASK (15 << 4)
-#define DRIVE6_04MA (0 << 4)
-#define DRIVE6_12MA (4 << 4)
-#define DRIVE6_19MA (8 << 4)
-#define DRIVE6_27MA (10 << 4)
-#define DRIVE6_32MA (15 << 4)
-#define DRIVE7_02MA (0 << 4)
-#define DRIVE7_04MA (1 << 4)
-#define DRIVE7_06MA (2 << 4)
-#define DRIVE7_08MA (3 << 4)
-#define DRIVE7_10MA (4 << 4)
-#define DRIVE7_12MA (5 << 4)
-#define DRIVE7_14MA (6 << 4)
-#define DRIVE7_16MA (7 << 4)
-#endif
diff --git a/include/dt-bindings/pinctrl/k3.h b/include/dt-bindings/pinctrl/k3.h
deleted file mode 100644
index ce0cd38..0000000
--- a/include/dt-bindings/pinctrl/k3.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * This header provides constants for TI K3-AM65 pinctrl bindings.
- *
- * Copyright (C) 2018 Texas Instruments
- */
-#ifndef _DT_BINDINGS_PINCTRL_TI_K3_AM65_H
-#define _DT_BINDINGS_PINCTRL_TI_K3_AM65_H
-
-#define PULL_DISABLE (1 << 16)
-#define PULL_UP (1 << 17)
-#define INPUT_EN (1 << 18)
-#define SLEWCTRL_200MHZ 0
-#define SLEWCTRL_150MHZ (1 << 19)
-#define SLEWCTRL_100MHZ (2 << 19)
-#define SLEWCTRL_50MHZ (3 << 19)
-#define TX_DIS (1 << 21)
-#define ISO_OVR (1 << 22)
-#define ISO_BYPASS (1 << 23)
-#define DS_EN (1 << 24)
-#define DS_INPUT (1 << 25)
-#define DS_FORCE_OUT_HIGH (1 << 26)
-#define DS_PULL_UP_DOWN_EN 0
-#define DS_PULL_UP_DOWN_DIS (1 << 27)
-#define DS_PULL_UP_SEL (1 << 28)
-#define WAKEUP_ENABLE (1 << 29)
-
-#define PIN_OUTPUT (PULL_DISABLE)
-#define PIN_OUTPUT_PULLUP (PULL_UP)
-#define PIN_OUTPUT_PULLDOWN 0
-#define PIN_INPUT (INPUT_EN | PULL_DISABLE)
-#define PIN_INPUT_PULLUP (INPUT_EN | PULL_UP)
-#define PIN_INPUT_PULLDOWN (INPUT_EN)
-
-#define AM65X_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
-#define AM65X_WKUP_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
-
-#define J721E_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
-#define J721E_WKUP_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
-
-#endif
diff --git a/include/dt-bindings/pinctrl/omap.h b/include/dt-bindings/pinctrl/omap.h
deleted file mode 100644
index 58fe28f..0000000
--- a/include/dt-bindings/pinctrl/omap.h
+++ /dev/null
@@ -1,93 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * This header provides constants for OMAP pinctrl bindings.
- *
- * Copyright (C) 2009 Nokia
- * Copyright (C) 2009-2010 Texas Instruments
- */
-
-#ifndef _DT_BINDINGS_PINCTRL_OMAP_H
-#define _DT_BINDINGS_PINCTRL_OMAP_H
-
-/* 34xx mux mode options for each pin. See TRM for options */
-#define MUX_MODE0 0
-#define MUX_MODE1 1
-#define MUX_MODE2 2
-#define MUX_MODE3 3
-#define MUX_MODE4 4
-#define MUX_MODE5 5
-#define MUX_MODE6 6
-#define MUX_MODE7 7
-
-/* 24xx/34xx mux bit defines */
-#define PULL_ENA (1 << 3)
-#define PULL_UP (1 << 4)
-#define ALTELECTRICALSEL (1 << 5)
-
-/* 34xx specific mux bit defines */
-#define INPUT_EN (1 << 8)
-#define OFF_EN (1 << 9)
-#define OFFOUT_EN (1 << 10)
-#define OFFOUT_VAL (1 << 11)
-#define OFF_PULL_EN (1 << 12)
-#define OFF_PULL_UP (1 << 13)
-#define WAKEUP_EN (1 << 14)
-
-/* 44xx specific mux bit defines */
-#define WAKEUP_EVENT (1 << 15)
-
-/* Active pin states */
-#define PIN_OUTPUT 0
-#define PIN_OUTPUT_PULLUP (PIN_OUTPUT | PULL_ENA | PULL_UP)
-#define PIN_OUTPUT_PULLDOWN (PIN_OUTPUT | PULL_ENA)
-#define PIN_INPUT INPUT_EN
-#define PIN_INPUT_PULLUP (PULL_ENA | INPUT_EN | PULL_UP)
-#define PIN_INPUT_PULLDOWN (PULL_ENA | INPUT_EN)
-
-/* Off mode states */
-#define PIN_OFF_NONE 0
-#define PIN_OFF_OUTPUT_HIGH (OFF_EN | OFFOUT_EN | OFFOUT_VAL)
-#define PIN_OFF_OUTPUT_LOW (OFF_EN | OFFOUT_EN)
-#define PIN_OFF_INPUT_PULLUP (OFF_EN | OFF_PULL_EN | OFF_PULL_UP)
-#define PIN_OFF_INPUT_PULLDOWN (OFF_EN | OFF_PULL_EN)
-#define PIN_OFF_WAKEUPENABLE WAKEUP_EN
-
-/*
- * Macros to allow using the absolute physical address instead of the
- * padconf registers instead of the offset from padconf base.
- */
-#define OMAP_IOPAD_OFFSET(pa, offset) (((pa) & 0xffff) - (offset))
-
-#define OMAP2420_CORE_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0030) (val)
-#define OMAP2430_CORE_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x2030) (val)
-#define OMAP3_CORE1_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x2030) (val)
-#define OMAP3430_CORE2_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x25d8) (val)
-#define OMAP3630_CORE2_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x25a0) (val)
-#define OMAP3_WKUP_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x2a00) (val)
-#define DM814X_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val)
-#define DM816X_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val)
-#define AM33XX_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val)
-
-/*
- * Macros to allow using the offset from the padconf physical address
- * instead of the offset from padconf base.
- */
-#define OMAP_PADCONF_OFFSET(offset, base_offset) ((offset) - (base_offset))
-
-#define OMAP4_IOPAD(offset, val) OMAP_PADCONF_OFFSET((offset), 0x0040) (val)
-#define OMAP5_IOPAD(offset, val) OMAP_PADCONF_OFFSET((offset), 0x0040) (val)
-
-/*
- * Define some commonly used pins configured by the boards.
- * Note that some boards use alternative pins, so check
- * the schematics before using these.
- */
-#define OMAP3_UART1_RX 0x152
-#define OMAP3_UART2_RX 0x14a
-#define OMAP3_UART3_RX 0x16e
-#define OMAP4_UART2_RX 0xdc
-#define OMAP4_UART3_RX 0x104
-#define OMAP4_UART4_RX 0x11c
-
-#endif
-
diff --git a/include/dt-bindings/pinctrl/pads-imx8qm.h b/include/dt-bindings/pinctrl/pads-imx8qm.h
deleted file mode 100644
index e980fd5..0000000
--- a/include/dt-bindings/pinctrl/pads-imx8qm.h
+++ /dev/null
@@ -1,961 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2018 NXP
- */
-
-#ifndef SC_PADS_H
-#define SC_PADS_H
-
-#define SC_P_SIM0_CLK 0 /* DMA.SIM0.CLK, LSIO.GPIO0.IO00 */
-#define SC_P_SIM0_RST 1 /* DMA.SIM0.RST, LSIO.GPIO0.IO01 */
-#define SC_P_SIM0_IO 2 /* DMA.SIM0.IO, LSIO.GPIO0.IO02 */
-#define SC_P_SIM0_PD 3 /* DMA.SIM0.PD, DMA.I2C3.SCL, LSIO.GPIO0.IO03 */
-#define SC_P_SIM0_POWER_EN 4 /* DMA.SIM0.POWER_EN, DMA.I2C3.SDA, LSIO.GPIO0.IO04 */
-#define SC_P_SIM0_GPIO0_00 5 /* DMA.SIM0.POWER_EN, LSIO.GPIO0.IO05 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_SIM 6 /* */
-#define SC_P_M40_I2C0_SCL 7 /* M40.I2C0.SCL, M40.UART0.RX, M40.GPIO0.IO02, LSIO.GPIO0.IO06 */
-#define SC_P_M40_I2C0_SDA 8 /* M40.I2C0.SDA, M40.UART0.TX, M40.GPIO0.IO03, LSIO.GPIO0.IO07 */
-#define SC_P_M40_GPIO0_00 9 /* M40.GPIO0.IO00, M40.TPM0.CH0, DMA.UART4.RX, LSIO.GPIO0.IO08 */
-#define SC_P_M40_GPIO0_01 10 /* M40.GPIO0.IO01, M40.TPM0.CH1, DMA.UART4.TX, LSIO.GPIO0.IO09 */
-#define SC_P_M41_I2C0_SCL 11 /* M41.I2C0.SCL, M41.UART0.RX, M41.GPIO0.IO02, LSIO.GPIO0.IO10 */
-#define SC_P_M41_I2C0_SDA 12 /* M41.I2C0.SDA, M41.UART0.TX, M41.GPIO0.IO03, LSIO.GPIO0.IO11 */
-#define SC_P_M41_GPIO0_00 13 /* M41.GPIO0.IO00, M41.TPM0.CH0, DMA.UART3.RX, LSIO.GPIO0.IO12 */
-#define SC_P_M41_GPIO0_01 14 /* M41.GPIO0.IO01, M41.TPM0.CH1, DMA.UART3.TX, LSIO.GPIO0.IO13 */
-#define SC_P_GPT0_CLK 15 /* LSIO.GPT0.CLK, DMA.I2C1.SCL, LSIO.KPP0.COL4, LSIO.GPIO0.IO14 */
-#define SC_P_GPT0_CAPTURE 16 /* LSIO.GPT0.CAPTURE, DMA.I2C1.SDA, LSIO.KPP0.COL5, LSIO.GPIO0.IO15 */
-#define SC_P_GPT0_COMPARE 17 /* LSIO.GPT0.COMPARE, LSIO.PWM3.OUT, LSIO.KPP0.COL6, LSIO.GPIO0.IO16 */
-#define SC_P_GPT1_CLK 18 /* LSIO.GPT1.CLK, DMA.I2C2.SCL, LSIO.KPP0.COL7, LSIO.GPIO0.IO17 */
-#define SC_P_GPT1_CAPTURE 19 /* LSIO.GPT1.CAPTURE, DMA.I2C2.SDA, LSIO.KPP0.ROW4, LSIO.GPIO0.IO18 */
-#define SC_P_GPT1_COMPARE 20 /* LSIO.GPT1.COMPARE, LSIO.PWM2.OUT, LSIO.KPP0.ROW5, LSIO.GPIO0.IO19 */
-#define SC_P_UART0_RX 21 /* DMA.UART0.RX, SCU.UART0.RX, LSIO.GPIO0.IO20 */
-#define SC_P_UART0_TX 22 /* DMA.UART0.TX, SCU.UART0.TX, LSIO.GPIO0.IO21 */
-#define SC_P_UART0_RTS_B 23 /* DMA.UART0.RTS_B, LSIO.PWM0.OUT, DMA.UART2.RX, LSIO.GPIO0.IO22 */
-#define SC_P_UART0_CTS_B 24 /* DMA.UART0.CTS_B, LSIO.PWM1.OUT, DMA.UART2.TX, LSIO.GPIO0.IO23 */
-#define SC_P_UART1_TX 25 /* DMA.UART1.TX, DMA.SPI3.SCK, LSIO.GPIO0.IO24 */
-#define SC_P_UART1_RX 26 /* DMA.UART1.RX, DMA.SPI3.SDO, LSIO.GPIO0.IO25 */
-#define SC_P_UART1_RTS_B 27 /* DMA.UART1.RTS_B, DMA.SPI3.SDI, DMA.UART1.CTS_B, LSIO.GPIO0.IO26 */
-#define SC_P_UART1_CTS_B 28 /* DMA.UART1.CTS_B, DMA.SPI3.CS0, DMA.UART1.RTS_B, LSIO.GPIO0.IO27 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOLH 29 /* */
-#define SC_P_SCU_PMIC_MEMC_ON 30 /* SCU.GPIO0.IOXX_PMIC_MEMC_ON */
-#define SC_P_SCU_WDOG_OUT 31 /* SCU.WDOG0.WDOG_OUT */
-#define SC_P_PMIC_I2C_SDA 32 /* SCU.PMIC_I2C.SDA */
-#define SC_P_PMIC_I2C_SCL 33 /* SCU.PMIC_I2C.SCL */
-#define SC_P_PMIC_EARLY_WARNING 34 /* SCU.PMIC_EARLY_WARNING */
-#define SC_P_PMIC_INT_B 35 /* SCU.DSC.PMIC_INT_B */
-#define SC_P_SCU_GPIO0_00 36 /* SCU.GPIO0.IO00, SCU.UART0.RX, LSIO.GPIO0.IO28 */
-#define SC_P_SCU_GPIO0_01 37 /* SCU.GPIO0.IO01, SCU.UART0.TX, LSIO.GPIO0.IO29 */
-#define SC_P_SCU_GPIO0_02 38 /* SCU.GPIO0.IO02, SCU.GPIO0.IOXX_PMIC_GPU0_ON, LSIO.GPIO0.IO30 */
-#define SC_P_SCU_GPIO0_03 39 /* SCU.GPIO0.IO03, SCU.GPIO0.IOXX_PMIC_GPU1_ON, LSIO.GPIO0.IO31 */
-#define SC_P_SCU_GPIO0_04 40 /* SCU.GPIO0.IO04, SCU.GPIO0.IOXX_PMIC_A72_ON, LSIO.GPIO1.IO00 */
-#define SC_P_SCU_GPIO0_05 41 /* SCU.GPIO0.IO05, SCU.GPIO0.IOXX_PMIC_A53_ON, LSIO.GPIO1.IO01 */
-#define SC_P_SCU_GPIO0_06 42 /* SCU.GPIO0.IO06, SCU.TPM0.CH0, LSIO.GPIO1.IO02 */
-#define SC_P_SCU_GPIO0_07 43 /* SCU.GPIO0.IO07, SCU.TPM0.CH1, SCU.DSC.RTC_CLOCK_OUTPUT_32K, LSIO.GPIO1.IO03 */
-#define SC_P_SCU_BOOT_MODE0 44 /* SCU.DSC.BOOT_MODE0 */
-#define SC_P_SCU_BOOT_MODE1 45 /* SCU.DSC.BOOT_MODE1 */
-#define SC_P_SCU_BOOT_MODE2 46 /* SCU.DSC.BOOT_MODE2 */
-#define SC_P_SCU_BOOT_MODE3 47 /* SCU.DSC.BOOT_MODE3 */
-#define SC_P_SCU_BOOT_MODE4 48 /* SCU.DSC.BOOT_MODE4, SCU.PMIC_I2C.SCL */
-#define SC_P_SCU_BOOT_MODE5 49 /* SCU.DSC.BOOT_MODE5, SCU.PMIC_I2C.SDA */
-#define SC_P_LVDS0_GPIO00 50 /* LVDS0.GPIO0.IO00, LVDS0.PWM0.OUT, LSIO.GPIO1.IO04 */
-#define SC_P_LVDS0_GPIO01 51 /* LVDS0.GPIO0.IO01, LSIO.GPIO1.IO05 */
-#define SC_P_LVDS0_I2C0_SCL 52 /* LVDS0.I2C0.SCL, LVDS0.GPIO0.IO02, LSIO.GPIO1.IO06 */
-#define SC_P_LVDS0_I2C0_SDA 53 /* LVDS0.I2C0.SDA, LVDS0.GPIO0.IO03, LSIO.GPIO1.IO07 */
-#define SC_P_LVDS0_I2C1_SCL 54 /* LVDS0.I2C1.SCL, DMA.UART2.TX, LSIO.GPIO1.IO08 */
-#define SC_P_LVDS0_I2C1_SDA 55 /* LVDS0.I2C1.SDA, DMA.UART2.RX, LSIO.GPIO1.IO09 */
-#define SC_P_LVDS1_GPIO00 56 /* LVDS1.GPIO0.IO00, LVDS1.PWM0.OUT, LSIO.GPIO1.IO10 */
-#define SC_P_LVDS1_GPIO01 57 /* LVDS1.GPIO0.IO01, LSIO.GPIO1.IO11 */
-#define SC_P_LVDS1_I2C0_SCL 58 /* LVDS1.I2C0.SCL, LVDS1.GPIO0.IO02, LSIO.GPIO1.IO12 */
-#define SC_P_LVDS1_I2C0_SDA 59 /* LVDS1.I2C0.SDA, LVDS1.GPIO0.IO03, LSIO.GPIO1.IO13 */
-#define SC_P_LVDS1_I2C1_SCL 60 /* LVDS1.I2C1.SCL, DMA.UART3.TX, LSIO.GPIO1.IO14 */
-#define SC_P_LVDS1_I2C1_SDA 61 /* LVDS1.I2C1.SDA, DMA.UART3.RX, LSIO.GPIO1.IO15 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO 62 /* */
-#define SC_P_MIPI_DSI0_I2C0_SCL 63 /* MIPI_DSI0.I2C0.SCL, LSIO.GPIO1.IO16 */
-#define SC_P_MIPI_DSI0_I2C0_SDA 64 /* MIPI_DSI0.I2C0.SDA, LSIO.GPIO1.IO17 */
-#define SC_P_MIPI_DSI0_GPIO0_00 65 /* MIPI_DSI0.GPIO0.IO00, MIPI_DSI0.PWM0.OUT, LSIO.GPIO1.IO18 */
-#define SC_P_MIPI_DSI0_GPIO0_01 66 /* MIPI_DSI0.GPIO0.IO01, LSIO.GPIO1.IO19 */
-#define SC_P_MIPI_DSI1_I2C0_SCL 67 /* MIPI_DSI1.I2C0.SCL, LSIO.GPIO1.IO20 */
-#define SC_P_MIPI_DSI1_I2C0_SDA 68 /* MIPI_DSI1.I2C0.SDA, LSIO.GPIO1.IO21 */
-#define SC_P_MIPI_DSI1_GPIO0_00 69 /* MIPI_DSI1.GPIO0.IO00, MIPI_DSI1.PWM0.OUT, LSIO.GPIO1.IO22 */
-#define SC_P_MIPI_DSI1_GPIO0_01 70 /* MIPI_DSI1.GPIO0.IO01, LSIO.GPIO1.IO23 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO 71 /* */
-#define SC_P_MIPI_CSI0_MCLK_OUT 72 /* MIPI_CSI0.ACM.MCLK_OUT, LSIO.GPIO1.IO24 */
-#define SC_P_MIPI_CSI0_I2C0_SCL 73 /* MIPI_CSI0.I2C0.SCL, LSIO.GPIO1.IO25 */
-#define SC_P_MIPI_CSI0_I2C0_SDA 74 /* MIPI_CSI0.I2C0.SDA, LSIO.GPIO1.IO26 */
-#define SC_P_MIPI_CSI0_GPIO0_00 75 /* MIPI_CSI0.GPIO0.IO00, DMA.I2C0.SCL, MIPI_CSI1.I2C0.SCL, LSIO.GPIO1.IO27 */
-#define SC_P_MIPI_CSI0_GPIO0_01 76 /* MIPI_CSI0.GPIO0.IO01, DMA.I2C0.SDA, MIPI_CSI1.I2C0.SDA, LSIO.GPIO1.IO28 */
-#define SC_P_MIPI_CSI1_MCLK_OUT 77 /* MIPI_CSI1.ACM.MCLK_OUT, LSIO.GPIO1.IO29 */
-#define SC_P_MIPI_CSI1_GPIO0_00 78 /* MIPI_CSI1.GPIO0.IO00, DMA.UART4.RX, LSIO.GPIO1.IO30 */
-#define SC_P_MIPI_CSI1_GPIO0_01 79 /* MIPI_CSI1.GPIO0.IO01, DMA.UART4.TX, LSIO.GPIO1.IO31 */
-#define SC_P_MIPI_CSI1_I2C0_SCL 80 /* MIPI_CSI1.I2C0.SCL, LSIO.GPIO2.IO00 */
-#define SC_P_MIPI_CSI1_I2C0_SDA 81 /* MIPI_CSI1.I2C0.SDA, LSIO.GPIO2.IO01 */
-#define SC_P_HDMI_TX0_TS_SCL 82 /* HDMI_TX0.I2C0.SCL, DMA.I2C0.SCL, LSIO.GPIO2.IO02 */
-#define SC_P_HDMI_TX0_TS_SDA 83 /* HDMI_TX0.I2C0.SDA, DMA.I2C0.SDA, LSIO.GPIO2.IO03 */
-#define SC_P_COMP_CTL_GPIO_3V3_HDMIGPIO 84 /* */
-#define SC_P_ESAI1_FSR 85 /* AUD.ESAI1.FSR, LSIO.GPIO2.IO04 */
-#define SC_P_ESAI1_FST 86 /* AUD.ESAI1.FST, AUD.SPDIF0.EXT_CLK, LSIO.GPIO2.IO05 */
-#define SC_P_ESAI1_SCKR 87 /* AUD.ESAI1.SCKR, LSIO.GPIO2.IO06 */
-#define SC_P_ESAI1_SCKT 88 /* AUD.ESAI1.SCKT, AUD.SAI2.RXC, AUD.SPDIF0.EXT_CLK, LSIO.GPIO2.IO07 */
-#define SC_P_ESAI1_TX0 89 /* AUD.ESAI1.TX0, AUD.SAI2.RXD, AUD.SPDIF0.RX, LSIO.GPIO2.IO08 */
-#define SC_P_ESAI1_TX1 90 /* AUD.ESAI1.TX1, AUD.SAI2.RXFS, AUD.SPDIF0.TX, LSIO.GPIO2.IO09 */
-#define SC_P_ESAI1_TX2_RX3 91 /* AUD.ESAI1.TX2_RX3, AUD.SPDIF0.RX, LSIO.GPIO2.IO10 */
-#define SC_P_ESAI1_TX3_RX2 92 /* AUD.ESAI1.TX3_RX2, AUD.SPDIF0.TX, LSIO.GPIO2.IO11 */
-#define SC_P_ESAI1_TX4_RX1 93 /* AUD.ESAI1.TX4_RX1, LSIO.GPIO2.IO12 */
-#define SC_P_ESAI1_TX5_RX0 94 /* AUD.ESAI1.TX5_RX0, LSIO.GPIO2.IO13 */
-#define SC_P_SPDIF0_RX 95 /* AUD.SPDIF0.RX, AUD.MQS.R, AUD.ACM.MCLK_IN1, LSIO.GPIO2.IO14 */
-#define SC_P_SPDIF0_TX 96 /* AUD.SPDIF0.TX, AUD.MQS.L, AUD.ACM.MCLK_OUT1, LSIO.GPIO2.IO15 */
-#define SC_P_SPDIF0_EXT_CLK 97 /* AUD.SPDIF0.EXT_CLK, DMA.DMA0.REQ_IN0, LSIO.GPIO2.IO16 */
-#define SC_P_SPI3_SCK 98 /* DMA.SPI3.SCK, LSIO.GPIO2.IO17 */
-#define SC_P_SPI3_SDO 99 /* DMA.SPI3.SDO, DMA.FTM.CH0, LSIO.GPIO2.IO18 */
-#define SC_P_SPI3_SDI 100 /* DMA.SPI3.SDI, DMA.FTM.CH1, LSIO.GPIO2.IO19 */
-#define SC_P_SPI3_CS0 101 /* DMA.SPI3.CS0, DMA.FTM.CH2, LSIO.GPIO2.IO20 */
-#define SC_P_SPI3_CS1 102 /* DMA.SPI3.CS1, LSIO.GPIO2.IO21 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB 103 /* */
-#define SC_P_ESAI0_FSR 104 /* AUD.ESAI0.FSR, LSIO.GPIO2.IO22 */
-#define SC_P_ESAI0_FST 105 /* AUD.ESAI0.FST, LSIO.GPIO2.IO23 */
-#define SC_P_ESAI0_SCKR 106 /* AUD.ESAI0.SCKR, LSIO.GPIO2.IO24 */
-#define SC_P_ESAI0_SCKT 107 /* AUD.ESAI0.SCKT, LSIO.GPIO2.IO25 */
-#define SC_P_ESAI0_TX0 108 /* AUD.ESAI0.TX0, LSIO.GPIO2.IO26 */
-#define SC_P_ESAI0_TX1 109 /* AUD.ESAI0.TX1, LSIO.GPIO2.IO27 */
-#define SC_P_ESAI0_TX2_RX3 110 /* AUD.ESAI0.TX2_RX3, LSIO.GPIO2.IO28 */
-#define SC_P_ESAI0_TX3_RX2 111 /* AUD.ESAI0.TX3_RX2, LSIO.GPIO2.IO29 */
-#define SC_P_ESAI0_TX4_RX1 112 /* AUD.ESAI0.TX4_RX1, LSIO.GPIO2.IO30 */
-#define SC_P_ESAI0_TX5_RX0 113 /* AUD.ESAI0.TX5_RX0, LSIO.GPIO2.IO31 */
-#define SC_P_MCLK_IN0 114 /* AUD.ACM.MCLK_IN0, AUD.ESAI0.RX_HF_CLK, AUD.ESAI1.RX_HF_CLK, LSIO.GPIO3.IO00 */
-#define SC_P_MCLK_OUT0 115 /* AUD.ACM.MCLK_OUT0, AUD.ESAI0.TX_HF_CLK, AUD.ESAI1.TX_HF_CLK, LSIO.GPIO3.IO01 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHC 116 /* */
-#define SC_P_SPI0_SCK 117 /* DMA.SPI0.SCK, AUD.SAI0.RXC, LSIO.GPIO3.IO02 */
-#define SC_P_SPI0_SDO 118 /* DMA.SPI0.SDO, AUD.SAI0.TXD, LSIO.GPIO3.IO03 */
-#define SC_P_SPI0_SDI 119 /* DMA.SPI0.SDI, AUD.SAI0.RXD, LSIO.GPIO3.IO04 */
-#define SC_P_SPI0_CS0 120 /* DMA.SPI0.CS0, AUD.SAI0.RXFS, LSIO.GPIO3.IO05 */
-#define SC_P_SPI0_CS1 121 /* DMA.SPI0.CS1, AUD.SAI0.TXC, LSIO.GPIO3.IO06 */
-#define SC_P_SPI2_SCK 122 /* DMA.SPI2.SCK, LSIO.GPIO3.IO07 */
-#define SC_P_SPI2_SDO 123 /* DMA.SPI2.SDO, LSIO.GPIO3.IO08 */
-#define SC_P_SPI2_SDI 124 /* DMA.SPI2.SDI, LSIO.GPIO3.IO09 */
-#define SC_P_SPI2_CS0 125 /* DMA.SPI2.CS0, LSIO.GPIO3.IO10 */
-#define SC_P_SPI2_CS1 126 /* DMA.SPI2.CS1, AUD.SAI0.TXFS, LSIO.GPIO3.IO11 */
-#define SC_P_SAI1_RXC 127 /* AUD.SAI1.RXC, AUD.SAI0.TXD, LSIO.GPIO3.IO12 */
-#define SC_P_SAI1_RXD 128 /* AUD.SAI1.RXD, AUD.SAI0.TXFS, LSIO.GPIO3.IO13 */
-#define SC_P_SAI1_RXFS 129 /* AUD.SAI1.RXFS, AUD.SAI0.RXD, LSIO.GPIO3.IO14 */
-#define SC_P_SAI1_TXC 130 /* AUD.SAI1.TXC, AUD.SAI0.TXC, LSIO.GPIO3.IO15 */
-#define SC_P_SAI1_TXD 131 /* AUD.SAI1.TXD, AUD.SAI1.RXC, LSIO.GPIO3.IO16 */
-#define SC_P_SAI1_TXFS 132 /* AUD.SAI1.TXFS, AUD.SAI1.RXFS, LSIO.GPIO3.IO17 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHT 133 /* */
-#define SC_P_ADC_IN7 134 /* DMA.ADC1.IN3, DMA.SPI1.CS1, LSIO.KPP0.ROW3, LSIO.GPIO3.IO25 */
-#define SC_P_ADC_IN6 135 /* DMA.ADC1.IN2, DMA.SPI1.CS0, LSIO.KPP0.ROW2, LSIO.GPIO3.IO24 */
-#define SC_P_ADC_IN5 136 /* DMA.ADC1.IN1, DMA.SPI1.SDI, LSIO.KPP0.ROW1, LSIO.GPIO3.IO23 */
-#define SC_P_ADC_IN4 137 /* DMA.ADC1.IN0, DMA.SPI1.SDO, LSIO.KPP0.ROW0, LSIO.GPIO3.IO22 */
-#define SC_P_ADC_IN3 138 /* DMA.ADC0.IN3, DMA.SPI1.SCK, LSIO.KPP0.COL3, LSIO.GPIO3.IO21 */
-#define SC_P_ADC_IN2 139 /* DMA.ADC0.IN2, LSIO.KPP0.COL2, LSIO.GPIO3.IO20 */
-#define SC_P_ADC_IN1 140 /* DMA.ADC0.IN1, LSIO.KPP0.COL1, LSIO.GPIO3.IO19 */
-#define SC_P_ADC_IN0 141 /* DMA.ADC0.IN0, LSIO.KPP0.COL0, LSIO.GPIO3.IO18 */
-#define SC_P_MLB_SIG 142 /* CONN.MLB.SIG, AUD.SAI3.RXC, LSIO.GPIO3.IO26 */
-#define SC_P_MLB_CLK 143 /* CONN.MLB.CLK, AUD.SAI3.RXFS, LSIO.GPIO3.IO27 */
-#define SC_P_MLB_DATA 144 /* CONN.MLB.DATA, AUD.SAI3.RXD, LSIO.GPIO3.IO28 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOLHT 145 /* */
-#define SC_P_FLEXCAN0_RX 146 /* DMA.FLEXCAN0.RX, LSIO.GPIO3.IO29 */
-#define SC_P_FLEXCAN0_TX 147 /* DMA.FLEXCAN0.TX, LSIO.GPIO3.IO30 */
-#define SC_P_FLEXCAN1_RX 148 /* DMA.FLEXCAN1.RX, LSIO.GPIO3.IO31 */
-#define SC_P_FLEXCAN1_TX 149 /* DMA.FLEXCAN1.TX, LSIO.GPIO4.IO00 */
-#define SC_P_FLEXCAN2_RX 150 /* DMA.FLEXCAN2.RX, LSIO.GPIO4.IO01 */
-#define SC_P_FLEXCAN2_TX 151 /* DMA.FLEXCAN2.TX, LSIO.GPIO4.IO02 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOTHR 152 /* */
-#define SC_P_USB_SS3_TC0 153 /* DMA.I2C1.SCL, CONN.USB_OTG1.PWR, LSIO.GPIO4.IO03 */
-#define SC_P_USB_SS3_TC1 154 /* DMA.I2C1.SCL, CONN.USB_OTG2.PWR, LSIO.GPIO4.IO04 */
-#define SC_P_USB_SS3_TC2 155 /* DMA.I2C1.SDA, CONN.USB_OTG1.OC, LSIO.GPIO4.IO05 */
-#define SC_P_USB_SS3_TC3 156 /* DMA.I2C1.SDA, CONN.USB_OTG2.OC, LSIO.GPIO4.IO06 */
-#define SC_P_COMP_CTL_GPIO_3V3_USB3IO 157 /* */
-#define SC_P_USDHC1_RESET_B 158 /* CONN.USDHC1.RESET_B, LSIO.GPIO4.IO07 */
-#define SC_P_USDHC1_VSELECT 159 /* CONN.USDHC1.VSELECT, LSIO.GPIO4.IO08 */
-#define SC_P_USDHC2_RESET_B 160 /* CONN.USDHC2.RESET_B, LSIO.GPIO4.IO09 */
-#define SC_P_USDHC2_VSELECT 161 /* CONN.USDHC2.VSELECT, LSIO.GPIO4.IO10 */
-#define SC_P_USDHC2_WP 162 /* CONN.USDHC2.WP, LSIO.GPIO4.IO11 */
-#define SC_P_USDHC2_CD_B 163 /* CONN.USDHC2.CD_B, LSIO.GPIO4.IO12 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSELSEP 164 /* */
-#define SC_P_ENET0_MDIO 165 /* CONN.ENET0.MDIO, DMA.I2C4.SDA, LSIO.GPIO4.IO13 */
-#define SC_P_ENET0_MDC 166 /* CONN.ENET0.MDC, DMA.I2C4.SCL, LSIO.GPIO4.IO14 */
-#define SC_P_ENET0_REFCLK_125M_25M 167 /* CONN.ENET0.REFCLK_125M_25M, CONN.ENET0.PPS, LSIO.GPIO4.IO15 */
-#define SC_P_ENET1_REFCLK_125M_25M 168 /* CONN.ENET1.REFCLK_125M_25M, CONN.ENET1.PPS, LSIO.GPIO4.IO16 */
-#define SC_P_ENET1_MDIO 169 /* CONN.ENET1.MDIO, DMA.I2C4.SDA, LSIO.GPIO4.IO17 */
-#define SC_P_ENET1_MDC 170 /* CONN.ENET1.MDC, DMA.I2C4.SCL, LSIO.GPIO4.IO18 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOCT 171 /* */
-#define SC_P_QSPI1A_SS0_B 172 /* LSIO.QSPI1A.SS0_B, LSIO.GPIO4.IO19 */
-#define SC_P_QSPI1A_SS1_B 173 /* LSIO.QSPI1A.SS1_B, LSIO.QSPI1A.SCLK2, LSIO.GPIO4.IO20 */
-#define SC_P_QSPI1A_SCLK 174 /* LSIO.QSPI1A.SCLK, LSIO.GPIO4.IO21 */
-#define SC_P_QSPI1A_DQS 175 /* LSIO.QSPI1A.DQS, LSIO.GPIO4.IO22 */
-#define SC_P_QSPI1A_DATA3 176 /* LSIO.QSPI1A.DATA3, DMA.I2C1.SDA, CONN.USB_OTG1.OC, LSIO.GPIO4.IO23 */
-#define SC_P_QSPI1A_DATA2 177 /* LSIO.QSPI1A.DATA2, DMA.I2C1.SCL, CONN.USB_OTG2.PWR, LSIO.GPIO4.IO24 */
-#define SC_P_QSPI1A_DATA1 178 /* LSIO.QSPI1A.DATA1, DMA.I2C1.SDA, CONN.USB_OTG2.OC, LSIO.GPIO4.IO25 */
-#define SC_P_QSPI1A_DATA0 179 /* LSIO.QSPI1A.DATA0, LSIO.GPIO4.IO26 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI1 180 /* */
-#define SC_P_QSPI0A_DATA0 181 /* LSIO.QSPI0A.DATA0 */
-#define SC_P_QSPI0A_DATA1 182 /* LSIO.QSPI0A.DATA1 */
-#define SC_P_QSPI0A_DATA2 183 /* LSIO.QSPI0A.DATA2 */
-#define SC_P_QSPI0A_DATA3 184 /* LSIO.QSPI0A.DATA3 */
-#define SC_P_QSPI0A_DQS 185 /* LSIO.QSPI0A.DQS */
-#define SC_P_QSPI0A_SS0_B 186 /* LSIO.QSPI0A.SS0_B */
-#define SC_P_QSPI0A_SS1_B 187 /* LSIO.QSPI0A.SS1_B, LSIO.QSPI0A.SCLK2 */
-#define SC_P_QSPI0A_SCLK 188 /* LSIO.QSPI0A.SCLK */
-#define SC_P_QSPI0B_SCLK 189 /* LSIO.QSPI0B.SCLK */
-#define SC_P_QSPI0B_DATA0 190 /* LSIO.QSPI0B.DATA0 */
-#define SC_P_QSPI0B_DATA1 191 /* LSIO.QSPI0B.DATA1 */
-#define SC_P_QSPI0B_DATA2 192 /* LSIO.QSPI0B.DATA2 */
-#define SC_P_QSPI0B_DATA3 193 /* LSIO.QSPI0B.DATA3 */
-#define SC_P_QSPI0B_DQS 194 /* LSIO.QSPI0B.DQS */
-#define SC_P_QSPI0B_SS0_B 195 /* LSIO.QSPI0B.SS0_B */
-#define SC_P_QSPI0B_SS1_B 196 /* LSIO.QSPI0B.SS1_B, LSIO.QSPI0B.SCLK2 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0 197 /* */
-#define SC_P_PCIE_CTRL0_CLKREQ_B 198 /* HSIO.PCIE0.CLKREQ_B, LSIO.GPIO4.IO27 */
-#define SC_P_PCIE_CTRL0_WAKE_B 199 /* HSIO.PCIE0.WAKE_B, LSIO.GPIO4.IO28 */
-#define SC_P_PCIE_CTRL0_PERST_B 200 /* HSIO.PCIE0.PERST_B, LSIO.GPIO4.IO29 */
-#define SC_P_PCIE_CTRL1_CLKREQ_B 201 /* HSIO.PCIE1.CLKREQ_B, DMA.I2C1.SDA, CONN.USB_OTG2.OC, LSIO.GPIO4.IO30 */
-#define SC_P_PCIE_CTRL1_WAKE_B 202 /* HSIO.PCIE1.WAKE_B, DMA.I2C1.SCL, CONN.USB_OTG2.PWR, LSIO.GPIO4.IO31 */
-#define SC_P_PCIE_CTRL1_PERST_B 203 /* HSIO.PCIE1.PERST_B, DMA.I2C1.SCL, CONN.USB_OTG1.PWR, LSIO.GPIO5.IO00 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_PCIESEP 204 /* */
-#define SC_P_USB_HSIC0_DATA 205 /* CONN.USB_HSIC0.DATA, DMA.I2C1.SDA, LSIO.GPIO5.IO01 */
-#define SC_P_USB_HSIC0_STROBE 206 /* CONN.USB_HSIC0.STROBE, DMA.I2C1.SCL, LSIO.GPIO5.IO02 */
-#define SC_P_CALIBRATION_0_HSIC 207 /* */
-#define SC_P_CALIBRATION_1_HSIC 208 /* */
-#define SC_P_EMMC0_CLK 209 /* CONN.EMMC0.CLK, CONN.NAND.READY_B */
-#define SC_P_EMMC0_CMD 210 /* CONN.EMMC0.CMD, CONN.NAND.DQS, AUD.MQS.R, LSIO.GPIO5.IO03 */
-#define SC_P_EMMC0_DATA0 211 /* CONN.EMMC0.DATA0, CONN.NAND.DATA00, LSIO.GPIO5.IO04 */
-#define SC_P_EMMC0_DATA1 212 /* CONN.EMMC0.DATA1, CONN.NAND.DATA01, LSIO.GPIO5.IO05 */
-#define SC_P_EMMC0_DATA2 213 /* CONN.EMMC0.DATA2, CONN.NAND.DATA02, LSIO.GPIO5.IO06 */
-#define SC_P_EMMC0_DATA3 214 /* CONN.EMMC0.DATA3, CONN.NAND.DATA03, LSIO.GPIO5.IO07 */
-#define SC_P_EMMC0_DATA4 215 /* CONN.EMMC0.DATA4, CONN.NAND.DATA04, LSIO.GPIO5.IO08 */
-#define SC_P_EMMC0_DATA5 216 /* CONN.EMMC0.DATA5, CONN.NAND.DATA05, LSIO.GPIO5.IO09 */
-#define SC_P_EMMC0_DATA6 217 /* CONN.EMMC0.DATA6, CONN.NAND.DATA06, LSIO.GPIO5.IO10 */
-#define SC_P_EMMC0_DATA7 218 /* CONN.EMMC0.DATA7, CONN.NAND.DATA07, LSIO.GPIO5.IO11 */
-#define SC_P_EMMC0_STROBE 219 /* CONN.EMMC0.STROBE, CONN.NAND.CLE, LSIO.GPIO5.IO12 */
-#define SC_P_EMMC0_RESET_B 220 /* CONN.EMMC0.RESET_B, CONN.NAND.WP_B, CONN.USDHC1.VSELECT, LSIO.GPIO5.IO13 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX 221 /* */
-#define SC_P_USDHC1_CLK 222 /* CONN.USDHC1.CLK, AUD.MQS.R */
-#define SC_P_USDHC1_CMD 223 /* CONN.USDHC1.CMD, AUD.MQS.L, LSIO.GPIO5.IO14 */
-#define SC_P_USDHC1_DATA0 224 /* CONN.USDHC1.DATA0, CONN.NAND.RE_N, LSIO.GPIO5.IO15 */
-#define SC_P_USDHC1_DATA1 225 /* CONN.USDHC1.DATA1, CONN.NAND.RE_P, LSIO.GPIO5.IO16 */
-#define SC_P_CTL_NAND_RE_P_N 226 /* */
-#define SC_P_USDHC1_DATA2 227 /* CONN.USDHC1.DATA2, CONN.NAND.DQS_N, LSIO.GPIO5.IO17 */
-#define SC_P_USDHC1_DATA3 228 /* CONN.USDHC1.DATA3, CONN.NAND.DQS_P, LSIO.GPIO5.IO18 */
-#define SC_P_CTL_NAND_DQS_P_N 229 /* */
-#define SC_P_USDHC1_DATA4 230 /* CONN.USDHC1.DATA4, CONN.NAND.CE0_B, AUD.MQS.R, LSIO.GPIO5.IO19 */
-#define SC_P_USDHC1_DATA5 231 /* CONN.USDHC1.DATA5, CONN.NAND.RE_B, AUD.MQS.L, LSIO.GPIO5.IO20 */
-#define SC_P_USDHC1_DATA6 232 /* CONN.USDHC1.DATA6, CONN.NAND.WE_B, CONN.USDHC1.WP, LSIO.GPIO5.IO21 */
-#define SC_P_USDHC1_DATA7 233 /* CONN.USDHC1.DATA7, CONN.NAND.ALE, CONN.USDHC1.CD_B, LSIO.GPIO5.IO22 */
-#define SC_P_USDHC1_STROBE 234 /* CONN.USDHC1.STROBE, CONN.NAND.CE1_B, CONN.USDHC1.RESET_B, LSIO.GPIO5.IO23 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSEL2 235 /* */
-#define SC_P_USDHC2_CLK 236 /* CONN.USDHC2.CLK, AUD.MQS.R, LSIO.GPIO5.IO24 */
-#define SC_P_USDHC2_CMD 237 /* CONN.USDHC2.CMD, AUD.MQS.L, LSIO.GPIO5.IO25 */
-#define SC_P_USDHC2_DATA0 238 /* CONN.USDHC2.DATA0, DMA.UART4.RX, LSIO.GPIO5.IO26 */
-#define SC_P_USDHC2_DATA1 239 /* CONN.USDHC2.DATA1, DMA.UART4.TX, LSIO.GPIO5.IO27 */
-#define SC_P_USDHC2_DATA2 240 /* CONN.USDHC2.DATA2, DMA.UART4.CTS_B, LSIO.GPIO5.IO28 */
-#define SC_P_USDHC2_DATA3 241 /* CONN.USDHC2.DATA3, DMA.UART4.RTS_B, LSIO.GPIO5.IO29 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSEL3 242 /* */
-#define SC_P_ENET0_RGMII_TXC 243 /* CONN.ENET0.RGMII_TXC, CONN.ENET0.RCLK50M_OUT, CONN.ENET0.RCLK50M_IN, LSIO.GPIO5.IO30 */
-#define SC_P_ENET0_RGMII_TX_CTL 244 /* CONN.ENET0.RGMII_TX_CTL, LSIO.GPIO5.IO31 */
-#define SC_P_ENET0_RGMII_TXD0 245 /* CONN.ENET0.RGMII_TXD0, LSIO.GPIO6.IO00 */
-#define SC_P_ENET0_RGMII_TXD1 246 /* CONN.ENET0.RGMII_TXD1, LSIO.GPIO6.IO01 */
-#define SC_P_ENET0_RGMII_TXD2 247 /* CONN.ENET0.RGMII_TXD2, DMA.UART3.TX, VPU.TSI_S1.VID, LSIO.GPIO6.IO02 */
-#define SC_P_ENET0_RGMII_TXD3 248 /* CONN.ENET0.RGMII_TXD3, DMA.UART3.RTS_B, VPU.TSI_S1.SYNC, LSIO.GPIO6.IO03 */
-#define SC_P_ENET0_RGMII_RXC 249 /* CONN.ENET0.RGMII_RXC, DMA.UART3.CTS_B, VPU.TSI_S1.DATA, LSIO.GPIO6.IO04 */
-#define SC_P_ENET0_RGMII_RX_CTL 250 /* CONN.ENET0.RGMII_RX_CTL, VPU.TSI_S0.VID, LSIO.GPIO6.IO05 */
-#define SC_P_ENET0_RGMII_RXD0 251 /* CONN.ENET0.RGMII_RXD0, VPU.TSI_S0.SYNC, LSIO.GPIO6.IO06 */
-#define SC_P_ENET0_RGMII_RXD1 252 /* CONN.ENET0.RGMII_RXD1, VPU.TSI_S0.DATA, LSIO.GPIO6.IO07 */
-#define SC_P_ENET0_RGMII_RXD2 253 /* CONN.ENET0.RGMII_RXD2, CONN.ENET0.RMII_RX_ER, VPU.TSI_S0.CLK, LSIO.GPIO6.IO08 */
-#define SC_P_ENET0_RGMII_RXD3 254 /* CONN.ENET0.RGMII_RXD3, DMA.UART3.RX, VPU.TSI_S1.CLK, LSIO.GPIO6.IO09 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB 255 /* */
-#define SC_P_ENET1_RGMII_TXC 256 /* CONN.ENET1.RGMII_TXC, CONN.ENET1.RCLK50M_OUT, CONN.ENET1.RCLK50M_IN, LSIO.GPIO6.IO10 */
-#define SC_P_ENET1_RGMII_TX_CTL 257 /* CONN.ENET1.RGMII_TX_CTL, LSIO.GPIO6.IO11 */
-#define SC_P_ENET1_RGMII_TXD0 258 /* CONN.ENET1.RGMII_TXD0, LSIO.GPIO6.IO12 */
-#define SC_P_ENET1_RGMII_TXD1 259 /* CONN.ENET1.RGMII_TXD1, LSIO.GPIO6.IO13 */
-#define SC_P_ENET1_RGMII_TXD2 260 /* CONN.ENET1.RGMII_TXD2, DMA.UART3.TX, VPU.TSI_S1.VID, LSIO.GPIO6.IO14 */
-#define SC_P_ENET1_RGMII_TXD3 261 /* CONN.ENET1.RGMII_TXD3, DMA.UART3.RTS_B, VPU.TSI_S1.SYNC, LSIO.GPIO6.IO15 */
-#define SC_P_ENET1_RGMII_RXC 262 /* CONN.ENET1.RGMII_RXC, DMA.UART3.CTS_B, VPU.TSI_S1.DATA, LSIO.GPIO6.IO16 */
-#define SC_P_ENET1_RGMII_RX_CTL 263 /* CONN.ENET1.RGMII_RX_CTL, VPU.TSI_S0.VID, LSIO.GPIO6.IO17 */
-#define SC_P_ENET1_RGMII_RXD0 264 /* CONN.ENET1.RGMII_RXD0, VPU.TSI_S0.SYNC, LSIO.GPIO6.IO18 */
-#define SC_P_ENET1_RGMII_RXD1 265 /* CONN.ENET1.RGMII_RXD1, VPU.TSI_S0.DATA, LSIO.GPIO6.IO19 */
-#define SC_P_ENET1_RGMII_RXD2 266 /* CONN.ENET1.RGMII_RXD2, CONN.ENET1.RMII_RX_ER, VPU.TSI_S0.CLK, LSIO.GPIO6.IO20 */
-#define SC_P_ENET1_RGMII_RXD3 267 /* CONN.ENET1.RGMII_RXD3, DMA.UART3.RX, VPU.TSI_S1.CLK, LSIO.GPIO6.IO21 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA 268 /* */
-/*@}*/
-
-/*!
- * @name Pad Mux Definitions
- * format: name padid padmux
- */
-/*@{*/
-#define SC_P_SIM0_CLK_DMA_SIM0_CLK SC_P_SIM0_CLK 0
-#define SC_P_SIM0_CLK_LSIO_GPIO0_IO00 SC_P_SIM0_CLK 3
-#define SC_P_SIM0_RST_DMA_SIM0_RST SC_P_SIM0_RST 0
-#define SC_P_SIM0_RST_LSIO_GPIO0_IO01 SC_P_SIM0_RST 3
-#define SC_P_SIM0_IO_DMA_SIM0_IO SC_P_SIM0_IO 0
-#define SC_P_SIM0_IO_LSIO_GPIO0_IO02 SC_P_SIM0_IO 3
-#define SC_P_SIM0_PD_DMA_SIM0_PD SC_P_SIM0_PD 0
-#define SC_P_SIM0_PD_DMA_I2C3_SCL SC_P_SIM0_PD 1
-#define SC_P_SIM0_PD_LSIO_GPIO0_IO03 SC_P_SIM0_PD 3
-#define SC_P_SIM0_POWER_EN_DMA_SIM0_POWER_EN SC_P_SIM0_POWER_EN 0
-#define SC_P_SIM0_POWER_EN_DMA_I2C3_SDA SC_P_SIM0_POWER_EN 1
-#define SC_P_SIM0_POWER_EN_LSIO_GPIO0_IO04 SC_P_SIM0_POWER_EN 3
-#define SC_P_SIM0_GPIO0_00_DMA_SIM0_POWER_EN SC_P_SIM0_GPIO0_00 0
-#define SC_P_SIM0_GPIO0_00_LSIO_GPIO0_IO05 SC_P_SIM0_GPIO0_00 3
-#define SC_P_M40_I2C0_SCL_M40_I2C0_SCL SC_P_M40_I2C0_SCL 0
-#define SC_P_M40_I2C0_SCL_M40_UART0_RX SC_P_M40_I2C0_SCL 1
-#define SC_P_M40_I2C0_SCL_M40_GPIO0_IO02 SC_P_M40_I2C0_SCL 2
-#define SC_P_M40_I2C0_SCL_LSIO_GPIO0_IO06 SC_P_M40_I2C0_SCL 3
-#define SC_P_M40_I2C0_SDA_M40_I2C0_SDA SC_P_M40_I2C0_SDA 0
-#define SC_P_M40_I2C0_SDA_M40_UART0_TX SC_P_M40_I2C0_SDA 1
-#define SC_P_M40_I2C0_SDA_M40_GPIO0_IO03 SC_P_M40_I2C0_SDA 2
-#define SC_P_M40_I2C0_SDA_LSIO_GPIO0_IO07 SC_P_M40_I2C0_SDA 3
-#define SC_P_M40_GPIO0_00_M40_GPIO0_IO00 SC_P_M40_GPIO0_00 0
-#define SC_P_M40_GPIO0_00_M40_TPM0_CH0 SC_P_M40_GPIO0_00 1
-#define SC_P_M40_GPIO0_00_DMA_UART4_RX SC_P_M40_GPIO0_00 2
-#define SC_P_M40_GPIO0_00_LSIO_GPIO0_IO08 SC_P_M40_GPIO0_00 3
-#define SC_P_M40_GPIO0_01_M40_GPIO0_IO01 SC_P_M40_GPIO0_01 0
-#define SC_P_M40_GPIO0_01_M40_TPM0_CH1 SC_P_M40_GPIO0_01 1
-#define SC_P_M40_GPIO0_01_DMA_UART4_TX SC_P_M40_GPIO0_01 2
-#define SC_P_M40_GPIO0_01_LSIO_GPIO0_IO09 SC_P_M40_GPIO0_01 3
-#define SC_P_M41_I2C0_SCL_M41_I2C0_SCL SC_P_M41_I2C0_SCL 0
-#define SC_P_M41_I2C0_SCL_M41_UART0_RX SC_P_M41_I2C0_SCL 1
-#define SC_P_M41_I2C0_SCL_M41_GPIO0_IO02 SC_P_M41_I2C0_SCL 2
-#define SC_P_M41_I2C0_SCL_LSIO_GPIO0_IO10 SC_P_M41_I2C0_SCL 3
-#define SC_P_M41_I2C0_SDA_M41_I2C0_SDA SC_P_M41_I2C0_SDA 0
-#define SC_P_M41_I2C0_SDA_M41_UART0_TX SC_P_M41_I2C0_SDA 1
-#define SC_P_M41_I2C0_SDA_M41_GPIO0_IO03 SC_P_M41_I2C0_SDA 2
-#define SC_P_M41_I2C0_SDA_LSIO_GPIO0_IO11 SC_P_M41_I2C0_SDA 3
-#define SC_P_M41_GPIO0_00_M41_GPIO0_IO00 SC_P_M41_GPIO0_00 0
-#define SC_P_M41_GPIO0_00_M41_TPM0_CH0 SC_P_M41_GPIO0_00 1
-#define SC_P_M41_GPIO0_00_DMA_UART3_RX SC_P_M41_GPIO0_00 2
-#define SC_P_M41_GPIO0_00_LSIO_GPIO0_IO12 SC_P_M41_GPIO0_00 3
-#define SC_P_M41_GPIO0_01_M41_GPIO0_IO01 SC_P_M41_GPIO0_01 0
-#define SC_P_M41_GPIO0_01_M41_TPM0_CH1 SC_P_M41_GPIO0_01 1
-#define SC_P_M41_GPIO0_01_DMA_UART3_TX SC_P_M41_GPIO0_01 2
-#define SC_P_M41_GPIO0_01_LSIO_GPIO0_IO13 SC_P_M41_GPIO0_01 3
-#define SC_P_GPT0_CLK_LSIO_GPT0_CLK SC_P_GPT0_CLK 0
-#define SC_P_GPT0_CLK_DMA_I2C1_SCL SC_P_GPT0_CLK 1
-#define SC_P_GPT0_CLK_LSIO_KPP0_COL4 SC_P_GPT0_CLK 2
-#define SC_P_GPT0_CLK_LSIO_GPIO0_IO14 SC_P_GPT0_CLK 3
-#define SC_P_GPT0_CAPTURE_LSIO_GPT0_CAPTURE SC_P_GPT0_CAPTURE 0
-#define SC_P_GPT0_CAPTURE_DMA_I2C1_SDA SC_P_GPT0_CAPTURE 1
-#define SC_P_GPT0_CAPTURE_LSIO_KPP0_COL5 SC_P_GPT0_CAPTURE 2
-#define SC_P_GPT0_CAPTURE_LSIO_GPIO0_IO15 SC_P_GPT0_CAPTURE 3
-#define SC_P_GPT0_COMPARE_LSIO_GPT0_COMPARE SC_P_GPT0_COMPARE 0
-#define SC_P_GPT0_COMPARE_LSIO_PWM3_OUT SC_P_GPT0_COMPARE 1
-#define SC_P_GPT0_COMPARE_LSIO_KPP0_COL6 SC_P_GPT0_COMPARE 2
-#define SC_P_GPT0_COMPARE_LSIO_GPIO0_IO16 SC_P_GPT0_COMPARE 3
-#define SC_P_GPT1_CLK_LSIO_GPT1_CLK SC_P_GPT1_CLK 0
-#define SC_P_GPT1_CLK_DMA_I2C2_SCL SC_P_GPT1_CLK 1
-#define SC_P_GPT1_CLK_LSIO_KPP0_COL7 SC_P_GPT1_CLK 2
-#define SC_P_GPT1_CLK_LSIO_GPIO0_IO17 SC_P_GPT1_CLK 3
-#define SC_P_GPT1_CAPTURE_LSIO_GPT1_CAPTURE SC_P_GPT1_CAPTURE 0
-#define SC_P_GPT1_CAPTURE_DMA_I2C2_SDA SC_P_GPT1_CAPTURE 1
-#define SC_P_GPT1_CAPTURE_LSIO_KPP0_ROW4 SC_P_GPT1_CAPTURE 2
-#define SC_P_GPT1_CAPTURE_LSIO_GPIO0_IO18 SC_P_GPT1_CAPTURE 3
-#define SC_P_GPT1_COMPARE_LSIO_GPT1_COMPARE SC_P_GPT1_COMPARE 0
-#define SC_P_GPT1_COMPARE_LSIO_PWM2_OUT SC_P_GPT1_COMPARE 1
-#define SC_P_GPT1_COMPARE_LSIO_KPP0_ROW5 SC_P_GPT1_COMPARE 2
-#define SC_P_GPT1_COMPARE_LSIO_GPIO0_IO19 SC_P_GPT1_COMPARE 3
-#define SC_P_UART0_RX_DMA_UART0_RX SC_P_UART0_RX 0
-#define SC_P_UART0_RX_SCU_UART0_RX SC_P_UART0_RX 1
-#define SC_P_UART0_RX_LSIO_GPIO0_IO20 SC_P_UART0_RX 3
-#define SC_P_UART0_TX_DMA_UART0_TX SC_P_UART0_TX 0
-#define SC_P_UART0_TX_SCU_UART0_TX SC_P_UART0_TX 1
-#define SC_P_UART0_TX_LSIO_GPIO0_IO21 SC_P_UART0_TX 3
-#define SC_P_UART0_RTS_B_DMA_UART0_RTS_B SC_P_UART0_RTS_B 0
-#define SC_P_UART0_RTS_B_LSIO_PWM0_OUT SC_P_UART0_RTS_B 1
-#define SC_P_UART0_RTS_B_DMA_UART2_RX SC_P_UART0_RTS_B 2
-#define SC_P_UART0_RTS_B_LSIO_GPIO0_IO22 SC_P_UART0_RTS_B 3
-#define SC_P_UART0_CTS_B_DMA_UART0_CTS_B SC_P_UART0_CTS_B 0
-#define SC_P_UART0_CTS_B_LSIO_PWM1_OUT SC_P_UART0_CTS_B 1
-#define SC_P_UART0_CTS_B_DMA_UART2_TX SC_P_UART0_CTS_B 2
-#define SC_P_UART0_CTS_B_LSIO_GPIO0_IO23 SC_P_UART0_CTS_B 3
-#define SC_P_UART1_TX_DMA_UART1_TX SC_P_UART1_TX 0
-#define SC_P_UART1_TX_DMA_SPI3_SCK SC_P_UART1_TX 1
-#define SC_P_UART1_TX_LSIO_GPIO0_IO24 SC_P_UART1_TX 3
-#define SC_P_UART1_RX_DMA_UART1_RX SC_P_UART1_RX 0
-#define SC_P_UART1_RX_DMA_SPI3_SDO SC_P_UART1_RX 1
-#define SC_P_UART1_RX_LSIO_GPIO0_IO25 SC_P_UART1_RX 3
-#define SC_P_UART1_RTS_B_DMA_UART1_RTS_B SC_P_UART1_RTS_B 0
-#define SC_P_UART1_RTS_B_DMA_SPI3_SDI SC_P_UART1_RTS_B 1
-#define SC_P_UART1_RTS_B_DMA_UART1_CTS_B SC_P_UART1_RTS_B 2
-#define SC_P_UART1_RTS_B_LSIO_GPIO0_IO26 SC_P_UART1_RTS_B 3
-#define SC_P_UART1_CTS_B_DMA_UART1_CTS_B SC_P_UART1_CTS_B 0
-#define SC_P_UART1_CTS_B_DMA_SPI3_CS0 SC_P_UART1_CTS_B 1
-#define SC_P_UART1_CTS_B_DMA_UART1_RTS_B SC_P_UART1_CTS_B 2
-#define SC_P_UART1_CTS_B_LSIO_GPIO0_IO27 SC_P_UART1_CTS_B 3
-#define SC_P_SCU_PMIC_MEMC_ON_SCU_GPIO0_IOXX_PMIC_MEMC_ON SC_P_SCU_PMIC_MEMC_ON 0
-#define SC_P_SCU_WDOG_OUT_SCU_WDOG0_WDOG_OUT SC_P_SCU_WDOG_OUT 0
-#define SC_P_PMIC_I2C_SDA_SCU_PMIC_I2C_SDA SC_P_PMIC_I2C_SDA 0
-#define SC_P_PMIC_I2C_SCL_SCU_PMIC_I2C_SCL SC_P_PMIC_I2C_SCL 0
-#define SC_P_PMIC_EARLY_WARNING_SCU_PMIC_EARLY_WARNING SC_P_PMIC_EARLY_WARNING 0
-#define SC_P_PMIC_INT_B_SCU_DSC_PMIC_INT_B SC_P_PMIC_INT_B 0
-#define SC_P_SCU_GPIO0_00_SCU_GPIO0_IO00 SC_P_SCU_GPIO0_00 0
-#define SC_P_SCU_GPIO0_00_SCU_UART0_RX SC_P_SCU_GPIO0_00 1
-#define SC_P_SCU_GPIO0_00_LSIO_GPIO0_IO28 SC_P_SCU_GPIO0_00 3
-#define SC_P_SCU_GPIO0_01_SCU_GPIO0_IO01 SC_P_SCU_GPIO0_01 0
-#define SC_P_SCU_GPIO0_01_SCU_UART0_TX SC_P_SCU_GPIO0_01 1
-#define SC_P_SCU_GPIO0_01_LSIO_GPIO0_IO29 SC_P_SCU_GPIO0_01 3
-#define SC_P_SCU_GPIO0_02_SCU_GPIO0_IO02 SC_P_SCU_GPIO0_02 0
-#define SC_P_SCU_GPIO0_02_SCU_GPIO0_IOXX_PMIC_GPU0_ON SC_P_SCU_GPIO0_02 1
-#define SC_P_SCU_GPIO0_02_LSIO_GPIO0_IO30 SC_P_SCU_GPIO0_02 3
-#define SC_P_SCU_GPIO0_03_SCU_GPIO0_IO03 SC_P_SCU_GPIO0_03 0
-#define SC_P_SCU_GPIO0_03_SCU_GPIO0_IOXX_PMIC_GPU1_ON SC_P_SCU_GPIO0_03 1
-#define SC_P_SCU_GPIO0_03_LSIO_GPIO0_IO31 SC_P_SCU_GPIO0_03 3
-#define SC_P_SCU_GPIO0_04_SCU_GPIO0_IO04 SC_P_SCU_GPIO0_04 0
-#define SC_P_SCU_GPIO0_04_SCU_GPIO0_IOXX_PMIC_A72_ON SC_P_SCU_GPIO0_04 1
-#define SC_P_SCU_GPIO0_04_LSIO_GPIO1_IO00 SC_P_SCU_GPIO0_04 3
-#define SC_P_SCU_GPIO0_05_SCU_GPIO0_IO05 SC_P_SCU_GPIO0_05 0
-#define SC_P_SCU_GPIO0_05_SCU_GPIO0_IOXX_PMIC_A53_ON SC_P_SCU_GPIO0_05 1
-#define SC_P_SCU_GPIO0_05_LSIO_GPIO1_IO01 SC_P_SCU_GPIO0_05 3
-#define SC_P_SCU_GPIO0_06_SCU_GPIO0_IO06 SC_P_SCU_GPIO0_06 0
-#define SC_P_SCU_GPIO0_06_SCU_TPM0_CH0 SC_P_SCU_GPIO0_06 1
-#define SC_P_SCU_GPIO0_06_LSIO_GPIO1_IO02 SC_P_SCU_GPIO0_06 3
-#define SC_P_SCU_GPIO0_07_SCU_GPIO0_IO07 SC_P_SCU_GPIO0_07 0
-#define SC_P_SCU_GPIO0_07_SCU_TPM0_CH1 SC_P_SCU_GPIO0_07 1
-#define SC_P_SCU_GPIO0_07_SCU_DSC_RTC_CLOCK_OUTPUT_32K SC_P_SCU_GPIO0_07 2
-#define SC_P_SCU_GPIO0_07_LSIO_GPIO1_IO03 SC_P_SCU_GPIO0_07 3
-#define SC_P_SCU_BOOT_MODE0_SCU_DSC_BOOT_MODE0 SC_P_SCU_BOOT_MODE0 0
-#define SC_P_SCU_BOOT_MODE1_SCU_DSC_BOOT_MODE1 SC_P_SCU_BOOT_MODE1 0
-#define SC_P_SCU_BOOT_MODE2_SCU_DSC_BOOT_MODE2 SC_P_SCU_BOOT_MODE2 0
-#define SC_P_SCU_BOOT_MODE3_SCU_DSC_BOOT_MODE3 SC_P_SCU_BOOT_MODE3 0
-#define SC_P_SCU_BOOT_MODE4_SCU_DSC_BOOT_MODE4 SC_P_SCU_BOOT_MODE4 0
-#define SC_P_SCU_BOOT_MODE4_SCU_PMIC_I2C_SCL SC_P_SCU_BOOT_MODE4 1
-#define SC_P_SCU_BOOT_MODE5_SCU_DSC_BOOT_MODE5 SC_P_SCU_BOOT_MODE5 0
-#define SC_P_SCU_BOOT_MODE5_SCU_PMIC_I2C_SDA SC_P_SCU_BOOT_MODE5 1
-#define SC_P_LVDS0_GPIO00_LVDS0_GPIO0_IO00 SC_P_LVDS0_GPIO00 0
-#define SC_P_LVDS0_GPIO00_LVDS0_PWM0_OUT SC_P_LVDS0_GPIO00 1
-#define SC_P_LVDS0_GPIO00_LSIO_GPIO1_IO04 SC_P_LVDS0_GPIO00 3
-#define SC_P_LVDS0_GPIO01_LVDS0_GPIO0_IO01 SC_P_LVDS0_GPIO01 0
-#define SC_P_LVDS0_GPIO01_LSIO_GPIO1_IO05 SC_P_LVDS0_GPIO01 3
-#define SC_P_LVDS0_I2C0_SCL_LVDS0_I2C0_SCL SC_P_LVDS0_I2C0_SCL 0
-#define SC_P_LVDS0_I2C0_SCL_LVDS0_GPIO0_IO02 SC_P_LVDS0_I2C0_SCL 1
-#define SC_P_LVDS0_I2C0_SCL_LSIO_GPIO1_IO06 SC_P_LVDS0_I2C0_SCL 3
-#define SC_P_LVDS0_I2C0_SDA_LVDS0_I2C0_SDA SC_P_LVDS0_I2C0_SDA 0
-#define SC_P_LVDS0_I2C0_SDA_LVDS0_GPIO0_IO03 SC_P_LVDS0_I2C0_SDA 1
-#define SC_P_LVDS0_I2C0_SDA_LSIO_GPIO1_IO07 SC_P_LVDS0_I2C0_SDA 3
-#define SC_P_LVDS0_I2C1_SCL_LVDS0_I2C1_SCL SC_P_LVDS0_I2C1_SCL 0
-#define SC_P_LVDS0_I2C1_SCL_DMA_UART2_TX SC_P_LVDS0_I2C1_SCL 1
-#define SC_P_LVDS0_I2C1_SCL_LSIO_GPIO1_IO08 SC_P_LVDS0_I2C1_SCL 3
-#define SC_P_LVDS0_I2C1_SDA_LVDS0_I2C1_SDA SC_P_LVDS0_I2C1_SDA 0
-#define SC_P_LVDS0_I2C1_SDA_DMA_UART2_RX SC_P_LVDS0_I2C1_SDA 1
-#define SC_P_LVDS0_I2C1_SDA_LSIO_GPIO1_IO09 SC_P_LVDS0_I2C1_SDA 3
-#define SC_P_LVDS1_GPIO00_LVDS1_GPIO0_IO00 SC_P_LVDS1_GPIO00 0
-#define SC_P_LVDS1_GPIO00_LVDS1_PWM0_OUT SC_P_LVDS1_GPIO00 1
-#define SC_P_LVDS1_GPIO00_LSIO_GPIO1_IO10 SC_P_LVDS1_GPIO00 3
-#define SC_P_LVDS1_GPIO01_LVDS1_GPIO0_IO01 SC_P_LVDS1_GPIO01 0
-#define SC_P_LVDS1_GPIO01_LSIO_GPIO1_IO11 SC_P_LVDS1_GPIO01 3
-#define SC_P_LVDS1_I2C0_SCL_LVDS1_I2C0_SCL SC_P_LVDS1_I2C0_SCL 0
-#define SC_P_LVDS1_I2C0_SCL_LVDS1_GPIO0_IO02 SC_P_LVDS1_I2C0_SCL 1
-#define SC_P_LVDS1_I2C0_SCL_LSIO_GPIO1_IO12 SC_P_LVDS1_I2C0_SCL 3
-#define SC_P_LVDS1_I2C0_SDA_LVDS1_I2C0_SDA SC_P_LVDS1_I2C0_SDA 0
-#define SC_P_LVDS1_I2C0_SDA_LVDS1_GPIO0_IO03 SC_P_LVDS1_I2C0_SDA 1
-#define SC_P_LVDS1_I2C0_SDA_LSIO_GPIO1_IO13 SC_P_LVDS1_I2C0_SDA 3
-#define SC_P_LVDS1_I2C1_SCL_LVDS1_I2C1_SCL SC_P_LVDS1_I2C1_SCL 0
-#define SC_P_LVDS1_I2C1_SCL_DMA_UART3_TX SC_P_LVDS1_I2C1_SCL 1
-#define SC_P_LVDS1_I2C1_SCL_LSIO_GPIO1_IO14 SC_P_LVDS1_I2C1_SCL 3
-#define SC_P_LVDS1_I2C1_SDA_LVDS1_I2C1_SDA SC_P_LVDS1_I2C1_SDA 0
-#define SC_P_LVDS1_I2C1_SDA_DMA_UART3_RX SC_P_LVDS1_I2C1_SDA 1
-#define SC_P_LVDS1_I2C1_SDA_LSIO_GPIO1_IO15 SC_P_LVDS1_I2C1_SDA 3
-#define SC_P_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL SC_P_MIPI_DSI0_I2C0_SCL 0
-#define SC_P_MIPI_DSI0_I2C0_SCL_LSIO_GPIO1_IO16 SC_P_MIPI_DSI0_I2C0_SCL 3
-#define SC_P_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA SC_P_MIPI_DSI0_I2C0_SDA 0
-#define SC_P_MIPI_DSI0_I2C0_SDA_LSIO_GPIO1_IO17 SC_P_MIPI_DSI0_I2C0_SDA 3
-#define SC_P_MIPI_DSI0_GPIO0_00_MIPI_DSI0_GPIO0_IO00 SC_P_MIPI_DSI0_GPIO0_00 0
-#define SC_P_MIPI_DSI0_GPIO0_00_MIPI_DSI0_PWM0_OUT SC_P_MIPI_DSI0_GPIO0_00 1
-#define SC_P_MIPI_DSI0_GPIO0_00_LSIO_GPIO1_IO18 SC_P_MIPI_DSI0_GPIO0_00 3
-#define SC_P_MIPI_DSI0_GPIO0_01_MIPI_DSI0_GPIO0_IO01 SC_P_MIPI_DSI0_GPIO0_01 0
-#define SC_P_MIPI_DSI0_GPIO0_01_LSIO_GPIO1_IO19 SC_P_MIPI_DSI0_GPIO0_01 3
-#define SC_P_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL SC_P_MIPI_DSI1_I2C0_SCL 0
-#define SC_P_MIPI_DSI1_I2C0_SCL_LSIO_GPIO1_IO20 SC_P_MIPI_DSI1_I2C0_SCL 3
-#define SC_P_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA SC_P_MIPI_DSI1_I2C0_SDA 0
-#define SC_P_MIPI_DSI1_I2C0_SDA_LSIO_GPIO1_IO21 SC_P_MIPI_DSI1_I2C0_SDA 3
-#define SC_P_MIPI_DSI1_GPIO0_00_MIPI_DSI1_GPIO0_IO00 SC_P_MIPI_DSI1_GPIO0_00 0
-#define SC_P_MIPI_DSI1_GPIO0_00_MIPI_DSI1_PWM0_OUT SC_P_MIPI_DSI1_GPIO0_00 1
-#define SC_P_MIPI_DSI1_GPIO0_00_LSIO_GPIO1_IO22 SC_P_MIPI_DSI1_GPIO0_00 3
-#define SC_P_MIPI_DSI1_GPIO0_01_MIPI_DSI1_GPIO0_IO01 SC_P_MIPI_DSI1_GPIO0_01 0
-#define SC_P_MIPI_DSI1_GPIO0_01_LSIO_GPIO1_IO23 SC_P_MIPI_DSI1_GPIO0_01 3
-#define SC_P_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_ACM_MCLK_OUT SC_P_MIPI_CSI0_MCLK_OUT 0
-#define SC_P_MIPI_CSI0_MCLK_OUT_LSIO_GPIO1_IO24 SC_P_MIPI_CSI0_MCLK_OUT 3
-#define SC_P_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_I2C0_SCL SC_P_MIPI_CSI0_I2C0_SCL 0
-#define SC_P_MIPI_CSI0_I2C0_SCL_LSIO_GPIO1_IO25 SC_P_MIPI_CSI0_I2C0_SCL 3
-#define SC_P_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_I2C0_SDA SC_P_MIPI_CSI0_I2C0_SDA 0
-#define SC_P_MIPI_CSI0_I2C0_SDA_LSIO_GPIO1_IO26 SC_P_MIPI_CSI0_I2C0_SDA 3
-#define SC_P_MIPI_CSI0_GPIO0_00_MIPI_CSI0_GPIO0_IO00 SC_P_MIPI_CSI0_GPIO0_00 0
-#define SC_P_MIPI_CSI0_GPIO0_00_DMA_I2C0_SCL SC_P_MIPI_CSI0_GPIO0_00 1
-#define SC_P_MIPI_CSI0_GPIO0_00_MIPI_CSI1_I2C0_SCL SC_P_MIPI_CSI0_GPIO0_00 2
-#define SC_P_MIPI_CSI0_GPIO0_00_LSIO_GPIO1_IO27 SC_P_MIPI_CSI0_GPIO0_00 3
-#define SC_P_MIPI_CSI0_GPIO0_01_MIPI_CSI0_GPIO0_IO01 SC_P_MIPI_CSI0_GPIO0_01 0
-#define SC_P_MIPI_CSI0_GPIO0_01_DMA_I2C0_SDA SC_P_MIPI_CSI0_GPIO0_01 1
-#define SC_P_MIPI_CSI0_GPIO0_01_MIPI_CSI1_I2C0_SDA SC_P_MIPI_CSI0_GPIO0_01 2
-#define SC_P_MIPI_CSI0_GPIO0_01_LSIO_GPIO1_IO28 SC_P_MIPI_CSI0_GPIO0_01 3
-#define SC_P_MIPI_CSI1_MCLK_OUT_MIPI_CSI1_ACM_MCLK_OUT SC_P_MIPI_CSI1_MCLK_OUT 0
-#define SC_P_MIPI_CSI1_MCLK_OUT_LSIO_GPIO1_IO29 SC_P_MIPI_CSI1_MCLK_OUT 3
-#define SC_P_MIPI_CSI1_GPIO0_00_MIPI_CSI1_GPIO0_IO00 SC_P_MIPI_CSI1_GPIO0_00 0
-#define SC_P_MIPI_CSI1_GPIO0_00_DMA_UART4_RX SC_P_MIPI_CSI1_GPIO0_00 1
-#define SC_P_MIPI_CSI1_GPIO0_00_LSIO_GPIO1_IO30 SC_P_MIPI_CSI1_GPIO0_00 3
-#define SC_P_MIPI_CSI1_GPIO0_01_MIPI_CSI1_GPIO0_IO01 SC_P_MIPI_CSI1_GPIO0_01 0
-#define SC_P_MIPI_CSI1_GPIO0_01_DMA_UART4_TX SC_P_MIPI_CSI1_GPIO0_01 1
-#define SC_P_MIPI_CSI1_GPIO0_01_LSIO_GPIO1_IO31 SC_P_MIPI_CSI1_GPIO0_01 3
-#define SC_P_MIPI_CSI1_I2C0_SCL_MIPI_CSI1_I2C0_SCL SC_P_MIPI_CSI1_I2C0_SCL 0
-#define SC_P_MIPI_CSI1_I2C0_SCL_LSIO_GPIO2_IO00 SC_P_MIPI_CSI1_I2C0_SCL 3
-#define SC_P_MIPI_CSI1_I2C0_SDA_MIPI_CSI1_I2C0_SDA SC_P_MIPI_CSI1_I2C0_SDA 0
-#define SC_P_MIPI_CSI1_I2C0_SDA_LSIO_GPIO2_IO01 SC_P_MIPI_CSI1_I2C0_SDA 3
-#define SC_P_HDMI_TX0_TS_SCL_HDMI_TX0_I2C0_SCL SC_P_HDMI_TX0_TS_SCL 0
-#define SC_P_HDMI_TX0_TS_SCL_DMA_I2C0_SCL SC_P_HDMI_TX0_TS_SCL 1
-#define SC_P_HDMI_TX0_TS_SCL_LSIO_GPIO2_IO02 SC_P_HDMI_TX0_TS_SCL 3
-#define SC_P_HDMI_TX0_TS_SDA_HDMI_TX0_I2C0_SDA SC_P_HDMI_TX0_TS_SDA 0
-#define SC_P_HDMI_TX0_TS_SDA_DMA_I2C0_SDA SC_P_HDMI_TX0_TS_SDA 1
-#define SC_P_HDMI_TX0_TS_SDA_LSIO_GPIO2_IO03 SC_P_HDMI_TX0_TS_SDA 3
-#define SC_P_ESAI1_FSR_AUD_ESAI1_FSR SC_P_ESAI1_FSR 0
-#define SC_P_ESAI1_FSR_LSIO_GPIO2_IO04 SC_P_ESAI1_FSR 3
-#define SC_P_ESAI1_FST_AUD_ESAI1_FST SC_P_ESAI1_FST 0
-#define SC_P_ESAI1_FST_AUD_SPDIF0_EXT_CLK SC_P_ESAI1_FST 1
-#define SC_P_ESAI1_FST_LSIO_GPIO2_IO05 SC_P_ESAI1_FST 3
-#define SC_P_ESAI1_SCKR_AUD_ESAI1_SCKR SC_P_ESAI1_SCKR 0
-#define SC_P_ESAI1_SCKR_LSIO_GPIO2_IO06 SC_P_ESAI1_SCKR 3
-#define SC_P_ESAI1_SCKT_AUD_ESAI1_SCKT SC_P_ESAI1_SCKT 0
-#define SC_P_ESAI1_SCKT_AUD_SAI2_RXC SC_P_ESAI1_SCKT 1
-#define SC_P_ESAI1_SCKT_AUD_SPDIF0_EXT_CLK SC_P_ESAI1_SCKT 2
-#define SC_P_ESAI1_SCKT_LSIO_GPIO2_IO07 SC_P_ESAI1_SCKT 3
-#define SC_P_ESAI1_TX0_AUD_ESAI1_TX0 SC_P_ESAI1_TX0 0
-#define SC_P_ESAI1_TX0_AUD_SAI2_RXD SC_P_ESAI1_TX0 1
-#define SC_P_ESAI1_TX0_AUD_SPDIF0_RX SC_P_ESAI1_TX0 2
-#define SC_P_ESAI1_TX0_LSIO_GPIO2_IO08 SC_P_ESAI1_TX0 3
-#define SC_P_ESAI1_TX1_AUD_ESAI1_TX1 SC_P_ESAI1_TX1 0
-#define SC_P_ESAI1_TX1_AUD_SAI2_RXFS SC_P_ESAI1_TX1 1
-#define SC_P_ESAI1_TX1_AUD_SPDIF0_TX SC_P_ESAI1_TX1 2
-#define SC_P_ESAI1_TX1_LSIO_GPIO2_IO09 SC_P_ESAI1_TX1 3
-#define SC_P_ESAI1_TX2_RX3_AUD_ESAI1_TX2_RX3 SC_P_ESAI1_TX2_RX3 0
-#define SC_P_ESAI1_TX2_RX3_AUD_SPDIF0_RX SC_P_ESAI1_TX2_RX3 1
-#define SC_P_ESAI1_TX2_RX3_LSIO_GPIO2_IO10 SC_P_ESAI1_TX2_RX3 3
-#define SC_P_ESAI1_TX3_RX2_AUD_ESAI1_TX3_RX2 SC_P_ESAI1_TX3_RX2 0
-#define SC_P_ESAI1_TX3_RX2_AUD_SPDIF0_TX SC_P_ESAI1_TX3_RX2 1
-#define SC_P_ESAI1_TX3_RX2_LSIO_GPIO2_IO11 SC_P_ESAI1_TX3_RX2 3
-#define SC_P_ESAI1_TX4_RX1_AUD_ESAI1_TX4_RX1 SC_P_ESAI1_TX4_RX1 0
-#define SC_P_ESAI1_TX4_RX1_LSIO_GPIO2_IO12 SC_P_ESAI1_TX4_RX1 3
-#define SC_P_ESAI1_TX5_RX0_AUD_ESAI1_TX5_RX0 SC_P_ESAI1_TX5_RX0 0
-#define SC_P_ESAI1_TX5_RX0_LSIO_GPIO2_IO13 SC_P_ESAI1_TX5_RX0 3
-#define SC_P_SPDIF0_RX_AUD_SPDIF0_RX SC_P_SPDIF0_RX 0
-#define SC_P_SPDIF0_RX_AUD_MQS_R SC_P_SPDIF0_RX 1
-#define SC_P_SPDIF0_RX_AUD_ACM_MCLK_IN1 SC_P_SPDIF0_RX 2
-#define SC_P_SPDIF0_RX_LSIO_GPIO2_IO14 SC_P_SPDIF0_RX 3
-#define SC_P_SPDIF0_TX_AUD_SPDIF0_TX SC_P_SPDIF0_TX 0
-#define SC_P_SPDIF0_TX_AUD_MQS_L SC_P_SPDIF0_TX 1
-#define SC_P_SPDIF0_TX_AUD_ACM_MCLK_OUT1 SC_P_SPDIF0_TX 2
-#define SC_P_SPDIF0_TX_LSIO_GPIO2_IO15 SC_P_SPDIF0_TX 3
-#define SC_P_SPDIF0_EXT_CLK_AUD_SPDIF0_EXT_CLK SC_P_SPDIF0_EXT_CLK 0
-#define SC_P_SPDIF0_EXT_CLK_DMA_DMA0_REQ_IN0 SC_P_SPDIF0_EXT_CLK 1
-#define SC_P_SPDIF0_EXT_CLK_LSIO_GPIO2_IO16 SC_P_SPDIF0_EXT_CLK 3
-#define SC_P_SPI3_SCK_DMA_SPI3_SCK SC_P_SPI3_SCK 0
-#define SC_P_SPI3_SCK_LSIO_GPIO2_IO17 SC_P_SPI3_SCK 3
-#define SC_P_SPI3_SDO_DMA_SPI3_SDO SC_P_SPI3_SDO 0
-#define SC_P_SPI3_SDO_DMA_FTM_CH0 SC_P_SPI3_SDO 1
-#define SC_P_SPI3_SDO_LSIO_GPIO2_IO18 SC_P_SPI3_SDO 3
-#define SC_P_SPI3_SDI_DMA_SPI3_SDI SC_P_SPI3_SDI 0
-#define SC_P_SPI3_SDI_DMA_FTM_CH1 SC_P_SPI3_SDI 1
-#define SC_P_SPI3_SDI_LSIO_GPIO2_IO19 SC_P_SPI3_SDI 3
-#define SC_P_SPI3_CS0_DMA_SPI3_CS0 SC_P_SPI3_CS0 0
-#define SC_P_SPI3_CS0_DMA_FTM_CH2 SC_P_SPI3_CS0 1
-#define SC_P_SPI3_CS0_LSIO_GPIO2_IO20 SC_P_SPI3_CS0 3
-#define SC_P_SPI3_CS1_DMA_SPI3_CS1 SC_P_SPI3_CS1 0
-#define SC_P_SPI3_CS1_LSIO_GPIO2_IO21 SC_P_SPI3_CS1 3
-#define SC_P_ESAI0_FSR_AUD_ESAI0_FSR SC_P_ESAI0_FSR 0
-#define SC_P_ESAI0_FSR_LSIO_GPIO2_IO22 SC_P_ESAI0_FSR 3
-#define SC_P_ESAI0_FST_AUD_ESAI0_FST SC_P_ESAI0_FST 0
-#define SC_P_ESAI0_FST_LSIO_GPIO2_IO23 SC_P_ESAI0_FST 3
-#define SC_P_ESAI0_SCKR_AUD_ESAI0_SCKR SC_P_ESAI0_SCKR 0
-#define SC_P_ESAI0_SCKR_LSIO_GPIO2_IO24 SC_P_ESAI0_SCKR 3
-#define SC_P_ESAI0_SCKT_AUD_ESAI0_SCKT SC_P_ESAI0_SCKT 0
-#define SC_P_ESAI0_SCKT_LSIO_GPIO2_IO25 SC_P_ESAI0_SCKT 3
-#define SC_P_ESAI0_TX0_AUD_ESAI0_TX0 SC_P_ESAI0_TX0 0
-#define SC_P_ESAI0_TX0_LSIO_GPIO2_IO26 SC_P_ESAI0_TX0 3
-#define SC_P_ESAI0_TX1_AUD_ESAI0_TX1 SC_P_ESAI0_TX1 0
-#define SC_P_ESAI0_TX1_LSIO_GPIO2_IO27 SC_P_ESAI0_TX1 3
-#define SC_P_ESAI0_TX2_RX3_AUD_ESAI0_TX2_RX3 SC_P_ESAI0_TX2_RX3 0
-#define SC_P_ESAI0_TX2_RX3_LSIO_GPIO2_IO28 SC_P_ESAI0_TX2_RX3 3
-#define SC_P_ESAI0_TX3_RX2_AUD_ESAI0_TX3_RX2 SC_P_ESAI0_TX3_RX2 0
-#define SC_P_ESAI0_TX3_RX2_LSIO_GPIO2_IO29 SC_P_ESAI0_TX3_RX2 3
-#define SC_P_ESAI0_TX4_RX1_AUD_ESAI0_TX4_RX1 SC_P_ESAI0_TX4_RX1 0
-#define SC_P_ESAI0_TX4_RX1_LSIO_GPIO2_IO30 SC_P_ESAI0_TX4_RX1 3
-#define SC_P_ESAI0_TX5_RX0_AUD_ESAI0_TX5_RX0 SC_P_ESAI0_TX5_RX0 0
-#define SC_P_ESAI0_TX5_RX0_LSIO_GPIO2_IO31 SC_P_ESAI0_TX5_RX0 3
-#define SC_P_MCLK_IN0_AUD_ACM_MCLK_IN0 SC_P_MCLK_IN0 0
-#define SC_P_MCLK_IN0_AUD_ESAI0_RX_HF_CLK SC_P_MCLK_IN0 1
-#define SC_P_MCLK_IN0_AUD_ESAI1_RX_HF_CLK SC_P_MCLK_IN0 2
-#define SC_P_MCLK_IN0_LSIO_GPIO3_IO00 SC_P_MCLK_IN0 3
-#define SC_P_MCLK_OUT0_AUD_ACM_MCLK_OUT0 SC_P_MCLK_OUT0 0
-#define SC_P_MCLK_OUT0_AUD_ESAI0_TX_HF_CLK SC_P_MCLK_OUT0 1
-#define SC_P_MCLK_OUT0_AUD_ESAI1_TX_HF_CLK SC_P_MCLK_OUT0 2
-#define SC_P_MCLK_OUT0_LSIO_GPIO3_IO01 SC_P_MCLK_OUT0 3
-#define SC_P_SPI0_SCK_DMA_SPI0_SCK SC_P_SPI0_SCK 0
-#define SC_P_SPI0_SCK_AUD_SAI0_RXC SC_P_SPI0_SCK 1
-#define SC_P_SPI0_SCK_LSIO_GPIO3_IO02 SC_P_SPI0_SCK 3
-#define SC_P_SPI0_SDO_DMA_SPI0_SDO SC_P_SPI0_SDO 0
-#define SC_P_SPI0_SDO_AUD_SAI0_TXD SC_P_SPI0_SDO 1
-#define SC_P_SPI0_SDO_LSIO_GPIO3_IO03 SC_P_SPI0_SDO 3
-#define SC_P_SPI0_SDI_DMA_SPI0_SDI SC_P_SPI0_SDI 0
-#define SC_P_SPI0_SDI_AUD_SAI0_RXD SC_P_SPI0_SDI 1
-#define SC_P_SPI0_SDI_LSIO_GPIO3_IO04 SC_P_SPI0_SDI 3
-#define SC_P_SPI0_CS0_DMA_SPI0_CS0 SC_P_SPI0_CS0 0
-#define SC_P_SPI0_CS0_AUD_SAI0_RXFS SC_P_SPI0_CS0 1
-#define SC_P_SPI0_CS0_LSIO_GPIO3_IO05 SC_P_SPI0_CS0 3
-#define SC_P_SPI0_CS1_DMA_SPI0_CS1 SC_P_SPI0_CS1 0
-#define SC_P_SPI0_CS1_AUD_SAI0_TXC SC_P_SPI0_CS1 1
-#define SC_P_SPI0_CS1_LSIO_GPIO3_IO06 SC_P_SPI0_CS1 3
-#define SC_P_SPI2_SCK_DMA_SPI2_SCK SC_P_SPI2_SCK 0
-#define SC_P_SPI2_SCK_LSIO_GPIO3_IO07 SC_P_SPI2_SCK 3
-#define SC_P_SPI2_SDO_DMA_SPI2_SDO SC_P_SPI2_SDO 0
-#define SC_P_SPI2_SDO_LSIO_GPIO3_IO08 SC_P_SPI2_SDO 3
-#define SC_P_SPI2_SDI_DMA_SPI2_SDI SC_P_SPI2_SDI 0
-#define SC_P_SPI2_SDI_LSIO_GPIO3_IO09 SC_P_SPI2_SDI 3
-#define SC_P_SPI2_CS0_DMA_SPI2_CS0 SC_P_SPI2_CS0 0
-#define SC_P_SPI2_CS0_LSIO_GPIO3_IO10 SC_P_SPI2_CS0 3
-#define SC_P_SPI2_CS1_DMA_SPI2_CS1 SC_P_SPI2_CS1 0
-#define SC_P_SPI2_CS1_AUD_SAI0_TXFS SC_P_SPI2_CS1 1
-#define SC_P_SPI2_CS1_LSIO_GPIO3_IO11 SC_P_SPI2_CS1 3
-#define SC_P_SAI1_RXC_AUD_SAI1_RXC SC_P_SAI1_RXC 0
-#define SC_P_SAI1_RXC_AUD_SAI0_TXD SC_P_SAI1_RXC 1
-#define SC_P_SAI1_RXC_LSIO_GPIO3_IO12 SC_P_SAI1_RXC 3
-#define SC_P_SAI1_RXD_AUD_SAI1_RXD SC_P_SAI1_RXD 0
-#define SC_P_SAI1_RXD_AUD_SAI0_TXFS SC_P_SAI1_RXD 1
-#define SC_P_SAI1_RXD_LSIO_GPIO3_IO13 SC_P_SAI1_RXD 3
-#define SC_P_SAI1_RXFS_AUD_SAI1_RXFS SC_P_SAI1_RXFS 0
-#define SC_P_SAI1_RXFS_AUD_SAI0_RXD SC_P_SAI1_RXFS 1
-#define SC_P_SAI1_RXFS_LSIO_GPIO3_IO14 SC_P_SAI1_RXFS 3
-#define SC_P_SAI1_TXC_AUD_SAI1_TXC SC_P_SAI1_TXC 0
-#define SC_P_SAI1_TXC_AUD_SAI0_TXC SC_P_SAI1_TXC 1
-#define SC_P_SAI1_TXC_LSIO_GPIO3_IO15 SC_P_SAI1_TXC 3
-#define SC_P_SAI1_TXD_AUD_SAI1_TXD SC_P_SAI1_TXD 0
-#define SC_P_SAI1_TXD_AUD_SAI1_RXC SC_P_SAI1_TXD 1
-#define SC_P_SAI1_TXD_LSIO_GPIO3_IO16 SC_P_SAI1_TXD 3
-#define SC_P_SAI1_TXFS_AUD_SAI1_TXFS SC_P_SAI1_TXFS 0
-#define SC_P_SAI1_TXFS_AUD_SAI1_RXFS SC_P_SAI1_TXFS 1
-#define SC_P_SAI1_TXFS_LSIO_GPIO3_IO17 SC_P_SAI1_TXFS 3
-#define SC_P_ADC_IN7_DMA_ADC1_IN3 SC_P_ADC_IN7 0
-#define SC_P_ADC_IN7_DMA_SPI1_CS1 SC_P_ADC_IN7 1
-#define SC_P_ADC_IN7_LSIO_KPP0_ROW3 SC_P_ADC_IN7 2
-#define SC_P_ADC_IN7_LSIO_GPIO3_IO25 SC_P_ADC_IN7 3
-#define SC_P_ADC_IN6_DMA_ADC1_IN2 SC_P_ADC_IN6 0
-#define SC_P_ADC_IN6_DMA_SPI1_CS0 SC_P_ADC_IN6 1
-#define SC_P_ADC_IN6_LSIO_KPP0_ROW2 SC_P_ADC_IN6 2
-#define SC_P_ADC_IN6_LSIO_GPIO3_IO24 SC_P_ADC_IN6 3
-#define SC_P_ADC_IN5_DMA_ADC1_IN1 SC_P_ADC_IN5 0
-#define SC_P_ADC_IN5_DMA_SPI1_SDI SC_P_ADC_IN5 1
-#define SC_P_ADC_IN5_LSIO_KPP0_ROW1 SC_P_ADC_IN5 2
-#define SC_P_ADC_IN5_LSIO_GPIO3_IO23 SC_P_ADC_IN5 3
-#define SC_P_ADC_IN4_DMA_ADC1_IN0 SC_P_ADC_IN4 0
-#define SC_P_ADC_IN4_DMA_SPI1_SDO SC_P_ADC_IN4 1
-#define SC_P_ADC_IN4_LSIO_KPP0_ROW0 SC_P_ADC_IN4 2
-#define SC_P_ADC_IN4_LSIO_GPIO3_IO22 SC_P_ADC_IN4 3
-#define SC_P_ADC_IN3_DMA_ADC0_IN3 SC_P_ADC_IN3 0
-#define SC_P_ADC_IN3_DMA_SPI1_SCK SC_P_ADC_IN3 1
-#define SC_P_ADC_IN3_LSIO_KPP0_COL3 SC_P_ADC_IN3 2
-#define SC_P_ADC_IN3_LSIO_GPIO3_IO21 SC_P_ADC_IN3 3
-#define SC_P_ADC_IN2_DMA_ADC0_IN2 SC_P_ADC_IN2 0
-#define SC_P_ADC_IN2_LSIO_KPP0_COL2 SC_P_ADC_IN2 2
-#define SC_P_ADC_IN2_LSIO_GPIO3_IO20 SC_P_ADC_IN2 3
-#define SC_P_ADC_IN1_DMA_ADC0_IN1 SC_P_ADC_IN1 0
-#define SC_P_ADC_IN1_LSIO_KPP0_COL1 SC_P_ADC_IN1 2
-#define SC_P_ADC_IN1_LSIO_GPIO3_IO19 SC_P_ADC_IN1 3
-#define SC_P_ADC_IN0_DMA_ADC0_IN0 SC_P_ADC_IN0 0
-#define SC_P_ADC_IN0_LSIO_KPP0_COL0 SC_P_ADC_IN0 2
-#define SC_P_ADC_IN0_LSIO_GPIO3_IO18 SC_P_ADC_IN0 3
-#define SC_P_MLB_SIG_CONN_MLB_SIG SC_P_MLB_SIG 0
-#define SC_P_MLB_SIG_AUD_SAI3_RXC SC_P_MLB_SIG 1
-#define SC_P_MLB_SIG_LSIO_GPIO3_IO26 SC_P_MLB_SIG 3
-#define SC_P_MLB_CLK_CONN_MLB_CLK SC_P_MLB_CLK 0
-#define SC_P_MLB_CLK_AUD_SAI3_RXFS SC_P_MLB_CLK 1
-#define SC_P_MLB_CLK_LSIO_GPIO3_IO27 SC_P_MLB_CLK 3
-#define SC_P_MLB_DATA_CONN_MLB_DATA SC_P_MLB_DATA 0
-#define SC_P_MLB_DATA_AUD_SAI3_RXD SC_P_MLB_DATA 1
-#define SC_P_MLB_DATA_LSIO_GPIO3_IO28 SC_P_MLB_DATA 3
-#define SC_P_FLEXCAN0_RX_DMA_FLEXCAN0_RX SC_P_FLEXCAN0_RX 0
-#define SC_P_FLEXCAN0_RX_LSIO_GPIO3_IO29 SC_P_FLEXCAN0_RX 3
-#define SC_P_FLEXCAN0_TX_DMA_FLEXCAN0_TX SC_P_FLEXCAN0_TX 0
-#define SC_P_FLEXCAN0_TX_LSIO_GPIO3_IO30 SC_P_FLEXCAN0_TX 3
-#define SC_P_FLEXCAN1_RX_DMA_FLEXCAN1_RX SC_P_FLEXCAN1_RX 0
-#define SC_P_FLEXCAN1_RX_LSIO_GPIO3_IO31 SC_P_FLEXCAN1_RX 3
-#define SC_P_FLEXCAN1_TX_DMA_FLEXCAN1_TX SC_P_FLEXCAN1_TX 0
-#define SC_P_FLEXCAN1_TX_LSIO_GPIO4_IO00 SC_P_FLEXCAN1_TX 3
-#define SC_P_FLEXCAN2_RX_DMA_FLEXCAN2_RX SC_P_FLEXCAN2_RX 0
-#define SC_P_FLEXCAN2_RX_LSIO_GPIO4_IO01 SC_P_FLEXCAN2_RX 3
-#define SC_P_FLEXCAN2_TX_DMA_FLEXCAN2_TX SC_P_FLEXCAN2_TX 0
-#define SC_P_FLEXCAN2_TX_LSIO_GPIO4_IO02 SC_P_FLEXCAN2_TX 3
-#define SC_P_USB_SS3_TC0_DMA_I2C1_SCL SC_P_USB_SS3_TC0 0
-#define SC_P_USB_SS3_TC0_CONN_USB_OTG1_PWR SC_P_USB_SS3_TC0 1
-#define SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03 SC_P_USB_SS3_TC0 3
-#define SC_P_USB_SS3_TC1_DMA_I2C1_SCL SC_P_USB_SS3_TC1 0
-#define SC_P_USB_SS3_TC1_CONN_USB_OTG2_PWR SC_P_USB_SS3_TC1 1
-#define SC_P_USB_SS3_TC1_LSIO_GPIO4_IO04 SC_P_USB_SS3_TC1 3
-#define SC_P_USB_SS3_TC2_DMA_I2C1_SDA SC_P_USB_SS3_TC2 0
-#define SC_P_USB_SS3_TC2_CONN_USB_OTG1_OC SC_P_USB_SS3_TC2 1
-#define SC_P_USB_SS3_TC2_LSIO_GPIO4_IO05 SC_P_USB_SS3_TC2 3
-#define SC_P_USB_SS3_TC3_DMA_I2C1_SDA SC_P_USB_SS3_TC3 0
-#define SC_P_USB_SS3_TC3_CONN_USB_OTG2_OC SC_P_USB_SS3_TC3 1
-#define SC_P_USB_SS3_TC3_LSIO_GPIO4_IO06 SC_P_USB_SS3_TC3 3
-#define SC_P_USDHC1_RESET_B_CONN_USDHC1_RESET_B SC_P_USDHC1_RESET_B 0
-#define SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO07 SC_P_USDHC1_RESET_B 3
-#define SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT SC_P_USDHC1_VSELECT 0
-#define SC_P_USDHC1_VSELECT_LSIO_GPIO4_IO08 SC_P_USDHC1_VSELECT 3
-#define SC_P_USDHC2_RESET_B_CONN_USDHC2_RESET_B SC_P_USDHC2_RESET_B 0
-#define SC_P_USDHC2_RESET_B_LSIO_GPIO4_IO09 SC_P_USDHC2_RESET_B 3
-#define SC_P_USDHC2_VSELECT_CONN_USDHC2_VSELECT SC_P_USDHC2_VSELECT 0
-#define SC_P_USDHC2_VSELECT_LSIO_GPIO4_IO10 SC_P_USDHC2_VSELECT 3
-#define SC_P_USDHC2_WP_CONN_USDHC2_WP SC_P_USDHC2_WP 0
-#define SC_P_USDHC2_WP_LSIO_GPIO4_IO11 SC_P_USDHC2_WP 3
-#define SC_P_USDHC2_CD_B_CONN_USDHC2_CD_B SC_P_USDHC2_CD_B 0
-#define SC_P_USDHC2_CD_B_LSIO_GPIO4_IO12 SC_P_USDHC2_CD_B 3
-#define SC_P_ENET0_MDIO_CONN_ENET0_MDIO SC_P_ENET0_MDIO 0
-#define SC_P_ENET0_MDIO_DMA_I2C4_SDA SC_P_ENET0_MDIO 1
-#define SC_P_ENET0_MDIO_LSIO_GPIO4_IO13 SC_P_ENET0_MDIO 3
-#define SC_P_ENET0_MDC_CONN_ENET0_MDC SC_P_ENET0_MDC 0
-#define SC_P_ENET0_MDC_DMA_I2C4_SCL SC_P_ENET0_MDC 1
-#define SC_P_ENET0_MDC_LSIO_GPIO4_IO14 SC_P_ENET0_MDC 3
-#define SC_P_ENET0_REFCLK_125M_25M_CONN_ENET0_REFCLK_125M_25M SC_P_ENET0_REFCLK_125M_25M 0
-#define SC_P_ENET0_REFCLK_125M_25M_CONN_ENET0_PPS SC_P_ENET0_REFCLK_125M_25M 1
-#define SC_P_ENET0_REFCLK_125M_25M_LSIO_GPIO4_IO15 SC_P_ENET0_REFCLK_125M_25M 3
-#define SC_P_ENET1_REFCLK_125M_25M_CONN_ENET1_REFCLK_125M_25M SC_P_ENET1_REFCLK_125M_25M 0
-#define SC_P_ENET1_REFCLK_125M_25M_CONN_ENET1_PPS SC_P_ENET1_REFCLK_125M_25M 1
-#define SC_P_ENET1_REFCLK_125M_25M_LSIO_GPIO4_IO16 SC_P_ENET1_REFCLK_125M_25M 3
-#define SC_P_ENET1_MDIO_CONN_ENET1_MDIO SC_P_ENET1_MDIO 0
-#define SC_P_ENET1_MDIO_DMA_I2C4_SDA SC_P_ENET1_MDIO 1
-#define SC_P_ENET1_MDIO_LSIO_GPIO4_IO17 SC_P_ENET1_MDIO 3
-#define SC_P_ENET1_MDC_CONN_ENET1_MDC SC_P_ENET1_MDC 0
-#define SC_P_ENET1_MDC_DMA_I2C4_SCL SC_P_ENET1_MDC 1
-#define SC_P_ENET1_MDC_LSIO_GPIO4_IO18 SC_P_ENET1_MDC 3
-#define SC_P_QSPI1A_SS0_B_LSIO_QSPI1A_SS0_B SC_P_QSPI1A_SS0_B 0
-#define SC_P_QSPI1A_SS0_B_LSIO_GPIO4_IO19 SC_P_QSPI1A_SS0_B 3
-#define SC_P_QSPI1A_SS1_B_LSIO_QSPI1A_SS1_B SC_P_QSPI1A_SS1_B 0
-#define SC_P_QSPI1A_SS1_B_LSIO_QSPI1A_SCLK2 SC_P_QSPI1A_SS1_B 1
-#define SC_P_QSPI1A_SS1_B_LSIO_GPIO4_IO20 SC_P_QSPI1A_SS1_B 3
-#define SC_P_QSPI1A_SCLK_LSIO_QSPI1A_SCLK SC_P_QSPI1A_SCLK 0
-#define SC_P_QSPI1A_SCLK_LSIO_GPIO4_IO21 SC_P_QSPI1A_SCLK 3
-#define SC_P_QSPI1A_DQS_LSIO_QSPI1A_DQS SC_P_QSPI1A_DQS 0
-#define SC_P_QSPI1A_DQS_LSIO_GPIO4_IO22 SC_P_QSPI1A_DQS 3
-#define SC_P_QSPI1A_DATA3_LSIO_QSPI1A_DATA3 SC_P_QSPI1A_DATA3 0
-#define SC_P_QSPI1A_DATA3_DMA_I2C1_SDA SC_P_QSPI1A_DATA3 1
-#define SC_P_QSPI1A_DATA3_CONN_USB_OTG1_OC SC_P_QSPI1A_DATA3 2
-#define SC_P_QSPI1A_DATA3_LSIO_GPIO4_IO23 SC_P_QSPI1A_DATA3 3
-#define SC_P_QSPI1A_DATA2_LSIO_QSPI1A_DATA2 SC_P_QSPI1A_DATA2 0
-#define SC_P_QSPI1A_DATA2_DMA_I2C1_SCL SC_P_QSPI1A_DATA2 1
-#define SC_P_QSPI1A_DATA2_CONN_USB_OTG2_PWR SC_P_QSPI1A_DATA2 2
-#define SC_P_QSPI1A_DATA2_LSIO_GPIO4_IO24 SC_P_QSPI1A_DATA2 3
-#define SC_P_QSPI1A_DATA1_LSIO_QSPI1A_DATA1 SC_P_QSPI1A_DATA1 0
-#define SC_P_QSPI1A_DATA1_DMA_I2C1_SDA SC_P_QSPI1A_DATA1 1
-#define SC_P_QSPI1A_DATA1_CONN_USB_OTG2_OC SC_P_QSPI1A_DATA1 2
-#define SC_P_QSPI1A_DATA1_LSIO_GPIO4_IO25 SC_P_QSPI1A_DATA1 3
-#define SC_P_QSPI1A_DATA0_LSIO_QSPI1A_DATA0 SC_P_QSPI1A_DATA0 0
-#define SC_P_QSPI1A_DATA0_LSIO_GPIO4_IO26 SC_P_QSPI1A_DATA0 3
-#define SC_P_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 SC_P_QSPI0A_DATA0 0
-#define SC_P_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 SC_P_QSPI0A_DATA1 0
-#define SC_P_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 SC_P_QSPI0A_DATA2 0
-#define SC_P_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 SC_P_QSPI0A_DATA3 0
-#define SC_P_QSPI0A_DQS_LSIO_QSPI0A_DQS SC_P_QSPI0A_DQS 0
-#define SC_P_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B SC_P_QSPI0A_SS0_B 0
-#define SC_P_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B SC_P_QSPI0A_SS1_B 0
-#define SC_P_QSPI0A_SS1_B_LSIO_QSPI0A_SCLK2 SC_P_QSPI0A_SS1_B 1
-#define SC_P_QSPI0A_SCLK_LSIO_QSPI0A_SCLK SC_P_QSPI0A_SCLK 0
-#define SC_P_QSPI0B_SCLK_LSIO_QSPI0B_SCLK SC_P_QSPI0B_SCLK 0
-#define SC_P_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 SC_P_QSPI0B_DATA0 0
-#define SC_P_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 SC_P_QSPI0B_DATA1 0
-#define SC_P_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 SC_P_QSPI0B_DATA2 0
-#define SC_P_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 SC_P_QSPI0B_DATA3 0
-#define SC_P_QSPI0B_DQS_LSIO_QSPI0B_DQS SC_P_QSPI0B_DQS 0
-#define SC_P_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B SC_P_QSPI0B_SS0_B 0
-#define SC_P_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B SC_P_QSPI0B_SS1_B 0
-#define SC_P_QSPI0B_SS1_B_LSIO_QSPI0B_SCLK2 SC_P_QSPI0B_SS1_B 1
-#define SC_P_PCIE_CTRL0_CLKREQ_B_HSIO_PCIE0_CLKREQ_B SC_P_PCIE_CTRL0_CLKREQ_B 0
-#define SC_P_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO27 SC_P_PCIE_CTRL0_CLKREQ_B 3
-#define SC_P_PCIE_CTRL0_WAKE_B_HSIO_PCIE0_WAKE_B SC_P_PCIE_CTRL0_WAKE_B 0
-#define SC_P_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO28 SC_P_PCIE_CTRL0_WAKE_B 3
-#define SC_P_PCIE_CTRL0_PERST_B_HSIO_PCIE0_PERST_B SC_P_PCIE_CTRL0_PERST_B 0
-#define SC_P_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO29 SC_P_PCIE_CTRL0_PERST_B 3
-#define SC_P_PCIE_CTRL1_CLKREQ_B_HSIO_PCIE1_CLKREQ_B SC_P_PCIE_CTRL1_CLKREQ_B 0
-#define SC_P_PCIE_CTRL1_CLKREQ_B_DMA_I2C1_SDA SC_P_PCIE_CTRL1_CLKREQ_B 1
-#define SC_P_PCIE_CTRL1_CLKREQ_B_CONN_USB_OTG2_OC SC_P_PCIE_CTRL1_CLKREQ_B 2
-#define SC_P_PCIE_CTRL1_CLKREQ_B_LSIO_GPIO4_IO30 SC_P_PCIE_CTRL1_CLKREQ_B 3
-#define SC_P_PCIE_CTRL1_WAKE_B_HSIO_PCIE1_WAKE_B SC_P_PCIE_CTRL1_WAKE_B 0
-#define SC_P_PCIE_CTRL1_WAKE_B_DMA_I2C1_SCL SC_P_PCIE_CTRL1_WAKE_B 1
-#define SC_P_PCIE_CTRL1_WAKE_B_CONN_USB_OTG2_PWR SC_P_PCIE_CTRL1_WAKE_B 2
-#define SC_P_PCIE_CTRL1_WAKE_B_LSIO_GPIO4_IO31 SC_P_PCIE_CTRL1_WAKE_B 3
-#define SC_P_PCIE_CTRL1_PERST_B_HSIO_PCIE1_PERST_B SC_P_PCIE_CTRL1_PERST_B 0
-#define SC_P_PCIE_CTRL1_PERST_B_DMA_I2C1_SCL SC_P_PCIE_CTRL1_PERST_B 1
-#define SC_P_PCIE_CTRL1_PERST_B_CONN_USB_OTG1_PWR SC_P_PCIE_CTRL1_PERST_B 2
-#define SC_P_PCIE_CTRL1_PERST_B_LSIO_GPIO5_IO00 SC_P_PCIE_CTRL1_PERST_B 3
-#define SC_P_USB_HSIC0_DATA_CONN_USB_HSIC0_DATA SC_P_USB_HSIC0_DATA 0
-#define SC_P_USB_HSIC0_DATA_DMA_I2C1_SDA SC_P_USB_HSIC0_DATA 1
-#define SC_P_USB_HSIC0_DATA_LSIO_GPIO5_IO01 SC_P_USB_HSIC0_DATA 3
-#define SC_P_USB_HSIC0_STROBE_CONN_USB_HSIC0_STROBE SC_P_USB_HSIC0_STROBE 0
-#define SC_P_USB_HSIC0_STROBE_DMA_I2C1_SCL SC_P_USB_HSIC0_STROBE 1
-#define SC_P_USB_HSIC0_STROBE_LSIO_GPIO5_IO02 SC_P_USB_HSIC0_STROBE 3
-#define SC_P_EMMC0_CLK_CONN_EMMC0_CLK SC_P_EMMC0_CLK 0
-#define SC_P_EMMC0_CLK_CONN_NAND_READY_B SC_P_EMMC0_CLK 1
-#define SC_P_EMMC0_CMD_CONN_EMMC0_CMD SC_P_EMMC0_CMD 0
-#define SC_P_EMMC0_CMD_CONN_NAND_DQS SC_P_EMMC0_CMD 1
-#define SC_P_EMMC0_CMD_AUD_MQS_R SC_P_EMMC0_CMD 2
-#define SC_P_EMMC0_CMD_LSIO_GPIO5_IO03 SC_P_EMMC0_CMD 3
-#define SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 SC_P_EMMC0_DATA0 0
-#define SC_P_EMMC0_DATA0_CONN_NAND_DATA00 SC_P_EMMC0_DATA0 1
-#define SC_P_EMMC0_DATA0_LSIO_GPIO5_IO04 SC_P_EMMC0_DATA0 3
-#define SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 SC_P_EMMC0_DATA1 0
-#define SC_P_EMMC0_DATA1_CONN_NAND_DATA01 SC_P_EMMC0_DATA1 1
-#define SC_P_EMMC0_DATA1_LSIO_GPIO5_IO05 SC_P_EMMC0_DATA1 3
-#define SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 SC_P_EMMC0_DATA2 0
-#define SC_P_EMMC0_DATA2_CONN_NAND_DATA02 SC_P_EMMC0_DATA2 1
-#define SC_P_EMMC0_DATA2_LSIO_GPIO5_IO06 SC_P_EMMC0_DATA2 3
-#define SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 SC_P_EMMC0_DATA3 0
-#define SC_P_EMMC0_DATA3_CONN_NAND_DATA03 SC_P_EMMC0_DATA3 1
-#define SC_P_EMMC0_DATA3_LSIO_GPIO5_IO07 SC_P_EMMC0_DATA3 3
-#define SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 SC_P_EMMC0_DATA4 0
-#define SC_P_EMMC0_DATA4_CONN_NAND_DATA04 SC_P_EMMC0_DATA4 1
-#define SC_P_EMMC0_DATA4_LSIO_GPIO5_IO08 SC_P_EMMC0_DATA4 3
-#define SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 SC_P_EMMC0_DATA5 0
-#define SC_P_EMMC0_DATA5_CONN_NAND_DATA05 SC_P_EMMC0_DATA5 1
-#define SC_P_EMMC0_DATA5_LSIO_GPIO5_IO09 SC_P_EMMC0_DATA5 3
-#define SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 SC_P_EMMC0_DATA6 0
-#define SC_P_EMMC0_DATA6_CONN_NAND_DATA06 SC_P_EMMC0_DATA6 1
-#define SC_P_EMMC0_DATA6_LSIO_GPIO5_IO10 SC_P_EMMC0_DATA6 3
-#define SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 SC_P_EMMC0_DATA7 0
-#define SC_P_EMMC0_DATA7_CONN_NAND_DATA07 SC_P_EMMC0_DATA7 1
-#define SC_P_EMMC0_DATA7_LSIO_GPIO5_IO11 SC_P_EMMC0_DATA7 3
-#define SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE SC_P_EMMC0_STROBE 0
-#define SC_P_EMMC0_STROBE_CONN_NAND_CLE SC_P_EMMC0_STROBE 1
-#define SC_P_EMMC0_STROBE_LSIO_GPIO5_IO12 SC_P_EMMC0_STROBE 3
-#define SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B SC_P_EMMC0_RESET_B 0
-#define SC_P_EMMC0_RESET_B_CONN_NAND_WP_B SC_P_EMMC0_RESET_B 1
-#define SC_P_EMMC0_RESET_B_CONN_USDHC1_VSELECT SC_P_EMMC0_RESET_B 2
-#define SC_P_EMMC0_RESET_B_LSIO_GPIO5_IO13 SC_P_EMMC0_RESET_B 3
-#define SC_P_USDHC1_CLK_CONN_USDHC1_CLK SC_P_USDHC1_CLK 0
-#define SC_P_USDHC1_CLK_AUD_MQS_R SC_P_USDHC1_CLK 1
-#define SC_P_USDHC1_CMD_CONN_USDHC1_CMD SC_P_USDHC1_CMD 0
-#define SC_P_USDHC1_CMD_AUD_MQS_L SC_P_USDHC1_CMD 1
-#define SC_P_USDHC1_CMD_LSIO_GPIO5_IO14 SC_P_USDHC1_CMD 3
-#define SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 SC_P_USDHC1_DATA0 0
-#define SC_P_USDHC1_DATA0_CONN_NAND_RE_N SC_P_USDHC1_DATA0 1
-#define SC_P_USDHC1_DATA0_LSIO_GPIO5_IO15 SC_P_USDHC1_DATA0 3
-#define SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 SC_P_USDHC1_DATA1 0
-#define SC_P_USDHC1_DATA1_CONN_NAND_RE_P SC_P_USDHC1_DATA1 1
-#define SC_P_USDHC1_DATA1_LSIO_GPIO5_IO16 SC_P_USDHC1_DATA1 3
-#define SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 SC_P_USDHC1_DATA2 0
-#define SC_P_USDHC1_DATA2_CONN_NAND_DQS_N SC_P_USDHC1_DATA2 1
-#define SC_P_USDHC1_DATA2_LSIO_GPIO5_IO17 SC_P_USDHC1_DATA2 3
-#define SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 SC_P_USDHC1_DATA3 0
-#define SC_P_USDHC1_DATA3_CONN_NAND_DQS_P SC_P_USDHC1_DATA3 1
-#define SC_P_USDHC1_DATA3_LSIO_GPIO5_IO18 SC_P_USDHC1_DATA3 3
-#define SC_P_USDHC1_DATA4_CONN_USDHC1_DATA4 SC_P_USDHC1_DATA4 0
-#define SC_P_USDHC1_DATA4_CONN_NAND_CE0_B SC_P_USDHC1_DATA4 1
-#define SC_P_USDHC1_DATA4_AUD_MQS_R SC_P_USDHC1_DATA4 2
-#define SC_P_USDHC1_DATA4_LSIO_GPIO5_IO19 SC_P_USDHC1_DATA4 3
-#define SC_P_USDHC1_DATA5_CONN_USDHC1_DATA5 SC_P_USDHC1_DATA5 0
-#define SC_P_USDHC1_DATA5_CONN_NAND_RE_B SC_P_USDHC1_DATA5 1
-#define SC_P_USDHC1_DATA5_AUD_MQS_L SC_P_USDHC1_DATA5 2
-#define SC_P_USDHC1_DATA5_LSIO_GPIO5_IO20 SC_P_USDHC1_DATA5 3
-#define SC_P_USDHC1_DATA6_CONN_USDHC1_DATA6 SC_P_USDHC1_DATA6 0
-#define SC_P_USDHC1_DATA6_CONN_NAND_WE_B SC_P_USDHC1_DATA6 1
-#define SC_P_USDHC1_DATA6_CONN_USDHC1_WP SC_P_USDHC1_DATA6 2
-#define SC_P_USDHC1_DATA6_LSIO_GPIO5_IO21 SC_P_USDHC1_DATA6 3
-#define SC_P_USDHC1_DATA7_CONN_USDHC1_DATA7 SC_P_USDHC1_DATA7 0
-#define SC_P_USDHC1_DATA7_CONN_NAND_ALE SC_P_USDHC1_DATA7 1
-#define SC_P_USDHC1_DATA7_CONN_USDHC1_CD_B SC_P_USDHC1_DATA7 2
-#define SC_P_USDHC1_DATA7_LSIO_GPIO5_IO22 SC_P_USDHC1_DATA7 3
-#define SC_P_USDHC1_STROBE_CONN_USDHC1_STROBE SC_P_USDHC1_STROBE 0
-#define SC_P_USDHC1_STROBE_CONN_NAND_CE1_B SC_P_USDHC1_STROBE 1
-#define SC_P_USDHC1_STROBE_CONN_USDHC1_RESET_B SC_P_USDHC1_STROBE 2
-#define SC_P_USDHC1_STROBE_LSIO_GPIO5_IO23 SC_P_USDHC1_STROBE 3
-#define SC_P_USDHC2_CLK_CONN_USDHC2_CLK SC_P_USDHC2_CLK 0
-#define SC_P_USDHC2_CLK_AUD_MQS_R SC_P_USDHC2_CLK 1
-#define SC_P_USDHC2_CLK_LSIO_GPIO5_IO24 SC_P_USDHC2_CLK 3
-#define SC_P_USDHC2_CMD_CONN_USDHC2_CMD SC_P_USDHC2_CMD 0
-#define SC_P_USDHC2_CMD_AUD_MQS_L SC_P_USDHC2_CMD 1
-#define SC_P_USDHC2_CMD_LSIO_GPIO5_IO25 SC_P_USDHC2_CMD 3
-#define SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0 SC_P_USDHC2_DATA0 0
-#define SC_P_USDHC2_DATA0_DMA_UART4_RX SC_P_USDHC2_DATA0 1
-#define SC_P_USDHC2_DATA0_LSIO_GPIO5_IO26 SC_P_USDHC2_DATA0 3
-#define SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1 SC_P_USDHC2_DATA1 0
-#define SC_P_USDHC2_DATA1_DMA_UART4_TX SC_P_USDHC2_DATA1 1
-#define SC_P_USDHC2_DATA1_LSIO_GPIO5_IO27 SC_P_USDHC2_DATA1 3
-#define SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2 SC_P_USDHC2_DATA2 0
-#define SC_P_USDHC2_DATA2_DMA_UART4_CTS_B SC_P_USDHC2_DATA2 1
-#define SC_P_USDHC2_DATA2_LSIO_GPIO5_IO28 SC_P_USDHC2_DATA2 3
-#define SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3 SC_P_USDHC2_DATA3 0
-#define SC_P_USDHC2_DATA3_DMA_UART4_RTS_B SC_P_USDHC2_DATA3 1
-#define SC_P_USDHC2_DATA3_LSIO_GPIO5_IO29 SC_P_USDHC2_DATA3 3
-#define SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC SC_P_ENET0_RGMII_TXC 0
-#define SC_P_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_OUT SC_P_ENET0_RGMII_TXC 1
-#define SC_P_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_IN SC_P_ENET0_RGMII_TXC 2
-#define SC_P_ENET0_RGMII_TXC_LSIO_GPIO5_IO30 SC_P_ENET0_RGMII_TXC 3
-#define SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL SC_P_ENET0_RGMII_TX_CTL 0
-#define SC_P_ENET0_RGMII_TX_CTL_LSIO_GPIO5_IO31 SC_P_ENET0_RGMII_TX_CTL 3
-#define SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 SC_P_ENET0_RGMII_TXD0 0
-#define SC_P_ENET0_RGMII_TXD0_LSIO_GPIO6_IO00 SC_P_ENET0_RGMII_TXD0 3
-#define SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 SC_P_ENET0_RGMII_TXD1 0
-#define SC_P_ENET0_RGMII_TXD1_LSIO_GPIO6_IO01 SC_P_ENET0_RGMII_TXD1 3
-#define SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 SC_P_ENET0_RGMII_TXD2 0
-#define SC_P_ENET0_RGMII_TXD2_DMA_UART3_TX SC_P_ENET0_RGMII_TXD2 1
-#define SC_P_ENET0_RGMII_TXD2_VPU_TSI_S1_VID SC_P_ENET0_RGMII_TXD2 2
-#define SC_P_ENET0_RGMII_TXD2_LSIO_GPIO6_IO02 SC_P_ENET0_RGMII_TXD2 3
-#define SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 SC_P_ENET0_RGMII_TXD3 0
-#define SC_P_ENET0_RGMII_TXD3_DMA_UART3_RTS_B SC_P_ENET0_RGMII_TXD3 1
-#define SC_P_ENET0_RGMII_TXD3_VPU_TSI_S1_SYNC SC_P_ENET0_RGMII_TXD3 2
-#define SC_P_ENET0_RGMII_TXD3_LSIO_GPIO6_IO03 SC_P_ENET0_RGMII_TXD3 3
-#define SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC SC_P_ENET0_RGMII_RXC 0
-#define SC_P_ENET0_RGMII_RXC_DMA_UART3_CTS_B SC_P_ENET0_RGMII_RXC 1
-#define SC_P_ENET0_RGMII_RXC_VPU_TSI_S1_DATA SC_P_ENET0_RGMII_RXC 2
-#define SC_P_ENET0_RGMII_RXC_LSIO_GPIO6_IO04 SC_P_ENET0_RGMII_RXC 3
-#define SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL SC_P_ENET0_RGMII_RX_CTL 0
-#define SC_P_ENET0_RGMII_RX_CTL_VPU_TSI_S0_VID SC_P_ENET0_RGMII_RX_CTL 2
-#define SC_P_ENET0_RGMII_RX_CTL_LSIO_GPIO6_IO05 SC_P_ENET0_RGMII_RX_CTL 3
-#define SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 SC_P_ENET0_RGMII_RXD0 0
-#define SC_P_ENET0_RGMII_RXD0_VPU_TSI_S0_SYNC SC_P_ENET0_RGMII_RXD0 2
-#define SC_P_ENET0_RGMII_RXD0_LSIO_GPIO6_IO06 SC_P_ENET0_RGMII_RXD0 3
-#define SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 SC_P_ENET0_RGMII_RXD1 0
-#define SC_P_ENET0_RGMII_RXD1_VPU_TSI_S0_DATA SC_P_ENET0_RGMII_RXD1 2
-#define SC_P_ENET0_RGMII_RXD1_LSIO_GPIO6_IO07 SC_P_ENET0_RGMII_RXD1 3
-#define SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 SC_P_ENET0_RGMII_RXD2 0
-#define SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RMII_RX_ER SC_P_ENET0_RGMII_RXD2 1
-#define SC_P_ENET0_RGMII_RXD2_VPU_TSI_S0_CLK SC_P_ENET0_RGMII_RXD2 2
-#define SC_P_ENET0_RGMII_RXD2_LSIO_GPIO6_IO08 SC_P_ENET0_RGMII_RXD2 3
-#define SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 SC_P_ENET0_RGMII_RXD3 0
-#define SC_P_ENET0_RGMII_RXD3_DMA_UART3_RX SC_P_ENET0_RGMII_RXD3 1
-#define SC_P_ENET0_RGMII_RXD3_VPU_TSI_S1_CLK SC_P_ENET0_RGMII_RXD3 2
-#define SC_P_ENET0_RGMII_RXD3_LSIO_GPIO6_IO09 SC_P_ENET0_RGMII_RXD3 3
-#define SC_P_ENET1_RGMII_TXC_CONN_ENET1_RGMII_TXC SC_P_ENET1_RGMII_TXC 0
-#define SC_P_ENET1_RGMII_TXC_CONN_ENET1_RCLK50M_OUT SC_P_ENET1_RGMII_TXC 1
-#define SC_P_ENET1_RGMII_TXC_CONN_ENET1_RCLK50M_IN SC_P_ENET1_RGMII_TXC 2
-#define SC_P_ENET1_RGMII_TXC_LSIO_GPIO6_IO10 SC_P_ENET1_RGMII_TXC 3
-#define SC_P_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL SC_P_ENET1_RGMII_TX_CTL 0
-#define SC_P_ENET1_RGMII_TX_CTL_LSIO_GPIO6_IO11 SC_P_ENET1_RGMII_TX_CTL 3
-#define SC_P_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0 SC_P_ENET1_RGMII_TXD0 0
-#define SC_P_ENET1_RGMII_TXD0_LSIO_GPIO6_IO12 SC_P_ENET1_RGMII_TXD0 3
-#define SC_P_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1 SC_P_ENET1_RGMII_TXD1 0
-#define SC_P_ENET1_RGMII_TXD1_LSIO_GPIO6_IO13 SC_P_ENET1_RGMII_TXD1 3
-#define SC_P_ENET1_RGMII_TXD2_CONN_ENET1_RGMII_TXD2 SC_P_ENET1_RGMII_TXD2 0
-#define SC_P_ENET1_RGMII_TXD2_DMA_UART3_TX SC_P_ENET1_RGMII_TXD2 1
-#define SC_P_ENET1_RGMII_TXD2_VPU_TSI_S1_VID SC_P_ENET1_RGMII_TXD2 2
-#define SC_P_ENET1_RGMII_TXD2_LSIO_GPIO6_IO14 SC_P_ENET1_RGMII_TXD2 3
-#define SC_P_ENET1_RGMII_TXD3_CONN_ENET1_RGMII_TXD3 SC_P_ENET1_RGMII_TXD3 0
-#define SC_P_ENET1_RGMII_TXD3_DMA_UART3_RTS_B SC_P_ENET1_RGMII_TXD3 1
-#define SC_P_ENET1_RGMII_TXD3_VPU_TSI_S1_SYNC SC_P_ENET1_RGMII_TXD3 2
-#define SC_P_ENET1_RGMII_TXD3_LSIO_GPIO6_IO15 SC_P_ENET1_RGMII_TXD3 3
-#define SC_P_ENET1_RGMII_RXC_CONN_ENET1_RGMII_RXC SC_P_ENET1_RGMII_RXC 0
-#define SC_P_ENET1_RGMII_RXC_DMA_UART3_CTS_B SC_P_ENET1_RGMII_RXC 1
-#define SC_P_ENET1_RGMII_RXC_VPU_TSI_S1_DATA SC_P_ENET1_RGMII_RXC 2
-#define SC_P_ENET1_RGMII_RXC_LSIO_GPIO6_IO16 SC_P_ENET1_RGMII_RXC 3
-#define SC_P_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL SC_P_ENET1_RGMII_RX_CTL 0
-#define SC_P_ENET1_RGMII_RX_CTL_VPU_TSI_S0_VID SC_P_ENET1_RGMII_RX_CTL 2
-#define SC_P_ENET1_RGMII_RX_CTL_LSIO_GPIO6_IO17 SC_P_ENET1_RGMII_RX_CTL 3
-#define SC_P_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0 SC_P_ENET1_RGMII_RXD0 0
-#define SC_P_ENET1_RGMII_RXD0_VPU_TSI_S0_SYNC SC_P_ENET1_RGMII_RXD0 2
-#define SC_P_ENET1_RGMII_RXD0_LSIO_GPIO6_IO18 SC_P_ENET1_RGMII_RXD0 3
-#define SC_P_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1 SC_P_ENET1_RGMII_RXD1 0
-#define SC_P_ENET1_RGMII_RXD1_VPU_TSI_S0_DATA SC_P_ENET1_RGMII_RXD1 2
-#define SC_P_ENET1_RGMII_RXD1_LSIO_GPIO6_IO19 SC_P_ENET1_RGMII_RXD1 3
-#define SC_P_ENET1_RGMII_RXD2_CONN_ENET1_RGMII_RXD2 SC_P_ENET1_RGMII_RXD2 0
-#define SC_P_ENET1_RGMII_RXD2_CONN_ENET1_RMII_RX_ER SC_P_ENET1_RGMII_RXD2 1
-#define SC_P_ENET1_RGMII_RXD2_VPU_TSI_S0_CLK SC_P_ENET1_RGMII_RXD2 2
-#define SC_P_ENET1_RGMII_RXD2_LSIO_GPIO6_IO20 SC_P_ENET1_RGMII_RXD2 3
-#define SC_P_ENET1_RGMII_RXD3_CONN_ENET1_RGMII_RXD3 SC_P_ENET1_RGMII_RXD3 0
-#define SC_P_ENET1_RGMII_RXD3_DMA_UART3_RX SC_P_ENET1_RGMII_RXD3 1
-#define SC_P_ENET1_RGMII_RXD3_VPU_TSI_S1_CLK SC_P_ENET1_RGMII_RXD3 2
-#define SC_P_ENET1_RGMII_RXD3_LSIO_GPIO6_IO21 SC_P_ENET1_RGMII_RXD3 3
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB 0
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA 0
-
-#endif /* SC_PADS_H */
diff --git a/include/dt-bindings/pinctrl/pads-imx8qxp.h b/include/dt-bindings/pinctrl/pads-imx8qxp.h
deleted file mode 100644
index 41f4fe5..0000000
--- a/include/dt-bindings/pinctrl/pads-imx8qxp.h
+++ /dev/null
@@ -1,757 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2018 NXP
- */
-
-#ifndef _SC_PADS_H
-#define _SC_PADS_H
-
-#define SC_P_PCIE_CTRL0_PERST_B 0 /* HSIO.PCIE0.PERST_B, LSIO.GPIO4.IO00 */
-#define SC_P_PCIE_CTRL0_CLKREQ_B 1 /* HSIO.PCIE0.CLKREQ_B, LSIO.GPIO4.IO01 */
-#define SC_P_PCIE_CTRL0_WAKE_B 2 /* HSIO.PCIE0.WAKE_B, LSIO.GPIO4.IO02 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_PCIESEP 3 /* */
-#define SC_P_USB_SS3_TC0 4 /* ADMA.I2C1.SCL, CONN.USB_OTG1.PWR, CONN.USB_OTG2.PWR, LSIO.GPIO4.IO03 */
-#define SC_P_USB_SS3_TC1 5 /* ADMA.I2C1.SCL, CONN.USB_OTG2.PWR, LSIO.GPIO4.IO04 */
-#define SC_P_USB_SS3_TC2 6 /* ADMA.I2C1.SDA, CONN.USB_OTG1.OC, CONN.USB_OTG2.OC, LSIO.GPIO4.IO05 */
-#define SC_P_USB_SS3_TC3 7 /* ADMA.I2C1.SDA, CONN.USB_OTG2.OC, LSIO.GPIO4.IO06 */
-#define SC_P_COMP_CTL_GPIO_3V3_USB3IO 8 /* */
-#define SC_P_EMMC0_CLK 9 /* CONN.EMMC0.CLK, CONN.NAND.READY_B, LSIO.GPIO4.IO07 */
-#define SC_P_EMMC0_CMD 10 /* CONN.EMMC0.CMD, CONN.NAND.DQS, LSIO.GPIO4.IO08 */
-#define SC_P_EMMC0_DATA0 11 /* CONN.EMMC0.DATA0, CONN.NAND.DATA00, LSIO.GPIO4.IO09 */
-#define SC_P_EMMC0_DATA1 12 /* CONN.EMMC0.DATA1, CONN.NAND.DATA01, LSIO.GPIO4.IO10 */
-#define SC_P_EMMC0_DATA2 13 /* CONN.EMMC0.DATA2, CONN.NAND.DATA02, LSIO.GPIO4.IO11 */
-#define SC_P_EMMC0_DATA3 14 /* CONN.EMMC0.DATA3, CONN.NAND.DATA03, LSIO.GPIO4.IO12 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX0 15 /* */
-#define SC_P_EMMC0_DATA4 16 /* CONN.EMMC0.DATA4, CONN.NAND.DATA04, CONN.EMMC0.WP, LSIO.GPIO4.IO13 */
-#define SC_P_EMMC0_DATA5 17 /* CONN.EMMC0.DATA5, CONN.NAND.DATA05, CONN.EMMC0.VSELECT, LSIO.GPIO4.IO14 */
-#define SC_P_EMMC0_DATA6 18 /* CONN.EMMC0.DATA6, CONN.NAND.DATA06, CONN.MLB.CLK, LSIO.GPIO4.IO15 */
-#define SC_P_EMMC0_DATA7 19 /* CONN.EMMC0.DATA7, CONN.NAND.DATA07, CONN.MLB.SIG, LSIO.GPIO4.IO16 */
-#define SC_P_EMMC0_STROBE 20 /* CONN.EMMC0.STROBE, CONN.NAND.CLE, CONN.MLB.DATA, LSIO.GPIO4.IO17 */
-#define SC_P_EMMC0_RESET_B 21 /* CONN.EMMC0.RESET_B, CONN.NAND.WP_B, LSIO.GPIO4.IO18 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX1 22 /* */
-#define SC_P_USDHC1_RESET_B 23 /* CONN.USDHC1.RESET_B, CONN.NAND.RE_N, ADMA.SPI2.SCK, LSIO.GPIO4.IO19 */
-#define SC_P_USDHC1_VSELECT 24 /* CONN.USDHC1.VSELECT, CONN.NAND.RE_P, ADMA.SPI2.SDO, CONN.NAND.RE_B, LSIO.GPIO4.IO20 */
-#define SC_P_CTL_NAND_RE_P_N 25 /* */
-#define SC_P_USDHC1_WP 26 /* CONN.USDHC1.WP, CONN.NAND.DQS_N, ADMA.SPI2.SDI, LSIO.GPIO4.IO21 */
-#define SC_P_USDHC1_CD_B 27 /* CONN.USDHC1.CD_B, CONN.NAND.DQS_P, ADMA.SPI2.CS0, CONN.NAND.DQS, LSIO.GPIO4.IO22 */
-#define SC_P_CTL_NAND_DQS_P_N 28 /* */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSELSEP 29 /* */
-#define SC_P_USDHC1_CLK 30 /* CONN.USDHC1.CLK, ADMA.UART3.RX, LSIO.GPIO4.IO23 */
-#define SC_P_USDHC1_CMD 31 /* CONN.USDHC1.CMD, CONN.NAND.CE0_B, ADMA.MQS.R, LSIO.GPIO4.IO24 */
-#define SC_P_USDHC1_DATA0 32 /* CONN.USDHC1.DATA0, CONN.NAND.CE1_B, ADMA.MQS.L, LSIO.GPIO4.IO25 */
-#define SC_P_USDHC1_DATA1 33 /* CONN.USDHC1.DATA1, CONN.NAND.RE_B, ADMA.UART3.TX, LSIO.GPIO4.IO26 */
-#define SC_P_USDHC1_DATA2 34 /* CONN.USDHC1.DATA2, CONN.NAND.WE_B, ADMA.UART3.CTS_B, LSIO.GPIO4.IO27 */
-#define SC_P_USDHC1_DATA3 35 /* CONN.USDHC1.DATA3, CONN.NAND.ALE, ADMA.UART3.RTS_B, LSIO.GPIO4.IO28 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSEL3 36 /* */
-#define SC_P_ENET0_RGMII_TXC 37 /* CONN.ENET0.RGMII_TXC, CONN.ENET0.RCLK50M_OUT, CONN.ENET0.RCLK50M_IN, CONN.NAND.CE1_B, LSIO.GPIO4.IO29 */
-#define SC_P_ENET0_RGMII_TX_CTL 38 /* CONN.ENET0.RGMII_TX_CTL, CONN.USDHC1.RESET_B, LSIO.GPIO4.IO30 */
-#define SC_P_ENET0_RGMII_TXD0 39 /* CONN.ENET0.RGMII_TXD0, CONN.USDHC1.VSELECT, LSIO.GPIO4.IO31 */
-#define SC_P_ENET0_RGMII_TXD1 40 /* CONN.ENET0.RGMII_TXD1, CONN.USDHC1.WP, LSIO.GPIO5.IO00 */
-#define SC_P_ENET0_RGMII_TXD2 41 /* CONN.ENET0.RGMII_TXD2, CONN.MLB.CLK, CONN.NAND.CE0_B, CONN.USDHC1.CD_B, LSIO.GPIO5.IO01 */
-#define SC_P_ENET0_RGMII_TXD3 42 /* CONN.ENET0.RGMII_TXD3, CONN.MLB.SIG, CONN.NAND.RE_B, LSIO.GPIO5.IO02 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0 43 /* */
-#define SC_P_ENET0_RGMII_RXC 44 /* CONN.ENET0.RGMII_RXC, CONN.MLB.DATA, CONN.NAND.WE_B, CONN.USDHC1.CLK, LSIO.GPIO5.IO03 */
-#define SC_P_ENET0_RGMII_RX_CTL 45 /* CONN.ENET0.RGMII_RX_CTL, CONN.USDHC1.CMD, LSIO.GPIO5.IO04 */
-#define SC_P_ENET0_RGMII_RXD0 46 /* CONN.ENET0.RGMII_RXD0, CONN.USDHC1.DATA0, LSIO.GPIO5.IO05 */
-#define SC_P_ENET0_RGMII_RXD1 47 /* CONN.ENET0.RGMII_RXD1, CONN.USDHC1.DATA1, LSIO.GPIO5.IO06 */
-#define SC_P_ENET0_RGMII_RXD2 48 /* CONN.ENET0.RGMII_RXD2, CONN.ENET0.RMII_RX_ER, CONN.USDHC1.DATA2, LSIO.GPIO5.IO07 */
-#define SC_P_ENET0_RGMII_RXD3 49 /* CONN.ENET0.RGMII_RXD3, CONN.NAND.ALE, CONN.USDHC1.DATA3, LSIO.GPIO5.IO08 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1 50 /* */
-#define SC_P_ENET0_REFCLK_125M_25M 51 /* CONN.ENET0.REFCLK_125M_25M, CONN.ENET0.PPS, CONN.ENET1.PPS, LSIO.GPIO5.IO09 */
-#define SC_P_ENET0_MDIO 52 /* CONN.ENET0.MDIO, ADMA.I2C3.SDA, CONN.ENET1.MDIO, LSIO.GPIO5.IO10 */
-#define SC_P_ENET0_MDC 53 /* CONN.ENET0.MDC, ADMA.I2C3.SCL, CONN.ENET1.MDC, LSIO.GPIO5.IO11 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOCT 54 /* */
-#define SC_P_ESAI0_FSR 55 /* ADMA.ESAI0.FSR, CONN.ENET1.RCLK50M_OUT, ADMA.LCDIF.D00, CONN.ENET1.RGMII_TXC, CONN.ENET1.RCLK50M_IN */
-#define SC_P_ESAI0_FST 56 /* ADMA.ESAI0.FST, CONN.MLB.CLK, ADMA.LCDIF.D01, CONN.ENET1.RGMII_TXD2, LSIO.GPIO0.IO01 */
-#define SC_P_ESAI0_SCKR 57 /* ADMA.ESAI0.SCKR, ADMA.LCDIF.D02, CONN.ENET1.RGMII_TX_CTL, LSIO.GPIO0.IO02 */
-#define SC_P_ESAI0_SCKT 58 /* ADMA.ESAI0.SCKT, CONN.MLB.SIG, ADMA.LCDIF.D03, CONN.ENET1.RGMII_TXD3, LSIO.GPIO0.IO03 */
-#define SC_P_ESAI0_TX0 59 /* ADMA.ESAI0.TX0, CONN.MLB.DATA, ADMA.LCDIF.D04, CONN.ENET1.RGMII_RXC, LSIO.GPIO0.IO04 */
-#define SC_P_ESAI0_TX1 60 /* ADMA.ESAI0.TX1, ADMA.LCDIF.D05, CONN.ENET1.RGMII_RXD3, LSIO.GPIO0.IO05 */
-#define SC_P_ESAI0_TX2_RX3 61 /* ADMA.ESAI0.TX2_RX3, CONN.ENET1.RMII_RX_ER, ADMA.LCDIF.D06, CONN.ENET1.RGMII_RXD2, LSIO.GPIO0.IO06 */
-#define SC_P_ESAI0_TX3_RX2 62 /* ADMA.ESAI0.TX3_RX2, ADMA.LCDIF.D07, CONN.ENET1.RGMII_RXD1, LSIO.GPIO0.IO07 */
-#define SC_P_ESAI0_TX4_RX1 63 /* ADMA.ESAI0.TX4_RX1, ADMA.LCDIF.D08, CONN.ENET1.RGMII_TXD0, LSIO.GPIO0.IO08 */
-#define SC_P_ESAI0_TX5_RX0 64 /* ADMA.ESAI0.TX5_RX0, ADMA.LCDIF.D09, CONN.ENET1.RGMII_TXD1, LSIO.GPIO0.IO09 */
-#define SC_P_SPDIF0_RX 65 /* ADMA.SPDIF0.RX, ADMA.MQS.R, ADMA.LCDIF.D10, CONN.ENET1.RGMII_RXD0, LSIO.GPIO0.IO10 */
-#define SC_P_SPDIF0_TX 66 /* ADMA.SPDIF0.TX, ADMA.MQS.L, ADMA.LCDIF.D11, CONN.ENET1.RGMII_RX_CTL, LSIO.GPIO0.IO11 */
-#define SC_P_SPDIF0_EXT_CLK 67 /* ADMA.SPDIF0.EXT_CLK, ADMA.LCDIF.D12, CONN.ENET1.REFCLK_125M_25M, LSIO.GPIO0.IO12 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB 68 /* */
-#define SC_P_SPI3_SCK 69 /* ADMA.SPI3.SCK, ADMA.LCDIF.D13, LSIO.GPIO0.IO13 */
-#define SC_P_SPI3_SDO 70 /* ADMA.SPI3.SDO, ADMA.LCDIF.D14, LSIO.GPIO0.IO14 */
-#define SC_P_SPI3_SDI 71 /* ADMA.SPI3.SDI, ADMA.LCDIF.D15, LSIO.GPIO0.IO15 */
-#define SC_P_SPI3_CS0 72 /* ADMA.SPI3.CS0, ADMA.ACM.MCLK_OUT1, ADMA.LCDIF.HSYNC, LSIO.GPIO0.IO16 */
-#define SC_P_SPI3_CS1 73 /* ADMA.SPI3.CS1, ADMA.I2C3.SCL, ADMA.LCDIF.RESET, ADMA.SPI2.CS0, ADMA.LCDIF.D16 */
-#define SC_P_MCLK_IN1 74 /* ADMA.ACM.MCLK_IN1, ADMA.I2C3.SDA, ADMA.LCDIF.EN, ADMA.SPI2.SCK, ADMA.LCDIF.D17 */
-#define SC_P_MCLK_IN0 75 /* ADMA.ACM.MCLK_IN0, ADMA.ESAI0.RX_HF_CLK, ADMA.LCDIF.VSYNC, ADMA.SPI2.SDI, LSIO.GPIO0.IO19 */
-#define SC_P_MCLK_OUT0 76 /* ADMA.ACM.MCLK_OUT0, ADMA.ESAI0.TX_HF_CLK, ADMA.LCDIF.CLK, ADMA.SPI2.SDO, LSIO.GPIO0.IO20 */
-#define SC_P_UART1_TX 77 /* ADMA.UART1.TX, LSIO.PWM0.OUT, LSIO.GPT0.CAPTURE, LSIO.GPIO0.IO21 */
-#define SC_P_UART1_RX 78 /* ADMA.UART1.RX, LSIO.PWM1.OUT, LSIO.GPT0.COMPARE, LSIO.GPT1.CLK, LSIO.GPIO0.IO22 */
-#define SC_P_UART1_RTS_B 79 /* ADMA.UART1.RTS_B, LSIO.PWM2.OUT, ADMA.LCDIF.D16, LSIO.GPT1.CAPTURE, LSIO.GPT0.CLK */
-#define SC_P_UART1_CTS_B 80 /* ADMA.UART1.CTS_B, LSIO.PWM3.OUT, ADMA.LCDIF.D17, LSIO.GPT1.COMPARE, LSIO.GPIO0.IO24 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHK 81 /* */
-#define SC_P_SAI0_TXD 82 /* ADMA.SAI0.TXD, ADMA.SAI1.RXC, ADMA.SPI1.SDO, ADMA.LCDIF.D18, LSIO.GPIO0.IO25 */
-#define SC_P_SAI0_TXC 83 /* ADMA.SAI0.TXC, ADMA.SAI1.TXD, ADMA.SPI1.SDI, ADMA.LCDIF.D19, LSIO.GPIO0.IO26 */
-#define SC_P_SAI0_RXD 84 /* ADMA.SAI0.RXD, ADMA.SAI1.RXFS, ADMA.SPI1.CS0, ADMA.LCDIF.D20, LSIO.GPIO0.IO27 */
-#define SC_P_SAI0_TXFS 85 /* ADMA.SAI0.TXFS, ADMA.SPI2.CS1, ADMA.SPI1.SCK, LSIO.GPIO0.IO28 */
-#define SC_P_SAI1_RXD 86 /* ADMA.SAI1.RXD, ADMA.SAI0.RXFS, ADMA.SPI1.CS1, ADMA.LCDIF.D21, LSIO.GPIO0.IO29 */
-#define SC_P_SAI1_RXC 87 /* ADMA.SAI1.RXC, ADMA.SAI1.TXC, ADMA.LCDIF.D22, LSIO.GPIO0.IO30 */
-#define SC_P_SAI1_RXFS 88 /* ADMA.SAI1.RXFS, ADMA.SAI1.TXFS, ADMA.LCDIF.D23, LSIO.GPIO0.IO31 */
-#define SC_P_SPI2_CS0 89 /* ADMA.SPI2.CS0, LSIO.GPIO1.IO00 */
-#define SC_P_SPI2_SDO 90 /* ADMA.SPI2.SDO, LSIO.GPIO1.IO01 */
-#define SC_P_SPI2_SDI 91 /* ADMA.SPI2.SDI, LSIO.GPIO1.IO02 */
-#define SC_P_SPI2_SCK 92 /* ADMA.SPI2.SCK, LSIO.GPIO1.IO03 */
-#define SC_P_SPI0_SCK 93 /* ADMA.SPI0.SCK, ADMA.SAI0.TXC, M40.I2C0.SCL, M40.GPIO0.IO00, LSIO.GPIO1.IO04 */
-#define SC_P_SPI0_SDI 94 /* ADMA.SPI0.SDI, ADMA.SAI0.TXD, M40.TPM0.CH0, M40.GPIO0.IO02, LSIO.GPIO1.IO05 */
-#define SC_P_SPI0_SDO 95 /* ADMA.SPI0.SDO, ADMA.SAI0.TXFS, M40.I2C0.SDA, M40.GPIO0.IO01, LSIO.GPIO1.IO06 */
-#define SC_P_SPI0_CS1 96 /* ADMA.SPI0.CS1, ADMA.SAI0.RXC, ADMA.SAI1.TXD, ADMA.LCD_PWM0.OUT, LSIO.GPIO1.IO07 */
-#define SC_P_SPI0_CS0 97 /* ADMA.SPI0.CS0, ADMA.SAI0.RXD, M40.TPM0.CH1, M40.GPIO0.IO03, LSIO.GPIO1.IO08 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHT 98 /* */
-#define SC_P_ADC_IN1 99 /* ADMA.ADC.IN1, M40.I2C0.SDA, M40.GPIO0.IO01, LSIO.GPIO1.IO09 */
-#define SC_P_ADC_IN0 100 /* ADMA.ADC.IN0, M40.I2C0.SCL, M40.GPIO0.IO00, LSIO.GPIO1.IO10 */
-#define SC_P_ADC_IN3 101 /* ADMA.ADC.IN3, M40.UART0.TX, M40.GPIO0.IO03, ADMA.ACM.MCLK_OUT0, LSIO.GPIO1.IO11 */
-#define SC_P_ADC_IN2 102 /* ADMA.ADC.IN2, M40.UART0.RX, M40.GPIO0.IO02, ADMA.ACM.MCLK_IN0, LSIO.GPIO1.IO12 */
-#define SC_P_ADC_IN5 103 /* ADMA.ADC.IN5, M40.TPM0.CH1, M40.GPIO0.IO05, LSIO.GPIO1.IO13 */
-#define SC_P_ADC_IN4 104 /* ADMA.ADC.IN4, M40.TPM0.CH0, M40.GPIO0.IO04, LSIO.GPIO1.IO14 */
-#define SC_P_FLEXCAN0_RX 105 /* ADMA.FLEXCAN0.RX, ADMA.SAI2.RXC, ADMA.UART0.RTS_B, ADMA.SAI1.TXC, LSIO.GPIO1.IO15 */
-#define SC_P_FLEXCAN0_TX 106 /* ADMA.FLEXCAN0.TX, ADMA.SAI2.RXD, ADMA.UART0.CTS_B, ADMA.SAI1.TXFS, LSIO.GPIO1.IO16 */
-#define SC_P_FLEXCAN1_RX 107 /* ADMA.FLEXCAN1.RX, ADMA.SAI2.RXFS, ADMA.FTM.CH2, ADMA.SAI1.TXD, LSIO.GPIO1.IO17 */
-#define SC_P_FLEXCAN1_TX 108 /* ADMA.FLEXCAN1.TX, ADMA.SAI3.RXC, ADMA.DMA0.REQ_IN0, ADMA.SAI1.RXD, LSIO.GPIO1.IO18 */
-#define SC_P_FLEXCAN2_RX 109 /* ADMA.FLEXCAN2.RX, ADMA.SAI3.RXD, ADMA.UART3.RX, ADMA.SAI1.RXFS, LSIO.GPIO1.IO19 */
-#define SC_P_FLEXCAN2_TX 110 /* ADMA.FLEXCAN2.TX, ADMA.SAI3.RXFS, ADMA.UART3.TX, ADMA.SAI1.RXC, LSIO.GPIO1.IO20 */
-#define SC_P_UART0_RX 111 /* ADMA.UART0.RX, ADMA.MQS.R, ADMA.FLEXCAN0.RX, SCU.UART0.RX, LSIO.GPIO1.IO21 */
-#define SC_P_UART0_TX 112 /* ADMA.UART0.TX, ADMA.MQS.L, ADMA.FLEXCAN0.TX, SCU.UART0.TX, LSIO.GPIO1.IO22 */
-#define SC_P_UART2_TX 113 /* ADMA.UART2.TX, ADMA.FTM.CH1, ADMA.FLEXCAN1.TX, LSIO.GPIO1.IO23 */
-#define SC_P_UART2_RX 114 /* ADMA.UART2.RX, ADMA.FTM.CH0, ADMA.FLEXCAN1.RX, LSIO.GPIO1.IO24 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOLH 115 /* */
-#define SC_P_MIPI_DSI0_I2C0_SCL 116 /* MIPI_DSI0.I2C0.SCL, MIPI_DSI1.GPIO0.IO02, LSIO.GPIO1.IO25 */
-#define SC_P_MIPI_DSI0_I2C0_SDA 117 /* MIPI_DSI0.I2C0.SDA, MIPI_DSI1.GPIO0.IO03, LSIO.GPIO1.IO26 */
-#define SC_P_MIPI_DSI0_GPIO0_00 118 /* MIPI_DSI0.GPIO0.IO00, ADMA.I2C1.SCL, MIPI_DSI0.PWM0.OUT, LSIO.GPIO1.IO27 */
-#define SC_P_MIPI_DSI0_GPIO0_01 119 /* MIPI_DSI0.GPIO0.IO01, ADMA.I2C1.SDA, LSIO.GPIO1.IO28 */
-#define SC_P_MIPI_DSI1_I2C0_SCL 120 /* MIPI_DSI1.I2C0.SCL, MIPI_DSI0.GPIO0.IO02, LSIO.GPIO1.IO29 */
-#define SC_P_MIPI_DSI1_I2C0_SDA 121 /* MIPI_DSI1.I2C0.SDA, MIPI_DSI0.GPIO0.IO03, LSIO.GPIO1.IO30 */
-#define SC_P_MIPI_DSI1_GPIO0_00 122 /* MIPI_DSI1.GPIO0.IO00, ADMA.I2C2.SCL, MIPI_DSI1.PWM0.OUT, LSIO.GPIO1.IO31 */
-#define SC_P_MIPI_DSI1_GPIO0_01 123 /* MIPI_DSI1.GPIO0.IO01, ADMA.I2C2.SDA, LSIO.GPIO2.IO00 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO 124 /* */
-#define SC_P_JTAG_TRST_B 125 /* SCU.JTAG.TRST_B, SCU.WDOG0.WDOG_OUT */
-#define SC_P_PMIC_I2C_SCL 126 /* SCU.PMIC_I2C.SCL, SCU.GPIO0.IOXX_PMIC_A35_ON, LSIO.GPIO2.IO01 */
-#define SC_P_PMIC_I2C_SDA 127 /* SCU.PMIC_I2C.SDA, SCU.GPIO0.IOXX_PMIC_GPU_ON, LSIO.GPIO2.IO02 */
-#define SC_P_PMIC_INT_B 128 /* SCU.DSC.PMIC_INT_B */
-#define SC_P_SCU_GPIO0_00 129 /* SCU.GPIO0.IO00, SCU.UART0.RX, M40.UART0.RX, ADMA.UART3.RX, LSIO.GPIO2.IO03 */
-#define SC_P_SCU_GPIO0_01 130 /* SCU.GPIO0.IO01, SCU.UART0.TX, M40.UART0.TX, ADMA.UART3.TX, SCU.WDOG0.WDOG_OUT */
-#define SC_P_SCU_PMIC_STANDBY 131 /* SCU.DSC.PMIC_STANDBY */
-#define SC_P_SCU_BOOT_MODE0 132 /* SCU.DSC.BOOT_MODE0 */
-#define SC_P_SCU_BOOT_MODE1 133 /* SCU.DSC.BOOT_MODE1 */
-#define SC_P_SCU_BOOT_MODE2 134 /* SCU.DSC.BOOT_MODE2, SCU.PMIC_I2C.SDA */
-#define SC_P_SCU_BOOT_MODE3 135 /* SCU.DSC.BOOT_MODE3, SCU.PMIC_I2C.SCL, SCU.DSC.RTC_CLOCK_OUTPUT_32K */
-#define SC_P_CSI_D00 136 /* CI_PI.D02, ADMA.SAI0.RXC */
-#define SC_P_CSI_D01 137 /* CI_PI.D03, ADMA.SAI0.RXD */
-#define SC_P_CSI_D02 138 /* CI_PI.D04, ADMA.SAI0.RXFS */
-#define SC_P_CSI_D03 139 /* CI_PI.D05, ADMA.SAI2.RXC */
-#define SC_P_CSI_D04 140 /* CI_PI.D06, ADMA.SAI2.RXD */
-#define SC_P_CSI_D05 141 /* CI_PI.D07, ADMA.SAI2.RXFS */
-#define SC_P_CSI_D06 142 /* CI_PI.D08, ADMA.SAI3.RXC */
-#define SC_P_CSI_D07 143 /* CI_PI.D09, ADMA.SAI3.RXD */
-#define SC_P_CSI_HSYNC 144 /* CI_PI.HSYNC, CI_PI.D00, ADMA.SAI3.RXFS */
-#define SC_P_CSI_VSYNC 145 /* CI_PI.VSYNC, CI_PI.D01 */
-#define SC_P_CSI_PCLK 146 /* CI_PI.PCLK, MIPI_CSI0.I2C0.SCL, ADMA.SPI1.SCK, LSIO.GPIO3.IO00 */
-#define SC_P_CSI_MCLK 147 /* CI_PI.MCLK, MIPI_CSI0.I2C0.SDA, ADMA.SPI1.SDO, LSIO.GPIO3.IO01 */
-#define SC_P_CSI_EN 148 /* CI_PI.EN, CI_PI.I2C.SCL, ADMA.I2C3.SCL, ADMA.SPI1.SDI, LSIO.GPIO3.IO02 */
-#define SC_P_CSI_RESET 149 /* CI_PI.RESET, CI_PI.I2C.SDA, ADMA.I2C3.SDA, ADMA.SPI1.CS0, LSIO.GPIO3.IO03 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHD 150 /* */
-#define SC_P_MIPI_CSI0_MCLK_OUT 151 /* MIPI_CSI0.ACM.MCLK_OUT, LSIO.GPIO3.IO04 */
-#define SC_P_MIPI_CSI0_I2C0_SCL 152 /* MIPI_CSI0.I2C0.SCL, MIPI_CSI0.GPIO0.IO02, LSIO.GPIO3.IO05 */
-#define SC_P_MIPI_CSI0_I2C0_SDA 153 /* MIPI_CSI0.I2C0.SDA, MIPI_CSI0.GPIO0.IO03, LSIO.GPIO3.IO06 */
-#define SC_P_MIPI_CSI0_GPIO0_01 154 /* MIPI_CSI0.GPIO0.IO01, ADMA.I2C0.SDA, LSIO.GPIO3.IO07 */
-#define SC_P_MIPI_CSI0_GPIO0_00 155 /* MIPI_CSI0.GPIO0.IO00, ADMA.I2C0.SCL, LSIO.GPIO3.IO08 */
-#define SC_P_QSPI0A_DATA0 156 /* LSIO.QSPI0A.DATA0, LSIO.GPIO3.IO09 */
-#define SC_P_QSPI0A_DATA1 157 /* LSIO.QSPI0A.DATA1, LSIO.GPIO3.IO10 */
-#define SC_P_QSPI0A_DATA2 158 /* LSIO.QSPI0A.DATA2, LSIO.GPIO3.IO11 */
-#define SC_P_QSPI0A_DATA3 159 /* LSIO.QSPI0A.DATA3, LSIO.GPIO3.IO12 */
-#define SC_P_QSPI0A_DQS 160 /* LSIO.QSPI0A.DQS, LSIO.GPIO3.IO13 */
-#define SC_P_QSPI0A_SS0_B 161 /* LSIO.QSPI0A.SS0_B, LSIO.GPIO3.IO14 */
-#define SC_P_QSPI0A_SS1_B 162 /* LSIO.QSPI0A.SS1_B, LSIO.GPIO3.IO15 */
-#define SC_P_QSPI0A_SCLK 163 /* LSIO.QSPI0A.SCLK, LSIO.GPIO3.IO16 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0A 164 /* */
-#define SC_P_QSPI0B_SCLK 165 /* LSIO.QSPI0B.SCLK, LSIO.QSPI1A.SCLK, LSIO.KPP0.COL0, LSIO.GPIO3.IO17 */
-#define SC_P_QSPI0B_DATA0 166 /* LSIO.QSPI0B.DATA0, LSIO.QSPI1A.DATA0, LSIO.KPP0.COL1, LSIO.GPIO3.IO18 */
-#define SC_P_QSPI0B_DATA1 167 /* LSIO.QSPI0B.DATA1, LSIO.QSPI1A.DATA1, LSIO.KPP0.COL2, LSIO.GPIO3.IO19 */
-#define SC_P_QSPI0B_DATA2 168 /* LSIO.QSPI0B.DATA2, LSIO.QSPI1A.DATA2, LSIO.KPP0.COL3, LSIO.GPIO3.IO20 */
-#define SC_P_QSPI0B_DATA3 169 /* LSIO.QSPI0B.DATA3, LSIO.QSPI1A.DATA3, LSIO.KPP0.ROW0, LSIO.GPIO3.IO21 */
-#define SC_P_QSPI0B_DQS 170 /* LSIO.QSPI0B.DQS, LSIO.QSPI1A.DQS, LSIO.KPP0.ROW1, LSIO.GPIO3.IO22 */
-#define SC_P_QSPI0B_SS0_B 171 /* LSIO.QSPI0B.SS0_B, LSIO.QSPI1A.SS0_B, LSIO.KPP0.ROW2, LSIO.GPIO3.IO23 */
-#define SC_P_QSPI0B_SS1_B 172 /* LSIO.QSPI0B.SS1_B, LSIO.QSPI1A.SS1_B, LSIO.KPP0.ROW3, LSIO.GPIO3.IO24 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0B 173 /* */
-/*@}*/
-
-/*!
- * @name Pad Mux Definitions
- * format: name padid padmux
- */
-/*@{*/
-#define SC_P_PCIE_CTRL0_PERST_B_HSIO_PCIE0_PERST_B SC_P_PCIE_CTRL0_PERST_B 0
-#define SC_P_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 SC_P_PCIE_CTRL0_PERST_B 4
-#define SC_P_PCIE_CTRL0_CLKREQ_B_HSIO_PCIE0_CLKREQ_B SC_P_PCIE_CTRL0_CLKREQ_B 0
-#define SC_P_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 SC_P_PCIE_CTRL0_CLKREQ_B 4
-#define SC_P_PCIE_CTRL0_WAKE_B_HSIO_PCIE0_WAKE_B SC_P_PCIE_CTRL0_WAKE_B 0
-#define SC_P_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 SC_P_PCIE_CTRL0_WAKE_B 4
-#define SC_P_USB_SS3_TC0_ADMA_I2C1_SCL SC_P_USB_SS3_TC0 0
-#define SC_P_USB_SS3_TC0_CONN_USB_OTG1_PWR SC_P_USB_SS3_TC0 1
-#define SC_P_USB_SS3_TC0_CONN_USB_OTG2_PWR SC_P_USB_SS3_TC0 2
-#define SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03 SC_P_USB_SS3_TC0 4
-#define SC_P_USB_SS3_TC1_ADMA_I2C1_SCL SC_P_USB_SS3_TC1 0
-#define SC_P_USB_SS3_TC1_CONN_USB_OTG2_PWR SC_P_USB_SS3_TC1 1
-#define SC_P_USB_SS3_TC1_LSIO_GPIO4_IO04 SC_P_USB_SS3_TC1 4
-#define SC_P_USB_SS3_TC2_ADMA_I2C1_SDA SC_P_USB_SS3_TC2 0
-#define SC_P_USB_SS3_TC2_CONN_USB_OTG1_OC SC_P_USB_SS3_TC2 1
-#define SC_P_USB_SS3_TC2_CONN_USB_OTG2_OC SC_P_USB_SS3_TC2 2
-#define SC_P_USB_SS3_TC2_LSIO_GPIO4_IO05 SC_P_USB_SS3_TC2 4
-#define SC_P_USB_SS3_TC3_ADMA_I2C1_SDA SC_P_USB_SS3_TC3 0
-#define SC_P_USB_SS3_TC3_CONN_USB_OTG2_OC SC_P_USB_SS3_TC3 1
-#define SC_P_USB_SS3_TC3_LSIO_GPIO4_IO06 SC_P_USB_SS3_TC3 4
-#define SC_P_EMMC0_CLK_CONN_EMMC0_CLK SC_P_EMMC0_CLK 0
-#define SC_P_EMMC0_CLK_CONN_NAND_READY_B SC_P_EMMC0_CLK 1
-#define SC_P_EMMC0_CLK_LSIO_GPIO4_IO07 SC_P_EMMC0_CLK 4
-#define SC_P_EMMC0_CMD_CONN_EMMC0_CMD SC_P_EMMC0_CMD 0
-#define SC_P_EMMC0_CMD_CONN_NAND_DQS SC_P_EMMC0_CMD 1
-#define SC_P_EMMC0_CMD_LSIO_GPIO4_IO08 SC_P_EMMC0_CMD 4
-#define SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 SC_P_EMMC0_DATA0 0
-#define SC_P_EMMC0_DATA0_CONN_NAND_DATA00 SC_P_EMMC0_DATA0 1
-#define SC_P_EMMC0_DATA0_LSIO_GPIO4_IO09 SC_P_EMMC0_DATA0 4
-#define SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 SC_P_EMMC0_DATA1 0
-#define SC_P_EMMC0_DATA1_CONN_NAND_DATA01 SC_P_EMMC0_DATA1 1
-#define SC_P_EMMC0_DATA1_LSIO_GPIO4_IO10 SC_P_EMMC0_DATA1 4
-#define SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 SC_P_EMMC0_DATA2 0
-#define SC_P_EMMC0_DATA2_CONN_NAND_DATA02 SC_P_EMMC0_DATA2 1
-#define SC_P_EMMC0_DATA2_LSIO_GPIO4_IO11 SC_P_EMMC0_DATA2 4
-#define SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 SC_P_EMMC0_DATA3 0
-#define SC_P_EMMC0_DATA3_CONN_NAND_DATA03 SC_P_EMMC0_DATA3 1
-#define SC_P_EMMC0_DATA3_LSIO_GPIO4_IO12 SC_P_EMMC0_DATA3 4
-#define SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 SC_P_EMMC0_DATA4 0
-#define SC_P_EMMC0_DATA4_CONN_NAND_DATA04 SC_P_EMMC0_DATA4 1
-#define SC_P_EMMC0_DATA4_CONN_EMMC0_WP SC_P_EMMC0_DATA4 3
-#define SC_P_EMMC0_DATA4_LSIO_GPIO4_IO13 SC_P_EMMC0_DATA4 4
-#define SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 SC_P_EMMC0_DATA5 0
-#define SC_P_EMMC0_DATA5_CONN_NAND_DATA05 SC_P_EMMC0_DATA5 1
-#define SC_P_EMMC0_DATA5_CONN_EMMC0_VSELECT SC_P_EMMC0_DATA5 3
-#define SC_P_EMMC0_DATA5_LSIO_GPIO4_IO14 SC_P_EMMC0_DATA5 4
-#define SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 SC_P_EMMC0_DATA6 0
-#define SC_P_EMMC0_DATA6_CONN_NAND_DATA06 SC_P_EMMC0_DATA6 1
-#define SC_P_EMMC0_DATA6_CONN_MLB_CLK SC_P_EMMC0_DATA6 3
-#define SC_P_EMMC0_DATA6_LSIO_GPIO4_IO15 SC_P_EMMC0_DATA6 4
-#define SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 SC_P_EMMC0_DATA7 0
-#define SC_P_EMMC0_DATA7_CONN_NAND_DATA07 SC_P_EMMC0_DATA7 1
-#define SC_P_EMMC0_DATA7_CONN_MLB_SIG SC_P_EMMC0_DATA7 3
-#define SC_P_EMMC0_DATA7_LSIO_GPIO4_IO16 SC_P_EMMC0_DATA7 4
-#define SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE SC_P_EMMC0_STROBE 0
-#define SC_P_EMMC0_STROBE_CONN_NAND_CLE SC_P_EMMC0_STROBE 1
-#define SC_P_EMMC0_STROBE_CONN_MLB_DATA SC_P_EMMC0_STROBE 3
-#define SC_P_EMMC0_STROBE_LSIO_GPIO4_IO17 SC_P_EMMC0_STROBE 4
-#define SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B SC_P_EMMC0_RESET_B 0
-#define SC_P_EMMC0_RESET_B_CONN_NAND_WP_B SC_P_EMMC0_RESET_B 1
-#define SC_P_EMMC0_RESET_B_LSIO_GPIO4_IO18 SC_P_EMMC0_RESET_B 4
-#define SC_P_USDHC1_RESET_B_CONN_USDHC1_RESET_B SC_P_USDHC1_RESET_B 0
-#define SC_P_USDHC1_RESET_B_CONN_NAND_RE_N SC_P_USDHC1_RESET_B 1
-#define SC_P_USDHC1_RESET_B_ADMA_SPI2_SCK SC_P_USDHC1_RESET_B 2
-#define SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO19 SC_P_USDHC1_RESET_B 4
-#define SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT SC_P_USDHC1_VSELECT 0
-#define SC_P_USDHC1_VSELECT_CONN_NAND_RE_P SC_P_USDHC1_VSELECT 1
-#define SC_P_USDHC1_VSELECT_ADMA_SPI2_SDO SC_P_USDHC1_VSELECT 2
-#define SC_P_USDHC1_VSELECT_CONN_NAND_RE_B SC_P_USDHC1_VSELECT 3
-#define SC_P_USDHC1_VSELECT_LSIO_GPIO4_IO20 SC_P_USDHC1_VSELECT 4
-#define SC_P_USDHC1_WP_CONN_USDHC1_WP SC_P_USDHC1_WP 0
-#define SC_P_USDHC1_WP_CONN_NAND_DQS_N SC_P_USDHC1_WP 1
-#define SC_P_USDHC1_WP_ADMA_SPI2_SDI SC_P_USDHC1_WP 2
-#define SC_P_USDHC1_WP_LSIO_GPIO4_IO21 SC_P_USDHC1_WP 4
-#define SC_P_USDHC1_CD_B_CONN_USDHC1_CD_B SC_P_USDHC1_CD_B 0
-#define SC_P_USDHC1_CD_B_CONN_NAND_DQS_P SC_P_USDHC1_CD_B 1
-#define SC_P_USDHC1_CD_B_ADMA_SPI2_CS0 SC_P_USDHC1_CD_B 2
-#define SC_P_USDHC1_CD_B_CONN_NAND_DQS SC_P_USDHC1_CD_B 3
-#define SC_P_USDHC1_CD_B_LSIO_GPIO4_IO22 SC_P_USDHC1_CD_B 4
-#define SC_P_USDHC1_CLK_CONN_USDHC1_CLK SC_P_USDHC1_CLK 0
-#define SC_P_USDHC1_CLK_ADMA_UART3_RX SC_P_USDHC1_CLK 2
-#define SC_P_USDHC1_CLK_LSIO_GPIO4_IO23 SC_P_USDHC1_CLK 4
-#define SC_P_USDHC1_CMD_CONN_USDHC1_CMD SC_P_USDHC1_CMD 0
-#define SC_P_USDHC1_CMD_CONN_NAND_CE0_B SC_P_USDHC1_CMD 1
-#define SC_P_USDHC1_CMD_ADMA_MQS_R SC_P_USDHC1_CMD 2
-#define SC_P_USDHC1_CMD_LSIO_GPIO4_IO24 SC_P_USDHC1_CMD 4
-#define SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 SC_P_USDHC1_DATA0 0
-#define SC_P_USDHC1_DATA0_CONN_NAND_CE1_B SC_P_USDHC1_DATA0 1
-#define SC_P_USDHC1_DATA0_ADMA_MQS_L SC_P_USDHC1_DATA0 2
-#define SC_P_USDHC1_DATA0_LSIO_GPIO4_IO25 SC_P_USDHC1_DATA0 4
-#define SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 SC_P_USDHC1_DATA1 0
-#define SC_P_USDHC1_DATA1_CONN_NAND_RE_B SC_P_USDHC1_DATA1 1
-#define SC_P_USDHC1_DATA1_ADMA_UART3_TX SC_P_USDHC1_DATA1 2
-#define SC_P_USDHC1_DATA1_LSIO_GPIO4_IO26 SC_P_USDHC1_DATA1 4
-#define SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 SC_P_USDHC1_DATA2 0
-#define SC_P_USDHC1_DATA2_CONN_NAND_WE_B SC_P_USDHC1_DATA2 1
-#define SC_P_USDHC1_DATA2_ADMA_UART3_CTS_B SC_P_USDHC1_DATA2 2
-#define SC_P_USDHC1_DATA2_LSIO_GPIO4_IO27 SC_P_USDHC1_DATA2 4
-#define SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 SC_P_USDHC1_DATA3 0
-#define SC_P_USDHC1_DATA3_CONN_NAND_ALE SC_P_USDHC1_DATA3 1
-#define SC_P_USDHC1_DATA3_ADMA_UART3_RTS_B SC_P_USDHC1_DATA3 2
-#define SC_P_USDHC1_DATA3_LSIO_GPIO4_IO28 SC_P_USDHC1_DATA3 4
-#define SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC SC_P_ENET0_RGMII_TXC 0
-#define SC_P_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_OUT SC_P_ENET0_RGMII_TXC 1
-#define SC_P_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_IN SC_P_ENET0_RGMII_TXC 2
-#define SC_P_ENET0_RGMII_TXC_CONN_NAND_CE1_B SC_P_ENET0_RGMII_TXC 3
-#define SC_P_ENET0_RGMII_TXC_LSIO_GPIO4_IO29 SC_P_ENET0_RGMII_TXC 4
-#define SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL SC_P_ENET0_RGMII_TX_CTL 0
-#define SC_P_ENET0_RGMII_TX_CTL_CONN_USDHC1_RESET_B SC_P_ENET0_RGMII_TX_CTL 3
-#define SC_P_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30 SC_P_ENET0_RGMII_TX_CTL 4
-#define SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 SC_P_ENET0_RGMII_TXD0 0
-#define SC_P_ENET0_RGMII_TXD0_CONN_USDHC1_VSELECT SC_P_ENET0_RGMII_TXD0 3
-#define SC_P_ENET0_RGMII_TXD0_LSIO_GPIO4_IO31 SC_P_ENET0_RGMII_TXD0 4
-#define SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 SC_P_ENET0_RGMII_TXD1 0
-#define SC_P_ENET0_RGMII_TXD1_CONN_USDHC1_WP SC_P_ENET0_RGMII_TXD1 3
-#define SC_P_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00 SC_P_ENET0_RGMII_TXD1 4
-#define SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 SC_P_ENET0_RGMII_TXD2 0
-#define SC_P_ENET0_RGMII_TXD2_CONN_MLB_CLK SC_P_ENET0_RGMII_TXD2 1
-#define SC_P_ENET0_RGMII_TXD2_CONN_NAND_CE0_B SC_P_ENET0_RGMII_TXD2 2
-#define SC_P_ENET0_RGMII_TXD2_CONN_USDHC1_CD_B SC_P_ENET0_RGMII_TXD2 3
-#define SC_P_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01 SC_P_ENET0_RGMII_TXD2 4
-#define SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 SC_P_ENET0_RGMII_TXD3 0
-#define SC_P_ENET0_RGMII_TXD3_CONN_MLB_SIG SC_P_ENET0_RGMII_TXD3 1
-#define SC_P_ENET0_RGMII_TXD3_CONN_NAND_RE_B SC_P_ENET0_RGMII_TXD3 2
-#define SC_P_ENET0_RGMII_TXD3_LSIO_GPIO5_IO02 SC_P_ENET0_RGMII_TXD3 4
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0 0
-#define SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC SC_P_ENET0_RGMII_RXC 0
-#define SC_P_ENET0_RGMII_RXC_CONN_MLB_DATA SC_P_ENET0_RGMII_RXC 1
-#define SC_P_ENET0_RGMII_RXC_CONN_NAND_WE_B SC_P_ENET0_RGMII_RXC 2
-#define SC_P_ENET0_RGMII_RXC_CONN_USDHC1_CLK SC_P_ENET0_RGMII_RXC 3
-#define SC_P_ENET0_RGMII_RXC_LSIO_GPIO5_IO03 SC_P_ENET0_RGMII_RXC 4
-#define SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL SC_P_ENET0_RGMII_RX_CTL 0
-#define SC_P_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD SC_P_ENET0_RGMII_RX_CTL 3
-#define SC_P_ENET0_RGMII_RX_CTL_LSIO_GPIO5_IO04 SC_P_ENET0_RGMII_RX_CTL 4
-#define SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 SC_P_ENET0_RGMII_RXD0 0
-#define SC_P_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0 SC_P_ENET0_RGMII_RXD0 3
-#define SC_P_ENET0_RGMII_RXD0_LSIO_GPIO5_IO05 SC_P_ENET0_RGMII_RXD0 4
-#define SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 SC_P_ENET0_RGMII_RXD1 0
-#define SC_P_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1 SC_P_ENET0_RGMII_RXD1 3
-#define SC_P_ENET0_RGMII_RXD1_LSIO_GPIO5_IO06 SC_P_ENET0_RGMII_RXD1 4
-#define SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 SC_P_ENET0_RGMII_RXD2 0
-#define SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RMII_RX_ER SC_P_ENET0_RGMII_RXD2 1
-#define SC_P_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2 SC_P_ENET0_RGMII_RXD2 3
-#define SC_P_ENET0_RGMII_RXD2_LSIO_GPIO5_IO07 SC_P_ENET0_RGMII_RXD2 4
-#define SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 SC_P_ENET0_RGMII_RXD3 0
-#define SC_P_ENET0_RGMII_RXD3_CONN_NAND_ALE SC_P_ENET0_RGMII_RXD3 2
-#define SC_P_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3 SC_P_ENET0_RGMII_RXD3 3
-#define SC_P_ENET0_RGMII_RXD3_LSIO_GPIO5_IO08 SC_P_ENET0_RGMII_RXD3 4
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1 0
-#define SC_P_ENET0_REFCLK_125M_25M_CONN_ENET0_REFCLK_125M_25M SC_P_ENET0_REFCLK_125M_25M 0
-#define SC_P_ENET0_REFCLK_125M_25M_CONN_ENET0_PPS SC_P_ENET0_REFCLK_125M_25M 1
-#define SC_P_ENET0_REFCLK_125M_25M_CONN_ENET1_PPS SC_P_ENET0_REFCLK_125M_25M 2
-#define SC_P_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09 SC_P_ENET0_REFCLK_125M_25M 4
-#define SC_P_ENET0_MDIO_CONN_ENET0_MDIO SC_P_ENET0_MDIO 0
-#define SC_P_ENET0_MDIO_ADMA_I2C3_SDA SC_P_ENET0_MDIO 1
-#define SC_P_ENET0_MDIO_CONN_ENET1_MDIO SC_P_ENET0_MDIO 2
-#define SC_P_ENET0_MDIO_LSIO_GPIO5_IO10 SC_P_ENET0_MDIO 4
-#define SC_P_ENET0_MDC_CONN_ENET0_MDC SC_P_ENET0_MDC 0
-#define SC_P_ENET0_MDC_ADMA_I2C3_SCL SC_P_ENET0_MDC 1
-#define SC_P_ENET0_MDC_CONN_ENET1_MDC SC_P_ENET0_MDC 2
-#define SC_P_ENET0_MDC_LSIO_GPIO5_IO11 SC_P_ENET0_MDC 4
-#define SC_P_ESAI0_FSR_ADMA_ESAI0_FSR SC_P_ESAI0_FSR 0
-#define SC_P_ESAI0_FSR_CONN_ENET1_RCLK50M_OUT SC_P_ESAI0_FSR 1
-#define SC_P_ESAI0_FSR_ADMA_LCDIF_D00 SC_P_ESAI0_FSR 2
-#define SC_P_ESAI0_FSR_CONN_ENET1_RGMII_TXC SC_P_ESAI0_FSR 3
-#define SC_P_ESAI0_FSR_CONN_ENET1_RCLK50M_IN SC_P_ESAI0_FSR 4
-#define SC_P_ESAI0_FST_ADMA_ESAI0_FST SC_P_ESAI0_FST 0
-#define SC_P_ESAI0_FST_CONN_MLB_CLK SC_P_ESAI0_FST 1
-#define SC_P_ESAI0_FST_ADMA_LCDIF_D01 SC_P_ESAI0_FST 2
-#define SC_P_ESAI0_FST_CONN_ENET1_RGMII_TXD2 SC_P_ESAI0_FST 3
-#define SC_P_ESAI0_FST_LSIO_GPIO0_IO01 SC_P_ESAI0_FST 4
-#define SC_P_ESAI0_SCKR_ADMA_ESAI0_SCKR SC_P_ESAI0_SCKR 0
-#define SC_P_ESAI0_SCKR_ADMA_LCDIF_D02 SC_P_ESAI0_SCKR 2
-#define SC_P_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL SC_P_ESAI0_SCKR 3
-#define SC_P_ESAI0_SCKR_LSIO_GPIO0_IO02 SC_P_ESAI0_SCKR 4
-#define SC_P_ESAI0_SCKT_ADMA_ESAI0_SCKT SC_P_ESAI0_SCKT 0
-#define SC_P_ESAI0_SCKT_CONN_MLB_SIG SC_P_ESAI0_SCKT 1
-#define SC_P_ESAI0_SCKT_ADMA_LCDIF_D03 SC_P_ESAI0_SCKT 2
-#define SC_P_ESAI0_SCKT_CONN_ENET1_RGMII_TXD3 SC_P_ESAI0_SCKT 3
-#define SC_P_ESAI0_SCKT_LSIO_GPIO0_IO03 SC_P_ESAI0_SCKT 4
-#define SC_P_ESAI0_TX0_ADMA_ESAI0_TX0 SC_P_ESAI0_TX0 0
-#define SC_P_ESAI0_TX0_CONN_MLB_DATA SC_P_ESAI0_TX0 1
-#define SC_P_ESAI0_TX0_ADMA_LCDIF_D04 SC_P_ESAI0_TX0 2
-#define SC_P_ESAI0_TX0_CONN_ENET1_RGMII_RXC SC_P_ESAI0_TX0 3
-#define SC_P_ESAI0_TX0_LSIO_GPIO0_IO04 SC_P_ESAI0_TX0 4
-#define SC_P_ESAI0_TX1_ADMA_ESAI0_TX1 SC_P_ESAI0_TX1 0
-#define SC_P_ESAI0_TX1_ADMA_LCDIF_D05 SC_P_ESAI0_TX1 2
-#define SC_P_ESAI0_TX1_CONN_ENET1_RGMII_RXD3 SC_P_ESAI0_TX1 3
-#define SC_P_ESAI0_TX1_LSIO_GPIO0_IO05 SC_P_ESAI0_TX1 4
-#define SC_P_ESAI0_TX2_RX3_ADMA_ESAI0_TX2_RX3 SC_P_ESAI0_TX2_RX3 0
-#define SC_P_ESAI0_TX2_RX3_CONN_ENET1_RMII_RX_ER SC_P_ESAI0_TX2_RX3 1
-#define SC_P_ESAI0_TX2_RX3_ADMA_LCDIF_D06 SC_P_ESAI0_TX2_RX3 2
-#define SC_P_ESAI0_TX2_RX3_CONN_ENET1_RGMII_RXD2 SC_P_ESAI0_TX2_RX3 3
-#define SC_P_ESAI0_TX2_RX3_LSIO_GPIO0_IO06 SC_P_ESAI0_TX2_RX3 4
-#define SC_P_ESAI0_TX3_RX2_ADMA_ESAI0_TX3_RX2 SC_P_ESAI0_TX3_RX2 0
-#define SC_P_ESAI0_TX3_RX2_ADMA_LCDIF_D07 SC_P_ESAI0_TX3_RX2 2
-#define SC_P_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1 SC_P_ESAI0_TX3_RX2 3
-#define SC_P_ESAI0_TX3_RX2_LSIO_GPIO0_IO07 SC_P_ESAI0_TX3_RX2 4
-#define SC_P_ESAI0_TX4_RX1_ADMA_ESAI0_TX4_RX1 SC_P_ESAI0_TX4_RX1 0
-#define SC_P_ESAI0_TX4_RX1_ADMA_LCDIF_D08 SC_P_ESAI0_TX4_RX1 2
-#define SC_P_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0 SC_P_ESAI0_TX4_RX1 3
-#define SC_P_ESAI0_TX4_RX1_LSIO_GPIO0_IO08 SC_P_ESAI0_TX4_RX1 4
-#define SC_P_ESAI0_TX5_RX0_ADMA_ESAI0_TX5_RX0 SC_P_ESAI0_TX5_RX0 0
-#define SC_P_ESAI0_TX5_RX0_ADMA_LCDIF_D09 SC_P_ESAI0_TX5_RX0 2
-#define SC_P_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1 SC_P_ESAI0_TX5_RX0 3
-#define SC_P_ESAI0_TX5_RX0_LSIO_GPIO0_IO09 SC_P_ESAI0_TX5_RX0 4
-#define SC_P_SPDIF0_RX_ADMA_SPDIF0_RX SC_P_SPDIF0_RX 0
-#define SC_P_SPDIF0_RX_ADMA_MQS_R SC_P_SPDIF0_RX 1
-#define SC_P_SPDIF0_RX_ADMA_LCDIF_D10 SC_P_SPDIF0_RX 2
-#define SC_P_SPDIF0_RX_CONN_ENET1_RGMII_RXD0 SC_P_SPDIF0_RX 3
-#define SC_P_SPDIF0_RX_LSIO_GPIO0_IO10 SC_P_SPDIF0_RX 4
-#define SC_P_SPDIF0_TX_ADMA_SPDIF0_TX SC_P_SPDIF0_TX 0
-#define SC_P_SPDIF0_TX_ADMA_MQS_L SC_P_SPDIF0_TX 1
-#define SC_P_SPDIF0_TX_ADMA_LCDIF_D11 SC_P_SPDIF0_TX 2
-#define SC_P_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL SC_P_SPDIF0_TX 3
-#define SC_P_SPDIF0_TX_LSIO_GPIO0_IO11 SC_P_SPDIF0_TX 4
-#define SC_P_SPDIF0_EXT_CLK_ADMA_SPDIF0_EXT_CLK SC_P_SPDIF0_EXT_CLK 0
-#define SC_P_SPDIF0_EXT_CLK_ADMA_LCDIF_D12 SC_P_SPDIF0_EXT_CLK 2
-#define SC_P_SPDIF0_EXT_CLK_CONN_ENET1_REFCLK_125M_25M SC_P_SPDIF0_EXT_CLK 3
-#define SC_P_SPDIF0_EXT_CLK_LSIO_GPIO0_IO12 SC_P_SPDIF0_EXT_CLK 4
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB 0
-#define SC_P_SPI3_SCK_ADMA_SPI3_SCK SC_P_SPI3_SCK 0
-#define SC_P_SPI3_SCK_ADMA_LCDIF_D13 SC_P_SPI3_SCK 2
-#define SC_P_SPI3_SCK_LSIO_GPIO0_IO13 SC_P_SPI3_SCK 4
-#define SC_P_SPI3_SDO_ADMA_SPI3_SDO SC_P_SPI3_SDO 0
-#define SC_P_SPI3_SDO_ADMA_LCDIF_D14 SC_P_SPI3_SDO 2
-#define SC_P_SPI3_SDO_LSIO_GPIO0_IO14 SC_P_SPI3_SDO 4
-#define SC_P_SPI3_SDI_ADMA_SPI3_SDI SC_P_SPI3_SDI 0
-#define SC_P_SPI3_SDI_ADMA_LCDIF_D15 SC_P_SPI3_SDI 2
-#define SC_P_SPI3_SDI_LSIO_GPIO0_IO15 SC_P_SPI3_SDI 4
-#define SC_P_SPI3_CS0_ADMA_SPI3_CS0 SC_P_SPI3_CS0 0
-#define SC_P_SPI3_CS0_ADMA_ACM_MCLK_OUT1 SC_P_SPI3_CS0 1
-#define SC_P_SPI3_CS0_ADMA_LCDIF_HSYNC SC_P_SPI3_CS0 2
-#define SC_P_SPI3_CS0_LSIO_GPIO0_IO16 SC_P_SPI3_CS0 4
-#define SC_P_SPI3_CS1_ADMA_SPI3_CS1 SC_P_SPI3_CS1 0
-#define SC_P_SPI3_CS1_ADMA_I2C3_SCL SC_P_SPI3_CS1 1
-#define SC_P_SPI3_CS1_ADMA_LCDIF_RESET SC_P_SPI3_CS1 2
-#define SC_P_SPI3_CS1_ADMA_SPI2_CS0 SC_P_SPI3_CS1 3
-#define SC_P_SPI3_CS1_ADMA_LCDIF_D16 SC_P_SPI3_CS1 4
-#define SC_P_MCLK_IN1_ADMA_ACM_MCLK_IN1 SC_P_MCLK_IN1 0
-#define SC_P_MCLK_IN1_ADMA_I2C3_SDA SC_P_MCLK_IN1 1
-#define SC_P_MCLK_IN1_ADMA_LCDIF_EN SC_P_MCLK_IN1 2
-#define SC_P_MCLK_IN1_ADMA_SPI2_SCK SC_P_MCLK_IN1 3
-#define SC_P_MCLK_IN1_ADMA_LCDIF_D17 SC_P_MCLK_IN1 4
-#define SC_P_MCLK_IN0_ADMA_ACM_MCLK_IN0 SC_P_MCLK_IN0 0
-#define SC_P_MCLK_IN0_ADMA_ESAI0_RX_HF_CLK SC_P_MCLK_IN0 1
-#define SC_P_MCLK_IN0_ADMA_LCDIF_VSYNC SC_P_MCLK_IN0 2
-#define SC_P_MCLK_IN0_ADMA_SPI2_SDI SC_P_MCLK_IN0 3
-#define SC_P_MCLK_IN0_LSIO_GPIO0_IO19 SC_P_MCLK_IN0 4
-#define SC_P_MCLK_OUT0_ADMA_ACM_MCLK_OUT0 SC_P_MCLK_OUT0 0
-#define SC_P_MCLK_OUT0_ADMA_ESAI0_TX_HF_CLK SC_P_MCLK_OUT0 1
-#define SC_P_MCLK_OUT0_ADMA_LCDIF_CLK SC_P_MCLK_OUT0 2
-#define SC_P_MCLK_OUT0_ADMA_SPI2_SDO SC_P_MCLK_OUT0 3
-#define SC_P_MCLK_OUT0_LSIO_GPIO0_IO20 SC_P_MCLK_OUT0 4
-#define SC_P_UART1_TX_ADMA_UART1_TX SC_P_UART1_TX 0
-#define SC_P_UART1_TX_LSIO_PWM0_OUT SC_P_UART1_TX 1
-#define SC_P_UART1_TX_LSIO_GPT0_CAPTURE SC_P_UART1_TX 2
-#define SC_P_UART1_TX_LSIO_GPIO0_IO21 SC_P_UART1_TX 4
-#define SC_P_UART1_RX_ADMA_UART1_RX SC_P_UART1_RX 0
-#define SC_P_UART1_RX_LSIO_PWM1_OUT SC_P_UART1_RX 1
-#define SC_P_UART1_RX_LSIO_GPT0_COMPARE SC_P_UART1_RX 2
-#define SC_P_UART1_RX_LSIO_GPT1_CLK SC_P_UART1_RX 3
-#define SC_P_UART1_RX_LSIO_GPIO0_IO22 SC_P_UART1_RX 4
-#define SC_P_UART1_RTS_B_ADMA_UART1_RTS_B SC_P_UART1_RTS_B 0
-#define SC_P_UART1_RTS_B_LSIO_PWM2_OUT SC_P_UART1_RTS_B 1
-#define SC_P_UART1_RTS_B_ADMA_LCDIF_D16 SC_P_UART1_RTS_B 2
-#define SC_P_UART1_RTS_B_LSIO_GPT1_CAPTURE SC_P_UART1_RTS_B 3
-#define SC_P_UART1_RTS_B_LSIO_GPT0_CLK SC_P_UART1_RTS_B 4
-#define SC_P_UART1_CTS_B_ADMA_UART1_CTS_B SC_P_UART1_CTS_B 0
-#define SC_P_UART1_CTS_B_LSIO_PWM3_OUT SC_P_UART1_CTS_B 1
-#define SC_P_UART1_CTS_B_ADMA_LCDIF_D17 SC_P_UART1_CTS_B 2
-#define SC_P_UART1_CTS_B_LSIO_GPT1_COMPARE SC_P_UART1_CTS_B 3
-#define SC_P_UART1_CTS_B_LSIO_GPIO0_IO24 SC_P_UART1_CTS_B 4
-#define SC_P_SAI0_TXD_ADMA_SAI0_TXD SC_P_SAI0_TXD 0
-#define SC_P_SAI0_TXD_ADMA_SAI1_RXC SC_P_SAI0_TXD 1
-#define SC_P_SAI0_TXD_ADMA_SPI1_SDO SC_P_SAI0_TXD 2
-#define SC_P_SAI0_TXD_ADMA_LCDIF_D18 SC_P_SAI0_TXD 3
-#define SC_P_SAI0_TXD_LSIO_GPIO0_IO25 SC_P_SAI0_TXD 4
-#define SC_P_SAI0_TXC_ADMA_SAI0_TXC SC_P_SAI0_TXC 0
-#define SC_P_SAI0_TXC_ADMA_SAI1_TXD SC_P_SAI0_TXC 1
-#define SC_P_SAI0_TXC_ADMA_SPI1_SDI SC_P_SAI0_TXC 2
-#define SC_P_SAI0_TXC_ADMA_LCDIF_D19 SC_P_SAI0_TXC 3
-#define SC_P_SAI0_TXC_LSIO_GPIO0_IO26 SC_P_SAI0_TXC 4
-#define SC_P_SAI0_RXD_ADMA_SAI0_RXD SC_P_SAI0_RXD 0
-#define SC_P_SAI0_RXD_ADMA_SAI1_RXFS SC_P_SAI0_RXD 1
-#define SC_P_SAI0_RXD_ADMA_SPI1_CS0 SC_P_SAI0_RXD 2
-#define SC_P_SAI0_RXD_ADMA_LCDIF_D20 SC_P_SAI0_RXD 3
-#define SC_P_SAI0_RXD_LSIO_GPIO0_IO27 SC_P_SAI0_RXD 4
-#define SC_P_SAI0_TXFS_ADMA_SAI0_TXFS SC_P_SAI0_TXFS 0
-#define SC_P_SAI0_TXFS_ADMA_SPI2_CS1 SC_P_SAI0_TXFS 1
-#define SC_P_SAI0_TXFS_ADMA_SPI1_SCK SC_P_SAI0_TXFS 2
-#define SC_P_SAI0_TXFS_LSIO_GPIO0_IO28 SC_P_SAI0_TXFS 4
-#define SC_P_SAI1_RXD_ADMA_SAI1_RXD SC_P_SAI1_RXD 0
-#define SC_P_SAI1_RXD_ADMA_SAI0_RXFS SC_P_SAI1_RXD 1
-#define SC_P_SAI1_RXD_ADMA_SPI1_CS1 SC_P_SAI1_RXD 2
-#define SC_P_SAI1_RXD_ADMA_LCDIF_D21 SC_P_SAI1_RXD 3
-#define SC_P_SAI1_RXD_LSIO_GPIO0_IO29 SC_P_SAI1_RXD 4
-#define SC_P_SAI1_RXC_ADMA_SAI1_RXC SC_P_SAI1_RXC 0
-#define SC_P_SAI1_RXC_ADMA_SAI1_TXC SC_P_SAI1_RXC 1
-#define SC_P_SAI1_RXC_ADMA_LCDIF_D22 SC_P_SAI1_RXC 3
-#define SC_P_SAI1_RXC_LSIO_GPIO0_IO30 SC_P_SAI1_RXC 4
-#define SC_P_SAI1_RXFS_ADMA_SAI1_RXFS SC_P_SAI1_RXFS 0
-#define SC_P_SAI1_RXFS_ADMA_SAI1_TXFS SC_P_SAI1_RXFS 1
-#define SC_P_SAI1_RXFS_ADMA_LCDIF_D23 SC_P_SAI1_RXFS 3
-#define SC_P_SAI1_RXFS_LSIO_GPIO0_IO31 SC_P_SAI1_RXFS 4
-#define SC_P_SPI2_CS0_ADMA_SPI2_CS0 SC_P_SPI2_CS0 0
-#define SC_P_SPI2_CS0_LSIO_GPIO1_IO00 SC_P_SPI2_CS0 4
-#define SC_P_SPI2_SDO_ADMA_SPI2_SDO SC_P_SPI2_SDO 0
-#define SC_P_SPI2_SDO_LSIO_GPIO1_IO01 SC_P_SPI2_SDO 4
-#define SC_P_SPI2_SDI_ADMA_SPI2_SDI SC_P_SPI2_SDI 0
-#define SC_P_SPI2_SDI_LSIO_GPIO1_IO02 SC_P_SPI2_SDI 4
-#define SC_P_SPI2_SCK_ADMA_SPI2_SCK SC_P_SPI2_SCK 0
-#define SC_P_SPI2_SCK_LSIO_GPIO1_IO03 SC_P_SPI2_SCK 4
-#define SC_P_SPI0_SCK_ADMA_SPI0_SCK SC_P_SPI0_SCK 0
-#define SC_P_SPI0_SCK_ADMA_SAI0_TXC SC_P_SPI0_SCK 1
-#define SC_P_SPI0_SCK_M40_I2C0_SCL SC_P_SPI0_SCK 2
-#define SC_P_SPI0_SCK_M40_GPIO0_IO00 SC_P_SPI0_SCK 3
-#define SC_P_SPI0_SCK_LSIO_GPIO1_IO04 SC_P_SPI0_SCK 4
-#define SC_P_SPI0_SDI_ADMA_SPI0_SDI SC_P_SPI0_SDI 0
-#define SC_P_SPI0_SDI_ADMA_SAI0_TXD SC_P_SPI0_SDI 1
-#define SC_P_SPI0_SDI_M40_TPM0_CH0 SC_P_SPI0_SDI 2
-#define SC_P_SPI0_SDI_M40_GPIO0_IO02 SC_P_SPI0_SDI 3
-#define SC_P_SPI0_SDI_LSIO_GPIO1_IO05 SC_P_SPI0_SDI 4
-#define SC_P_SPI0_SDO_ADMA_SPI0_SDO SC_P_SPI0_SDO 0
-#define SC_P_SPI0_SDO_ADMA_SAI0_TXFS SC_P_SPI0_SDO 1
-#define SC_P_SPI0_SDO_M40_I2C0_SDA SC_P_SPI0_SDO 2
-#define SC_P_SPI0_SDO_M40_GPIO0_IO01 SC_P_SPI0_SDO 3
-#define SC_P_SPI0_SDO_LSIO_GPIO1_IO06 SC_P_SPI0_SDO 4
-#define SC_P_SPI0_CS1_ADMA_SPI0_CS1 SC_P_SPI0_CS1 0
-#define SC_P_SPI0_CS1_ADMA_SAI0_RXC SC_P_SPI0_CS1 1
-#define SC_P_SPI0_CS1_ADMA_SAI1_TXD SC_P_SPI0_CS1 2
-#define SC_P_SPI0_CS1_ADMA_LCD_PWM0_OUT SC_P_SPI0_CS1 3
-#define SC_P_SPI0_CS1_LSIO_GPIO1_IO07 SC_P_SPI0_CS1 4
-#define SC_P_SPI0_CS0_ADMA_SPI0_CS0 SC_P_SPI0_CS0 0
-#define SC_P_SPI0_CS0_ADMA_SAI0_RXD SC_P_SPI0_CS0 1
-#define SC_P_SPI0_CS0_M40_TPM0_CH1 SC_P_SPI0_CS0 2
-#define SC_P_SPI0_CS0_M40_GPIO0_IO03 SC_P_SPI0_CS0 3
-#define SC_P_SPI0_CS0_LSIO_GPIO1_IO08 SC_P_SPI0_CS0 4
-#define SC_P_ADC_IN1_ADMA_ADC_IN1 SC_P_ADC_IN1 0
-#define SC_P_ADC_IN1_M40_I2C0_SDA SC_P_ADC_IN1 1
-#define SC_P_ADC_IN1_M40_GPIO0_IO01 SC_P_ADC_IN1 2
-#define SC_P_ADC_IN1_LSIO_GPIO1_IO09 SC_P_ADC_IN1 4
-#define SC_P_ADC_IN0_ADMA_ADC_IN0 SC_P_ADC_IN0 0
-#define SC_P_ADC_IN0_M40_I2C0_SCL SC_P_ADC_IN0 1
-#define SC_P_ADC_IN0_M40_GPIO0_IO00 SC_P_ADC_IN0 2
-#define SC_P_ADC_IN0_LSIO_GPIO1_IO10 SC_P_ADC_IN0 4
-#define SC_P_ADC_IN3_ADMA_ADC_IN3 SC_P_ADC_IN3 0
-#define SC_P_ADC_IN3_M40_UART0_TX SC_P_ADC_IN3 1
-#define SC_P_ADC_IN3_M40_GPIO0_IO03 SC_P_ADC_IN3 2
-#define SC_P_ADC_IN3_ADMA_ACM_MCLK_OUT0 SC_P_ADC_IN3 3
-#define SC_P_ADC_IN3_LSIO_GPIO1_IO11 SC_P_ADC_IN3 4
-#define SC_P_ADC_IN2_ADMA_ADC_IN2 SC_P_ADC_IN2 0
-#define SC_P_ADC_IN2_M40_UART0_RX SC_P_ADC_IN2 1
-#define SC_P_ADC_IN2_M40_GPIO0_IO02 SC_P_ADC_IN2 2
-#define SC_P_ADC_IN2_ADMA_ACM_MCLK_IN0 SC_P_ADC_IN2 3
-#define SC_P_ADC_IN2_LSIO_GPIO1_IO12 SC_P_ADC_IN2 4
-#define SC_P_ADC_IN5_ADMA_ADC_IN5 SC_P_ADC_IN5 0
-#define SC_P_ADC_IN5_M40_TPM0_CH1 SC_P_ADC_IN5 1
-#define SC_P_ADC_IN5_M40_GPIO0_IO05 SC_P_ADC_IN5 2
-#define SC_P_ADC_IN5_LSIO_GPIO1_IO13 SC_P_ADC_IN5 4
-#define SC_P_ADC_IN4_ADMA_ADC_IN4 SC_P_ADC_IN4 0
-#define SC_P_ADC_IN4_M40_TPM0_CH0 SC_P_ADC_IN4 1
-#define SC_P_ADC_IN4_M40_GPIO0_IO04 SC_P_ADC_IN4 2
-#define SC_P_ADC_IN4_LSIO_GPIO1_IO14 SC_P_ADC_IN4 4
-#define SC_P_FLEXCAN0_RX_ADMA_FLEXCAN0_RX SC_P_FLEXCAN0_RX 0
-#define SC_P_FLEXCAN0_RX_ADMA_SAI2_RXC SC_P_FLEXCAN0_RX 1
-#define SC_P_FLEXCAN0_RX_ADMA_UART0_RTS_B SC_P_FLEXCAN0_RX 2
-#define SC_P_FLEXCAN0_RX_ADMA_SAI1_TXC SC_P_FLEXCAN0_RX 3
-#define SC_P_FLEXCAN0_RX_LSIO_GPIO1_IO15 SC_P_FLEXCAN0_RX 4
-#define SC_P_FLEXCAN0_TX_ADMA_FLEXCAN0_TX SC_P_FLEXCAN0_TX 0
-#define SC_P_FLEXCAN0_TX_ADMA_SAI2_RXD SC_P_FLEXCAN0_TX 1
-#define SC_P_FLEXCAN0_TX_ADMA_UART0_CTS_B SC_P_FLEXCAN0_TX 2
-#define SC_P_FLEXCAN0_TX_ADMA_SAI1_TXFS SC_P_FLEXCAN0_TX 3
-#define SC_P_FLEXCAN0_TX_LSIO_GPIO1_IO16 SC_P_FLEXCAN0_TX 4
-#define SC_P_FLEXCAN1_RX_ADMA_FLEXCAN1_RX SC_P_FLEXCAN1_RX 0
-#define SC_P_FLEXCAN1_RX_ADMA_SAI2_RXFS SC_P_FLEXCAN1_RX 1
-#define SC_P_FLEXCAN1_RX_ADMA_FTM_CH2 SC_P_FLEXCAN1_RX 2
-#define SC_P_FLEXCAN1_RX_ADMA_SAI1_TXD SC_P_FLEXCAN1_RX 3
-#define SC_P_FLEXCAN1_RX_LSIO_GPIO1_IO17 SC_P_FLEXCAN1_RX 4
-#define SC_P_FLEXCAN1_TX_ADMA_FLEXCAN1_TX SC_P_FLEXCAN1_TX 0
-#define SC_P_FLEXCAN1_TX_ADMA_SAI3_RXC SC_P_FLEXCAN1_TX 1
-#define SC_P_FLEXCAN1_TX_ADMA_DMA0_REQ_IN0 SC_P_FLEXCAN1_TX 2
-#define SC_P_FLEXCAN1_TX_ADMA_SAI1_RXD SC_P_FLEXCAN1_TX 3
-#define SC_P_FLEXCAN1_TX_LSIO_GPIO1_IO18 SC_P_FLEXCAN1_TX 4
-#define SC_P_FLEXCAN2_RX_ADMA_FLEXCAN2_RX SC_P_FLEXCAN2_RX 0
-#define SC_P_FLEXCAN2_RX_ADMA_SAI3_RXD SC_P_FLEXCAN2_RX 1
-#define SC_P_FLEXCAN2_RX_ADMA_UART3_RX SC_P_FLEXCAN2_RX 2
-#define SC_P_FLEXCAN2_RX_ADMA_SAI1_RXFS SC_P_FLEXCAN2_RX 3
-#define SC_P_FLEXCAN2_RX_LSIO_GPIO1_IO19 SC_P_FLEXCAN2_RX 4
-#define SC_P_FLEXCAN2_TX_ADMA_FLEXCAN2_TX SC_P_FLEXCAN2_TX 0
-#define SC_P_FLEXCAN2_TX_ADMA_SAI3_RXFS SC_P_FLEXCAN2_TX 1
-#define SC_P_FLEXCAN2_TX_ADMA_UART3_TX SC_P_FLEXCAN2_TX 2
-#define SC_P_FLEXCAN2_TX_ADMA_SAI1_RXC SC_P_FLEXCAN2_TX 3
-#define SC_P_FLEXCAN2_TX_LSIO_GPIO1_IO20 SC_P_FLEXCAN2_TX 4
-#define SC_P_UART0_RX_ADMA_UART0_RX SC_P_UART0_RX 0
-#define SC_P_UART0_RX_ADMA_MQS_R SC_P_UART0_RX 1
-#define SC_P_UART0_RX_ADMA_FLEXCAN0_RX SC_P_UART0_RX 2
-#define SC_P_UART0_RX_SCU_UART0_RX SC_P_UART0_RX 3
-#define SC_P_UART0_RX_LSIO_GPIO1_IO21 SC_P_UART0_RX 4
-#define SC_P_UART0_TX_ADMA_UART0_TX SC_P_UART0_TX 0
-#define SC_P_UART0_TX_ADMA_MQS_L SC_P_UART0_TX 1
-#define SC_P_UART0_TX_ADMA_FLEXCAN0_TX SC_P_UART0_TX 2
-#define SC_P_UART0_TX_SCU_UART0_TX SC_P_UART0_TX 3
-#define SC_P_UART0_TX_LSIO_GPIO1_IO22 SC_P_UART0_TX 4
-#define SC_P_UART2_TX_ADMA_UART2_TX SC_P_UART2_TX 0
-#define SC_P_UART2_TX_ADMA_FTM_CH1 SC_P_UART2_TX 1
-#define SC_P_UART2_TX_ADMA_FLEXCAN1_TX SC_P_UART2_TX 2
-#define SC_P_UART2_TX_LSIO_GPIO1_IO23 SC_P_UART2_TX 4
-#define SC_P_UART2_RX_ADMA_UART2_RX SC_P_UART2_RX 0
-#define SC_P_UART2_RX_ADMA_FTM_CH0 SC_P_UART2_RX 1
-#define SC_P_UART2_RX_ADMA_FLEXCAN1_RX SC_P_UART2_RX 2
-#define SC_P_UART2_RX_LSIO_GPIO1_IO24 SC_P_UART2_RX 4
-#define SC_P_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL SC_P_MIPI_DSI0_I2C0_SCL 0
-#define SC_P_MIPI_DSI0_I2C0_SCL_MIPI_DSI1_GPIO0_IO02 SC_P_MIPI_DSI0_I2C0_SCL 1
-#define SC_P_MIPI_DSI0_I2C0_SCL_LSIO_GPIO1_IO25 SC_P_MIPI_DSI0_I2C0_SCL 4
-#define SC_P_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA SC_P_MIPI_DSI0_I2C0_SDA 0
-#define SC_P_MIPI_DSI0_I2C0_SDA_MIPI_DSI1_GPIO0_IO03 SC_P_MIPI_DSI0_I2C0_SDA 1
-#define SC_P_MIPI_DSI0_I2C0_SDA_LSIO_GPIO1_IO26 SC_P_MIPI_DSI0_I2C0_SDA 4
-#define SC_P_MIPI_DSI0_GPIO0_00_MIPI_DSI0_GPIO0_IO00 SC_P_MIPI_DSI0_GPIO0_00 0
-#define SC_P_MIPI_DSI0_GPIO0_00_ADMA_I2C1_SCL SC_P_MIPI_DSI0_GPIO0_00 1
-#define SC_P_MIPI_DSI0_GPIO0_00_MIPI_DSI0_PWM0_OUT SC_P_MIPI_DSI0_GPIO0_00 2
-#define SC_P_MIPI_DSI0_GPIO0_00_LSIO_GPIO1_IO27 SC_P_MIPI_DSI0_GPIO0_00 4
-#define SC_P_MIPI_DSI0_GPIO0_01_MIPI_DSI0_GPIO0_IO01 SC_P_MIPI_DSI0_GPIO0_01 0
-#define SC_P_MIPI_DSI0_GPIO0_01_ADMA_I2C1_SDA SC_P_MIPI_DSI0_GPIO0_01 1
-#define SC_P_MIPI_DSI0_GPIO0_01_LSIO_GPIO1_IO28 SC_P_MIPI_DSI0_GPIO0_01 4
-#define SC_P_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL SC_P_MIPI_DSI1_I2C0_SCL 0
-#define SC_P_MIPI_DSI1_I2C0_SCL_MIPI_DSI0_GPIO0_IO02 SC_P_MIPI_DSI1_I2C0_SCL 1
-#define SC_P_MIPI_DSI1_I2C0_SCL_LSIO_GPIO1_IO29 SC_P_MIPI_DSI1_I2C0_SCL 4
-#define SC_P_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA SC_P_MIPI_DSI1_I2C0_SDA 0
-#define SC_P_MIPI_DSI1_I2C0_SDA_MIPI_DSI0_GPIO0_IO03 SC_P_MIPI_DSI1_I2C0_SDA 1
-#define SC_P_MIPI_DSI1_I2C0_SDA_LSIO_GPIO1_IO30 SC_P_MIPI_DSI1_I2C0_SDA 4
-#define SC_P_MIPI_DSI1_GPIO0_00_MIPI_DSI1_GPIO0_IO00 SC_P_MIPI_DSI1_GPIO0_00 0
-#define SC_P_MIPI_DSI1_GPIO0_00_ADMA_I2C2_SCL SC_P_MIPI_DSI1_GPIO0_00 1
-#define SC_P_MIPI_DSI1_GPIO0_00_MIPI_DSI1_PWM0_OUT SC_P_MIPI_DSI1_GPIO0_00 2
-#define SC_P_MIPI_DSI1_GPIO0_00_LSIO_GPIO1_IO31 SC_P_MIPI_DSI1_GPIO0_00 4
-#define SC_P_MIPI_DSI1_GPIO0_01_MIPI_DSI1_GPIO0_IO01 SC_P_MIPI_DSI1_GPIO0_01 0
-#define SC_P_MIPI_DSI1_GPIO0_01_ADMA_I2C2_SDA SC_P_MIPI_DSI1_GPIO0_01 1
-#define SC_P_MIPI_DSI1_GPIO0_01_LSIO_GPIO2_IO00 SC_P_MIPI_DSI1_GPIO0_01 4
-#define SC_P_JTAG_TRST_B_SCU_JTAG_TRST_B SC_P_JTAG_TRST_B 0
-#define SC_P_JTAG_TRST_B_SCU_WDOG0_WDOG_OUT SC_P_JTAG_TRST_B 1
-#define SC_P_PMIC_I2C_SCL_SCU_PMIC_I2C_SCL SC_P_PMIC_I2C_SCL 0
-#define SC_P_PMIC_I2C_SCL_SCU_GPIO0_IOXX_PMIC_A35_ON SC_P_PMIC_I2C_SCL 1
-#define SC_P_PMIC_I2C_SCL_LSIO_GPIO2_IO01 SC_P_PMIC_I2C_SCL 4
-#define SC_P_PMIC_I2C_SDA_SCU_PMIC_I2C_SDA SC_P_PMIC_I2C_SDA 0
-#define SC_P_PMIC_I2C_SDA_SCU_GPIO0_IOXX_PMIC_GPU_ON SC_P_PMIC_I2C_SDA 1
-#define SC_P_PMIC_I2C_SDA_LSIO_GPIO2_IO02 SC_P_PMIC_I2C_SDA 4
-#define SC_P_PMIC_INT_B_SCU_DSC_PMIC_INT_B SC_P_PMIC_INT_B 0
-#define SC_P_SCU_GPIO0_00_SCU_GPIO0_IO00 SC_P_SCU_GPIO0_00 0
-#define SC_P_SCU_GPIO0_00_SCU_UART0_RX SC_P_SCU_GPIO0_00 1
-#define SC_P_SCU_GPIO0_00_M40_UART0_RX SC_P_SCU_GPIO0_00 2
-#define SC_P_SCU_GPIO0_00_ADMA_UART3_RX SC_P_SCU_GPIO0_00 3
-#define SC_P_SCU_GPIO0_00_LSIO_GPIO2_IO03 SC_P_SCU_GPIO0_00 4
-#define SC_P_SCU_GPIO0_01_SCU_GPIO0_IO01 SC_P_SCU_GPIO0_01 0
-#define SC_P_SCU_GPIO0_01_SCU_UART0_TX SC_P_SCU_GPIO0_01 1
-#define SC_P_SCU_GPIO0_01_M40_UART0_TX SC_P_SCU_GPIO0_01 2
-#define SC_P_SCU_GPIO0_01_ADMA_UART3_TX SC_P_SCU_GPIO0_01 3
-#define SC_P_SCU_GPIO0_01_SCU_WDOG0_WDOG_OUT SC_P_SCU_GPIO0_01 4
-#define SC_P_SCU_PMIC_STANDBY_SCU_DSC_PMIC_STANDBY SC_P_SCU_PMIC_STANDBY 0
-#define SC_P_SCU_BOOT_MODE0_SCU_DSC_BOOT_MODE0 SC_P_SCU_BOOT_MODE0 0
-#define SC_P_SCU_BOOT_MODE1_SCU_DSC_BOOT_MODE1 SC_P_SCU_BOOT_MODE1 0
-#define SC_P_SCU_BOOT_MODE2_SCU_DSC_BOOT_MODE2 SC_P_SCU_BOOT_MODE2 0
-#define SC_P_SCU_BOOT_MODE2_SCU_PMIC_I2C_SDA SC_P_SCU_BOOT_MODE2 1
-#define SC_P_SCU_BOOT_MODE3_SCU_DSC_BOOT_MODE3 SC_P_SCU_BOOT_MODE3 0
-#define SC_P_SCU_BOOT_MODE3_SCU_PMIC_I2C_SCL SC_P_SCU_BOOT_MODE3 1
-#define SC_P_SCU_BOOT_MODE3_SCU_DSC_RTC_CLOCK_OUTPUT_32K SC_P_SCU_BOOT_MODE3 3
-#define SC_P_CSI_D00_CI_PI_D02 SC_P_CSI_D00 0
-#define SC_P_CSI_D00_ADMA_SAI0_RXC SC_P_CSI_D00 2
-#define SC_P_CSI_D01_CI_PI_D03 SC_P_CSI_D01 0
-#define SC_P_CSI_D01_ADMA_SAI0_RXD SC_P_CSI_D01 2
-#define SC_P_CSI_D02_CI_PI_D04 SC_P_CSI_D02 0
-#define SC_P_CSI_D02_ADMA_SAI0_RXFS SC_P_CSI_D02 2
-#define SC_P_CSI_D03_CI_PI_D05 SC_P_CSI_D03 0
-#define SC_P_CSI_D03_ADMA_SAI2_RXC SC_P_CSI_D03 2
-#define SC_P_CSI_D04_CI_PI_D06 SC_P_CSI_D04 0
-#define SC_P_CSI_D04_ADMA_SAI2_RXD SC_P_CSI_D04 2
-#define SC_P_CSI_D05_CI_PI_D07 SC_P_CSI_D05 0
-#define SC_P_CSI_D05_ADMA_SAI2_RXFS SC_P_CSI_D05 2
-#define SC_P_CSI_D06_CI_PI_D08 SC_P_CSI_D06 0
-#define SC_P_CSI_D06_ADMA_SAI3_RXC SC_P_CSI_D06 2
-#define SC_P_CSI_D07_CI_PI_D09 SC_P_CSI_D07 0
-#define SC_P_CSI_D07_ADMA_SAI3_RXD SC_P_CSI_D07 2
-#define SC_P_CSI_HSYNC_CI_PI_HSYNC SC_P_CSI_HSYNC 0
-#define SC_P_CSI_HSYNC_CI_PI_D00 SC_P_CSI_HSYNC 1
-#define SC_P_CSI_HSYNC_ADMA_SAI3_RXFS SC_P_CSI_HSYNC 2
-#define SC_P_CSI_VSYNC_CI_PI_VSYNC SC_P_CSI_VSYNC 0
-#define SC_P_CSI_VSYNC_CI_PI_D01 SC_P_CSI_VSYNC 1
-#define SC_P_CSI_PCLK_CI_PI_PCLK SC_P_CSI_PCLK 0
-#define SC_P_CSI_PCLK_MIPI_CSI0_I2C0_SCL SC_P_CSI_PCLK 1
-#define SC_P_CSI_PCLK_ADMA_SPI1_SCK SC_P_CSI_PCLK 3
-#define SC_P_CSI_PCLK_LSIO_GPIO3_IO00 SC_P_CSI_PCLK 4
-#define SC_P_CSI_MCLK_CI_PI_MCLK SC_P_CSI_MCLK 0
-#define SC_P_CSI_MCLK_MIPI_CSI0_I2C0_SDA SC_P_CSI_MCLK 1
-#define SC_P_CSI_MCLK_ADMA_SPI1_SDO SC_P_CSI_MCLK 3
-#define SC_P_CSI_MCLK_LSIO_GPIO3_IO01 SC_P_CSI_MCLK 4
-#define SC_P_CSI_EN_CI_PI_EN SC_P_CSI_EN 0
-#define SC_P_CSI_EN_CI_PI_I2C_SCL SC_P_CSI_EN 1
-#define SC_P_CSI_EN_ADMA_I2C3_SCL SC_P_CSI_EN 2
-#define SC_P_CSI_EN_ADMA_SPI1_SDI SC_P_CSI_EN 3
-#define SC_P_CSI_EN_LSIO_GPIO3_IO02 SC_P_CSI_EN 4
-#define SC_P_CSI_RESET_CI_PI_RESET SC_P_CSI_RESET 0
-#define SC_P_CSI_RESET_CI_PI_I2C_SDA SC_P_CSI_RESET 1
-#define SC_P_CSI_RESET_ADMA_I2C3_SDA SC_P_CSI_RESET 2
-#define SC_P_CSI_RESET_ADMA_SPI1_CS0 SC_P_CSI_RESET 3
-#define SC_P_CSI_RESET_LSIO_GPIO3_IO03 SC_P_CSI_RESET 4
-#define SC_P_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_ACM_MCLK_OUT SC_P_MIPI_CSI0_MCLK_OUT 0
-#define SC_P_MIPI_CSI0_MCLK_OUT_LSIO_GPIO3_IO04 SC_P_MIPI_CSI0_MCLK_OUT 4
-#define SC_P_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_I2C0_SCL SC_P_MIPI_CSI0_I2C0_SCL 0
-#define SC_P_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_GPIO0_IO02 SC_P_MIPI_CSI0_I2C0_SCL 1
-#define SC_P_MIPI_CSI0_I2C0_SCL_LSIO_GPIO3_IO05 SC_P_MIPI_CSI0_I2C0_SCL 4
-#define SC_P_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_I2C0_SDA SC_P_MIPI_CSI0_I2C0_SDA 0
-#define SC_P_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_GPIO0_IO03 SC_P_MIPI_CSI0_I2C0_SDA 1
-#define SC_P_MIPI_CSI0_I2C0_SDA_LSIO_GPIO3_IO06 SC_P_MIPI_CSI0_I2C0_SDA 4
-#define SC_P_MIPI_CSI0_GPIO0_01_MIPI_CSI0_GPIO0_IO01 SC_P_MIPI_CSI0_GPIO0_01 0
-#define SC_P_MIPI_CSI0_GPIO0_01_ADMA_I2C0_SDA SC_P_MIPI_CSI0_GPIO0_01 1
-#define SC_P_MIPI_CSI0_GPIO0_01_LSIO_GPIO3_IO07 SC_P_MIPI_CSI0_GPIO0_01 4
-#define SC_P_MIPI_CSI0_GPIO0_00_MIPI_CSI0_GPIO0_IO00 SC_P_MIPI_CSI0_GPIO0_00 0
-#define SC_P_MIPI_CSI0_GPIO0_00_ADMA_I2C0_SCL SC_P_MIPI_CSI0_GPIO0_00 1
-#define SC_P_MIPI_CSI0_GPIO0_00_LSIO_GPIO3_IO08 SC_P_MIPI_CSI0_GPIO0_00 4
-#define SC_P_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 SC_P_QSPI0A_DATA0 0
-#define SC_P_QSPI0A_DATA0_LSIO_GPIO3_IO09 SC_P_QSPI0A_DATA0 4
-#define SC_P_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 SC_P_QSPI0A_DATA1 0
-#define SC_P_QSPI0A_DATA1_LSIO_GPIO3_IO10 SC_P_QSPI0A_DATA1 4
-#define SC_P_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 SC_P_QSPI0A_DATA2 0
-#define SC_P_QSPI0A_DATA2_LSIO_GPIO3_IO11 SC_P_QSPI0A_DATA2 4
-#define SC_P_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 SC_P_QSPI0A_DATA3 0
-#define SC_P_QSPI0A_DATA3_LSIO_GPIO3_IO12 SC_P_QSPI0A_DATA3 4
-#define SC_P_QSPI0A_DQS_LSIO_QSPI0A_DQS SC_P_QSPI0A_DQS 0
-#define SC_P_QSPI0A_DQS_LSIO_GPIO3_IO13 SC_P_QSPI0A_DQS 4
-#define SC_P_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B SC_P_QSPI0A_SS0_B 0
-#define SC_P_QSPI0A_SS0_B_LSIO_GPIO3_IO14 SC_P_QSPI0A_SS0_B 4
-#define SC_P_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B SC_P_QSPI0A_SS1_B 0
-#define SC_P_QSPI0A_SS1_B_LSIO_GPIO3_IO15 SC_P_QSPI0A_SS1_B 4
-#define SC_P_QSPI0A_SCLK_LSIO_QSPI0A_SCLK SC_P_QSPI0A_SCLK 0
-#define SC_P_QSPI0A_SCLK_LSIO_GPIO3_IO16 SC_P_QSPI0A_SCLK 4
-#define SC_P_QSPI0B_SCLK_LSIO_QSPI0B_SCLK SC_P_QSPI0B_SCLK 0
-#define SC_P_QSPI0B_SCLK_LSIO_QSPI1A_SCLK SC_P_QSPI0B_SCLK 1
-#define SC_P_QSPI0B_SCLK_LSIO_KPP0_COL0 SC_P_QSPI0B_SCLK 2
-#define SC_P_QSPI0B_SCLK_LSIO_GPIO3_IO17 SC_P_QSPI0B_SCLK 4
-#define SC_P_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 SC_P_QSPI0B_DATA0 0
-#define SC_P_QSPI0B_DATA0_LSIO_QSPI1A_DATA0 SC_P_QSPI0B_DATA0 1
-#define SC_P_QSPI0B_DATA0_LSIO_KPP0_COL1 SC_P_QSPI0B_DATA0 2
-#define SC_P_QSPI0B_DATA0_LSIO_GPIO3_IO18 SC_P_QSPI0B_DATA0 4
-#define SC_P_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 SC_P_QSPI0B_DATA1 0
-#define SC_P_QSPI0B_DATA1_LSIO_QSPI1A_DATA1 SC_P_QSPI0B_DATA1 1
-#define SC_P_QSPI0B_DATA1_LSIO_KPP0_COL2 SC_P_QSPI0B_DATA1 2
-#define SC_P_QSPI0B_DATA1_LSIO_GPIO3_IO19 SC_P_QSPI0B_DATA1 4
-#define SC_P_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 SC_P_QSPI0B_DATA2 0
-#define SC_P_QSPI0B_DATA2_LSIO_QSPI1A_DATA2 SC_P_QSPI0B_DATA2 1
-#define SC_P_QSPI0B_DATA2_LSIO_KPP0_COL3 SC_P_QSPI0B_DATA2 2
-#define SC_P_QSPI0B_DATA2_LSIO_GPIO3_IO20 SC_P_QSPI0B_DATA2 4
-#define SC_P_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 SC_P_QSPI0B_DATA3 0
-#define SC_P_QSPI0B_DATA3_LSIO_QSPI1A_DATA3 SC_P_QSPI0B_DATA3 1
-#define SC_P_QSPI0B_DATA3_LSIO_KPP0_ROW0 SC_P_QSPI0B_DATA3 2
-#define SC_P_QSPI0B_DATA3_LSIO_GPIO3_IO21 SC_P_QSPI0B_DATA3 4
-#define SC_P_QSPI0B_DQS_LSIO_QSPI0B_DQS SC_P_QSPI0B_DQS 0
-#define SC_P_QSPI0B_DQS_LSIO_QSPI1A_DQS SC_P_QSPI0B_DQS 1
-#define SC_P_QSPI0B_DQS_LSIO_KPP0_ROW1 SC_P_QSPI0B_DQS 2
-#define SC_P_QSPI0B_DQS_LSIO_GPIO3_IO22 SC_P_QSPI0B_DQS 4
-#define SC_P_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B SC_P_QSPI0B_SS0_B 0
-#define SC_P_QSPI0B_SS0_B_LSIO_QSPI1A_SS0_B SC_P_QSPI0B_SS0_B 1
-#define SC_P_QSPI0B_SS0_B_LSIO_KPP0_ROW2 SC_P_QSPI0B_SS0_B 2
-#define SC_P_QSPI0B_SS0_B_LSIO_GPIO3_IO23 SC_P_QSPI0B_SS0_B 4
-#define SC_P_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B SC_P_QSPI0B_SS1_B 0
-#define SC_P_QSPI0B_SS1_B_LSIO_QSPI1A_SS1_B SC_P_QSPI0B_SS1_B 1
-#define SC_P_QSPI0B_SS1_B_LSIO_KPP0_ROW3 SC_P_QSPI0B_SS1_B 2
-#define SC_P_QSPI0B_SS1_B_LSIO_GPIO3_IO24 SC_P_QSPI0B_SS1_B 4
-
-#endif /* _SC_PADS_H */
diff --git a/include/dt-bindings/pinctrl/pinctrl-snapdragon.h b/include/dt-bindings/pinctrl/pinctrl-snapdragon.h
deleted file mode 100644
index 615affb..0000000
--- a/include/dt-bindings/pinctrl/pinctrl-snapdragon.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * This header provides constants for Qualcomm Snapdragon pinctrl bindings.
- *
- * (C) Copyright 2018 Ramon Fried <ramon.fried@gmail.com>
- *
- */
-
-#ifndef _DT_BINDINGS_PINCTRL_SNAPDRAGON_H
-#define _DT_BINDINGS_PINCTRL_SNAPDRAGON_H
-
-/* GPIO Drive Strength */
-#define DRIVE_STRENGTH_2MA 0
-#define DRIVE_STRENGTH_4MA 1
-#define DRIVE_STRENGTH_6MA 2
-#define DRIVE_STRENGTH_8MA 3
-#define DRIVE_STRENGTH_10MA 4
-#define DRIVE_STRENGTH_12MA 5
-#define DRIVE_STRENGTH_14MA 6
-#define DRIVE_STRENGTH_16MA 7
-
-#endif
diff --git a/include/dt-bindings/pinctrl/pinctrl-tegra-xusb.h b/include/dt-bindings/pinctrl/pinctrl-tegra-xusb.h
deleted file mode 100644
index 914d56d..0000000
--- a/include/dt-bindings/pinctrl/pinctrl-tegra-xusb.h
+++ /dev/null
@@ -1,7 +0,0 @@
-#ifndef _DT_BINDINGS_PINCTRL_TEGRA_XUSB_H
-#define _DT_BINDINGS_PINCTRL_TEGRA_XUSB_H 1
-
-#define TEGRA_XUSB_PADCTL_PCIE 0
-#define TEGRA_XUSB_PADCTL_SATA 1
-
-#endif /* _DT_BINDINGS_PINCTRL_TEGRA_XUSB_H */
diff --git a/include/dt-bindings/pinctrl/pinctrl-tegra.h b/include/dt-bindings/pinctrl/pinctrl-tegra.h
deleted file mode 100644
index c9b5740..0000000
--- a/include/dt-bindings/pinctrl/pinctrl-tegra.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * This header provides constants for Tegra pinctrl bindings.
- *
- * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved.
- *
- * Author: Laxman Dewangan <ldewangan@nvidia.com>
- */
-
-#ifndef _DT_BINDINGS_PINCTRL_TEGRA_H
-#define _DT_BINDINGS_PINCTRL_TEGRA_H
-
-/*
- * Enable/disable for diffeent dt properties. This is applicable for
- * properties nvidia,enable-input, nvidia,tristate, nvidia,open-drain,
- * nvidia,lock, nvidia,rcv-sel, nvidia,high-speed-mode, nvidia,schmitt.
- */
-#define TEGRA_PIN_DISABLE 0
-#define TEGRA_PIN_ENABLE 1
-
-#define TEGRA_PIN_PULL_NONE 0
-#define TEGRA_PIN_PULL_DOWN 1
-#define TEGRA_PIN_PULL_UP 2
-
-/* Low power mode driver */
-#define TEGRA_PIN_LP_DRIVE_DIV_8 0
-#define TEGRA_PIN_LP_DRIVE_DIV_4 1
-#define TEGRA_PIN_LP_DRIVE_DIV_2 2
-#define TEGRA_PIN_LP_DRIVE_DIV_1 3
-
-/* Rising/Falling slew rate */
-#define TEGRA_PIN_SLEW_RATE_FASTEST 0
-#define TEGRA_PIN_SLEW_RATE_FAST 1
-#define TEGRA_PIN_SLEW_RATE_SLOW 2
-#define TEGRA_PIN_SLEW_RATE_SLOWEST 3
-
-#endif
diff --git a/include/dt-bindings/pinctrl/pins-imx8mq.h b/include/dt-bindings/pinctrl/pins-imx8mq.h
deleted file mode 100644
index 0e1d67d..0000000
--- a/include/dt-bindings/pinctrl/pins-imx8mq.h
+++ /dev/null
@@ -1,632 +0,0 @@
-/*
- * Copyright (C) 2016 Freescale Semiconductor, Inc.
- * Copyright 2017 NXP
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef __DTS_IMX8MQ_PINFUNC_H
-#define __DTS_IMX8MQ_PINFUNC_H
-
-/*
- * The pin function ID is a tuple of
- * <mux_reg conf_reg input_reg mux_mode input_val>
- */
-
-#define MX8MQ_IOMUXC_PMIC_STBY_REQ_CCMSRCGPCMIX_PMIC_STBY_REQ 0x014 0x27C 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_PMIC_ON_REQ_SNVSMIX_PMIC_ON_REQ 0x018 0x280 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_ONOFF_SNVSMIX_ONOFF 0x01C 0x284 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_POR_B_SNVSMIX_POR_B 0x020 0x288 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_RTC_RESET_B_SNVSMIX_RTC_RESET_B 0x024 0x28C 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO01_ANAMIX_REF_CLK_24M 0x02C 0x294 0x4BC 0x5 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO01_CCMSRCGPCMIX_EXT_CLK2 0x02C 0x294 0x000 0x6 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO01_SJC_ACTIVE 0x02C 0x294 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO02_GPIO1_IO2 0x030 0x298 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x030 0x298 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x030 0x298 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO02_SJC_DE_B 0x030 0x298 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x034 0x29C 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x034 0x29C 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x034 0x29C 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO03_ANAMIX_XTAL_OK 0x034 0x29C 0x000 0x6 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO03_SJC_DONE 0x034 0x29C 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x038 0x2A0 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x038 0x2A0 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x038 0x2A0 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO04_ANAMIX_XTAL_OK_LV 0x038 0x2A0 0x000 0x6 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO04_USDHC1_TEST_TRIG 0x038 0x2A0 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x03C 0x2A4 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO05_M4_NMI 0x03C 0x2A4 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO05_CCMSRCGPCMIX_PMIC_READY 0x03C 0x2A4 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO05_CCMSRCGPCMIX_INT_BOOT 0x03C 0x2A4 0x000 0x6 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO05_USDHC2_TEST_TRIG 0x03C 0x2A4 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x040 0x2A8 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO06_ENET1_MDC 0x040 0x2A8 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x040 0x2A8 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO06_CCMSRCGPCMIX_EXT_CLK3 0x040 0x2A8 0x000 0x6 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO06_ECSPI1_TEST_TRIG 0x040 0x2A8 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x044 0x2AC 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO07_ENET1_MDIO 0x044 0x2AC 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO07_USDHC1_WP 0x044 0x2AC 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO07_CCMSRCGPCMIX_EXT_CLK4 0x044 0x2AC 0x000 0x6 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO07_ECSPI2_TEST_TRIG 0x044 0x2AC 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x048 0x2B0 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x048 0x2B0 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x048 0x2B0 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO08_CCMSRCGPCMIX_WAIT 0x048 0x2B0 0x000 0x6 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO08_QSPI_TEST_TRIG 0x048 0x2B0 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x04C 0x2B4 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x04C 0x2B4 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x04C 0x2B4 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO09_CCMSRCGPCMIX_STOP 0x04C 0x2B4 0x000 0x6 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO09_RAWNAND_TEST_TRIG 0x04C 0x2B4 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x050 0x2B8 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x050 0x2B8 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO10_OCOTP_CTRL_WRAPPER_FUSE_LATCHED 0x050 0x2B8 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x054 0x2BC 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO11_USB2_OTG_ID 0x054 0x2BC 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO11_CCMSRCGPCMIX_PMIC_READY 0x054 0x2BC 0x4BC 0x5 0x1
-#define MX8MQ_IOMUXC_GPIO1_IO11_CCMSRCGPCMIX_OUT0 0x054 0x2BC 0x000 0x6 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO11_CAAM_WRAPPER_RNG_OSC_OBS 0x054 0x2BC 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x058 0x2C0 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x058 0x2C0 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x058 0x2C0 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO12_CCMSRCGPCMIX_OUT1 0x058 0x2C0 0x000 0x6 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO12_CSU_CSU_ALARM_AUT0 0x058 0x2C0 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x05C 0x2C4 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x05C 0x2C4 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO13_PWM2_OUT 0x05C 0x2C4 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO13_CCMSRCGPCMIX_OUT2 0x05C 0x2C4 0x000 0x6 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO13_CSU_CSU_ALARM_AUT1 0x05C 0x2C4 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x060 0x2C8 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO14_USB2_OTG_PWR 0x060 0x2C8 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO14_PWM3_OUT 0x060 0x2C8 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x060 0x2C8 0x000 0x6 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO14_CSU_CSU_ALARM_AUT2 0x060 0x2C8 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x064 0x2CC 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x064 0x2CC 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO15_PWM4_OUT 0x064 0x2CC 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2 0x064 0x2CC 0x000 0x6 0x0
-#define MX8MQ_IOMUXC_GPIO1_IO15_CSU_CSU_INT_DEB 0x064 0x2CC 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x068 0x2D0 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_ENET_MDC_GPIO1_IO16 0x068 0x2D0 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x06C 0x2D4 0x4C0 0x0 0x1
-#define MX8MQ_IOMUXC_ENET_MDIO_GPIO1_IO17 0x06C 0x2D4 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x070 0x2D8 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_ENET_TD3_GPIO1_IO18 0x070 0x2D8 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x074 0x2DC 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_ENET_TD2_ENET1_TX_CLK 0x074 0x2DC 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_ENET_TD2_GPIO1_IO19 0x074 0x2DC 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x078 0x2E0 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_ENET_TD1_GPIO1_IO20 0x078 0x2E0 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x07C 0x2E4 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_ENET_TD0_GPIO1_IO21 0x07C 0x2E4 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x080 0x2E8 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x080 0x2E8 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x084 0x2EC 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_ENET_TXC_ENET1_TX_ER 0x084 0x2EC 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_ENET_TXC_GPIO1_IO23 0x084 0x2EC 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x088 0x2F0 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x088 0x2F0 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x08C 0x2F4 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_ENET_RXC_ENET1_RX_ER 0x08C 0x2F4 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_ENET_RXC_GPIO1_IO25 0x08C 0x2F4 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x090 0x2F8 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_ENET_RD0_GPIO1_IO26 0x090 0x2F8 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x094 0x2FC 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_ENET_RD1_GPIO1_IO27 0x094 0x2FC 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x098 0x300 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_ENET_RD2_GPIO1_IO28 0x098 0x300 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x09C 0x304 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_ENET_RD3_GPIO1_IO29 0x09C 0x304 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x0A0 0x308 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SD1_CLK_GPIO2_IO0 0x0A0 0x308 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0x0A4 0x30C 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SD1_CMD_GPIO2_IO1 0x0A4 0x30C 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x0A8 0x310 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SD1_DATA0_GPIO2_IO2 0x0A8 0x31 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x0AC 0x314 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SD1_DATA1_GPIO2_IO3 0x0AC 0x314 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x0B0 0x318 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SD1_DATA2_GPIO2_IO4 0x0B0 0x318 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x0B4 0x31C 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SD1_DATA3_GPIO2_IO5 0x0B4 0x31C 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x0B8 0x320 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SD1_DATA4_GPIO2_IO6 0x0B8 0x320 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x0BC 0x324 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SD1_DATA5_GPIO2_IO7 0x0BC 0x324 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x0C0 0x328 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SD1_DATA6_GPIO2_IO8 0x0C0 0x328 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x0C4 0x32C 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SD1_DATA7_GPIO2_IO9 0x0C4 0x32C 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x0C8 0x330 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x0C8 0x330 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x0CC 0x334 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SD1_STROBE_GPIO2_IO11 0x0CC 0x334 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x0D0 0x338 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x0D0 0x338 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x0D4 0x33C 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SD2_CLK_GPIO2_IO13 0x0D4 0x33C 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SD2_CLK_CCMSRCGPCMIX_OBSERVE0 0x0D4 0x33C 0x000 0x6 0x0
-#define MX8MQ_IOMUXC_SD2_CLK_OBSERVE_MUX_OUT0 0x0D4 0x33C 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0x0D8 0x340 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SD2_CMD_GPIO2_IO14 0x0D8 0x340 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SD2_CMD_CCMSRCGPCMIX_OBSERVE1 0x0D8 0x340 0x000 0x6 0x0
-#define MX8MQ_IOMUXC_SD2_CMD_OBSERVE_MUX_OUT1 0x0D8 0x340 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x0DC 0x344 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SD2_DATA0_GPIO2_IO15 0x0DC 0x344 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SD2_DATA0_CCMSRCGPCMIX_OBSERVE2 0x0DC 0x344 0x000 0x6 0x0
-#define MX8MQ_IOMUXC_SD2_DATA0_OBSERVE_MUX_OUT2 0x0DC 0x344 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x0E0 0x348 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SD2_DATA1_GPIO2_IO16 0x0E0 0x348 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SD2_DATA1_CCMSRCGPCMIX_WAIT 0x0E0 0x348 0x000 0x6 0x0
-#define MX8MQ_IOMUXC_SD2_DATA1_OBSERVE_MUX_OUT3 0x0E0 0x348 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x0E4 0x34C 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SD2_DATA2_GPIO2_IO17 0x0E4 0x34C 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SD2_DATA2_CCMSRCGPCMIX_STOP 0x0E4 0x34C 0x000 0x6 0x0
-#define MX8MQ_IOMUXC_SD2_DATA2_OBSERVE_MUX_OUT4 0x0E4 0x34C 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x0E8 0x350 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SD2_DATA3_GPIO2_IO18 0x0E8 0x350 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SD2_DATA3_CCMSRCGPCMIX_EARLY_RESET 0x0E8 0x350 0x000 0x6 0x0
-#define MX8MQ_IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x0EC 0x354 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x0EC 0x354 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SD2_RESET_B_CCMSRCGPCMIX_SYSTEM_RESET 0x0EC 0x354 0x000 0x6 0x0
-#define MX8MQ_IOMUXC_SD2_WP_USDHC2_WP 0x0F0 0x358 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SD2_WP_GPIO2_IO20 0x0F0 0x358 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SD2_WP_SIM_M_HMASTLOCK 0x0F0 0x358 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_NAND_ALE_RAWNAND_ALE 0x0F4 0x35C 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x0F4 0x35C 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_NAND_ALE_GPIO3_IO0 0x0F4 0x35C 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_NAND_ALE_SIM_M_HPROT0 0x0F4 0x35C 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x0F8 0x360 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x0F8 0x360 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x0F8 0x360 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_NAND_CE0_B_SIM_M_HPROT1 0x0F8 0x360 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x0FC 0x364 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x0FC 0x364 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x0FC 0x364 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_NAND_CE1_B_SIM_M_HPROT2 0x0FC 0x364 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x100 0x368 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x100 0x368 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x100 0x368 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_NAND_CE2_B_SIM_M_HPROT3 0x100 0x368 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 0x104 0x36C 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x104 0x36C 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x104 0x36C 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_NAND_CE3_B_SIM_M_HADDR0 0x104 0x36C 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_NAND_CLE_RAWNAND_CLE 0x108 0x370 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_NAND_CLE_QSPI_B_SCLK 0x108 0x370 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x108 0x370 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_NAND_CLE_SIM_M_HADDR1 0x108 0x370 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x10C 0x374 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x10C 0x374 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_NAND_DATA00_GPIO3_IO6 0x10C 0x374 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_NAND_DATA00_SIM_M_HADDR2 0x10C 0x374 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x110 0x378 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x110 0x378 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_NAND_DATA01_GPIO3_IO7 0x110 0x378 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_NAND_DATA01_SIM_M_HADDR3 0x110 0x378 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x114 0x37C 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x114 0x37C 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_NAND_DATA02_GPIO3_IO8 0x114 0x37C 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_NAND_DATA02_SIM_M_HADDR4 0x114 0x37C 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x118 0x380 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x118 0x380 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_NAND_DATA03_GPIO3_IO9 0x118 0x380 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_NAND_DATA03_SIM_M_HADDR5 0x118 0x380 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x11C 0x384 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x11C 0x384 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_NAND_DATA04_GPIO3_IO10 0x11C 0x384 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_NAND_DATA04_SIM_M_HADDR6 0x11C 0x384 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x120 0x388 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x120 0x388 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11 0x120 0x388 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_NAND_DATA05_SIM_M_HADDR7 0x120 0x388 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x124 0x38C 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x124 0x38C 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12 0x124 0x38C 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_NAND_DATA06_SIM_M_HADDR8 0x124 0x38C 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x128 0x390 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x128 0x390 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_NAND_DATA07_GPIO3_IO13 0x128 0x390 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_NAND_DATA07_SIM_M_HADDR9 0x128 0x390 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_NAND_DQS_RAWNAND_DQS 0x12C 0x394 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_NAND_DQS_QSPI_A_DQS 0x12C 0x394 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_NAND_DQS_GPIO3_IO14 0x12C 0x394 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_NAND_DQS_SIM_M_HADDR10 0x12C 0x394 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x130 0x398 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_NAND_RE_B_QSPI_B_DQS 0x130 0x398 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_NAND_RE_B_GPIO3_IO15 0x130 0x398 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_NAND_RE_B_SIM_M_HADDR11 0x130 0x398 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x134 0x39C 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_NAND_READY_B_GPIO3_IO16 0x134 0x39C 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_NAND_READY_B_SIM_M_HADDR12 0x134 0x39C 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x138 0x3A0 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_NAND_WE_B_GPIO3_IO17 0x138 0x3A0 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_NAND_WE_B_SIM_M_HADDR13 0x138 0x3A0 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x13C 0x3A4 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_NAND_WP_B_GPIO3_IO18 0x13C 0x3A4 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_NAND_WP_B_SIM_M_HADDR14 0x13C 0x3A4 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x140 0x3A8 0x4E4 0x0 0x0
-#define MX8MQ_IOMUXC_SAI5_RXFS_SAI1_TX_DATA0 0x140 0x3A8 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x140 0x3A8 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x144 0x3AC 0x4D0 0x0 0x0
-#define MX8MQ_IOMUXC_SAI5_RXC_SAI1_TX_DATA1 0x144 0x3AC 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20 0x144 0x3AC 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x148 0x3B0 0x4D4 0x0 0x0
-#define MX8MQ_IOMUXC_SAI5_RXD0_SAI1_TX_DATA2 0x148 0x3B0 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x148 0x3B0 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x14C 0x3B4 0x4D8 0x0 0x0
-#define MX8MQ_IOMUXC_SAI5_RXD1_SAI1_TX_DATA3 0x14C 0x3B4 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_SAI5_RXD1_SAI1_TX_SYNC 0x14C 0x3B4 0x4CC 0x2 0x0
-#define MX8MQ_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x14C 0x3B4 0x4EC 0x3 0x0
-#define MX8MQ_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x14C 0x3B4 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x150 0x3B8 0x4DC 0x0 0x0
-#define MX8MQ_IOMUXC_SAI5_RXD2_SAI1_TX_DATA4 0x150 0x3B8 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_SAI5_RXD2_SAI1_TX_SYNC 0x150 0x3B8 0x4CC 0x2 0x1
-#define MX8MQ_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x150 0x3B8 0x4E8 0x3 0x0
-#define MX8MQ_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x150 0x3B8 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x154 0x3BC 0x4E0 0x0 0x0
-#define MX8MQ_IOMUXC_SAI5_RXD3_SAI1_TX_DATA5 0x154 0x3BC 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_SAI5_RXD3_SAI1_TX_SYNC 0x154 0x3BC 0x4CC 0x2 0x2
-#define MX8MQ_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x154 0x3BC 0x000 0x3 0x0
-#define MX8MQ_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x154 0x3BC 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SAI5_MCLK_SAI5_MCLK 0x158 0x3C0 0x52C 0x0 0x0
-#define MX8MQ_IOMUXC_SAI5_MCLK_SAI1_TX_BCLK 0x158 0x3C0 0x4C8 0x1 0x0
-#define MX8MQ_IOMUXC_SAI5_MCLK_SAI4_MCLK 0x158 0x3C0 0x000 0x2 0x0
-#define MX8MQ_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x158 0x3C0 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SAI5_MCLK_CCMSRCGPCMIX_TESTER_ACK 0x158 0x3C0 0x000 0x6 0x0
-#define MX8MQ_IOMUXC_SAI1_RXFS_SAI1_RX_SYNC 0x15C 0x3C4 0x4C4 0x0 0x0
-#define MX8MQ_IOMUXC_SAI1_RXFS_SAI5_RX_SYNC 0x15C 0x3C4 0x4E4 0x1 0x1
-#define MX8MQ_IOMUXC_SAI1_RXFS_CORESIGHT_TRACE_CLK 0x15C 0x3C4 0x000 0x4 0x0
-#define MX8MQ_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x15C 0x3C4 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SAI1_RXFS_SIM_M_HADDR15 0x15C 0x3C4 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_SAI1_RXC_SAI1_RX_BCLK 0x160 0x3C8 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SAI1_RXC_SAI5_RX_BCLK 0x160 0x3C8 0x4D0 0x1 0x1
-#define MX8MQ_IOMUXC_SAI1_RXC_CORESIGHT_TRACE_CTL 0x160 0x3C8 0x000 0x4 0x0
-#define MX8MQ_IOMUXC_SAI1_RXC_GPIO4_IO1 0x160 0x3C8 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SAI1_RXC_SIM_M_HADDR16 0x160 0x3C8 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0x164 0x3CC 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD0_SAI5_RX_DATA0 0x164 0x3CC 0x4D4 0x1 0x1
-#define MX8MQ_IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0 0x164 0x3CC 0x000 0x4 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x164 0x3CC 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD0_CCMSRCGPCMIX_BOOT_CFG0 0x164 0x3CC 0x000 0x6 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD0_SIM_M_HADDR17 0x164 0x3CC 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0x168 0x3D0 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD1_SAI5_RX_DATA1 0x168 0x3D0 0x4D8 0x1 0x1
-#define MX8MQ_IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1 0x168 0x3D0 0x000 0x4 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x168 0x3D0 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD1_CCMSRCGPCMIX_BOOT_CFG1 0x168 0x3D0 0x000 0x6 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD1_SIM_M_HADDR18 0x168 0x3D0 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD2_SAI1_RX_DATA2 0x16C 0x3D4 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD2_SAI5_RX_DATA2 0x16C 0x3D4 0x4DC 0x1 0x1
-#define MX8MQ_IOMUXC_SAI1_RXD2_CORESIGHT_TRACE2 0x16C 0x3D4 0x000 0x4 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x16C 0x3D4 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD2_CCMSRCGPCMIX_BOOT_CFG2 0x16C 0x3D4 0x000 0x6 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD2_SIM_M_HADDR19 0x16C 0x3D4 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD3_SAI1_RX_DATA3 0x170 0x3D8 0x4E0 0x0 0x1
-#define MX8MQ_IOMUXC_SAI1_RXD3_SAI5_RX_DATA3 0x170 0x3D8 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD3_CORESIGHT_TRACE3 0x170 0x3D8 0x000 0x4 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x170 0x3D8 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD3_CCMSRCGPCMIX_BOOT_CFG3 0x170 0x3D8 0x000 0x6 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD3_SIM_M_HADDR20 0x170 0x3D8 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD4_SAI1_RX_DATA4 0x174 0x3DC 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x174 0x3DC 0x51C 0x1 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD4_SAI6_RX_BCLK 0x174 0x3DC 0x510 0x2 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4 0x174 0x3DC 0x000 0x4 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x174 0x3DC 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD4_CCMSRCGPCMIX_BOOT_CFG4 0x174 0x3DC 0x000 0x6 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD4_SIM_M_HADDR21 0x174 0x3DC 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD5_SAI1_RX_DATA5 0x178 0x3E0 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x178 0x3E0 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0x178 0x3E0 0x514 0x2 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD5_SAI1_RX_SYNC 0x178 0x3E0 0x4C4 0x3 0x1
-#define MX8MQ_IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5 0x178 0x3E0 0x000 0x4 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x178 0x3E0 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD5_CCMSRCGPCMIX_BOOT_CFG5 0x178 0x3E0 0x000 0x6 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD5_SIM_M_HADDR22 0x178 0x3E0 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD6_SAI1_RX_DATA6 0x17C 0x3E4 0x520 0x0 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x17C 0x3E4 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0x17C 0x3E4 0x518 0x2 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD6_CORESIGHT_TRACE6 0x17C 0x3E4 0x000 0x4 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x17C 0x3E4 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD6_CCMSRCGPCMIX_BOOT_CFG6 0x17C 0x3E4 0x000 0x6 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD6_SIM_M_HADDR23 0x17C 0x3E4 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD7_SAI1_RX_DATA7 0x180 0x3E8 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD7_SAI6_MCLK 0x180 0x3E8 0x530 0x1 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0x180 0x3E8 0x4CC 0x2 0x4
-#define MX8MQ_IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0x180 0x3E8 0x000 0x3 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD7_CORESIGHT_TRACE7 0x180 0x3E8 0x000 0x4 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x180 0x3E8 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD7_CCMSRCGPCMIX_BOOT_CFG7 0x180 0x3E8 0x000 0x6 0x0
-#define MX8MQ_IOMUXC_SAI1_RXD7_SIM_M_HADDR24 0x180 0x3E8 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0x184 0x3EC 0x4CC 0x0 0x3
-#define MX8MQ_IOMUXC_SAI1_TXFS_SAI5_TX_SYNC 0x184 0x3EC 0x4EC 0x1 0x1
-#define MX8MQ_IOMUXC_SAI1_TXFS_CORESIGHT_EVENTO 0x184 0x3EC 0x000 0x4 0x0
-#define MX8MQ_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x184 0x3EC 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SAI1_TXFS_SIM_M_HADDR25 0x184 0x3EC 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0x188 0x3F0 0x4C8 0x0 0x1
-#define MX8MQ_IOMUXC_SAI1_TXC_SAI5_TX_BCLK 0x188 0x3F0 0x4E8 0x1 0x1
-#define MX8MQ_IOMUXC_SAI1_TXC_CORESIGHT_EVENTI 0x188 0x3F0 0x000 0x4 0x0
-#define MX8MQ_IOMUXC_SAI1_TXC_GPIO4_IO11 0x188 0x3F0 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SAI1_TXC_SIM_M_HADDR26 0x188 0x3F0 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0x18C 0x3F4 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD0_SAI5_TX_DATA0 0x18C 0x3F4 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD0_CORESIGHT_TRACE8 0x18C 0x3F4 0x000 0x4 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x18C 0x3F4 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD0_CCMSRCGPCMIX_BOOT_CFG8 0x18C 0x3F4 0x000 0x6 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD0_SIM_M_HADDR27 0x18C 0x3F4 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0x190 0x3F8 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD1_SAI5_TX_DATA1 0x190 0x3F8 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD1_CORESIGHT_TRACE9 0x190 0x3F8 0x000 0x4 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD1_GPIO4_IO13 0x190 0x3F8 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD1_CCMSRCGPCMIX_BOOT_CFG9 0x190 0x3F8 0x000 0x6 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD1_SIM_M_HADDR28 0x190 0x3F8 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0x194 0x3FC 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD2_SAI5_TX_DATA2 0x194 0x3FC 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10 0x194 0x3FC 0x000 0x4 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x194 0x3FC 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD2_CCMSRCGPCMIX_BOOT_CFG10 0x194 0x3FC 0x000 0x6 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD2_SIM_M_HADDR29 0x194 0x3FC 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0x198 0x400 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD3_SAI5_TX_DATA3 0x198 0x400 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD3_CORESIGHT_TRACE11 0x198 0x400 0x000 0x4 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x198 0x400 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD3_CCMSRCGPCMIX_BOOT_CFG11 0x198 0x400 0x000 0x6 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD3_SIM_M_HADDR30 0x198 0x400 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0x19C 0x404 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0x19C 0x404 0x510 0x1 0x1
-#define MX8MQ_IOMUXC_SAI1_TXD4_SAI6_TX_BCLK 0x19C 0x404 0x51C 0x2 0x1
-#define MX8MQ_IOMUXC_SAI1_TXD4_CORESIGHT_TRACE12 0x19C 0x404 0x000 0x4 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x19C 0x404 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD4_CCMSRCGPCMIX_BOOT_CFG12 0x19C 0x404 0x000 0x6 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD4_SIM_M_HADDR31 0x19C 0x404 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0x1A0 0x408 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x1A0 0x408 0x514 0x1 0x1
-#define MX8MQ_IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0x1A0 0x408 0x000 0x2 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD5_CORESIGHT_TRACE13 0x1A0 0x408 0x000 0x4 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x1A0 0x408 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD5_CCMSRCGPCMIX_BOOT_CFG13 0x1A0 0x408 0x000 0x6 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD5_SIM_M_HBURST0 0x1A0 0x408 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0x1A4 0x40C 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD6_SAI6_RX_SYNC 0x1A4 0x40C 0x518 0x1 0x1
-#define MX8MQ_IOMUXC_SAI1_TXD6_SAI6_TX_SYNC 0x1A4 0x40C 0x520 0x2 0x1
-#define MX8MQ_IOMUXC_SAI1_TXD6_CORESIGHT_TRACE14 0x1A4 0x40C 0x000 0x4 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x1A4 0x40C 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD6_CCMSRCGPCMIX_BOOT_CFG14 0x1A4 0x40C 0x000 0x6 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD6_SIM_M_HBURST1 0x1A4 0x40C 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0x1A8 0x410 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD7_SAI6_MCLK 0x1A8 0x410 0x530 0x1 0x1
-#define MX8MQ_IOMUXC_SAI1_TXD7_CORESIGHT_TRACE15 0x1A8 0x410 0x000 0x4 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x1A8 0x410 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD7_CCMSRCGPCMIX_BOOT_CFG15 0x1A8 0x410 0x000 0x6 0x0
-#define MX8MQ_IOMUXC_SAI1_TXD7_SIM_M_HBURST2 0x1A8 0x410 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_SAI1_MCLK_SAI1_MCLK 0x1AC 0x414 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SAI1_MCLK_SAI5_MCLK 0x1AC 0x414 0x52C 0x1 0x1
-#define MX8MQ_IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0x1AC 0x414 0x4C8 0x2 0x2
-#define MX8MQ_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x1AC 0x414 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SAI1_MCLK_SIM_M_HRESP 0x1AC 0x414 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x1B0 0x418 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x1B0 0x418 0x4EC 0x1 0x2
-#define MX8MQ_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x1B0 0x418 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SAI2_RXFS_SIM_M_HSIZE0 0x1B0 0x418 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x1B4 0x41C 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x1B4 0x41C 0x4E8 0x1 0x2
-#define MX8MQ_IOMUXC_SAI2_RXC_GPIO4_IO22 0x1B4 0x41C 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SAI2_RXC_SIM_M_HSIZE1 0x1B4 0x41C 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x1B8 0x420 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x1B8 0x420 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_SAI2_RXD0_GPIO4_IO23 0x1B8 0x420 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SAI2_RXD0_SIM_M_HSIZE2 0x1B8 0x420 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x1BC 0x424 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x1BC 0x424 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_SAI2_TXFS_GPIO4_IO24 0x1BC 0x424 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SAI2_TXFS_SIM_M_HWRITE 0x1BC 0x424 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x1C0 0x428 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x1C0 0x428 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_SAI2_TXC_GPIO4_IO25 0x1C0 0x428 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SAI2_TXC_SIM_M_HREADYOUT 0x1C0 0x428 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x1C4 0x42C 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x1C4 0x42C 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x1C4 0x42C 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SAI2_TXD0_TPSMP_CLK 0x1C4 0x42C 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0x1C8 0x430 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SAI2_MCLK_SAI5_MCLK 0x1C8 0x430 0x52C 0x1 0x2
-#define MX8MQ_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x1C8 0x430 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SAI2_MCLK_TPSMP_HDATA_DIR 0x1C8 0x430 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x1CC 0x434 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x1CC 0x434 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x1CC 0x434 0x4E4 0x2 0x2
-#define MX8MQ_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x1CC 0x434 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SAI3_RXFS_TPSMP_HTRANS0 0x1CC 0x434 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x1D0 0x438 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SAI3_RXC_GPT1_CAPTURE2 0x1D0 0x438 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x1D0 0x438 0x4D0 0x2 0x2
-#define MX8MQ_IOMUXC_SAI3_RXC_GPIO4_IO29 0x1D0 0x438 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SAI3_RXC_TPSMP_HTRANS1 0x1D0 0x438 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x1D4 0x43C 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x1D4 0x43C 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x1D4 0x43C 0x4D4 0x2 0x2
-#define MX8MQ_IOMUXC_SAI3_RXD_GPIO4_IO30 0x1D4 0x43C 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SAI3_RXD_TPSMP_HDATA0 0x1D4 0x43C 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x1D8 0x440 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SAI3_TXFS_GPT1_CLK 0x1D8 0x440 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x1D8 0x440 0x4D8 0x2 0x2
-#define MX8MQ_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x1D8 0x440 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SAI3_TXFS_TPSMP_HDATA1 0x1D8 0x440 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x1DC 0x444 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x1DC 0x444 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x1DC 0x444 0x4DC 0x2 0x2
-#define MX8MQ_IOMUXC_SAI3_TXC_GPIO5_IO0 0x1DC 0x444 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SAI3_TXC_TPSMP_HDATA2 0x1DC 0x444 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x1E0 0x448 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x1E0 0x448 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x1E0 0x448 0x4E0 0x2 0x2
-#define MX8MQ_IOMUXC_SAI3_TXD_GPIO5_IO1 0x1E0 0x448 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SAI3_TXD_TPSMP_HDATA3 0x1E0 0x448 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_SAI3_MCLK_SAI3_MCLK 0x1E4 0x44C 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SAI3_MCLK_PWM4_OUT 0x1E4 0x44C 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_SAI3_MCLK_SAI5_MCLK 0x1E4 0x44C 0x52C 0x2 0x3
-#define MX8MQ_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x1E4 0x44C 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SAI3_MCLK_TPSMP_HDATA4 0x1E4 0x44C 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_SPDIF_TX_SPDIF1_OUT 0x1E8 0x450 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SPDIF_TX_PWM3_OUT 0x1E8 0x450 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_SPDIF_TX_GPIO5_IO3 0x1E8 0x450 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SPDIF_TX_TPSMP_HDATA5 0x1E8 0x450 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_SPDIF_RX_SPDIF1_IN 0x1EC 0x454 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SPDIF_RX_PWM2_OUT 0x1EC 0x454 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_SPDIF_RX_GPIO5_IO4 0x1EC 0x454 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SPDIF_RX_TPSMP_HDATA6 0x1EC 0x454 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x1F0 0x458 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x1F0 0x458 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x1F0 0x458 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_SPDIF_EXT_CLK_TPSMP_HDATA7 0x1F0 0x458 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x1F4 0x45C 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x1F4 0x45C 0x504 0x1 0x0
-#define MX8MQ_IOMUXC_ECSPI1_SCLK_UART3_DTE_TX 0x1F4 0x45C 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_ECSPI1_SCLK_GPIO5_IO6 0x1F4 0x45C 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_ECSPI1_SCLK_TPSMP_HDATA8 0x1F4 0x45C 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x1F8 0x460 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x1F8 0x460 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_ECSPI1_MOSI_UART3_DTE_RX 0x1F8 0x460 0x504 0x1 0x1
-#define MX8MQ_IOMUXC_ECSPI1_MOSI_GPIO5_IO7 0x1F8 0x460 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_ECSPI1_MOSI_TPSMP_HDATA9 0x1F8 0x460 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x1FC 0x464 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x1FC 0x464 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_ECSPI1_MISO_UART3_DTE_RTS_B 0x1FC 0x464 0x500 0x1 0x0
-#define MX8MQ_IOMUXC_ECSPI1_MISO_GPIO5_IO8 0x1FC 0x464 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_ECSPI1_MISO_TPSMP_HDATA10 0x1FC 0x464 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x200 0x468 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x200 0x468 0x500 0x1 0x1
-#define MX8MQ_IOMUXC_ECSPI1_SS0_UART3_DTE_CTS_B 0x200 0x468 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x200 0x468 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_ECSPI1_SS0_TPSMP_HDATA11 0x200 0x468 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x204 0x46C 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX 0x204 0x46C 0x50C 0x1 0x0
-#define MX8MQ_IOMUXC_ECSPI2_SCLK_UART4_DTE_TX 0x204 0x46C 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x204 0x46C 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_ECSPI2_SCLK_TPSMP_HDATA12 0x204 0x46C 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x208 0x470 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_ECSPI2_MOSI_UART4_DCE_TX 0x208 0x470 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_ECSPI2_MOSI_UART4_DTE_RX 0x208 0x470 0x50C 0x1 0x1
-#define MX8MQ_IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x208 0x470 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_ECSPI2_MOSI_TPSMP_HDATA13 0x208 0x470 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x20C 0x474 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS_B 0x20C 0x474 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_ECSPI2_MISO_UART4_DTE_RTS_B 0x20C 0x474 0x508 0x1 0x0
-#define MX8MQ_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x20C 0x474 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_ECSPI2_MISO_TPSMP_HDATA14 0x20C 0x474 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x210 0x478 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_B 0x210 0x478 0x508 0x1 0x1
-#define MX8MQ_IOMUXC_ECSPI2_SS0_UART4_DTE_CTS_B 0x210 0x478 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x210 0x478 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_ECSPI2_SS0_TPSMP_HDATA15 0x210 0x478 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x214 0x47C 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_I2C1_SCL_ENET1_MDC 0x214 0x47C 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_I2C1_SCL_GPIO5_IO14 0x214 0x47C 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_I2C1_SCL_TPSMP_HDATA16 0x214 0x47C 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x218 0x480 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_I2C1_SDA_ENET1_MDIO 0x218 0x480 0x4C0 0x1 0x2
-#define MX8MQ_IOMUXC_I2C1_SDA_GPIO5_IO15 0x218 0x480 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_I2C1_SDA_TPSMP_HDATA17 0x218 0x480 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x21C 0x484 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x21C 0x484 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_I2C2_SCL_GPIO5_IO16 0x21C 0x484 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_I2C2_SCL_TPSMP_HDATA18 0x21C 0x484 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x220 0x488 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x220 0x488 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_I2C2_SDA_GPIO5_IO17 0x220 0x488 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_I2C2_SDA_TPSMP_HDATA19 0x220 0x488 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x224 0x48C 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_I2C3_SCL_PWM4_OUT 0x224 0x48C 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_I2C3_SCL_GPT2_CLK 0x224 0x48C 0x000 0x2 0x0
-#define MX8MQ_IOMUXC_I2C3_SCL_GPIO5_IO18 0x224 0x48C 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_I2C3_SCL_TPSMP_HDATA20 0x224 0x48C 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x228 0x490 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_I2C3_SDA_PWM3_OUT 0x228 0x490 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_I2C3_SDA_GPT3_CLK 0x228 0x490 0x000 0x2 0x0
-#define MX8MQ_IOMUXC_I2C3_SDA_GPIO5_IO19 0x228 0x490 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_I2C3_SDA_TPSMP_HDATA21 0x228 0x490 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL 0x22C 0x494 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_I2C4_SCL_PWM2_OUT 0x22C 0x494 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x22C 0x494 0x524 0x2 0x0
-#define MX8MQ_IOMUXC_I2C4_SCL_GPIO5_IO20 0x22C 0x494 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_I2C4_SCL_TPSMP_HDATA22 0x22C 0x494 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA 0x230 0x498 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_I2C4_SDA_PWM1_OUT 0x230 0x498 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B 0x230 0x498 0x528 0x2 0x0
-#define MX8MQ_IOMUXC_I2C4_SDA_GPIO5_IO21 0x230 0x498 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_I2C4_SDA_TPSMP_HDATA23 0x230 0x498 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x234 0x49C 0x4F4 0x0 0x0
-#define MX8MQ_IOMUXC_UART1_RXD_UART1_DTE_TX 0x234 0x49C 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x234 0x49C 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_UART1_RXD_GPIO5_IO22 0x234 0x49C 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_UART1_RXD_TPSMP_HDATA24 0x234 0x49C 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x238 0x4A0 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_UART1_TXD_UART1_DTE_RX 0x238 0x4A0 0x4F4 0x0 0x0
-#define MX8MQ_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x238 0x4A0 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_UART1_TXD_GPIO5_IO23 0x238 0x4A0 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_UART1_TXD_TPSMP_HDATA25 0x238 0x4A0 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x23C 0x4A4 0x4FC 0x0 0x0
-#define MX8MQ_IOMUXC_UART2_RXD_UART2_DTE_TX 0x23C 0x4A4 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_UART2_RXD_ECSPI3_MISO 0x23C 0x4A4 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_UART2_RXD_GPIO5_IO24 0x23C 0x4A4 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_UART2_RXD_TPSMP_HDATA26 0x23C 0x4A4 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x240 0x4A8 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_UART2_TXD_UART2_DTE_RX 0x240 0x4A8 0x4FC 0x0 0x1
-#define MX8MQ_IOMUXC_UART2_TXD_ECSPI3_SS0 0x240 0x4A8 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_UART2_TXD_GPIO5_IO25 0x240 0x4A8 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_UART2_TXD_TPSMP_HDATA27 0x240 0x4A8 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x244 0x4AC 0x504 0x0 0x2
-#define MX8MQ_IOMUXC_UART3_RXD_UART3_DTE_TX 0x244 0x4AC 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x244 0x4AC 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_UART3_RXD_UART1_DTE_RTS_B 0x244 0x4AC 0x4F0 0x1 0x0
-#define MX8MQ_IOMUXC_UART3_RXD_GPIO5_IO26 0x244 0x4AC 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_UART3_RXD_TPSMP_HDATA28 0x244 0x4AC 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x248 0x4B0 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_UART3_TXD_UART3_DTE_RX 0x248 0x4B0 0x504 0x0 0x3
-#define MX8MQ_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x248 0x4B0 0x4F0 0x1 0x1
-#define MX8MQ_IOMUXC_UART3_TXD_UART1_DTE_CTS_B 0x248 0x4B0 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_UART3_TXD_GPIO5_IO27 0x248 0x4B0 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_UART3_TXD_TPSMP_HDATA29 0x248 0x4B0 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_UART4_RXD_UART4_DCE_RX 0x24C 0x4B4 0x50C 0x0 0x2
-#define MX8MQ_IOMUXC_UART4_RXD_UART4_DTE_TX 0x24C 0x4B4 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_UART4_RXD_UART2_DCE_CTS_B 0x24C 0x4B4 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_UART4_RXD_UART2_DTE_RTS_B 0x24C 0x4B4 0x4F8 0x1 0x0
-#define MX8MQ_IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x24C 0x4B4 0x524 0x2 0x1
-#define MX8MQ_IOMUXC_UART4_RXD_GPIO5_IO28 0x24C 0x4B4 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_UART4_RXD_TPSMP_HDATA30 0x24C 0x4B4 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_UART4_TXD_UART4_DCE_TX 0x250 0x4B8 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_UART4_TXD_UART4_DTE_RX 0x250 0x4B8 0x50C 0x0 0x3
-#define MX8MQ_IOMUXC_UART4_TXD_UART2_DCE_RTS_B 0x250 0x4B8 0x4F8 0x1 0x1
-#define MX8MQ_IOMUXC_UART4_TXD_UART2_DTE_CTS_B 0x250 0x4B8 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_UART4_TXD_PCIE2_CLKREQ_B 0x250 0x4B8 0x528 0x2 0x1
-#define MX8MQ_IOMUXC_UART4_TXD_GPIO5_IO29 0x250 0x4B8 0x000 0x5 0x0
-#define MX8MQ_IOMUXC_UART4_TXD_TPSMP_HDATA31 0x250 0x4B8 0x000 0x7 0x0
-#define MX8MQ_IOMUXC_TEST_MODE 0x000 0x254 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_BOOT_MODE0 0x000 0x258 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_BOOT_MODE1 0x000 0x25C 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_JTAG_MOD 0x000 0x260 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_JTAG_TRST_B 0x000 0x264 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_JTAG_TDI 0x000 0x268 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_JTAG_TMS 0x000 0x26C 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_JTAG_TCK 0x000 0x270 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_JTAG_TDO 0x000 0x274 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_RTC 0x000 0x278 0x000 0x0 0x0
-
-#endif /* __DTS_IMX8MQ_PINFUNC_H */
diff --git a/include/dt-bindings/pinctrl/r7s72100-pinctrl.h b/include/dt-bindings/pinctrl/r7s72100-pinctrl.h
deleted file mode 100644
index 31ee376..0000000
--- a/include/dt-bindings/pinctrl/r7s72100-pinctrl.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Defines macros and constants for Renesas RZ/A1 pin controller pin
- * muxing functions.
- */
-#ifndef __DT_BINDINGS_PINCTRL_RENESAS_RZA1_H
-#define __DT_BINDINGS_PINCTRL_RENESAS_RZA1_H
-
-#define RZA1_PINS_PER_PORT 16
-
-/*
- * Create the pin index from its bank and position numbers and store in
- * the upper 16 bits the alternate function identifier
- */
-#define RZA1_PINMUX(b, p, f) \
- ((b) * RZA1_PINS_PER_PORT + (p) | ((f) << 16))
-
-#endif /* __DT_BINDINGS_PINCTRL_RENESAS_RZA1_H */
diff --git a/include/dt-bindings/pinctrl/rockchip.h b/include/dt-bindings/pinctrl/rockchip.h
deleted file mode 100644
index 1c28d6c..0000000
--- a/include/dt-bindings/pinctrl/rockchip.h
+++ /dev/null
@@ -1,60 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Header providing constants for Rockchip pinctrl bindings.
- *
- * Copyright (c) 2013 MundoReader S.L.
- * Author: Heiko Stuebner <heiko@sntech.de>
- */
-
-#ifndef __DT_BINDINGS_ROCKCHIP_PINCTRL_H__
-#define __DT_BINDINGS_ROCKCHIP_PINCTRL_H__
-
-#define RK_GPIO0 0
-#define RK_GPIO1 1
-#define RK_GPIO2 2
-#define RK_GPIO3 3
-#define RK_GPIO4 4
-#define RK_GPIO6 6
-
-#define RK_PA0 0
-#define RK_PA1 1
-#define RK_PA2 2
-#define RK_PA3 3
-#define RK_PA4 4
-#define RK_PA5 5
-#define RK_PA6 6
-#define RK_PA7 7
-#define RK_PB0 8
-#define RK_PB1 9
-#define RK_PB2 10
-#define RK_PB3 11
-#define RK_PB4 12
-#define RK_PB5 13
-#define RK_PB6 14
-#define RK_PB7 15
-#define RK_PC0 16
-#define RK_PC1 17
-#define RK_PC2 18
-#define RK_PC3 19
-#define RK_PC4 20
-#define RK_PC5 21
-#define RK_PC6 22
-#define RK_PC7 23
-#define RK_PD0 24
-#define RK_PD1 25
-#define RK_PD2 26
-#define RK_PD3 27
-#define RK_PD4 28
-#define RK_PD5 29
-#define RK_PD6 30
-#define RK_PD7 31
-
-#define RK_FUNC_GPIO 0
-#define RK_FUNC_1 1
-#define RK_FUNC_2 2
-#define RK_FUNC_3 3
-#define RK_FUNC_4 4
-#define RK_FUNC_5 5
-#define RK_FUNC_6 6
-
-#endif
diff --git a/include/dt-bindings/pinctrl/stm32-pinfunc.h b/include/dt-bindings/pinctrl/stm32-pinfunc.h
deleted file mode 100644
index e6fb8ad..0000000
--- a/include/dt-bindings/pinctrl/stm32-pinfunc.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
-/*
- * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
- * Author: Torgue Alexandre <alexandre.torgue@st.com> for STMicroelectronics.
- */
-
-#ifndef _DT_BINDINGS_STM32_PINFUNC_H
-#define _DT_BINDINGS_STM32_PINFUNC_H
-
-/* define PIN modes */
-#define GPIO 0x0
-#define AF0 0x1
-#define AF1 0x2
-#define AF2 0x3
-#define AF3 0x4
-#define AF4 0x5
-#define AF5 0x6
-#define AF6 0x7
-#define AF7 0x8
-#define AF8 0x9
-#define AF9 0xa
-#define AF10 0xb
-#define AF11 0xc
-#define AF12 0xd
-#define AF13 0xe
-#define AF14 0xf
-#define AF15 0x10
-#define ANALOG 0x11
-
-/* define Pins number*/
-#define PIN_NO(port, line) (((port) - 'A') * 0x10 + (line))
-
-#define STM32_PINMUX(port, line, mode) (((PIN_NO(port, line)) << 8) | (mode))
-
-/* package information */
-#define STM32MP_PKG_AA 0x1
-#define STM32MP_PKG_AB 0x2
-#define STM32MP_PKG_AC 0x4
-#define STM32MP_PKG_AD 0x8
-
-#endif /* _DT_BINDINGS_STM32_PINFUNC_H */
-
diff --git a/include/dt-bindings/pinctrl/sun4i-a10.h b/include/dt-bindings/pinctrl/sun4i-a10.h
deleted file mode 100644
index f7553c1..0000000
--- a/include/dt-bindings/pinctrl/sun4i-a10.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
- * Copyright 2014 Maxime Ripard
- *
- * Maxime Ripard <maxime.ripard@free-electrons.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public
- * License along with this file; if not, write to the Free
- * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef __DT_BINDINGS_PINCTRL_SUN4I_A10_H_
-#define __DT_BINDINGS_PINCTRL_SUN4I_A10_H_
-
-#define SUN4I_PINCTRL_10_MA 0
-#define SUN4I_PINCTRL_20_MA 1
-#define SUN4I_PINCTRL_30_MA 2
-#define SUN4I_PINCTRL_40_MA 3
-
-#define SUN4I_PINCTRL_NO_PULL 0
-#define SUN4I_PINCTRL_PULL_UP 1
-#define SUN4I_PINCTRL_PULL_DOWN 2
-
-#endif /* __DT_BINDINGS_PINCTRL_SUN4I_A10_H_ */
diff --git a/include/dt-bindings/pmic/sandbox_pmic.h b/include/dt-bindings/pmic/sandbox_pmic.h
deleted file mode 100644
index 749c0d1..0000000
--- a/include/dt-bindings/pmic/sandbox_pmic.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2015 Samsung Electronics
- * Przemyslaw Marczak <p.marczak@samsung.com>
- */
-
-#ifndef _DT_BINDINGS_SANDBOX_PMIC_H_
-#define _DT_BINDINGS_SANDBOX_PMIC_H_
-
-/*
- * Sandbox PMIC - prepare reset values
- * To provide the default (reset) values as in the real hardware,
- * the registers are set in i2c pmic emul driver's probe() method.
- * The default values are defined as below.
- */
-
-/* Buck operation mode IDs */
-#define BUCK_OM_OFF 0
-#define BUCK_OM_ON 1
-#define BUCK_OM_PWM 2
-#define BUCK_OM_COUNT 3
-
-/* Ldo operation mode IDs */
-#define LDO_OM_OFF 0
-#define LDO_OM_ON 1
-#define LDO_OM_SLEEP 2
-#define LDO_OM_STANDBY 3
-#define LDO_OM_COUNT 4
-
-/* [Value uV/uA]/[Mode ID] to register */
-#define VAL2REG(min, step, val) (((val) - (min)) / (step))
-#define VAL2OMREG(x) (x)
-
-#endif
diff --git a/include/dt-bindings/power-domain/bcm6318-power-domain.h b/include/dt-bindings/power-domain/bcm6318-power-domain.h
deleted file mode 100644
index b213cae..0000000
--- a/include/dt-bindings/power-domain/bcm6318-power-domain.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2018 Álvaro Fernández Rojas <noltari@gmail.com>
- */
-
-#ifndef __DT_BINDINGS_POWER_DOMAIN_BCM6318_H
-#define __DT_BINDINGS_POWER_DOMAIN_BCM6318_H
-
-#define BCM6318_PWR_PCIE 0
-#define BCM6318_PWR_USB 1
-
-#endif /* __DT_BINDINGS_POWER_DOMAIN_BCM6318_H */
diff --git a/include/dt-bindings/power-domain/bcm63268-power-domain.h b/include/dt-bindings/power-domain/bcm63268-power-domain.h
deleted file mode 100644
index 7208506..0000000
--- a/include/dt-bindings/power-domain/bcm63268-power-domain.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
- */
-
-#ifndef __DT_BINDINGS_POWER_DOMAIN_BCM63268_H
-#define __DT_BINDINGS_POWER_DOMAIN_BCM63268_H
-
-#define BCM63268_PWR_SAR 0
-#define BCM63268_PWR_IPSEC 1
-#define BCM63268_PWR_MIPS 2
-#define BCM63268_PWR_DECT 3
-#define BCM63268_PWR_USBH 4
-#define BCM63268_PWR_USBD 5
-#define BCM63268_PWR_ROBOSW 6
-#define BCM63268_PWR_PCM 7
-#define BCM63268_PWR_PERIPH 8
-#define BCM63268_PWR_VDSL_PHY 9
-#define BCM63268_PWR_VDSL_MIPS 10
-#define BCM63268_PWR_FAP 11
-#define BCM63268_PWR_PCIE 12
-#define BCM63268_PWR_WLAN_PADS 13
-
-#endif /* __DT_BINDINGS_POWER_DOMAIN_BCM63268_H */
diff --git a/include/dt-bindings/power-domain/bcm6328-power-domain.h b/include/dt-bindings/power-domain/bcm6328-power-domain.h
deleted file mode 100644
index 6b4b199..0000000
--- a/include/dt-bindings/power-domain/bcm6328-power-domain.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
- */
-
-#ifndef __DT_BINDINGS_POWER_DOMAIN_BCM6328_H
-#define __DT_BINDINGS_POWER_DOMAIN_BCM6328_H
-
-#define BCM6328_PWR_ADSL2_MIPS 0
-#define BCM6328_PWR_ADSL2_PHY 1
-#define BCM6328_PWR_ADSL2_AFE 2
-#define BCM6328_PWR_SAR 3
-#define BCM6328_PWR_PCM 4
-#define BCM6328_PWR_USBD 5
-#define BCM6328_PWR_USBH 6
-#define BCM6328_PWR_PCIE 7
-#define BCM6328_PWR_ROBOSW 8
-#define BCM6328_PWR_EPHY 9
-
-#endif /* __DT_BINDINGS_POWER_DOMAIN_BCM6328_H */
diff --git a/include/dt-bindings/power-domain/bcm6362-power-domain.h b/include/dt-bindings/power-domain/bcm6362-power-domain.h
deleted file mode 100644
index 1a708a9..0000000
--- a/include/dt-bindings/power-domain/bcm6362-power-domain.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2018 Álvaro Fernández Rojas <noltari@gmail.com>
- */
-
-#ifndef __DT_BINDINGS_POWER_DOMAIN_BCM6362_H
-#define __DT_BINDINGS_POWER_DOMAIN_BCM6362_H
-
-#define BCM6362_PWR_SAR 0
-#define BCM6362_PWR_IPSEC 1
-#define BCM6362_PWR_MIPS 2
-#define BCM6362_PWR_DECT 3
-#define BCM6362_PWR_USBH 4
-#define BCM6362_PWR_USBD 5
-#define BCM6362_PWR_ROBOSW 6
-#define BCM6362_PWR_PCM 7
-#define BCM6362_PWR_PERIPH 8
-#define BCM6362_PWR_ADSL_PHY 9
-#define BCM6362_PWR_GMII_PADS 10
-#define BCM6362_PWR_FAP 11
-#define BCM6362_PWR_PCIE 12
-#define BCM6362_PWR_WLAN_PADS 13
-
-#endif /* __DT_BINDINGS_POWER_DOMAIN_BCM6362_H */
diff --git a/include/dt-bindings/power-domain/rk3288.h b/include/dt-bindings/power-domain/rk3288.h
deleted file mode 100644
index ca68c11..0000000
--- a/include/dt-bindings/power-domain/rk3288.h
+++ /dev/null
@@ -1,11 +0,0 @@
-#ifndef __DT_BINDINGS_POWER_DOMAIN_RK3288_H__
-#define __DT_BINDINGS_POWER_DOMAIN_RK3288_H__
-
-/* RK3288 power domain index */
-#define RK3288_PD_GPU 0
-#define RK3288_PD_VIO 1
-#define RK3288_PD_VIDEO 2
-#define RK3288_PD_HEVC 3
-#define RK3288_PD_PERI 4
-
-#endif
diff --git a/include/dt-bindings/power/imx7-power.h b/include/dt-bindings/power/imx7-power.h
deleted file mode 100644
index 3a181e4..0000000
--- a/include/dt-bindings/power/imx7-power.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/*
- * Copyright (C) 2017 Impinj
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __DT_BINDINGS_IMX7_POWER_H__
-#define __DT_BINDINGS_IMX7_POWER_H__
-
-#define IMX7_POWER_DOMAIN_MIPI_PHY 0
-#define IMX7_POWER_DOMAIN_PCIE_PHY 1
-#define IMX7_POWER_DOMAIN_USB_HSIC_PHY 2
-
-#endif
diff --git a/include/dt-bindings/power/imx8mq-power.h b/include/dt-bindings/power/imx8mq-power.h
deleted file mode 100755
index 8a513bd..0000000
--- a/include/dt-bindings/power/imx8mq-power.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
-/*
- * Copyright (C) 2018 Pengutronix, Lucas Stach <kernel@pengutronix.de>
- */
-
-#ifndef __DT_BINDINGS_IMX8MQ_POWER_H__
-#define __DT_BINDINGS_IMX8MQ_POWER_H__
-
-#define IMX8M_POWER_DOMAIN_MIPI 0
-#define IMX8M_POWER_DOMAIN_PCIE1 1
-#define IMX8M_POWER_DOMAIN_USB_OTG1 2
-#define IMX8M_POWER_DOMAIN_USB_OTG2 3
-#define IMX8M_POWER_DOMAIN_DDR1 4
-#define IMX8M_POWER_DOMAIN_GPU 5
-#define IMX8M_POWER_DOMAIN_VPU 6
-#define IMX8M_POWER_DOMAIN_DISP 7
-#define IMX8M_POWER_DOMAIN_MIPI_CSI1 8
-#define IMX8M_POWER_DOMAIN_MIPI_CSI2 9
-#define IMX8M_POWER_DOMAIN_PCIE2 10
-
-#endif
diff --git a/include/dt-bindings/power/meson-g12a-power.h b/include/dt-bindings/power/meson-g12a-power.h
deleted file mode 100644
index bb5e67a..0000000
--- a/include/dt-bindings/power/meson-g12a-power.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
-/*
- * Copyright (c) 2019 BayLibre, SAS
- * Author: Neil Armstrong <narmstrong@baylibre.com>
- */
-
-#ifndef _DT_BINDINGS_MESON_G12A_POWER_H
-#define _DT_BINDINGS_MESON_G12A_POWER_H
-
-#define PWRC_G12A_VPU_ID 0
-#define PWRC_G12A_ETH_ID 1
-
-#endif
diff --git a/include/dt-bindings/power/meson-sm1-power.h b/include/dt-bindings/power/meson-sm1-power.h
deleted file mode 100644
index a020ab0..0000000
--- a/include/dt-bindings/power/meson-sm1-power.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
-/*
- * Copyright (c) 2019 BayLibre, SAS
- * Author: Neil Armstrong <narmstrong@baylibre.com>
- */
-
-#ifndef _DT_BINDINGS_MESON_SM1_POWER_H
-#define _DT_BINDINGS_MESON_SM1_POWER_H
-
-#define PWRC_SM1_VPU_ID 0
-#define PWRC_SM1_NNA_ID 1
-#define PWRC_SM1_USB_ID 2
-#define PWRC_SM1_PCIE_ID 3
-#define PWRC_SM1_GE2D_ID 4
-#define PWRC_SM1_AUDIO_ID 5
-#define PWRC_SM1_ETH_ID 6
-
-#endif
diff --git a/include/dt-bindings/power/mt7623-power.h b/include/dt-bindings/power/mt7623-power.h
deleted file mode 100644
index 0e73bb4..0000000
--- a/include/dt-bindings/power/mt7623-power.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2018 MediaTek Inc.
- */
-
-#ifndef _DT_BINDINGS_MT7623_POWER_H
-#define _DT_BINDINGS_MT7623_POWER_H
-
-#define MT7623_POWER_DOMAIN_CONN 0
-#define MT7623_POWER_DOMAIN_DISP 1
-#define MT7623_POWER_DOMAIN_MFG 2
-#define MT7623_POWER_DOMAIN_VDEC 3
-#define MT7623_POWER_DOMAIN_ISP 4
-#define MT7623_POWER_DOMAIN_BDP 5
-#define MT7623_POWER_DOMAIN_ETH 6
-#define MT7623_POWER_DOMAIN_HIF 7
-#define MT7623_POWER_DOMAIN_IFR_MSC 8
-
-#endif /* _DT_BINDINGS_MT7623_POWER_H */
diff --git a/include/dt-bindings/power/mt7629-power.h b/include/dt-bindings/power/mt7629-power.h
deleted file mode 100644
index c7e6130..0000000
--- a/include/dt-bindings/power/mt7629-power.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2018 MediaTek Inc.
- */
-
-#ifndef _DT_BINDINGS_MT7629_POWER_H
-#define _DT_BINDINGS_MT7629_POWER_H
-
-#define MT7629_POWER_DOMAIN_ETHSYS 0
-#define MT7629_POWER_DOMAIN_HIF0 1
-#define MT7629_POWER_DOMAIN_HIF1 2
-
-#endif /* _DT_BINDINGS_MT7629_POWER_H */
diff --git a/include/dt-bindings/power/r8a7790-sysc.h b/include/dt-bindings/power/r8a7790-sysc.h
deleted file mode 100644
index 6af4e99..0000000
--- a/include/dt-bindings/power/r8a7790-sysc.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * Copyright (C) 2016 Glider bvba
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- */
-#ifndef __DT_BINDINGS_POWER_R8A7790_SYSC_H__
-#define __DT_BINDINGS_POWER_R8A7790_SYSC_H__
-
-/*
- * These power domain indices match the numbers of the interrupt bits
- * representing the power areas in the various Interrupt Registers
- * (e.g. SYSCISR, Interrupt Status Register)
- */
-
-#define R8A7790_PD_CA15_CPU0 0
-#define R8A7790_PD_CA15_CPU1 1
-#define R8A7790_PD_CA15_CPU2 2
-#define R8A7790_PD_CA15_CPU3 3
-#define R8A7790_PD_CA7_CPU0 5
-#define R8A7790_PD_CA7_CPU1 6
-#define R8A7790_PD_CA7_CPU2 7
-#define R8A7790_PD_CA7_CPU3 8
-#define R8A7790_PD_CA15_SCU 12
-#define R8A7790_PD_SH_4A 16
-#define R8A7790_PD_RGX 20
-#define R8A7790_PD_CA7_SCU 21
-#define R8A7790_PD_IMP 24
-
-/* Always-on power area */
-#define R8A7790_PD_ALWAYS_ON 32
-
-#endif /* __DT_BINDINGS_POWER_R8A7790_SYSC_H__ */
diff --git a/include/dt-bindings/power/r8a7791-sysc.h b/include/dt-bindings/power/r8a7791-sysc.h
deleted file mode 100644
index 1403baa..0000000
--- a/include/dt-bindings/power/r8a7791-sysc.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * Copyright (C) 2016 Glider bvba
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- */
-#ifndef __DT_BINDINGS_POWER_R8A7791_SYSC_H__
-#define __DT_BINDINGS_POWER_R8A7791_SYSC_H__
-
-/*
- * These power domain indices match the numbers of the interrupt bits
- * representing the power areas in the various Interrupt Registers
- * (e.g. SYSCISR, Interrupt Status Register)
- */
-
-#define R8A7791_PD_CA15_CPU0 0
-#define R8A7791_PD_CA15_CPU1 1
-#define R8A7791_PD_CA15_SCU 12
-#define R8A7791_PD_SH_4A 16
-#define R8A7791_PD_SGX 20
-
-/* Always-on power area */
-#define R8A7791_PD_ALWAYS_ON 32
-
-#endif /* __DT_BINDINGS_POWER_R8A7791_SYSC_H__ */
diff --git a/include/dt-bindings/power/r8a7792-sysc.h b/include/dt-bindings/power/r8a7792-sysc.h
deleted file mode 100644
index 74f4a78..0000000
--- a/include/dt-bindings/power/r8a7792-sysc.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * Copyright (C) 2016 Cogent Embedded Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- */
-#ifndef __DT_BINDINGS_POWER_R8A7792_SYSC_H__
-#define __DT_BINDINGS_POWER_R8A7792_SYSC_H__
-
-/*
- * These power domain indices match the numbers of the interrupt bits
- * representing the power areas in the various Interrupt Registers
- * (e.g. SYSCISR, Interrupt Status Register)
- */
-
-#define R8A7792_PD_CA15_CPU0 0
-#define R8A7792_PD_CA15_CPU1 1
-#define R8A7792_PD_CA15_SCU 12
-#define R8A7792_PD_SGX 20
-#define R8A7792_PD_IMP 24
-
-/* Always-on power area */
-#define R8A7792_PD_ALWAYS_ON 32
-
-#endif /* __DT_BINDINGS_POWER_R8A7792_SYSC_H__ */
diff --git a/include/dt-bindings/power/r8a7793-sysc.h b/include/dt-bindings/power/r8a7793-sysc.h
deleted file mode 100644
index b5693df..0000000
--- a/include/dt-bindings/power/r8a7793-sysc.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * Copyright (C) 2016 Glider bvba
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- */
-#ifndef __DT_BINDINGS_POWER_R8A7793_SYSC_H__
-#define __DT_BINDINGS_POWER_R8A7793_SYSC_H__
-
-/*
- * These power domain indices match the numbers of the interrupt bits
- * representing the power areas in the various Interrupt Registers
- * (e.g. SYSCISR, Interrupt Status Register)
- *
- * Note that R-Car M2-N is identical to R-Car M2-W w.r.t. power domains.
- */
-
-#define R8A7793_PD_CA15_CPU0 0
-#define R8A7793_PD_CA15_CPU1 1
-#define R8A7793_PD_CA15_SCU 12
-#define R8A7793_PD_SH_4A 16
-#define R8A7793_PD_SGX 20
-
-/* Always-on power area */
-#define R8A7793_PD_ALWAYS_ON 32
-
-#endif /* __DT_BINDINGS_POWER_R8A7793_SYSC_H__ */
diff --git a/include/dt-bindings/power/r8a7794-sysc.h b/include/dt-bindings/power/r8a7794-sysc.h
deleted file mode 100644
index 862241c..0000000
--- a/include/dt-bindings/power/r8a7794-sysc.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * Copyright (C) 2016 Glider bvba
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- */
-#ifndef __DT_BINDINGS_POWER_R8A7794_SYSC_H__
-#define __DT_BINDINGS_POWER_R8A7794_SYSC_H__
-
-/*
- * These power domain indices match the numbers of the interrupt bits
- * representing the power areas in the various Interrupt Registers
- * (e.g. SYSCISR, Interrupt Status Register)
- */
-
-#define R8A7794_PD_CA7_CPU0 5
-#define R8A7794_PD_CA7_CPU1 6
-#define R8A7794_PD_SH_4A 16
-#define R8A7794_PD_SGX 20
-#define R8A7794_PD_CA7_SCU 21
-
-/* Always-on power area */
-#define R8A7794_PD_ALWAYS_ON 32
-
-#endif /* __DT_BINDINGS_POWER_R8A7794_SYSC_H__ */
diff --git a/include/dt-bindings/power/r8a7795-sysc.h b/include/dt-bindings/power/r8a7795-sysc.h
deleted file mode 100644
index ad679ee..0000000
--- a/include/dt-bindings/power/r8a7795-sysc.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * Copyright (C) 2016 Glider bvba
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- */
-#ifndef __DT_BINDINGS_POWER_R8A7795_SYSC_H__
-#define __DT_BINDINGS_POWER_R8A7795_SYSC_H__
-
-/*
- * These power domain indices match the numbers of the interrupt bits
- * representing the power areas in the various Interrupt Registers
- * (e.g. SYSCISR, Interrupt Status Register)
- */
-
-#define R8A7795_PD_CA57_CPU0 0
-#define R8A7795_PD_CA57_CPU1 1
-#define R8A7795_PD_CA57_CPU2 2
-#define R8A7795_PD_CA57_CPU3 3
-#define R8A7795_PD_CA53_CPU0 5
-#define R8A7795_PD_CA53_CPU1 6
-#define R8A7795_PD_CA53_CPU2 7
-#define R8A7795_PD_CA53_CPU3 8
-#define R8A7795_PD_A3VP 9
-#define R8A7795_PD_CA57_SCU 12
-#define R8A7795_PD_CR7 13
-#define R8A7795_PD_A3VC 14
-#define R8A7795_PD_3DG_A 17
-#define R8A7795_PD_3DG_B 18
-#define R8A7795_PD_3DG_C 19
-#define R8A7795_PD_3DG_D 20
-#define R8A7795_PD_CA53_SCU 21
-#define R8A7795_PD_3DG_E 22
-#define R8A7795_PD_A3IR 24
-#define R8A7795_PD_A2VC0 25 /* ES1.x only */
-#define R8A7795_PD_A2VC1 26
-
-/* Always-on power area */
-#define R8A7795_PD_ALWAYS_ON 32
-
-#endif /* __DT_BINDINGS_POWER_R8A7795_SYSC_H__ */
diff --git a/include/dt-bindings/power/r8a7796-sysc.h b/include/dt-bindings/power/r8a7796-sysc.h
deleted file mode 100644
index 5b4daab..0000000
--- a/include/dt-bindings/power/r8a7796-sysc.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * Copyright (C) 2016 Glider bvba
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- */
-#ifndef __DT_BINDINGS_POWER_R8A7796_SYSC_H__
-#define __DT_BINDINGS_POWER_R8A7796_SYSC_H__
-
-/*
- * These power domain indices match the numbers of the interrupt bits
- * representing the power areas in the various Interrupt Registers
- * (e.g. SYSCISR, Interrupt Status Register)
- */
-
-#define R8A7796_PD_CA57_CPU0 0
-#define R8A7796_PD_CA57_CPU1 1
-#define R8A7796_PD_CA53_CPU0 5
-#define R8A7796_PD_CA53_CPU1 6
-#define R8A7796_PD_CA53_CPU2 7
-#define R8A7796_PD_CA53_CPU3 8
-#define R8A7796_PD_CA57_SCU 12
-#define R8A7796_PD_CR7 13
-#define R8A7796_PD_A3VC 14
-#define R8A7796_PD_3DG_A 17
-#define R8A7796_PD_3DG_B 18
-#define R8A7796_PD_CA53_SCU 21
-#define R8A7796_PD_A3IR 24
-#define R8A7796_PD_A2VC0 25
-#define R8A7796_PD_A2VC1 26
-
-/* Always-on power area */
-#define R8A7796_PD_ALWAYS_ON 32
-
-#endif /* __DT_BINDINGS_POWER_R8A7796_SYSC_H__ */
diff --git a/include/dt-bindings/power/r8a77965-sysc.h b/include/dt-bindings/power/r8a77965-sysc.h
deleted file mode 100644
index de82d8a..0000000
--- a/include/dt-bindings/power/r8a77965-sysc.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2018 Jacopo Mondi <jacopo+renesas@jmondi.org>
- * Copyright (C) 2016 Glider bvba
- */
-
-#ifndef __DT_BINDINGS_POWER_R8A77965_SYSC_H__
-#define __DT_BINDINGS_POWER_R8A77965_SYSC_H__
-
-/*
- * These power domain indices match the numbers of the interrupt bits
- * representing the power areas in the various Interrupt Registers
- * (e.g. SYSCISR, Interrupt Status Register)
- */
-
-#define R8A77965_PD_CA57_CPU0 0
-#define R8A77965_PD_CA57_CPU1 1
-#define R8A77965_PD_A3VP 9
-#define R8A77965_PD_CA57_SCU 12
-#define R8A77965_PD_CR7 13
-#define R8A77965_PD_A3VC 14
-#define R8A77965_PD_3DG_A 17
-#define R8A77965_PD_3DG_B 18
-#define R8A77965_PD_A2VC1 26
-
-/* Always-on power area */
-#define R8A77965_PD_ALWAYS_ON 32
-
-#endif /* __DT_BINDINGS_POWER_R8A77965_SYSC_H__ */
diff --git a/include/dt-bindings/power/r8a77970-sysc.h b/include/dt-bindings/power/r8a77970-sysc.h
deleted file mode 100644
index 85cc5f2..0000000
--- a/include/dt-bindings/power/r8a77970-sysc.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * Copyright (C) 2017 Cogent Embedded Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#ifndef __DT_BINDINGS_POWER_R8A77970_SYSC_H__
-#define __DT_BINDINGS_POWER_R8A77970_SYSC_H__
-
-/*
- * These power domain indices match the numbers of the interrupt bits
- * representing the power areas in the various Interrupt Registers
- * (e.g. SYSCISR, Interrupt Status Register)
- */
-
-#define R8A77970_PD_CA53_CPU0 5
-#define R8A77970_PD_CA53_CPU1 6
-#define R8A77970_PD_CA53_SCU 21
-#define R8A77970_PD_A2IR0 23
-#define R8A77970_PD_A3IR 24
-#define R8A77970_PD_A2IR1 27
-#define R8A77970_PD_A2DP 28
-#define R8A77970_PD_A2CN 29
-#define R8A77970_PD_A2SC0 30
-#define R8A77970_PD_A2SC1 31
-
-/* Always-on power area */
-#define R8A77970_PD_ALWAYS_ON 32
-
-#endif /* __DT_BINDINGS_POWER_R8A77970_SYSC_H__ */
diff --git a/include/dt-bindings/power/r8a77980-sysc.h b/include/dt-bindings/power/r8a77980-sysc.h
deleted file mode 100644
index e12c858..0000000
--- a/include/dt-bindings/power/r8a77980-sysc.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0
- *
- * Copyright (C) 2018 Renesas Electronics Corp.
- * Copyright (C) 2018 Cogent Embedded, Inc.
- */
-#ifndef __DT_BINDINGS_POWER_R8A77980_SYSC_H__
-#define __DT_BINDINGS_POWER_R8A77980_SYSC_H__
-
-/*
- * These power domain indices match the numbers of the interrupt bits
- * representing the power areas in the various Interrupt Registers
- * (e.g. SYSCISR, Interrupt Status Register)
- */
-
-#define R8A77980_PD_A2SC2 0
-#define R8A77980_PD_A2SC3 1
-#define R8A77980_PD_A2SC4 2
-#define R8A77980_PD_A2DP0 3
-#define R8A77980_PD_A2DP1 4
-#define R8A77980_PD_CA53_CPU0 5
-#define R8A77980_PD_CA53_CPU1 6
-#define R8A77980_PD_CA53_CPU2 7
-#define R8A77980_PD_CA53_CPU3 8
-#define R8A77980_PD_A2CN 10
-#define R8A77980_PD_A3VIP0 11
-#define R8A77980_PD_A2IR5 12
-#define R8A77980_PD_CR7 13
-#define R8A77980_PD_A2IR4 15
-#define R8A77980_PD_CA53_SCU 21
-#define R8A77980_PD_A2IR0 23
-#define R8A77980_PD_A3IR 24
-#define R8A77980_PD_A3VIP1 25
-#define R8A77980_PD_A3VIP2 26
-#define R8A77980_PD_A2IR1 27
-#define R8A77980_PD_A2IR2 28
-#define R8A77980_PD_A2IR3 29
-#define R8A77980_PD_A2SC0 30
-#define R8A77980_PD_A2SC1 31
-
-/* Always-on power area */
-#define R8A77980_PD_ALWAYS_ON 32
-
-#endif /* __DT_BINDINGS_POWER_R8A77980_SYSC_H__ */
diff --git a/include/dt-bindings/power/r8a77990-sysc.h b/include/dt-bindings/power/r8a77990-sysc.h
deleted file mode 100644
index 944d85b..0000000
--- a/include/dt-bindings/power/r8a77990-sysc.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2018 Renesas Electronics Corp.
- */
-#ifndef __DT_BINDINGS_POWER_R8A77990_SYSC_H__
-#define __DT_BINDINGS_POWER_R8A77990_SYSC_H__
-
-/*
- * These power domain indices match the numbers of the interrupt bits
- * representing the power areas in the various Interrupt Registers
- * (e.g. SYSCISR, Interrupt Status Register)
- */
-
-#define R8A77990_PD_CA53_CPU0 5
-#define R8A77990_PD_CA53_CPU1 6
-#define R8A77990_PD_CR7 13
-#define R8A77990_PD_A3VC 14
-#define R8A77990_PD_3DG_A 17
-#define R8A77990_PD_3DG_B 18
-#define R8A77990_PD_CA53_SCU 21
-#define R8A77990_PD_A2VC1 26
-
-/* Always-on power area */
-#define R8A77990_PD_ALWAYS_ON 32
-
-#endif /* __DT_BINDINGS_POWER_R8A77990_SYSC_H__ */
diff --git a/include/dt-bindings/power/r8a77995-sysc.h b/include/dt-bindings/power/r8a77995-sysc.h
deleted file mode 100644
index 09d0ed5..0000000
--- a/include/dt-bindings/power/r8a77995-sysc.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * Copyright (C) 2017 Glider bvba
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- */
-#ifndef __DT_BINDINGS_POWER_R8A77995_SYSC_H__
-#define __DT_BINDINGS_POWER_R8A77995_SYSC_H__
-
-/*
- * These power domain indices match the numbers of the interrupt bits
- * representing the power areas in the various Interrupt Registers
- * (e.g. SYSCISR, Interrupt Status Register)
- */
-
-#define R8A77995_PD_CA53_CPU0 5
-#define R8A77995_PD_CA53_SCU 21
-
-/* Always-on power area */
-#define R8A77995_PD_ALWAYS_ON 32
-
-#endif /* __DT_BINDINGS_POWER_R8A77995_SYSC_H__ */
diff --git a/include/dt-bindings/power/raspberrypi-power.h b/include/dt-bindings/power/raspberrypi-power.h
deleted file mode 100644
index b3ff8e0..0000000
--- a/include/dt-bindings/power/raspberrypi-power.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * Copyright © 2015 Broadcom
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef _DT_BINDINGS_ARM_BCM2835_RPI_POWER_H
-#define _DT_BINDINGS_ARM_BCM2835_RPI_POWER_H
-
-/* These power domain indices are the firmware interface's indices
- * minus one.
- */
-#define RPI_POWER_DOMAIN_I2C0 0
-#define RPI_POWER_DOMAIN_I2C1 1
-#define RPI_POWER_DOMAIN_I2C2 2
-#define RPI_POWER_DOMAIN_VIDEO_SCALER 3
-#define RPI_POWER_DOMAIN_VPU1 4
-#define RPI_POWER_DOMAIN_HDMI 5
-#define RPI_POWER_DOMAIN_USB 6
-#define RPI_POWER_DOMAIN_VEC 7
-#define RPI_POWER_DOMAIN_JPEG 8
-#define RPI_POWER_DOMAIN_H264 9
-#define RPI_POWER_DOMAIN_V3D 10
-#define RPI_POWER_DOMAIN_ISP 11
-#define RPI_POWER_DOMAIN_UNICAM0 12
-#define RPI_POWER_DOMAIN_UNICAM1 13
-#define RPI_POWER_DOMAIN_CCP2RX 14
-#define RPI_POWER_DOMAIN_CSI2 15
-#define RPI_POWER_DOMAIN_CPI 16
-#define RPI_POWER_DOMAIN_DSI0 17
-#define RPI_POWER_DOMAIN_DSI1 18
-#define RPI_POWER_DOMAIN_TRANSPOSER 19
-#define RPI_POWER_DOMAIN_CCP2TX 20
-#define RPI_POWER_DOMAIN_CDP 21
-#define RPI_POWER_DOMAIN_ARM 22
-
-#define RPI_POWER_DOMAIN_COUNT 23
-
-#endif /* _DT_BINDINGS_ARM_BCM2835_RPI_POWER_H */
diff --git a/include/dt-bindings/power/rk3399-power.h b/include/dt-bindings/power/rk3399-power.h
deleted file mode 100644
index 168b3bf..0000000
--- a/include/dt-bindings/power/rk3399-power.h
+++ /dev/null
@@ -1,53 +0,0 @@
-#ifndef __DT_BINDINGS_POWER_RK3399_POWER_H__
-#define __DT_BINDINGS_POWER_RK3399_POWER_H__
-
-/* VD_CORE_L */
-#define RK3399_PD_A53_L0 0
-#define RK3399_PD_A53_L1 1
-#define RK3399_PD_A53_L2 2
-#define RK3399_PD_A53_L3 3
-#define RK3399_PD_SCU_L 4
-
-/* VD_CORE_B */
-#define RK3399_PD_A72_B0 5
-#define RK3399_PD_A72_B1 6
-#define RK3399_PD_SCU_B 7
-
-/* VD_LOGIC */
-#define RK3399_PD_TCPD0 8
-#define RK3399_PD_TCPD1 9
-#define RK3399_PD_CCI 10
-#define RK3399_PD_CCI0 11
-#define RK3399_PD_CCI1 12
-#define RK3399_PD_PERILP 13
-#define RK3399_PD_PERIHP 14
-#define RK3399_PD_VIO 15
-#define RK3399_PD_VO 16
-#define RK3399_PD_VOPB 17
-#define RK3399_PD_VOPL 18
-#define RK3399_PD_ISP0 19
-#define RK3399_PD_ISP1 20
-#define RK3399_PD_HDCP 21
-#define RK3399_PD_GMAC 22
-#define RK3399_PD_EMMC 23
-#define RK3399_PD_USB3 24
-#define RK3399_PD_EDP 25
-#define RK3399_PD_GIC 26
-#define RK3399_PD_SD 27
-#define RK3399_PD_SDIOAUDIO 28
-#define RK3399_PD_ALIVE 29
-
-/* VD_CENTER */
-#define RK3399_PD_CENTER 30
-#define RK3399_PD_VCODEC 31
-#define RK3399_PD_VDU 32
-#define RK3399_PD_RGA 33
-#define RK3399_PD_IEP 34
-
-/* VD_GPU */
-#define RK3399_PD_GPU 35
-
-/* VD_PMU */
-#define RK3399_PD_PMU 36
-
-#endif
diff --git a/include/dt-bindings/power/tegra186-powergate.h b/include/dt-bindings/power/tegra186-powergate.h
deleted file mode 100644
index 17e7549..0000000
--- a/include/dt-bindings/power/tegra186-powergate.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (c) 2015-2016, NVIDIA CORPORATION.
- */
-
-#ifndef _DT_BINDINGS_POWER_TEGRA186_POWERGATE_H
-#define _DT_BINDINGS_POWER_TEGRA186_POWERGATE_H
-
-#define TEGRA186_POWER_DOMAIN_AUD 0
-#define TEGRA186_POWER_DOMAIN_DFD 1
-#define TEGRA186_POWER_DOMAIN_DISP 2
-#define TEGRA186_POWER_DOMAIN_DISPB 3
-#define TEGRA186_POWER_DOMAIN_DISPC 4
-#define TEGRA186_POWER_DOMAIN_ISPA 5
-#define TEGRA186_POWER_DOMAIN_NVDEC 6
-#define TEGRA186_POWER_DOMAIN_NVJPG 7
-#define TEGRA186_POWER_DOMAIN_MPE 8
-#define TEGRA186_POWER_DOMAIN_PCX 9
-#define TEGRA186_POWER_DOMAIN_SAX 10
-#define TEGRA186_POWER_DOMAIN_VE 11
-#define TEGRA186_POWER_DOMAIN_VIC 12
-#define TEGRA186_POWER_DOMAIN_XUSBA 13
-#define TEGRA186_POWER_DOMAIN_XUSBB 14
-#define TEGRA186_POWER_DOMAIN_XUSBC 15
-#define TEGRA186_POWER_DOMAIN_GPU 43
-#define TEGRA186_POWER_DOMAIN_MAX 44
-
-#endif
diff --git a/include/dt-bindings/power/xlnx-zynqmp-power.h b/include/dt-bindings/power/xlnx-zynqmp-power.h
deleted file mode 100644
index 0d9a412..0000000
--- a/include/dt-bindings/power/xlnx-zynqmp-power.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2018 Xilinx, Inc.
- */
-
-#ifndef _DT_BINDINGS_ZYNQMP_POWER_H
-#define _DT_BINDINGS_ZYNQMP_POWER_H
-
-#define PD_USB_0 22
-#define PD_USB_1 23
-#define PD_TTC_0 24
-#define PD_TTC_1 25
-#define PD_TTC_2 26
-#define PD_TTC_3 27
-#define PD_SATA 28
-#define PD_ETH_0 29
-#define PD_ETH_1 30
-#define PD_ETH_2 31
-#define PD_ETH_3 32
-#define PD_UART_0 33
-#define PD_UART_1 34
-#define PD_SPI_0 35
-#define PD_SPI_1 36
-#define PD_I2C_0 37
-#define PD_I2C_1 38
-#define PD_SD_0 39
-#define PD_SD_1 40
-#define PD_DP 41
-#define PD_GDMA 42
-#define PD_ADMA 43
-#define PD_NAND 44
-#define PD_QSPI 45
-#define PD_GPIO 46
-#define PD_CAN_0 47
-#define PD_CAN_1 48
-#define PD_GPU 58
-#define PD_PCIE 59
-
-#endif
diff --git a/include/dt-bindings/pwm/pwm.h b/include/dt-bindings/pwm/pwm.h
deleted file mode 100644
index 96f49e8..0000000
--- a/include/dt-bindings/pwm/pwm.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * This header provides constants for most PWM bindings.
- *
- * Most PWM bindings can include a flags cell as part of the PWM specifier.
- * In most cases, the format of the flags cell uses the standard values
- * defined in this header.
- */
-
-#ifndef _DT_BINDINGS_PWM_PWM_H
-#define _DT_BINDINGS_PWM_PWM_H
-
-#define PWM_POLARITY_INVERTED (1 << 0)
-
-#endif
diff --git a/include/dt-bindings/regulator/maxim,max77802.h b/include/dt-bindings/regulator/maxim,max77802.h
deleted file mode 100644
index cf28631..0000000
--- a/include/dt-bindings/regulator/maxim,max77802.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- * Copyright (C) 2014 Google, Inc
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * Device Tree binding constants for the Maxim 77802 PMIC regulators
- */
-
-#ifndef _DT_BINDINGS_REGULATOR_MAXIM_MAX77802_H
-#define _DT_BINDINGS_REGULATOR_MAXIM_MAX77802_H
-
-/* Regulator operating modes */
-#define MAX77802_OPMODE_LP 1
-#define MAX77802_OPMODE_NORMAL 3
-
-#endif /* _DT_BINDINGS_REGULATOR_MAXIM_MAX77802_H */
diff --git a/include/dt-bindings/reset/altr,rst-mgr-a10.h b/include/dt-bindings/reset/altr,rst-mgr-a10.h
deleted file mode 100644
index acb0bbf..0000000
--- a/include/dt-bindings/reset/altr,rst-mgr-a10.h
+++ /dev/null
@@ -1,110 +0,0 @@
-/*
- * Copyright (c) 2014, Steffen Trumtrar <s.trumtrar@pengutronix.de>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_A10_H
-#define _DT_BINDINGS_RESET_ALTR_RST_MGR_A10_H
-
-/* MPUMODRST */
-#define CPU0_RESET 0
-#define CPU1_RESET 1
-#define WDS_RESET 2
-#define SCUPER_RESET 3
-
-/* PER0MODRST */
-#define EMAC0_RESET 32
-#define EMAC1_RESET 33
-#define EMAC2_RESET 34
-#define USB0_RESET 35
-#define USB1_RESET 36
-#define NAND_RESET 37
-#define QSPI_RESET 38
-#define SDMMC_RESET 39
-#define EMAC0_OCP_RESET 40
-#define EMAC1_OCP_RESET 41
-#define EMAC2_OCP_RESET 42
-#define USB0_OCP_RESET 43
-#define USB1_OCP_RESET 44
-#define NAND_OCP_RESET 45
-#define QSPI_OCP_RESET 46
-#define SDMMC_OCP_RESET 47
-#define DMA_RESET 48
-#define SPIM0_RESET 49
-#define SPIM1_RESET 50
-#define SPIS0_RESET 51
-#define SPIS1_RESET 52
-#define DMA_OCP_RESET 53
-#define EMAC_PTP_RESET 54
-/* 55 is empty*/
-#define DMAIF0_RESET 56
-#define DMAIF1_RESET 57
-#define DMAIF2_RESET 58
-#define DMAIF3_RESET 59
-#define DMAIF4_RESET 60
-#define DMAIF5_RESET 61
-#define DMAIF6_RESET 62
-#define DMAIF7_RESET 63
-
-/* PER1MODRST */
-#define L4WD0_RESET 64
-#define L4WD1_RESET 65
-#define L4SYSTIMER0_RESET 66
-#define L4SYSTIMER1_RESET 67
-#define SPTIMER0_RESET 68
-#define SPTIMER1_RESET 69
-/* 70-71 is reserved */
-#define I2C0_RESET 72
-#define I2C1_RESET 73
-#define I2C2_RESET 74
-#define I2C3_RESET 75
-#define I2C4_RESET 76
-/* 77-79 is reserved */
-#define UART0_RESET 80
-#define UART1_RESET 81
-/* 82-87 is reserved */
-#define GPIO0_RESET 88
-#define GPIO1_RESET 89
-#define GPIO2_RESET 90
-
-/* BRGMODRST */
-#define HPS2FPGA_RESET 96
-#define LWHPS2FPGA_RESET 97
-#define FPGA2HPS_RESET 98
-#define F2SSDRAM0_RESET 99
-#define F2SSDRAM1_RESET 100
-#define F2SSDRAM2_RESET 101
-#define DDRSCH_RESET 102
-
-/* SYSMODRST*/
-#define ROM_RESET 128
-#define OCRAM_RESET 129
-/* 130 is reserved */
-#define FPGAMGR_RESET 131
-#define S2F_RESET 132
-#define SYSDBG_RESET 133
-#define OCRAM_OCP_RESET 134
-
-/* COLDMODRST */
-#define CLKMGRCOLD_RESET 160
-/* 161-162 is reserved */
-#define S2FCOLD_RESET 163
-#define TIMESTAMPCOLD_RESET 164
-#define TAPCOLD_RESET 165
-#define HMCCOLD_RESET 166
-#define IOMGRCOLD_RESET 167
-
-/* NRSTMODRST */
-#define NRSTPINOE_RESET 192
-
-/* DBGMODRST */
-#define DBG_RESET 224
-#endif
diff --git a/include/dt-bindings/reset/altr,rst-mgr-s10.h b/include/dt-bindings/reset/altr,rst-mgr-s10.h
deleted file mode 100644
index 1fdcf8a..0000000
--- a/include/dt-bindings/reset/altr,rst-mgr-s10.h
+++ /dev/null
@@ -1,96 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2016-2018 Intel Corporation. All rights reserved
- * Copyright (C) 2016 Altera Corporation. All rights reserved
- * derived from Steffen Trumtrar's "altr,rst-mgr-a10.h"
- */
-
-#ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_S10_H
-#define _DT_BINDINGS_RESET_ALTR_RST_MGR_S10_H
-
-/* MPUMODRST */
-#define CPU0_RESET 0
-#define CPU1_RESET 1
-#define CPU2_RESET 2
-#define CPU3_RESET 3
-
-/* PER0MODRST */
-#define EMAC0_RESET 32
-#define EMAC1_RESET 33
-#define EMAC2_RESET 34
-#define USB0_RESET 35
-#define USB1_RESET 36
-#define NAND_RESET 37
-/* 38 is empty */
-#define SDMMC_RESET 39
-#define EMAC0_OCP_RESET 40
-#define EMAC1_OCP_RESET 41
-#define EMAC2_OCP_RESET 42
-#define USB0_OCP_RESET 43
-#define USB1_OCP_RESET 44
-#define NAND_OCP_RESET 45
-/* 46 is empty */
-#define SDMMC_OCP_RESET 47
-#define DMA_RESET 48
-#define SPIM0_RESET 49
-#define SPIM1_RESET 50
-#define SPIS0_RESET 51
-#define SPIS1_RESET 52
-#define DMA_OCP_RESET 53
-#define EMAC_PTP_RESET 54
-/* 55 is empty*/
-#define DMAIF0_RESET 56
-#define DMAIF1_RESET 57
-#define DMAIF2_RESET 58
-#define DMAIF3_RESET 59
-#define DMAIF4_RESET 60
-#define DMAIF5_RESET 61
-#define DMAIF6_RESET 62
-#define DMAIF7_RESET 63
-
-/* PER1MODRST */
-#define WATCHDOG0_RESET 64
-#define WATCHDOG1_RESET 65
-#define WATCHDOG2_RESET 66
-#define WATCHDOG3_RESET 67
-#define L4SYSTIMER0_RESET 68
-#define L4SYSTIMER1_RESET 69
-#define SPTIMER0_RESET 70
-#define SPTIMER1_RESET 71
-#define I2C0_RESET 72
-#define I2C1_RESET 73
-#define I2C2_RESET 74
-#define I2C3_RESET 75
-#define I2C4_RESET 76
-/* 77-79 is empty */
-#define UART0_RESET 80
-#define UART1_RESET 81
-/* 82-87 is empty */
-#define GPIO0_RESET 88
-#define GPIO1_RESET 89
-
-/* BRGMODRST */
-#define SOC2FPGA_RESET 96
-#define LWHPS2FPGA_RESET 97
-#define FPGA2SOC_RESET 98
-#define F2SSDRAM0_RESET 99
-#define F2SSDRAM1_RESET 100
-#define F2SSDRAM2_RESET 101
-#define DDRSCH_RESET 102
-
-/* COLDMODRST */
-#define CPUPO0_RESET 160
-#define CPUPO1_RESET 161
-#define CPUPO2_RESET 162
-#define CPUPO3_RESET 163
-/* 164-167 is empty */
-#define L2_RESET 168
-
-/* DBGMODRST */
-#define DBG_RESET 224
-#define CSDAP_RESET 225
-
-/* TAPMODRST */
-#define TAP_RESET 256
-
-#endif
diff --git a/include/dt-bindings/reset/altr,rst-mgr.h b/include/dt-bindings/reset/altr,rst-mgr.h
deleted file mode 100644
index 5b7ad73..0000000
--- a/include/dt-bindings/reset/altr,rst-mgr.h
+++ /dev/null
@@ -1,82 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (c) 2014, Steffen Trumtrar <s.trumtrar@pengutronix.de>
- */
-
-#ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_H
-#define _DT_BINDINGS_RESET_ALTR_RST_MGR_H
-
-/* MPUMODRST */
-#define CPU0_RESET 0
-#define CPU1_RESET 1
-#define WDS_RESET 2
-#define SCUPER_RESET 3
-#define L2_RESET 4
-
-/* PERMODRST */
-#define EMAC0_RESET 32
-#define EMAC1_RESET 33
-#define USB0_RESET 34
-#define USB1_RESET 35
-#define NAND_RESET 36
-#define QSPI_RESET 37
-#define L4WD0_RESET 38
-#define L4WD1_RESET 39
-#define OSC1TIMER0_RESET 40
-#define OSC1TIMER1_RESET 41
-#define SPTIMER0_RESET 42
-#define SPTIMER1_RESET 43
-#define I2C0_RESET 44
-#define I2C1_RESET 45
-#define I2C2_RESET 46
-#define I2C3_RESET 47
-#define UART0_RESET 48
-#define UART1_RESET 49
-#define SPIM0_RESET 50
-#define SPIM1_RESET 51
-#define SPIS0_RESET 52
-#define SPIS1_RESET 53
-#define SDMMC_RESET 54
-#define CAN0_RESET 55
-#define CAN1_RESET 56
-#define GPIO0_RESET 57
-#define GPIO1_RESET 58
-#define GPIO2_RESET 59
-#define DMA_RESET 60
-#define SDR_RESET 61
-
-/* PER2MODRST */
-#define DMAIF0_RESET 64
-#define DMAIF1_RESET 65
-#define DMAIF2_RESET 66
-#define DMAIF3_RESET 67
-#define DMAIF4_RESET 68
-#define DMAIF5_RESET 69
-#define DMAIF6_RESET 70
-#define DMAIF7_RESET 71
-
-/* BRGMODRST */
-#define HPS2FPGA_RESET 96
-#define LWHPS2FPGA_RESET 97
-#define FPGA2HPS_RESET 98
-
-/* MISCMODRST*/
-#define ROM_RESET 128
-#define OCRAM_RESET 129
-#define SYSMGR_RESET 130
-#define SYSMGRCOLD_RESET 131
-#define FPGAMGR_RESET 132
-#define ACPIDMAP_RESET 133
-#define S2F_RESET 134
-#define S2FCOLD_RESET 135
-#define NRSTPIN_RESET 136
-#define TIMESTAMPCOLD_RESET 137
-#define CLKMGRCOLD_RESET 138
-#define SCANMGR_RESET 139
-#define FRZCTRLCOLD_RESET 140
-#define SYSDBG_RESET 141
-#define DBG_RESET 142
-#define TAPCOLD_RESET 143
-#define SDRCOLD_RESET 144
-
-#endif
diff --git a/include/dt-bindings/reset/amlogic,meson-axg-audio-arb.h b/include/dt-bindings/reset/amlogic,meson-axg-audio-arb.h
deleted file mode 100644
index 05c3636..0000000
--- a/include/dt-bindings/reset/amlogic,meson-axg-audio-arb.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0 OR MIT)
- *
- * Copyright (c) 2018 Baylibre SAS.
- * Author: Jerome Brunet <jbrunet@baylibre.com>
- */
-
-#ifndef _DT_BINDINGS_AMLOGIC_MESON_AXG_AUDIO_ARB_H
-#define _DT_BINDINGS_AMLOGIC_MESON_AXG_AUDIO_ARB_H
-
-#define AXG_ARB_TODDR_A 0
-#define AXG_ARB_TODDR_B 1
-#define AXG_ARB_TODDR_C 2
-#define AXG_ARB_FRDDR_A 3
-#define AXG_ARB_FRDDR_B 4
-#define AXG_ARB_FRDDR_C 5
-
-#endif /* _DT_BINDINGS_AMLOGIC_MESON_AXG_AUDIO_ARB_H */
diff --git a/include/dt-bindings/reset/amlogic,meson-axg-reset.h b/include/dt-bindings/reset/amlogic,meson-axg-reset.h
deleted file mode 100644
index ad6f55d..0000000
--- a/include/dt-bindings/reset/amlogic,meson-axg-reset.h
+++ /dev/null
@@ -1,124 +0,0 @@
-/*
- *
- * Copyright (c) 2016 BayLibre, SAS.
- * Author: Neil Armstrong <narmstrong@baylibre.com>
- *
- * Copyright (c) 2017 Amlogic, inc.
- * Author: Yixun Lan <yixun.lan@amlogic.com>
- *
- * SPDX-License-Identifier: (GPL-2.0+ OR BSD)
- */
-
-#ifndef _DT_BINDINGS_AMLOGIC_MESON_AXG_RESET_H
-#define _DT_BINDINGS_AMLOGIC_MESON_AXG_RESET_H
-
-/* RESET0 */
-#define RESET_HIU 0
-#define RESET_PCIE_A 1
-#define RESET_PCIE_B 2
-#define RESET_DDR_TOP 3
-/* 4 */
-#define RESET_VIU 5
-#define RESET_PCIE_PHY 6
-#define RESET_PCIE_APB 7
-/* 8 */
-/* 9 */
-#define RESET_VENC 10
-#define RESET_ASSIST 11
-/* 12 */
-#define RESET_VCBUS 13
-/* 14 */
-/* 15 */
-#define RESET_GIC 16
-#define RESET_CAPB3_DECODE 17
-/* 18-21 */
-#define RESET_SYS_CPU_CAPB3 22
-#define RESET_CBUS_CAPB3 23
-#define RESET_AHB_CNTL 24
-#define RESET_AHB_DATA 25
-#define RESET_VCBUS_CLK81 26
-#define RESET_MMC 27
-/* 28-31 */
-/* RESET1 */
-/* 32 */
-/* 33 */
-#define RESET_USB_OTG 34
-#define RESET_DDR 35
-#define RESET_AO_RESET 36
-/* 37 */
-#define RESET_AHB_SRAM 38
-/* 39 */
-/* 40 */
-#define RESET_DMA 41
-#define RESET_ISA 42
-#define RESET_ETHERNET 43
-/* 44 */
-#define RESET_SD_EMMC_B 45
-#define RESET_SD_EMMC_C 46
-#define RESET_ROM_BOOT 47
-#define RESET_SYS_CPU_0 48
-#define RESET_SYS_CPU_1 49
-#define RESET_SYS_CPU_2 50
-#define RESET_SYS_CPU_3 51
-#define RESET_SYS_CPU_CORE_0 52
-#define RESET_SYS_CPU_CORE_1 53
-#define RESET_SYS_CPU_CORE_2 54
-#define RESET_SYS_CPU_CORE_3 55
-#define RESET_SYS_PLL_DIV 56
-#define RESET_SYS_CPU_AXI 57
-#define RESET_SYS_CPU_L2 58
-#define RESET_SYS_CPU_P 59
-#define RESET_SYS_CPU_MBIST 60
-/* 61-63 */
-/* RESET2 */
-/* 64 */
-/* 65 */
-#define RESET_AUDIO 66
-/* 67 */
-#define RESET_MIPI_HOST 68
-#define RESET_AUDIO_LOCKER 69
-#define RESET_GE2D 70
-/* 71-76 */
-#define RESET_AO_CPU_RESET 77
-/* 78-95 */
-/* RESET3 */
-#define RESET_RING_OSCILLATOR 96
-/* 97-127 */
-/* RESET4 */
-/* 128 */
-/* 129 */
-#define RESET_MIPI_PHY 130
-/* 131-140 */
-#define RESET_VENCL 141
-#define RESET_I2C_MASTER_2 142
-#define RESET_I2C_MASTER_1 143
-/* 144-159 */
-/* RESET5 */
-/* 160-191 */
-/* RESET6 */
-#define RESET_PERIPHS_GENERAL 192
-#define RESET_PERIPHS_SPICC 193
-/* 194 */
-/* 195 */
-#define RESET_PERIPHS_I2C_MASTER_0 196
-/* 197-200 */
-#define RESET_PERIPHS_UART_0 201
-#define RESET_PERIPHS_UART_1 202
-/* 203-204 */
-#define RESET_PERIPHS_SPI_0 205
-#define RESET_PERIPHS_I2C_MASTER_3 206
-/* 207-223 */
-/* RESET7 */
-#define RESET_USB_DDR_0 224
-#define RESET_USB_DDR_1 225
-#define RESET_USB_DDR_2 226
-#define RESET_USB_DDR_3 227
-/* 228 */
-#define RESET_DEVICE_MMC_ARB 229
-/* 230 */
-#define RESET_VID_LOCK 231
-#define RESET_A9_DMC_PIPEL 232
-#define RESET_DMC_VPU_PIPEL 233
-/* 234-255 */
-
-#endif
diff --git a/include/dt-bindings/reset/amlogic,meson-g12a-audio-reset.h b/include/dt-bindings/reset/amlogic,meson-g12a-audio-reset.h
deleted file mode 100644
index 14b78da..0000000
--- a/include/dt-bindings/reset/amlogic,meson-g12a-audio-reset.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (c) 2019 BayLibre, SAS.
- * Author: Jerome Brunet <jbrunet@baylibre.com>
- *
- */
-
-#ifndef _DT_BINDINGS_AMLOGIC_MESON_G12A_AUDIO_RESET_H
-#define _DT_BINDINGS_AMLOGIC_MESON_G12A_AUDIO_RESET_H
-
-#define AUD_RESET_PDM 0
-#define AUD_RESET_TDMIN_A 1
-#define AUD_RESET_TDMIN_B 2
-#define AUD_RESET_TDMIN_C 3
-#define AUD_RESET_TDMIN_LB 4
-#define AUD_RESET_LOOPBACK 5
-#define AUD_RESET_TODDR_A 6
-#define AUD_RESET_TODDR_B 7
-#define AUD_RESET_TODDR_C 8
-#define AUD_RESET_FRDDR_A 9
-#define AUD_RESET_FRDDR_B 10
-#define AUD_RESET_FRDDR_C 11
-#define AUD_RESET_TDMOUT_A 12
-#define AUD_RESET_TDMOUT_B 13
-#define AUD_RESET_TDMOUT_C 14
-#define AUD_RESET_SPDIFOUT 15
-#define AUD_RESET_SPDIFOUT_B 16
-#define AUD_RESET_SPDIFIN 17
-#define AUD_RESET_EQDRC 18
-#define AUD_RESET_RESAMPLE 19
-#define AUD_RESET_DDRARB 20
-#define AUD_RESET_POWDET 21
-#define AUD_RESET_TORAM 22
-#define AUD_RESET_TOACODEC 23
-#define AUD_RESET_TOHDMITX 24
-#define AUD_RESET_CLKTREE 25
-
-#endif
diff --git a/include/dt-bindings/reset/amlogic,meson-g12a-reset.h b/include/dt-bindings/reset/amlogic,meson-g12a-reset.h
deleted file mode 100644
index 6d487c5..0000000
--- a/include/dt-bindings/reset/amlogic,meson-g12a-reset.h
+++ /dev/null
@@ -1,137 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
-/*
- * Copyright (c) 2019 BayLibre, SAS.
- * Author: Jerome Brunet <jbrunet@baylibre.com>
- *
- */
-
-#ifndef _DT_BINDINGS_AMLOGIC_MESON_G12A_RESET_H
-#define _DT_BINDINGS_AMLOGIC_MESON_G12A_RESET_H
-
-/* RESET0 */
-#define RESET_HIU 0
-/* 1 */
-#define RESET_DOS 2
-/* 3-4 */
-#define RESET_VIU 5
-#define RESET_AFIFO 6
-#define RESET_VID_PLL_DIV 7
-/* 8-9 */
-#define RESET_VENC 10
-#define RESET_ASSIST 11
-#define RESET_PCIE_CTRL_A 12
-#define RESET_VCBUS 13
-#define RESET_PCIE_PHY 14
-#define RESET_PCIE_APB 15
-#define RESET_GIC 16
-#define RESET_CAPB3_DECODE 17
-/* 18 */
-#define RESET_HDMITX_CAPB3 19
-#define RESET_DVALIN_CAPB3 20
-#define RESET_DOS_CAPB3 21
-/* 22 */
-#define RESET_CBUS_CAPB3 23
-#define RESET_AHB_CNTL 24
-#define RESET_AHB_DATA 25
-#define RESET_VCBUS_CLK81 26
-/* 27-31 */
-/* RESET1 */
-/* 32 */
-#define RESET_DEMUX 33
-#define RESET_USB 34
-#define RESET_DDR 35
-/* 36 */
-#define RESET_BT656 37
-#define RESET_AHB_SRAM 38
-/* 39 */
-#define RESET_PARSER 40
-/* 41 */
-#define RESET_ISA 42
-#define RESET_ETHERNET 43
-#define RESET_SD_EMMC_A 44
-#define RESET_SD_EMMC_B 45
-#define RESET_SD_EMMC_C 46
-/* 47 */
-#define RESET_USB_PHY20 48
-#define RESET_USB_PHY21 49
-/* 50-60 */
-#define RESET_AUDIO_CODEC 61
-/* 62-63 */
-/* RESET2 */
-/* 64 */
-#define RESET_AUDIO 65
-#define RESET_HDMITX_PHY 66
-/* 67 */
-#define RESET_MIPI_DSI_HOST 68
-#define RESET_ALOCKER 69
-#define RESET_GE2D 70
-#define RESET_PARSER_REG 71
-#define RESET_PARSER_FETCH 72
-#define RESET_CTL 73
-#define RESET_PARSER_TOP 74
-/* 75-77 */
-#define RESET_DVALIN 78
-#define RESET_HDMITX 79
-/* 80-95 */
-/* RESET3 */
-/* 96-95 */
-#define RESET_DEMUX_TOP 105
-#define RESET_DEMUX_DES_PL 106
-#define RESET_DEMUX_S2P_0 107
-#define RESET_DEMUX_S2P_1 108
-#define RESET_DEMUX_0 109
-#define RESET_DEMUX_1 110
-#define RESET_DEMUX_2 111
-/* 112-127 */
-/* RESET4 */
-/* 128-129 */
-#define RESET_MIPI_DSI_PHY 130
-/* 131-132 */
-#define RESET_RDMA 133
-#define RESET_VENCI 134
-#define RESET_VENCP 135
-/* 136 */
-#define RESET_VDAC 137
-/* 138-139 */
-#define RESET_VDI6 140
-#define RESET_VENCL 141
-#define RESET_I2C_M1 142
-#define RESET_I2C_M2 143
-/* 144-159 */
-/* RESET5 */
-/* 160-191 */
-/* RESET6 */
-#define RESET_GEN 192
-#define RESET_SPICC0 193
-#define RESET_SC 194
-#define RESET_SANA_3 195
-#define RESET_I2C_M0 196
-#define RESET_TS_PLL 197
-#define RESET_SPICC1 198
-#define RESET_STREAM 199
-#define RESET_TS_CPU 200
-#define RESET_UART0 201
-#define RESET_UART1_2 202
-#define RESET_ASYNC0 203
-#define RESET_ASYNC1 204
-#define RESET_SPIFC0 205
-#define RESET_I2C_M3 206
-/* 207-223 */
-/* RESET7 */
-#define RESET_USB_DDR_0 224
-#define RESET_USB_DDR_1 225
-#define RESET_USB_DDR_2 226
-#define RESET_USB_DDR_3 227
-#define RESET_TS_GPU 228
-#define RESET_DEVICE_MMC_ARB 229
-#define RESET_DVALIN_DMC_PIPL 230
-#define RESET_VID_LOCK 231
-#define RESET_NIC_DMC_PIPL 232
-#define RESET_DMC_VPU_PIPL 233
-#define RESET_GE2D_DMC_PIPL 234
-#define RESET_HCODEC_DMC_PIPL 235
-#define RESET_WAVE420_DMC_PIPL 236
-#define RESET_HEVCF_DMC_PIPL 237
-/* 238-255 */
-
-#endif
diff --git a/include/dt-bindings/reset/amlogic,meson-gxbb-reset.h b/include/dt-bindings/reset/amlogic,meson-gxbb-reset.h
deleted file mode 100644
index 524d607..0000000
--- a/include/dt-bindings/reset/amlogic,meson-gxbb-reset.h
+++ /dev/null
@@ -1,210 +0,0 @@
-/*
- * This file is provided under a dual BSD/GPLv2 license. When using or
- * redistributing this file, you may do so under either license.
- *
- * GPL LICENSE SUMMARY
- *
- * Copyright (c) 2016 BayLibre, SAS.
- * Author: Neil Armstrong <narmstrong@baylibre.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of version 2 of the GNU General Public License as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- * General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, see <http://www.gnu.org/licenses/>.
- * The full GNU General Public License is included in this distribution
- * in the file called COPYING.
- *
- * BSD LICENSE
- *
- * Copyright (c) 2016 BayLibre, SAS.
- * Author: Neil Armstrong <narmstrong@baylibre.com>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * * Neither the name of Intel Corporation nor the names of its
- * contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#ifndef _DT_BINDINGS_AMLOGIC_MESON_GXBB_RESET_H
-#define _DT_BINDINGS_AMLOGIC_MESON_GXBB_RESET_H
-
-/* RESET0 */
-#define RESET_HIU 0
-/* 1 */
-#define RESET_DOS_RESET 2
-#define RESET_DDR_TOP 3
-#define RESET_DCU_RESET 4
-#define RESET_VIU 5
-#define RESET_AIU 6
-#define RESET_VID_PLL_DIV 7
-/* 8 */
-#define RESET_PMUX 9
-#define RESET_VENC 10
-#define RESET_ASSIST 11
-#define RESET_AFIFO2 12
-#define RESET_VCBUS 13
-/* 14 */
-/* 15 */
-#define RESET_GIC 16
-#define RESET_CAPB3_DECODE 17
-#define RESET_NAND_CAPB3 18
-#define RESET_HDMITX_CAPB3 19
-#define RESET_MALI_CAPB3 20
-#define RESET_DOS_CAPB3 21
-#define RESET_SYS_CPU_CAPB3 22
-#define RESET_CBUS_CAPB3 23
-#define RESET_AHB_CNTL 24
-#define RESET_AHB_DATA 25
-#define RESET_VCBUS_CLK81 26
-#define RESET_MMC 27
-#define RESET_MIPI_0 28
-#define RESET_MIPI_1 29
-#define RESET_MIPI_2 30
-#define RESET_MIPI_3 31
-/* RESET1 */
-#define RESET_CPPM 32
-#define RESET_DEMUX 33
-#define RESET_USB_OTG 34
-#define RESET_DDR 35
-#define RESET_AO_RESET 36
-#define RESET_BT656 37
-#define RESET_AHB_SRAM 38
-/* 39 */
-#define RESET_PARSER 40
-#define RESET_BLKMV 41
-#define RESET_ISA 42
-#define RESET_ETHERNET 43
-#define RESET_SD_EMMC_A 44
-#define RESET_SD_EMMC_B 45
-#define RESET_SD_EMMC_C 46
-#define RESET_ROM_BOOT 47
-#define RESET_SYS_CPU_0 48
-#define RESET_SYS_CPU_1 49
-#define RESET_SYS_CPU_2 50
-#define RESET_SYS_CPU_3 51
-#define RESET_SYS_CPU_CORE_0 52
-#define RESET_SYS_CPU_CORE_1 53
-#define RESET_SYS_CPU_CORE_2 54
-#define RESET_SYS_CPU_CORE_3 55
-#define RESET_SYS_PLL_DIV 56
-#define RESET_SYS_CPU_AXI 57
-#define RESET_SYS_CPU_L2 58
-#define RESET_SYS_CPU_P 59
-#define RESET_SYS_CPU_MBIST 60
-/* 61 */
-/* 62 */
-/* 63 */
-/* RESET2 */
-#define RESET_VD_RMEM 64
-#define RESET_AUDIN 65
-#define RESET_HDMI_TX 66
-/* 67 */
-/* 68 */
-/* 69 */
-#define RESET_GE2D 70
-#define RESET_PARSER_REG 71
-#define RESET_PARSER_FETCH 72
-#define RESET_PARSER_CTL 73
-#define RESET_PARSER_TOP 74
-/* 75 */
-/* 76 */
-#define RESET_AO_CPU_RESET 77
-#define RESET_MALI 78
-#define RESET_HDMI_SYSTEM_RESET 79
-/* 80-95 */
-/* RESET3 */
-#define RESET_RING_OSCILLATOR 96
-#define RESET_SYS_CPU 97
-#define RESET_EFUSE 98
-#define RESET_SYS_CPU_BVCI 99
-#define RESET_AIFIFO 100
-#define RESET_TVFE 101
-#define RESET_AHB_BRIDGE_CNTL 102
-/* 103 */
-#define RESET_AUDIO_DAC 104
-#define RESET_DEMUX_TOP 105
-#define RESET_DEMUX_DES 106
-#define RESET_DEMUX_S2P_0 107
-#define RESET_DEMUX_S2P_1 108
-#define RESET_DEMUX_RESET_0 109
-#define RESET_DEMUX_RESET_1 110
-#define RESET_DEMUX_RESET_2 111
-/* 112-127 */
-/* RESET4 */
-/* 128 */
-/* 129 */
-/* 130 */
-/* 131 */
-#define RESET_DVIN_RESET 132
-#define RESET_RDMA 133
-#define RESET_VENCI 134
-#define RESET_VENCP 135
-/* 136 */
-#define RESET_VDAC 137
-#define RESET_RTC 138
-/* 139 */
-#define RESET_VDI6 140
-#define RESET_VENCL 141
-#define RESET_I2C_MASTER_2 142
-#define RESET_I2C_MASTER_1 143
-/* 144-159 */
-/* RESET5 */
-/* 160-191 */
-/* RESET6 */
-#define RESET_PERIPHS_GENERAL 192
-#define RESET_PERIPHS_SPICC 193
-#define RESET_PERIPHS_SMART_CARD 194
-#define RESET_PERIPHS_SAR_ADC 195
-#define RESET_PERIPHS_I2C_MASTER_0 196
-#define RESET_SANA 197
-/* 198 */
-#define RESET_PERIPHS_STREAM_INTERFACE 199
-#define RESET_PERIPHS_SDIO 200
-#define RESET_PERIPHS_UART_0 201
-#define RESET_PERIPHS_UART_1_2 202
-#define RESET_PERIPHS_ASYNC_0 203
-#define RESET_PERIPHS_ASYNC_1 204
-#define RESET_PERIPHS_SPI_0 205
-#define RESET_PERIPHS_SDHC 206
-#define RESET_UART_SLIP 207
-/* 208-223 */
-/* RESET7 */
-#define RESET_USB_DDR_0 224
-#define RESET_USB_DDR_1 225
-#define RESET_USB_DDR_2 226
-#define RESET_USB_DDR_3 227
-/* 228 */
-#define RESET_DEVICE_MMC_ARB 229
-/* 230 */
-#define RESET_VID_LOCK 231
-#define RESET_A9_DMC_PIPEL 232
-/* 233-255 */
-
-#endif
diff --git a/include/dt-bindings/reset/ast2500-reset.h b/include/dt-bindings/reset/ast2500-reset.h
deleted file mode 100644
index d1b6b23..0000000
--- a/include/dt-bindings/reset/ast2500-reset.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2017 Google, Inc
- */
-
-#ifndef _ABI_MACH_ASPEED_AST2500_RESET_H_
-#define _ABI_MACH_ASPEED_AST2500_RESET_H_
-
-/*
- * The values are intentionally layed out as flags in
- * WDT reset parameter.
- */
-
-#define AST_RESET_SOC 0
-#define AST_RESET_CHIP 1
-#define AST_RESET_CPU (1 << 1)
-#define AST_RESET_ARM (1 << 2)
-#define AST_RESET_COPROC (1 << 3)
-#define AST_RESET_SDRAM (1 << 4)
-#define AST_RESET_AHB (1 << 5)
-#define AST_RESET_I2C (1 << 6)
-#define AST_RESET_MAC1 (1 << 7)
-#define AST_RESET_MAC2 (1 << 8)
-#define AST_RESET_GCRT (1 << 9)
-#define AST_RESET_USB20 (1 << 10)
-#define AST_RESET_USB11_HOST (1 << 11)
-#define AST_RESET_USB11_HID (1 << 12)
-#define AST_RESET_VIDEO (1 << 13)
-#define AST_RESET_HAC (1 << 14)
-#define AST_RESET_LPC (1 << 15)
-#define AST_RESET_SDIO (1 << 16)
-#define AST_RESET_MIC (1 << 17)
-#define AST_RESET_CRT2D (1 << 18)
-#define AST_RESET_PWM (1 << 19)
-#define AST_RESET_PECI (1 << 20)
-#define AST_RESET_JTAG (1 << 21)
-#define AST_RESET_ADC (1 << 22)
-#define AST_RESET_GPIO (1 << 23)
-#define AST_RESET_MCTP (1 << 24)
-#define AST_RESET_XDMA (1 << 25)
-#define AST_RESET_SPI (1 << 26)
-#define AST_RESET_MISC (1 << 27)
-
-#endif /* _ABI_MACH_ASPEED_AST2500_RESET_H_ */
diff --git a/include/dt-bindings/reset/axg-aoclkc.h b/include/dt-bindings/reset/axg-aoclkc.h
deleted file mode 100644
index d342c0b..0000000
--- a/include/dt-bindings/reset/axg-aoclkc.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
-/*
- * Copyright (c) 2016 BayLibre, SAS
- * Author: Neil Armstrong <narmstrong@baylibre.com>
- *
- * Copyright (c) 2018 Amlogic, inc.
- * Author: Qiufang Dai <qiufang.dai@amlogic.com>
- */
-
-#ifndef DT_BINDINGS_RESET_AMLOGIC_MESON_AXG_AOCLK
-#define DT_BINDINGS_RESET_AMLOGIC_MESON_AXG_AOCLK
-
-#define RESET_AO_REMOTE 0
-#define RESET_AO_I2C_MASTER 1
-#define RESET_AO_I2C_SLAVE 2
-#define RESET_AO_UART1 3
-#define RESET_AO_UART2 4
-#define RESET_AO_IR_BLASTER 5
-
-#endif
diff --git a/include/dt-bindings/reset/bcm3380-reset.h b/include/dt-bindings/reset/bcm3380-reset.h
deleted file mode 100644
index 4cbf4d2..0000000
--- a/include/dt-bindings/reset/bcm3380-reset.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
- *
- * Derived from Broadcom GPL Source Code:
- * Copyright (C) Broadcom Corporation
- */
-
-#ifndef __DT_BINDINGS_RESET_BCM3380_H
-#define __DT_BINDINGS_RESET_BCM3380_H
-
-#define BCM3380_RST0_SPI 0
-#define BCM3380_RST0_PCM 13
-
-#endif /* __DT_BINDINGS_RESET_BCM3380_H */
diff --git a/include/dt-bindings/reset/bcm6318-reset.h b/include/dt-bindings/reset/bcm6318-reset.h
deleted file mode 100644
index 1422500..0000000
--- a/include/dt-bindings/reset/bcm6318-reset.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2018 Álvaro Fernández Rojas <noltari@gmail.com>
- *
- * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
- */
-
-#ifndef __DT_BINDINGS_RESET_BCM6318_H
-#define __DT_BINDINGS_RESET_BCM6318_H
-
-#define BCM6318_RST_SPI 0
-#define BCM6318_RST_EPHY 1
-#define BCM6318_RST_SAR 2
-#define BCM6318_RST_ENETSW 3
-#define BCM6318_RST_USBD 4
-#define BCM6318_RST_USBH 5
-#define BCM6318_RST_PCIE_CORE 6
-#define BCM6318_RST_PCIE 7
-#define BCM6318_RST_PCIE_EXT 8
-#define BCM6318_RST_PCIE_HARD 9
-#define BCM6318_RST_ADSL 10
-#define BCM6318_RST_PHYMIPS 11
-#define BCM6318_RST_HOSTMIPS 11
-
-#endif /* __DT_BINDINGS_RESET_BCM6318_H */
diff --git a/include/dt-bindings/reset/bcm63268-reset.h b/include/dt-bindings/reset/bcm63268-reset.h
deleted file mode 100644
index a45abed..0000000
--- a/include/dt-bindings/reset/bcm63268-reset.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
- *
- * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
- */
-
-#ifndef __DT_BINDINGS_RESET_BCM63268_H
-#define __DT_BINDINGS_RESET_BCM63268_H
-
-#define BCM63268_RST_SPI 0
-#define BCM63268_RST_IPSEC 1
-#define BCM63268_RST_EPHY 2
-#define BCM63268_RST_SAR 3
-#define BCM63268_RST_ENETSW 4
-#define BCM63268_RST_USBS 5
-#define BCM63268_RST_USBH 6
-#define BCM63268_RST_PCM 7
-#define BCM63268_RST_PCIE_CORE 8
-#define BCM63268_RST_PCIE 9
-#define BCM63268_RST_PCIE_EXT 10
-#define BCM63268_RST_WLAN_SHIM 11
-#define BCM63268_RST_DDR_PHY 12
-#define BCM63268_RST_FAP0 13
-#define BCM63268_RST_WLAN_UBUS 14
-#define BCM63268_RST_DECT 15
-#define BCM63268_RST_FAP1 16
-#define BCM63268_RST_PCIE_HARD 17
-#define BCM63268_RST_GPHY 18
-
-#endif /* __DT_BINDINGS_RESET_BCM63268_H */
diff --git a/include/dt-bindings/reset/bcm6328-reset.h b/include/dt-bindings/reset/bcm6328-reset.h
deleted file mode 100644
index f2dd4f7..0000000
--- a/include/dt-bindings/reset/bcm6328-reset.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
- *
- * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
- */
-
-#ifndef __DT_BINDINGS_RESET_BCM6328_H
-#define __DT_BINDINGS_RESET_BCM6328_H
-
-#define BCM6328_RST_SPI 0
-#define BCM6328_RST_EPHY 1
-#define BCM6328_RST_SAR 2
-#define BCM6328_RST_ENETSW 3
-#define BCM6328_RST_USBS 4
-#define BCM6328_RST_USBH 5
-#define BCM6328_RST_PCM 6
-#define BCM6328_RST_PCIE_CORE 7
-#define BCM6328_RST_PCIE 8
-#define BCM6328_RST_PCIE_EXT 9
-#define BCM6328_RST_PCIE_HARD 10
-
-#endif /* __DT_BINDINGS_RESET_BCM6328_H */
diff --git a/include/dt-bindings/reset/bcm6338-reset.h b/include/dt-bindings/reset/bcm6338-reset.h
deleted file mode 100644
index 4aec7a4..0000000
--- a/include/dt-bindings/reset/bcm6338-reset.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
- *
- * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
- */
-
-#ifndef __DT_BINDINGS_RESET_BCM6338_H
-#define __DT_BINDINGS_RESET_BCM6338_H
-
-#define BCM6338_RST_SPI 0
-#define BCM6338_RST_ENET 2
-#define BCM6338_RST_USBH 3
-#define BCM6338_RST_USBS 4
-#define BCM6338_RST_ADSL 5
-#define BCM6338_RST_DMAMEM 6
-#define BCM6338_RST_SAR 7
-#define BCM6338_RST_ACLC 8
-#define BCM6338_RST_ADSL_MIPS 10
-
-#endif /* __DT_BINDINGS_RESET_BCM6338_H */
diff --git a/include/dt-bindings/reset/bcm6348-reset.h b/include/dt-bindings/reset/bcm6348-reset.h
deleted file mode 100644
index b298c18..0000000
--- a/include/dt-bindings/reset/bcm6348-reset.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
- *
- * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
- */
-
-#ifndef __DT_BINDINGS_RESET_BCM6348_H
-#define __DT_BINDINGS_RESET_BCM6348_H
-
-#define BCM6348_RST_SPI 0
-#define BCM6348_RST_ENET 2
-#define BCM6348_RST_USBH 3
-#define BCM6348_RST_USBS 4
-#define BCM6348_RST_ADSL 5
-#define BCM6348_RST_DMAMEM 6
-#define BCM6348_RST_SAR 7
-#define BCM6348_RST_ACLC 8
-#define BCM6348_RST_ADSL_MIPS 10
-
-#endif /* __DT_BINDINGS_RESET_BCM6348_H */
diff --git a/include/dt-bindings/reset/bcm6358-reset.h b/include/dt-bindings/reset/bcm6358-reset.h
deleted file mode 100644
index 075706e..0000000
--- a/include/dt-bindings/reset/bcm6358-reset.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
- *
- * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
- */
-
-#ifndef __DT_BINDINGS_RESET_BCM6358_H
-#define __DT_BINDINGS_RESET_BCM6358_H
-
-#define BCM6358_RST_SPI 0
-#define BCM6358_RST_ENET 2
-#define BCM6358_RST_MPI 3
-#define BCM6358_RST_EPHY 6
-#define BCM6358_RST_SAR 7
-#define BCM6358_RST_USBH 12
-#define BCM6358_RST_PCM 13
-#define BCM6358_RST_ADSL 14
-
-#endif /* __DT_BINDINGS_RESET_BCM6358_H */
diff --git a/include/dt-bindings/reset/bcm6362-reset.h b/include/dt-bindings/reset/bcm6362-reset.h
deleted file mode 100644
index 8202e49..0000000
--- a/include/dt-bindings/reset/bcm6362-reset.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2018 Álvaro Fernández Rojas <noltari@gmail.com>
- *
- * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
- */
-
-#ifndef __DT_BINDINGS_RESET_BCM6362_H
-#define __DT_BINDINGS_RESET_BCM6362_H
-
-#define BCM6362_RST_SPI 0
-#define BCM6362_RST_IPSEC 1
-#define BCM6362_RST_EPHY 2
-#define BCM6362_RST_SAR 3
-#define BCM6362_RST_ENETSW 4
-#define BCM6362_RST_USBD 5
-#define BCM6362_RST_USBH 6
-#define BCM6362_RST_PCM 7
-#define BCM6362_RST_PCIE_CORE 8
-#define BCM6362_RST_PCIE 9
-#define BCM6362_RST_PCIE_EXT 10
-#define BCM6362_RST_WLAN_SHIM 11
-#define BCM6362_RST_DDR_PHY 12
-#define BCM6362_RST_FAP 13
-#define BCM6362_RST_WLAN_UBUS 14
-
-#endif /* __DT_BINDINGS_RESET_BCM6362_H */
diff --git a/include/dt-bindings/reset/bcm6368-reset.h b/include/dt-bindings/reset/bcm6368-reset.h
deleted file mode 100644
index 0038a7c..0000000
--- a/include/dt-bindings/reset/bcm6368-reset.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
- *
- * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
- */
-
-#ifndef __DT_BINDINGS_RESET_BCM6368_H
-#define __DT_BINDINGS_RESET_BCM6368_H
-
-#define BCM6368_RST_SPI 0
-#define BCM6368_RST_MPI 3
-#define BCM6368_RST_IPSEC 4
-#define BCM6368_RST_EPHY 6
-#define BCM6368_RST_SAR 7
-#define BCM6368_RST_SWITCH 10
-#define BCM6368_RST_USBD 11
-#define BCM6368_RST_USBH 12
-#define BCM6368_RST_PCM 13
-
-#endif /* __DT_BINDINGS_RESET_BCM6368_H */
diff --git a/include/dt-bindings/reset/g12a-aoclkc.h b/include/dt-bindings/reset/g12a-aoclkc.h
deleted file mode 100644
index bd2e233..0000000
--- a/include/dt-bindings/reset/g12a-aoclkc.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
-/*
- * Copyright (c) 2016 BayLibre, SAS
- * Author: Neil Armstrong <narmstrong@baylibre.com>
- */
-
-#ifndef DT_BINDINGS_RESET_AMLOGIC_MESON_G12A_AOCLK
-#define DT_BINDINGS_RESET_AMLOGIC_MESON_G12A_AOCLK
-
-#define RESET_AO_IR_IN 0
-#define RESET_AO_UART 1
-#define RESET_AO_I2C_M 2
-#define RESET_AO_I2C_S 3
-#define RESET_AO_SAR_ADC 4
-#define RESET_AO_UART2 5
-#define RESET_AO_IR_OUT 6
-
-#endif
diff --git a/include/dt-bindings/reset/gxbb-aoclkc.h b/include/dt-bindings/reset/gxbb-aoclkc.h
deleted file mode 100644
index 9e3fd60..0000000
--- a/include/dt-bindings/reset/gxbb-aoclkc.h
+++ /dev/null
@@ -1,66 +0,0 @@
-/*
- * This file is provided under a dual BSD/GPLv2 license. When using or
- * redistributing this file, you may do so under either license.
- *
- * GPL LICENSE SUMMARY
- *
- * Copyright (c) 2016 BayLibre, SAS.
- * Author: Neil Armstrong <narmstrong@baylibre.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of version 2 of the GNU General Public License as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- * General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, see <http://www.gnu.org/licenses/>.
- * The full GNU General Public License is included in this distribution
- * in the file called COPYING.
- *
- * BSD LICENSE
- *
- * Copyright (c) 2016 BayLibre, SAS.
- * Author: Neil Armstrong <narmstrong@baylibre.com>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * * Neither the name of Intel Corporation nor the names of its
- * contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef DT_BINDINGS_RESET_AMLOGIC_MESON_GXBB_AOCLK
-#define DT_BINDINGS_RESET_AMLOGIC_MESON_GXBB_AOCLK
-
-#define RESET_AO_REMOTE 0
-#define RESET_AO_I2C_MASTER 1
-#define RESET_AO_I2C_SLAVE 2
-#define RESET_AO_UART1 3
-#define RESET_AO_UART2 4
-#define RESET_AO_IR_BLASTER 5
-
-#endif
diff --git a/include/dt-bindings/reset/imx7-reset.h b/include/dt-bindings/reset/imx7-reset.h
deleted file mode 100644
index bb92452..0000000
--- a/include/dt-bindings/reset/imx7-reset.h
+++ /dev/null
@@ -1,52 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (C) 2017 Impinj, Inc.
- *
- * Author: Andrey Smirnov <andrew.smirnov@gmail.com>
- */
-
-#ifndef DT_BINDING_RESET_IMX7_H
-#define DT_BINDING_RESET_IMX7_H
-
-#define IMX7_RESET_A7_CORE_POR_RESET0 0
-#define IMX7_RESET_A7_CORE_POR_RESET1 1
-#define IMX7_RESET_A7_CORE_RESET0 2
-#define IMX7_RESET_A7_CORE_RESET1 3
-#define IMX7_RESET_A7_DBG_RESET0 4
-#define IMX7_RESET_A7_DBG_RESET1 5
-#define IMX7_RESET_A7_ETM_RESET0 6
-#define IMX7_RESET_A7_ETM_RESET1 7
-#define IMX7_RESET_A7_SOC_DBG_RESET 8
-#define IMX7_RESET_A7_L2RESET 9
-#define IMX7_RESET_SW_M4C_RST 10
-#define IMX7_RESET_SW_M4P_RST 11
-#define IMX7_RESET_EIM_RST 12
-#define IMX7_RESET_HSICPHY_PORT_RST 13
-#define IMX7_RESET_USBPHY1_POR 14
-#define IMX7_RESET_USBPHY1_PORT_RST 15
-#define IMX7_RESET_USBPHY2_POR 16
-#define IMX7_RESET_USBPHY2_PORT_RST 17
-#define IMX7_RESET_MIPI_PHY_MRST 18
-#define IMX7_RESET_MIPI_PHY_SRST 19
-
-/*
- * IMX7_RESET_PCIEPHY is a logical reset line combining PCIEPHY_BTN
- * and PCIEPHY_G_RST
- */
-#define IMX7_RESET_PCIEPHY 20
-#define IMX7_RESET_PCIEPHY_PERST 21
-
-/*
- * IMX7_RESET_PCIE_CTRL_APPS_EN is not strictly a reset line, but it
- * can be used to inhibit PCIe LTTSM, so, in a way, it can be thoguht
- * of as one
- */
-#define IMX7_RESET_PCIE_CTRL_APPS_EN 22
-#define IMX7_RESET_DDRC_PRST 23
-#define IMX7_RESET_DDRC_CORE_RST 24
-
-#define IMX7_RESET_PCIE_CTRL_APPS_TURNOFF 25
-
-#define IMX7_RESET_NUM 26
-
-#endif
diff --git a/include/dt-bindings/reset/imx8mq-reset.h b/include/dt-bindings/reset/imx8mq-reset.h
deleted file mode 100755
index 9a30108..0000000
--- a/include/dt-bindings/reset/imx8mq-reset.h
+++ /dev/null
@@ -1,64 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2018 Zodiac Inflight Innovations
- *
- * Author: Andrey Smirnov <andrew.smirnov@gmail.com>
- */
-
-#ifndef DT_BINDING_RESET_IMX8MQ_H
-#define DT_BINDING_RESET_IMX8MQ_H
-
-#define IMX8MQ_RESET_A53_CORE_POR_RESET0 0
-#define IMX8MQ_RESET_A53_CORE_POR_RESET1 1
-#define IMX8MQ_RESET_A53_CORE_POR_RESET2 2
-#define IMX8MQ_RESET_A53_CORE_POR_RESET3 3
-#define IMX8MQ_RESET_A53_CORE_RESET0 4
-#define IMX8MQ_RESET_A53_CORE_RESET1 5
-#define IMX8MQ_RESET_A53_CORE_RESET2 6
-#define IMX8MQ_RESET_A53_CORE_RESET3 7
-#define IMX8MQ_RESET_A53_DBG_RESET0 8
-#define IMX8MQ_RESET_A53_DBG_RESET1 9
-#define IMX8MQ_RESET_A53_DBG_RESET2 10
-#define IMX8MQ_RESET_A53_DBG_RESET3 11
-#define IMX8MQ_RESET_A53_ETM_RESET0 12
-#define IMX8MQ_RESET_A53_ETM_RESET1 13
-#define IMX8MQ_RESET_A53_ETM_RESET2 14
-#define IMX8MQ_RESET_A53_ETM_RESET3 15
-#define IMX8MQ_RESET_A53_SOC_DBG_RESET 16
-#define IMX8MQ_RESET_A53_L2RESET 17
-#define IMX8MQ_RESET_SW_NON_SCLR_M4C_RST 18
-#define IMX8MQ_RESET_OTG1_PHY_RESET 19
-#define IMX8MQ_RESET_OTG2_PHY_RESET 20
-#define IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N 21
-#define IMX8MQ_RESET_MIPI_DSI_RESET_N 22
-#define IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N 23
-#define IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N 24
-#define IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N 25
-#define IMX8MQ_RESET_PCIEPHY 26
-#define IMX8MQ_RESET_PCIEPHY_PERST 27
-#define IMX8MQ_RESET_PCIE_CTRL_APPS_EN 28
-#define IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF 29
-#define IMX8MQ_RESET_HDMI_PHY_APB_RESET 30 /* i.MX8MM does NOT support */
-#define IMX8MQ_RESET_DISP_RESET 31
-#define IMX8MQ_RESET_GPU_RESET 32
-#define IMX8MQ_RESET_VPU_RESET 33
-#define IMX8MQ_RESET_PCIEPHY2 34 /* i.MX8MM does NOT support */
-#define IMX8MQ_RESET_PCIEPHY2_PERST 35 /* i.MX8MM does NOT support */
-#define IMX8MQ_RESET_PCIE2_CTRL_APPS_EN 36 /* i.MX8MM does NOT support */
-#define IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF 37 /* i.MX8MM does NOT support */
-#define IMX8MQ_RESET_MIPI_CSI1_CORE_RESET 38 /* i.MX8MM does NOT support */
-#define IMX8MQ_RESET_MIPI_CSI1_PHY_REF_RESET 39 /* i.MX8MM does NOT support */
-#define IMX8MQ_RESET_MIPI_CSI1_ESC_RESET 40 /* i.MX8MM does NOT support */
-#define IMX8MQ_RESET_MIPI_CSI2_CORE_RESET 41 /* i.MX8MM does NOT support */
-#define IMX8MQ_RESET_MIPI_CSI2_PHY_REF_RESET 42 /* i.MX8MM does NOT support */
-#define IMX8MQ_RESET_MIPI_CSI2_ESC_RESET 43 /* i.MX8MM does NOT support */
-#define IMX8MQ_RESET_DDRC1_PRST 44
-#define IMX8MQ_RESET_DDRC1_CORE_RESET 45
-#define IMX8MQ_RESET_DDRC1_PHY_RESET 46
-#define IMX8MQ_RESET_DDRC2_PRST 47 /* i.MX8MM does NOT support */
-#define IMX8MQ_RESET_DDRC2_CORE_RESET 48 /* i.MX8MM does NOT support */
-#define IMX8MQ_RESET_DDRC2_PHY_RESET 49 /* i.MX8MM does NOT support */
-
-#define IMX8MQ_RESET_NUM 50
-
-#endif
diff --git a/include/dt-bindings/reset/mt7623-reset.h b/include/dt-bindings/reset/mt7623-reset.h
deleted file mode 100644
index a859a5b..0000000
--- a/include/dt-bindings/reset/mt7623-reset.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2018 MediaTek Inc.
- */
-
-#ifndef _DT_BINDINGS_MTK_RESET_H_
-#define _DT_BINDINGS_MTK_RESET_H_
-
-/* ETHSYS resets */
-#define ETHSYS_PPE_RST 31
-#define ETHSYS_GMAC_RST 23
-#define ETHSYS_FE_RST 6
-#define ETHSYS_MCM_RST 2
-#define ETHSYS_SYS_RST 0
-
-/* HIFSYS resets */
-#define HIFSYS_PCIE2_RST 26
-#define HIFSYS_PCIE1_RST 25
-#define HIFSYS_PCIE0_RST 24
-#define HIFSYS_UPHY1_RST 22
-#define HIFSYS_UPHY0_RST 21
-#define HIFSYS_UHOST1_RST 4
-#define HIFSYS_UHOST0_RST 3
-
-#endif /* _DT_BINDINGS_MTK_RESET_H_ */
diff --git a/include/dt-bindings/reset/mt7628-reset.h b/include/dt-bindings/reset/mt7628-reset.h
deleted file mode 100644
index 2a674c1..0000000
--- a/include/dt-bindings/reset/mt7628-reset.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2019 MediaTek Inc.
- *
- * Author: Weijie Gao <weijie.gao@mediatek.com>
- */
-
-#ifndef _DT_BINDINGS_MT7628_RESET_H_
-#define _DT_BINDINGS_MT7628_RESET_H_
-
-#define MT7628_PWM_RST 31
-#define MT7628_SDXC_RST 30
-#define MT7628_CRYPTO_RST 29
-#define MT7628_AUX_STCK_RST 28
-#define MT7628_PCIE_RST 26
-#define MT7628_EPHY_RST 24
-#define MT7628_ETH_RST 23
-#define MT7628_UPHY_RST 22
-#define MT7628_UART2_RST 20
-#define MT7628_UART1_RST 19
-#define MT7628_SPI_RST 18
-#define MT7628_I2S_RST 17
-#define MT7628_I2C_RST 16
-#define MT7628_GDMA_RST 14
-#define MT7628_PIO_RST 13
-#define MT7628_UART0_RST 12
-#define MT7628_PCM_RST 11
-#define MT7628_MC_RST 10
-#define MT7628_INT_RST 9
-#define MT7628_TIMER_RST 8
-#define MT7628_HIF_RST 5
-#define MT7628_WIFI_RST 4
-#define MT7628_SPIS_RST 3
-#define MT7628_SYS_RST 0
-
-#endif /* _DT_BINDINGS_MT7628_RESET_H_ */
diff --git a/include/dt-bindings/reset/mt7629-reset.h b/include/dt-bindings/reset/mt7629-reset.h
deleted file mode 100644
index 8f1634f..0000000
--- a/include/dt-bindings/reset/mt7629-reset.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2019 MediaTek Inc.
- */
-
-#ifndef _DT_BINDINGS_MTK_RESET_H_
-#define _DT_BINDINGS_MTK_RESET_H_
-
-/* PCIe Subsystem resets */
-#define PCIE1_CORE_RST 19
-#define PCIE1_MMIO_RST 20
-#define PCIE1_HRST 21
-#define PCIE1_USER_RST 22
-#define PCIE1_PIPE_RST 23
-#define PCIE0_CORE_RST 27
-#define PCIE0_MMIO_RST 28
-#define PCIE0_HRST 29
-#define PCIE0_USER_RST 30
-#define PCIE0_PIPE_RST 31
-
-/* SSUSB Subsystem resets */
-#define SSUSB_PHY_PWR_RST 3
-#define SSUSB_MAC_PWR_RST 4
-
-/* ETH Subsystem resets */
-#define ETHSYS_SYS_RST 0
-#define ETHSYS_MCM_RST 2
-#define ETHSYS_HSDMA_RST 5
-#define ETHSYS_FE_RST 6
-#define ETHSYS_ESW_RST 16
-#define ETHSYS_GMAC_RST 23
-#define ETHSYS_EPHY_RST 24
-#define ETHSYS_CRYPTO_RST 29
-#define ETHSYS_PPE_RST 31
-
-#endif /* _DT_BINDINGS_MTK_RESET_H_ */
diff --git a/include/dt-bindings/reset/stih407-resets.h b/include/dt-bindings/reset/stih407-resets.h
deleted file mode 100644
index 4ab3a1c..0000000
--- a/include/dt-bindings/reset/stih407-resets.h
+++ /dev/null
@@ -1,65 +0,0 @@
-/*
- * This header provides constants for the reset controller
- * based peripheral powerdown requests on the STMicroelectronics
- * STiH407 SoC.
- */
-#ifndef _DT_BINDINGS_RESET_CONTROLLER_STIH407
-#define _DT_BINDINGS_RESET_CONTROLLER_STIH407
-
-/* Powerdown requests control 0 */
-#define STIH407_EMISS_POWERDOWN 0
-#define STIH407_NAND_POWERDOWN 1
-
-/* Synp GMAC PowerDown */
-#define STIH407_ETH1_POWERDOWN 2
-
-/* Powerdown requests control 1 */
-#define STIH407_USB3_POWERDOWN 3
-#define STIH407_USB2_PORT1_POWERDOWN 4
-#define STIH407_USB2_PORT0_POWERDOWN 5
-#define STIH407_PCIE1_POWERDOWN 6
-#define STIH407_PCIE0_POWERDOWN 7
-#define STIH407_SATA1_POWERDOWN 8
-#define STIH407_SATA0_POWERDOWN 9
-
-/* Reset defines */
-#define STIH407_ETH1_SOFTRESET 0
-#define STIH407_MMC1_SOFTRESET 1
-#define STIH407_PICOPHY_SOFTRESET 2
-#define STIH407_IRB_SOFTRESET 3
-#define STIH407_PCIE0_SOFTRESET 4
-#define STIH407_PCIE1_SOFTRESET 5
-#define STIH407_SATA0_SOFTRESET 6
-#define STIH407_SATA1_SOFTRESET 7
-#define STIH407_MIPHY0_SOFTRESET 8
-#define STIH407_MIPHY1_SOFTRESET 9
-#define STIH407_MIPHY2_SOFTRESET 10
-#define STIH407_SATA0_PWR_SOFTRESET 11
-#define STIH407_SATA1_PWR_SOFTRESET 12
-#define STIH407_DELTA_SOFTRESET 13
-#define STIH407_BLITTER_SOFTRESET 14
-#define STIH407_HDTVOUT_SOFTRESET 15
-#define STIH407_HDQVDP_SOFTRESET 16
-#define STIH407_VDP_AUX_SOFTRESET 17
-#define STIH407_COMPO_SOFTRESET 18
-#define STIH407_HDMI_TX_PHY_SOFTRESET 19
-#define STIH407_JPEG_DEC_SOFTRESET 20
-#define STIH407_VP8_DEC_SOFTRESET 21
-#define STIH407_GPU_SOFTRESET 22
-#define STIH407_HVA_SOFTRESET 23
-#define STIH407_ERAM_HVA_SOFTRESET 24
-#define STIH407_LPM_SOFTRESET 25
-#define STIH407_KEYSCAN_SOFTRESET 26
-#define STIH407_USB2_PORT0_SOFTRESET 27
-#define STIH407_USB2_PORT1_SOFTRESET 28
-#define STIH407_ST231_AUD_SOFTRESET 29
-#define STIH407_ST231_DMU_SOFTRESET 30
-#define STIH407_ST231_GP0_SOFTRESET 31
-#define STIH407_ST231_GP1_SOFTRESET 32
-
-/* Picophy reset defines */
-#define STIH407_PICOPHY0_RESET 0
-#define STIH407_PICOPHY1_RESET 1
-#define STIH407_PICOPHY2_RESET 2
-
-#endif /* _DT_BINDINGS_RESET_CONTROLLER_STIH407 */
diff --git a/include/dt-bindings/reset/stm32mp1-resets.h b/include/dt-bindings/reset/stm32mp1-resets.h
deleted file mode 100644
index f0c3aae..0000000
--- a/include/dt-bindings/reset/stm32mp1-resets.h
+++ /dev/null
@@ -1,108 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */
-/*
- * Copyright (C) STMicroelectronics 2018 - All Rights Reserved
- * Author: Gabriel Fernandez <gabriel.fernandez@st.com> for STMicroelectronics.
- */
-
-#ifndef _DT_BINDINGS_STM32MP1_RESET_H_
-#define _DT_BINDINGS_STM32MP1_RESET_H_
-
-#define LTDC_R 3072
-#define DSI_R 3076
-#define DDRPERFM_R 3080
-#define USBPHY_R 3088
-#define SPI6_R 3136
-#define I2C4_R 3138
-#define I2C6_R 3139
-#define USART1_R 3140
-#define STGEN_R 3156
-#define GPIOZ_R 3200
-#define CRYP1_R 3204
-#define HASH1_R 3205
-#define RNG1_R 3206
-#define AXIM_R 3216
-#define GPU_R 3269
-#define ETHMAC_R 3274
-#define FMC_R 3276
-#define QSPI_R 3278
-#define SDMMC1_R 3280
-#define SDMMC2_R 3281
-#define CRC1_R 3284
-#define USBH_R 3288
-#define MDMA_R 3328
-#define MCU_R 8225
-#define TIM2_R 19456
-#define TIM3_R 19457
-#define TIM4_R 19458
-#define TIM5_R 19459
-#define TIM6_R 19460
-#define TIM7_R 19461
-#define TIM12_R 16462
-#define TIM13_R 16463
-#define TIM14_R 16464
-#define LPTIM1_R 19465
-#define SPI2_R 19467
-#define SPI3_R 19468
-#define USART2_R 19470
-#define USART3_R 19471
-#define UART4_R 19472
-#define UART5_R 19473
-#define UART7_R 19474
-#define UART8_R 19475
-#define I2C1_R 19477
-#define I2C2_R 19478
-#define I2C3_R 19479
-#define I2C5_R 19480
-#define SPDIF_R 19482
-#define CEC_R 19483
-#define DAC12_R 19485
-#define MDIO_R 19847
-#define TIM1_R 19520
-#define TIM8_R 19521
-#define TIM15_R 19522
-#define TIM16_R 19523
-#define TIM17_R 19524
-#define SPI1_R 19528
-#define SPI4_R 19529
-#define SPI5_R 19530
-#define USART6_R 19533
-#define SAI1_R 19536
-#define SAI2_R 19537
-#define SAI3_R 19538
-#define DFSDM_R 19540
-#define FDCAN_R 19544
-#define LPTIM2_R 19584
-#define LPTIM3_R 19585
-#define LPTIM4_R 19586
-#define LPTIM5_R 19587
-#define SAI4_R 19592
-#define SYSCFG_R 19595
-#define VREF_R 19597
-#define TMPSENS_R 19600
-#define PMBCTRL_R 19601
-#define DMA1_R 19648
-#define DMA2_R 19649
-#define DMAMUX_R 19650
-#define ADC12_R 19653
-#define USBO_R 19656
-#define SDMMC3_R 19664
-#define CAMITF_R 19712
-#define CRYP2_R 19716
-#define HASH2_R 19717
-#define RNG2_R 19718
-#define CRC2_R 19719
-#define HSEM_R 19723
-#define MBOX_R 19724
-#define GPIOA_R 19776
-#define GPIOB_R 19777
-#define GPIOC_R 19778
-#define GPIOD_R 19779
-#define GPIOE_R 19780
-#define GPIOF_R 19781
-#define GPIOG_R 19782
-#define GPIOH_R 19783
-#define GPIOI_R 19784
-#define GPIOJ_R 19785
-#define GPIOK_R 19786
-
-#endif /* _DT_BINDINGS_STM32MP1_RESET_H_ */
diff --git a/include/dt-bindings/reset/sun4i-a10-ccu.h b/include/dt-bindings/reset/sun4i-a10-ccu.h
deleted file mode 100644
index 5f4480b..0000000
--- a/include/dt-bindings/reset/sun4i-a10-ccu.h
+++ /dev/null
@@ -1,69 +0,0 @@
-/*
- * Copyright (C) 2017 Priit Laes <plaes@plaes.org>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef _DT_BINDINGS_RST_SUN4I_A10_H
-#define _DT_BINDINGS_RST_SUN4I_A10_H
-
-#define RST_USB_PHY0 1
-#define RST_USB_PHY1 2
-#define RST_USB_PHY2 3
-#define RST_GPS 4
-#define RST_DE_BE0 5
-#define RST_DE_BE1 6
-#define RST_DE_FE0 7
-#define RST_DE_FE1 8
-#define RST_DE_MP 9
-#define RST_TVE0 10
-#define RST_TCON0 11
-#define RST_TVE1 12
-#define RST_TCON1 13
-#define RST_CSI0 14
-#define RST_CSI1 15
-#define RST_VE 16
-#define RST_ACE 17
-#define RST_LVDS 18
-#define RST_GPU 19
-#define RST_HDMI_H 20
-#define RST_HDMI_SYS 21
-#define RST_HDMI_AUDIO_DMA 22
-
-#endif /* DT_BINDINGS_RST_SUN4I_A10_H */
diff --git a/include/dt-bindings/reset/sun50i-a64-ccu.h b/include/dt-bindings/reset/sun50i-a64-ccu.h
deleted file mode 100644
index db60b29..0000000
--- a/include/dt-bindings/reset/sun50i-a64-ccu.h
+++ /dev/null
@@ -1,98 +0,0 @@
-/*
- * Copyright (C) 2016 Maxime Ripard <maxime.ripard@free-electrons.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef _DT_BINDINGS_RST_SUN50I_A64_H_
-#define _DT_BINDINGS_RST_SUN50I_A64_H_
-
-#define RST_USB_PHY0 0
-#define RST_USB_PHY1 1
-#define RST_USB_HSIC 2
-#define RST_DRAM 3
-#define RST_MBUS 4
-#define RST_BUS_MIPI_DSI 5
-#define RST_BUS_CE 6
-#define RST_BUS_DMA 7
-#define RST_BUS_MMC0 8
-#define RST_BUS_MMC1 9
-#define RST_BUS_MMC2 10
-#define RST_BUS_NAND 11
-#define RST_BUS_DRAM 12
-#define RST_BUS_EMAC 13
-#define RST_BUS_TS 14
-#define RST_BUS_HSTIMER 15
-#define RST_BUS_SPI0 16
-#define RST_BUS_SPI1 17
-#define RST_BUS_OTG 18
-#define RST_BUS_EHCI0 19
-#define RST_BUS_EHCI1 20
-#define RST_BUS_OHCI0 21
-#define RST_BUS_OHCI1 22
-#define RST_BUS_VE 23
-#define RST_BUS_TCON0 24
-#define RST_BUS_TCON1 25
-#define RST_BUS_DEINTERLACE 26
-#define RST_BUS_CSI 27
-#define RST_BUS_HDMI0 28
-#define RST_BUS_HDMI1 29
-#define RST_BUS_DE 30
-#define RST_BUS_GPU 31
-#define RST_BUS_MSGBOX 32
-#define RST_BUS_SPINLOCK 33
-#define RST_BUS_DBG 34
-#define RST_BUS_LVDS 35
-#define RST_BUS_CODEC 36
-#define RST_BUS_SPDIF 37
-#define RST_BUS_THS 38
-#define RST_BUS_I2S0 39
-#define RST_BUS_I2S1 40
-#define RST_BUS_I2S2 41
-#define RST_BUS_I2C0 42
-#define RST_BUS_I2C1 43
-#define RST_BUS_I2C2 44
-#define RST_BUS_SCR 45
-#define RST_BUS_UART0 46
-#define RST_BUS_UART1 47
-#define RST_BUS_UART2 48
-#define RST_BUS_UART3 49
-#define RST_BUS_UART4 50
-
-#endif /* _DT_BINDINGS_RST_SUN50I_A64_H_ */
diff --git a/include/dt-bindings/reset/sun50i-h6-ccu.h b/include/dt-bindings/reset/sun50i-h6-ccu.h
deleted file mode 100644
index 81106f4..0000000
--- a/include/dt-bindings/reset/sun50i-h6-ccu.h
+++ /dev/null
@@ -1,73 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ or MIT)
-/*
- * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
- */
-
-#ifndef _DT_BINDINGS_RESET_SUN50I_H6_H_
-#define _DT_BINDINGS_RESET_SUN50I_H6_H_
-
-#define RST_MBUS 0
-#define RST_BUS_DE 1
-#define RST_BUS_DEINTERLACE 2
-#define RST_BUS_GPU 3
-#define RST_BUS_CE 4
-#define RST_BUS_VE 5
-#define RST_BUS_EMCE 6
-#define RST_BUS_VP9 7
-#define RST_BUS_DMA 8
-#define RST_BUS_MSGBOX 9
-#define RST_BUS_SPINLOCK 10
-#define RST_BUS_HSTIMER 11
-#define RST_BUS_DBG 12
-#define RST_BUS_PSI 13
-#define RST_BUS_PWM 14
-#define RST_BUS_IOMMU 15
-#define RST_BUS_DRAM 16
-#define RST_BUS_NAND 17
-#define RST_BUS_MMC0 18
-#define RST_BUS_MMC1 19
-#define RST_BUS_MMC2 20
-#define RST_BUS_UART0 21
-#define RST_BUS_UART1 22
-#define RST_BUS_UART2 23
-#define RST_BUS_UART3 24
-#define RST_BUS_I2C0 25
-#define RST_BUS_I2C1 26
-#define RST_BUS_I2C2 27
-#define RST_BUS_I2C3 28
-#define RST_BUS_SCR0 29
-#define RST_BUS_SCR1 30
-#define RST_BUS_SPI0 31
-#define RST_BUS_SPI1 32
-#define RST_BUS_EMAC 33
-#define RST_BUS_TS 34
-#define RST_BUS_IR_TX 35
-#define RST_BUS_THS 36
-#define RST_BUS_I2S0 37
-#define RST_BUS_I2S1 38
-#define RST_BUS_I2S2 39
-#define RST_BUS_I2S3 40
-#define RST_BUS_SPDIF 41
-#define RST_BUS_DMIC 42
-#define RST_BUS_AUDIO_HUB 43
-#define RST_USB_PHY0 44
-#define RST_USB_PHY1 45
-#define RST_USB_PHY3 46
-#define RST_USB_HSIC 47
-#define RST_BUS_OHCI0 48
-#define RST_BUS_OHCI3 49
-#define RST_BUS_EHCI0 50
-#define RST_BUS_XHCI 51
-#define RST_BUS_EHCI3 52
-#define RST_BUS_OTG 53
-#define RST_BUS_PCIE 54
-#define RST_PCIE_POWERUP 55
-#define RST_BUS_HDMI 56
-#define RST_BUS_HDMI_SUB 57
-#define RST_BUS_TCON_TOP 58
-#define RST_BUS_TCON_LCD0 59
-#define RST_BUS_TCON_TV0 60
-#define RST_BUS_CSI 61
-#define RST_BUS_HDCP 62
-
-#endif /* _DT_BINDINGS_RESET_SUN50I_H6_H_ */
diff --git a/include/dt-bindings/reset/sun50i-h6-r-ccu.h b/include/dt-bindings/reset/sun50i-h6-r-ccu.h
deleted file mode 100644
index 01c84db..0000000
--- a/include/dt-bindings/reset/sun50i-h6-r-ccu.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
-/*
- * Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.xyz>
- */
-
-#ifndef _DT_BINDINGS_RST_SUN50I_H6_R_CCU_H_
-#define _DT_BINDINGS_RST_SUN50I_H6_R_CCU_H_
-
-#define RST_R_APB1_TIMER 0
-#define RST_R_APB1_TWD 1
-#define RST_R_APB1_PWM 2
-#define RST_R_APB2_UART 3
-#define RST_R_APB2_I2C 4
-#define RST_R_APB1_IR 5
-#define RST_R_APB1_W1 6
-
-#endif /* _DT_BINDINGS_RST_SUN50I_H6_R_CCU_H_ */
diff --git a/include/dt-bindings/reset/sun5i-ccu.h b/include/dt-bindings/reset/sun5i-ccu.h
deleted file mode 100644
index c2b9726..0000000
--- a/include/dt-bindings/reset/sun5i-ccu.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * Copyright 2016 Maxime Ripard
- *
- * Maxime Ripard <maxime.ripard@free-electrons.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef _RST_SUN5I_H_
-#define _RST_SUN5I_H_
-
-#define RST_USB_PHY0 0
-#define RST_USB_PHY1 1
-#define RST_GPS 2
-#define RST_DE_BE 3
-#define RST_DE_FE 4
-#define RST_TVE 5
-#define RST_LCD 6
-#define RST_CSI 7
-#define RST_VE 8
-#define RST_GPU 9
-#define RST_IEP 10
-
-#endif /* _RST_SUN5I_H_ */
diff --git a/include/dt-bindings/reset/sun6i-a31-ccu.h b/include/dt-bindings/reset/sun6i-a31-ccu.h
deleted file mode 100644
index fbff365..0000000
--- a/include/dt-bindings/reset/sun6i-a31-ccu.h
+++ /dev/null
@@ -1,106 +0,0 @@
-/*
- * Copyright (C) 2016 Chen-Yu Tsai <wens@csie.org>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef _DT_BINDINGS_RST_SUN6I_A31_H_
-#define _DT_BINDINGS_RST_SUN6I_A31_H_
-
-#define RST_USB_PHY0 0
-#define RST_USB_PHY1 1
-#define RST_USB_PHY2 2
-
-#define RST_AHB1_MIPI_DSI 3
-#define RST_AHB1_SS 4
-#define RST_AHB1_DMA 5
-#define RST_AHB1_MMC0 6
-#define RST_AHB1_MMC1 7
-#define RST_AHB1_MMC2 8
-#define RST_AHB1_MMC3 9
-#define RST_AHB1_NAND1 10
-#define RST_AHB1_NAND0 11
-#define RST_AHB1_SDRAM 12
-#define RST_AHB1_EMAC 13
-#define RST_AHB1_TS 14
-#define RST_AHB1_HSTIMER 15
-#define RST_AHB1_SPI0 16
-#define RST_AHB1_SPI1 17
-#define RST_AHB1_SPI2 18
-#define RST_AHB1_SPI3 19
-#define RST_AHB1_OTG 20
-#define RST_AHB1_EHCI0 21
-#define RST_AHB1_EHCI1 22
-#define RST_AHB1_OHCI0 23
-#define RST_AHB1_OHCI1 24
-#define RST_AHB1_OHCI2 25
-#define RST_AHB1_VE 26
-#define RST_AHB1_LCD0 27
-#define RST_AHB1_LCD1 28
-#define RST_AHB1_CSI 29
-#define RST_AHB1_HDMI 30
-#define RST_AHB1_BE0 31
-#define RST_AHB1_BE1 32
-#define RST_AHB1_FE0 33
-#define RST_AHB1_FE1 34
-#define RST_AHB1_MP 35
-#define RST_AHB1_GPU 36
-#define RST_AHB1_DEU0 37
-#define RST_AHB1_DEU1 38
-#define RST_AHB1_DRC0 39
-#define RST_AHB1_DRC1 40
-#define RST_AHB1_LVDS 41
-
-#define RST_APB1_CODEC 42
-#define RST_APB1_SPDIF 43
-#define RST_APB1_DIGITAL_MIC 44
-#define RST_APB1_DAUDIO0 45
-#define RST_APB1_DAUDIO1 46
-#define RST_APB2_I2C0 47
-#define RST_APB2_I2C1 48
-#define RST_APB2_I2C2 49
-#define RST_APB2_I2C3 50
-#define RST_APB2_UART0 51
-#define RST_APB2_UART1 52
-#define RST_APB2_UART2 53
-#define RST_APB2_UART3 54
-#define RST_APB2_UART4 55
-#define RST_APB2_UART5 56
-
-#endif /* _DT_BINDINGS_RST_SUN6I_A31_H_ */
diff --git a/include/dt-bindings/reset/sun8i-a23-a33-ccu.h b/include/dt-bindings/reset/sun8i-a23-a33-ccu.h
deleted file mode 100644
index 6121f2b..0000000
--- a/include/dt-bindings/reset/sun8i-a23-a33-ccu.h
+++ /dev/null
@@ -1,87 +0,0 @@
-/*
- * Copyright (C) 2016 Maxime Ripard <maxime.ripard@free-electrons.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef _DT_BINDINGS_RST_SUN8I_A23_A33_H_
-#define _DT_BINDINGS_RST_SUN8I_A23_A33_H_
-
-#define RST_USB_PHY0 0
-#define RST_USB_PHY1 1
-#define RST_USB_HSIC 2
-#define RST_MBUS 3
-#define RST_BUS_MIPI_DSI 4
-#define RST_BUS_SS 5
-#define RST_BUS_DMA 6
-#define RST_BUS_MMC0 7
-#define RST_BUS_MMC1 8
-#define RST_BUS_MMC2 9
-#define RST_BUS_NAND 10
-#define RST_BUS_DRAM 11
-#define RST_BUS_HSTIMER 12
-#define RST_BUS_SPI0 13
-#define RST_BUS_SPI1 14
-#define RST_BUS_OTG 15
-#define RST_BUS_EHCI 16
-#define RST_BUS_OHCI 17
-#define RST_BUS_VE 18
-#define RST_BUS_LCD 19
-#define RST_BUS_CSI 20
-#define RST_BUS_DE_BE 21
-#define RST_BUS_DE_FE 22
-#define RST_BUS_GPU 23
-#define RST_BUS_MSGBOX 24
-#define RST_BUS_SPINLOCK 25
-#define RST_BUS_DRC 26
-#define RST_BUS_SAT 27
-#define RST_BUS_LVDS 28
-#define RST_BUS_CODEC 29
-#define RST_BUS_I2S0 30
-#define RST_BUS_I2S1 31
-#define RST_BUS_I2C0 32
-#define RST_BUS_I2C1 33
-#define RST_BUS_I2C2 34
-#define RST_BUS_UART0 35
-#define RST_BUS_UART1 36
-#define RST_BUS_UART2 37
-#define RST_BUS_UART3 38
-#define RST_BUS_UART4 39
-
-#endif /* _DT_BINDINGS_RST_SUN8I_A23_A33_H_ */
diff --git a/include/dt-bindings/reset/sun8i-a83t-ccu.h b/include/dt-bindings/reset/sun8i-a83t-ccu.h
deleted file mode 100644
index 784f6e1..0000000
--- a/include/dt-bindings/reset/sun8i-a83t-ccu.h
+++ /dev/null
@@ -1,98 +0,0 @@
-/*
- * Copyright (C) 2017 Chen-Yu Tsai <wens@csie.org>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef _DT_BINDINGS_RESET_SUN8I_A83T_CCU_H_
-#define _DT_BINDINGS_RESET_SUN8I_A83T_CCU_H_
-
-#define RST_USB_PHY0 0
-#define RST_USB_PHY1 1
-#define RST_USB_HSIC 2
-
-#define RST_DRAM 3
-#define RST_MBUS 4
-
-#define RST_BUS_MIPI_DSI 5
-#define RST_BUS_SS 6
-#define RST_BUS_DMA 7
-#define RST_BUS_MMC0 8
-#define RST_BUS_MMC1 9
-#define RST_BUS_MMC2 10
-#define RST_BUS_NAND 11
-#define RST_BUS_DRAM 12
-#define RST_BUS_EMAC 13
-#define RST_BUS_HSTIMER 14
-#define RST_BUS_SPI0 15
-#define RST_BUS_SPI1 16
-#define RST_BUS_OTG 17
-#define RST_BUS_EHCI0 18
-#define RST_BUS_EHCI1 19
-#define RST_BUS_OHCI0 20
-
-#define RST_BUS_VE 21
-#define RST_BUS_TCON0 22
-#define RST_BUS_TCON1 23
-#define RST_BUS_CSI 24
-#define RST_BUS_HDMI0 25
-#define RST_BUS_HDMI1 26
-#define RST_BUS_DE 27
-#define RST_BUS_GPU 28
-#define RST_BUS_MSGBOX 29
-#define RST_BUS_SPINLOCK 30
-
-#define RST_BUS_LVDS 31
-
-#define RST_BUS_SPDIF 32
-#define RST_BUS_I2S0 33
-#define RST_BUS_I2S1 34
-#define RST_BUS_I2S2 35
-#define RST_BUS_TDM 36
-
-#define RST_BUS_I2C0 37
-#define RST_BUS_I2C1 38
-#define RST_BUS_I2C2 39
-#define RST_BUS_UART0 40
-#define RST_BUS_UART1 41
-#define RST_BUS_UART2 42
-#define RST_BUS_UART3 43
-#define RST_BUS_UART4 44
-
-#endif /* _DT_BINDINGS_RESET_SUN8I_A83T_CCU_H_ */
diff --git a/include/dt-bindings/reset/sun8i-de2.h b/include/dt-bindings/reset/sun8i-de2.h
deleted file mode 100644
index 9526017..0000000
--- a/include/dt-bindings/reset/sun8i-de2.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.io>
- *
- * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- */
-
-#ifndef _DT_BINDINGS_RESET_SUN8I_DE2_H_
-#define _DT_BINDINGS_RESET_SUN8I_DE2_H_
-
-#define RST_MIXER0 0
-#define RST_MIXER1 1
-#define RST_WB 2
-
-#endif /* _DT_BINDINGS_RESET_SUN8I_DE2_H_ */
diff --git a/include/dt-bindings/reset/sun8i-h3-ccu.h b/include/dt-bindings/reset/sun8i-h3-ccu.h
deleted file mode 100644
index 6b7af80..0000000
--- a/include/dt-bindings/reset/sun8i-h3-ccu.h
+++ /dev/null
@@ -1,103 +0,0 @@
-/*
- * Copyright (C) 2016 Maxime Ripard <maxime.ripard@free-electrons.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef _DT_BINDINGS_RST_SUN8I_H3_H_
-#define _DT_BINDINGS_RST_SUN8I_H3_H_
-
-#define RST_USB_PHY0 0
-#define RST_USB_PHY1 1
-#define RST_USB_PHY2 2
-#define RST_USB_PHY3 3
-
-#define RST_MBUS 4
-
-#define RST_BUS_CE 5
-#define RST_BUS_DMA 6
-#define RST_BUS_MMC0 7
-#define RST_BUS_MMC1 8
-#define RST_BUS_MMC2 9
-#define RST_BUS_NAND 10
-#define RST_BUS_DRAM 11
-#define RST_BUS_EMAC 12
-#define RST_BUS_TS 13
-#define RST_BUS_HSTIMER 14
-#define RST_BUS_SPI0 15
-#define RST_BUS_SPI1 16
-#define RST_BUS_OTG 17
-#define RST_BUS_EHCI0 18
-#define RST_BUS_EHCI1 19
-#define RST_BUS_EHCI2 20
-#define RST_BUS_EHCI3 21
-#define RST_BUS_OHCI0 22
-#define RST_BUS_OHCI1 23
-#define RST_BUS_OHCI2 24
-#define RST_BUS_OHCI3 25
-#define RST_BUS_VE 26
-#define RST_BUS_TCON0 27
-#define RST_BUS_TCON1 28
-#define RST_BUS_DEINTERLACE 29
-#define RST_BUS_CSI 30
-#define RST_BUS_TVE 31
-#define RST_BUS_HDMI0 32
-#define RST_BUS_HDMI1 33
-#define RST_BUS_DE 34
-#define RST_BUS_GPU 35
-#define RST_BUS_MSGBOX 36
-#define RST_BUS_SPINLOCK 37
-#define RST_BUS_DBG 38
-#define RST_BUS_EPHY 39
-#define RST_BUS_CODEC 40
-#define RST_BUS_SPDIF 41
-#define RST_BUS_THS 42
-#define RST_BUS_I2S0 43
-#define RST_BUS_I2S1 44
-#define RST_BUS_I2S2 45
-#define RST_BUS_I2C0 46
-#define RST_BUS_I2C1 47
-#define RST_BUS_I2C2 48
-#define RST_BUS_UART0 49
-#define RST_BUS_UART1 50
-#define RST_BUS_UART2 51
-#define RST_BUS_UART3 52
-#define RST_BUS_SCR 53
-
-#endif /* _DT_BINDINGS_RST_SUN8I_H3_H_ */
diff --git a/include/dt-bindings/reset/sun8i-r-ccu.h b/include/dt-bindings/reset/sun8i-r-ccu.h
deleted file mode 100644
index 4ba64f3..0000000
--- a/include/dt-bindings/reset/sun8i-r-ccu.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.xyz>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef _DT_BINDINGS_RST_SUN8I_R_CCU_H_
-#define _DT_BINDINGS_RST_SUN8I_R_CCU_H_
-
-#define RST_APB0_IR 0
-#define RST_APB0_TIMER 1
-#define RST_APB0_RSB 2
-#define RST_APB0_UART 3
-/* 4 is reserved for RST_APB0_W1 on A31 */
-#define RST_APB0_I2C 5
-
-#endif /* _DT_BINDINGS_RST_SUN8I_R_CCU_H_ */
diff --git a/include/dt-bindings/reset/sun8i-r40-ccu.h b/include/dt-bindings/reset/sun8i-r40-ccu.h
deleted file mode 100644
index c5ebcf6..0000000
--- a/include/dt-bindings/reset/sun8i-r40-ccu.h
+++ /dev/null
@@ -1,130 +0,0 @@
-/*
- * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef _DT_BINDINGS_RST_SUN8I_R40_H_
-#define _DT_BINDINGS_RST_SUN8I_R40_H_
-
-#define RST_USB_PHY0 0
-#define RST_USB_PHY1 1
-#define RST_USB_PHY2 2
-
-#define RST_DRAM 3
-#define RST_MBUS 4
-
-#define RST_BUS_MIPI_DSI 5
-#define RST_BUS_CE 6
-#define RST_BUS_DMA 7
-#define RST_BUS_MMC0 8
-#define RST_BUS_MMC1 9
-#define RST_BUS_MMC2 10
-#define RST_BUS_MMC3 11
-#define RST_BUS_NAND 12
-#define RST_BUS_DRAM 13
-#define RST_BUS_EMAC 14
-#define RST_BUS_TS 15
-#define RST_BUS_HSTIMER 16
-#define RST_BUS_SPI0 17
-#define RST_BUS_SPI1 18
-#define RST_BUS_SPI2 19
-#define RST_BUS_SPI3 20
-#define RST_BUS_SATA 21
-#define RST_BUS_OTG 22
-#define RST_BUS_EHCI0 23
-#define RST_BUS_EHCI1 24
-#define RST_BUS_EHCI2 25
-#define RST_BUS_OHCI0 26
-#define RST_BUS_OHCI1 27
-#define RST_BUS_OHCI2 28
-#define RST_BUS_VE 29
-#define RST_BUS_MP 30
-#define RST_BUS_DEINTERLACE 31
-#define RST_BUS_CSI0 32
-#define RST_BUS_CSI1 33
-#define RST_BUS_HDMI0 34
-#define RST_BUS_HDMI1 35
-#define RST_BUS_DE 36
-#define RST_BUS_TVE0 37
-#define RST_BUS_TVE1 38
-#define RST_BUS_TVE_TOP 39
-#define RST_BUS_GMAC 40
-#define RST_BUS_GPU 41
-#define RST_BUS_TVD0 42
-#define RST_BUS_TVD1 43
-#define RST_BUS_TVD2 44
-#define RST_BUS_TVD3 45
-#define RST_BUS_TVD_TOP 46
-#define RST_BUS_TCON_LCD0 47
-#define RST_BUS_TCON_LCD1 48
-#define RST_BUS_TCON_TV0 49
-#define RST_BUS_TCON_TV1 50
-#define RST_BUS_TCON_TOP 51
-#define RST_BUS_DBG 52
-#define RST_BUS_LVDS 53
-#define RST_BUS_CODEC 54
-#define RST_BUS_SPDIF 55
-#define RST_BUS_AC97 56
-#define RST_BUS_IR0 57
-#define RST_BUS_IR1 58
-#define RST_BUS_THS 59
-#define RST_BUS_KEYPAD 60
-#define RST_BUS_I2S0 61
-#define RST_BUS_I2S1 62
-#define RST_BUS_I2S2 63
-#define RST_BUS_I2C0 64
-#define RST_BUS_I2C1 65
-#define RST_BUS_I2C2 66
-#define RST_BUS_I2C3 67
-#define RST_BUS_CAN 68
-#define RST_BUS_SCR 69
-#define RST_BUS_PS20 70
-#define RST_BUS_PS21 71
-#define RST_BUS_I2C4 72
-#define RST_BUS_UART0 73
-#define RST_BUS_UART1 74
-#define RST_BUS_UART2 75
-#define RST_BUS_UART3 76
-#define RST_BUS_UART4 77
-#define RST_BUS_UART5 78
-#define RST_BUS_UART6 79
-#define RST_BUS_UART7 80
-
-#endif /* _DT_BINDINGS_RST_SUN8I_R40_H_ */
diff --git a/include/dt-bindings/reset/sun8i-v3s-ccu.h b/include/dt-bindings/reset/sun8i-v3s-ccu.h
deleted file mode 100644
index b58ef21..0000000
--- a/include/dt-bindings/reset/sun8i-v3s-ccu.h
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- * Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.xyz>
- *
- * Based on sun8i-v3s-ccu.h, which is
- * Copyright (C) 2016 Maxime Ripard <maxime.ripard@free-electrons.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef _DT_BINDINGS_RST_SUN8I_V3S_H_
-#define _DT_BINDINGS_RST_SUN8I_V3S_H_
-
-#define RST_USB_PHY0 0
-
-#define RST_MBUS 1
-
-#define RST_BUS_CE 5
-#define RST_BUS_DMA 6
-#define RST_BUS_MMC0 7
-#define RST_BUS_MMC1 8
-#define RST_BUS_MMC2 9
-#define RST_BUS_DRAM 11
-#define RST_BUS_EMAC 12
-#define RST_BUS_HSTIMER 14
-#define RST_BUS_SPI0 15
-#define RST_BUS_OTG 17
-#define RST_BUS_EHCI0 18
-#define RST_BUS_OHCI0 22
-#define RST_BUS_VE 26
-#define RST_BUS_TCON0 27
-#define RST_BUS_CSI 30
-#define RST_BUS_DE 34
-#define RST_BUS_DBG 38
-#define RST_BUS_EPHY 39
-#define RST_BUS_CODEC 40
-#define RST_BUS_I2C0 46
-#define RST_BUS_I2C1 47
-#define RST_BUS_UART0 49
-#define RST_BUS_UART1 50
-#define RST_BUS_UART2 51
-
-#endif /* _DT_BINDINGS_RST_SUN8I_H3_H_ */
diff --git a/include/dt-bindings/reset/sun9i-a80-ccu.h b/include/dt-bindings/reset/sun9i-a80-ccu.h
deleted file mode 100644
index 4b8df4b..0000000
--- a/include/dt-bindings/reset/sun9i-a80-ccu.h
+++ /dev/null
@@ -1,102 +0,0 @@
-/*
- * Copyright (C) 2016 Chen-Yu Tsai <wens@csie.org>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef _DT_BINDINGS_RESET_SUN9I_A80_CCU_H_
-#define _DT_BINDINGS_RESET_SUN9I_A80_CCU_H_
-
-#define RST_BUS_FD 0
-#define RST_BUS_VE 1
-#define RST_BUS_GPU_CTRL 2
-#define RST_BUS_SS 3
-#define RST_BUS_MMC 4
-#define RST_BUS_NAND0 5
-#define RST_BUS_NAND1 6
-#define RST_BUS_SDRAM 7
-#define RST_BUS_SATA 8
-#define RST_BUS_TS 9
-#define RST_BUS_SPI0 10
-#define RST_BUS_SPI1 11
-#define RST_BUS_SPI2 12
-#define RST_BUS_SPI3 13
-
-#define RST_BUS_OTG 14
-#define RST_BUS_OTG_PHY 15
-#define RST_BUS_MIPI_HSI 16
-#define RST_BUS_GMAC 17
-#define RST_BUS_MSGBOX 18
-#define RST_BUS_SPINLOCK 19
-#define RST_BUS_HSTIMER 20
-#define RST_BUS_DMA 21
-
-#define RST_BUS_LCD0 22
-#define RST_BUS_LCD1 23
-#define RST_BUS_EDP 24
-#define RST_BUS_LVDS 25
-#define RST_BUS_CSI 26
-#define RST_BUS_HDMI0 27
-#define RST_BUS_HDMI1 28
-#define RST_BUS_DE 29
-#define RST_BUS_MP 30
-#define RST_BUS_GPU 31
-#define RST_BUS_MIPI_DSI 32
-
-#define RST_BUS_SPDIF 33
-#define RST_BUS_AC97 34
-#define RST_BUS_I2S0 35
-#define RST_BUS_I2S1 36
-#define RST_BUS_LRADC 37
-#define RST_BUS_GPADC 38
-#define RST_BUS_CIR_TX 39
-
-#define RST_BUS_I2C0 40
-#define RST_BUS_I2C1 41
-#define RST_BUS_I2C2 42
-#define RST_BUS_I2C3 43
-#define RST_BUS_I2C4 44
-#define RST_BUS_UART0 45
-#define RST_BUS_UART1 46
-#define RST_BUS_UART2 47
-#define RST_BUS_UART3 48
-#define RST_BUS_UART4 49
-#define RST_BUS_UART5 50
-
-#endif /* _DT_BINDINGS_RESET_SUN9I_A80_CCU_H_ */
diff --git a/include/dt-bindings/reset/sun9i-a80-de.h b/include/dt-bindings/reset/sun9i-a80-de.h
deleted file mode 100644
index 2050727..0000000
--- a/include/dt-bindings/reset/sun9i-a80-de.h
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- * Copyright (C) 2016 Chen-Yu Tsai <wens@csie.org>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef _DT_BINDINGS_RESET_SUN9I_A80_DE_H_
-#define _DT_BINDINGS_RESET_SUN9I_A80_DE_H_
-
-#define RST_FE0 0
-#define RST_FE1 1
-#define RST_FE2 2
-#define RST_DEU0 3
-#define RST_DEU1 4
-#define RST_BE0 5
-#define RST_BE1 6
-#define RST_BE2 7
-#define RST_DRC0 8
-#define RST_DRC1 9
-#define RST_MERGE 10
-
-#endif /* _DT_BINDINGS_RESET_SUN9I_A80_DE_H_ */
diff --git a/include/dt-bindings/reset/sun9i-a80-usb.h b/include/dt-bindings/reset/sun9i-a80-usb.h
deleted file mode 100644
index ee49286..0000000
--- a/include/dt-bindings/reset/sun9i-a80-usb.h
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
- * Copyright (C) 2016 Chen-Yu Tsai <wens@csie.org>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef _DT_BINDINGS_RESET_SUN9I_A80_USB_H_
-#define _DT_BINDINGS_RESET_SUN9I_A80_USB_H_
-
-#define RST_USB0_HCI 0
-#define RST_USB1_HCI 1
-#define RST_USB2_HCI 2
-
-#define RST_USB0_PHY 3
-#define RST_USB1_HSIC 4
-#define RST_USB1_PHY 5
-#define RST_USB2_HSIC 6
-#define RST_USB2_PHY 7
-
-#endif /* _DT_BINDINGS_RESET_SUN9I_A80_USB_H_ */
diff --git a/include/dt-bindings/reset/tegra124-car.h b/include/dt-bindings/reset/tegra124-car.h
deleted file mode 100644
index 070e4f6..0000000
--- a/include/dt-bindings/reset/tegra124-car.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/*
- * This header provides Tegra124-specific constants for binding
- * nvidia,tegra124-car.
- */
-
-#ifndef _DT_BINDINGS_RESET_TEGRA124_CAR_H
-#define _DT_BINDINGS_RESET_TEGRA124_CAR_H
-
-#define TEGRA124_RESET(x) (6 * 32 + (x))
-#define TEGRA124_RST_DFLL_DVCO TEGRA124_RESET(0)
-
-#endif /* _DT_BINDINGS_RESET_TEGRA124_CAR_H */
diff --git a/include/dt-bindings/reset/tegra186-reset.h b/include/dt-bindings/reset/tegra186-reset.h
deleted file mode 100644
index 7efec92..0000000
--- a/include/dt-bindings/reset/tegra186-reset.h
+++ /dev/null
@@ -1,205 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (c) 2015, NVIDIA CORPORATION.
- */
-
-#ifndef _ABI_MACH_T186_RESET_T186_H_
-#define _ABI_MACH_T186_RESET_T186_H_
-
-#define TEGRA186_RESET_ACTMON 0
-#define TEGRA186_RESET_AFI 1
-#define TEGRA186_RESET_CEC 2
-#define TEGRA186_RESET_CSITE 3
-#define TEGRA186_RESET_DP2 4
-#define TEGRA186_RESET_DPAUX 5
-#define TEGRA186_RESET_DSI 6
-#define TEGRA186_RESET_DSIB 7
-#define TEGRA186_RESET_DTV 8
-#define TEGRA186_RESET_DVFS 9
-#define TEGRA186_RESET_ENTROPY 10
-#define TEGRA186_RESET_EXTPERIPH1 11
-#define TEGRA186_RESET_EXTPERIPH2 12
-#define TEGRA186_RESET_EXTPERIPH3 13
-#define TEGRA186_RESET_GPU 14
-#define TEGRA186_RESET_HDA 15
-#define TEGRA186_RESET_HDA2CODEC_2X 16
-#define TEGRA186_RESET_HDA2HDMICODEC 17
-#define TEGRA186_RESET_HOST1X 18
-#define TEGRA186_RESET_I2C1 19
-#define TEGRA186_RESET_I2C2 20
-#define TEGRA186_RESET_I2C3 21
-#define TEGRA186_RESET_I2C4 22
-#define TEGRA186_RESET_I2C5 23
-#define TEGRA186_RESET_I2C6 24
-#define TEGRA186_RESET_ISP 25
-#define TEGRA186_RESET_KFUSE 26
-#define TEGRA186_RESET_LA 27
-#define TEGRA186_RESET_MIPI_CAL 28
-#define TEGRA186_RESET_PCIE 29
-#define TEGRA186_RESET_PCIEXCLK 30
-#define TEGRA186_RESET_SATA 31
-#define TEGRA186_RESET_SATACOLD 32
-#define TEGRA186_RESET_SDMMC1 33
-#define TEGRA186_RESET_SDMMC2 34
-#define TEGRA186_RESET_SDMMC3 35
-#define TEGRA186_RESET_SDMMC4 36
-#define TEGRA186_RESET_SE 37
-#define TEGRA186_RESET_SOC_THERM 38
-#define TEGRA186_RESET_SOR0 39
-#define TEGRA186_RESET_SPI1 40
-#define TEGRA186_RESET_SPI2 41
-#define TEGRA186_RESET_SPI3 42
-#define TEGRA186_RESET_SPI4 43
-#define TEGRA186_RESET_TMR 44
-#define TEGRA186_RESET_TRIG_SYS 45
-#define TEGRA186_RESET_TSEC 46
-#define TEGRA186_RESET_UARTA 47
-#define TEGRA186_RESET_UARTB 48
-#define TEGRA186_RESET_UARTC 49
-#define TEGRA186_RESET_UARTD 50
-#define TEGRA186_RESET_VI 51
-#define TEGRA186_RESET_VIC 52
-#define TEGRA186_RESET_XUSB_DEV 53
-#define TEGRA186_RESET_XUSB_HOST 54
-#define TEGRA186_RESET_XUSB_PADCTL 55
-#define TEGRA186_RESET_XUSB_SS 56
-#define TEGRA186_RESET_AON_APB 57
-#define TEGRA186_RESET_AXI_CBB 58
-#define TEGRA186_RESET_BPMP_APB 59
-#define TEGRA186_RESET_CAN1 60
-#define TEGRA186_RESET_CAN2 61
-#define TEGRA186_RESET_DMIC5 62
-#define TEGRA186_RESET_DSIC 63
-#define TEGRA186_RESET_DSID 64
-#define TEGRA186_RESET_EMC_EMC 65
-#define TEGRA186_RESET_EMC_MEM 66
-#define TEGRA186_RESET_EMCSB_EMC 67
-#define TEGRA186_RESET_EMCSB_MEM 68
-#define TEGRA186_RESET_EQOS 69
-#define TEGRA186_RESET_GPCDMA 70
-#define TEGRA186_RESET_GPIO_CTL0 71
-#define TEGRA186_RESET_GPIO_CTL1 72
-#define TEGRA186_RESET_GPIO_CTL2 73
-#define TEGRA186_RESET_GPIO_CTL3 74
-#define TEGRA186_RESET_GPIO_CTL4 75
-#define TEGRA186_RESET_GPIO_CTL5 76
-#define TEGRA186_RESET_I2C10 77
-#define TEGRA186_RESET_I2C12 78
-#define TEGRA186_RESET_I2C13 79
-#define TEGRA186_RESET_I2C14 80
-#define TEGRA186_RESET_I2C7 81
-#define TEGRA186_RESET_I2C8 82
-#define TEGRA186_RESET_I2C9 83
-#define TEGRA186_RESET_JTAG2AXI 84
-#define TEGRA186_RESET_MPHY_IOBIST 85
-#define TEGRA186_RESET_MPHY_L0_RX 86
-#define TEGRA186_RESET_MPHY_L0_TX 87
-#define TEGRA186_RESET_NVCSI 88
-#define TEGRA186_RESET_NVDISPLAY0_HEAD0 89
-#define TEGRA186_RESET_NVDISPLAY0_HEAD1 90
-#define TEGRA186_RESET_NVDISPLAY0_HEAD2 91
-#define TEGRA186_RESET_NVDISPLAY0_MISC 92
-#define TEGRA186_RESET_NVDISPLAY0_WGRP0 93
-#define TEGRA186_RESET_NVDISPLAY0_WGRP1 94
-#define TEGRA186_RESET_NVDISPLAY0_WGRP2 95
-#define TEGRA186_RESET_NVDISPLAY0_WGRP3 96
-#define TEGRA186_RESET_NVDISPLAY0_WGRP4 97
-#define TEGRA186_RESET_NVDISPLAY0_WGRP5 98
-#define TEGRA186_RESET_PWM1 99
-#define TEGRA186_RESET_PWM2 100
-#define TEGRA186_RESET_PWM3 101
-#define TEGRA186_RESET_PWM4 102
-#define TEGRA186_RESET_PWM5 103
-#define TEGRA186_RESET_PWM6 104
-#define TEGRA186_RESET_PWM7 105
-#define TEGRA186_RESET_PWM8 106
-#define TEGRA186_RESET_SCE_APB 107
-#define TEGRA186_RESET_SOR1 108
-#define TEGRA186_RESET_TACH 109
-#define TEGRA186_RESET_TSC 110
-#define TEGRA186_RESET_UARTF 111
-#define TEGRA186_RESET_UARTG 112
-#define TEGRA186_RESET_UFSHC 113
-#define TEGRA186_RESET_UFSHC_AXI_M 114
-#define TEGRA186_RESET_UPHY 115
-#define TEGRA186_RESET_ADSP 116
-#define TEGRA186_RESET_ADSPDBG 117
-#define TEGRA186_RESET_ADSPINTF 118
-#define TEGRA186_RESET_ADSPNEON 119
-#define TEGRA186_RESET_ADSPPERIPH 120
-#define TEGRA186_RESET_ADSPSCU 121
-#define TEGRA186_RESET_ADSPWDT 122
-#define TEGRA186_RESET_APE 123
-#define TEGRA186_RESET_DPAUX1 124
-#define TEGRA186_RESET_NVDEC 125
-#define TEGRA186_RESET_NVENC 126
-#define TEGRA186_RESET_NVJPG 127
-#define TEGRA186_RESET_PEX_USB_UPHY 128
-#define TEGRA186_RESET_QSPI 129
-#define TEGRA186_RESET_TSECB 130
-#define TEGRA186_RESET_VI_I2C 131
-#define TEGRA186_RESET_UARTE 132
-#define TEGRA186_RESET_TOP_GTE 133
-#define TEGRA186_RESET_SHSP 134
-#define TEGRA186_RESET_PEX_USB_UPHY_L5 135
-#define TEGRA186_RESET_PEX_USB_UPHY_L4 136
-#define TEGRA186_RESET_PEX_USB_UPHY_L3 137
-#define TEGRA186_RESET_PEX_USB_UPHY_L2 138
-#define TEGRA186_RESET_PEX_USB_UPHY_L1 139
-#define TEGRA186_RESET_PEX_USB_UPHY_L0 140
-#define TEGRA186_RESET_PEX_USB_UPHY_PLL1 141
-#define TEGRA186_RESET_PEX_USB_UPHY_PLL0 142
-#define TEGRA186_RESET_TSCTNVI 143
-#define TEGRA186_RESET_EXTPERIPH4 144
-#define TEGRA186_RESET_DSIPADCTL 145
-#define TEGRA186_RESET_AUD_MCLK 146
-#define TEGRA186_RESET_MPHY_CLK_CTL 147
-#define TEGRA186_RESET_MPHY_L1_RX 148
-#define TEGRA186_RESET_MPHY_L1_TX 149
-#define TEGRA186_RESET_UFSHC_LP 150
-#define TEGRA186_RESET_BPMP_NIC 151
-#define TEGRA186_RESET_BPMP_NSYSPORESET 152
-#define TEGRA186_RESET_BPMP_NRESET 153
-#define TEGRA186_RESET_BPMP_DBGRESETN 154
-#define TEGRA186_RESET_BPMP_PRESETDBGN 155
-#define TEGRA186_RESET_BPMP_PM 156
-#define TEGRA186_RESET_BPMP_CVC 157
-#define TEGRA186_RESET_BPMP_DMA 158
-#define TEGRA186_RESET_BPMP_HSP 159
-#define TEGRA186_RESET_TSCTNBPMP 160
-#define TEGRA186_RESET_BPMP_TKE 161
-#define TEGRA186_RESET_BPMP_GTE 162
-#define TEGRA186_RESET_BPMP_PM_ACTMON 163
-#define TEGRA186_RESET_AON_NIC 164
-#define TEGRA186_RESET_AON_NSYSPORESET 165
-#define TEGRA186_RESET_AON_NRESET 166
-#define TEGRA186_RESET_AON_DBGRESETN 167
-#define TEGRA186_RESET_AON_PRESETDBGN 168
-#define TEGRA186_RESET_AON_ACTMON 169
-#define TEGRA186_RESET_AOPM 170
-#define TEGRA186_RESET_AOVC 171
-#define TEGRA186_RESET_AON_DMA 172
-#define TEGRA186_RESET_AON_GPIO 173
-#define TEGRA186_RESET_AON_HSP 174
-#define TEGRA186_RESET_TSCTNAON 175
-#define TEGRA186_RESET_AON_TKE 176
-#define TEGRA186_RESET_AON_GTE 177
-#define TEGRA186_RESET_SCE_NIC 178
-#define TEGRA186_RESET_SCE_NSYSPORESET 179
-#define TEGRA186_RESET_SCE_NRESET 180
-#define TEGRA186_RESET_SCE_DBGRESETN 181
-#define TEGRA186_RESET_SCE_PRESETDBGN 182
-#define TEGRA186_RESET_SCE_ACTMON 183
-#define TEGRA186_RESET_SCE_PM 184
-#define TEGRA186_RESET_SCE_DMA 185
-#define TEGRA186_RESET_SCE_HSP 186
-#define TEGRA186_RESET_TSCTNSCE 187
-#define TEGRA186_RESET_SCE_TKE 188
-#define TEGRA186_RESET_SCE_GTE 189
-#define TEGRA186_RESET_SCE_CFG 190
-#define TEGRA186_RESET_ADSP_ALL 191
-/** @brief controls the power up/down sequence of UFSHC PSW partition. Controls LP_PWR_READY, LP_ISOL_EN, and LP_RESET_N signals */
-#define TEGRA186_RESET_UFSHC_LP_SEQ 192
-#define TEGRA186_RESET_SIZE 193
-
-#endif
diff --git a/include/dt-bindings/reset/ti-syscon.h b/include/dt-bindings/reset/ti-syscon.h
deleted file mode 100644
index 884fd91..0000000
--- a/include/dt-bindings/reset/ti-syscon.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * TI Syscon Reset definitions
- *
- * Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef __DT_BINDINGS_RESET_TI_SYSCON_H__
-#define __DT_BINDINGS_RESET_TI_SYSCON_H__
-
-/*
- * The reset does not support the feature and corresponding
- * values are not valid
- */
-#define ASSERT_NONE (1 << 0)
-#define DEASSERT_NONE (1 << 1)
-#define STATUS_NONE (1 << 2)
-
-/* When set this function is activated by setting(vs clearing) this bit */
-#define ASSERT_SET (1 << 3)
-#define DEASSERT_SET (1 << 4)
-#define STATUS_SET (1 << 5)
-
-/* The following are the inverse of the above and are added for consistency */
-#define ASSERT_CLEAR (0 << 3)
-#define DEASSERT_CLEAR (0 << 4)
-#define STATUS_CLEAR (0 << 5)
-
-#endif
diff --git a/include/dt-bindings/reset/xlnx-zynqmp-resets.h b/include/dt-bindings/reset/xlnx-zynqmp-resets.h
deleted file mode 100644
index d44525b..0000000
--- a/include/dt-bindings/reset/xlnx-zynqmp-resets.h
+++ /dev/null
@@ -1,130 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2018 Xilinx, Inc.
- */
-
-#ifndef _DT_BINDINGS_ZYNQMP_RESETS_H
-#define _DT_BINDINGS_ZYNQMP_RESETS_H
-
-#define ZYNQMP_RESET_PCIE_CFG 0
-#define ZYNQMP_RESET_PCIE_BRIDGE 1
-#define ZYNQMP_RESET_PCIE_CTRL 2
-#define ZYNQMP_RESET_DP 3
-#define ZYNQMP_RESET_SWDT_CRF 4
-#define ZYNQMP_RESET_AFI_FM5 5
-#define ZYNQMP_RESET_AFI_FM4 6
-#define ZYNQMP_RESET_AFI_FM3 7
-#define ZYNQMP_RESET_AFI_FM2 8
-#define ZYNQMP_RESET_AFI_FM1 9
-#define ZYNQMP_RESET_AFI_FM0 10
-#define ZYNQMP_RESET_GDMA 11
-#define ZYNQMP_RESET_GPU_PP1 12
-#define ZYNQMP_RESET_GPU_PP0 13
-#define ZYNQMP_RESET_GPU 14
-#define ZYNQMP_RESET_GT 15
-#define ZYNQMP_RESET_SATA 16
-#define ZYNQMP_RESET_ACPU3_PWRON 17
-#define ZYNQMP_RESET_ACPU2_PWRON 18
-#define ZYNQMP_RESET_ACPU1_PWRON 19
-#define ZYNQMP_RESET_ACPU0_PWRON 20
-#define ZYNQMP_RESET_APU_L2 21
-#define ZYNQMP_RESET_ACPU3 22
-#define ZYNQMP_RESET_ACPU2 23
-#define ZYNQMP_RESET_ACPU1 24
-#define ZYNQMP_RESET_ACPU0 25
-#define ZYNQMP_RESET_DDR 26
-#define ZYNQMP_RESET_APM_FPD 27
-#define ZYNQMP_RESET_SOFT 28
-#define ZYNQMP_RESET_GEM0 29
-#define ZYNQMP_RESET_GEM1 30
-#define ZYNQMP_RESET_GEM2 31
-#define ZYNQMP_RESET_GEM3 32
-#define ZYNQMP_RESET_QSPI 33
-#define ZYNQMP_RESET_UART0 34
-#define ZYNQMP_RESET_UART1 35
-#define ZYNQMP_RESET_SPI0 36
-#define ZYNQMP_RESET_SPI1 37
-#define ZYNQMP_RESET_SDIO0 38
-#define ZYNQMP_RESET_SDIO1 39
-#define ZYNQMP_RESET_CAN0 40
-#define ZYNQMP_RESET_CAN1 41
-#define ZYNQMP_RESET_I2C0 42
-#define ZYNQMP_RESET_I2C1 43
-#define ZYNQMP_RESET_TTC0 44
-#define ZYNQMP_RESET_TTC1 45
-#define ZYNQMP_RESET_TTC2 46
-#define ZYNQMP_RESET_TTC3 47
-#define ZYNQMP_RESET_SWDT_CRL 48
-#define ZYNQMP_RESET_NAND 49
-#define ZYNQMP_RESET_ADMA 50
-#define ZYNQMP_RESET_GPIO 51
-#define ZYNQMP_RESET_IOU_CC 52
-#define ZYNQMP_RESET_TIMESTAMP 53
-#define ZYNQMP_RESET_RPU_R50 54
-#define ZYNQMP_RESET_RPU_R51 55
-#define ZYNQMP_RESET_RPU_AMBA 56
-#define ZYNQMP_RESET_OCM 57
-#define ZYNQMP_RESET_RPU_PGE 58
-#define ZYNQMP_RESET_USB0_CORERESET 59
-#define ZYNQMP_RESET_USB1_CORERESET 60
-#define ZYNQMP_RESET_USB0_HIBERRESET 61
-#define ZYNQMP_RESET_USB1_HIBERRESET 62
-#define ZYNQMP_RESET_USB0_APB 63
-#define ZYNQMP_RESET_USB1_APB 64
-#define ZYNQMP_RESET_IPI 65
-#define ZYNQMP_RESET_APM_LPD 66
-#define ZYNQMP_RESET_RTC 67
-#define ZYNQMP_RESET_SYSMON 68
-#define ZYNQMP_RESET_AFI_FM6 69
-#define ZYNQMP_RESET_LPD_SWDT 70
-#define ZYNQMP_RESET_FPD 71
-#define ZYNQMP_RESET_RPU_DBG1 72
-#define ZYNQMP_RESET_RPU_DBG0 73
-#define ZYNQMP_RESET_DBG_LPD 74
-#define ZYNQMP_RESET_DBG_FPD 75
-#define ZYNQMP_RESET_APLL 76
-#define ZYNQMP_RESET_DPLL 77
-#define ZYNQMP_RESET_VPLL 78
-#define ZYNQMP_RESET_IOPLL 79
-#define ZYNQMP_RESET_RPLL 80
-#define ZYNQMP_RESET_GPO3_PL_0 81
-#define ZYNQMP_RESET_GPO3_PL_1 82
-#define ZYNQMP_RESET_GPO3_PL_2 83
-#define ZYNQMP_RESET_GPO3_PL_3 84
-#define ZYNQMP_RESET_GPO3_PL_4 85
-#define ZYNQMP_RESET_GPO3_PL_5 86
-#define ZYNQMP_RESET_GPO3_PL_6 87
-#define ZYNQMP_RESET_GPO3_PL_7 88
-#define ZYNQMP_RESET_GPO3_PL_8 89
-#define ZYNQMP_RESET_GPO3_PL_9 90
-#define ZYNQMP_RESET_GPO3_PL_10 91
-#define ZYNQMP_RESET_GPO3_PL_11 92
-#define ZYNQMP_RESET_GPO3_PL_12 93
-#define ZYNQMP_RESET_GPO3_PL_13 94
-#define ZYNQMP_RESET_GPO3_PL_14 95
-#define ZYNQMP_RESET_GPO3_PL_15 96
-#define ZYNQMP_RESET_GPO3_PL_16 97
-#define ZYNQMP_RESET_GPO3_PL_17 98
-#define ZYNQMP_RESET_GPO3_PL_18 99
-#define ZYNQMP_RESET_GPO3_PL_19 100
-#define ZYNQMP_RESET_GPO3_PL_20 101
-#define ZYNQMP_RESET_GPO3_PL_21 102
-#define ZYNQMP_RESET_GPO3_PL_22 103
-#define ZYNQMP_RESET_GPO3_PL_23 104
-#define ZYNQMP_RESET_GPO3_PL_24 105
-#define ZYNQMP_RESET_GPO3_PL_25 106
-#define ZYNQMP_RESET_GPO3_PL_26 107
-#define ZYNQMP_RESET_GPO3_PL_27 108
-#define ZYNQMP_RESET_GPO3_PL_28 109
-#define ZYNQMP_RESET_GPO3_PL_29 110
-#define ZYNQMP_RESET_GPO3_PL_30 111
-#define ZYNQMP_RESET_GPO3_PL_31 112
-#define ZYNQMP_RESET_RPU_LS 113
-#define ZYNQMP_RESET_PS_ONLY 114
-#define ZYNQMP_RESET_PL 115
-#define ZYNQMP_RESET_PS_PL0 116
-#define ZYNQMP_RESET_PS_PL1 117
-#define ZYNQMP_RESET_PS_PL2 118
-#define ZYNQMP_RESET_PS_PL3 119
-
-#endif
diff --git a/include/dt-bindings/soc/bcm2835-pm.h b/include/dt-bindings/soc/bcm2835-pm.h
deleted file mode 100644
index 153d75b..0000000
--- a/include/dt-bindings/soc/bcm2835-pm.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
-
-#ifndef _DT_BINDINGS_ARM_BCM2835_PM_H
-#define _DT_BINDINGS_ARM_BCM2835_PM_H
-
-#define BCM2835_POWER_DOMAIN_GRAFX 0
-#define BCM2835_POWER_DOMAIN_GRAFX_V3D 1
-#define BCM2835_POWER_DOMAIN_IMAGE 2
-#define BCM2835_POWER_DOMAIN_IMAGE_PERI 3
-#define BCM2835_POWER_DOMAIN_IMAGE_ISP 4
-#define BCM2835_POWER_DOMAIN_IMAGE_H264 5
-#define BCM2835_POWER_DOMAIN_USB 6
-#define BCM2835_POWER_DOMAIN_DSI0 7
-#define BCM2835_POWER_DOMAIN_DSI1 8
-#define BCM2835_POWER_DOMAIN_CAM0 9
-#define BCM2835_POWER_DOMAIN_CAM1 10
-#define BCM2835_POWER_DOMAIN_CCP2TX 11
-#define BCM2835_POWER_DOMAIN_HDMI 12
-
-#define BCM2835_POWER_DOMAIN_COUNT 13
-
-#define BCM2835_RESET_V3D 0
-#define BCM2835_RESET_ISP 1
-#define BCM2835_RESET_H264 2
-
-#define BCM2835_RESET_COUNT 3
-
-#endif /* _DT_BINDINGS_ARM_BCM2835_PM_H */
diff --git a/include/dt-bindings/soc/imx8_pd.h b/include/dt-bindings/soc/imx8_pd.h
deleted file mode 100644
index 682b608..0000000
--- a/include/dt-bindings/soc/imx8_pd.h
+++ /dev/null
@@ -1,188 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2018 NXP
- */
-
-#ifndef __DT_BINDINGS_IMX8_PD_H
-#define __DT_BINDINGS_IMX8_PD_H
-
-/*!
- * These defines are used to indicate a resource. Resources include peripherals
- * and bus masters (but not memory regions). Note items from list should
- * never be changed or removed (only added to at the end of the list).
- */
-#define PD_DC_0 dc0_power_domain
-#define PD_DC_0_PLL_0 dc0_pll0
-#define PD_DC_0_PLL_1 dc0_pll1
-#define PD_LVDS0 lvds0_power_domain
-#define PD_LVDS0_I2C0 lvds0_i2c0
-#define PD_LVDS0_I2C1 lvds0_i2c1
-#define PD_LVDS0_PWM lvds0_pwm
-#define PD_LVDS0_PWM lvds0_pwm
-#define PD_LVDS0_GPIO lvds0_gpio
-#define PD_DC_1 dc1_power_domain
-#define PD_DC_1_PLL_0 dc1_pll0
-#define PD_DC_1_PLL_1 dc1_pll1
-#define PD_LVDS1 lvds1_power_domain
-#define PD_LVDS1_I2C0 lvds1_i2c0
-#define PD_LVDS1_I2C1 lvds1_i2c1
-#define PD_LVDS1_PWM lvds1_pwm
-#define PD_LVDS1_GPIO lvds1_gpio
-
-#define PD_DMA dma_power_domain
-#define PD_DMA_SPI_0 dma_spi0
-#define PD_DMA_SPI_1 dma_spi1
-#define PD_DMA_SPI_2 dma_spi2
-#define PD_DMA_SPI_3 dma_spi3
-#define PD_DMA_UART0 dma_lpuart0
-#define PD_DMA_UART1 dma_lpuart1
-#define PD_DMA_UART2 dma_lpuart2
-#define PD_DMA_UART3 dma_lpuart3
-#define PD_DMA_UART4 dma_lpuart4
-#define PD_DMA_EMVSIM_0 dma_emvsim0
-#define PD_DMA_EMVSIM_1 dma_emvsim1
-#define PD_DMA_I2C_0 dma_lpi2c0
-#define PD_DMA_I2C_1 dma_lpi2c1
-#define PD_DMA_I2C_2 dma_lpi2c2
-#define PD_DMA_I2C_3 dma_lpi2c3
-#define PD_DMA_I2C_4 dma_lpi2c4
-#define PD_DMA_ADC_0 dma_adc0
-#define PD_DMA_ADC_1 dma_adc1
-#define PD_DMA_FTM_0 dma_ftm0
-#define PD_DMA_FTM_1 dma_ftm1
-#define PD_DMA_CAN_0 dma_flexcan0
-#define PD_DMA_CAN_1 dma_flexcan1
-#define PD_DMA_CAN_2 dma_flexcan2
-#define PD_DMA_PWM_0 dma_pwm0
-#define PD_DMA_LCD_0 dma_lcd0
-
-#define PD_HSIO hsio_power_domain
-#define PD_HSIO_PCIE_A hsio_pcie0
-#define PD_HSIO_PCIE_B hsio_pcie1
-#define PD_HSIO_SATA_0 hsio_sata0
-#define PD_HSIO_GPIO hsio_gpio
-
-#define PD_LCD_0 lcd0_power_domain
-#define PD_LCD_0_I2C_0 lcd0_i2c0
-#define PD_LCD_0_I2C_1 lcd0_i2c1
-#define PD_LCD_PWM_0 lcd0_pwm0
-
-#define PD_LSIO lsio_power_domain
-#define PD_LSIO_GPIO_0 lsio_gpio0
-#define PD_LSIO_GPIO_1 lsio_gpio1
-#define PD_LSIO_GPIO_2 lsio_gpio2
-#define PD_LSIO_GPIO_3 lsio_gpio3
-#define PD_LSIO_GPIO_4 lsio_gpio4
-#define PD_LSIO_GPIO_5 lsio_gpio5
-#define PD_LSIO_GPIO_6 lsio_gpio6
-#define PD_LSIO_GPIO_7 lsio_gpio7
-#define PD_LSIO_GPT_0 lsio_gpt0
-#define PD_LSIO_GPT_1 lsio_gpt1
-#define PD_LSIO_GPT_2 lsio_gpt2
-#define PD_LSIO_GPT_3 lsio_gpt3
-#define PD_LSIO_GPT_4 lsio_gpt4
-#define PD_LSIO_KPP lsio_kpp
-#define PD_LSIO_FSPI_0 lsio_fspi0
-#define PD_LSIO_FSPI_1 lsio_fspi1
-#define PD_LSIO_PWM_0 lsio_pwm0
-#define PD_LSIO_PWM_1 lsio_pwm1
-#define PD_LSIO_PWM_2 lsio_pwm2
-#define PD_LSIO_PWM_3 lsio_pwm3
-#define PD_LSIO_PWM_4 lsio_pwm4
-#define PD_LSIO_PWM_5 lsio_pwm5
-#define PD_LSIO_PWM_6 lsio_pwm6
-#define PD_LSIO_PWM_7 lsio_pwm7
-
-#define PD_CONN connectivity_power_domain
-#define PD_CONN_SDHC_0 conn_sdhc0
-#define PD_CONN_SDHC_1 conn_sdhc1
-#define PD_CONN_SDHC_2 conn_sdhc2
-#define PD_CONN_ENET_0 conn_enet0
-#define PD_CONN_ENET_1 conn_enet1
-#define PD_CONN_MLB_0 conn_mlb0
-#define PD_CONN_DMA_4_CH0 conn_dma4_ch0
-#define PD_CONN_DMA_4_CH1 conn_dma4_ch1
-#define PD_CONN_DMA_4_CH2 conn_dma4_ch2
-#define PD_CONN_DMA_4_CH3 conn_dma4_ch3
-#define PD_CONN_DMA_4_CH4 conn_dma4_ch4
-#define PD_CONN_USB_0 conn_usb0
-#define PD_CONN_USB_1 conn_usb1
-#define PD_CONN_USB_0_PHY conn_usb0_phy
-#define PD_CONN_USB_2 conn_usb2
-#define PD_CONN_USB_2_PHY conn_usb2_phy
-#define PD_CONN_NAND conn_nand
-
-#define PD_AUDIO audio_power_domain
-#define PD_AUD_SAI_0 audio_sai0
-#define PD_AUD_SAI_1 audio_sai1
-#define PD_AUD_SAI_2 audio_sai2
-#define PD_AUD_ASRC_0 audio_asrc0
-#define PD_AUD_ASRC_1 audio_asrc1
-#define PD_AUD_ESAI_0 audio_esai0
-#define PD_AUD_ESAI_1 audio_esai1
-#define PD_AUD_SPDIF_0 audio_spdif0
-#define PD_AUD_SPDIF_1 audio_spdif1
-#define PD_AUD_SAI_3 audio_sai3
-#define PD_AUD_SAI_4 audio_sai4
-#define PD_AUD_SAI_5 audio_sai5
-#define PD_AUD_SAI_6 audio_sai6
-#define PD_AUD_SAI_7 audio_sai7
-#define PD_AUD_GPT_5 audio_gpt5
-#define PD_AUD_GPT_6 audio_gpt6
-#define PD_AUD_GPT_7 audio_gpt7
-#define PD_AUD_GPT_8 audio_gpt8
-#define PD_AUD_GPT_9 audio_gpt9
-#define PD_AUD_GPT_10 audio_gpt10
-#define PD_AUD_AMIX audio_amix
-#define PD_AUD_MQS_0 audio_mqs0
-#define PD_AUD_HIFI audio_hifi
-#define PD_AUD_OCRAM audio_ocram
-#define PD_AUD_MCLK_OUT_0 audio_mclkout0
-#define PD_AUD_MCLK_OUT_1 audio_mclkout1
-#define PD_AUD_AUDIO_PLL_0 audio_audiopll0
-#define PD_AUD_AUDIO_PLL_1 audio_audiopll1
-#define PD_AUD_AUDIO_CLK_0 audio_audioclk0
-#define PD_AUD_AUDIO_CLK_1 audio_audioclk1
-
-#define PD_IMAGING imaging_power_domain
-#define PD_IMAGING_JPEG_DEC imaging_jpeg_dec
-#define PD_IMAGING_JPEG_ENC imaging_jpeg_enc
-#define PD_IMAGING_PDMA0 PD_IMAGING
-#define PD_IMAGING_PDMA1 imaging_pdma1
-#define PD_IMAGING_PDMA2 imaging_pdma2
-#define PD_IMAGING_PDMA3 imaging_pdma3
-#define PD_IMAGING_PDMA4 imaging_pdma4
-#define PD_IMAGING_PDMA5 imaging_pdma5
-#define PD_IMAGING_PDMA6 imaging_pdma6
-#define PD_IMAGING_PDMA7 imaging_pdma7
-
-#define PD_MIPI_0_DSI mipi0_dsi_power_domain
-#define PD_MIPI_0_DSI_I2C0 mipi0_dsi_i2c0
-#define PD_MIPI_0_DSI_I2C1 mipi0_dsi_i2c1
-#define PD_MIPI_0_DSI_PWM0 mipi0_dsi_pwm0
-#define PD_MIPI_1_DSI mipi1_dsi_power_domain
-#define PD_MIPI_1_DSI_I2C0 mipi1_dsi_i2c0
-#define PD_MIPI_1_DSI_I2C1 mipi1_dsi_i2c1
-#define PD_MIPI_1_DSI_PWM0 mipi1_dsi_pwm0
-
-#define PD_MIPI_CSI0 mipi_csi0_power_domain
-#define PD_MIPI_CSI0_PWM mipi_csi0_pwm
-#define PD_MIPI_CSI0_I2C mipi_csi0_i2c
-#define PD_MIPI_CSI1 mipi_csi1_power_domain
-#define PD_MIPI_CSI1_PWM_0 mipi_csi1_pwm
-#define PD_MIPI_CSI1_I2C_0 mipi_csi1_i2c
-
-#define PD_HDMI hdmi_power_domain
-#define PD_HDMI_I2C_0 hdmi_i2c
-#define PD_HDMI_PWM_0 hdmi_pwm
-#define PD_HDMI_GPIO_0 hdmi_gpio
-
-#define PD_HDMI_RX hdmi_rx_power_domain
-#define PD_HDMI_RX_I2C hdmi_rx_i2c
-#define PD_HDMI_RX_PWM hdmi_rx_pwm
-
-#define PD_CM40 cm40_power_domain
-#define PD_CM40_I2C cm40_i2c
-#define PD_CM40_INTMUX cm40_intmux
-
-#endif /* __DT_BINDINGS_IMX8_PD_H */
diff --git a/include/dt-bindings/soc/imx_rsrc.h b/include/dt-bindings/soc/imx_rsrc.h
deleted file mode 100644
index 4870eb9..0000000
--- a/include/dt-bindings/soc/imx_rsrc.h
+++ /dev/null
@@ -1,557 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2018 NXP
- */
-
-#ifndef DT_BINDINGS_RSCRC_IMX_H
-#define DT_BINDINGS_RSCRC_IMX_H
-
-/*!
- * These defines are used to indicate a resource. Resources include peripherals
- * and bus masters (but not memory regions). Note items from list should
- * never be changed or removed (only added to at the end of the list).
- */
-#define SC_R_A53 0
-#define SC_R_A53_0 1
-#define SC_R_A53_1 2
-#define SC_R_A53_2 3
-#define SC_R_A53_3 4
-#define SC_R_A72 5
-#define SC_R_A72_0 6
-#define SC_R_A72_1 7
-#define SC_R_A72_2 8
-#define SC_R_A72_3 9
-#define SC_R_CCI 10
-#define SC_R_DB 11
-#define SC_R_DRC_0 12
-#define SC_R_DRC_1 13
-#define SC_R_GIC_SMMU 14
-#define SC_R_IRQSTR_M4_0 15
-#define SC_R_IRQSTR_M4_1 16
-#define SC_R_SMMU 17
-#define SC_R_GIC 18
-#define SC_R_DC_0_BLIT0 19
-#define SC_R_DC_0_BLIT1 20
-#define SC_R_DC_0_BLIT2 21
-#define SC_R_DC_0_BLIT_OUT 22
-#define SC_R_DC_0_CAPTURE0 23
-#define SC_R_DC_0_CAPTURE1 24
-#define SC_R_DC_0_WARP 25
-#define SC_R_DC_0_INTEGRAL0 26
-#define SC_R_DC_0_INTEGRAL1 27
-#define SC_R_DC_0_VIDEO0 28
-#define SC_R_DC_0_VIDEO1 29
-#define SC_R_DC_0_FRAC0 30
-#define SC_R_DC_0_FRAC1 31
-#define SC_R_DC_0 32
-#define SC_R_GPU_2_PID0 33
-#define SC_R_DC_0_PLL_0 34
-#define SC_R_DC_0_PLL_1 35
-#define SC_R_DC_1_BLIT0 36
-#define SC_R_DC_1_BLIT1 37
-#define SC_R_DC_1_BLIT2 38
-#define SC_R_DC_1_BLIT_OUT 39
-#define SC_R_DC_1_CAPTURE0 40
-#define SC_R_DC_1_CAPTURE1 41
-#define SC_R_DC_1_WARP 42
-#define SC_R_DC_1_INTEGRAL0 43
-#define SC_R_DC_1_INTEGRAL1 44
-#define SC_R_DC_1_VIDEO0 45
-#define SC_R_DC_1_VIDEO1 46
-#define SC_R_DC_1_FRAC0 47
-#define SC_R_DC_1_FRAC1 48
-#define SC_R_DC_1 49
-#define SC_R_GPU_3_PID0 50
-#define SC_R_DC_1_PLL_0 51
-#define SC_R_DC_1_PLL_1 52
-#define SC_R_SPI_0 53
-#define SC_R_SPI_1 54
-#define SC_R_SPI_2 55
-#define SC_R_SPI_3 56
-#define SC_R_UART_0 57
-#define SC_R_UART_1 58
-#define SC_R_UART_2 59
-#define SC_R_UART_3 60
-#define SC_R_UART_4 61
-#define SC_R_EMVSIM_0 62
-#define SC_R_EMVSIM_1 63
-#define SC_R_DMA_0_CH0 64
-#define SC_R_DMA_0_CH1 65
-#define SC_R_DMA_0_CH2 66
-#define SC_R_DMA_0_CH3 67
-#define SC_R_DMA_0_CH4 68
-#define SC_R_DMA_0_CH5 69
-#define SC_R_DMA_0_CH6 70
-#define SC_R_DMA_0_CH7 71
-#define SC_R_DMA_0_CH8 72
-#define SC_R_DMA_0_CH9 73
-#define SC_R_DMA_0_CH10 74
-#define SC_R_DMA_0_CH11 75
-#define SC_R_DMA_0_CH12 76
-#define SC_R_DMA_0_CH13 77
-#define SC_R_DMA_0_CH14 78
-#define SC_R_DMA_0_CH15 79
-#define SC_R_DMA_0_CH16 80
-#define SC_R_DMA_0_CH17 81
-#define SC_R_DMA_0_CH18 82
-#define SC_R_DMA_0_CH19 83
-#define SC_R_DMA_0_CH20 84
-#define SC_R_DMA_0_CH21 85
-#define SC_R_DMA_0_CH22 86
-#define SC_R_DMA_0_CH23 87
-#define SC_R_DMA_0_CH24 88
-#define SC_R_DMA_0_CH25 89
-#define SC_R_DMA_0_CH26 90
-#define SC_R_DMA_0_CH27 91
-#define SC_R_DMA_0_CH28 92
-#define SC_R_DMA_0_CH29 93
-#define SC_R_DMA_0_CH30 94
-#define SC_R_DMA_0_CH31 95
-#define SC_R_I2C_0 96
-#define SC_R_I2C_1 97
-#define SC_R_I2C_2 98
-#define SC_R_I2C_3 99
-#define SC_R_I2C_4 100
-#define SC_R_ADC_0 101
-#define SC_R_ADC_1 102
-#define SC_R_FTM_0 103
-#define SC_R_FTM_1 104
-#define SC_R_CAN_0 105
-#define SC_R_CAN_1 106
-#define SC_R_CAN_2 107
-#define SC_R_DMA_1_CH0 108
-#define SC_R_DMA_1_CH1 109
-#define SC_R_DMA_1_CH2 110
-#define SC_R_DMA_1_CH3 111
-#define SC_R_DMA_1_CH4 112
-#define SC_R_DMA_1_CH5 113
-#define SC_R_DMA_1_CH6 114
-#define SC_R_DMA_1_CH7 115
-#define SC_R_DMA_1_CH8 116
-#define SC_R_DMA_1_CH9 117
-#define SC_R_DMA_1_CH10 118
-#define SC_R_DMA_1_CH11 119
-#define SC_R_DMA_1_CH12 120
-#define SC_R_DMA_1_CH13 121
-#define SC_R_DMA_1_CH14 122
-#define SC_R_DMA_1_CH15 123
-#define SC_R_DMA_1_CH16 124
-#define SC_R_DMA_1_CH17 125
-#define SC_R_DMA_1_CH18 126
-#define SC_R_DMA_1_CH19 127
-#define SC_R_DMA_1_CH20 128
-#define SC_R_DMA_1_CH21 129
-#define SC_R_DMA_1_CH22 130
-#define SC_R_DMA_1_CH23 131
-#define SC_R_DMA_1_CH24 132
-#define SC_R_DMA_1_CH25 133
-#define SC_R_DMA_1_CH26 134
-#define SC_R_DMA_1_CH27 135
-#define SC_R_DMA_1_CH28 136
-#define SC_R_DMA_1_CH29 137
-#define SC_R_DMA_1_CH30 138
-#define SC_R_DMA_1_CH31 139
-#define SC_R_UNUSED1 140
-#define SC_R_UNUSED2 141
-#define SC_R_UNUSED3 142
-#define SC_R_UNUSED4 143
-#define SC_R_GPU_0_PID0 144
-#define SC_R_GPU_0_PID1 145
-#define SC_R_GPU_0_PID2 146
-#define SC_R_GPU_0_PID3 147
-#define SC_R_GPU_1_PID0 148
-#define SC_R_GPU_1_PID1 149
-#define SC_R_GPU_1_PID2 150
-#define SC_R_GPU_1_PID3 151
-#define SC_R_PCIE_A 152
-#define SC_R_SERDES_0 153
-#define SC_R_MATCH_0 154
-#define SC_R_MATCH_1 155
-#define SC_R_MATCH_2 156
-#define SC_R_MATCH_3 157
-#define SC_R_MATCH_4 158
-#define SC_R_MATCH_5 159
-#define SC_R_MATCH_6 160
-#define SC_R_MATCH_7 161
-#define SC_R_MATCH_8 162
-#define SC_R_MATCH_9 163
-#define SC_R_MATCH_10 164
-#define SC_R_MATCH_11 165
-#define SC_R_MATCH_12 166
-#define SC_R_MATCH_13 167
-#define SC_R_MATCH_14 168
-#define SC_R_PCIE_B 169
-#define SC_R_SATA_0 170
-#define SC_R_SERDES_1 171
-#define SC_R_HSIO_GPIO 172
-#define SC_R_MATCH_15 173
-#define SC_R_MATCH_16 174
-#define SC_R_MATCH_17 175
-#define SC_R_MATCH_18 176
-#define SC_R_MATCH_19 177
-#define SC_R_MATCH_20 178
-#define SC_R_MATCH_21 179
-#define SC_R_MATCH_22 180
-#define SC_R_MATCH_23 181
-#define SC_R_MATCH_24 182
-#define SC_R_MATCH_25 183
-#define SC_R_MATCH_26 184
-#define SC_R_MATCH_27 185
-#define SC_R_MATCH_28 186
-#define SC_R_LCD_0 187
-#define SC_R_LCD_0_PWM_0 188
-#define SC_R_LCD_0_I2C_0 189
-#define SC_R_LCD_0_I2C_1 190
-#define SC_R_PWM_0 191
-#define SC_R_PWM_1 192
-#define SC_R_PWM_2 193
-#define SC_R_PWM_3 194
-#define SC_R_PWM_4 195
-#define SC_R_PWM_5 196
-#define SC_R_PWM_6 197
-#define SC_R_PWM_7 198
-#define SC_R_GPIO_0 199
-#define SC_R_GPIO_1 200
-#define SC_R_GPIO_2 201
-#define SC_R_GPIO_3 202
-#define SC_R_GPIO_4 203
-#define SC_R_GPIO_5 204
-#define SC_R_GPIO_6 205
-#define SC_R_GPIO_7 206
-#define SC_R_GPT_0 207
-#define SC_R_GPT_1 208
-#define SC_R_GPT_2 209
-#define SC_R_GPT_3 210
-#define SC_R_GPT_4 211
-#define SC_R_KPP 212
-#define SC_R_MU_0A 213
-#define SC_R_MU_1A 214
-#define SC_R_MU_2A 215
-#define SC_R_MU_3A 216
-#define SC_R_MU_4A 217
-#define SC_R_MU_5A 218
-#define SC_R_MU_6A 219
-#define SC_R_MU_7A 220
-#define SC_R_MU_8A 221
-#define SC_R_MU_9A 222
-#define SC_R_MU_10A 223
-#define SC_R_MU_11A 224
-#define SC_R_MU_12A 225
-#define SC_R_MU_13A 226
-#define SC_R_MU_5B 227
-#define SC_R_MU_6B 228
-#define SC_R_MU_7B 229
-#define SC_R_MU_8B 230
-#define SC_R_MU_9B 231
-#define SC_R_MU_10B 232
-#define SC_R_MU_11B 233
-#define SC_R_MU_12B 234
-#define SC_R_MU_13B 235
-#define SC_R_ROM_0 236
-#define SC_R_FSPI_0 237
-#define SC_R_FSPI_1 238
-#define SC_R_IEE 239
-#define SC_R_IEE_R0 240
-#define SC_R_IEE_R1 241
-#define SC_R_IEE_R2 242
-#define SC_R_IEE_R3 243
-#define SC_R_IEE_R4 244
-#define SC_R_IEE_R5 245
-#define SC_R_IEE_R6 246
-#define SC_R_IEE_R7 247
-#define SC_R_SDHC_0 248
-#define SC_R_SDHC_1 249
-#define SC_R_SDHC_2 250
-#define SC_R_ENET_0 251
-#define SC_R_ENET_1 252
-#define SC_R_MLB_0 253
-#define SC_R_DMA_2_CH0 254
-#define SC_R_DMA_2_CH1 255
-#define SC_R_DMA_2_CH2 256
-#define SC_R_DMA_2_CH3 257
-#define SC_R_DMA_2_CH4 258
-#define SC_R_USB_0 259
-#define SC_R_USB_1 260
-#define SC_R_USB_0_PHY 261
-#define SC_R_USB_2 262
-#define SC_R_USB_2_PHY 263
-#define SC_R_DTCP 264
-#define SC_R_NAND 265
-#define SC_R_LVDS_0 266
-#define SC_R_LVDS_0_PWM_0 267
-#define SC_R_LVDS_0_I2C_0 268
-#define SC_R_LVDS_0_I2C_1 269
-#define SC_R_LVDS_1 270
-#define SC_R_LVDS_1_PWM_0 271
-#define SC_R_LVDS_1_I2C_0 272
-#define SC_R_LVDS_1_I2C_1 273
-#define SC_R_LVDS_2 274
-#define SC_R_LVDS_2_PWM_0 275
-#define SC_R_LVDS_2_I2C_0 276
-#define SC_R_LVDS_2_I2C_1 277
-#define SC_R_M4_0_PID0 278
-#define SC_R_M4_0_PID1 279
-#define SC_R_M4_0_PID2 280
-#define SC_R_M4_0_PID3 281
-#define SC_R_M4_0_PID4 282
-#define SC_R_M4_0_RGPIO 283
-#define SC_R_M4_0_SEMA42 284
-#define SC_R_M4_0_TPM 285
-#define SC_R_M4_0_PIT 286
-#define SC_R_M4_0_UART 287
-#define SC_R_M4_0_I2C 288
-#define SC_R_M4_0_INTMUX 289
-#define SC_R_M4_0_SIM 290
-#define SC_R_M4_0_WDOG 291
-#define SC_R_M4_0_MU_0B 292
-#define SC_R_M4_0_MU_0A0 293
-#define SC_R_M4_0_MU_0A1 294
-#define SC_R_M4_0_MU_0A2 295
-#define SC_R_M4_0_MU_0A3 296
-#define SC_R_M4_0_MU_1A 297
-#define SC_R_M4_1_PID0 298
-#define SC_R_M4_1_PID1 299
-#define SC_R_M4_1_PID2 300
-#define SC_R_M4_1_PID3 301
-#define SC_R_M4_1_PID4 302
-#define SC_R_M4_1_RGPIO 303
-#define SC_R_M4_1_SEMA42 304
-#define SC_R_M4_1_TPM 305
-#define SC_R_M4_1_PIT 306
-#define SC_R_M4_1_UART 307
-#define SC_R_M4_1_I2C 308
-#define SC_R_M4_1_INTMUX 309
-#define SC_R_M4_1_SIM 310
-#define SC_R_M4_1_WDOG 311
-#define SC_R_M4_1_MU_0B 312
-#define SC_R_M4_1_MU_0A0 313
-#define SC_R_M4_1_MU_0A1 314
-#define SC_R_M4_1_MU_0A2 315
-#define SC_R_M4_1_MU_0A3 316
-#define SC_R_M4_1_MU_1A 317
-#define SC_R_SAI_0 318
-#define SC_R_SAI_1 319
-#define SC_R_SAI_2 320
-#define SC_R_IRQSTR_SCU2 321
-#define SC_R_IRQSTR_DSP 322
-#define SC_R_UNUSED5 323
-#define SC_R_OCRAM 324
-#define SC_R_AUDIO_PLL_0 325
-#define SC_R_PI_0 326
-#define SC_R_PI_0_PWM_0 327
-#define SC_R_PI_0_PWM_1 328
-#define SC_R_PI_0_I2C_0 329
-#define SC_R_PI_0_PLL 330
-#define SC_R_PI_1 331
-#define SC_R_PI_1_PWM_0 332
-#define SC_R_PI_1_PWM_1 333
-#define SC_R_PI_1_I2C_0 334
-#define SC_R_PI_1_PLL 335
-#define SC_R_SC_PID0 336
-#define SC_R_SC_PID1 337
-#define SC_R_SC_PID2 338
-#define SC_R_SC_PID3 339
-#define SC_R_SC_PID4 340
-#define SC_R_SC_SEMA42 341
-#define SC_R_SC_TPM 342
-#define SC_R_SC_PIT 343
-#define SC_R_SC_UART 344
-#define SC_R_SC_I2C 345
-#define SC_R_SC_MU_0B 346
-#define SC_R_SC_MU_0A0 347
-#define SC_R_SC_MU_0A1 348
-#define SC_R_SC_MU_0A2 349
-#define SC_R_SC_MU_0A3 350
-#define SC_R_SC_MU_1A 351
-#define SC_R_SYSCNT_RD 352
-#define SC_R_SYSCNT_CMP 353
-#define SC_R_DEBUG 354
-#define SC_R_SYSTEM 355
-#define SC_R_SNVS 356
-#define SC_R_OTP 357
-#define SC_R_VPU_PID0 358
-#define SC_R_VPU_PID1 359
-#define SC_R_VPU_PID2 360
-#define SC_R_VPU_PID3 361
-#define SC_R_VPU_PID4 362
-#define SC_R_VPU_PID5 363
-#define SC_R_VPU_PID6 364
-#define SC_R_VPU_PID7 365
-#define SC_R_VPU_UART 366
-#define SC_R_VPUCORE 367
-#define SC_R_VPUCORE_0 368
-#define SC_R_VPUCORE_1 369
-#define SC_R_VPUCORE_2 370
-#define SC_R_VPUCORE_3 371
-#define SC_R_DMA_4_CH0 372
-#define SC_R_DMA_4_CH1 373
-#define SC_R_DMA_4_CH2 374
-#define SC_R_DMA_4_CH3 375
-#define SC_R_DMA_4_CH4 376
-#define SC_R_ISI_CH0 377
-#define SC_R_ISI_CH1 378
-#define SC_R_ISI_CH2 379
-#define SC_R_ISI_CH3 380
-#define SC_R_ISI_CH4 381
-#define SC_R_ISI_CH5 382
-#define SC_R_ISI_CH6 383
-#define SC_R_ISI_CH7 384
-#define SC_R_MJPEG_DEC_S0 385
-#define SC_R_MJPEG_DEC_S1 386
-#define SC_R_MJPEG_DEC_S2 387
-#define SC_R_MJPEG_DEC_S3 388
-#define SC_R_MJPEG_ENC_S0 389
-#define SC_R_MJPEG_ENC_S1 390
-#define SC_R_MJPEG_ENC_S2 391
-#define SC_R_MJPEG_ENC_S3 392
-#define SC_R_MIPI_0 393
-#define SC_R_MIPI_0_PWM_0 394
-#define SC_R_MIPI_0_I2C_0 395
-#define SC_R_MIPI_0_I2C_1 396
-#define SC_R_MIPI_1 397
-#define SC_R_MIPI_1_PWM_0 398
-#define SC_R_MIPI_1_I2C_0 399
-#define SC_R_MIPI_1_I2C_1 400
-#define SC_R_CSI_0 401
-#define SC_R_CSI_0_PWM_0 402
-#define SC_R_CSI_0_I2C_0 403
-#define SC_R_CSI_1 404
-#define SC_R_CSI_1_PWM_0 405
-#define SC_R_CSI_1_I2C_0 406
-#define SC_R_HDMI 407
-#define SC_R_HDMI_I2S 408
-#define SC_R_HDMI_I2C_0 409
-#define SC_R_HDMI_PLL_0 410
-#define SC_R_HDMI_RX 411
-#define SC_R_HDMI_RX_BYPASS 412
-#define SC_R_HDMI_RX_I2C_0 413
-#define SC_R_ASRC_0 414
-#define SC_R_ESAI_0 415
-#define SC_R_SPDIF_0 416
-#define SC_R_SPDIF_1 417
-#define SC_R_SAI_3 418
-#define SC_R_SAI_4 419
-#define SC_R_SAI_5 420
-#define SC_R_GPT_5 421
-#define SC_R_GPT_6 422
-#define SC_R_GPT_7 423
-#define SC_R_GPT_8 424
-#define SC_R_GPT_9 425
-#define SC_R_GPT_10 426
-#define SC_R_DMA_2_CH5 427
-#define SC_R_DMA_2_CH6 428
-#define SC_R_DMA_2_CH7 429
-#define SC_R_DMA_2_CH8 430
-#define SC_R_DMA_2_CH9 431
-#define SC_R_DMA_2_CH10 432
-#define SC_R_DMA_2_CH11 433
-#define SC_R_DMA_2_CH12 434
-#define SC_R_DMA_2_CH13 435
-#define SC_R_DMA_2_CH14 436
-#define SC_R_DMA_2_CH15 437
-#define SC_R_DMA_2_CH16 438
-#define SC_R_DMA_2_CH17 439
-#define SC_R_DMA_2_CH18 440
-#define SC_R_DMA_2_CH19 441
-#define SC_R_DMA_2_CH20 442
-#define SC_R_DMA_2_CH21 443
-#define SC_R_DMA_2_CH22 444
-#define SC_R_DMA_2_CH23 445
-#define SC_R_DMA_2_CH24 446
-#define SC_R_DMA_2_CH25 447
-#define SC_R_DMA_2_CH26 448
-#define SC_R_DMA_2_CH27 449
-#define SC_R_DMA_2_CH28 450
-#define SC_R_DMA_2_CH29 451
-#define SC_R_DMA_2_CH30 452
-#define SC_R_DMA_2_CH31 453
-#define SC_R_ASRC_1 454
-#define SC_R_ESAI_1 455
-#define SC_R_SAI_6 456
-#define SC_R_SAI_7 457
-#define SC_R_AMIX 458
-#define SC_R_MQS_0 459
-#define SC_R_DMA_3_CH0 460
-#define SC_R_DMA_3_CH1 461
-#define SC_R_DMA_3_CH2 462
-#define SC_R_DMA_3_CH3 463
-#define SC_R_DMA_3_CH4 464
-#define SC_R_DMA_3_CH5 465
-#define SC_R_DMA_3_CH6 466
-#define SC_R_DMA_3_CH7 467
-#define SC_R_DMA_3_CH8 468
-#define SC_R_DMA_3_CH9 469
-#define SC_R_DMA_3_CH10 470
-#define SC_R_DMA_3_CH11 471
-#define SC_R_DMA_3_CH12 472
-#define SC_R_DMA_3_CH13 473
-#define SC_R_DMA_3_CH14 474
-#define SC_R_DMA_3_CH15 475
-#define SC_R_DMA_3_CH16 476
-#define SC_R_DMA_3_CH17 477
-#define SC_R_DMA_3_CH18 478
-#define SC_R_DMA_3_CH19 479
-#define SC_R_DMA_3_CH20 480
-#define SC_R_DMA_3_CH21 481
-#define SC_R_DMA_3_CH22 482
-#define SC_R_DMA_3_CH23 483
-#define SC_R_DMA_3_CH24 484
-#define SC_R_DMA_3_CH25 485
-#define SC_R_DMA_3_CH26 486
-#define SC_R_DMA_3_CH27 487
-#define SC_R_DMA_3_CH28 488
-#define SC_R_DMA_3_CH29 489
-#define SC_R_DMA_3_CH30 490
-#define SC_R_DMA_3_CH31 491
-#define SC_R_AUDIO_PLL_1 492
-#define SC_R_AUDIO_CLK_0 493
-#define SC_R_AUDIO_CLK_1 494
-#define SC_R_MCLK_OUT_0 495
-#define SC_R_MCLK_OUT_1 496
-#define SC_R_PMIC_0 497
-#define SC_R_PMIC_1 498
-#define SC_R_SECO 499
-#define SC_R_CAAM_JR1 500
-#define SC_R_CAAM_JR2 501
-#define SC_R_CAAM_JR3 502
-#define SC_R_SECO_MU_2 503
-#define SC_R_SECO_MU_3 504
-#define SC_R_SECO_MU_4 505
-#define SC_R_HDMI_RX_PWM_0 506
-#define SC_R_A35 507
-#define SC_R_A35_0 508
-#define SC_R_A35_1 509
-#define SC_R_A35_2 510
-#define SC_R_A35_3 511
-#define SC_R_DSP 512
-#define SC_R_DSP_RAM 513
-#define SC_R_CAAM_JR1_OUT 514
-#define SC_R_CAAM_JR2_OUT 515
-#define SC_R_CAAM_JR3_OUT 516
-#define SC_R_VPU_DEC_0 517
-#define SC_R_VPU_ENC_0 518
-#define SC_R_CAAM_JR0 519
-#define SC_R_CAAM_JR0_OUT 520
-#define SC_R_PMIC_2 521
-#define SC_R_DBLOGIC 522
-#define SC_R_HDMI_PLL_1 523
-#define SC_R_BOARD_R0 524
-#define SC_R_BOARD_R1 525
-#define SC_R_BOARD_R2 526
-#define SC_R_BOARD_R3 527
-#define SC_R_BOARD_R4 528
-#define SC_R_BOARD_R5 529
-#define SC_R_BOARD_R6 530
-#define SC_R_BOARD_R7 531
-#define SC_R_MJPEG_DEC_MP 532
-#define SC_R_MJPEG_ENC_MP 533
-#define SC_R_VPU_TS_0 534
-#define SC_R_VPU_MU_0 535
-#define SC_R_VPU_MU_1 536
-#define SC_R_VPU_MU_2 537
-#define SC_R_VPU_MU_3 538
-#define SC_R_VPU_ENC_1 539
-#define SC_R_VPU 540
-#define SC_R_LAST 541
-
-#endif /* DT_BINDINGS_RSCRC_IMX_H */
diff --git a/include/dt-bindings/soc/ti,sci_pm_domain.h b/include/dt-bindings/soc/ti,sci_pm_domain.h
deleted file mode 100644
index 8f2a736..0000000
--- a/include/dt-bindings/soc/ti,sci_pm_domain.h
+++ /dev/null
@@ -1,9 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-
-#ifndef __DT_BINDINGS_TI_SCI_PM_DOMAIN_H
-#define __DT_BINDINGS_TI_SCI_PM_DOMAIN_H
-
-#define TI_SCI_PD_EXCLUSIVE 1
-#define TI_SCI_PD_SHARED 0
-
-#endif /* __DT_BINDINGS_TI_SCI_PM_DOMAIN_H */
diff --git a/include/dt-bindings/sound/azalia.h b/include/dt-bindings/sound/azalia.h
deleted file mode 100644
index 10ace3e..0000000
--- a/include/dt-bindings/sound/azalia.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Intel HDA audio codec config. This is a mechanicm to configure codecs when
- * using Intel HDA audio.
- *
- * Copyright 2018 Google LLC
- * Written by Simon Glass <sjg@chromium.org>
- */
-
-#ifndef __AZALIA_H
-#define __AZALIA_H
-
-#define AZALIA_CODEC_SHIFT 28
-#define AZALIA_NID_SHIFT 20
-#define AZALIA_VERB_SHIFT 8
-
-/* Supported opcodes */
-#define AZALIA_OPCODE_CONFIG_DEFAULT 0x71c
-#define AZALIA_OPCODE_IMPL_ID 0x720
-#define AZALIA_OPCODE_READ_PARAM 0xf00
-
-#define AZALIA_PARAM_VENDOR_ID 0
-
-/* Generate the register value to write a particular byte of a 32-bit value */
-#define AZALIA_SET_BYTE(codec, nid, opcode, val, byte) \
- ((codec) << AZALIA_CODEC_SHIFT | \
- (nid) << AZALIA_NID_SHIFT | \
- ((opcode) + (byte)) << AZALIA_VERB_SHIFT | \
- (((val) >> ((byte) * 8)) & 0xff))
-
-/* Generate the register value to write all bytes of a 32-bit value */
-#define AZALIA_WORD(codec, nid, opcode, val) \
- (AZALIA_SET_BYTE(codec, nid, opcode, val, 0) | \
- AZALIA_SET_BYTE(codec, nid, opcode, val, 1) | \
- AZALIA_SET_BYTE(codec, nid, opcode, val, 2) | \
- AZALIA_SET_BYTE(codec, nid, opcode, val, 3))
-
-#define AZALIA_PIN_CFG(codec, nid, val) \
- AZALIA_WORD(codec, nid, AZALIA_OPCODE_CONFIG_DEFAULT, val)
-
-#define AZALIA_SUBVENDOR(codec, val) \
- AZALIA_WORD(codec, 1, AZALIA_OPCODE_IMPL_ID, val)
-
-#endif /* __AZALIA_H */
diff --git a/include/dt-bindings/sound/meson-g12a-tohdmitx.h b/include/dt-bindings/sound/meson-g12a-tohdmitx.h
deleted file mode 100644
index c5e1f48..0000000
--- a/include/dt-bindings/sound/meson-g12a-tohdmitx.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __DT_MESON_G12A_TOHDMITX_H
-#define __DT_MESON_G12A_TOHDMITX_H
-
-#define TOHDMITX_I2S_IN_A 0
-#define TOHDMITX_I2S_IN_B 1
-#define TOHDMITX_I2S_IN_C 2
-#define TOHDMITX_I2S_OUT 3
-#define TOHDMITX_SPDIF_IN_A 4
-#define TOHDMITX_SPDIF_IN_B 5
-#define TOHDMITX_SPDIF_OUT 6
-
-#endif /* __DT_MESON_G12A_TOHDMITX_H */
diff --git a/include/dt-bindings/sound/tlv320aic31xx-micbias.h b/include/dt-bindings/sound/tlv320aic31xx-micbias.h
deleted file mode 100644
index f5cb772..0000000
--- a/include/dt-bindings/sound/tlv320aic31xx-micbias.h
+++ /dev/null
@@ -1,8 +0,0 @@
-#ifndef __DT_TLV320AIC31XX_MICBIAS_H
-#define __DT_TLV320AIC31XX_MICBIAS_H
-
-#define MICBIAS_2_0V 1
-#define MICBIAS_2_5V 2
-#define MICBIAS_AVDDV 3
-
-#endif /* __DT_TLV320AIC31XX_MICBIAS_H */
diff --git a/include/dt-bindings/thermal/tegra124-soctherm.h b/include/dt-bindings/thermal/tegra124-soctherm.h
deleted file mode 100644
index 729ab9f..0000000
--- a/include/dt-bindings/thermal/tegra124-soctherm.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * This header provides constants for binding nvidia,tegra124-soctherm.
- */
-
-#ifndef _DT_BINDINGS_THERMAL_TEGRA124_SOCTHERM_H
-#define _DT_BINDINGS_THERMAL_TEGRA124_SOCTHERM_H
-
-#define TEGRA124_SOCTHERM_SENSOR_CPU 0
-#define TEGRA124_SOCTHERM_SENSOR_MEM 1
-#define TEGRA124_SOCTHERM_SENSOR_GPU 2
-#define TEGRA124_SOCTHERM_SENSOR_PLLX 3
-#define TEGRA124_SOCTHERM_SENSOR_NUM 4
-
-#endif
diff --git a/include/dt-bindings/thermal/thermal.h b/include/dt-bindings/thermal/thermal.h
deleted file mode 100644
index b5e6b00..0000000
--- a/include/dt-bindings/thermal/thermal.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/*
- * This header provides constants for most thermal bindings.
- *
- * Copyright (C) 2013 Texas Instruments
- * Eduardo Valentin <eduardo.valentin@ti.com>
- *
- * GPLv2 only
- */
-
-#ifndef _DT_BINDINGS_THERMAL_THERMAL_H
-#define _DT_BINDINGS_THERMAL_THERMAL_H
-
-/* On cooling devices upper and lower limits */
-#define THERMAL_NO_LIMIT (~0)
-
-#endif
-
diff --git a/include/dt-bindings/video/rk3288.h b/include/dt-bindings/video/rk3288.h
deleted file mode 100644
index 7bfd247..0000000
--- a/include/dt-bindings/video/rk3288.h
+++ /dev/null
@@ -1,11 +0,0 @@
-#ifndef __DT_BINDINGS_VIDEO_RK3288_H__
-#define __DT_BINDINGS_VIDEO_RK3288_H__
-
-#define LVDS_OUTPUT_RGB 0
-#define LVDS_OUTPUT_SINGLE 1
-#define LVDS_OUTPUT_DUAL 2
-
-#define LVDS_FORMAT_VESA 0
-#define LVDS_FORMAT_JEIDA 1
-
-#endif