diff options
Diffstat (limited to 'arch/arm/include/asm/arch-am33xx')
25 files changed, 3271 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-am33xx/chilisom.h b/arch/arm/include/asm/arch-am33xx/chilisom.h new file mode 100644 index 0000000..493be64 --- /dev/null +++ b/arch/arm/include/asm/arch-am33xx/chilisom.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2017 Grinn + */ + +#ifndef __ARCH_ARM_MACH_CHILISOM_SOM_H__ +#define __ARCH_ARM_MACH_CHILISOM_SOM_H__ + +#ifndef CONFIG_SKIP_LOWLEVEL_INIT +void chilisom_enable_pin_mux(void); +void chilisom_spl_board_init(void); +#endif + +#endif diff --git a/arch/arm/include/asm/arch-am33xx/clk_synthesizer.h b/arch/arm/include/asm/arch-am33xx/clk_synthesizer.h new file mode 100644 index 0000000..6579cc0 --- /dev/null +++ b/arch/arm/include/asm/arch-am33xx/clk_synthesizer.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * clk-synthesizer.h + * + * Clock synthesizer header + * + * Copyright (C) 2016, Texas Instruments, Incorporated - http://www.ti.com/ + */ + +#ifndef __CLK_SYNTHESIZER_H +#define __CLK_SYNTHESIZER_H + +#include <common.h> + +#define CLK_SYNTHESIZER_ID_REG 0x0 +#define CLK_SYNTHESIZER_XCSEL 0x05 +#define CLK_SYNTHESIZER_MUX_REG 0x14 +#define CLK_SYNTHESIZER_PDIV2_REG 0x16 +#define CLK_SYNTHESIZER_PDIV3_REG 0x17 + +#define CLK_SYNTHESIZER_BYTE_MODE 0x80 + +/** + * struct clk_synth: This structure holds data neeed for configuring + * for clock synthesizer. + * @id: The id of synthesizer + * @capacitor: value of the capacitor attached + * @mux: mux settings. + * @pdiv2: Div to be applied to second output + * @pdiv3: Div to be applied to third output + */ +struct clk_synth { + u32 id; + u32 capacitor; + u32 mux; + u32 pdiv2; + u32 pdiv3; +}; + +int setup_clock_synthesizer(struct clk_synth *data); + +#endif diff --git a/arch/arm/include/asm/arch-am33xx/clock.h b/arch/arm/include/asm/arch-am33xx/clock.h new file mode 100644 index 0000000..dc7a9b1 --- /dev/null +++ b/arch/arm/include/asm/arch-am33xx/clock.h @@ -0,0 +1,134 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * clock.h + * + * clock header + * + * Copyright (C) 2011, Texas Instruments Incorporated - http://www.ti.com/ + */ + +#ifndef _CLOCKS_H_ +#define _CLOCKS_H_ + +#include <asm/arch/clocks_am33xx.h> +#include <asm/arch/hardware.h> + +#if defined(CONFIG_TI816X) || defined(CONFIG_TI814X) +#include <asm/arch/clock_ti81xx.h> +#endif + +#define LDELAY 1000000 + +/*CM_<clock_domain>__CLKCTRL */ +#define CD_CLKCTRL_CLKTRCTRL_SHIFT 0 +#define CD_CLKCTRL_CLKTRCTRL_MASK 3 + +#define CD_CLKCTRL_CLKTRCTRL_NO_SLEEP 0 +#define CD_CLKCTRL_CLKTRCTRL_SW_SLEEP 1 +#define CD_CLKCTRL_CLKTRCTRL_SW_WKUP 2 + +/* CM_<clock_domain>_<module>_CLKCTRL */ +#define MODULE_CLKCTRL_MODULEMODE_SHIFT 0 +#define MODULE_CLKCTRL_MODULEMODE_MASK 3 +#define MODULE_CLKCTRL_IDLEST_SHIFT 16 +#define MODULE_CLKCTRL_IDLEST_MASK (3 << 16) + +#define MODULE_CLKCTRL_MODULEMODE_SW_DISABLE 0 +#define MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN 2 + +#define MODULE_CLKCTRL_IDLEST_FULLY_FUNCTIONAL 0 +#define MODULE_CLKCTRL_IDLEST_TRANSITIONING 1 +#define MODULE_CLKCTRL_IDLEST_IDLE 2 +#define MODULE_CLKCTRL_IDLEST_DISABLED 3 + +/* CM_CLKMODE_DPLL */ +#define CM_CLKMODE_DPLL_SSC_EN_SHIFT 12 +#define CM_CLKMODE_DPLL_SSC_EN_MASK (1 << 12) +#define CM_CLKMODE_DPLL_SSC_ACK_MASK (1 << 13) +#define CM_CLKMODE_DPLL_SSC_DOWNSPREAD_MASK (1 << 14) +#define CM_CLKMODE_DPLL_SSC_TYPE_MASK (1 << 15) +#define CM_CLKMODE_DPLL_REGM4XEN_SHIFT 11 +#define CM_CLKMODE_DPLL_REGM4XEN_MASK (1 << 11) +#define CM_CLKMODE_DPLL_LPMODE_EN_SHIFT 10 +#define CM_CLKMODE_DPLL_LPMODE_EN_MASK (1 << 10) +#define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_SHIFT 9 +#define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK (1 << 9) +#define CM_CLKMODE_DPLL_DRIFTGUARD_EN_SHIFT 8 +#define CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK (1 << 8) +#define CM_CLKMODE_DPLL_RAMP_RATE_SHIFT 5 +#define CM_CLKMODE_DPLL_RAMP_RATE_MASK (0x7 << 5) +#define CM_CLKMODE_DPLL_EN_SHIFT 0 +#define CM_CLKMODE_DPLL_EN_MASK (0x7 << 0) + +#define CM_CLKMODE_DPLL_DPLL_EN_SHIFT 0 +#define CM_CLKMODE_DPLL_DPLL_EN_MASK 7 + +#define DPLL_EN_STOP 1 +#define DPLL_EN_MN_BYPASS 4 +#define DPLL_EN_LOW_POWER_BYPASS 5 +#define DPLL_EN_LOCK 7 + +/* CM_IDLEST_DPLL fields */ +#define ST_DPLL_CLK_MASK 1 + +/* CM_CLKSEL_DPLL */ +#define CM_CLKSEL_DPLL_M_SHIFT 8 +#define CM_CLKSEL_DPLL_M_MASK (0x7FF << 8) +#define CM_CLKSEL_DPLL_N_SHIFT 0 +#define CM_CLKSEL_DPLL_N_MASK 0x7F + +struct dpll_params { + u32 m; + u32 n; + s8 m2; + s8 m3; + s8 m4; + s8 m5; + s8 m6; +}; + +struct dpll_regs { + u32 cm_clkmode_dpll; + u32 cm_idlest_dpll; + u32 cm_autoidle_dpll; + u32 cm_clksel_dpll; + u32 cm_div_m2_dpll; + u32 cm_div_m3_dpll; + u32 cm_div_m4_dpll; + u32 cm_div_m5_dpll; + u32 cm_div_m6_dpll; +}; + +extern const struct dpll_regs dpll_mpu_regs; +extern const struct dpll_regs dpll_core_regs; +extern const struct dpll_regs dpll_per_regs; +extern const struct dpll_regs dpll_ddr_regs; +extern const struct dpll_regs dpll_disp_regs; +extern const struct dpll_params dpll_mpu_opp[NUM_CRYSTAL_FREQ][NUM_OPPS]; +extern const struct dpll_params dpll_core_1000MHz[NUM_CRYSTAL_FREQ]; +extern const struct dpll_params dpll_per_192MHz[NUM_CRYSTAL_FREQ]; +extern const struct dpll_params dpll_ddr2_266MHz[NUM_CRYSTAL_FREQ]; +extern const struct dpll_params dpll_ddr3_303MHz[NUM_CRYSTAL_FREQ]; +extern const struct dpll_params dpll_ddr3_400MHz[NUM_CRYSTAL_FREQ]; + +extern struct cm_wkuppll *const cmwkup; + +const struct dpll_params *get_dpll_mpu_params(void); +const struct dpll_params *get_dpll_core_params(void); +const struct dpll_params *get_dpll_per_params(void); +const struct dpll_params *get_dpll_ddr_params(void); +void scale_vcores(void); +void do_setup_dpll(const struct dpll_regs *, const struct dpll_params *); +void prcm_init(void); +void enable_basic_clocks(void); + +void rtc_only_update_board_type(u32 btype); +u32 rtc_only_get_board_type(void); +void rtc_only_prcm_init(void); +void rtc_only_enable_basic_clocks(void); + +void do_enable_clocks(u32 *const *, u32 *const *, u8); +void do_disable_clocks(u32 *const *, u32 *const *, u8); + +void set_mpu_spreadspectrum(int permille); +#endif diff --git a/arch/arm/include/asm/arch-am33xx/clock_ti81xx.h b/arch/arm/include/asm/arch-am33xx/clock_ti81xx.h new file mode 100644 index 0000000..f069922 --- /dev/null +++ b/arch/arm/include/asm/arch-am33xx/clock_ti81xx.h @@ -0,0 +1,142 @@ +/* + * ti81xx.h + * + * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com> + * Antoine Tenart, <atenart@adeneo-embedded.com> + * + * This file is released under the terms of GPL v2 and any later version. + * See the file COPYING in the root directory of the source tree for details. + */ + +#ifndef _CLOCK_TI81XX_H_ +#define _CLOCK_TI81XX_H_ + +#define PRCM_MOD_EN 0x2 + +#define CM_DEFAULT_BASE (PRCM_BASE + 0x0500) +#define CM_ALWON_BASE (PRCM_BASE + 0x1400) + +struct cm_def { + unsigned int resv0[2]; + unsigned int l3fastclkstctrl; + unsigned int resv1[1]; + unsigned int pciclkstctrl; + unsigned int resv2[1]; + unsigned int ducaticlkstctrl; + unsigned int resv3[1]; + unsigned int emif0clkctrl; + unsigned int emif1clkctrl; + unsigned int dmmclkctrl; + unsigned int fwclkctrl; + unsigned int resv4[10]; + unsigned int usbclkctrl; + unsigned int resv5[1]; + unsigned int sataclkctrl; + unsigned int resv6[4]; + unsigned int ducaticlkctrl; + unsigned int pciclkctrl; +}; + +struct cm_alwon { + unsigned int l3slowclkstctrl; + unsigned int ethclkstctrl; + unsigned int l3medclkstctrl; + unsigned int mmu_clkstctrl; + unsigned int mmucfg_clkstctrl; + unsigned int ocmc0clkstctrl; +#if defined(CONFIG_TI814X) + unsigned int vcpclkstctrl; +#elif defined(CONFIG_TI816X) + unsigned int ocmc1clkstctrl; +#endif + unsigned int mpuclkstctrl; + unsigned int sysclk4clkstctrl; + unsigned int sysclk5clkstctrl; + unsigned int sysclk6clkstctrl; + unsigned int rtcclkstctrl; + unsigned int l3fastclkstctrl; + unsigned int resv0[67]; + unsigned int mcasp0clkctrl; + unsigned int mcasp1clkctrl; + unsigned int mcasp2clkctrl; + unsigned int mcbspclkctrl; + unsigned int uart0clkctrl; + unsigned int uart1clkctrl; + unsigned int uart2clkctrl; + unsigned int gpio0clkctrl; + unsigned int gpio1clkctrl; + unsigned int i2c0clkctrl; + unsigned int i2c1clkctrl; +#if defined(CONFIG_TI814X) + unsigned int mcasp345clkctrl; + unsigned int atlclkctrl; + unsigned int mlbclkctrl; + unsigned int pataclkctrl; + unsigned int resv1[1]; + unsigned int uart3clkctrl; + unsigned int uart4clkctrl; + unsigned int uart5clkctrl; +#elif defined(CONFIG_TI816X) + unsigned int resv1[1]; + unsigned int timer1clkctrl; + unsigned int timer2clkctrl; + unsigned int timer3clkctrl; + unsigned int timer4clkctrl; + unsigned int timer5clkctrl; + unsigned int timer6clkctrl; + unsigned int timer7clkctrl; +#endif + unsigned int wdtimerclkctrl; + unsigned int spiclkctrl; + unsigned int mailboxclkctrl; + unsigned int spinboxclkctrl; + unsigned int mmudataclkctrl; + unsigned int resv2[2]; + unsigned int mmucfgclkctrl; +#if defined(CONFIG_TI814X) + unsigned int resv3[2]; +#elif defined(CONFIG_TI816X) + unsigned int resv3[1]; + unsigned int sdioclkctrl; +#endif + unsigned int ocmc0clkctrl; +#if defined(CONFIG_TI814X) + unsigned int vcpclkctrl; +#elif defined(CONFIG_TI816X) + unsigned int ocmc1clkctrl; +#endif + unsigned int resv4[2]; + unsigned int controlclkctrl; + unsigned int resv5[2]; + unsigned int gpmcclkctrl; + unsigned int ethernet0clkctrl; + unsigned int ethernet1clkctrl; + unsigned int mpuclkctrl; +#if defined(CONFIG_TI814X) + unsigned int debugssclkctrl; +#elif defined(CONFIG_TI816X) + unsigned int resv6[1]; +#endif + unsigned int l3clkctrl; + unsigned int l4hsclkctrl; + unsigned int l4lsclkctrl; + unsigned int rtcclkctrl; + unsigned int tpccclkctrl; + unsigned int tptc0clkctrl; + unsigned int tptc1clkctrl; + unsigned int tptc2clkctrl; + unsigned int tptc3clkctrl; +#if defined(CONFIG_TI814X) + unsigned int resv6[4]; + unsigned int dcan01clkctrl; + unsigned int mmchs0clkctrl; + unsigned int mmchs1clkctrl; + unsigned int mmchs2clkctrl; + unsigned int custefuseclkctrl; +#elif defined(CONFIG_TI816X) + unsigned int sr0clkctrl; + unsigned int sr1clkctrl; +#endif +}; + +#endif /* _CLOCK_TI81XX_H_ */ diff --git a/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h b/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h new file mode 100644 index 0000000..e5ad507 --- /dev/null +++ b/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * clocks_am33xx.h + * + * AM33xx clock define + * + * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ + */ + +#ifndef _CLOCKS_AM33XX_H_ +#define _CLOCKS_AM33XX_H_ + +/* MAIN PLL Fdll supported frequencies */ +#define MPUPLL_M_1000 1000 +#define MPUPLL_M_800 800 +#define MPUPLL_M_720 720 +#define MPUPLL_M_600 600 +#define MPUPLL_M_500 500 +#define MPUPLL_M_300 300 + +#define UART_RESET (0x1 << 1) +#define UART_CLK_RUNNING_MASK 0x1 +#define UART_SMART_IDLE_EN (0x1 << 0x3) + +#define CM_DLL_CTRL_NO_OVERRIDE 0x0 +#define CM_DLL_READYST 0x4 + +#define NUM_OPPS 6 + +extern void enable_dmm_clocks(void); +extern void enable_emif_clocks(void); +extern const struct dpll_params dpll_core_opp100; +extern struct dpll_params dpll_mpu_opp100; + +#endif /* endif _CLOCKS_AM33XX_H_ */ diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h new file mode 100644 index 0000000..9b819b0 --- /dev/null +++ b/arch/arm/include/asm/arch-am33xx/cpu.h @@ -0,0 +1,611 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * cpu.h + * + * AM33xx specific header file + * + * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ + */ + +#ifndef _AM33XX_CPU_H +#define _AM33XX_CPU_H + +#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) +#include <asm/types.h> +#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */ + +#include <asm/arch/hardware.h> + +#define CL_BIT(x) (0 << x) + +/* Timer register bits */ +#define TCLR_ST BIT(0) /* Start=1 Stop=0 */ +#define TCLR_AR BIT(1) /* Auto reload */ +#define TCLR_PRE BIT(5) /* Pre-scaler enable */ +#define TCLR_PTV_SHIFT (2) /* Pre-scaler shift value */ +#define TCLR_PRE_DISABLE CL_BIT(5) /* Pre-scalar disable */ +#define TCLR_CE BIT(6) /* compare mode enable */ +#define TCLR_SCPWM BIT(7) /* pwm outpin behaviour */ +#define TCLR_TCM BIT(8) /* edge detection of input pin*/ +#define TCLR_TRG_SHIFT (10) /* trigmode on pwm outpin */ +#define TCLR_PT BIT(12) /* pulse/toggle mode of outpin*/ +#define TCLR_CAPTMODE BIT(13) /* capture mode */ +#define TCLR_GPOCFG BIT(14) /* 0=output,1=input */ + +#define TCFG_RESET BIT(0) /* software reset */ +#define TCFG_EMUFREE BIT(1) /* behaviour of tmr on debug */ +#define TCFG_IDLEMOD_SHIFT (2) /* power management */ + +/* cpu-id for AM43XX AM33XX and TI81XX family */ +#define AM437X 0xB98C +#define AM335X 0xB944 +#define TI81XX 0xB81E +#define DEVICE_ID (CTRL_BASE + 0x0600) +#define DEVICE_ID_MASK 0x1FFF +#define PACKAGE_TYPE_SHIFT 16 +#define PACKAGE_TYPE_MASK (3 << 16) + +/* Package Type */ +#define PACKAGE_TYPE_UNDEFINED 0x0 +#define PACKAGE_TYPE_ZCZ 0x1 +#define PACKAGE_TYPE_ZCE 0x2 +#define PACKAGE_TYPE_RESERVED 0x3 + +/* MPU max frequencies */ +#define AM335X_ZCZ_300 0x1FEF +#define AM335X_ZCZ_600 0x1FAF +#define AM335X_ZCZ_720 0x1F2F +#define AM335X_ZCZ_800 0x1E2F +#define AM335X_ZCZ_1000 0x1C2F +#define AM335X_ZCE_300 0x1FDF +#define AM335X_ZCE_600 0x1F9F + +/* This gives the status of the boot mode pins on the evm */ +#define SYSBOOT_MASK (BIT(0) | BIT(1) | BIT(2)\ + | BIT(3) | BIT(4)) + +#define PRM_RSTCTRL_RESET 0x01 +#define PRM_RSTST_WARM_RESET_MASK 0x232 + +/* EMIF Control register bits */ +#define EMIF_CTRL_DEVOFF BIT(0) + +#ifndef __KERNEL_STRICT_NAMES +#ifndef __ASSEMBLY__ +#include <asm/ti-common/omap_wdt.h> + +#ifndef CONFIG_AM43XX +/* Encapsulating core pll registers */ +struct cm_wkuppll { + unsigned int wkclkstctrl; /* offset 0x00 */ + unsigned int wkctrlclkctrl; /* offset 0x04 */ + unsigned int wkgpio0clkctrl; /* offset 0x08 */ + unsigned int wkl4wkclkctrl; /* offset 0x0c */ + unsigned int timer0clkctrl; /* offset 0x10 */ + unsigned int resv2[3]; + unsigned int idlestdpllmpu; /* offset 0x20 */ + unsigned int sscdeltamstepdllmpu; /* off 0x24 */ + unsigned int sscmodfreqdivdpllmpu; /* off 0x28 */ + unsigned int clkseldpllmpu; /* offset 0x2c */ + unsigned int resv4[1]; + unsigned int idlestdpllddr; /* offset 0x34 */ + unsigned int resv5[2]; + unsigned int clkseldpllddr; /* offset 0x40 */ + unsigned int resv6[4]; + unsigned int clkseldplldisp; /* offset 0x54 */ + unsigned int resv7[1]; + unsigned int idlestdpllcore; /* offset 0x5c */ + unsigned int resv8[2]; + unsigned int clkseldpllcore; /* offset 0x68 */ + unsigned int resv9[1]; + unsigned int idlestdpllper; /* offset 0x70 */ + unsigned int resv10[2]; + unsigned int clkdcoldodpllper; /* offset 0x7c */ + unsigned int divm4dpllcore; /* offset 0x80 */ + unsigned int divm5dpllcore; /* offset 0x84 */ + unsigned int clkmoddpllmpu; /* offset 0x88 */ + unsigned int clkmoddpllper; /* offset 0x8c */ + unsigned int clkmoddpllcore; /* offset 0x90 */ + unsigned int clkmoddpllddr; /* offset 0x94 */ + unsigned int clkmoddplldisp; /* offset 0x98 */ + unsigned int clkseldpllper; /* offset 0x9c */ + unsigned int divm2dpllddr; /* offset 0xA0 */ + unsigned int divm2dplldisp; /* offset 0xA4 */ + unsigned int divm2dpllmpu; /* offset 0xA8 */ + unsigned int divm2dpllper; /* offset 0xAC */ + unsigned int resv11[1]; + unsigned int wkup_uart0ctrl; /* offset 0xB4 */ + unsigned int wkup_i2c0ctrl; /* offset 0xB8 */ + unsigned int wkup_adctscctrl; /* offset 0xBC */ + unsigned int resv12; + unsigned int timer1clkctrl; /* offset 0xC4 */ + unsigned int resv13[4]; + unsigned int divm6dpllcore; /* offset 0xD8 */ +}; + +/** + * Encapsulating peripheral functional clocks + * pll registers + */ +struct cm_perpll { + unsigned int l4lsclkstctrl; /* offset 0x00 */ + unsigned int l3sclkstctrl; /* offset 0x04 */ + unsigned int l4fwclkstctrl; /* offset 0x08 */ + unsigned int l3clkstctrl; /* offset 0x0c */ + unsigned int resv1; + unsigned int cpgmac0clkctrl; /* offset 0x14 */ + unsigned int lcdclkctrl; /* offset 0x18 */ + unsigned int usb0clkctrl; /* offset 0x1C */ + unsigned int resv2; + unsigned int tptc0clkctrl; /* offset 0x24 */ + unsigned int emifclkctrl; /* offset 0x28 */ + unsigned int ocmcramclkctrl; /* offset 0x2c */ + unsigned int gpmcclkctrl; /* offset 0x30 */ + unsigned int mcasp0clkctrl; /* offset 0x34 */ + unsigned int uart5clkctrl; /* offset 0x38 */ + unsigned int mmc0clkctrl; /* offset 0x3C */ + unsigned int elmclkctrl; /* offset 0x40 */ + unsigned int i2c2clkctrl; /* offset 0x44 */ + unsigned int i2c1clkctrl; /* offset 0x48 */ + unsigned int spi0clkctrl; /* offset 0x4C */ + unsigned int spi1clkctrl; /* offset 0x50 */ + unsigned int resv3[3]; + unsigned int l4lsclkctrl; /* offset 0x60 */ + unsigned int l4fwclkctrl; /* offset 0x64 */ + unsigned int mcasp1clkctrl; /* offset 0x68 */ + unsigned int uart1clkctrl; /* offset 0x6C */ + unsigned int uart2clkctrl; /* offset 0x70 */ + unsigned int uart3clkctrl; /* offset 0x74 */ + unsigned int uart4clkctrl; /* offset 0x78 */ + unsigned int timer7clkctrl; /* offset 0x7C */ + unsigned int timer2clkctrl; /* offset 0x80 */ + unsigned int timer3clkctrl; /* offset 0x84 */ + unsigned int timer4clkctrl; /* offset 0x88 */ + unsigned int resv4[8]; + unsigned int gpio1clkctrl; /* offset 0xAC */ + unsigned int gpio2clkctrl; /* offset 0xB0 */ + unsigned int gpio3clkctrl; /* offset 0xB4 */ + unsigned int resv5; + unsigned int tpccclkctrl; /* offset 0xBC */ + unsigned int dcan0clkctrl; /* offset 0xC0 */ + unsigned int dcan1clkctrl; /* offset 0xC4 */ + unsigned int resv6; + unsigned int epwmss1clkctrl; /* offset 0xCC */ + unsigned int emiffwclkctrl; /* offset 0xD0 */ + unsigned int epwmss0clkctrl; /* offset 0xD4 */ + unsigned int epwmss2clkctrl; /* offset 0xD8 */ + unsigned int l3instrclkctrl; /* offset 0xDC */ + unsigned int l3clkctrl; /* Offset 0xE0 */ + unsigned int resv8[2]; + unsigned int timer5clkctrl; /* offset 0xEC */ + unsigned int timer6clkctrl; /* offset 0xF0 */ + unsigned int mmc1clkctrl; /* offset 0xF4 */ + unsigned int mmc2clkctrl; /* offset 0xF8 */ + unsigned int resv9[8]; + unsigned int l4hsclkstctrl; /* offset 0x11C */ + unsigned int l4hsclkctrl; /* offset 0x120 */ + unsigned int resv10[8]; + unsigned int cpswclkstctrl; /* offset 0x144 */ + unsigned int lcdcclkstctrl; /* offset 0x148 */ +}; + +/* Encapsulating Display pll registers */ +struct cm_dpll { + unsigned int resv1; + unsigned int clktimer7clk; /* offset 0x04 */ + unsigned int clktimer2clk; /* offset 0x08 */ + unsigned int clktimer3clk; /* offset 0x0C */ + unsigned int clktimer4clk; /* offset 0x10 */ + unsigned int resv2; + unsigned int clktimer5clk; /* offset 0x18 */ + unsigned int clktimer6clk; /* offset 0x1C */ + unsigned int resv3[2]; + unsigned int clktimer1clk; /* offset 0x28 */ + unsigned int resv4[2]; + unsigned int clklcdcpixelclk; /* offset 0x34 */ +}; + +struct prm_device_inst { + unsigned int prm_rstctrl; + unsigned int prm_rsttime; + unsigned int prm_rstst; +}; +#else +/* Encapsulating core pll registers */ +struct cm_wkuppll { + unsigned int resv0[136]; + unsigned int wkl4wkclkctrl; /* offset 0x220 */ + unsigned int resv1[7]; + unsigned int usbphy0clkctrl; /* offset 0x240 */ + unsigned int resv112; + unsigned int usbphy1clkctrl; /* offset 0x248 */ + unsigned int resv113[45]; + unsigned int wkclkstctrl; /* offset 0x300 */ + unsigned int resv2[15]; + unsigned int wkup_i2c0ctrl; /* offset 0x340 */ + unsigned int resv3; + unsigned int wkup_uart0ctrl; /* offset 0x348 */ + unsigned int resv4[5]; + unsigned int wkctrlclkctrl; /* offset 0x360 */ + unsigned int resv5; + unsigned int wkgpio0clkctrl; /* offset 0x368 */ + + unsigned int resv6[109]; + unsigned int clkmoddpllcore; /* offset 0x520 */ + unsigned int idlestdpllcore; /* offset 0x524 */ + unsigned int resv61; + unsigned int clkseldpllcore; /* offset 0x52C */ + unsigned int resv7[2]; + unsigned int divm4dpllcore; /* offset 0x538 */ + unsigned int divm5dpllcore; /* offset 0x53C */ + unsigned int divm6dpllcore; /* offset 0x540 */ + + unsigned int resv8[7]; + unsigned int clkmoddpllmpu; /* offset 0x560 */ + unsigned int idlestdpllmpu; /* offset 0x564 */ + unsigned int resv9; + unsigned int clkseldpllmpu; /* offset 0x56c */ + unsigned int divm2dpllmpu; /* offset 0x570 */ + + unsigned int resv10[11]; + unsigned int clkmoddpllddr; /* offset 0x5A0 */ + unsigned int idlestdpllddr; /* offset 0x5A4 */ + unsigned int resv11; + unsigned int clkseldpllddr; /* offset 0x5AC */ + unsigned int divm2dpllddr; /* offset 0x5B0 */ + + unsigned int resv12[11]; + unsigned int clkmoddpllper; /* offset 0x5E0 */ + unsigned int idlestdpllper; /* offset 0x5E4 */ + unsigned int resv13; + unsigned int clkseldpllper; /* offset 0x5EC */ + unsigned int divm2dpllper; /* offset 0x5F0 */ + unsigned int resv14[8]; + unsigned int clkdcoldodpllper; /* offset 0x614 */ + + unsigned int resv15[2]; + unsigned int clkmoddplldisp; /* offset 0x620 */ + unsigned int resv16[2]; + unsigned int clkseldplldisp; /* offset 0x62C */ + unsigned int divm2dplldisp; /* offset 0x630 */ +}; + +/* + * Encapsulating peripheral functional clocks + * pll registers + */ +struct cm_perpll { + unsigned int l3clkstctrl; /* offset 0x00 */ + unsigned int resv0[7]; + unsigned int l3clkctrl; /* Offset 0x20 */ + unsigned int resv112[7]; + unsigned int l3instrclkctrl; /* offset 0x40 */ + unsigned int resv2[3]; + unsigned int ocmcramclkctrl; /* offset 0x50 */ + unsigned int resv3[9]; + unsigned int tpccclkctrl; /* offset 0x78 */ + unsigned int resv4; + unsigned int tptc0clkctrl; /* offset 0x80 */ + + unsigned int resv5[7]; + unsigned int l4hsclkctrl; /* offset 0x0A0 */ + unsigned int resv6; + unsigned int l4fwclkctrl; /* offset 0x0A8 */ + unsigned int resv7[85]; + unsigned int l3sclkstctrl; /* offset 0x200 */ + unsigned int resv8[7]; + unsigned int gpmcclkctrl; /* offset 0x220 */ + unsigned int resv9[5]; + unsigned int mcasp0clkctrl; /* offset 0x238 */ + unsigned int resv10; + unsigned int mcasp1clkctrl; /* offset 0x240 */ + unsigned int resv11; + unsigned int mmc2clkctrl; /* offset 0x248 */ + unsigned int resv12[3]; + unsigned int qspiclkctrl; /* offset 0x258 */ + unsigned int resv121; + unsigned int usb0clkctrl; /* offset 0x260 */ + unsigned int resv122; + unsigned int usb1clkctrl; /* offset 0x268 */ + unsigned int resv13[101]; + unsigned int l4lsclkstctrl; /* offset 0x400 */ + unsigned int resv14[7]; + unsigned int l4lsclkctrl; /* offset 0x420 */ + unsigned int resv15; + unsigned int dcan0clkctrl; /* offset 0x428 */ + unsigned int resv16; + unsigned int dcan1clkctrl; /* offset 0x430 */ + unsigned int resv17[13]; + unsigned int elmclkctrl; /* offset 0x468 */ + + unsigned int resv18[3]; + unsigned int gpio1clkctrl; /* offset 0x478 */ + unsigned int resv19; + unsigned int gpio2clkctrl; /* offset 0x480 */ + unsigned int resv20; + unsigned int gpio3clkctrl; /* offset 0x488 */ + unsigned int resv41; + unsigned int gpio4clkctrl; /* offset 0x490 */ + unsigned int resv42; + unsigned int gpio5clkctrl; /* offset 0x498 */ + unsigned int resv21[3]; + + unsigned int i2c1clkctrl; /* offset 0x4A8 */ + unsigned int resv22; + unsigned int i2c2clkctrl; /* offset 0x4B0 */ + unsigned int resv23[3]; + unsigned int mmc0clkctrl; /* offset 0x4C0 */ + unsigned int resv24; + unsigned int mmc1clkctrl; /* offset 0x4C8 */ + + unsigned int resv25[13]; + unsigned int spi0clkctrl; /* offset 0x500 */ + unsigned int resv26; + unsigned int spi1clkctrl; /* offset 0x508 */ + unsigned int resv27[9]; + unsigned int timer2clkctrl; /* offset 0x530 */ + unsigned int resv28; + unsigned int timer3clkctrl; /* offset 0x538 */ + unsigned int resv29; + unsigned int timer4clkctrl; /* offset 0x540 */ + unsigned int resv30[5]; + unsigned int timer7clkctrl; /* offset 0x558 */ + + unsigned int resv31[9]; + unsigned int uart1clkctrl; /* offset 0x580 */ + unsigned int resv32; + unsigned int uart2clkctrl; /* offset 0x588 */ + unsigned int resv33; + unsigned int uart3clkctrl; /* offset 0x590 */ + unsigned int resv34; + unsigned int uart4clkctrl; /* offset 0x598 */ + unsigned int resv35; + unsigned int uart5clkctrl; /* offset 0x5A0 */ + unsigned int resv36[5]; + unsigned int usbphyocp2scp0clkctrl; /* offset 0x5B8 */ + unsigned int resv361; + unsigned int usbphyocp2scp1clkctrl; /* offset 0x5C0 */ + unsigned int resv3611[79]; + + unsigned int emifclkstctrl; /* offset 0x700 */ + unsigned int resv362[7]; + unsigned int emifclkctrl; /* offset 0x720 */ + unsigned int resv37[3]; + unsigned int emiffwclkctrl; /* offset 0x730 */ + unsigned int resv371; + unsigned int otfaemifclkctrl; /* offset 0x738 */ + unsigned int resv38[57]; + unsigned int lcdclkctrl; /* offset 0x820 */ + unsigned int resv39[183]; + unsigned int cpswclkstctrl; /* offset 0xB00 */ + unsigned int resv40[7]; + unsigned int cpgmac0clkctrl; /* offset 0xB20 */ +}; + +struct cm_device_inst { + unsigned int cm_clkout1_ctrl; + unsigned int cm_dll_ctrl; +}; + +struct prm_device_inst { + unsigned int rstctrl; + unsigned int rstst; + unsigned int rsttime; + unsigned int sram_count; + unsigned int ldo_sram_core_set; /* offset 0x10 */ + unsigned int ldo_sram_core_ctr; + unsigned int ldo_sram_mpu_setu; + unsigned int ldo_sram_mpu_ctrl; + unsigned int io_count; /* offset 0x20 */ + unsigned int io_pmctrl; + unsigned int vc_val_bypass; + unsigned int resv1; + unsigned int emif_ctrl; /* offset 0x30 */ +}; + +struct cm_dpll { + unsigned int resv1; + unsigned int clktimer2clk; /* offset 0x04 */ + unsigned int resv2[11]; + unsigned int clkselmacclk; /* offset 0x34 */ +}; +#endif /* CONFIG_AM43XX */ + +/* Control Module RTC registers */ +struct cm_rtc { + unsigned int rtcclkctrl; /* offset 0x0 */ + unsigned int clkstctrl; /* offset 0x4 */ +}; + +/* Timer 32 bit registers */ +struct gptimer { + unsigned int tidr; /* offset 0x00 */ + unsigned char res1[12]; + unsigned int tiocp_cfg; /* offset 0x10 */ + unsigned char res2[12]; + unsigned int tier; /* offset 0x20 */ + unsigned int tistatr; /* offset 0x24 */ + unsigned int tistat; /* offset 0x28 */ + unsigned int tisr; /* offset 0x2c */ + unsigned int tcicr; /* offset 0x30 */ + unsigned int twer; /* offset 0x34 */ + unsigned int tclr; /* offset 0x38 */ + unsigned int tcrr; /* offset 0x3c */ + unsigned int tldr; /* offset 0x40 */ + unsigned int ttgr; /* offset 0x44 */ + unsigned int twpc; /* offset 0x48 */ + unsigned int tmar; /* offset 0x4c */ + unsigned int tcar1; /* offset 0x50 */ + unsigned int tscir; /* offset 0x54 */ + unsigned int tcar2; /* offset 0x58 */ +}; + +/* UART Registers */ +struct uart_sys { + unsigned int resv1[21]; + unsigned int uartsyscfg; /* offset 0x54 */ + unsigned int uartsyssts; /* offset 0x58 */ +}; + +/* VTP Registers */ +struct vtp_reg { + unsigned int vtp0ctrlreg; +}; + +/* Control Status Register */ +struct ctrl_stat { + unsigned int resv1[16]; + unsigned int statusreg; /* ofset 0x40 */ + unsigned int resv2[51]; + unsigned int secure_emif_sdram_config; /* offset 0x0110 */ + unsigned int resv3[319]; + unsigned int dev_attr; +}; + +/* AM33XX GPIO registers */ +#define OMAP_GPIO_REVISION 0x0000 +#define OMAP_GPIO_SYSCONFIG 0x0010 +#define OMAP_GPIO_SYSSTATUS 0x0114 +#define OMAP_GPIO_IRQSTATUS1 0x002c +#define OMAP_GPIO_IRQSTATUS2 0x0030 +#define OMAP_GPIO_IRQSTATUS_SET_0 0x0034 +#define OMAP_GPIO_IRQSTATUS_SET_1 0x0038 +#define OMAP_GPIO_CTRL 0x0130 +#define OMAP_GPIO_OE 0x0134 +#define OMAP_GPIO_DATAIN 0x0138 +#define OMAP_GPIO_DATAOUT 0x013c +#define OMAP_GPIO_LEVELDETECT0 0x0140 +#define OMAP_GPIO_LEVELDETECT1 0x0144 +#define OMAP_GPIO_RISINGDETECT 0x0148 +#define OMAP_GPIO_FALLINGDETECT 0x014c +#define OMAP_GPIO_DEBOUNCE_EN 0x0150 +#define OMAP_GPIO_DEBOUNCE_VAL 0x0154 +#define OMAP_GPIO_CLEARDATAOUT 0x0190 +#define OMAP_GPIO_SETDATAOUT 0x0194 + +/* Control Device Register */ + + /* Control Device Register */ +#define MREQPRIO_0_SAB_INIT1_MASK 0xFFFFFF8F +#define MREQPRIO_0_SAB_INIT0_MASK 0xFFFFFFF8 +#define MREQPRIO_1_DSS_MASK 0xFFFFFF8F + +struct ctrl_dev { + unsigned int deviceid; /* offset 0x00 */ + unsigned int resv1[7]; + unsigned int usb_ctrl0; /* offset 0x20 */ + unsigned int resv2; + unsigned int usb_ctrl1; /* offset 0x28 */ + unsigned int resv3; + unsigned int macid0l; /* offset 0x30 */ + unsigned int macid0h; /* offset 0x34 */ + unsigned int macid1l; /* offset 0x38 */ + unsigned int macid1h; /* offset 0x3c */ + unsigned int resv4[4]; + unsigned int miisel; /* offset 0x50 */ + unsigned int resv5[7]; + unsigned int mreqprio_0; /* offset 0x70 */ + unsigned int mreqprio_1; /* offset 0x74 */ + unsigned int resv6[97]; + unsigned int efuse_sma; /* offset 0x1FC */ +}; + +/* Bandwidth Limiter Portion of the L3Fast Configuration Register */ +#define BW_LIMITER_BW_FRAC_MASK 0xFFFFFFE0 +#define BW_LIMITER_BW_INT_MASK 0xFFFFFFF0 +#define BW_LIMITER_BW_WATERMARK_MASK 0xFFFFF800 + +struct l3f_cfg_bwlimiter { + u32 padding0[2]; + u32 modena_init0_bw_fractional; + u32 modena_init0_bw_integer; + u32 modena_init0_watermark_0; +}; + +/* gmii_sel register defines */ +#define GMII1_SEL_MII 0x0 +#define GMII1_SEL_RMII 0x1 +#define GMII1_SEL_RGMII 0x2 +#define GMII2_SEL_MII 0x0 +#define GMII2_SEL_RMII 0x4 +#define GMII2_SEL_RGMII 0x8 +#define RGMII1_IDMODE BIT(4) +#define RGMII2_IDMODE BIT(5) +#define RMII1_IO_CLK_EN BIT(6) +#define RMII2_IO_CLK_EN BIT(7) + +#define MII_MODE_ENABLE (GMII1_SEL_MII | GMII2_SEL_MII) +#define RMII_MODE_ENABLE (GMII1_SEL_RMII | GMII2_SEL_RMII) +#define RGMII_MODE_ENABLE (GMII1_SEL_RGMII | GMII2_SEL_RGMII) +#define RGMII_INT_DELAY (RGMII1_IDMODE | RGMII2_IDMODE) +#define RMII_CHIPCKL_ENABLE (RMII1_IO_CLK_EN | RMII2_IO_CLK_EN) + +/* PWMSS */ +struct pwmss_regs { + unsigned int idver; + unsigned int sysconfig; + unsigned int clkconfig; + unsigned int clkstatus; +}; +#define ECAP_CLK_EN BIT(0) +#define ECAP_CLK_STOP_REQ BIT(1) +#define EPWM_CLK_EN BIT(8) +#define EPWM_CLK_STOP_REQ BIT(9) + +struct pwmss_ecap_regs { + unsigned int tsctr; + unsigned int ctrphs; + unsigned int cap1; + unsigned int cap2; + unsigned int cap3; + unsigned int cap4; + unsigned int resv1[4]; + unsigned short ecctl1; + unsigned short ecctl2; +}; + +struct pwmss_epwm_regs { + unsigned short tbctl; + unsigned short tbsts; + unsigned short tbphshr; + unsigned short tbphs; + unsigned short tbcnt; + unsigned short tbprd; + unsigned short res1; + unsigned short cmpctl; + unsigned short cmpahr; + unsigned short cmpa; + unsigned short cmpb; + unsigned short aqctla; + unsigned short aqctlb; + unsigned short aqsfrc; + unsigned short aqcsfrc; + unsigned short dbctl; + unsigned short dbred; + unsigned short dbfed; + unsigned short tzsel; + unsigned short tzctl; + unsigned short tzflg; + unsigned short tzclr; + unsigned short tzfrc; + unsigned short etsel; + unsigned short etps; + unsigned short etflg; + unsigned short etclr; + unsigned short etfrc; + unsigned short pcctl; + unsigned int res2[66]; + unsigned short hrcnfg; +}; + +/* Capture Control register 2 */ +#define ECTRL2_SYNCOSEL_MASK (0x03 << 6) +#define ECTRL2_MDSL_ECAP BIT(9) +#define ECTRL2_CTRSTP_FREERUN BIT(4) +#define ECTRL2_PLSL_LOW BIT(10) +#define ECTRL2_SYNC_EN BIT(5) + +#endif /* __ASSEMBLY__ */ +#endif /* __KERNEL_STRICT_NAMES */ + +#endif /* _AM33XX_CPU_H */ diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h new file mode 100644 index 0000000..15a5b64 --- /dev/null +++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h @@ -0,0 +1,383 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * ddr_defs.h + * + * ddr specific header + * + * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ + */ + +#ifndef _DDR_DEFS_H +#define _DDR_DEFS_H + +#include <asm/arch/hardware.h> +#include <asm/emif.h> + +/* AM335X EMIF Register values */ +#define VTP_CTRL_READY (0x1 << 5) +#define VTP_CTRL_ENABLE (0x1 << 6) +#define VTP_CTRL_START_EN (0x1) +#ifdef CONFIG_AM43XX +#define DDR_CKE_CTRL_NORMAL 0x3 +#else +#define DDR_CKE_CTRL_NORMAL 0x1 +#endif +#define PHY_EN_DYN_PWRDN (0x1 << 20) + +/* Micron MT47H128M16RT-25E */ +#define MT47H128M16RT25E_EMIF_READ_LATENCY 0x100005 +#define MT47H128M16RT25E_EMIF_TIM1 0x0666B3C9 +#define MT47H128M16RT25E_EMIF_TIM2 0x243631CA +#define MT47H128M16RT25E_EMIF_TIM3 0x0000033F +#define MT47H128M16RT25E_EMIF_SDCFG 0x41805332 +#define MT47H128M16RT25E_EMIF_SDREF 0x0000081a +#define MT47H128M16RT25E_RATIO 0x80 +#define MT47H128M16RT25E_RD_DQS 0x12 +#define MT47H128M16RT25E_PHY_WR_DATA 0x40 +#define MT47H128M16RT25E_PHY_FIFO_WE 0x80 +#define MT47H128M16RT25E_IOCTRL_VALUE 0x18B + +/* Micron MT41J128M16JT-125 */ +#define MT41J128MJT125_EMIF_READ_LATENCY 0x100006 +#define MT41J128MJT125_EMIF_TIM1 0x0888A39B +#define MT41J128MJT125_EMIF_TIM2 0x26337FDA +#define MT41J128MJT125_EMIF_TIM3 0x501F830F +#define MT41J128MJT125_EMIF_SDCFG 0x61C04AB2 +#define MT41J128MJT125_EMIF_SDREF 0x0000093B +#define MT41J128MJT125_ZQ_CFG 0x50074BE4 +#define MT41J128MJT125_RATIO 0x40 +#define MT41J128MJT125_INVERT_CLKOUT 0x1 +#define MT41J128MJT125_RD_DQS 0x3B +#define MT41J128MJT125_WR_DQS 0x85 +#define MT41J128MJT125_PHY_WR_DATA 0xC1 +#define MT41J128MJT125_PHY_FIFO_WE 0x100 +#define MT41J128MJT125_IOCTRL_VALUE 0x18B + +/* Micron MT41J128M16JT-125 at 400MHz*/ +#define MT41J128MJT125_EMIF_READ_LATENCY_400MHz 0x100007 +#define MT41J128MJT125_EMIF_TIM1_400MHz 0x0AAAD4DB +#define MT41J128MJT125_EMIF_TIM2_400MHz 0x26437FDA +#define MT41J128MJT125_EMIF_TIM3_400MHz 0x501F83FF +#define MT41J128MJT125_EMIF_SDCFG_400MHz 0x61C052B2 +#define MT41J128MJT125_EMIF_SDREF_400MHz 0x00000C30 +#define MT41J128MJT125_ZQ_CFG_400MHz 0x50074BE4 +#define MT41J128MJT125_RATIO_400MHz 0x80 +#define MT41J128MJT125_INVERT_CLKOUT_400MHz 0x0 +#define MT41J128MJT125_RD_DQS_400MHz 0x3A +#define MT41J128MJT125_WR_DQS_400MHz 0x3B +#define MT41J128MJT125_PHY_WR_DATA_400MHz 0x76 +#define MT41J128MJT125_PHY_FIFO_WE_400MHz 0x96 + +/* Micron MT41K128M16JT-187E */ +#define MT41K128MJT187E_EMIF_READ_LATENCY 0x06 +#define MT41K128MJT187E_EMIF_TIM1 0x0888B3DB +#define MT41K128MJT187E_EMIF_TIM2 0x36337FDA +#define MT41K128MJT187E_EMIF_TIM3 0x501F830F +#define MT41K128MJT187E_EMIF_SDCFG 0x61C04AB2 +#define MT41K128MJT187E_EMIF_SDREF 0x0000093B +#define MT41K128MJT187E_ZQ_CFG 0x50074BE4 +#define MT41K128MJT187E_RATIO 0x40 +#define MT41K128MJT187E_INVERT_CLKOUT 0x1 +#define MT41K128MJT187E_RD_DQS 0x3B +#define MT41K128MJT187E_WR_DQS 0x85 +#define MT41K128MJT187E_PHY_WR_DATA 0xC1 +#define MT41K128MJT187E_PHY_FIFO_WE 0x100 +#define MT41K128MJT187E_IOCTRL_VALUE 0x18B + +/* Micron MT41K128M16JT-125 IT:K (256 MB) at 400MHz */ +#define MT41K128M16JT125K_EMIF_READ_LATENCY 0x07 +#define MT41K128M16JT125K_EMIF_TIM1 0x0AAAD4DB +#define MT41K128M16JT125K_EMIF_TIM2 0x2A437FDA +#define MT41K128M16JT125K_EMIF_TIM3 0x501F83FF +#define MT41K128M16JT125K_EMIF_SDCFG 0x61A052B2 +#define MT41K128M16JT125K_EMIF_SDREF 0x00000C30 +#define MT41K128M16JT125K_ZQ_CFG 0x50074BE4 +#define MT41K128M16JT125K_RATIO 0x80 +#define MT41K128M16JT125K_INVERT_CLKOUT 0x0 +#define MT41K128M16JT125K_RD_DQS 0x38 +#define MT41K128M16JT125K_WR_DQS 0x46 +#define MT41K128M16JT125K_PHY_WR_DATA 0x7D +#define MT41K128M16JT125K_PHY_FIFO_WE 0x9B +#define MT41K128M16JT125K_IOCTRL_VALUE 0x18B + +/* Micron MT41J64M16JT-125 */ +#define MT41J64MJT125_EMIF_SDCFG 0x61C04A32 + +/* Micron MT41J256M16JT-125 */ +#define MT41J256MJT125_EMIF_SDCFG 0x61C04B32 + +/* Micron MT41J256M8HX-15E */ +#define MT41J256M8HX15E_EMIF_READ_LATENCY 0x100006 +#define MT41J256M8HX15E_EMIF_TIM1 0x0888A39B +#define MT41J256M8HX15E_EMIF_TIM2 0x26337FDA +#define MT41J256M8HX15E_EMIF_TIM3 0x501F830F +#define MT41J256M8HX15E_EMIF_SDCFG 0x61C04B32 +#define MT41J256M8HX15E_EMIF_SDREF 0x0000093B +#define MT41J256M8HX15E_ZQ_CFG 0x50074BE4 +#define MT41J256M8HX15E_RATIO 0x40 +#define MT41J256M8HX15E_INVERT_CLKOUT 0x1 +#define MT41J256M8HX15E_RD_DQS 0x3B +#define MT41J256M8HX15E_WR_DQS 0x85 +#define MT41J256M8HX15E_PHY_WR_DATA 0xC1 +#define MT41J256M8HX15E_PHY_FIFO_WE 0x100 +#define MT41J256M8HX15E_IOCTRL_VALUE 0x18B + +/* Micron MT41K256M16HA-125E */ +#define MT41K256M16HA125E_EMIF_READ_LATENCY 0x100007 +#define MT41K256M16HA125E_EMIF_TIM1 0x0AAAD4DB +#define MT41K256M16HA125E_EMIF_TIM2 0x266B7FDA +#define MT41K256M16HA125E_EMIF_TIM3 0x501F867F +#define MT41K256M16HA125E_EMIF_SDCFG 0x61C05332 +#define MT41K256M16HA125E_EMIF_SDREF 0xC30 +#define MT41K256M16HA125E_ZQ_CFG 0x50074BE4 +#define MT41K256M16HA125E_RATIO 0x80 +#define MT41K256M16HA125E_INVERT_CLKOUT 0x0 +#define MT41K256M16HA125E_RD_DQS 0x38 +#define MT41K256M16HA125E_WR_DQS 0x44 +#define MT41K256M16HA125E_PHY_WR_DATA 0x7D +#define MT41K256M16HA125E_PHY_FIFO_WE 0x94 +#define MT41K256M16HA125E_IOCTRL_VALUE 0x18B + +/* Micron MT41J512M8RH-125 on EVM v1.5 */ +#define MT41J512M8RH125_EMIF_READ_LATENCY 0x100006 +#define MT41J512M8RH125_EMIF_TIM1 0x0888A39B +#define MT41J512M8RH125_EMIF_TIM2 0x26517FDA +#define MT41J512M8RH125_EMIF_TIM3 0x501F84EF +#define MT41J512M8RH125_EMIF_SDCFG 0x61C04BB2 +#define MT41J512M8RH125_EMIF_SDREF 0x0000093B +#define MT41J512M8RH125_ZQ_CFG 0x50074BE4 +#define MT41J512M8RH125_RATIO 0x80 +#define MT41J512M8RH125_INVERT_CLKOUT 0x0 +#define MT41J512M8RH125_RD_DQS 0x3B +#define MT41J512M8RH125_WR_DQS 0x3C +#define MT41J512M8RH125_PHY_FIFO_WE 0xA5 +#define MT41J512M8RH125_PHY_WR_DATA 0x74 +#define MT41J512M8RH125_IOCTRL_VALUE 0x18B + +/* Samsung K4B2G1646E-BIH9 */ +#define K4B2G1646EBIH9_EMIF_READ_LATENCY 0x100007 +#define K4B2G1646EBIH9_EMIF_TIM1 0x0AAAE51B +#define K4B2G1646EBIH9_EMIF_TIM2 0x2A1D7FDA +#define K4B2G1646EBIH9_EMIF_TIM3 0x501F83FF +#define K4B2G1646EBIH9_EMIF_SDCFG 0x61C052B2 +#define K4B2G1646EBIH9_EMIF_SDREF 0x00000C30 +#define K4B2G1646EBIH9_ZQ_CFG 0x50074BE4 +#define K4B2G1646EBIH9_RATIO 0x80 +#define K4B2G1646EBIH9_INVERT_CLKOUT 0x0 +#define K4B2G1646EBIH9_RD_DQS 0x35 +#define K4B2G1646EBIH9_WR_DQS 0x3A +#define K4B2G1646EBIH9_PHY_FIFO_WE 0x97 +#define K4B2G1646EBIH9_PHY_WR_DATA 0x76 +#define K4B2G1646EBIH9_IOCTRL_VALUE 0x18B + +#define LPDDR2_ADDRCTRL_IOCTRL_VALUE 0x294 +#define LPDDR2_ADDRCTRL_WD0_IOCTRL_VALUE 0x00000000 +#define LPDDR2_ADDRCTRL_WD1_IOCTRL_VALUE 0x00000000 +#define LPDDR2_DATA0_IOCTRL_VALUE 0x20000294 +#define LPDDR2_DATA1_IOCTRL_VALUE 0x20000294 +#define LPDDR2_DATA2_IOCTRL_VALUE 0x20000294 +#define LPDDR2_DATA3_IOCTRL_VALUE 0x20000294 + +#define DDR3_ADDRCTRL_WD0_IOCTRL_VALUE 0x00000000 +#define DDR3_ADDRCTRL_WD1_IOCTRL_VALUE 0x00000000 +#define DDR3_ADDRCTRL_IOCTRL_VALUE 0x84 +#define DDR3_DATA0_IOCTRL_VALUE 0x84 +#define DDR3_DATA1_IOCTRL_VALUE 0x84 +#define DDR3_DATA2_IOCTRL_VALUE 0x84 +#define DDR3_DATA3_IOCTRL_VALUE 0x84 + +/** + * Configure DMM + */ +void config_dmm(const struct dmm_lisa_map_regs *regs); + +/** + * Configure SDRAM + */ +void config_sdram(const struct emif_regs *regs, int nr); +void config_sdram_emif4d5(const struct emif_regs *regs, int nr); + +/** + * Set SDRAM timings + */ +void set_sdram_timings(const struct emif_regs *regs, int nr); + +/** + * Configure DDR PHY + */ +void config_ddr_phy(const struct emif_regs *regs, int nr); + +struct ddr_cmd_regs { + unsigned int resv0[7]; + unsigned int cm0csratio; /* offset 0x01C */ + unsigned int resv1[3]; + unsigned int cm0iclkout; /* offset 0x02C */ + unsigned int resv2[8]; + unsigned int cm1csratio; /* offset 0x050 */ + unsigned int resv3[3]; + unsigned int cm1iclkout; /* offset 0x060 */ + unsigned int resv4[8]; + unsigned int cm2csratio; /* offset 0x084 */ + unsigned int resv5[3]; + unsigned int cm2iclkout; /* offset 0x094 */ + unsigned int resv6[3]; +}; + +struct ddr_data_regs { + unsigned int dt0rdsratio0; /* offset 0x0C8 */ + unsigned int resv1[4]; + unsigned int dt0wdsratio0; /* offset 0x0DC */ + unsigned int resv2[4]; + unsigned int dt0wiratio0; /* offset 0x0F0 */ + unsigned int resv3; + unsigned int dt0wimode0; /* offset 0x0F8 */ + unsigned int dt0giratio0; /* offset 0x0FC */ + unsigned int resv4; + unsigned int dt0gimode0; /* offset 0x104 */ + unsigned int dt0fwsratio0; /* offset 0x108 */ + unsigned int resv5[4]; + unsigned int dt0dqoffset; /* offset 0x11C */ + unsigned int dt0wrsratio0; /* offset 0x120 */ + unsigned int resv6[4]; + unsigned int dt0rdelays0; /* offset 0x134 */ + unsigned int dt0dldiff0; /* offset 0x138 */ + unsigned int resv7[12]; +}; + +/** + * This structure represents the DDR registers on AM33XX devices. + * We make use of DDR_PHY_BASE_ADDR2 to address the DATA1 registers that + * correspond to DATA1 registers defined here. + */ +struct ddr_regs { + unsigned int resv0[3]; + unsigned int cm0config; /* offset 0x00C */ + unsigned int cm0configclk; /* offset 0x010 */ + unsigned int resv1[2]; + unsigned int cm0csratio; /* offset 0x01C */ + unsigned int resv2[3]; + unsigned int cm0iclkout; /* offset 0x02C */ + unsigned int resv3[4]; + unsigned int cm1config; /* offset 0x040 */ + unsigned int cm1configclk; /* offset 0x044 */ + unsigned int resv4[2]; + unsigned int cm1csratio; /* offset 0x050 */ + unsigned int resv5[3]; + unsigned int cm1iclkout; /* offset 0x060 */ + unsigned int resv6[4]; + unsigned int cm2config; /* offset 0x074 */ + unsigned int cm2configclk; /* offset 0x078 */ + unsigned int resv7[2]; + unsigned int cm2csratio; /* offset 0x084 */ + unsigned int resv8[3]; + unsigned int cm2iclkout; /* offset 0x094 */ + unsigned int resv9[12]; + unsigned int dt0rdsratio0; /* offset 0x0C8 */ + unsigned int resv10[4]; + unsigned int dt0wdsratio0; /* offset 0x0DC */ + unsigned int resv11[4]; + unsigned int dt0wiratio0; /* offset 0x0F0 */ + unsigned int resv12; + unsigned int dt0wimode0; /* offset 0x0F8 */ + unsigned int dt0giratio0; /* offset 0x0FC */ + unsigned int resv13; + unsigned int dt0gimode0; /* offset 0x104 */ + unsigned int dt0fwsratio0; /* offset 0x108 */ + unsigned int resv14[4]; + unsigned int dt0dqoffset; /* offset 0x11C */ + unsigned int dt0wrsratio0; /* offset 0x120 */ + unsigned int resv15[4]; + unsigned int dt0rdelays0; /* offset 0x134 */ + unsigned int dt0dldiff0; /* offset 0x138 */ +}; + +/** + * Encapsulates DDR CMD control registers. + */ +struct cmd_control { + unsigned long cmd0csratio; + unsigned long cmd0csforce; + unsigned long cmd0csdelay; + unsigned long cmd0iclkout; + unsigned long cmd1csratio; + unsigned long cmd1csforce; + unsigned long cmd1csdelay; + unsigned long cmd1iclkout; + unsigned long cmd2csratio; + unsigned long cmd2csforce; + unsigned long cmd2csdelay; + unsigned long cmd2iclkout; +}; + +/** + * Encapsulates DDR DATA registers. + */ +struct ddr_data { + unsigned long datardsratio0; + unsigned long datawdsratio0; + unsigned long datawiratio0; + unsigned long datagiratio0; + unsigned long datafwsratio0; + unsigned long datawrsratio0; +}; + +/** + * Configure DDR CMD control registers + */ +void config_cmd_ctrl(const struct cmd_control *cmd, int nr); + +/** + * Configure DDR DATA registers + */ +void config_ddr_data(const struct ddr_data *data, int nr); + +/** + * This structure represents the DDR io control on AM33XX devices. + */ +struct ddr_cmdtctrl { + unsigned int cm0ioctl; + unsigned int cm1ioctl; + unsigned int cm2ioctl; + unsigned int resv2[12]; + unsigned int dt0ioctl; + unsigned int dt1ioctl; + unsigned int dt2ioctrl; + unsigned int dt3ioctrl; + unsigned int resv3[4]; + unsigned int emif_sdram_config_ext; +}; + +struct ctrl_ioregs { + unsigned int cm0ioctl; + unsigned int cm1ioctl; + unsigned int cm2ioctl; + unsigned int dt0ioctl; + unsigned int dt1ioctl; + unsigned int dt2ioctrl; + unsigned int dt3ioctrl; + unsigned int emif_sdram_config_ext; +}; + +/** + * Configure DDR io control registers + */ +void config_io_ctrl(const struct ctrl_ioregs *ioregs); + +struct ddr_ctrl { + unsigned int ddrioctrl; + unsigned int resv1[325]; + unsigned int ddrckectrl; +}; + +#ifdef CONFIG_TI816X +void config_ddr(const struct ddr_data *data, const struct cmd_control *ctrl, + const struct emif_regs *regs, + const struct dmm_lisa_map_regs *lisa_regs, int nrs); +#else +void config_ddr(unsigned int pll, const struct ctrl_ioregs *ioregs, + const struct ddr_data *data, const struct cmd_control *ctrl, + const struct emif_regs *regs, int nr); +#endif +void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size); + +#endif /* _DDR_DEFS_H */ diff --git a/arch/arm/include/asm/arch-am33xx/emac_defs.h b/arch/arm/include/asm/arch-am33xx/emac_defs.h new file mode 100644 index 0000000..eb6516d --- /dev/null +++ b/arch/arm/include/asm/arch-am33xx/emac_defs.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2010 Texas Instruments + * + * Based on: + * + * ---------------------------------------------------------------------------- + * + * dm644x_emac.h + * + * TI DaVinci (DM644X) EMAC peripheral driver header for DV-EVM + * + * Copyright (C) 2005 Texas Instruments. + * + * ---------------------------------------------------------------------------- + * + */ + +#ifndef _EMAC_DEFS_H_ +#define _EMAC_DEFS_H_ + +#ifdef CONFIG_TI816X +#define EMAC_BASE_ADDR (0x4A100000) +#define EMAC_WRAPPER_BASE_ADDR (0x4A100900) +#define EMAC_WRAPPER_RAM_ADDR (0x4A102000) +#define EMAC_MDIO_BASE_ADDR (0x4A100800) +#define EMAC_MDIO_BUS_FREQ (250000000UL) +#define EMAC_MDIO_CLOCK_FREQ (2000000UL) + +typedef volatile unsigned int dv_reg; +typedef volatile unsigned int *dv_reg_p; + +#define DAVINCI_EMAC_VERSION2 +#define DAVINCI_EMAC_GIG_ENABLE +#endif + +#endif /* _EMAC_DEFS_H_ */ diff --git a/arch/arm/include/asm/arch-am33xx/gpio.h b/arch/arm/include/asm/arch-am33xx/gpio.h new file mode 100644 index 0000000..24dc4bb --- /dev/null +++ b/arch/arm/include/asm/arch-am33xx/gpio.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +#ifndef _GPIO_AM33xx_H +#define _GPIO_AM33xx_H + +#include <asm/omap_gpio.h> + +#ifdef CONFIG_AM43XX +#define OMAP_MAX_GPIO 192 +#else +#define OMAP_MAX_GPIO 128 +#endif + +#define AM33XX_GPIO0_BASE 0x44E07000 +#define AM33XX_GPIO1_BASE 0x4804C000 +#define AM33XX_GPIO2_BASE 0x481AC000 +#define AM33XX_GPIO3_BASE 0x481AE000 +#define AM33XX_GPIO4_BASE 0x48320000 +#define AM33XX_GPIO5_BASE 0x48322000 + +/* GPIO CTRL register */ +#define GPIO_CTRL_DISABLEMODULE_SHIFT 0 +#define GPIO_CTRL_DISABLEMODULE_MASK (1 << 0) +#define GPIO_CTRL_ENABLEMODULE GPIO_CTRL_DISABLEMODULE_MASK + +/* GPIO OUTPUT ENABLE register */ +#define GPIO_OE_ENABLE(x) (1 << x) + +/* GPIO SETDATAOUT register */ +#define GPIO_SETDATAOUT(x) (1 << x) +#endif /* _GPIO_AM33xx_H */ diff --git a/arch/arm/include/asm/arch-am33xx/hardware.h b/arch/arm/include/asm/arch-am33xx/hardware.h new file mode 100644 index 0000000..0508b8c --- /dev/null +++ b/arch/arm/include/asm/arch-am33xx/hardware.h @@ -0,0 +1,89 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * hardware.h + * + * hardware specific header + * + * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/ + */ + +#ifndef __AM33XX_HARDWARE_H +#define __AM33XX_HARDWARE_H + +#include <config.h> +#include <asm/arch/omap.h> +#ifdef CONFIG_AM33XX +#include <asm/arch/hardware_am33xx.h> +#elif defined(CONFIG_TI816X) +#include <asm/arch/hardware_ti816x.h> +#elif defined(CONFIG_TI814X) +#include <asm/arch/hardware_ti814x.h> +#elif defined(CONFIG_AM43XX) +#include <asm/arch/hardware_am43xx.h> +#endif + +/* + * Common hardware definitions + */ + +/* DM Timer base addresses */ +#define DM_TIMER0_BASE 0x4802C000 +#define DM_TIMER1_BASE 0x4802E000 +#define DM_TIMER2_BASE 0x48040000 +#define DM_TIMER3_BASE 0x48042000 +#define DM_TIMER4_BASE 0x48044000 +#define DM_TIMER5_BASE 0x48046000 +#define DM_TIMER6_BASE 0x48048000 +#define DM_TIMER7_BASE 0x4804A000 + +/* GPIO Base address */ +#define GPIO0_BASE 0x48032000 +#define GPIO1_BASE 0x4804C000 + +/* BCH Error Location Module */ +#define ELM_BASE 0x48080000 + +/* EMIF Base address */ +#define EMIF4_0_CFG_BASE 0x4C000000 +#define EMIF4_1_CFG_BASE 0x4D000000 + +/* DDR Base address */ +#define DDR_CTRL_ADDR 0x44E10E04 +#define DDR_CONTROL_BASE_ADDR 0x44E11404 + +/* UART */ +#if CONFIG_CONS_INDEX == 1 +# define DEFAULT_UART_BASE UART0_BASE +#elif CONFIG_CONS_INDEX == 2 +# define DEFAULT_UART_BASE UART1_BASE +#elif CONFIG_CONS_INDEX == 3 +# define DEFAULT_UART_BASE UART2_BASE +#elif CONFIG_CONS_INDEX == 4 +# define DEFAULT_UART_BASE UART3_BASE +#elif CONFIG_CONS_INDEX == 5 +# define DEFAULT_UART_BASE UART4_BASE +#elif CONFIG_CONS_INDEX == 6 +# define DEFAULT_UART_BASE UART5_BASE +#endif + +/* GPMC Base address */ +#define GPMC_BASE 0x50000000 + +/* CPSW Config space */ +#define CPSW_BASE 0x4A100000 + +/* Control status register */ +#define CTRL_CRYSTAL_FREQ_SRC_MASK (1 << 31) +#define CTRL_CRYSTAL_FREQ_SRC_SHIFT 31 +#define CTRL_CRYSTAL_FREQ_SELECTION_MASK (0x3 << 29) +#define CTRL_CRYSTAL_FREQ_SELECTION_SHIFT 29 +#define CTRL_SYSBOOT_15_14_MASK (0x3 << 22) +#define CTRL_SYSBOOT_15_14_SHIFT 22 + +#define CTRL_CRYSTAL_FREQ_SRC_SYSBOOT 0x0 +#define CTRL_CRYSTAL_FREQ_SRC_EFUSE 0x1 + +#define NUM_CRYSTAL_FREQ 0x4 + +int clk_get(int clk); +#endif /* __AM33XX_HARDWARE_H */ diff --git a/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h b/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h new file mode 100644 index 0000000..878ef3e --- /dev/null +++ b/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h @@ -0,0 +1,76 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * hardware_am33xx.h + * + * AM33xx hardware specific header + * + * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/ + */ + +#ifndef __AM33XX_HARDWARE_AM33XX_H +#define __AM33XX_HARDWARE_AM33XX_H + +/* Module base addresses */ + +/* UART Base Address */ +#define UART0_BASE 0x44E09000 +#define UART1_BASE 0x48022000 +#define UART2_BASE 0x48024000 +#define UART3_BASE 0x481A6000 +#define UART4_BASE 0x481A8000 +#define UART5_BASE 0x481AA000 + +/* GPIO Base address */ +#define GPIO2_BASE 0x481AC000 + +/* Watchdog Timer */ +#define WDT_BASE 0x44E35000 + +/* Control Module Base Address */ +#define CTRL_BASE 0x44E10000 +#define CTRL_DEVICE_BASE 0x44E10600 + +/* PRCM Base Address */ +#define PRCM_BASE 0x44E00000 +#define CM_PER 0x44E00000 +#define CM_WKUP 0x44E00400 +#define CM_DPLL 0x44E00500 +#define CM_RTC 0x44E00800 + +#define PRM_RSTCTRL (PRCM_BASE + 0x0F00) +#define PRM_RSTST (PRM_RSTCTRL + 8) + +/* VTP Base address */ +#define VTP0_CTRL_ADDR 0x44E10E0C +#define VTP1_CTRL_ADDR 0x48140E10 +#define PRM_DEVICE_INST 0x44E00F00 + +/* DDR Base address */ +#define DDR_PHY_CMD_ADDR 0x44E12000 +#define DDR_PHY_DATA_ADDR 0x44E120C8 +#define DDR_PHY_CMD_ADDR2 0x47C0C800 +#define DDR_PHY_DATA_ADDR2 0x47C0C8C8 +#define DDR_DATA_REGS_NR 2 + +#define DDRPHY_0_CONFIG_BASE (CTRL_BASE + 0x1400) +#define DDRPHY_CONFIG_BASE DDRPHY_0_CONFIG_BASE + +/* CPSW Config space */ +#define CPSW_MDIO_BASE 0x4A101000 + +/* RTC base address */ +#define RTC_BASE 0x44E3E000 + +/* OTG */ +#define USB0_OTG_BASE 0x47401000 +#define USB1_OTG_BASE 0x47401800 + +/* LCD Controller */ +#define LCD_CNTL_BASE 0x4830E000 + +/* PWMSS */ +#define PWMSS0_BASE 0x48300000 +#define AM33XX_ECAP0_BASE 0x48300100 +#define AM33XX_EPWM_BASE 0x48300200 + +#endif /* __AM33XX_HARDWARE_AM33XX_H */ diff --git a/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h b/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h new file mode 100644 index 0000000..64809d5 --- /dev/null +++ b/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h @@ -0,0 +1,90 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * hardware_am43xx.h + * + * AM43xx hardware specific header + * + * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/ + */ + +#ifndef __AM43XX_HARDWARE_AM43XX_H +#define __AM43XX_HARDWARE_AM43XX_H + +/* Module base addresses */ + +/* L3 Fast Configuration Bandwidth Limiter Base Address */ +#define L3F_CFG_BWLIMITER 0x44005200 + +/* UART Base Address */ +#define UART0_BASE 0x44E09000 + +/* GPIO Base address */ +#define GPIO2_BASE 0x481AC000 + +/* Watchdog Timer */ +#define WDT_BASE 0x44E35000 + +/* Control Module Base Address */ +#define CTRL_BASE 0x44E10000 +#define CTRL_DEVICE_BASE 0x44E10600 + +/* PRCM Base Address */ +#define PRCM_BASE 0x44DF0000 +#define CM_WKUP 0x44DF2800 +#define CM_PER 0x44DF8800 +#define CM_DPLL 0x44DF4200 +#define CM_RTC 0x44DF8500 + +#define PRM_RSTCTRL (PRCM_BASE + 0x4000) +#define PRM_RSTST (PRM_RSTCTRL + 4) + +/* VTP Base address */ +#define VTP0_CTRL_ADDR 0x44E10E0C +#define VTP1_CTRL_ADDR 0x48140E10 + +/* USB CTRL Base Address */ +#define USB1_CTRL 0x44e10628 +#define USB1_CTRL_CM_PWRDN BIT(0) +#define USB1_CTRL_OTG_PWRDN BIT(1) + +/* DDR Base address */ +#define DDR_PHY_CMD_ADDR 0x44E12000 +#define DDR_PHY_DATA_ADDR 0x44E120C8 +#define DDR_PHY_CMD_ADDR2 0x47C0C800 +#define DDR_PHY_DATA_ADDR2 0x47C0C8C8 +#define DDR_DATA_REGS_NR 2 + +/* CPSW Config space */ +#define CPSW_MDIO_BASE 0x4A101000 + +/* RTC base address */ +#define RTC_BASE 0x44E3E000 + +/* USB OTG */ +#define USB_OTG_SS1_BASE 0x48390000 +#define USB_OTG_SS1_GLUE_BASE 0x48380000 +#define USB2_PHY1_POWER 0x44E10620 + +#define USB_OTG_SS2_BASE 0x483D0000 +#define USB_OTG_SS2_GLUE_BASE 0x483C0000 +#define USB2_PHY2_POWER 0x44E10628 + +/* USB Clock Control */ +#define PRM_PER_USB_OTG_SS0_CLKCTRL (CM_PER + 0x260) +#define PRM_PER_USB_OTG_SS1_CLKCTRL (CM_PER + 0x268) +#define USBOTGSSX_CLKCTRL_MODULE_EN (1 << 1) +#define USBOTGSSX_CLKCTRL_OPTFCLKEN_REFCLK960 (1 << 8) + +#define PRM_PER_USBPHYOCP2SCP0_CLKCTRL (CM_PER + 0x5b8) +#define PRM_PER_USBPHYOCP2SCP1_CLKCTRL (CM_PER + 0x5c0) +#define USBPHYOCPSCP_MODULE_EN (1 << 1) +#define CM_DEVICE_INST 0x44df4100 +#define PRM_DEVICE_INST 0x44df4000 + +#define USBOTGSSX_CLKCTRL_OPTFCLKEN_REFCLK960 (1 << 8) +#define USBPHY0_CLKCTRL_OPTFCLKEN_CLK32K (1 << 8) + +/* EDMA3 Base Address */ +#define EDMA3_BASE 0x49000000 + +#endif /* __AM43XX_HARDWARE_AM43XX_H */ diff --git a/arch/arm/include/asm/arch-am33xx/hardware_ti814x.h b/arch/arm/include/asm/arch-am33xx/hardware_ti814x.h new file mode 100644 index 0000000..b00d592 --- /dev/null +++ b/arch/arm/include/asm/arch-am33xx/hardware_ti814x.h @@ -0,0 +1,60 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * hardware_ti814x.h + * + * TI814x hardware specific header + * + * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/ + */ + +#ifndef __AM33XX_HARDWARE_TI814X_H +#define __AM33XX_HARDWARE_TI814X_H + +/* Module base addresses */ + +/* UART Base Address */ +#define UART0_BASE 0x48020000 + +/* Watchdog Timer */ +#define WDT_BASE 0x481C7000 + +/* Control Module Base Address */ +#define CTRL_BASE 0x48140000 +#define CTRL_DEVICE_BASE 0x48140600 + +/* PRCM Base Address */ +#define PRCM_BASE 0x48180000 +#define CM_PER 0x44E00000 +#define CM_WKUP 0x44E00400 + +#define PRM_RSTCTRL (PRCM_BASE + 0x00A0) +#define PRM_RSTST (PRM_RSTCTRL + 8) + +/* PLL Subsystem Base Address */ +#define PLL_SUBSYS_BASE 0x481C5000 + +/* VTP Base address */ +#define VTP0_CTRL_ADDR 0x48140E0C +#define VTP1_CTRL_ADDR 0x48140E10 + +/* DDR Base address */ +#define DDR_PHY_CMD_ADDR 0x47C0C400 +#define DDR_PHY_DATA_ADDR 0x47C0C4C8 +#define DDR_PHY_CMD_ADDR2 0x47C0C800 +#define DDR_PHY_DATA_ADDR2 0x47C0C8C8 +#define DDR_DATA_REGS_NR 4 + +#define DDRPHY_0_CONFIG_BASE (CTRL_BASE + 0x1400) +#define DDRPHY_CONFIG_BASE DDRPHY_0_CONFIG_BASE + +/* CPSW Config space */ +#define CPSW_MDIO_BASE 0x4A100800 + +/* RTC base address */ +#define RTC_BASE 0x480C0000 + +/* OTG */ +#define USB0_OTG_BASE 0x47401000 +#define USB1_OTG_BASE 0x47401800 + +#endif /* __AM33XX_HARDWARE_TI814X_H */ diff --git a/arch/arm/include/asm/arch-am33xx/hardware_ti816x.h b/arch/arm/include/asm/arch-am33xx/hardware_ti816x.h new file mode 100644 index 0000000..78b7948 --- /dev/null +++ b/arch/arm/include/asm/arch-am33xx/hardware_ti816x.h @@ -0,0 +1,62 @@ +/* + * hardware_ti816x.h + * + * TI816x hardware specific header + * + * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com> + * Antoine Tenart, <atenart@adeneo-embedded.com> + * Based on TI-PSP-04.00.02.14 + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __AM33XX_HARDWARE_TI816X_H +#define __AM33XX_HARDWARE_TI816X_H + +/* UART */ +#define UART0_BASE 0x48020000 +#define UART1_BASE 0x48022000 +#define UART2_BASE 0x48024000 + +/* Watchdog Timer */ +#define WDT_BASE 0x480C2000 + +/* Control Module Base Address */ +#define CTRL_BASE 0x48140000 +#define CTRL_DEVICE_BASE 0x48140600 + +/* PRCM Base Address */ +#define PRCM_BASE 0x48180000 + +#define PRM_RSTCTRL (PRCM_BASE + 0x00A0) +#define PRM_RSTST (PRM_RSTCTRL + 8) + +/* VTP Base address */ +#define VTP0_CTRL_ADDR 0x48198358 +#define VTP1_CTRL_ADDR 0x4819A358 + +/* DDR Base address */ +#define DDR_PHY_CMD_ADDR 0x48198000 +#define DDR_PHY_DATA_ADDR 0x481980C8 +#define DDR_PHY_CMD_ADDR2 0x4819A000 +#define DDR_PHY_DATA_ADDR2 0x4819A0C8 +#define DDR_DATA_REGS_NR 4 + + +#define DDRPHY_0_CONFIG_BASE 0x48198000 +#define DDRPHY_1_CONFIG_BASE 0x4819A000 +#define DDRPHY_CONFIG_BASE ((emif == 0) ? \ + DDRPHY_0_CONFIG_BASE : DDRPHY_1_CONFIG_BASE) + +/* RTC base address */ +#define RTC_BASE 0x480C0000 + +#endif /* __AM33XX_HARDWARE_TI816X_H */ diff --git a/arch/arm/include/asm/arch-am33xx/i2c.h b/arch/arm/include/asm/arch-am33xx/i2c.h new file mode 100644 index 0000000..c2a9850 --- /dev/null +++ b/arch/arm/include/asm/arch-am33xx/i2c.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2012 + * Texas Instruments, <www.ti.com> + */ +#ifndef _I2C_AM33XX_H_ +#define _I2C_AM33XX_H_ + +#include <asm/omap_i2c.h> + +#define I2C_BASE1 0x44E0B000 +#define I2C_BASE2 0x4802A000 +#define I2C_BASE3 0x4819C000 + +#define I2C_DEFAULT_BASE I2C_BASE1 + +#define I2C_IP_CLK 48000000 +#define I2C_INTERNAL_SAMPLING_CLK 12000000 + +#endif /* _I2C_AM33XX_H_ */ diff --git a/arch/arm/include/asm/arch-am33xx/mem.h b/arch/arm/include/asm/arch-am33xx/mem.h new file mode 100644 index 0000000..0fd52f8 --- /dev/null +++ b/arch/arm/include/asm/arch-am33xx/mem.h @@ -0,0 +1,63 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2006-2008 + * Texas Instruments, <www.ti.com> + * + * Author + * Mansoor Ahamed <mansoor.ahamed@ti.com> + * + * Initial Code from: + * Richard Woodruff <r-woodruff2@ti.com> + */ + +#ifndef _MEM_H_ +#define _MEM_H_ + +/* + * GPMC settings - + * Definitions is as per the following format + * #define <PART>_GPMC_CONFIG<x> <value> + * Where: + * PART is the part name e.g. STNOR - Intel Strata Flash + * x is GPMC config registers from 1 to 6 (there will be 6 macros) + * Value is corresponding value + * + * For every valid PRCM configuration there should be only one definition of + * the same. if values are independent of the board, this definition will be + * present in this file if values are dependent on the board, then this should + * go into corresponding mem-boardName.h file + * + * Currently valid part Names are (PART): + * M_NAND - Micron NAND + * STNOR - STMicrolelctronics M29W128GL + */ +#define GPMC_SIZE_256M 0x0 +#define GPMC_SIZE_128M 0x8 +#define GPMC_SIZE_64M 0xC +#define GPMC_SIZE_32M 0xE +#define GPMC_SIZE_16M 0xF + +#define M_NAND_GPMC_CONFIG1 0x00000800 +#define M_NAND_GPMC_CONFIG2 0x001e1e00 +#define M_NAND_GPMC_CONFIG3 0x001e1e00 +#define M_NAND_GPMC_CONFIG4 0x16051807 +#define M_NAND_GPMC_CONFIG5 0x00151e1e +#define M_NAND_GPMC_CONFIG6 0x16000f80 +#define M_NAND_GPMC_CONFIG7 0x00000008 + +#define STNOR_GPMC_CONFIG1 0x00001200 +#define STNOR_GPMC_CONFIG2 0x00101000 +#define STNOR_GPMC_CONFIG3 0x00030301 +#define STNOR_GPMC_CONFIG4 0x10041004 +#define STNOR_GPMC_CONFIG5 0x000C1010 +#define STNOR_GPMC_CONFIG6 0x08070280 +#define STNOR_GPMC_CONFIG7 0x00000F48 + +/* max number of GPMC Chip Selects */ +#define GPMC_MAX_CS 8 +/* max number of GPMC regs */ +#define GPMC_MAX_REG 7 + +#define DBG_MPDB 6 + +#endif /* endif _MEM_H_ */ diff --git a/arch/arm/include/asm/arch-am33xx/mmc_host_def.h b/arch/arm/include/asm/arch-am33xx/mmc_host_def.h new file mode 100644 index 0000000..5a2ea8f --- /dev/null +++ b/arch/arm/include/asm/arch-am33xx/mmc_host_def.h @@ -0,0 +1,35 @@ +/* + * mmc_host_def.h + * + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef MMC_HOST_DEF_H +#define MMC_HOST_DEF_H + +#include <asm/omap_mmc.h> + +/* + * OMAP HSMMC register definitions + */ +#define OMAP_HSMMC1_BASE 0x48060000 +#define OMAP_HSMMC2_BASE 0x481D8000 + +#if defined(CONFIG_TI814X) +#undef MMC_CLOCK_REFERENCE +#define MMC_CLOCK_REFERENCE 192 /* MHz */ +#elif defined(CONFIG_TI816X) +#undef MMC_CLOCK_REFERENCE +#define MMC_CLOCK_REFERENCE 48 /* MHz */ +#endif + +#endif /* MMC_HOST_DEF_H */ diff --git a/arch/arm/include/asm/arch-am33xx/mux.h b/arch/arm/include/asm/arch-am33xx/mux.h new file mode 100644 index 0000000..d8bf872 --- /dev/null +++ b/arch/arm/include/asm/arch-am33xx/mux.h @@ -0,0 +1,47 @@ +/* + * mux.h + * + * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _MUX_H_ +#define _MUX_H_ + +#include <common.h> +#include <asm/io.h> + +#ifdef CONFIG_AM33XX +#include <asm/arch/mux_am33xx.h> +#elif defined(CONFIG_TI814X) +#include <asm/arch/mux_ti814x.h> +#elif defined(CONFIG_TI816X) +#include <asm/arch/mux_ti816x.h> +#elif defined(CONFIG_AM43XX) +#include <asm/arch/mux_am43xx.h> +#endif + +struct module_pin_mux { + short reg_offset; + unsigned int val; +}; + +/* Pad control register offset */ +#define PAD_CTRL_BASE 0x800 +#define OFFSET(x) (unsigned int) (&((struct pad_signals *)\ + (PAD_CTRL_BASE))->x) + +/* + * Configure the pin mux for the module + */ +void configure_module_pin_mux(struct module_pin_mux *mod_pin_mux); + +#endif /* endif _MUX_H */ diff --git a/arch/arm/include/asm/arch-am33xx/mux_am33xx.h b/arch/arm/include/asm/arch-am33xx/mux_am33xx.h new file mode 100644 index 0000000..d5cab3e --- /dev/null +++ b/arch/arm/include/asm/arch-am33xx/mux_am33xx.h @@ -0,0 +1,247 @@ +/* + * mux_am33xx.h + * + * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _MUX_AM33XX_H_ +#define _MUX_AM33XX_H_ + +#include <common.h> +#include <asm/io.h> + +#define MUX_CFG(value, offset) \ + __raw_writel(value, (CTRL_BASE + offset)); + +/* PAD Control Fields */ +#define SLEWCTRL (0x1 << 6) +#define RXACTIVE (0x1 << 5) +#define PULLDOWN_EN (0x0 << 4) /* Pull Down Selection */ +#define PULLUP_EN (0x1 << 4) /* Pull Up Selection */ +#define PULLUDEN (0x0 << 3) /* Pull up enabled */ +#define PULLUDDIS (0x1 << 3) /* Pull up disabled */ +#define MODE(val) val /* used for Readability */ + +/* + * PAD CONTROL OFFSETS + * Field names corresponds to the pad signal name + */ +struct pad_signals { + int gpmc_ad0; + int gpmc_ad1; + int gpmc_ad2; + int gpmc_ad3; + int gpmc_ad4; + int gpmc_ad5; + int gpmc_ad6; + int gpmc_ad7; + int gpmc_ad8; + int gpmc_ad9; + int gpmc_ad10; + int gpmc_ad11; + int gpmc_ad12; + int gpmc_ad13; + int gpmc_ad14; + int gpmc_ad15; + int gpmc_a0; + int gpmc_a1; + int gpmc_a2; + int gpmc_a3; + int gpmc_a4; + int gpmc_a5; + int gpmc_a6; + int gpmc_a7; + int gpmc_a8; + int gpmc_a9; + int gpmc_a10; + int gpmc_a11; + int gpmc_wait0; + int gpmc_wpn; + int gpmc_be1n; + int gpmc_csn0; + int gpmc_csn1; + int gpmc_csn2; + int gpmc_csn3; + int gpmc_clk; + int gpmc_advn_ale; + int gpmc_oen_ren; + int gpmc_wen; + int gpmc_be0n_cle; + int lcd_data0; + int lcd_data1; + int lcd_data2; + int lcd_data3; + int lcd_data4; + int lcd_data5; + int lcd_data6; + int lcd_data7; + int lcd_data8; + int lcd_data9; + int lcd_data10; + int lcd_data11; + int lcd_data12; + int lcd_data13; + int lcd_data14; + int lcd_data15; + int lcd_vsync; + int lcd_hsync; + int lcd_pclk; + int lcd_ac_bias_en; + int mmc0_dat3; + int mmc0_dat2; + int mmc0_dat1; + int mmc0_dat0; + int mmc0_clk; + int mmc0_cmd; + int mii1_col; + int mii1_crs; + int mii1_rxerr; + int mii1_txen; + int mii1_rxdv; + int mii1_txd3; + int mii1_txd2; + int mii1_txd1; + int mii1_txd0; + int mii1_txclk; + int mii1_rxclk; + int mii1_rxd3; + int mii1_rxd2; + int mii1_rxd1; + int mii1_rxd0; + int rmii1_refclk; + int mdio_data; + int mdio_clk; + int spi0_sclk; + int spi0_d0; + int spi0_d1; + int spi0_cs0; + int spi0_cs1; + int ecap0_in_pwm0_out; + int uart0_ctsn; + int uart0_rtsn; + int uart0_rxd; + int uart0_txd; + int uart1_ctsn; + int uart1_rtsn; + int uart1_rxd; + int uart1_txd; + int i2c0_sda; + int i2c0_scl; + int mcasp0_aclkx; + int mcasp0_fsx; + int mcasp0_axr0; + int mcasp0_ahclkr; + int mcasp0_aclkr; + int mcasp0_fsr; + int mcasp0_axr1; + int mcasp0_ahclkx; + int xdma_event_intr0; + int xdma_event_intr1; + int nresetin_out; + int porz; + int nnmi; + int osc0_in; + int osc0_out; + int rsvd1; + int tms; + int tdi; + int tdo; + int tck; + int ntrst; + int emu0; + int emu1; + int osc1_in; + int osc1_out; + int pmic_power_en; + int rtc_porz; + int rsvd2; + int ext_wakeup; + int enz_kaldo_1p8v; + int usb0_dm; + int usb0_dp; + int usb0_ce; + int usb0_id; + int usb0_vbus; + int usb0_drvvbus; + int usb1_dm; + int usb1_dp; + int usb1_ce; + int usb1_id; + int usb1_vbus; + int usb1_drvvbus; + int ddr_resetn; + int ddr_csn0; + int ddr_cke; + int ddr_ck; + int ddr_nck; + int ddr_casn; + int ddr_rasn; + int ddr_wen; + int ddr_ba0; + int ddr_ba1; + int ddr_ba2; + int ddr_a0; + int ddr_a1; + int ddr_a2; + int ddr_a3; + int ddr_a4; + int ddr_a5; + int ddr_a6; + int ddr_a7; + int ddr_a8; + int ddr_a9; + int ddr_a10; + int ddr_a11; + int ddr_a12; + int ddr_a13; + int ddr_a14; + int ddr_a15; + int ddr_odt; + int ddr_d0; + int ddr_d1; + int ddr_d2; + int ddr_d3; + int ddr_d4; + int ddr_d5; + int ddr_d6; + int ddr_d7; + int ddr_d8; + int ddr_d9; + int ddr_d10; + int ddr_d11; + int ddr_d12; + int ddr_d13; + int ddr_d14; + int ddr_d15; + int ddr_dqm0; + int ddr_dqm1; + int ddr_dqs0; + int ddr_dqsn0; + int ddr_dqs1; + int ddr_dqsn1; + int ddr_vref; + int ddr_vtp; + int ddr_strben0; + int ddr_strben1; + int ain7; + int ain6; + int ain5; + int ain4; + int ain3; + int ain2; + int ain1; + int ain0; + int vrefp; + int vrefn; +}; + +#endif /* endif _MUX_AM33XX_H_ */ diff --git a/arch/arm/include/asm/arch-am33xx/mux_am43xx.h b/arch/arm/include/asm/arch-am33xx/mux_am43xx.h new file mode 100644 index 0000000..256c5e2 --- /dev/null +++ b/arch/arm/include/asm/arch-am33xx/mux_am43xx.h @@ -0,0 +1,211 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * mux_am43xx.h + * + * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ + */ + +#ifndef _MUX_AM43XX_H_ +#define _MUX_AM43XX_H_ + +#include <common.h> +#include <asm/io.h> + +#define MUX_CFG(value, offset) \ + __raw_writel(value, (CTRL_BASE + offset)); + +/* PAD Control Fields */ +#define SLEWCTRL (0x1 << 19) +#define RXACTIVE (0x1 << 18) +#define PULLDOWN_EN (0x0 << 17) /* Pull Down Selection */ +#define PULLUP_EN (0x1 << 17) /* Pull Up Selection */ +#define PULLUDEN (0x0 << 16) /* Pull up/down enable */ +#define PULLUDDIS (0x1 << 16) /* Pull up/down disable */ +#define MODE(val) val /* used for Readability */ + +/* + * PAD CONTROL OFFSETS + * Field names corresponds to the pad signal name + */ +struct pad_signals { + int gpmc_ad0; + int gpmc_ad1; + int gpmc_ad2; + int gpmc_ad3; + int gpmc_ad4; + int gpmc_ad5; + int gpmc_ad6; + int gpmc_ad7; + int gpmc_ad8; + int gpmc_ad9; + int gpmc_ad10; + int gpmc_ad11; + int gpmc_ad12; + int gpmc_ad13; + int gpmc_ad14; + int gpmc_ad15; + int gpmc_a0; + int gpmc_a1; + int gpmc_a2; + int gpmc_a3; + int gpmc_a4; + int gpmc_a5; + int gpmc_a6; + int gpmc_a7; + int gpmc_a8; + int gpmc_a9; + int gpmc_a10; + int gpmc_a11; + int gpmc_wait0; + int gpmc_wpn; + int gpmc_be1n; + int gpmc_csn0; + int gpmc_csn1; + int gpmc_csn2; + int gpmc_csn3; + int gpmc_clk; + int gpmc_advn_ale; + int gpmc_oen_ren; + int gpmc_wen; + int gpmc_be0n_cle; + int lcd_data0; + int lcd_data1; + int lcd_data2; + int lcd_data3; + int lcd_data4; + int lcd_data5; + int lcd_data6; + int lcd_data7; + int lcd_data8; + int lcd_data9; + int lcd_data10; + int lcd_data11; + int lcd_data12; + int lcd_data13; + int lcd_data14; + int lcd_data15; + int lcd_vsync; + int lcd_hsync; + int lcd_pclk; + int lcd_ac_bias_en; + int mmc0_dat3; + int mmc0_dat2; + int mmc0_dat1; + int mmc0_dat0; + int mmc0_clk; + int mmc0_cmd; + int mii1_col; + int mii1_crs; + int mii1_rxerr; + int mii1_txen; + int mii1_rxdv; + int mii1_txd3; + int mii1_txd2; + int mii1_txd1; + int mii1_txd0; + int mii1_txclk; + int mii1_rxclk; + int mii1_rxd3; + int mii1_rxd2; + int mii1_rxd1; + int mii1_rxd0; + int rmii1_refclk; + int mdio_data; + int mdio_clk; + int spi0_sclk; + int spi0_d0; + int spi0_d1; + int spi0_cs0; + int spi0_cs1; + int ecap0_in_pwm0_out; + int uart0_ctsn; + int uart0_rtsn; + int uart0_rxd; + int uart0_txd; + int uart1_ctsn; + int uart1_rtsn; + int uart1_rxd; + int uart1_txd; + int i2c0_sda; + int i2c0_scl; + int mcasp0_aclkx; + int mcasp0_fsx; + int mcasp0_axr0; + int mcasp0_ahclkr; + int mcasp0_aclkr; + int mcasp0_fsr; + int mcasp0_axr1; + int mcasp0_ahclkx; + int cam0_hd; + int cam0_vd; + int cam0_field; + int cam0_wen; + int cam0_pclk; + int cam0_data8; + int cam0_data9; + int cam1_data9; + int cam1_data8; + int cam1_hd; + int cam1_vd; + int cam1_pclk; + int cam1_field; + int cam1_wen; + int cam1_data0; + int cam1_data1; + int cam1_data2; + int cam1_data3; + int cam1_data4; + int cam1_data5; + int cam1_data6; + int cam1_data7; + int cam0_data0; + int cam0_data1; + int cam0_data2; + int cam0_data3; + int cam0_data4; + int cam0_data5; + int cam0_data6; + int cam0_data7; + int uart3_rxd; + int uart3_txd; + int uart3_ctsn; + int uart3_rtsn; + int gpio5_8; + int gpio5_9; + int gpio5_10; + int gpio5_11; + int gpio5_12; + int gpio5_13; + int spi4_sclk; + int spi4_d0; + int spi4_d1; + int spi4_cs0; + int spi2_sclk; + int spi2_d0; + int spi2_d1; + int spi2_cs0; + int xdma_evt_intr0; + int xdma_evt_intr1; + int clkreq; + int nresetin_out; + int rsvd1; + int nnmi; + int rsvd2; + int rsvd3; + int tms; + int tdi; + int tdo; + int tck; + int ntrst; + int emu0; + int emu1; + int osc1_in; + int osc1_out; + int rtc_porz; + int ext_wakeup0; + int pmic_power_en0; + int usb0_drvvbus; + int usb1_drvvbus; +}; + +#endif /* _MUX_AM43XX_H_ */ diff --git a/arch/arm/include/asm/arch-am33xx/mux_ti814x.h b/arch/arm/include/asm/arch-am33xx/mux_ti814x.h new file mode 100644 index 0000000..a26e503 --- /dev/null +++ b/arch/arm/include/asm/arch-am33xx/mux_ti814x.h @@ -0,0 +1,311 @@ +/* + * mux_ti814x.h + * + * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _MUX_TI814X_H_ +#define _MUX_TI814X_H_ + +/* PAD Control Fields */ +#define PINCNTL_RSV_MSK (0x3 << 18) /* Reserved bitmask */ +#define PULLUP_EN (0x1 << 17) /* Pull UP Selection */ +#define PULLUDEN (0x0 << 16) /* Pull up enabled */ +#define PULLUDDIS (0x1 << 16) /* Pull up disabled */ +#define MODE(val) val /* used for Readability */ + +#define MUX_CFG(value, offset) \ +{ \ + int tmp; \ + tmp = __raw_readl(CTRL_BASE + offset); \ + tmp &= PINCNTL_RSV_MSK; \ + __raw_writel(tmp | value, (CTRL_BASE + offset));\ +} + +/* + * PAD CONTROL OFFSETS + * Field names corresponds to the pad signal name + */ +struct pad_signals { + int pincntl1; + int pincntl2; + int pincntl3; + int pincntl4; + int pincntl5; + int pincntl6; + int pincntl7; + int pincntl8; + int pincntl9; + int pincntl10; + int pincntl11; + int pincntl12; + int pincntl13; + int pincntl14; + int pincntl15; + int pincntl16; + int pincntl17; + int pincntl18; + int pincntl19; + int pincntl20; + int pincntl21; + int pincntl22; + int pincntl23; + int pincntl24; + int pincntl25; + int pincntl26; + int pincntl27; + int pincntl28; + int pincntl29; + int pincntl30; + int pincntl31; + int pincntl32; + int pincntl33; + int pincntl34; + int pincntl35; + int pincntl36; + int pincntl37; + int pincntl38; + int pincntl39; + int pincntl40; + int pincntl41; + int pincntl42; + int pincntl43; + int pincntl44; + int pincntl45; + int pincntl46; + int pincntl47; + int pincntl48; + int pincntl49; + int pincntl50; + int pincntl51; + int pincntl52; + int pincntl53; + int pincntl54; + int pincntl55; + int pincntl56; + int pincntl57; + int pincntl58; + int pincntl59; + int pincntl60; + int pincntl61; + int pincntl62; + int pincntl63; + int pincntl64; + int pincntl65; + int pincntl66; + int pincntl67; + int pincntl68; + int pincntl69; + int pincntl70; + int pincntl71; + int pincntl72; + int pincntl73; + int pincntl74; + int pincntl75; + int pincntl76; + int pincntl77; + int pincntl78; + int pincntl79; + int pincntl80; + int pincntl81; + int pincntl82; + int pincntl83; + int pincntl84; + int pincntl85; + int pincntl86; + int pincntl87; + int pincntl88; + int pincntl89; + int pincntl90; + int pincntl91; + int pincntl92; + int pincntl93; + int pincntl94; + int pincntl95; + int pincntl96; + int pincntl97; + int pincntl98; + int pincntl99; + int pincntl100; + int pincntl101; + int pincntl102; + int pincntl103; + int pincntl104; + int pincntl105; + int pincntl106; + int pincntl107; + int pincntl108; + int pincntl109; + int pincntl110; + int pincntl111; + int pincntl112; + int pincntl113; + int pincntl114; + int pincntl115; + int pincntl116; + int pincntl117; + int pincntl118; + int pincntl119; + int pincntl120; + int pincntl121; + int pincntl122; + int pincntl123; + int pincntl124; + int pincntl125; + int pincntl126; + int pincntl127; + int pincntl128; + int pincntl129; + int pincntl130; + int pincntl131; + int pincntl132; + int pincntl133; + int pincntl134; + int pincntl135; + int pincntl136; + int pincntl137; + int pincntl138; + int pincntl139; + int pincntl140; + int pincntl141; + int pincntl142; + int pincntl143; + int pincntl144; + int pincntl145; + int pincntl146; + int pincntl147; + int pincntl148; + int pincntl149; + int pincntl150; + int pincntl151; + int pincntl152; + int pincntl153; + int pincntl154; + int pincntl155; + int pincntl156; + int pincntl157; + int pincntl158; + int pincntl159; + int pincntl160; + int pincntl161; + int pincntl162; + int pincntl163; + int pincntl164; + int pincntl165; + int pincntl166; + int pincntl167; + int pincntl168; + int pincntl169; + int pincntl170; + int pincntl171; + int pincntl172; + int pincntl173; + int pincntl174; + int pincntl175; + int pincntl176; + int pincntl177; + int pincntl178; + int pincntl179; + int pincntl180; + int pincntl181; + int pincntl182; + int pincntl183; + int pincntl184; + int pincntl185; + int pincntl186; + int pincntl187; + int pincntl188; + int pincntl189; + int pincntl190; + int pincntl191; + int pincntl192; + int pincntl193; + int pincntl194; + int pincntl195; + int pincntl196; + int pincntl197; + int pincntl198; + int pincntl199; + int pincntl200; + int pincntl201; + int pincntl202; + int pincntl203; + int pincntl204; + int pincntl205; + int pincntl206; + int pincntl207; + int pincntl208; + int pincntl209; + int pincntl210; + int pincntl211; + int pincntl212; + int pincntl213; + int pincntl214; + int pincntl215; + int pincntl216; + int pincntl217; + int pincntl218; + int pincntl219; + int pincntl220; + int pincntl221; + int pincntl222; + int pincntl223; + int pincntl224; + int pincntl225; + int pincntl226; + int pincntl227; + int pincntl228; + int pincntl229; + int pincntl230; + int pincntl231; + int pincntl232; + int pincntl233; + int pincntl234; + int pincntl235; + int pincntl236; + int pincntl237; + int pincntl238; + int pincntl239; + int pincntl240; + int pincntl241; + int pincntl242; + int pincntl243; + int pincntl244; + int pincntl245; + int pincntl246; + int pincntl247; + int pincntl248; + int pincntl249; + int pincntl250; + int pincntl251; + int pincntl252; + int pincntl253; + int pincntl254; + int pincntl255; + int pincntl256; + int pincntl257; + int pincntl258; + int pincntl259; + int pincntl260; + int pincntl261; + int pincntl262; + int pincntl263; + int pincntl264; + int pincntl265; + int pincntl266; + int pincntl267; + int pincntl268; + int pincntl269; + int pincntl270; +}; + +#endif /* endif _MUX_TI814X_H_ */ diff --git a/arch/arm/include/asm/arch-am33xx/mux_ti816x.h b/arch/arm/include/asm/arch-am33xx/mux_ti816x.h new file mode 100644 index 0000000..e4e5a48 --- /dev/null +++ b/arch/arm/include/asm/arch-am33xx/mux_ti816x.h @@ -0,0 +1,363 @@ +/* + * mux_ti816x.h + * + * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com> + * Antoine Tenart, <atenart@adeneo-embedded.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _MUX_TI816X_H_ +#define _MUX_TI816X_H_ + +#include <common.h> +#include <asm/io.h> + +#define MUX_CFG(value, offset) \ + __raw_writel(value, (CTRL_BASE + offset)); + +#define PULLDOWN_EN (0x0 << 4) /* Pull Down Selection */ +#define PULLUP_EN (0x1 << 4) /* Pull Up Selection */ +#define PULLUDEN (0x0 << 3) /* Pull up enabled */ +#define PULLUDDIS (0x1 << 3) /* Pull up disabled */ +#define MODE(val) (val) /* used for Readability */ + + +/* + * PAD CONTROL OFFSETS + * Field names corresponds to the pad signal name + */ +struct pad_signals { + int pincntl1; + int pincntl2; + int pincntl3; + int pincntl4; + int pincntl5; + int pincntl6; + int pincntl7; + int pincntl8; + int pincntl9; + int pincntl10; + int pincntl11; + int pincntl12; + int pincntl13; + int pincntl14; + int pincntl15; + int pincntl16; + int pincntl17; + int pincntl18; + int pincntl19; + int pincntl20; + int pincntl21; + int pincntl22; + int pincntl23; + int pincntl24; + int pincntl25; + int pincntl26; + int pincntl27; + int pincntl28; + int pincntl29; + int pincntl30; + int pincntl31; + int pincntl32; + int pincntl33; + int pincntl34; + int pincntl35; + int pincntl36; + int pincntl37; + int pincntl38; + int pincntl39; + int pincntl40; + int pincntl41; + int pincntl42; + int pincntl43; + int pincntl44; + int pincntl45; + int pincntl46; + int pincntl47; + int pincntl48; + int pincntl49; + int pincntl50; + int pincntl51; + int pincntl52; + int pincntl53; + int pincntl54; + int pincntl55; + int pincntl56; + int pincntl57; + int pincntl58; + int pincntl59; + int pincntl60; + int pincntl61; + int pincntl62; + int pincntl63; + int pincntl64; + int pincntl65; + int pincntl66; + int pincntl67; + int pincntl68; + int pincntl69; + int pincntl70; + int pincntl71; + int pincntl72; + int pincntl73; + int pincntl74; + int pincntl75; + int pincntl76; + int pincntl77; + int pincntl78; + int pincntl79; + int pincntl80; + int pincntl81; + int pincntl82; + int pincntl83; + int pincntl84; + int pincntl85; + int pincntl86; + int pincntl87; + int pincntl88; + int pincntl89; + int pincntl90; + int pincntl91; + int pincntl92; + int pincntl93; + int pincntl94; + int pincntl95; + int pincntl96; + int pincntl97; + int pincntl98; + int pincntl99; + int pincntl100; + int pincntl101; + int pincntl102; + int pincntl103; + int pincntl104; + int pincntl105; + int pincntl106; + int pincntl107; + int pincntl108; + int pincntl109; + int pincntl110; + int pincntl111; + int pincntl112; + int pincntl113; + int pincntl114; + int pincntl115; + int pincntl116; + int pincntl117; + int pincntl118; + int pincntl119; + int pincntl120; + int pincntl121; + int pincntl122; + int pincntl123; + int pincntl124; + int pincntl125; + int pincntl126; + int pincntl127; + int pincntl128; + int pincntl129; + int pincntl130; + int pincntl131; + int pincntl132; + int pincntl133; + int pincntl134; + int pincntl135; + int pincntl136; + int pincntl137; + int pincntl138; + int pincntl139; + int pincntl140; + int pincntl141; + int pincntl142; + int pincntl143; + int pincntl144; + int pincntl145; + int pincntl146; + int pincntl147; + int pincntl148; + int pincntl149; + int pincntl150; + int pincntl151; + int pincntl152; + int pincntl153; + int pincntl154; + int pincntl155; + int pincntl156; + int pincntl157; + int pincntl158; + int pincntl159; + int pincntl160; + int pincntl161; + int pincntl162; + int pincntl163; + int pincntl164; + int pincntl165; + int pincntl166; + int pincntl167; + int pincntl168; + int pincntl169; + int pincntl170; + int pincntl171; + int pincntl172; + int pincntl173; + int pincntl174; + int pincntl175; + int pincntl176; + int pincntl177; + int pincntl178; + int pincntl179; + int pincntl180; + int pincntl181; + int pincntl182; + int pincntl183; + int pincntl184; + int pincntl185; + int pincntl186; + int pincntl187; + int pincntl188; + int pincntl189; + int pincntl190; + int pincntl191; + int pincntl192; + int pincntl193; + int pincntl194; + int pincntl195; + int pincntl196; + int pincntl197; + int pincntl198; + int pincntl199; + int pincntl200; + int pincntl201; + int pincntl202; + int pincntl203; + int pincntl204; + int pincntl205; + int pincntl206; + int pincntl207; + int pincntl208; + int pincntl209; + int pincntl210; + int pincntl211; + int pincntl212; + int pincntl213; + int pincntl214; + int pincntl215; + int pincntl216; + int pincntl217; + int pincntl218; + int pincntl219; + int pincntl220; + int pincntl221; + int pincntl222; + int pincntl223; + int pincntl224; + int pincntl225; + int pincntl226; + int pincntl227; + int pincntl228; + int pincntl229; + int pincntl230; + int pincntl231; + int pincntl232; + int pincntl233; + int pincntl234; + int pincntl235; + int pincntl236; + int pincntl237; + int pincntl238; + int pincntl239; + int pincntl240; + int pincntl241; + int pincntl242; + int pincntl243; + int pincntl244; + int pincntl245; + int pincntl246; + int pincntl247; + int pincntl248; + int pincntl249; + int pincntl250; + int pincntl251; + int pincntl252; + int pincntl253; + int pincntl254; + int pincntl255; + int pincntl256; + int pincntl257; + int pincntl258; + int pincntl259; + int pincntl260; + int pincntl261; + int pincntl262; + int pincntl263; + int pincntl264; + int pincntl265; + int pincntl266; + int pincntl267; + int pincntl268; + int pincntl269; + int pincntl270; + int pincntl271; + int pincntl272; + int pincntl273; + int pincntl274; + int pincntl275; + int pincntl276; + int pincntl277; + int pincntl278; + int pincntl279; + int pincntl280; + int pincntl281; + int pincntl282; + int pincntl283; + int pincntl284; + int pincntl285; + int pincntl286; + int pincntl287; + int pincntl288; + int pincntl289; + int pincntl290; + int pincntl291; + int pincntl292; + int pincntl293; + int pincntl294; + int pincntl295; + int pincntl296; + int pincntl297; + int pincntl298; + int pincntl299; + int pincntl300; + int pincntl301; + int pincntl302; + int pincntl303; + int pincntl304; + int pincntl305; + int pincntl306; + int pincntl307; + int pincntl308; + int pincntl309; + int pincntl310; + int pincntl311; + int pincntl312; + int pincntl313; + int pincntl314; + int pincntl315; + int pincntl316; + int pincntl317; + int pincntl318; + int pincntl319; + int pincntl320; + int pincntl321; + int pincntl322; + int pincntl323; +}; + +#endif /* endif _MUX_TI816X_H_ */ diff --git a/arch/arm/include/asm/arch-am33xx/omap.h b/arch/arm/include/asm/arch-am33xx/omap.h new file mode 100644 index 0000000..bc9f0a1 --- /dev/null +++ b/arch/arm/include/asm/arch-am33xx/omap.h @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * omap.h + * + * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ + * + * Author: + * Chandan Nath <chandan.nath@ti.com> + * + * Derived from OMAP4 work by + * Aneesh V <aneesh@ti.com> + */ + +#ifndef _OMAP_H_ +#define _OMAP_H_ + +#include <linux/sizes.h> + +#ifdef CONFIG_AM33XX +#define NON_SECURE_SRAM_START 0x402F0400 +#define NON_SECURE_SRAM_END 0x40310000 +#define NON_SECURE_SRAM_IMG_END 0x4030B800 +#elif defined(CONFIG_TI816X) || defined(CONFIG_TI814X) +#define NON_SECURE_SRAM_START 0x40300000 +#define NON_SECURE_SRAM_END 0x40320000 +#define NON_SECURE_SRAM_IMG_END 0x4031B800 +#elif defined(CONFIG_AM43XX) +#define NON_SECURE_SRAM_START 0x402F0400 +#define NON_SECURE_SRAM_END 0x40340000 +#define NON_SECURE_SRAM_IMG_END 0x40337DE0 +#define QSPI_BASE 0x47900000 +#endif +#define SRAM_SCRATCH_SPACE_ADDR (NON_SECURE_SRAM_IMG_END - SZ_1K) + +/* Boot parameters */ +#ifndef __ASSEMBLY__ +struct omap_boot_parameters { + unsigned int reserved; + unsigned int boot_device_descriptor; + unsigned char boot_device; + unsigned char reset_reason; +}; + +#define DEVICE_TYPE_SHIFT 0x8 +#define DEVICE_TYPE_MASK (0x7 << DEVICE_TYPE_SHIFT) +#endif + +#endif diff --git a/arch/arm/include/asm/arch-am33xx/spl.h b/arch/arm/include/asm/arch-am33xx/spl.h new file mode 100644 index 0000000..f3910c2 --- /dev/null +++ b/arch/arm/include/asm/arch-am33xx/spl.h @@ -0,0 +1,72 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2012 + * Texas Instruments, <www.ti.com> + */ +#ifndef _ASM_ARCH_SPL_H_ +#define _ASM_ARCH_SPL_H_ + +#define BOOT_DEVICE_NONE 0x00 +#define BOOT_DEVICE_MMC2_2 0xFF + +#if defined(CONFIG_TI814X) +#define BOOT_DEVICE_XIP 0x01 +#define BOOT_DEVICE_XIPWAIT 0x02 +#define BOOT_DEVICE_NAND 0x05 +#define BOOT_DEVICE_NAND_I2C 0x06 +#define BOOT_DEVICE_MMC2 0x08 /* ROM only supports 2nd instance. */ +#define BOOT_DEVICE_MMC1 0x09 +#define BOOT_DEVICE_SPI 0x15 +#define BOOT_DEVICE_UART 0x41 +#define BOOT_DEVICE_USBETH 0x44 +#define BOOT_DEVICE_CPGMAC 0x46 + +#define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC2 +#define MMC_BOOT_DEVICES_END BOOT_DEVICE_MMC1 +#elif defined(CONFIG_TI816X) +#define BOOT_DEVICE_XIP 0x01 +#define BOOT_DEVICE_XIPWAIT 0x02 +#define BOOT_DEVICE_NAND 0x03 +#define BOOT_DEVICE_ONENAND 0x04 +#define BOOT_DEVICE_MMC2 0x05 /* ROM only supports 2nd instance. */ +#define BOOT_DEVICE_MMC1 0x06 +#define BOOT_DEVICE_UART 0x43 +#define BOOT_DEVICE_USB 0x45 + +#define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC2 +#define MMC_BOOT_DEVICES_END BOOT_DEVICE_MMC1 +#elif defined(CONFIG_AM33XX) +#define BOOT_DEVICE_XIP 0x01 +#define BOOT_DEVICE_XIPWAIT 0x02 +#define BOOT_DEVICE_NAND 0x05 +#define BOOT_DEVICE_NAND_I2C 0x06 +#define BOOT_DEVICE_MMC1 0x08 +#define BOOT_DEVICE_MMC2 0x09 +#define BOOT_DEVICE_SPI 0x0B +#define BOOT_DEVICE_UART 0x41 +#define BOOT_DEVICE_USBETH 0x44 +#define BOOT_DEVICE_CPGMAC 0x46 +#define BOOT_DEVICE_ONENAND 0xFF /* ROM does not support OneNAND. */ + +#define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC1 +#define MMC_BOOT_DEVICES_END BOOT_DEVICE_MMC2 +#elif defined(CONFIG_AM43XX) +#define BOOT_DEVICE_NOR 0x01 +#define BOOT_DEVICE_NAND 0x05 +#define BOOT_DEVICE_MMC1 0x07 +#define BOOT_DEVICE_MMC2 0x08 +#define BOOT_DEVICE_SPI 0x0A +#define BOOT_DEVICE_USB 0x0D +#define BOOT_DEVICE_UART 0x41 +#define BOOT_DEVICE_USBETH 0x45 +#define BOOT_DEVICE_CPGMAC 0x47 + +#define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC1 +#ifdef CONFIG_SPL_USB_STORAGE +#define MMC_BOOT_DEVICES_END BOOT_DEVICE_USB +#else +#define MMC_BOOT_DEVICES_END BOOT_DEVICE_MMC2 +#endif +#endif + +#endif diff --git a/arch/arm/include/asm/arch-am33xx/sys_proto.h b/arch/arm/include/asm/arch-am33xx/sys_proto.h new file mode 100644 index 0000000..be17aad --- /dev/null +++ b/arch/arm/include/asm/arch-am33xx/sys_proto.h @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * sys_proto.h + * + * System information header + * + * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ + */ + +#ifndef _SYS_PROTO_H_ +#define _SYS_PROTO_H_ +#include <linux/mtd/omap_gpmc.h> +#include <asm/arch/cpu.h> + +u32 get_cpu_rev(void); +u32 get_sysboot_value(void); + +extern struct ctrl_stat *cstat; +u32 get_device_type(void); +void save_omap_boot_params(void); +void setup_early_clocks(void); +void setup_clocks_for_console(void); +void mpu_pll_config_val(int mpull_m); +void ddr_pll_config(unsigned int ddrpll_M); + +void sdelay(unsigned long); + +void gpmc_init(void); +void enable_gpmc_cs_config(const u32 *gpmc_config, const struct gpmc_cs *cs, u32 base, + u32 size); +int omap_nand_switch_ecc(uint32_t, uint32_t); + +void set_uart_mux_conf(void); +void set_mux_conf_regs(void); +void sdram_init(void); +u32 wait_on_value(u32, u32, void *, u32); +#ifdef CONFIG_NOR_BOOT +void enable_norboot_pin_mux(void); +#endif +void am33xx_spl_board_init(void); +int am335x_get_efuse_mpu_max_freq(struct ctrl_dev *cdev); +int am335x_get_mpu_vdd(int sil_rev, int frequency); +int am335x_get_tps65910_mpu_vdd(int sil_rev, int frequency); +#endif + +void enable_usb_clocks(int index); +void disable_usb_clocks(int index); +void do_board_detect(void); +u32 get_sys_clk_index(void); |