3 files changed, 77 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-stm32f4/gpio.h b/arch/arm/include/asm/arch-stm32f4/gpio.h
new file mode 100644
index 0000000..490f686
--- /dev/null
+++ b/arch/arm/include/asm/arch-stm32f4/gpio.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2011
+ * Yuri Tikhonov, Emcraft Systems, yur@emcraft.com
+ *
+ * (C) Copyright 2015
+ * Kamil Lulko, <kamil.lulko@gmail.com>
+ */
+
+#ifndef _STM32_GPIO_H_
+#define _STM32_GPIO_H_
+
+#include <asm/arch-stm32/gpio.h>
+
+#endif /* _STM32_GPIO_H_ */
diff --git a/arch/arm/include/asm/arch-stm32f4/stm32.h b/arch/arm/include/asm/arch-stm32f4/stm32.h
new file mode 100644
index 0000000..2094bd7
--- /dev/null
+++ b/arch/arm/include/asm/arch-stm32f4/stm32.h
@@ -0,0 +1,40 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2011
+ * Yuri Tikhonov, Emcraft Systems, yur@emcraft.com
+ *
+ * (C) Copyright 2015
+ * Kamil Lulko, <kamil.lulko@gmail.com>
+ */
+
+#ifndef _MACH_STM32_H_
+#define _MACH_STM32_H_
+
+#include <asm/arch-stm32/stm32f.h>
+
+/*
+ * Peripheral memory map
+ */
+#define STM32_SYSMEM_BASE	0x1FFF0000
+
+/*
+ * Register maps
+ */
+struct stm32_u_id_regs {
+	u32 u_id_low;
+	u32 u_id_mid;
+	u32 u_id_high;
+};
+
+/*
+ * Registers access macros
+ */
+#define STM32_U_ID_BASE		(STM32_SYSMEM_BASE + 0x7A10)
+#define STM32_U_ID		((struct stm32_u_id_regs *)STM32_U_ID_BASE)
+static const u32 sect_sz_kb[CONFIG_SYS_MAX_FLASH_SECT] = {
+	[0 ... 3] =	16 * 1024,
+	[4] =		64 * 1024,
+	[5 ... 11] =	128 * 1024
+};
+
+#endif /* _MACH_STM32_H_ */
diff --git a/arch/arm/include/asm/arch-stm32f4/stm32_pwr.h b/arch/arm/include/asm/arch-stm32f4/stm32_pwr.h
new file mode 100644
index 0000000..de42996
--- /dev/null
+++ b/arch/arm/include/asm/arch-stm32f4/stm32_pwr.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
+ * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics.
+ */
+
+#ifndef __STM32_PWR_H_
+
+/*
+ * Offsets of some PWR registers
+ */
+#define PWR_CR1_ODEN			BIT(16)
+#define PWR_CR1_ODSWEN			BIT(17)
+#define PWR_CSR1_ODRDY			BIT(16)
+#define PWR_CSR1_ODSWRDY		BIT(17)
+
+struct stm32_pwr_regs {
+	u32 cr1;   /* power control register 1 */
+	u32 csr1;  /* power control/status register 2 */
+};
+
+#endif /* __STM32_PWR_H_ */