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Diffstat (limited to 'arch/microblaze/include/asm/cache.h')
| -rw-r--r-- | arch/microblaze/include/asm/cache.h | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/arch/microblaze/include/asm/cache.h b/arch/microblaze/include/asm/cache.h new file mode 100644 index 0000000..baee01a --- /dev/null +++ b/arch/microblaze/include/asm/cache.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2011 The Chromium OS Authors. + */ + +#ifndef __MICROBLAZE_CACHE_H__ +#define __MICROBLAZE_CACHE_H__ + +/* + * The microblaze can have either a 4 or 16 byte cacheline depending on whether + * you are using OPB(4) or CacheLink(16). If the board config has not specified + * a cacheline size we assume the larger value of 16 bytes for DMA buffer + * alignment. + */ +#ifdef CONFIG_SYS_CACHELINE_SIZE +#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE +#else +#define ARCH_DMA_MINALIGN 16 +#endif + +#endif /* __MICROBLAZE_CACHE_H__ */ |