diff options
Diffstat (limited to 'arch/x86/include/asm/acpi')
| -rw-r--r-- | arch/x86/include/asm/acpi/debug.asl | 135 | ||||
| -rw-r--r-- | arch/x86/include/asm/acpi/global_nvs.h | 18 | ||||
| -rw-r--r-- | arch/x86/include/asm/acpi/globutil.asl | 112 | ||||
| -rw-r--r-- | arch/x86/include/asm/acpi/irq_helper.h | 110 | ||||
| -rw-r--r-- | arch/x86/include/asm/acpi/irqlinks.asl | 485 | ||||
| -rw-r--r-- | arch/x86/include/asm/acpi/irqroute.asl | 47 | ||||
| -rw-r--r-- | arch/x86/include/asm/acpi/sleepstates.asl | 14 | ||||
| -rw-r--r-- | arch/x86/include/asm/acpi/statdef.asl | 81 |
8 files changed, 1002 insertions, 0 deletions
diff --git a/arch/x86/include/asm/acpi/debug.asl b/arch/x86/include/asm/acpi/debug.asl new file mode 100644 index 0000000..6025507 --- /dev/null +++ b/arch/x86/include/asm/acpi/debug.asl @@ -0,0 +1,135 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2008 Advanced Micro Devices, Inc. + * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com> + * + * Modified from coreboot src/arch/x86/acpi/debug.asl + */ + +/* POST register region */ +OperationRegion(X80, SystemIO, 0x80, 1) +Field(X80, ByteAcc, NoLock, Preserve) +{ + P80, 8 +} + +/* Legacy serial port register region */ +OperationRegion(CREG, SystemIO, 0x3F8, 8) +Field(CREG, ByteAcc, NoLock, Preserve) +{ + CDAT, 8, + CDLM, 8, + , 8, + CLCR, 8, + CMCR, 8, + CLSR, 8 +} + +/* DINI - Initialize the serial port to 115200 8-N-1 */ +Method(DINI) +{ + Store(0x83, CLCR) + Store(0x01, CDAT) /* 115200 baud (low) */ + Store(0x00, CDLM) /* 115200 baud (high) */ + Store(0x03, CLCR) /* word=8 stop=1 parity=none */ + Store(0x03, CMCR) /* DTR=1 RTS=1 out1/2=Off loop=Off */ + Store(0x00, CDLM) /* turn off interrupts */ +} + +/* THRE - Wait for serial port transmitter holding register to go empty */ +Method(THRE) +{ + And(CLSR, 0x20, Local0) + While (LEqual(Local0, Zero)) { + And(CLSR, 0x20, Local0) + } +} + +/* OUTX - Send a single raw character */ +Method(OUTX, 1) +{ + THRE() + Store(Arg0, CDAT) +} + +/* OUTC - Send a single character, expanding LF into CR/LF */ +Method(OUTC, 1) +{ + If (LEqual(Arg0, 0x0a)) { + OUTX(0x0d) + } + OUTX(Arg0) +} + +/* DBGN - Send a single hex nibble */ +Method(DBGN, 1) +{ + And(Arg0, 0x0f, Local0) + If (LLess(Local0, 10)) { + Add(Local0, 0x30, Local0) + } Else { + Add(Local0, 0x37, Local0) + } + OUTC(Local0) +} + +/* DBGB - Send a hex byte */ +Method(DBGB, 1) +{ + ShiftRight(Arg0, 4, Local0) + DBGN(Local0) + DBGN(Arg0) +} + +/* DBGW - Send a hex word */ +Method(DBGW, 1) +{ + ShiftRight(Arg0, 8, Local0) + DBGB(Local0) + DBGB(Arg0) +} + +/* DBGD - Send a hex dword */ +Method(DBGD, 1) +{ + ShiftRight(Arg0, 16, Local0) + DBGW(Local0) + DBGW(Arg0) +} + +/* Get a char from a string */ +Method(GETC, 2) +{ + CreateByteField(Arg0, Arg1, DBGC) + Return (DBGC) +} + +/* DBGO - Send either a string or an integer */ +Method(DBGO, 1, Serialized) +{ + If (LEqual(ObjectType(Arg0), 1)) { + If (LGreater(Arg0, 0xffff)) { + DBGD(Arg0) + } Else { + If (LGreater(Arg0, 0xff)) { + DBGW(Arg0) + } Else { + DBGB(Arg0) + } + } + } Else { + Name(BDBG, Buffer(80) {}) + Store(Arg0, BDBG) + Store(0, Local1) + While (One) { + Store(GETC(BDBG, Local1), Local0) + If (LEqual(Local0, 0)) { + Return (Zero) + } + OUTC(Local0) + Increment(Local1) + } + } + + Return (Zero) +} diff --git a/arch/x86/include/asm/acpi/global_nvs.h b/arch/x86/include/asm/acpi/global_nvs.h new file mode 100644 index 0000000..d56d35c --- /dev/null +++ b/arch/x86/include/asm/acpi/global_nvs.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com> + */ + +#ifndef _ACPI_GNVS_H_ +#define _ACPI_GNVS_H_ + +/* + * This file provides two ACPI global NVS macros: ACPI_GNVS_ADDR and + * ACPI_GNVS_SIZE. They are to be used in platform's global_nvs.asl file + * to declare the GNVS OperationRegion, as well as write_acpi_tables() + * for the GNVS address runtime fix up. + */ +#define ACPI_GNVS_ADDR 0xdeadbeef +#define ACPI_GNVS_SIZE 0x100 + +#endif /* _ACPI_GNVS_H_ */ diff --git a/arch/x86/include/asm/acpi/globutil.asl b/arch/x86/include/asm/acpi/globutil.asl new file mode 100644 index 0000000..5d50ef3 --- /dev/null +++ b/arch/x86/include/asm/acpi/globutil.asl @@ -0,0 +1,112 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2008 Advanced Micro Devices, Inc. + * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com> + * + * Modified from coreboot src/arch/x86/acpi/globutil.asl + */ + +Method(MIN, 2) +{ + If (LLess(Arg0, Arg1)) { + Return (Arg0) + } Else { + Return (Arg1) + } +} + +Method(SLEN, 1) +{ + Store(Arg0, Local0) + Return (Sizeof(Local0)) +} + +Method(S2BF, 1, Serialized) +{ + Add(SLEN(Arg0), One, Local0) + Name(BUFF, Buffer(Local0) {}) + Store(Arg0, BUFF) + Return (BUFF) +} + +/* + * SCMP - Strong string compare + * + * Checks both length and content + */ +Method(SCMP, 2) +{ + Store(S2BF(Arg0), Local0) + Store(S2BF(Arg1), Local1) + Store(Zero, Local4) + Store(SLEN(Arg0), Local5) + Store(SLEN(Arg1), Local6) + Store(MIN(Local5, Local6), Local7) + + While (LLess(Local4, Local7)) { + Store(Derefof(Index(Local0, Local4)), Local2) + Store(Derefof(Index(Local1, Local4)), Local3) + If (LGreater(Local2, Local3)) { + Return (One) + } Else { + If (LLess(Local2, Local3)) { + Return (Ones) + } + } + Increment(Local4) + } + + If (LLess(Local4, Local5)) { + Return (One) + } Else { + If (LLess(Local4, Local6)) { + Return (Ones) + } Else { + Return (Zero) + } + } +} + +/* + * WCMP - Weak string compare + * + * Checks to find Arg1 at beginning of Arg0. + * Fails if length(Arg0) < length(Arg1). + * Returns 0 on fail, 1 on pass. + */ +Method(WCMP, 2) +{ + Store(S2BF(Arg0), Local0) + Store(S2BF(Arg1), Local1) + If (LLess(SLEN(Arg0), SLEN(Arg1))) { + Return (Zero) + } + Store(Zero, Local2) + Store(SLEN(Arg1), Local3) + + While (LLess(Local2, Local3)) { + If (LNotEqual(Derefof(Index(Local0, Local2)), + Derefof(Index(Local1, Local2)))) { + Return (Zero) + } + Increment(Local2) + } + + Return (One) +} + +/* + * I2BM - Returns Bit Map + * + * Arg0 = IRQ Number (0-15) + */ +Method(I2BM, 1) +{ + Store(0, Local0) + If (LNotEqual(Arg0, 0)) { + Store(1, Local1) + ShiftLeft(Local1, Arg0, Local0) + } + + Return (Local0) +} diff --git a/arch/x86/include/asm/acpi/irq_helper.h b/arch/x86/include/asm/acpi/irq_helper.h new file mode 100644 index 0000000..6e404f4 --- /dev/null +++ b/arch/x86/include/asm/acpi/irq_helper.h @@ -0,0 +1,110 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2014 Sage Electronics Engineering, LLC. + * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com> + * + * Modified from coreboot src/soc/intel/baytrail/include/soc/irq_helper.h + */ + +/* + * This file intentionally gets included multiple times, to set pic and apic + * modes, so should not have guard statements added. + */ + +/* + * This file will use irqroute.asl and irqroute.h to generate the ACPI IRQ + * routing for the platform being compiled. + * + * This method uses #defines in irqroute.h along with the macros contained + * in this file to generate an IRQ routing for each PCI device in the system. + */ + +#undef PCI_DEV_PIRQ_ROUTES +#undef PCI_DEV_PIRQ_ROUTE +#undef ACPI_DEV_IRQ +#undef PCIE_BRIDGE_DEV +#undef RP_IRQ_ROUTES +#undef ROOTPORT_METHODS +#undef ROOTPORT_IRQ_ROUTES +#undef RP_METHOD + +#if defined(PIC_MODE) + +#define ACPI_DEV_IRQ(dev_, pin_, pin_name_) \ + Package() { ## dev_ ## ffff, pin_, \_SB.PCI0.LPCB.LNK ## pin_name_, 0 } + +#define RP_IRQ_ROUTES(prefix_, func_, a_, b_, c_, d_) \ +Name(prefix_ ## func_ ## P, Package() \ +{ \ + ACPI_DEV_IRQ(0x0000, 0, a_), \ + ACPI_DEV_IRQ(0x0000, 1, b_), \ + ACPI_DEV_IRQ(0x0000, 2, c_), \ + ACPI_DEV_IRQ(0x0000, 3, d_), \ +}) + +/* define as blank so ROOTPORT_METHODS only gets inserted once */ +#define ROOTPORT_METHODS(prefix_, dev_) + +#else /* defined(PIC_MODE) */ + +#define ACPI_DEV_IRQ(dev_, pin_, pin_name_) \ + Package() { ## dev_ ## ffff, pin_, 0, PIRQ ## pin_name_ ## _APIC_IRQ } + +#define RP_IRQ_ROUTES(prefix_, func_, a_, b_, c_, d_) \ +Name(prefix_ ## func_ ## A, Package() \ +{ \ + ACPI_DEV_IRQ(0x0000, 0, a_), \ + ACPI_DEV_IRQ(0x0000, 1, b_), \ + ACPI_DEV_IRQ(0x0000, 2, c_), \ + ACPI_DEV_IRQ(0x0000, 3, d_), \ +}) + +#define ROOTPORT_METHODS(prefix_, dev_) \ + RP_METHOD(prefix_, dev_, 0) \ + RP_METHOD(prefix_, dev_, 1) \ + RP_METHOD(prefix_, dev_, 2) \ + RP_METHOD(prefix_, dev_, 3) \ + RP_METHOD(prefix_, dev_, 4) \ + RP_METHOD(prefix_, dev_, 5) \ + RP_METHOD(prefix_, dev_, 6) \ + RP_METHOD(prefix_, dev_, 7) + +#endif /* defined(PIC_MODE) */ + +#define PCI_DEV_PIRQ_ROUTE(dev_, a_, b_, c_, d_) \ + ACPI_DEV_IRQ(dev_, 0, a_), \ + ACPI_DEV_IRQ(dev_, 1, b_), \ + ACPI_DEV_IRQ(dev_, 2, c_), \ + ACPI_DEV_IRQ(dev_, 3, d_) + +#define PCIE_BRIDGE_DEV(prefix_, dev_, a_, b_, c_, d_) \ + ROOTPORT_IRQ_ROUTES(prefix_, a_, b_, c_, d_) \ + ROOTPORT_METHODS(prefix_, dev_) + +#define ROOTPORT_IRQ_ROUTES(prefix_, a_, b_, c_, d_) \ + RP_IRQ_ROUTES(prefix_, 0, a_, b_, c_, d_) \ + RP_IRQ_ROUTES(prefix_, 1, b_, c_, d_, a_) \ + RP_IRQ_ROUTES(prefix_, 2, c_, d_, a_, b_) \ + RP_IRQ_ROUTES(prefix_, 3, d_, a_, b_, c_) \ + RP_IRQ_ROUTES(prefix_, 4, a_, b_, c_, d_) \ + RP_IRQ_ROUTES(prefix_, 5, b_, c_, d_, a_) \ + RP_IRQ_ROUTES(prefix_, 6, c_, d_, a_, b_) \ + RP_IRQ_ROUTES(prefix_, 7, d_, a_, b_, c_) + +#define RP_METHOD(prefix_, dev_, func_)\ +Device (prefix_ ## 0 ## func_) \ +{ \ + Name(_ADR, dev_ ## 000 ## func_) \ + Name(_PRW, Package() { 0, 0 }) \ + Method(_PRT) { \ + If (PICM) { \ + Return (prefix_ ## func_ ## A) \ + } Else { \ + Return (prefix_ ## func_ ## P) \ + } \ + } \ +} + +/* SoC specific PIRQ route configuration */ +#include <asm/arch/acpi/irqroute.h> diff --git a/arch/x86/include/asm/acpi/irqlinks.asl b/arch/x86/include/asm/acpi/irqlinks.asl new file mode 100644 index 0000000..9fc83a5 --- /dev/null +++ b/arch/x86/include/asm/acpi/irqlinks.asl @@ -0,0 +1,485 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com> + * + * Modified from coreboot src/soc/intel/baytrail/acpi/irqlinks.asl + */ + +/* + * Intel chipset PIRQ routing control ASL description + * + * The programming interface is common to most Intel chipsets. But the PRTx + * registers may be mapped to different blocks. Some chipsets map them to LPC + * device (00:1f:00) PCI configuration space (like TunnelCreek, Quark), while + * some newer Atom SoCs (like BayTrail, Braswell) map them to Intel Legacy + * Block (ILB) memory space. + * + * This file defines 8 PCI IRQ link devices which corresponds to 8 PIRQ lines + * PIRQ A/B/C/D/E/F/G/H. To incorperate this file, the PRTx registers must be + * defined somewhere else in the platform's ASL files. + */ + +Device (LNKA) +{ + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 1) + + /* Disable method */ + Method(_DIS, 0, Serialized) + { + Store(0x80, PRTA) + } + + /* Possible Resource Settings for this Link */ + Name(_PRS, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) { 5, 6, 7, 10, 11, 12, 14, 15 } + }) + + /* Current Resource Settings for this link */ + Method(_CRS, 0, Serialized) + { + Name(RTLA, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) {} + }) + CreateWordField(RTLA, 1, IRQ0) + + /* Clear the WordField */ + Store(Zero, IRQ0) + + /* Set the bit from PRTA */ + ShiftLeft(1, And(PRTA, 0x0f), IRQ0) + + Return (RTLA) + } + + /* Set Resource Setting for this IRQ link */ + Method(_SRS, 1, Serialized) + { + CreateWordField(Arg0, 1, IRQ0) + + /* Which bit is set? */ + FindSetRightBit(IRQ0, Local0) + + Decrement(Local0) + Store(Local0, PRTA) + } + + /* Status */ + Method(_STA, 0, Serialized) + { + If (And(PRTA, 0x80)) { + Return (STA_DISABLED) + } Else { + Return (STA_INVISIBLE) + } + } +} + +Device (LNKB) +{ + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 2) + + /* Disable method */ + Method(_DIS, 0, Serialized) + { + Store(0x80, PRTB) + } + + /* Possible Resource Settings for this Link */ + Name(_PRS, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) { 5, 6, 7, 10, 11, 12, 14, 15 } + }) + + /* Current Resource Settings for this link */ + Method(_CRS, 0, Serialized) + { + Name(RTLB, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) {} + }) + CreateWordField(RTLB, 1, IRQ0) + + /* Clear the WordField */ + Store(Zero, IRQ0) + + /* Set the bit from PRTB */ + ShiftLeft(1, And(PRTB, 0x0f), IRQ0) + + Return (RTLB) + } + + /* Set Resource Setting for this IRQ link */ + Method(_SRS, 1, Serialized) + { + CreateWordField(Arg0, 1, IRQ0) + + /* Which bit is set? */ + FindSetRightBit(IRQ0, Local0) + + Decrement(Local0) + Store(Local0, PRTB) + } + + /* Status */ + Method(_STA, 0, Serialized) + { + If (And(PRTB, 0x80)) { + Return (STA_DISABLED) + } Else { + Return (STA_INVISIBLE) + } + } +} + +Device (LNKC) +{ + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 3) + + /* Disable method */ + Method(_DIS, 0, Serialized) + { + Store(0x80, PRTC) + } + + /* Possible Resource Settings for this Link */ + Name(_PRS, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) { 5, 6, 7, 10, 11, 12, 14, 15 } + }) + + /* Current Resource Settings for this link */ + Method(_CRS, 0, Serialized) + { + Name(RTLC, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) {} + }) + CreateWordField(RTLC, 1, IRQ0) + + /* Clear the WordField */ + Store(Zero, IRQ0) + + /* Set the bit from PRTC */ + ShiftLeft(1, And(PRTC, 0x0f), IRQ0) + + Return (RTLC) + } + + /* Set Resource Setting for this IRQ link */ + Method(_SRS, 1, Serialized) + { + CreateWordField(Arg0, 1, IRQ0) + + /* Which bit is set? */ + FindSetRightBit(IRQ0, Local0) + + Decrement(Local0) + Store(Local0, PRTC) + } + + /* Status */ + Method(_STA, 0, Serialized) + { + If (And(PRTC, 0x80)) { + Return (STA_DISABLED) + } Else { + Return (STA_INVISIBLE) + } + } +} + +Device (LNKD) +{ + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 4) + + /* Disable method */ + Method(_DIS, 0, Serialized) + { + Store(0x80, PRTD) + } + + /* Possible Resource Settings for this Link */ + Name(_PRS, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) { 5, 6, 7, 10, 11, 12, 14, 15 } + }) + + /* Current Resource Settings for this link */ + Method(_CRS, 0, Serialized) + { + Name(RTLD, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) {} + }) + CreateWordField(RTLD, 1, IRQ0) + + /* Clear the WordField */ + Store(Zero, IRQ0) + + /* Set the bit from PRTD */ + ShiftLeft(1, And(PRTD, 0x0f), IRQ0) + + Return (RTLD) + } + + /* Set Resource Setting for this IRQ link */ + Method(_SRS, 1, Serialized) + { + CreateWordField(Arg0, 1, IRQ0) + + /* Which bit is set? */ + FindSetRightBit(IRQ0, Local0) + + Decrement(Local0) + Store(Local0, PRTD) + } + + /* Status */ + Method(_STA, 0, Serialized) + { + If (And(PRTD, 0x80)) { + Return (STA_DISABLED) + } Else { + Return (STA_INVISIBLE) + } + } +} + +Device (LNKE) +{ + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 5) + + /* Disable method */ + Method(_DIS, 0, Serialized) + { + Store(0x80, PRTE) + } + + /* Possible Resource Settings for this Link */ + Name(_PRS, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) { 5, 6, 7, 10, 11, 12, 14, 15 } + }) + + /* Current Resource Settings for this link */ + Method(_CRS, 0, Serialized) + { + Name(RTLE, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) {} + }) + CreateWordField(RTLE, 1, IRQ0) + + /* Clear the WordField */ + Store(Zero, IRQ0) + + /* Set the bit from PRTE */ + ShiftLeft(1, And(PRTE, 0x0f), IRQ0) + + Return (RTLE) + } + + /* Set Resource Setting for this IRQ link */ + Method(_SRS, 1, Serialized) + { + CreateWordField(Arg0, 1, IRQ0) + + /* Which bit is set? */ + FindSetRightBit(IRQ0, Local0) + + Decrement(Local0) + Store(Local0, PRTE) + } + + /* Status */ + Method(_STA, 0, Serialized) + { + If (And(PRTE, 0x80)) { + Return (STA_DISABLED) + } Else { + Return (STA_INVISIBLE) + } + } +} + +Device (LNKF) +{ + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 6) + + /* Disable method */ + Method(_DIS, 0, Serialized) + { + Store(0x80, PRTF) + } + + /* Possible Resource Settings for this Link */ + Name(_PRS, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) { 5, 6, 7, 10, 11, 12, 14, 15 } + }) + + /* Current Resource Settings for this link */ + Method(_CRS, 0, Serialized) + { + Name(RTLF, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) {} + }) + CreateWordField(RTLF, 1, IRQ0) + + /* Clear the WordField */ + Store(Zero, IRQ0) + + /* Set the bit from PRTF */ + ShiftLeft(1, And(PRTF, 0x0f), IRQ0) + + Return (RTLF) + } + + /* Set Resource Setting for this IRQ link */ + Method(_SRS, 1, Serialized) + { + CreateWordField(Arg0, 1, IRQ0) + + /* Which bit is set? */ + FindSetRightBit(IRQ0, Local0) + + Decrement(Local0) + Store(Local0, PRTF) + } + + /* Status */ + Method(_STA, 0, Serialized) + { + If (And(PRTF, 0x80)) { + Return (STA_DISABLED) + } Else { + Return (STA_INVISIBLE) + } + } +} + +Device (LNKG) +{ + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 7) + + /* Disable method */ + Method(_DIS, 0, Serialized) + { + Store(0x80, PRTG) + } + + /* Possible Resource Settings for this Link */ + Name(_PRS, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) { 5, 6, 7, 10, 11, 12, 14, 15 } + }) + + /* Current Resource Settings for this link */ + Method(_CRS, 0, Serialized) + { + Name(RTLG, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) {} + }) + CreateWordField(RTLG, 1, IRQ0) + + /* Clear the WordField */ + Store(Zero, IRQ0) + + /* Set the bit from PRTG */ + ShiftLeft(1, And(PRTG, 0x0f), IRQ0) + + Return (RTLG) + } + + /* Set Resource Setting for this IRQ link */ + Method(_SRS, 1, Serialized) + { + CreateWordField(Arg0, 1, IRQ0) + + /* Which bit is set? */ + FindSetRightBit(IRQ0, Local0) + + Decrement(Local0) + Store(Local0, PRTG) + } + + /* Status */ + Method(_STA, 0, Serialized) + { + If (And(PRTG, 0x80)) { + Return (STA_DISABLED) + } Else { + Return (STA_INVISIBLE) + } + } +} + +Device (LNKH) +{ + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 8) + + /* Disable method */ + Method(_DIS, 0, Serialized) + { + Store(0x80, PRTH) + } + + /* Possible Resource Settings for this Link */ + Name(_PRS, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) { 5, 6, 7, 10, 11, 12, 14, 15 } + }) + + /* Current Resource Settings for this link */ + Method(_CRS, 0, Serialized) + { + Name(RTLH, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) {} + }) + CreateWordField(RTLH, 1, IRQ0) + + /* Clear the WordField */ + Store(Zero, IRQ0) + + /* Set the bit from PRTH */ + ShiftLeft(1, And(PRTH, 0x0f), IRQ0) + + Return (RTLH) + } + + /* Set Resource Setting for this IRQ link */ + Method(_SRS, 1, Serialized) + { + CreateWordField(Arg0, 1, IRQ0) + + /* Which bit is set? */ + FindSetRightBit(IRQ0, Local0) + + Decrement(Local0) + Store(Local0, PRTH) + } + + /* Status */ + Method(_STA, 0, Serialized) + { + If (And(PRTH, 0x80)) { + Return (STA_DISABLED) + } Else { + Return (STA_INVISIBLE) + } + } +} diff --git a/arch/x86/include/asm/acpi/irqroute.asl b/arch/x86/include/asm/acpi/irqroute.asl new file mode 100644 index 0000000..0ed7efd --- /dev/null +++ b/arch/x86/include/asm/acpi/irqroute.asl @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com> + * + * Modified from coreboot src/soc/intel/baytrail/acpi/irqroute.asl + */ + +Name(\PICM, 0) + +/* + * The _PIC method is called by the OS to choose between interrupt + * routing via the i8259 interrupt controller or the APIC. + * + * _PIC is called with a parameter of 0 for i8259 configuration and + * with a parameter of 1 for Local APIC/IOAPIC configuration. + */ +Method(\_PIC, 1) +{ + /* Remember the OS' IRQ routing choice */ + Store(Arg0, PICM) +} + +/* PCI interrupt routing */ +Method(_PRT) { + If (PICM) { + Return (Package() { + #undef PIC_MODE + #include "irq_helper.h" + PCI_DEV_PIRQ_ROUTES + }) + } Else { + Return (Package() { + #define PIC_MODE + #include "irq_helper.h" + PCI_DEV_PIRQ_ROUTES + }) + } + +} + +/* PCIe downstream ports interrupt routing */ +PCIE_BRIDGE_IRQ_ROUTES +#undef PIC_MODE +#include "irq_helper.h" +PCIE_BRIDGE_IRQ_ROUTES diff --git a/arch/x86/include/asm/acpi/sleepstates.asl b/arch/x86/include/asm/acpi/sleepstates.asl new file mode 100644 index 0000000..32e16a2 --- /dev/null +++ b/arch/x86/include/asm/acpi/sleepstates.asl @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com> + * + * Modified from coreboot src/soc/intel/baytrail/acpi/sleepstates.asl + */ + +Name(\_S0, Package() {0x0, 0x0, 0x0, 0x0}) +#ifdef CONFIG_HAVE_ACPI_RESUME +Name(\_S3, Package() {0x5, 0x0, 0x0, 0x0}) +#endif +Name(\_S4, Package() {0x6, 0x0, 0x0, 0x0}) +Name(\_S5, Package() {0x7, 0x0, 0x0, 0x0}) diff --git a/arch/x86/include/asm/acpi/statdef.asl b/arch/x86/include/asm/acpi/statdef.asl new file mode 100644 index 0000000..6697bc4 --- /dev/null +++ b/arch/x86/include/asm/acpi/statdef.asl @@ -0,0 +1,81 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2008 Advanced Micro Devices, Inc. + * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com> + * + * Modified from coreboot src/arch/x86/acpi/statdef.asl + */ + +/* Status and notification definitions */ + +#define STA_MISSING 0x00 +#define STA_PRESENT 0x01 +#define STA_ENABLED 0x03 +#define STA_DISABLED 0x09 +#define STA_INVISIBLE 0x0b +#define STA_UNAVAILABLE 0x0d +#define STA_VISIBLE 0x0f + +/* SMBus status codes */ +#define SMB_OK 0x00 +#define SMB_UNKNOWN_FAIL 0x07 +#define SMB_DEV_ADDR_NAK 0x10 +#define SMB_DEVICE_ERROR 0x11 +#define SMB_DEV_CMD_DENIED 0x12 +#define SMB_UNKNOWN_ERR 0x13 +#define SMB_DEV_ACC_DENIED 0x17 +#define SMB_TIMEOUT 0x18 +#define SMB_HST_UNSUPP_PROTOCOL 0x19 +#define SMB_BUSY 0x1a +#define SMB_PKT_CHK_ERROR 0x1f + +/* Device Object Notification Values */ +#define NOTIFY_BUS_CHECK 0x00 +#define NOTIFY_DEVICE_CHECK 0x01 +#define NOTIFY_DEVICE_WAKE 0x02 +#define NOTIFY_EJECT_REQUEST 0x03 +#define NOTIFY_DEVICE_CHECK_JR 0x04 +#define NOTIFY_FREQUENCY_ERROR 0x05 +#define NOTIFY_BUS_MODE 0x06 +#define NOTIFY_POWER_FAULT 0x07 +#define NOTIFY_CAPABILITIES 0x08 +#define NOTIFY_PLD_CHECK 0x09 +#define NOTIFY_SLIT_UPDATE 0x0b +#define NOTIFY_SRA_UPDATE 0x0d + +/* Battery Device Notification Values */ +#define NOTIFY_BAT_STATUSCHG 0x80 +#define NOTIFY_BAT_INFOCHG 0x81 +#define NOTIFY_BAT_MAINTDATA 0x82 + +/* Power Source Object Notification Values */ +#define NOTIFY_PWR_STATUSCHG 0x80 +#define NOTIFY_PWR_INFOCHG 0x81 + +/* Thermal Zone Object Notification Values */ +#define NOTIFY_TZ_STATUSCHG 0x80 +#define NOTIFY_TZ_TRIPPTCHG 0x81 +#define NOTIFY_TZ_DEVLISTCHG 0x82 +#define NOTIFY_TZ_RELTBLCHG 0x83 + +/* Power Button Notification Values */ +#define NOTIFY_POWER_BUTTON 0x80 + +/* Sleep Button Notification Values */ +#define NOTIFY_SLEEP_BUTTON 0x80 + +/* Lid Notification Values */ +#define NOTIFY_LID_STATUSCHG 0x80 + +/* Processor Device Notification Values */ +#define NOTIFY_CPU_PPCCHG 0x80 +#define NOTIFY_CPU_CSTATECHG 0x81 +#define NOTIFY_CPU_THROTLCHG 0x82 + +/* User Presence Device Notification Values */ +#define NOTIFY_USR_PRESNCECHG 0x80 + +/* Ambient Light Sensor Notification Values */ +#define NOTIFY_ALS_ILLUMCHG 0x80 +#define NOTIFY_ALS_COLORTMPCHG 0x81 +#define NOTIFY_ALS_RESPCHG 0x82 |