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| author | raywu <raywu0301@gmail.com> | 2018-06-15 00:00:50 +0800 |
|---|---|---|
| committer | raywu <raywu0301@gmail.com> | 2018-06-15 00:00:50 +0800 |
| commit | b7c51c9cf4864df6aabb99a1ae843becd577237c (patch) | |
| tree | eebe9b0d0ca03062955223097e57da84dd618b9a /ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include | |
| download | zprj-b7c51c9cf4864df6aabb99a1ae843becd577237c.tar.xz | |
Diffstat (limited to 'ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include')
27 files changed, 75315 insertions, 0 deletions
diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/McAddress.h b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/McAddress.h new file mode 100644 index 0000000..ddd677b --- /dev/null +++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/McAddress.h @@ -0,0 +1,131 @@ +/** @file + The contents of this file has all the memory controller register addresses + and register bit fields for the MRC. + +@copyright + Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +**/ +#ifndef __McAddress_h__ +#define __McAddress_h__ + +#include "McGdxcbar.h" +#include "McIoCkeCtl.h" +#include "McIoClk.h" +#include "McIoCmd.h" +#include "McIoComp.h" +#include "McIoData.h" +#include "McMain.h" +#include "McScramble.h" +#include "Msa.h" +#include "Pci000.h" + +/// +/// The following is a copy of M_PCU_CR_SSKPD_PCU_STRUCT, modified to add in the +/// definition of the scratch pad bit fields. +/// +typedef union { + struct { + U64 OldWM0 : 4; ///< Bits 3:0 + U64 WM1 : 8; ///< Bits 11:4 + U64 WM2 : 8; ///< Bits 19:12 + U64 WM3 : 9; ///< Bits 28:20 + U64 : 3; ///< Bits 31:29 + U64 WM4 : 9; ///< Bits 40:32 + U64 : 15; ///< Bits 55:41 + U64 NewWM0 : 8; ///< Bits 63:56 + } Bits; + U64 Data; + U32 Data32[2]; + U16 Data16[4]; + U8 Data8[8]; +} M_PCU_CR_SSKPD_PCU_STRUCT; + +/// +/// Number of microseconds for level 0 old field (0.1us granularity). +/// 00h 0 us +/// 01h 0.1 us +/// Fh 1.5 us +/// +#define PCU_CR_SSKPD_PCU_OLD_WM0_OFF (0) +#define PCU_CR_SSKPD_PCU_OLD_WM0_WID (4) +#define PCU_CR_SSKPD_PCU_OLD_WM0_MSK (0xF) +#define PCU_CR_SSKPD_PCU_OLD_WM0_MAX (0xF) +#define PCU_CR_SSKPD_PCU_OLD_WM0_DEF (0xF) + +/// +/// Number of microseconds for level 0 new field (0.1us granularity). +/// 00h 0 us +/// 01h 0.1 us +/// FFh 25.5 us +/// +#define PCU_CR_SSKPD_PCU_NEW_WM0_OFF (56) +#define PCU_CR_SSKPD_PCU_NEW_WM0_WID (8) +#define PCU_CR_SSKPD_PCU_NEW_WM0_MSK (0xFF) +#define PCU_CR_SSKPD_PCU_NEW_WM0_MAX (0xFF) +#define PCU_CR_SSKPD_PCU_NEW_WM0_DEF (0x14) +/// +/// Number of microseconds for level 1 (0.5us granularity). +/// 00h 0 us +/// 01h 0.5 us +/// FFh 127.5 us +/// +#define PCU_CR_SSKPD_PCU_WM1_OFF (4) +#define PCU_CR_SSKPD_PCU_WM1_WID (8) +#define PCU_CR_SSKPD_PCU_WM1_MSK (0xFF) +#define PCU_CR_SSKPD_PCU_WM1_MAX (0xFF) +#define PCU_CR_SSKPD_PCU_WM1_DEF (4) + +/// +/// Number of microseconds for level 2 (0.5us granularity). +/// 00h 0 us +/// 01h 0.5 us +/// FFh 127.5 us +/// +#define PCU_CR_SSKPD_PCU_WM2_OFF (12) +#define PCU_CR_SSKPD_PCU_WM2_WID (8) +#define PCU_CR_SSKPD_PCU_WM2_MSK (0xFF) +#define PCU_CR_SSKPD_PCU_WM2_MAX (0xFF) +#define PCU_CR_SSKPD_PCU_WM2_DEF (36) + +/// +/// Number of microseconds for level 3 (0.5us granularity). +/// 00h 0 us +/// 01h 0.5 us +/// 01FFh 255.5 us +/// +#define PCU_CR_SSKPD_PCU_WM3_OFF (20) +#define PCU_CR_SSKPD_PCU_WM3_WID (9) +#define PCU_CR_SSKPD_PCU_WM3_MSK (0x1FF) +#define PCU_CR_SSKPD_PCU_WM3_MAX (0x1FF) +#define PCU_CR_SSKPD_PCU_WM3_DEF (90) + +/// +/// Number of microseconds for level 4 (0.5us granularity). +/// 00h 0 us +/// 01h 0.5 us +/// 01FFh 255.5 us +/// +#define PCU_CR_SSKPD_PCU_WM4_OFF (32) +#define PCU_CR_SSKPD_PCU_WM4_WID (9) +#define PCU_CR_SSKPD_PCU_WM4_MSK (0x1FF) +#define PCU_CR_SSKPD_PCU_WM4_MAX (0x1FF) +#define PCU_CR_SSKPD_PCU_WM4_DEF (160) + + +#define NCDECS_CR_GDXCBAR_NCU_MAX (0xFFFFF000) + +#endif // __McAddress_h__ diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcCommandTraining.h b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcCommandTraining.h new file mode 100644 index 0000000..c2b9b4a --- /dev/null +++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcCommandTraining.h @@ -0,0 +1,302 @@ +/** @file + Command training definitions. + +@copyright + Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved. + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement. + +**/ + +/// +/// Include files +/// +#ifndef _MrcCommandTraining_h_ +#define _MrcCommandTraining_h_ + +#include "MrcTypes.h" +#include "MrcApi.h" +#include "MrcCommon.h" +#include "MrcDdr3.h" +#include "MrcGlobal.h" +#include "MrcIoControl.h" +#include "MrcOem.h" +#include "MrcReadReceiveEnable.h" +#include "MrcReset.h" +#include "MrcTimingConfiguration.h" + +#define ECT_CLK_START (0) +#define ECT_CLK_STOP (128) + +#define ECT_CLK_STEP (2) + +#define ECT_CLK_LOOPS (ECT_CLK_STOP / ECT_CLK_STEP) + +#define ECT_DQS_START (-32) +#define ECT_DQS_STOP (32) +#define ECT_DQS_STEP (8) +#define ECT_MIN_WIDTH (16) + +/** +@brief + This function performs early command training. + Center CTL-CLK timing to allow subsequent steps to work + + @param[in] MrcData - Include all MRC global data. + + @retval MrcStatus - mrcSuccess if it succeeded +**/ +extern +MrcStatus +MrcEarlyCommandTraining ( + IN MrcParameters *const MrcData + ); + +/** +@brief + This function performs Late command training. + Center CMD/CTL-CLK timing using complex patterns. + + @param[in] MrcData - Include all MRC global data. + + @retval MrcStatus - If it's a success return mrcSuccess +**/ +extern +MrcStatus +MrcLateCommandTraining ( + IN MrcParameters *const MrcData + ); + +/** +@brief + Perform Command Voltage Centering. + + @param[in, out] MrcData - Include all MRC global data. + + @retval MrcStatus - if it succeded returns mrcSuccess +**/ +extern +MrcStatus +MrcCmdVoltageCentering ( + IN OUT MrcParameters *const MrcData + ); + +/** +@brief + Centers Command Timing around a MidPoint + + @param[in] MrcData - Include all MRC global data. + @param[in] Iteration - Determines which PI to shift + @param[in] Ranks - Valid Rank bit mask + @param[in] GroupMask - which LPDDR groups to work on for CMD/CLK/CKE; not used for DDR3 + @param[in] MidPoint - The MidPoint to center around (per channel) + + @retval Nothing +**/ +extern +void +CmdTimingCentering ( + IN MrcParameters *const MrcData, + IN U8 Iteration, + IN U8 Ranks, + IN U8 GroupMask, + IN U8 MidPoint[MAX_CHANNEL] + ); + +/** +@brief + Use a linear search to find the edges between Low and High + if WrapAround = 0: Look for largest passing region between low and high + if WrapAround = 1: Look for largest passing region, including wrapping from high to low + + @param[in, out] MrcData - Include all MRC global data. + @param[in] Iteration - Determines which PI to shift + @param[in] chBitMask - Valid Channel bit mask + @param[in] Ranks - Valid Rank bit mask + @param[in] GroupMask - which LPDDR groups to work on for CMD/CLK/CKE; not used for DDR3 + @param[in] Low - Low limit + @param[in] High - High limit + @param[in] WrapAllowed - Determines the search region + @param[in] VrefOffsets - Array of Vref offsets + @param[in] SkipPrint - Switch to enable or disable debug printing + @param[in] SkipVref - Skip changing CMD Vref offsets, only run test once at the current Vref. + + @retval MrcStatus - If it succeeds return mrcSuccess +**/ +extern +void +CmdLinearFindEdges ( + IN OUT MrcParameters *const MrcData, + IN U8 Iteration, + IN U8 chBitMask, + IN U8 Ranks, + IN U8 GroupMask, + IN S8 Low, + IN U8 High, + IN U8 WrapAllowed, + IN S8 *VrefOffsets, + IN BOOL SkipPrint, + IN BOOL SkipVref + ); + +/** +@brief + Use a binary search to find the edge between Low and High + High and Low track passing points + if CountUp: Low is a passing point and need to count up to find a failing point + if CountDn: High is a passing point and need to count dn to find a failing point + + @param[in] MrcData - Include all MRC global data. + @param[in] Iteration - Determines which PI to shift + @param[in] ChBitMask - Valid Channel bit mask + @param[in] Ranks - Valid Rank bit mask + @param[in] GroupMask - which LPDDR groups to work on for CMD/CLK/CKE; not used for DDR3 + @param[in, out] Low - Low limit + @param[in, out] High - High limit + @param[in] CountUp - The direction to search + @param[in] VrefOffsets - Array of Vref offsets + + @retval Nothing +**/ +extern +void +CmdBinaryFindEdge ( + IN MrcParameters *const MrcData, + IN U8 Iteration, + IN U8 ChBitMask, + IN U8 Ranks, + IN U8 GroupMask, + IN OUT U8 *Low, + IN OUT U8 *High, + IN U8 CountUp, + IN S8 *VrefOffsets + ); + +/** +@brief + Shift the CLK/CTL Timing + Shift the CMD Timing + + @param[in] MrcData - Include all MRC global data. + @param[in] Channel - Channel to shift + @param[in] Offset - Offset to shift by + @param[in] UpdateHost - Switch to update the host structure + + @retval Nothing +**/ +extern +void +ShiftChannelTiming ( + IN MrcParameters *const MrcData, + IN U8 Channel, + IN S32 Offset, + IN U8 UpdateHost + ); + +/** +@brief + This function updtes Command Mode register, tXP and Round trip latency + + @param[in, out] MrcData - Include all MRC global data. + @param[in] Channel - Channel to perform update to + @param[in] OldN - Old N Mode value + @param[in] NewN - New N mode value + + @retval Nothing +**/ +extern +void +UpdateCmdNTiming ( + IN OUT MrcParameters *const MrcData, + IN U8 Channel, + IN U8 OldN, + IN U8 NewN + ); + +#ifdef ULT_FLAG + +typedef struct _CADB_LINE { + U32 CaHigh; + U32 CaLow; + U32 ChipSelect; +} CADB_LINE; + +typedef enum { + CaTrainingMode41, ///< Enter CA training mode using MRW41 + CaTrainingMode48, ///< Enter CA training mode using MRW48 + CaTrainingMode42 ///< Exit CA training mode using MRW42 +} MrcCaTrainingMode; + +/** +@brief + Early CA / CS training for LPDDR. + Main flow: + 1. Put DRAMs in CA training mode using MRW41. + 2. Run CS vs. CLK training. + 3. Map DQ pins according to the board swizzling. + 4. Run CA vs. CLK training. + 5. Select optimal CA timings for each CA bus per rank + + @param[in] MrcData - The MRC global data. + + @retval mrcSuccess if succeeded +**/ +extern +MrcStatus +EarlyCommandTrainingLpddr ( + IN MrcParameters *const MrcData + ); + +/** +@brief + Early CS / CLK training for LPDDR. + Main flow: + 1. Setup CADB pattern for CS Training. + 2. Run CS vs. CLK training. + 3. Select optimal CS and CLK timings + + @param[in] MrcData - The MRC global data. + + @retval mrcSuccess if succeeded +**/ +extern +MrcStatus +EarlyChipSelectTraining ( + IN MrcParameters *const MrcData + ); + +/** +@brief + Sweep right and left from the current point to find the margins. + + @param[in, out] MrcData - Include all MRC global data. + @param[in] Iteration - Determines which PI to shift + @param[in] ChannelMask - Valid Channel bit mask + @param[in] RankMask - Valid Rank bit mask + @param[in] DebugPrint - Print debug messages or not + + @retval MrcStatus - If it succeeds return mrcSuccess +**/ +void +CmdLinearFindEdgesLpddr ( + IN OUT MrcParameters *const MrcData, + IN U8 Iteration, + IN U8 ChannelMask, + IN U8 RankMask, + IN BOOL DebugPrint + ); + +#endif // ULT_FLAG +#endif // _MrcCommandTraining_h_ diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcCommon.h b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcCommon.h new file mode 100644 index 0000000..718c066 --- /dev/null +++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcCommon.h @@ -0,0 +1,1836 @@ +/** @file + This file include all the MRC common data. + +@copyright + Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +**/ +#ifndef _MrcCommon_h_ +#define _MrcCommon_h_ + +#include "MrcTypes.h" +#include "MrcApi.h" +#include "MrcIoControl.h" +#include "McAddress.h" +#include "MrcDdr3.h" +#include "MrcReset.h" +#include "MrcOem.h" +#include "MrcOemPlatform.h" + + +/// +/// Convert rank to dimm number +/// +#ifndef RANK_TO_DIMM_NUMBER +#define RANK_TO_DIMM_NUMBER(Rank) (Rank / 2) +#endif + +/// +/// Convert rank to real rank number inside dimm +/// +#ifndef RANK_TO_RANK_NUMBER_IN_DIMM +#define RANK_TO_RANK_NUMBER_IN_DIMM(Rank) ((Rank % 2) + 1) +#endif + +/// +/// Convert rank and dimm to channel rank number +/// +#ifndef GET_RANK_NUMBER +#define GET_RANK_NUMBER(Dimm, Rank) ((Dimm * 2) + Rank) +#endif + +/// +/// Bit operation commands +/// +#ifndef MRC_MASK +#define MRC_MASK(offset, width) (((1 << width) - 1) << (offset)) +#endif + +#ifndef MRC_MASK_NOT +#define MRC_MASK_NOT(offset, width) (~(MRC_MASK (offset, width))) +#endif + +#ifndef MRC_CR_UPDATE +#define MRC_CR_UPDATE(Register, Offset, Width, Value) \ + (((Register) & MRC_MASK_NOT (Offset, Width)) | ((Value) << (Offset))) +#endif + +#ifndef MRC_CR_DUMP +#define MRC_CR_DUMP(Register, offset, Width)\ + (((Register) & (MRC_MASK(offset, Width))) >> offset) +#endif + +#define BER_TARGET 4 +#define BER_LOG_TARGET 7 ///< MRC_Log8(BER_TARGET) = 7 +#define BER_ERROR_MASK 0xFFFF00FF + +#define MRC_ASSERT(cond, DEBUG, ...) \ + if (!(cond)) { \ + MRC_DEBUG_MSG (DEBUG, MSG_LEVEL_ERROR, __VA_ARGS__); \ + MRC_DEADLOOP (); \ + } + +/// +/// Cache line size +/// +#define WDB_CACHE_LINE_SIZE (8) + +/// +/// CADB Entries +/// +#define MRC_NUM_CADB_ENTRIES (8) + +/// +/// Number of WDB Mux +/// +#define MRC_WDB_NUM_MUX_SEEDS (3) + +/// +/// Dimm Mode register selection +/// +typedef enum { + mrMR0 = 0, + mrMR1, + mrMR2, + mrMR3, + mrMR11 = 11 +} MrcModeRegister; + +typedef enum { + dDIMM0= 0, + dDIMM1 +} MrcDimmType; + +typedef enum { + cCHANNEL0 = 0, + cCHANNEL1 +} MrcChannelType; + +typedef enum { + rRank0 = 0, + rRank1, + rRank2, + rRank3 +} MrcRank; + +typedef enum { + ssOne = 0, + ssTwo, + ssThree, + ssFour +} TSubSequencesNumber; + +/// +/// Define ECC mode. +/// +typedef enum { + emNoEcc, + emEccIoActive, + emEccLogicActive, + emBothActive +} TEccModes; + +/// +/// Raw card list +/// +typedef enum { + rcA, + rcB, + rcC, + rcD, + rcE, + rcF, + rcG, + rcH, +} TRawCard; + +/// +/// Reut Addressing Parameters +/// +typedef enum { + MrcReutFieldRank, + MrcReutFieldBank, + MrcReutFieldRow, + MrcReutFieldCol, + MrcReutFieldMax ///< This must be the last entry in the enum. +} MrcReutField; + +typedef struct { + U16 Start[MrcReutFieldMax]; ///< (4, uint16) // Rank, Bank, Row, Col + U16 Stop[MrcReutFieldMax]; ///< (4, uint16) // Rank, Bank, Row, Col + U8 Order[MrcReutFieldMax]; ///< [4, uint8) // Rank, Bank, Row, Col + U32 IncRate[MrcReutFieldMax]; ///< (4, unit32) // Rank, Bank, Row, Col + U16 IncVal[MrcReutFieldMax]; ///< (4, unit16) // Rank, Bank, Row, Col +} MRC_REUTAddress; + +typedef struct { + U16 IncRate; ///< How quickly the WDB walks through cachelines (uint16) + U32 Start; ///< Starting pointer in WDB + U32 Stop; ///< Stopping pointer in WDB + U8 DQPat; ///< [0:BasicVA, 1:SegmentWDB, 2:CADB, 3:TurnAround, + ///< 4: LMNVa, 5: TurnAroundWR, 6: TurnAroundODT + ///< 7: CADBCol, 8: CADBRow] +} MRC_WDBPattern; + +typedef enum { + BasicVA = 0, ///< Use 2 LFSR VicAggressor pattern with rotation of 10 bits + SegmentWDB, ///< Use 2 LFSR VA pattern 10 bit rotation + 3 LFSR VA pattern 6 bit rotation + CADB, ///< Do CADB on command/address bus and LMN VA on DQ (power supply noise) + TurnAround, + LMNVa, ///< Use (LMN aggressor + LFSR Victim) with rotation of 10 bits + TurnAroundWR, ///< Run 8 tests, one for each subsequence with RankIncRate = 1/2/2/2/2/2/2/1 + TurnAroundODT, ///< Run 4 tests, one for each subsequence with RankIncRate = 1/2/1/2 + CADBCol, + CADBRow, + RdRdTA, ///< Run 2 tests, one with Trdrd=4 and one with Trdrd=5 + RdRdTA_All ///< Run 8 tests, Covering tRDRD_sr 4,5,6,7 and tRDRD_dr = Min,+1,+2,+3 +} MrcDqPat; + +typedef enum { + NSOE = 0, ///< Never Stop On Any Error + NTHSOE, ///< Stop on the Nth Any Lane Error + ABGSOE, ///< Stop on All Byte Groups Error + ALSOE ///< Stop on All Lanes Error +} TStopOnError; + +typedef enum { + MrcRegFileRank, ///< Used if ChangeMargin is being called within a Rank loop and the Parameters are Rank based. + MrcRegFileStart, ///< Used when changing parameters before the test. + MrcRegFileCurrent, ///< Used when changing parameters after the test. + MrcRegFileMax ///< This must be the last in the list +} MrcRegFile; + +/// +/// CADB commands +/// +#define MRS_CMD 0 +#define REF_CMD 1 +#define PRE_CMD 2 +#define ACT_CMD 3 +#define WR_CMD 4 +#define RD_CMD 5 +#define ZQ_CMD 6 +#define NOP_CMD 7 + +/// +/// REUT Init modes +/// +#define Idle_Mode 0 +#define REUT_Testing_Mode 1 +#define MRS_Mode 2 +#define NOP_Mode 3 ///< Normal Operation Mode + +/// +/// REUT CmdPattern +/// +#define PatWrRd 0 +#define PatWr 1 +#define PatRd 2 +#define PatRdWrTA 3 +#define PatWrRdTA 4 +#define PatODTTA 5 +#define DimmTest 6 +#define PatCADBCol 7 +#define PatCADBRow 8 + +/// +/// REUT Mux Control +/// +#define LMNMode 0 +#define BTBUFFER 1 +#define LFSRMode 2 + +/// +/// REUT Subsequence types +/// +#define BRd 0 +#define BWr 1 +#define BRdWr 2 +#define BWrRd 3 +#define ORd 4 +#define OWr 5 + +/// +/// WDB Patterns +/// +#define BASIC_VA_PATTERN_SPRED_8 0x01010101 + +/// +/// DQ time centering param: read or write +/// +/// +/// Margin params +/// + +/* + 1D Margin Types: + RcvEn: Shifts just RcvEn. Only side effect is it may eat into read dq-dqs for first bit of burst + RdT: Shifts read DQS timing, changing where DQ is sampled + WrT: Shifts write DQ timing, margining DQ-DQS timing + WrDqsT: Shifts write DQS timing, margining both DQ-DQS and DQS-CLK timing + RdV: Shifts read Vref voltage for DQ only + WrV: Shifts write Vref voltage for DQ only + WrLevel: Shifts write DQ and DQS timing, margining only DQS-CLK timing + WrTBit: Shifts write DQ per bit timing. + RdTBit: Shifts read DQ per bit timing. + RdVBit: Shifts read DQ per bit voltage. + + 2D Margin Types (Voltage, Time) + RdFan2: Margins both RdV and RdT at { (off, -2/3*off), (off, 2/3*off) } + WrFan2: Margins both WrV and WrT at { (off, -2/3*off), (off, 2/3*off) } + RdFan3: argins both RdV and RdT at { (off, -2/3*off), (5/4*off, 0), (off, 2/3*off) } + WrFan3: Margins both WrV and WrT at { (off, -2/3*off), (5/4*off, 0), (off, 2/3*off) } + + param = {0:RcvEn, 1:RdT, 2:WrT, 3: WrDqsT, 4:RdV, 5:WrV, 6:WrLevel, + 8:WrTBit, 9:RdTBit, 10:RdVBit, + 16:RdFan2, 17:WrFan2, 32:RdFan3, 32:WrFan3} +*/ + + typedef enum { + RcvEna = 0, + RdT, + WrT, + WrDqsT, + RdV, + WrV, + WrLevel, + WrTBox, + WrTBit, + RdTBit, + RdVBit, ///< 10 + RcvEnaX, + CmdT, + CmdV, + RdFan2 = 16, + WrFan2 = 17, + RdFan3 = 32, + WrFan3 = 33, + MarginTypeMax +} MRC_MarginTypes; + +typedef enum { + OptWrDS = 0, + OptRdOdt, + OptSComp, + OptTComp, + OptTxEq, + OptRxEq, + OptRxBias, + OptDimmOdt, + OptDimmOdtWr, + OptDimmRon, + OptDefault +} TOptParamOffset; + +typedef enum { + drrd2rd = 0, + ddrd2rd, + drwr2wr, + ddwr2wr, + drrd2wr, + ddrd2wr, + drwr2rd, + ddwr2rd, + rdodtd, + wrodtd, + mcodts, + mcodtd, + rtl, + srrd2rd, + srrd2wr +} TOptParamTAT; + +/// +/// Self refresh idle timer value +/// +#define SELF_REFRESH_IDLE_COUNT (0x200) + +#define RXF_SELECT_RC_100 (6) +#define RXF_SELECT_RC_133 (4) +#define RXF_SELECT_MIN (0) +#define RXF_SELECT_MAX (4) +#define RXF_SELECT_MAX_ULT (2) + +#ifdef MRC_DEBUG_PRINT +extern const char CcdString[]; +#endif + +/// +/// MRC common functions +/// + +/** + Return the rank mask in channel if rank exist exist. + + @param[in] MrcData - Pointer to MRC global data. + @param[in] Channel - Channel to work on. + @param[in] Rank - Rank to check. + + @retval Bit mask of Rank requested if the Rank exists in the system. +**/ +extern +U8 +MrcRankInChannelExist ( + IN MrcParameters *const MrcData, + IN const U8 Rank, + IN const U8 Channel + ); + +/** + Return the number of ranks in specific dimm. + + @param[in] MrcData - Pointer to MRC global data. + @param[in] Channel - Channel to work on. + @param[in] Dimm - Dimm in channel to return. + + @retval The number of ranks in the dimm. +**/ +extern +U8 +MrcGetRankInDimm ( + IN MrcParameters *const MrcData, + IN const U8 Dimm, + IN const U8 Channel + ); + +/** + Returns whether Channel is or is not present. + + @param[in] Outputs - Pointer to MRC global Output data. + @param[in] Channel - Channel to test. + + @retval TRUE - if there is at least one enabled DIMM in the channel. + @retval FALSE - if there are no enabled DIMMs in the channel. +**/ +extern +BOOL +MrcChannelExist ( + IN const MrcOutput *const Outputs, + IN const U8 Channel + ); + +/** + This function disable channel parameters. + After this function the MRC don't use with the channel. + + @param[in] MrcData - Include all MRC global data. + @param[in] ChannelToDisable - Channel to disable. + @param[in] SkipDimmCapacity - Switch to skip setting the DimmCapacity to 0 for the dimms in the channel disabled. + + @retval Nothing +**/ +extern +void +MrcChannelDisable ( + IN MrcParameters *const MrcData, + IN const U8 ChannelToDisable, + IN const U8 SkipDimmCapacity + ); + +/** + Convert the given frequency and reference clock to a clock ratio. + + @param[in] MrcData - Pointer to MRC global data. + @param[in] Frequency - The memory frequency. + @param[in] RefClk - The memory reference clock. + @param[in] BClk - The base system reference clock. + + @retval Returns the memory clock ratio. +**/ +extern +MrcClockRatio +MrcFrequencyToRatio ( + IN MrcParameters *const MrcData, + IN const MrcFrequency Frequency, + IN const MrcRefClkSelect RefClk, + IN const MrcBClkRef BClk + ); + +/** + @brief + Convert the given ratio and reference clocks to a memory frequency. + + @param[in] MrcData - Pointer to MRC global data. + @param[in] Ratio - The memory ratio. + @param[in] RefClk - The memory reference clock. + @param[in] BClk - The base system reference clock. + + @retval Returns the memory frequency. +**/ +extern +MrcFrequency +MrcRatioToFrequency ( + IN MrcParameters *const MrcData, + IN const MrcClockRatio Ratio, + IN const MrcRefClkSelect RefClk, + IN const MrcBClkRef BClk + ); + +/** + Convert the given ratio and reference clocks to a memory clock. + + @param[in] Ratio - The memory ratio. + @param[in] RefClk - The memory reference clock. + @param[in] BClk - The base system reference clock. + + @retval Returns the memory clock in femtoseconds. +**/ +extern +U32 +MrcRatioToClock ( + IN const MrcClockRatio Ratio, + IN const MrcRefClkSelect RefClk, + IN const MrcBClkRef BClk +); + +/** + This function return the DIMM number according to the rank number. + + @param[in] Rank - The requested rank. + + @retval The DIMM number. +**/ +extern +U8 +MrcGetDimmFromRank ( + IN const U8 Rank + ); + +/** + This function sets the memory frequency. + + @param[in] MrcData - Include all MRC global data. + + @retval mrcSuccess on success, mrcFrequencyError on error. +**/ +extern +MrcStatus +McFrequencySet ( + IN MrcParameters * const MrcData + ); + +/** + Returns the extrapolated margin to a fixed # of errors (logT) + vrefpass is 10x the first passing margin (with no errors) (10x used for int math) + Errors at vrefpass/10+1 = log1 + Errors at vrefpass/10+2 = logT + + @param[in] vrefpass - 10x the first pass margin (w/no errors) (10x used for int match) + @param[in] errLog_1 - Errors at vrefpass/10+1 + @param[in] errLog_2 - Errors at vrefpass/10+2 + @param[in] errLog_Target - Error target determines extrapolation vs interpolation + @param[in, out] *berStats - Used to track interpolation vs extrapolation or if the slope is non-monotonic. + NOTE: target would be Interpolation only + + @retval Interpolated/Extrapolated vref with the scale increased by 10. +**/ +extern +U32 +interpolateVref ( + IN U32 vrefpass, + IN U32 errLog_1, + IN U32 errLog_2, + IN U32 errLog_Target, + IN OUT U32 *berStats + ); + +/** + This function swaps a subfield, within a 32 bit integer value with the specified value. + + @param[in] CurrentValue - 32 bit input value. + @param[in] NewValue - 32 bit New value. + @param[in] Start - Subfield start bit. + @param[in] Length - Subfield length in bits/ + + @retval The updated 32 bit value. +**/ +extern +U32 +MrcBitSwap ( + IN U32 CurrentValue, + IN const U32 NewValue, + IN const U8 Start, + IN const U8 Length + ); + +/** + This function returns the maximim Rx margin for a given Channel, Rank(s), and byte. + + @param[in] MrcData - Pointer to MRC global data. + @param[in] Channel - Channel to calculate max Rx margin. + @param[in] RankRx - Rank index. 0xFF causes all ranks to be considered. + @param[in] byte - Byte to check. + @param[in] sign - Sign of the margins (0 - negative/min, 1 - positive/max). + @param[in] MaxMargin - Current max margin value. + + @retval The max Rx margin, either MaxMargin or value from stored margins. +**/ +extern +U8 +MrcCalcMaxRxMargin ( + IN MrcParameters *const MrcData, + IN const U8 Channel, + IN const U8 RankRx, + IN const U8 byte, + IN const U8 sign, + IN U8 MaxMargin + ); + +/** + This function determines if a bit lane[0-7] has seen a pass and a fail in each byte for all channels populated. + + @param[in] MrcData - Pointer to MRC global data. + @param[in] chBitmask - Bit mask of channels to consider. + @param[in] OnePass - Array of Bit masks marking DQ lanes has had a passing value. + @param[in] OneFail - Array of Bit masks marking DQ lanes has had a failing value. + + @retval The AND result of each Channel/byte for OnePass and OneFail. +**/ +extern +U8 +MrcAndBytes ( + IN MrcParameters *const MrcData, + IN const U8 chBitmask, + IN U8 OnePass[MAX_CHANNEL][MAX_SDRAM_IN_DIMM], + IN U8 OneFail[MAX_CHANNEL][MAX_SDRAM_IN_DIMM] + ); + +/** + This function Finds the margin for all channels/all bits. The margin sweep is a parameterized + Assume REUT test has already been fully setup to run + This will unscale the results such that future tests start at the correct point + Uses ChangeMargin function to handle a variety cases (Timing, Voltage, Fan, etc.) + + @param[in] MrcData - Include all MRC global data. + @param[in] chBitMask - Channel BIT mask for Channel(s) to work on + @param[in] Rank - Rank to work on + @param[in,out] marginbit - used as the return data ( real margin measurement, no 10x) + marginbit[ch,byte,bit,sign] = abs(Margin) + Note: If param == RdTBit/RdVBit/WrVBit, marginbit is also the starting point + @param[in,out] marginbyte - provides the starting point on a per byte basis (still 10x) + @param[in] param - defines the margin type + @param[in] mode - allows for different types of modes for margining + {Bit0: PhLock (keep all bytes within in ch in phase), + Bit1: Ch2Ch Data out of phase (LFSR seed) + Bits 15:2: Reserved} + @param[in] MaxMargin - Default Maximum margin + + @retval mrcSuccess if successful, otherwise it returns an error status. +**/ +extern +MrcStatus +MrcGetMarginBit ( + IN MrcParameters *const MrcData, + IN U8 chBitMask, + IN U8 Rank, + IN OUT U32 marginbit[MAX_CHANNEL][MAX_SDRAM_IN_DIMM][MAX_BITS][MAX_EDGES], + IN OUT U32 marginbyte[MAX_CHANNEL][MAX_SDRAM_IN_DIMM][MAX_EDGES], + IN U8 param, + IN U16 mode, + IN U8 MaxMargin + ); + +/** + Assume REUT test has already been fully setup to run + Finds the margin for all channels/all bytes + The margin sweep is parameterized + Uses ChangeMargin function to handle a variety of cases (Timing, Voltage, Fan, etc.) + mode allows for different types of modes for margining: + mode is {Bit0: PhLock (keep all bytes within in ch in phase), + Bit1: Ch2Ch Data out of phase (LFSR seed), Bit 15:2: Reserved} + marginByte is used as the starting point for the search (10x the actual margin) + marginch returns the results (10x the actual margin) + Interior: Search inside marginch limits, enabling multiple calls with different setups + To reduce repeatibility noise, the returned margins is actually a BER extrapolation + + @param[in] MrcData - The global MrcData + @param[in,out] marginByte - Data structure with the latest margin results + @param[in] chBitmask - Bit mask of present channels + @param[in] Rank - Rank to change margins for + @param[in] RankRx - Ranks for Rx margin + @param[in] param - parameter to get margins for + @param[in] mode - allows for different types of modes for margining: + @param[in] BMap - Byte mapping to configure error counter control register + @param[in] EnBER - Enable BER extrapolation calculations + @param[in] MaxMargin - Max Margin allowed for the parameter + @param[in] Interior - Search inside marginch limits, enabling multiple calls with different setups + @param[in,out] BERStats - Bit Error Rate Statistics. + + @retval mrcSuccess if successful, otherwise returns an error status. +**/ +extern +MrcStatus +MrcGetBERMarginByte ( + IN MrcParameters * const MrcData, + IN OUT U32 marginByte[MAX_RESULT_TYPE][MAX_RANK_IN_CHANNEL][MAX_CHANNEL][MAX_SDRAM_IN_DIMM][MAX_EDGES], + IN U8 chBitmask, + IN U8 Rank, + IN U8 RankRx, + IN U8 param, + IN U16 mode, + IN U8 *BMap, + IN U8 EnBER, + IN U8 MaxMargin, + IN U8 Interior, + IN OUT U32 *BERStats + ); + +/** + Assume REUT test has already been fully setup to run + Finds the margin for all channels/all bytes + The margin sweep is parameterized + Uses ChangeMargin function to handle a variety of cases (Timing, Voltage, Fan, etc.) + mode allows for different types of modes for margining: + mode is {Bit0: PhLock (keep all bytes within in ch in phase), + Bit1: Ch2Ch Data out of phase (LFSR seed), Bit 15:2: Reserved} + marginCh is used as the starting point for the search (10x the actual margin) + marginch returns the results (10x the actual margin) + Interior: Search inside marginch limits, enabling multiple calls with different setups + To reduce repeatibility noise, the returned margins is actually a BER extrapolation + + @param[in] MrcData - The global MrcData + @param[in,out] marginCh - Data structure with the latest margin results + @param[in] chBitmask - Bit mask of present channels + @param[in] RankRx - Ranks for Rx margin + @param[in] Rank - Rank to change margins for + @param[in] param - parameter to get margins for + @param[in] mode - allows for different types of modes for margining: + @param[in] EnBER - Enable BER extrapolation calculations + @param[in] MaxMargin - Max Margin allowed for the parameter + @param[in] Interior - Search inside marginch limits, enabling multiple calls with different setups + @param[in,out] BERStats - Bit Error Rate Statistics. + + @retval mrcSuccess if successful, otherwise returns an error status. +**/ +extern +MrcStatus +MrcGetBERMarginCh ( + IN MrcParameters *MrcData, + IN U32 marginCh[MAX_RESULT_TYPE][MAX_RANK_IN_CHANNEL][MAX_CHANNEL][MAX_SDRAM_IN_DIMM][MAX_EDGES], + IN OUT U8 chBitmask, + IN U8 RankRx, + IN U8 Rank, + IN U8 param, + IN U16 mode, + IN U8 EnBER, + IN U8 MaxMargin, + IN U8 Interior, + IN OUT U32 *BERStats + ); + +/** + This function shifts a 32 bit int either positive or negative + + @param[in] Value - Input value to be shifted + @param[in] ShiftAmount - Number of bits places to be shifted. + + @retval 0 if ShiftAmount exceeds +/- 31. Otherwise the updated 32 bit value. +**/ +extern +U32 +MrcBitShift ( + IN const U32 Value, + IN const S8 ShiftAmount + ); + +/** + This function Sign extends OldMSB to NewMSB Bits (Eg: Bit 6 to Bit 7) + + @param[in] CurrentValue - Input value to be shifted + @param[in] OldMSB - The original most significant Bit + @param[in] NewMSB - The new most significant bit. + + @retval The updated 8 bit value. +**/ +extern +U8 +MrcSE ( + IN U8 CurrentValue, + IN const U8 OldMSB, + IN const U8 NewMSB + ); + +/** + This function calculates the Log base 2 of the value to a maximum of Bits + + @param[in] Value - Input value + + @retval Returns the log base 2 of input value +**/ +extern +U8 +MrcLog2 ( + IN const U32 Value + ); + +/** + ***** Has Buffer Overflow for 68-71, 544-575, 4352-4607, ... **** + This function calculates the Log base 8 of the Input parameter using integers + + @param[in] Value - Input value + + @retval Returns 10x the log base 8 of input Value +**/ +extern +U32 +MrcLog8 ( + IN U32 Value + ); + +/** + This function Sorts Arr from largest to smallest + + @param[in,out] Arr - Array to be sorted + @param[in] Channel - Channel to sort. + @param[in] lenArr - Length of the array + + @retval Nothing +**/ +extern +void +MrcBsortPerChannel ( + IN OUT U32 Arr[MAX_CHANNEL][4], + IN const U8 Channel, + IN const U8 lenArr + ); + +/** + This function Sorts Arr from largest to smallest + + @param[in,out] Arr - Array to be sort + @param[in] lenArr - Lenght of the array + + @retval Nothing +**/ +extern +void +MrcBsort ( + IN OUT U32 *const Arr, + IN const U8 lenArr + ); + +/** + This function calculates the Natural Log of the Input parameter using integers + + @param[in] Input - 100 times a number to get the Natural log from. + Max Input Number is 40,000 (without 100x) + + @retval 100 times the actual result. Accurate within +/- 2 +**/ +extern +U32 +MrcNaturalLog ( + IN U32 Input + ); + +/** + This function calculates the number of bits set to 1 in a 32-bit value. + + @param[in] Input - The value to work on. + + @retval The number of bits set to 1 in Input. +**/ +extern +U8 +MrcCountBitsEqOne ( + IN U32 Input + ); + +/** + This function calculates e to the power of of the Input parameter using integers. + + @param[in] Input - 100 times a number to elevate e to. + + @retval 100 times the actual result. Accurate within +/- 2. +**/ +extern +U32 +Mrceexp ( + IN U32 Input + ); + +/** + This function writes a 32 bit register. + + @param[in] MrcData - Include all MRC global data. + @param[in] Offset - Offset of register from MchBar Base Address. + @param[in] Value - Value to write. + + @retval Nothing +**/ +extern +void +MrcWriteCrMulticast ( + IN MrcParameters *const MrcData, + IN const U32 Offset, + IN const U32 Value + ); + +/** + This function writes a 64 bit register. + + @param[in] MrcData - Include all MRC global data. + @param[in] Offset - Offset of register from MchBar Base Address. + @param[in] Value - Value to write. + + @retval Nothing +**/ +extern +void +MrcWriteCR64 ( + IN MrcParameters *const MrcData, + IN const U32 Offset, + IN const U64 Value + ); + +/** + This function writes a 32 bit register. + + @param[in] MrcData - Include all MRC global data. + @param[in] Offset - Offset of register from MchBar Base Address. + @param[in] Value - Value to write. + + @retval Nothing +**/ +extern +void +MrcWriteCR ( + IN MrcParameters *const MrcData, + IN const U32 Offset, + IN const U32 Value + ); + +/** + This function writes a 8 bit register. + + @param[in] MrcData - Include all MRC global data. + @param[in] Offset - Offset of register from MchBar Base Address. + @param[in] Value - The value to write. + + @retval Nothing +**/ +extern +void +MrcWriteCR8 ( + IN MrcParameters*const MrcData, + IN const U32 Offset, + IN const U8 Value + ); + +/** + This function reads a 64 bit register. + + @param[in] MrcData - Include all MRC global data. + @param[in] Offset - Offset of register from MchBar Base Address. + + @retval Value read from the register. +**/ +extern +U64 +MrcReadCR64 ( + IN MrcParameters *const MrcData, + IN const U32 Offset + ); + +/** + This function reads a 32 bit register. + + @param[in] MrcData - Include all MRC global data. + @param[in] Offset - Offset of register from MchBar Base Address. + + @retval Value read from the register +**/ +extern +U32 +MrcReadCR ( + IN MrcParameters *const MrcData, + IN const U32 Offset + ); + +/** + This function blocks the CPU for the duration specified in HPET Delay time. + + @param[in] MrcData - Include all MRC global data. + @param[in] DelayHPET - time to wait in 69.841279ns + + @retval Nothing +**/ +extern +void +MrcWait ( + IN MrcParameters *const MrcData, + IN U32 DelayHPET + ); + +/** + This function forces an RCOMP. + + @param[in] MrcData - Include all MRC global data. + + @retval Nothing +**/ +extern +void +ForceRcomp ( + IN MrcParameters * const MrcData + ); + +/** + This function sets the self refresh idle timer and enables it. + + @param[in] MrcData - Include all MRC global data. + + @retval Nothing +**/ +extern +void +EnterSR ( + IN MrcParameters * const MrcData + ); + +/** + This function sets the self refresh idle timer and disables it. + + @param[in] MrcData - Include all MRC global data. + + @retval Nothing +**/ +extern +void +ExitSR( + IN MrcParameters * const MrcData + ); + +/** + This function programs the WDB. + + @param[in] MrcData - Include all MRC global data. + + @retval Nothing +**/ +extern +void +SetupWDB( + IN MrcParameters * const MrcData + ); + +/* + This function will program all present channels with the 3 seeds passed in. + + @param[in] MrcData - Global MRC data structure + @param[in] seeds - Array of 3 seeds programmed into PAT_WDB_CL_MUX_PB_RD/WR + + @retval - Nothing +*/ +extern +void +MrcProgramLFSR ( + IN MrcParameters *const MrcData, + IN U32 const seeds[MRC_WDB_NUM_MUX_SEEDS] + ); + +/** + This function Write 1 cacheline worth of data to the WDB + + @param[in] MrcData - Include all MRC global data. + @param[in] Patterns - Array of bytes. Each bytes represents 8 chunks of the cachelines for 1 lane. + Each entry in Patterns represents a different cacheline for a different lane. + @param[in] PMask - Array of len Spread uint8. Maps the patterns to the actual DQ lanes. + DQ[0] = Patterns[PMask[0]], ... DQ[Spread-1] = Patterns[PMask[Spread-1]] + DQ[Spread] = DQ[0], ... DQ[2*Spread-1] = DQ[Spread-1] + @param[in] Start - Starting entry in the WDB. + + @retval Nothing +**/ +extern +void +WriteWDBFixedPattern ( + IN MrcParameters *const MrcData, + IN U8 *const Patterns, + IN U8 *const PMask, + IN const U8 Spread, + IN const U16 Start + ); + +/** + This rotine performs the following steps: + Step 0: Iterate through all VicRots + Step 1: Create a compressed vector for a given 32 byte cacheline + Each byte has a value of LFSR0=AA/LFSR1=CC/LFSR2=F0 + Step 2: Expand compressed vector into chunks and 32 bit segments + + @param[in] MrcData - Include all MRC global data. + @param[in] vmask - 32 bit victim mask. 1 indicates this bit should use LFSR0 + @param[in] amask - 32 bit aggressor mask. 0/1 indicates this bit should use LFSR1/2 + @param[in] VicRot - Number of times to circular rotate vmask/amask + @param[in] Start - Starting entry in the WDB + + @retval Nothing +**/ +extern +void +WriteWDBVAPattern ( + IN MrcParameters *const MrcData, + IN U32 amask, + IN U32 vmask, + IN const U8 VicRot, + IN const U16 Start + ); + +/** + Write VA pattern in CADB + Use basic VA pattern for CADB with 2 LFSRs. Rotation is manual + Bit Order is [CKE[3:0], ODT[3:0], CMD[2:0], CS[3:0], BA[2:0], MA[15:0]] + [59:56] [51:48] [42:40] [35:32] [26:24] [15:0] + + NOTE: CKE, ODT and CS are not used in functional mode and are ignored + + @param[in] MrcData - Include all MRC global data. + @param[in] Channel - Channel to setup. + @param[in] VicSpread - Separation of the Victim Bit. + @param[in] VicBit - The Bit to be the Victim. + @param[in] LMNEn - To enable LMN counter + + @retval Nothing +**/ +extern +void +SetupCADB ( + IN MrcParameters *const MrcData, + IN const U8 Channel, + IN const U8 VicSpread, + IN const U8 VicBit, + IN const U8 LMNEn + ); + +/** + Program the subsequence type field in a given MCDFXS_CR_REUT_CHx_SUBSEQ_CTL_MCMAIN_x_STRUCT register + + @param[in] MrcData - MRC global data + @param[in, out] SubSeqCtl - Address of the MCDFXS_CR_REUT_CHx_SUBSEQ_CTL_MCMAIN_x_STRUCT register + @param[in] Type - The subsequence type to program + + @retval Nothing. +**/ +void +SetSubsequenceType ( + IN MrcParameters *const MrcData, + IN OUT U32 *SubSeqCtl, + IN U32 Type + ); + +/* + This function handles writing to the REUT Addressing sequence for IO Tests. + To not write a certain parameter, pass a NULL pointer to the function. + + @param[in] MrcData - MRC global data structure. + @param[in] Channel - Specifies the channel to program. + @param[in] StartAddr - Start value for Rank/Bank/Row/Col. + @param[in] StopAddr - Stop value for Rank/Bank/Row/Col. + @param[in] FieldOrder - Relative order for carry propagates of Rank/Bank/Row/Col. + @param[in] IncRate - The number of writes to Rank/Bank/Row/Col before updating the address. + Note: The function will handle linear vs exponential and a value of 0 specifies a rate of 1. + @param[in] IncValue - The amount to increase Rank/Bank/Row/Col address. + @param[in] WrapTriggerEn - Enables wrap trigger for Rank/Bank/Row/Col to enable stopping on subsequence and sequence. + @param[in] WrapCarryEn - Enables carry propagation on wrap to the next higest order field + @param[in] AddrInvertEn - Enables inverting the Rank/Bank/Row/Col addresses based on AddrInvertRate. + @param[in] AddrIvertRate - Exponential rate of address inversion. Only updated if AddrInvertEn != NULL. + @param[in] EnableDebug - Enables/Disables debug printing. + + @retval Nothing +*/ +extern +void +MrcProgramSequenceAddress ( + IN MrcParameters *const MrcData, + IN const U8 Channel, + IN const U16 StartAddr[MrcReutFieldMax], + IN const U16 StopAddr[MrcReutFieldMax], + IN const U8 FieldOrder[MrcReutFieldMax], + IN const U32 IncRate[MrcReutFieldMax], + IN const U16 IncValue[MrcReutFieldMax], + IN const U8 WrapTriggerEn[MrcReutFieldMax], + IN const U8 WrapCarryEn[MrcReutFieldMax], + IN const U8 AddrInvertEn[MrcReutFieldMax], + IN const U8 AddrInvertRate, + IN const BOOL EnableDebug + ); + +/** + Programs all the key registers to define a CPCG test + + @param[in] MrcData - Include all MRC global data. + @param[in] WDBPattern - Structure that stores start, Stop, IncRate and Dqpat for pattern. + @param[in] ChbitMask - Channel Bit mak for which test should be setup for. + @param[in] CmdPat - [0: PatWrRd (Standard Write/Read Loopback), + 1: PatWr (Write Only), + 2: PatRd (Read Only), + 3: PatRdWrTA (ReadWrite Turnarounds), + 4: PatWrRdTA (WriteRead Turnarounds), + 5: PatODTTA (ODT Turnaround] + @param[in] NumCL - Number of Cache lines + @param[in] LC - Loop Count exponent + @param[in] REUTAddress - Structure that stores start, stop and increment details for address + @param[in] SOE - [0: Never Stop, 1: Stop on Any Lane, 2: Stop on All Byte, 3: Stop on All Lane] + @param[in] WDBPattern - Structure that stores start, Stop, IncRate and Dqpat for pattern. + @param[in] EnCADB - Enable test to write random deselect packages on bus to create xtalk/isi + @param[in] EnCKE - Enable CKE power down by adding 64 + @param[in] SubSeqWait - # of Dclks to stall at the end of a sub-sequence + + @retval Nothing +**/ +extern +void +SetupIOTest ( + IN MrcParameters *const MrcData, + IN const U8 ChbitMask, + IN const U8 CmdPat, + IN const U16 NumCL, + IN const U8 LC, + IN const MRC_REUTAddress *const REUTAddress, + IN const U8 SOE, + IN MRC_WDBPattern *const WDBPattern, + IN const U8 EnCADB, + IN const U8 EnCKE, + IN U16 SubSeqWait + ); + +/** + This function sets up a test with CADB for the given channel mask. + + @param[in,out] MrcData - Pointer to MRC global data. + @param[in] ChbitMask - Bit masks of channels to enable for the test. + @param[in] LC - Exponential umber of loops to run the test. + @param[in] SOE - Error handling switch for test. + @param[in] EnCADB - Switch to enable CADB + @param[in] EnCKE - Switch to enable CKE. + + @retval Nothing +**/ +extern +void +SetupIOTestCADB ( + IN OUT MrcParameters *const MrcData, + IN const U8 ChbitMask, + IN const U8 LC, + IN const U8 SOE, + IN const U8 EnCADB, + IN const U8 EnCKE + ); + +/** + This function sets up a basic victim-aggressor test for the given channel mask. + + @param[in,out] MrcData - Pointer to MRC global data. + @param[in] ChbitMask - Bit masks of channels to enable for the test. + @param[in] LC - Exponential umber of loops to run the test. + @param[in] SOE - Error handling switch for test. + @param[in] EnCADB - Switch to enable CADB + @param[in] EnCKE - Switch to enable CKE. + @param[in] Spread - Stopping point of the pattern. + + @retval Nothing +**/ +extern +void +SetupIOTestBasicVA ( + IN OUT MrcParameters *const MrcData, + IN const U8 ChbitMask, + IN const U8 LC, + IN const U8 SOE, + IN const U8 EnCADB, + IN const U8 EnCKE, + IN const U32 Spread + ); + +/** + This function sets up a DQ test for the given channel mask. + + @param[in,out] MrcData - Pointer to MRC global data. + @param[in] ChbitMask - Bit masks of channels to enable for the test. + @param[in] LC - Exponential umber of loops to run the test. + @param[in] SOE - Error handling switch for test. + @param[in] EnCADB - Switch to enable CADB + @param[in] EnCKE - Switch to enable CKE. + + @retval Nothing +**/ +extern +void +SetupIOTestDQ ( + IN OUT MrcParameters *const MrcData, + IN const U8 ChbitMask, + IN const U8 LC, + IN const U8 SOE, + IN const U8 EnCADB, + IN const U8 EnCKE + ); + +/** + This function sets up a test with CADB for the given channel mask. + + @param[in,out] MrcData - Pointer to MRC global data. + @param[in] ChbitMask - Bit masks of channels to enable for the test. + @param[in] LC - Exponential umber of loops to run the test. + @param[in] SOE - Error handling switch for test. + @param[in] EnCADB - Switch to enable CADB + @param[in] EnCKE - Switch to enable CKE. + + @retval Nothing +**/ +extern +void +SetupIOTestC2C ( + IN OUT MrcParameters *const MrcData, + IN const U8 ChbitMask, + IN const U8 LC, + IN const U8 SOE, + IN const U8 EnCADB, + IN const U8 EnCKE + ); + +/** + This function sets up a MPR test for the given channel mask. + + @param[in,out] MrcData - Pointer to MRC global data. + @param[in] ChbitMask - Bit masks of channels to enable for the test. + @param[in] LC - Exponential umber of loops to run the test. + @param[in] SOE - Error handling switch for test. + @param[in] EnCADB - Switch to enable CADB + @param[in] EnCKE - Switch to enable CKE. + + @retval Nothing +**/ +extern +void +SetupIOTestMPR ( + IN OUT MrcParameters *const MrcData, + IN const U8 ChbitMask, + IN const U8 LC, + IN const U8 SOE, + IN const U8 EnCADB, + IN const U8 EnCKE + ); + +/** + Runs one or more REUT tests (based on TestType) + + @param[in] MrcData - Include all MRC global data. + @param[in] ChbitMask - Channel Bit mask for which test should be setup for. + @param[in] DQPat - [0: BasicVA + 1: SegmentWDB + 2: CADB + 3: TurnAround + 4: LMNVa + 5: TurnAroundWR + 6: TurnAroundODT + 7: RdRdTA] + @param[in] SeqLCs - An array of one or more loopcounts. + @param[in] ClearErrors - Decision to clear or not errors. + @param[in] Mode - Allows for different types of modes for margining + {Bit0: PhLock (keep all bytes within in ch in phase), + Bit1: Ch2Ch Data out of phase (LFSR seed) + Bits 15:2: Reserved} + + @retval Returns ch errors +**/ +extern +U8 +RunIOTest ( + IN MrcParameters *const MrcData, + IN const U8 ChbitMask, + IN const U8 DQPat, + IN const U8 *const SeqLCs, + IN const U8 ClearErrors, + IN const U16 Mode + ); + +/** + Programs REUT to run on the selected physical ranks. + + @param[in] MrcData - Pointer to MRC global data. + @param[in] ch - Channel to enable. + @param[in] RankBitMask - Bit mask of ranks to enable. + @param[in] RankFeatureEnable - RankFeatureEnable is a bit mask that can enable CKE, Refresh or ZQ + RankFeatureEnable[0] enables Refresh on all non-selected ranks + RankFeatureEnable[1] enables Refresh on all ranks + RankFeatureEnable[2] enables ZQ on all non-selected ranks + RankFeatureEnable[3] enables ZQ on all ranks + RankFeatureEnable[4] enables CKE on all non-selected ranks + RankFeatureEnable[5] enables CKE on all ranks + + @retval Bit mask of channel enabled if rank in the channel exists. +**/ +extern +U8 +SelectReutRanks ( + IN MrcParameters *const MrcData, + IN const U8 ch, + IN U8 RankBitMask, + IN const U8 RankFeatureEnable + ); + +/** + This routine updates RXTRAINRANK register's specific fields defined by the subfield + subfield values: + 0 - Update RcvEn - leave other parameter the same + 1 - Update RxDqsP - leave other parameter the same + 2 - Update RxEq - leave other parameter the same + 3 - Update RxDqsN - leave other parameter the same + 4 - Update RxVref - leave other parameter the same + 5 - Update RxDqsP & RxDqsN - leave other parameter the same + FF - leave all parameter the same + + @param[in] MrcData - Include all MRC global data. + @param[in] Channel - Defines channel to update + @param[in] Rank - Defines rank to update + @param[in] Byte - Defines byte to update + @param[in] Subfield - Defines the register's field or fields to update + @param[in] Value - value to be writen into register fields + + @retval Nothing +**/ +extern +void +UpdateRxT ( + IN MrcParameters *const MrcData, + IN const U8 Channel, + IN const U8 Rank, + IN const U8 Byte, + IN const U8 Subfield, + IN const U16 Value + ); + +/** + This routine updates TXTRAINRANK register's specific fields defined by the subfield + subfield values: + 0 - Update TxDq - leave other parameter the same + 1 - Update TxDqs - leave other parameter the same + 2 - Update TxEq - leave other parameter the same + 3 - Update ALL from input value (non from Mrcdata structure) + + @param[in] MrcData - Include all MRC global data. + @param[in] Channel - Defines channel to update + @param[in] Rank - Defines rank to update + @param[in] Byte - Defines byte to update + @param[in] Subfield - Defines the register's field or fields to update + @param[in] Value - value to be writen into register fields + + @retval Nothing +**/ +extern +void +UpdateTxT ( + IN MrcParameters *const MrcData, + IN const U8 Channel, + IN const U8 Rank, + IN const U8 Byte, + IN const U8 Subfield, + IN const U32 Value + ); + +/** + Returns the index into the array MarginResult in the MrcOutput structure. + + @param[in] ParamV - Margin parameter + + @retval One of the following values: LastRxV(0), LastRxT (1), LastTxV(2), LastTxT (3), LastRcvEna (4), + LastWrLevel (5), LastCmdT (6), LastCmdV (7) +**/ +extern +U8 +GetMarginResultType ( + IN const U8 ParamV + ); + +/** + This function Reads MrcData structure and finds the minimum last recorded margin for param + Searches across all bytes and ranks in RankMask + + @param[in] MrcData - Include all MRC global data. + @param[in,out] MarginResult - Data structure with the latest margin results. + @param[in] Param - Defines the margin type + @param[in] Ranks - Condenses down the results from multiple ranks + + @retval mrcWrongInputParameter if a bad Param is passed in, otherwise mrcSuccess. +**/ +extern +MrcStatus +GetMarginCh ( + IN MrcParameters *const MrcData, + IN OUT U32 MarginResult[MAX_RESULT_TYPE][MAX_RANK_IN_CHANNEL][MAX_CHANNEL][MAX_SDRAM_IN_DIMM][MAX_EDGES], + IN const U8 Param, + IN const U8 Ranks + ); + +/** + Use this function to retrieve the last margin results from MrcData + + @param[in] MrcData - Include all MRC global data. + @param[in,out] MarginResult - Data structure with the latest margin results. + @param[in] Param - Defines the margin type + @param[in] RankIn - Which rank of the host structure you want the result returned on + @param[in] Ranks - Condenses down the results from multiple ranks + + @retval MarginResult structure has been updated if MrcStatus returns mrcSuccess. + @retval Otherwise, mrcWrongInputParameter is returned if an incorrect Param is passed in. +**/ +extern +MrcStatus +GetMarginByte ( + IN MrcParameters *const MrcData, + IN OUT U32 MarginResult[MAX_RESULT_TYPE][MAX_RANK_IN_CHANNEL][MAX_CHANNEL][MAX_SDRAM_IN_DIMM][MAX_EDGES], + IN const U8 Param, + IN const U8 RankIn, + IN const U8 Ranks + ); + +/** + This function is use to "unscale" the MrcData last margin point + GetMarginByte will scale the results for FAN margin + This will unscale the results such that future tests start at the correct point + + @param[in] MrcData - Include all MRC global data. + @param[in,out] MarginResult - Input array to be unscaled. + @param[in] Param - Defines the margin type for proper scale selection. + @param[in] Rank - Which rank of the host structure to work on + + @retval mrcSuccess +**/ +extern +MrcStatus +ScaleMarginByte ( + IN MrcParameters *const MrcData, + IN OUT U32 MarginResult[MAX_RESULT_TYPE][MAX_RANK_IN_CHANNEL][MAX_CHANNEL][MAX_SDRAM_IN_DIMM][MAX_EDGES], + IN const U8 Param, + IN const U8 Rank + ); + +/** + This function is used by most margin search functions to change te underlying margin parameter. + This function allows single search function to be used for different types of margins with minimal impact. + It provides multiple different parameters, including 2D parameters like Read or Write FAN. + It can work in either MultiCast or single register mode. + + @param[in,out] MrcData - Include all MRC global data. + @param[in] param - Includes parameter(s) to change including two dimentional. + @param[in] value0 - Selected value to program margin param to + @param[in] value1 - Selected value to program margin param to in 2D mode (FAN mode) + @param[in] EnMultiCast - To enable Multicast (broadcast) or single register mode + @param[in] channel - Desired Channel + @param[in] rankIn - Desired Rank - only used for the RxTBit and TxTBit settings and to propagate RdVref + @param[in] byte - Desired byte offset register + @param[in] bitIn - Desired bit offset Mrc data strucure if UpdateMrcData is 1 + @param[in] UpdateMrcData - Used to decide if Mrc host must be updated + @param[in] SkipWait - Used to skip wait until all channel are done + @param[in] RegFileParam - Used to determine which Rank to download. Passed to MrcDownloadRegFile. + + @retval MrcStatus - if succeeded, return mrcSuccess +**/ +extern +MrcStatus +ChangeMargin ( + IN OUT MrcParameters *const MrcData, + IN const U8 param, + IN const S32 value0, + IN const S32 value1, + IN const U8 EnMultiCast, + IN const U8 channel, + IN const U8 rankIn, + IN const U8 byte, + IN const U8 bitIn, + IN const U8 UpdateMrcData, + IN const U8 SkipWait, + IN const MrcRegFile RegFileParam + ); + +/** + This function triggers the hardware to download the specified RegFile. + The setting of ReadRfRd and ReadRfWr must be mutually exclusive. + Only 1 (start download) and 0 (do nothing) are valid values for ReadRfXx. + + @param[in] MrcData - Global MRC Data + @param[in] Channel - The Channel to download target. + @param[in] ByteMulticast - Enable Multicasting all bytes on that Channel. + @param[in] Rank - The Rank download target. + @param[in] RegFileParam - Used to determine which Rank to download. + MrcRegFileRank - Uses the Rank Parameter. + MrcRegFileStart - Uses the Rank in REUT_CH_SEQ_BASE_ADDR_START after decoding logical to physical. + MrcRegFileCurrent - Uses the Rank in REUT_CH_SEQ_BASE_ADDR_CURRENT after decoding logical to physical. + @param[in] Byte - The Byte download target. + @param[in] ReadRfRd - Download the read RegFile. 1 enables, 0 otherwise + @param[in] ReadRfWr - Download the write RegFile. 1 enables, 0 otherwise + + @retval MrcStatus - If both ReadRfRd and ReadRfWr are set, the functions returns mrcWrongInputParameters. + Otherwise, mrcSuccess. +**/ +void +MrcDownloadRegFile ( + IN MrcParameters * const MrcData, + IN const U8 Channel, + IN const BOOL ByteMulticast, + IN U8 Rank, + IN const MrcRegFile RegFileParam, + IN const U8 Byte, + IN const BOOL ReadRfRd, + IN const BOOL ReadRfWr + ); + +/** + This procedure is meant to handle basic timing centering, places strobe in the middle of the data eye, + for both read and write DQ/DQS using a very robust, linear search algorthim. + + @param[in,out] MrcData - Include all MRC global data. + @param[in] chBitMaskIn - Channel bit mask. + @param[in] param - {0:RcvEn, 1:RdT, 2:WrT, 3: WrDqsT, 4:RdV, 5:WrV, 6:WrLevel, + 8:WrTBit, 9:RdTBit, 10:RdVBit, + 16:RdFan2, 17:WrFan2, 32:RdFan3, 32:WrFan3} + ONLY RdT and WrT are allowed in this function + @param[in] ResetPerBit - Option to Reset PerBit Deskew to middle value before byte training + @param[in] loopcount - loop count + + @retval MrcStatus - If succeeded, return mrcSuccess +**/ +extern +MrcStatus +DQTimeCentering1D ( + IN OUT MrcParameters *const MrcData, + IN const U8 chBitMaskIn, + IN const U8 param, + IN const U8 ResetPerBit, + IN const U8 loopcount + ); + +/** + This procedure is meant to handle much more complex centering that will use a 2D algorithm to optimize asymetical + eyes for both timing and voltage margin. + + @param[in,out] MrcData - Include all MRC global data. + @param[in,out] MarginResult - Margin data from centering + @param[in] ChBitMaskIn - Channel bit mask. + @param[in] param - {0:RcvEn, 1:RdT, 2:WrT, 3: WrDqsT, 4:RdV, 5:WrV, 6:WrLevel, + 8:WrTBit, 9:RdTBit, 10:RdVBit, + 16:RdFan2, 17:WrFan2, 32:RdFan3, 32:WrFan3} + ONLY RdT and WrT are allowed in this function + @param[in] EnPerBit - Option to enable per bit margining + @param[in] EnRxDutyCycleIn - Phase to center. + @param[in] ResetPerBit - Option to Reset PerBit Deskew to middle value before byte training + @param[in] LoopCount - loop count + @param[in] En2D - Option to only run center at nominal Vref point + + @retval MrcStatus - If succeeded, return mrcSuccess +**/ +extern +MrcStatus +DataTimeCentering2D ( + IN OUT MrcParameters *const MrcData, + IN OUT U32 MarginResult[MAX_RESULT_TYPE][MAX_RANK_IN_CHANNEL][MAX_CHANNEL][MAX_SDRAM_IN_DIMM][MAX_EDGES], + IN const U8 ChBitMaskIn, + IN const U8 Param, + IN const U8 EnPerBit, + IN const U8 EnRxDutyCycleIn, + IN const U8 ResetPerBit, + IN const U8 LoopCount, + IN const U8 En2D + ); + +/** + Subfunction of 2D Timing Centering + Measures paramV margin across ch/bytes and updates the EH/VrefScale variables + + @param[in] MrcData - Include all MRC global data. + @param[in] ChBitMask - Channel Bit mak for which test should be setup for. + @param[in] rank - Defines rank to used for MrcData + @param[in] ParamV - Margin parameter + @param[in] MaxVScale - Maximum Voltage Scale to use + @param[in] BMap - Byte mapping to configure error counter control register + @param[in,out] EH - Structure that stores start, stop and increment details for address + @param[in,out] VrefScale - Parameter to be updated + @param[in,out] BERStats - Bit Error Rate Statistics. + + @retval mrcSuccess if successful, otherwise the function returns an error status. +**/ +extern +MrcStatus +DQTimeCenterEH ( + IN MrcParameters * const MrcData, + IN const U8 ChBitMask, + IN const U8 rank, + IN const U8 ParamV, + IN const U8 MaxVScale, + IN U8 * const BMap, + IN OUT U32 EH[MAX_CHANNEL][MAX_SDRAM_IN_DIMM], + IN OUT U32 VrefScale[MAX_CHANNEL][MAX_SDRAM_IN_DIMM], + IN OUT U32 * const BERStats + ); + +/** + Update the Vref value + if VrefType = 0 Updates Ch0 Vref_Dq + if VrefType = 1 Updates Ch1 Vref_Dq + if VrefType = 2 Updates Vref_CA + + @param[in,out] MrcData - Include all MRC global data. + @param[in] VrefType - Determines the Vref to change + @param[in] UpdateMrcData - Used to decide if Mrc host must be updated + @param[in] Offset - Vref value + @param[in] SkipWait - Determines if we will wait for vref to settle after writing to register + + @retval Nothing +**/ +extern +void +UpdateVrefWaitTilStable ( + IN OUT MrcParameters *const MrcData, + IN const U8 VrefType, + IN const U8 UpdateMrcData, + IN S32 Offset, + IN U8 SkipWait + ); + +/** + This function is used to move CMD/CTL/CLK/CKE PIs during training + + @param[in,out] MrcData - Include all MRC global data. + @param[in] Channel - Channel to shift PI for + @param[in] Iteration - Determines which PI to shift: + MrcIterationClock = 0 + MrcIterationCmdN = 1 + MrcIterationCmdS = 2 + MrcIterationCke = 3 + MrcIterationCtl = 4 + MrcIterationCmdV = 5 + @param[in] RankMask - Ranks to work on + @param[in] GroupMask - which LPDDR groups to work on for CMD/CLK/CKE; not used for DDR3 + @param[in] NewValue - value to shift in case of CLK Iteration, New value for all other cases + @param[in] UpdateHost - Determines if MrcData structure is updated + + @retval Nothing +**/ +extern +void +ShiftPIforCmdTraining ( + IN OUT MrcParameters *const MrcData, + IN const U8 Channel, + IN const U8 Iteration, + IN const U8 RankMask, + IN const U8 GroupMask, + IN S32 NewValue, + IN const U8 UpdateHost + ); + +/** + Shifts RcvEn, WriteLevel and WriteDQS timing for all bytes + Usually used when moving the clocks on a channel + + @param[in,out] MrcData - Include all MRC global data. + @param[in] Channel - Channel to update + @param[in] Rank - Rank to update + @param[in] ByteMask - Bytes to update + @param[in] Offset - value to shift + @param[in] UpdateHost - Determines if MrcData structure is updated + @param[in] SkipTx - Determines if TX update should be skipped + + @retval Nothing +**/ +extern +void +ShiftDQPIs ( + IN OUT MrcParameters *const MrcData, + IN const U8 Channel, + IN const U8 Rank, + IN const U32 ByteMask, + IN const S8 Offset, + IN const U8 UpdateHost, + IN const U8 SkipTx + ); + +/** + Retrieve the current memory frequency and clock from the memory controller. + + @param[in] MrcData - Include all MRC global data. + @param[in, out] MemoryClock - The current memory clock. + @param[in, out] Ratio - The current memory ratio setting. + @param[in, out] RefClk - The current memory reference clock. + + @retval: The current memory frequency. +**/ +extern +MrcFrequency +MrcGetCurrentMemoryFrequency ( + IN MrcParameters * const MrcData, + IN OUT U32 * const MemoryClock, + IN OUT MrcClockRatio * const Ratio, + IN OUT MrcRefClkSelect * const RefClk + ); + +#ifdef ULT_FLAG +/** + Translate LPDDR command from CA[9:0] high and low phase to DDR3 MA/BA/CMD. + This is needed to program CADB. + + @param[in] CaHigh - CA[9:0] value on the rising clock + @param[in] CaLow - CA[9:0] value on the falling clock + @param[out] MA - Translated value of MA[15:0] + @param[out] BA - Translated value of BA[2:0] + @param[out] CMD - Translated value of CMD[2:0] = [RASb, CASb, WEb] + + @retval none +**/ +extern +void +MrcConvertLpddr2Ddr ( + IN U32 const CaHigh, + IN U32 const CaLow, + OUT U32 * MA, + OUT U32 * BA, + OUT U32 * CMD + ); + +/** + Run a short CADB sequence on selected channels + + @param[in] MrcData - The MRC global data. + @param[in] ChBitMask - channels to work on. + + @retval none +**/ +extern +void +ShortRunCADB ( + IN MrcParameters * const MrcData, + IN U8 ChBitMask + ); + +#endif // ULT_FLAG +/** + Get the Rx Bias values + + @param[in, out] MrcData - Include all MRC global data. + @param[in, out] RxFselect - Location to save RxFselect. + @param[in, out] RxCBSelect - Location to save RxCBSelect. + + @retval none +**/ +extern +void +GetRxFselect ( + IN MrcParameters *const MrcData, + IN OUT S8 *RxFselect, + IN OUT U8 *RxCBSelect + ); + +#endif // _MrcCommon_h_ diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcCrosser.h b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcCrosser.h new file mode 100644 index 0000000..a0d838a --- /dev/null +++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcCrosser.h @@ -0,0 +1,1329 @@ +/** @file + This file contains all the crosser training algorithm definitions. + +@Copyright + Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved. + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement. +**/ +#ifndef _MrcCrosser_h_ +#define _MrcCrosser_h_ + +// +// Include files +// +#include "MrcTypes.h" +#include "MrcApi.h" +#include "McAddress.h" +#include "MrcCommon.h" +#include "MrcDdr3.h" +#include "MrcIoControl.h" +#include "MrcOem.h" +#include "MrcReadDqDqs.h" +#include "MrcWriteDqDqs.h" +#include "MrcRefreshConfiguration.h" +#include "MrcTimingConfiguration.h" +#include "MrcReset.h" + +#define MAX_BITS_FOR_OFFSET_TRAINING (MAX_BITS + 1) ///< for ULT offset training done for 8 bits + DQS bit + +/// +/// Module Defines +/// +#define CROSSER_DISABLE_SQUARED_FUNCTION (0) +#define CROSSER_ENABLE_SQUARED_FUNCTION (1) +#define CROSSER_MIDDLE_SCALING_1 (1) +#define CROSSER_OPTIMIZE_LOW_POWER (0) +#define CROSSER_OPTIMIZE_HIGH_POWER (1) +#define CROSSER_EXCLUDE_END_POINTS (0) +#define CROSSER_INCLUDE_END_POINTS (1) + +/// +/// Enumerations and Structs +/// + +typedef enum { + RdOdt, + WrDS, + WrDSCmd, + WrDSCtl, + WrDSClk, + SCompDq, + SCompCmd, + SCompCtl, + SCompClk, + DisOdtStatic +} TGlobalCompOffset; + +typedef enum { + RdSAmpOfft, + WrDSOfft, + RxEqOfft, + TxEqOfft, + RdOdtOfft, + SizeOfTCompOffset +} TCompOffset; + +typedef enum { + rd2rdXtalk, + rd2wrXtalk, + wr2wrXtalk, + wr2rdXtalk, + AllXtalk +} CrossTalkModes; + +/// +/// These enums index MoreResultsStrings in PrintCalcResultTableCh() +/// +typedef enum { + MrcOptResultBest, + MrcOptResultGrdBnd, + MrcOptResultOffSel, + MrcOptResultScale, + MrcOptResultSignal, + MrcOptResultNoise, + MrcOptResultRatio, + MrcOptResultMaxPost, + MrcOptResultMinPost, + MrcOptResultTicks, + MrcOptResultSnrTot, + + MrcOptResultMax +} MrcOptResultString; + + +#define MaxOptOff (35) + +#pragma pack (push, 1) +typedef struct { + U32 EW; +} OptResult; + +typedef struct { + U16 Best; + S8 GuardBand; + U8 Scale[5]; + U32 Signal[5]; + U32 Noise[5]; + U32 Ratio[5]; + U32 MaxPost[5]; + U32 MinPost[5]; + U16 Ticks[5]; + U64 SNRTotal; + U64 MaxR; + U64 MinR; + U64 Result[MaxOptOff]; + OptResult Margins[5][MaxOptOff]; +} OptResultsPerByte; +#pragma pack (pop) + +typedef struct { + S16 Offset[MAX_CHANNEL][MAX_SDRAM_IN_DIMM]; + U16 Margins[4][MAX_CHANNEL]; + U8 TestList[4][MAX_CHANNEL]; + U8 NumTests; + U8 Best; +} OptOffsetChByte; + +typedef struct { + U8 RttNom[MAX_CHANNEL][MAX_DIMMS_IN_CHANNEL]; + U8 RttWr[MAX_CHANNEL][MAX_DIMMS_IN_CHANNEL]; + S8 GRdOdt; + U32 GRdOdtCode; +} DimmOffset; + +typedef struct { + U32 CpuPwrRd; + U32 DimmPwrRd; + U32 CpuPwrWr; + U32 DimmPwrWrNT; + U32 DimmPwrWrT; + U32 ACPowerRd; + U32 ACPowerWr; + U32 ACPower; + U16 CpuPower; + U16 DimmPwr; + U16 TotPwr; +} MrcPower; + +typedef struct { + DimmOffset ODTSet; + MrcPower PowerCalc; + U16 Test[5][MAX_CHANNEL]; + OptOffsetChByte BestOptOff[SizeOfTCompOffset][MAX_RANK_IN_CHANNEL]; + U8 NumTests; + U8 TestList[4]; + U8 OptParamTestList[5]; + U8 OptParamTestListSize; + U16 Points2Trade[5][MAX_CHANNEL]; +} DimmOptPoint; + +/** + This function implements Sense Amp Offset training. + SenseAmp/ODT offset cancellation + Find the best "average" point for Vref Control + Test Vref point with SampOffset=-7 and Test Vref Point with SampOffset=+7 + Find Vref on per ch/byte basis where -7 samples all 1 and +7 samples all 0 + + @param[in,out] MrcData - Include all MRC global data. + + @retval MrcStatus - if it succeded return mrcSuccess +**/ +extern +MrcStatus +MrcSenseAmpOffsetTraining ( + IN OUT MrcParameters *const MrcData + ); + +/** + This function looks at the margin values stored in the global data structure and checks + WrT, WrV, RdT, and RdV to see if they are above the minimum margin required. + + @param[in, out] MrcData - MRC global data. + + @retval mrcSuccess if margins are acceptable. + @retval Otherwise, mrcRetrain. +**/ +MrcStatus +MrcRetrainMarginCheck ( + IN OUT MrcParameters *const MrcData + ); + +/** + This function implements Dimm Ron training. + + @param[in] MrcData - Include all MRC global data. + + @retval MrcStatus - if it succeeds return mrcSuccess +**/ +extern +MrcStatus +MrcDimmRonTraining ( + IN MrcParameters *const MrcData + ); + +/** + This function implements DIMM ODT training. + Adjust DIMM RTT_NOM/RTT_WR value to maximize read/write voltage/timing + + RdOdtPriority Needs to be an input parameter + option to prioritize the ReadODT setting and attempt to optimize that value first, + reducing CPU TDP power (as opposed to system power for the DRAM). + For this case, the base value for ReadODT is changed at the compensation block + by looking at the following values: + RdOdt Global: (50, 64, 84, 110) + + In the case of 2 dpc, the flow will first optimizing RttNom, while keeping RttWr fixed + at 60 Ohms (60 Ohms usually gives the best results). It will then try to reduce RttWr + to 120 Ohms if possible. + + In the case of 1 dpc, only RttNom is used and only a single pass is required. + However, it is important to note that the two channels are completely independent + and can have different numbers of dimms populated. + + @param[in] MrcData - Include all MRC global data. + + @retval MrcStatus - if it succeed return mrcSuccess +**/ +extern +MrcStatus +MrcDimmODTTraining ( + IN MrcParameters *const MrcData + ); + +/** + This function implements Dimm Odt training. + Optimize Dimm Odt value for performance/power + + @param[in] MrcData - Include all MRC global data. + + @retval MrcStatus - If it succeded return mrcSuccess +**/ +extern +MrcStatus +MrcDimmODT1dTraining ( + IN MrcParameters *const MrcData + ); + +/** + This function implements Read Equalization training. + + @param[in] MrcData - Include all MRC global data. + + @retval MrcStatus - if it succeeds return mrcSuccess +**/ +extern +MrcStatus +MrcReadEQTraining ( + IN MrcParameters *const MrcData + ); + +/** + This function implements Write (Transmitter) Equalization training. + + @param[in] MrcData - Include all MRC global data. + + @retval MrcStatus - if it succeeds return mrcSuccess +**/ +extern +MrcStatus +MrcWriteEQTraining ( + IN MrcParameters *const MrcData + ); + +/** + This function implements Read Amplifier Power training. + + @param[in] MrcData - Include all MRC global data. + + @retval MrcStatus - If it succeeds return mrcSuccess +**/ +extern +MrcStatus +MrcReadAmplifierPower ( + IN MrcParameters *const MrcData + ); + +/** + Returns the index into the array OptResult in the MrcOutput structure. + + @param[in] OptParam - Margin parameter + + @retval One of the following values: RdSAmpOfft(0), WrDSOfft (1), RxEqOfft(2), TxEqOfft (3), RdOdtOfft(4) +**/ +extern +U8 +GetOptResultType( + IN U8 OptParam + ); + +/** + This function implements Read ODT training and Write DS. + Optimize Read ODT strength for performance & power. + + @param[in,out] MrcData - Include all MRC global data. + @param[in,out] BestOff - Structure containg the best offest and margins for th Opt param. + @param[in] ChannelMask - Channels to train + @param[in] RankMask - Condenses down the results from multiple ranks + @param[in] OptParam - Defines the OptParam Offsets. + Supported OptParam = [0: WrDS, 1: RdODT, 2: SComp, 3: TComp, 3: TxEq, 4: RxEq, + 5: RxBias, 6: DimmOdt, 7: DimmOdtWr] + @param[in] TestList - List of margin params that will be tested (up to 4) + @param[in] NumTests - The length of TestList + @param[in] Scale - List of the relative importance between the 4 tests + @param[in] PwrLimitsABC - List of the values for each test margin, above which margin is "adequate" + @param[in] Start - Start point of sweeping the Comp values + @param[in] Stop - Stop point of sweeping the Comp values + @param[in] LoopCount - The number of loops to run in IO tests. + @param[in] Repeats - Number of times to repeat the test to average out any noise + @param[in] NoPrint - Switch to disable printing. + @param[in] SkipOptUpdate - Switch to train but not update Opt settings. + @param[in] RdRd2Test - Switch to run with different TA times: possible values are [0, RdRdTA, RdRdTA_All] + @param[in] GuardBand - Signed offset to apply to the Opt params best value. + + @retval Nothing +**/ +extern +void +TrainDDROptParam ( + IN OUT MrcParameters *const MrcData, + IN OUT OptOffsetChByte *BestOff, + IN U8 ChannelMask, + IN U8 RankMask, + IN U8 OptParam, + IN U8 *TestList, + IN U8 NumTests, + IN U8 *Scale, + IN U16 *PwrLimitsABC, + IN S8 Start, + IN S8 Stop, + IN U8 LoopCount, + IN U8 Repeats, + IN BOOL NoPrint, + IN BOOL SkipOptUpdate, + IN U8 RdRd2Test, + IN S8 GuardBand + ); + +/** + This function implements Read ODT training. + Optimize Read ODT strength for performance & power + + @param[in] MrcData - Include all MRC global data. + + @retval MrcStatus - If it succeded return mrcSuccess +**/ +extern +MrcStatus +MrcReadODTTraining ( + IN MrcParameters *const MrcData + ); + +/** + This function is the Write Drive Strength training entry point. + This step will optimize write drive strength for performance & power. + + @param[in] MrcData - Include all MRC global data. + + @retval MrcStatus - If it succeeds return mrcSuccess +**/ +extern +MrcStatus +MrcWriteDriveStrength ( + IN MrcParameters *const MrcData + ); + +/** + Updates a given ch/Rank/byte combination with a new value for OptParam + OptParam can be: WrDS, RdOdt, TComp, SComp, RxEq, TxEq, RxBias or DimmOdt + OptParam == OptDefault restore values from Host except Dimms Odt's + @param[in,out] MrcData - Include all MRC global data. + @param[in] Channel - Channel index to work on. + @param[in] Ranks - Condenses down the results from multiple ranks + @param[in] Byte - Byte index to work on. + @param[in] OptParam - Defines the OptParam Offsets. + Supported OptParam = [0: WrDS, 1: RdODT, 2: SComp, 3: TComp, 4: TxEq, + 5: RxEq, 6: RxBias, 7: DimmOdt, 8: DimmOdtWr] + @param[in] Off - Offset + @param[in] UpdateHost - Desides if MrcData has to be updated + + @retval Nothing +**/ +extern +void +UpdateOptParamOffset ( + IN OUT MrcParameters *const MrcData, + IN const U8 Channel, + IN const U8 Ranks, + IN const U8 Byte, + IN const U8 OptParam, + IN S16 Off, + IN const U8 UpdateHost + ); + +/** + Slightly penalize any Asymmetry in margin + + @param[in] NegEdge - Negative edge of the margin + @param[in] PosEdge - Positive edge of the margin + + @retval p2p - Width/Height reduced by the asymmetric difference in margin. +**/ +extern +U16 +EffectiveMargin ( + IN const U16 NegEdge, + IN const U16 PosEdge + ); + +/** + This function does a running average on Margins in two dimentional fashion. + + @param[in,out] Margins - Margins to average + @param[in] Test - Selects the Margins to average + @param[in] MLen - Determines the Y-Dimension lengths + @param[in] XDim - Determines the X-Dimension lengths + @param[in] XMin - Used to skip the first elements in the Margin when averaging. + @param[in] CScale - Used to place more weight on the center point. + + @retval Nothing +**/ +extern +void +RunningAverage2D ( + IN OUT U16 Margins[2][24], + IN const U8 Test, + IN const U8 MLen, + IN const U8 XDim, + IN const U8 XMin, + IN const U8 CScale + ); + +/** + Updates a given ch/Rank/byte combination with a new value for OptParam + OptParam can be: WrDS, RdOdt, TComp, SComp, RxEq, TxEq, RxBias or DimmOdt + + # Margins: Upto 4 arrays that contain lenMargin elements + # Index to the array represents some arbitrary parameter value that we are optimizing + # Scale is 4 element array that scales the relative importance on Margins[0] vs. [1] ... + # ex: To make Margins[0] twice as important, set Scale = [1, 2, 2, 2] + # Since the search optimizes the lowest margin, increasing 1/2/3 makes 0 more important + # This function can be used to optimize only Margin[0] by setting Scale = [1, 0, 0, 0] + # EnSq = 1 uses a squared function to make the tradeoff between 0/1/2/3 steeper + # If AveN > 0, pre-processes the results with a N point running average filter + # IncEnds: By setting to 1, the running average will also include the end points + # ScaleM: Allows the middle point of the running average to be scaled up + # + # In addition to optimizing for margin, this function can also optimize for power + # PwrLimit is a 4 element array that sets level where pwr is more important than margin + # Find any points where ((Margin[0]>PwrLimit[0]) & (Margin[1]>PwrLimit[1]) & ... ) + # If such points exists and PwrOptHigh = 1, returns point with the highest X value + # If such points exists and PwrOptHigh = 0, returns point with the lowest X value + # If you don't want to optimize for power, set PwrLimitA and PwrLimitB to large number + # Power Optimize still uses the running average filter + # + # To avoid overflow, this function will automatic scale margins to fit in uint32 + + @param[in] MrcData - The global MRC data structure. + @param[in,out] OptResByte - Structure containing the optimized results. + @param[in] inputMargins - Margins we are optimizing + @param[in] MarginsLength - The length of inputMargins + @param[in] LenMargin - The length of inputMargins we are optimizing (0 - LenMargin -1). + @param[in] Scale - Controls the scaling of the input margin: 1-1, 1-2, ... and so on. + @param[in] EnSq - Enables the square root term in the optimization functions. + @param[in] AveN - The number of points used for the averaging filter. + @param[in] IncEnds - Controls if the endpoints are to be included. + @param[in] ScaleM - Controls the scaling of the middle point in 1-D average filter. + @param[in] PwrLimit - The power limit above which we only trade-off for power and not margin. + @param[in] PwrOptHigh - Controls returning the highest or lowest optimization point. + @param[in] GuardBand - Signed offest to check if margin drop is acceptable. Save good guardband + in OptResByte. + + @retval Nothing. +**/ +extern +void +FindOptimalTradeOff ( + IN MrcParameters *const MrcData, + IN OUT OptResultsPerByte *OptResByte, + IN void *inputMargins, + IN U8 MarginsLength, + IN S8 LenMargin, + IN U8 *Scale, + IN U8 EnSq, + IN U8 AveN, + IN U8 IncEnds, + IN U8 ScaleM, + IN U16 *PwrLimit, + IN U8 PwrOptHigh, + IN S8 GuardBand + ); + +/** + This function implements Turn Around Timing training. + Optimize TA ODT Delay and Duration + + @param[in] MrcData - Include all MRC global data. + + @retval MrcStatus - If it succeeds return mrcSuccess. +**/ +extern +MrcStatus +MrcTurnAroundTiming ( + IN MrcParameters * const MrcData + ); + +/** + General purpose function to optimize an abritray value, OptParam (see list above) + OptParam is generally some timing number that impacts performance or power + Expects that as OptParam gets smaller*, margins are flat until we hit a cliff + This procedure defines a cliff as a reducution of 4 ticks in eye height/width + * In the case of mcodts, higher values are actually worst + To stress out the timing, xxDDR_CLK is shifted by +/- 15 PI ticks + + @param[in] MrcData - Include all MRC global data. + @param[in] OptParam - Supports Turnaround Timings and ODT Start / Duration + @param[in] TestList - List of margin param to check to make sure timing are okay. + @param[in] NumTests - The size of TestList + @param[in] Start - Start point for this turn around time setting. + @param[in] Stop - Stop point for this turnaround time setting. + Note that the Start/Stop values are the real values, not the encoded value + @param[in] LoopCount - Length of a given test + @param[in] Update - Update the CRs and host structure with ideal values + @param[in] ClkShifts - Array of Pi clocks to be shifted + @param[in] MarginByte - Byte level margins + @param[in] NumR2RPhases - Number of PI clock phases + @param[in] rank - rank to work on + @param[in] RankMask - RankMask to be optimized + @param[in] GuardBand - GuardBand to be added to last pass value (to be a bit conservative). + + @retval MrcStatus - If it succeeds return mrcSuccess +**/ +extern +MrcStatus +TrainDDROptParamCliff ( + IN MrcParameters *const MrcData, + IN U8 OptParam, + IN U8 TestList[], + IN U8 NumTests, + IN S8 Start, + IN S8 Stop, + IN U8 LoopCount, + IN U8 Update, + IN U32 MarginByte[MAX_RESULT_TYPE][MAX_RANK_IN_CHANNEL][MAX_CHANNEL][MAX_SDRAM_IN_DIMM][MAX_EDGES], + IN S8 *ClkShifts, + IN U8 NumR2RPhases, + IN U8 rank, + IN U8 RankMask, + IN U8 GuardBand + ); + +/** + Sets commnad margins when moving WrT, WrTBox, or WrV + NOTE: ONLY one, ResetDDR or SelfRefresh can be set inside this function + + @param[in] MrcData - Include all MRC global data. + @param[in] ChBitMask - Bit mask of populated channels + @param[in] Ranks - Bit Mask of populated ranks + @param[in] Param - Input parameter to update + @param[in] Value0 - value to be added + @param[in] Value1 - value to be added + @param[in] ResetDDR - Do we reset DDR? + @param[in] SelfRefresh - Do we perform Self refresh? + + @retval MrcStatus - If it succeeds return mrcSuccess +**/ +extern +void +SetCmdMargin ( + IN MrcParameters *const MrcData, + IN const U8 ChBitMask, + IN const U8 Ranks, + IN const U8 Param, + IN const U8 Value0, + IN const U8 Value1, + IN U8 ResetDDR, + IN const U8 SelfRefresh + ); + +/** + Updates the value for following OptParamCliff variables: + drrd2rd=0, ddrd2rd=1, drwr2wr=2, ddwr2wr=3, drrd2wr=4, ddrd2wr=5, drwr2rd=6, ddwr2rd=7, + rdodtd=8, wrodtd=9, mcodts=10, mcodtd=11, rtl=12} + + @param[in,out] MrcData - Include all MRC global data. + @param[in] Channel - Channel to update the specificed parameter. + @param[in] Byte - Byte to update the specified parameter. + @param[in] OptParam - Parameter to update. + @param[in] Off - Value to offset the current setting. + @param[in] UpdateHost - Switch to update the host structure with the new value. + @param[in] SkipPrint - Switch to skip debug prints. + @param[in] RankMask - Bit mask of Ranks to update. + + @retval Nothing +**/ +extern +void +UpdateTAParamOffset ( + IN OUT MrcParameters *const MrcData, + IN const U8 Channel, + IN const U8 Byte, + IN const U8 OptParam, + IN const U8 Off, + IN const U8 UpdateHost, + IN const U8 SkipPrint, + IN const U8 RankMask + ); + +/** + This function applies the new DRAM ODT settings + Walks through various optimizations to get the best result with new ODT values + This includes WrDS, RdODT, Eq, etc. + Updates Best* variables if this point if better than the prior points + chDone is both an input and output. Reports which channels have a good enough value + if SkipRd is high, it will skip the read related functions (RdODT, RdEq, RdTiming) + + @param[in] MrcData - Include all MRC global data. + @param[in,out] DimmOptPoints - Structure of all the DIMM ODT optimal settings. + @param[in] ChMask - Channel to work on. + @param[in] RankMask - Rank to work on. + @param[in] skipGRdOdt - Used to skip RdODT. + @param[in] RttNom - Rtt_Nom value for each DIMM. + @param[in] RttWr - Rtt_Wr value for each DIMM. + @param[in] GRdOdt - CPU Global Read ODT. + @param[in] OptParamTestList - List of Opt test(Drive Strength, RxBias, TxEq, RxEq) to run. + @param[in] OptParamTestListSize - Size of OptParamTestList. + @param[in] SubPwrLimits - Switch to apply power limits to the suboptimization. + @param[in] skipOptTests - Skips the suboptimization. + @param[in] skipOptPrint - Skip printing of the suboptimization steps. + @param[in] RdCenter - Switch to recenter read. + @param[in] WrCenter - Switch to recenter write. + @param[in] inputBestMargin - Array of the best margin for each test. + @param[in] MarginsLength - Length of inputBestMargin. + @param[in] OffsetPoint - Index inside inputBestMargin to start. + + @retval Nothing. +**/ +extern +void +TrainDimmOdtSetting ( + IN MrcParameters *const MrcData, + IN OUT DimmOptPoint *DimmOptPoints, + IN U8 ChMask, + IN U8 RankMask, + IN U8 skipGRdOdt, + IN U8 RttNom[MAX_CHANNEL][MAX_DIMMS_IN_CHANNEL], + IN U8 RttWr[MAX_CHANNEL][MAX_DIMMS_IN_CHANNEL], + IN S8 GRdOdt, + IN U8 *OptParamTestList, + IN U8 OptParamTestListSize, + IN BOOL SubPwrLimits, + IN BOOL skipOptTests, + IN BOOL skipOptPrint, + IN BOOL RdCenter, + IN BOOL WrCenter, + IN void *inputBestMargin, + IN U8 MarginsLength, + IN U8 OffsetPoint + ); + +/** + This function applies an offset to the global compensation logic. + Reruns Compensation and returns the new comp value + + @param[in,out] MrcData - Include all MRC global data. + @param[in] param - Parameter defining the desired global compensation logic + @param[in] offset - Value to apply + @param[in] UpdateHost - Desides if MrcData has to be updated + + @retval Returns the new comp value. +**/ +extern +U32 +UpdateCompGlobalOffset ( + IN OUT MrcParameters *const MrcData, + IN const U8 param, + IN const U32 offset, + IN const U8 UpdateHost + ); + +/** + Programs Delay/Duration for the SenseAmp and MCODT based on RcvEn timing + Provide GuardBand > 0 if needed to be more conservative in timing + Main goal is to optimize power + + @param[in,out] MrcData - Include all MRC global data. + @param[in] GuardBand - Input parameter with more conservative value + + @retval Nothing +**/ +extern +void +UpdateSampOdtTiming( + IN OUT MrcParameters *const MrcData, + IN const U8 GuardBand + ); + +/** + Turns off unused portions of the slave DLL to save power + + @param[in,out] MrcData - Include all MRC global data. + + @retval Nothing +**/ +extern +void +UpdateSlaveDLLLength( + IN OUT MrcParameters * const MrcData + ); + +#ifdef TRAD_FLAG +/** + Update Internal clocks on setting if needed. + + @param[in,out] MrcData - Include all MRC global data. + + @retval Nothing +**/ +extern +void +UpdateInternalClksOn ( + IN OUT MrcParameters *const MrcData + ); +#endif // TRAD_FLAG + +/** + This function Shifts the CMD timing. + NOTE: ONLY one, ResetDDR or SelfRefresh can be set inside this function + + @param[in,out] MrcData - Include all MRC global data. + @param[in] Ranks - Parameter defining the desired global compensation logic + @param[in] offset - per channel Value to shift picode for + @param[in] ResetDDR - Do we reset DDR? + @param[in] SelfRefresh - Do we perform Self refresh? + @param[in] UpdateHost - Determines if MrcData has to be updated + @param[in] SkipTx - Determines if TX update should be skipped + @todo: SkipTx is NOT USED at this time and we don't skip it anyway + + @retval MrcStatus - If it succeeds return mrcSuccess +**/ +extern +MrcStatus +ShiftCh2Ch ( + IN OUT MrcParameters *const MrcData, + IN const U8 Ranks, + IN const U8 *const offset, + IN U8 ResetDDR, + IN const U8 SelfRefresh, + IN const U8 UpdateHost, + IN const U8 SkipTx + ); + +/** + Programs Delay/Duration for the SenseAmp and MCODT based on RcvEn timing + Provide GuardBand > 0 if needed to be more conservative in timing + Main goal is to optimize power + + @param[in,out] MrcData - Include all MRC global data. + @param[in] ChMask - Channel to work on. + @param[in,out] BestDimmOptPoint - Best DIMM Opt settings used to update hardware + @param[in] SkipGRdOdt - Switch to skip updating CPU ODT + @param[in] SkipDimmOdts - Switch to skip updating DIMM ODT + @param[in] SkipBestOffsets - Switch to skip updating Opt settings + @param[in] UpdateHost - Switch to skip updating MRC host structure + + @retval Nothing +**/ +extern +void +UpdateOdtsValues( + IN OUT MrcParameters *const MrcData, + IN U8 ChMask, + IN OUT DimmOptPoint *BestDimmOptPoint, + IN BOOL SkipGRdOdt, + IN BOOL SkipDimmOdts, + IN BOOL SkipBestOffsets, + IN BOOL UpdateHost + ); + +/** + Peform Read Voltage Centering in 2D. + Note: This function currently only supports param = RdV + + @param[in,out] MrcData - Include all MRC global data. + @param[in,out] MarginByte - Pointer to Marging Results data structure + @param[in] ChBitMask - Channel bit mask. + @param[in] Param - {0:RcvEn, 1:RdT, 2:WrT, 3: WrDqsT, 4:RdV, 5:WrV, 6:WrLevel, + 8:WrTBit, 9:RdTBit, 10:RdVBit, + 16:RdFan2, 17:WrFan2, 32:RdFan3, 32:WrFan3} + ONLY RdV is allowed in this function + @param[in] EnPerBit - Option to enable per bit margining + @param[in] ResetPerBit - Option to Reset PerBit Deskew to middle value before byte training + @param[in] LoopCount - Loop count + @param[in] En2D - Option to only run center at nominal Vref point + + @retval MrcStatus - If it succeded return mrcSuccess +**/ +extern +MrcStatus +ReadVoltageCentering2D ( + IN OUT MrcParameters *const MrcData, + IN OUT U32 MarginByte[MAX_RESULT_TYPE][MAX_RANK_IN_CHANNEL][MAX_CHANNEL][MAX_SDRAM_IN_DIMM][MAX_EDGES], + IN U8 ChBitMask, + IN U8 Param, + IN U8 EnPerBit, + IN U8 ResetPerBit, + IN U8 LoopCount, + IN U8 En2D + ); + +#ifdef MRC_DEBUG_PRINT +/** + Prints OptParam values from CRs and Host structure for all ch/Rank/byte as well as + the Best optimization value (if requested) + OptWrDS = 0 + OptRdOd = 1 + OptSCom = 2 + OptTComp = 3 + OptTxEq = 4 + OptRxEq = 5 + OptRxBias = 6 + OptDimmOdt = 7 + OptDimmOdtWr = 8 + OptDimmRon = 9 + OptDefault = 10 + + @param[in] MrcData - Include all MRC global data. + @param[in] ChMask - Channel Mask to print the summary for + @param[in] RankMask - Rank Mask to print the summary for (in case Rank is not applicable set RankMask = 0xF) + @param[in] OptParam - Defines the OptParam Offsets. OptDefault reports all parameters + @param[in] OptOff - Structure containg the best offest and margins for the OptParam. + If OptOffsetChByte is not available, NullPtr needs to be passed (void *NullPtr) + @param[in] OptResult - True/False: Whether to print the Best optimization value + + @retval Nothing +**/ +extern +void +ReadOptParamOffsetSum ( + IN MrcParameters *const MrcData, + IN U8 ChMask, + IN U8 RankMask, + IN const U8 OptParam, + IN OptOffsetChByte *OptOff, + IN BOOL OptResult + ); + +/** + Reads OptParam value from CRs and Host structure for a given ch/Rank/byte combination + OptParam can be: WrDS, RdOdt, TComp, SComp, RxEq, TxEq, RxBias, DIMM Ron, DIMM RttNom or DIMM RttWr + + @param[in] MrcData - Include all MRC global data. + @param[out] FinalVal - Pointer to the array consisting of CR value and Host value for a particular + OptParam and given ch/Rank/byte combination. + @param[in] Channel - Channel index to work on. + @param[in] Rank - Rank index to work on (valid only for TxEq and RxEq, for others is ignored) + @param[in] Byte - Byte index to work on. + @param[in] OptParam - Defines the OptParam Offsets. Supported OptParam = + [0: WrDS, 1: RdODT, 2: SComp, 3: TComp, 3: TxEq, + 4: RxEq, 5: RxBias, 6: DimmOdt, 7: DimmOdtWr] + + @retval Nothing +**/ +extern +void +ReadOptParamOffset ( + IN MrcParameters *const MrcData, + OUT S16 *FinalVal, + IN const U8 Channel, + IN const U8 Rank, + IN const U8 Byte, + IN const U8 OptParam + ); + +/** + This function prints the Optimize margin result table + e.g: MarginResult[Test][Offset][Channel][Byte][sign] + + @param[in] MrcData - MRC data structure + @param[in] ChMask - Channels to print + @param[in] ResultArray - Array with saved margin results + @param[in] TestNum - Test index + @param[in] OffsetsNum - number of offsets + @param[in] MidPoint - Zero point + @param[in] Edges - 1 edge or 2 edge + @param[in] OptParam - Used to convert to the Opt param string for printing + @param[in] Param - Margin type to be printed. + @param[in] PowerLimits - Power limits to print. + @param[in] noPrint - Used to skip printing. + + @retval Nothing +**/ +extern +void +PrintResultTableByte4by24( + IN MrcParameters *MrcData, + IN U8 ChMask, + IN U16 ResultArray[4][24][MAX_CHANNEL][MAX_SDRAM_IN_DIMM][MAX_EDGES], + IN U16 TestNum, + IN U8 OffsetsNum, + IN U8 MidPoint, + IN U8 Edges, + IN U8 OptParam, + IN U8 Param, + IN U16 *PowerLimits, + IN BOOL noPrint + ); + +/** + This function prints the Optimize margin result table + e.g: calcResultSummary[MAX_CHANNEL][MAX_SDRAM_IN_DIMM] + + @param[in] MrcData - MRC data structure + @param[in] calcResultSummary - The data array [MAX_CHANNEL][MAX_SDRAM_IN_DIMM] + @param[in] TestList - Test list + @param[in] NumTest - Number of test + @param[in] NumOffsets - Number of offsets + @param[in] MidPoint - Middle point + @param[in] IncEnds - Print ends points + @param[in] OptParam - Used to convert to the Opt param string for printing + @param[in] OptPower - Opt Power values to be printed + @param[in] Channel - Channel to print + @param[in] Ranks - Ranks to print + @param[in] TrendLine - Switch to print the trend line + @param[in] Nibble - take low/high bytes + @param[in] perCh - Switch to only print 1 Byte of data + @param[in] noPrint - Boolean used to disable printing of results + + @retval Nothing +**/ +extern +void +PrintCalcResultTableCh( + IN MrcParameters *const MrcData, + IN OptResultsPerByte calcResultSummary[MAX_CHANNEL][MAX_SDRAM_IN_DIMM], + IN U8 *TestList, + IN U8 NumTest, + IN U8 NumOffsets, + IN S8 MidPoint, + IN BOOL IncEnds, + IN U8 OptParam, + IN U16 *OptPower, + IN U8 Channel, + IN U8 Ranks, + IN BOOL TrendLine, + IN U8 Nibble, + IN BOOL perCh, + IN BOOL noPrint + ); + +/** + This function prints the Optimize margin result table + e.g: calcResultSummary[MAX_CHANNEL][MAX_SDRAM_IN_DIMM] + + @param[in] MrcData - MRC data structure + @param[in] calcResultSummary - The data array [MAX_CHANNEL][MAX_SDRAM_IN_DIMM] + @param[in] DimmOptPoints - add argument and description to function comment + @param[in] TestList - Test list + @param[in] NumTest - Number of test + @param[in] NumOffsets - Number of offsets + @param[in] MidPoint - Middle point + @param[in] IncEnds - Print ends points + @param[in] OptParam - Used to convert to the Opt param string for printing + @param[in] Channel - Channel to print + @param[in] Ranks - Ranks to print + @param[in] TrendLine - Switch to print the trend line + @param[in] Nibble - take low/high bytes + @param[in] perCh - Switch to only print 1 Byte of data + + @retval Nothing +**/ +extern +void +PrintODTResultTable( + IN MrcParameters *const MrcData, + IN OptResultsPerByte *calcResultSummary, + IN DimmOptPoint *DimmOptPoints, + IN U8 NumOffsets, + IN S8 MidPoint, + IN BOOL IncEnds, + IN U8 OptParam, + IN U8 Channel, + IN U8 Ranks, + IN BOOL TrendLine, + IN U8 Nibble, + IN BOOL perCh + ); + +/** + This function will print out the last margin data collected of the Param passed in. + It will print both edges of all the requested bytes, Ranks and Channels. + NOTE: The function will not check to see if the Rank/Channel exists. It will print out the + values stored in the margin array regardless of population status. + + @param[in] MrcData - Global MRC data. + @param[in] Param - Parameter of MRC_MarginTypes of which to print the margin. + @param[in] ChannelMask - Bit mask of channels to print. + @param[in] RankMask - Bit mask of ranks to print. + @param[in] ByteMask - Bit mask of bytes to print. + + @retval Nothing. +**/ +void +MrcPrintLastMargins ( + IN MrcParameters *const MrcData, + IN const U8 Param, + IN const U8 ChannelMask, + IN const U8 RankMask, + IN const U16 ByteMask + ); +#endif // MRC_DEBUG_PRINT + +/** + This function returns the UPM or PWR limit value for the specified parameter + + @param[in] MrcData - Pointer to MRC global data. + @param[in] Param - Margin type + @param[in] LimitType - Type of limit: UpmLimit or PowerLimit + + @retval Returns the UPM or PWR limit +**/ +extern +U16 +UpmPwrLimitValue ( + IN MrcParameters *const MrcData, + IN U8 Param, + IN U8 LimitType + ); + +/** + This function will adjust the requested Limit Type of the margin parameter by the signed offset passed in. + + @param[in] MrcData - MRC global data. + @param[in] Param - Margin parameter type to adjust. + @param[in] LimitType - MRC_MARGIN_LIMIT_TYPE to adjust. + @param[in] Offset - The adjustment value. + + @retval U16 - The new value of Param[MRC_MARGIN_LIMIT_TYPE] +**/ +U16 +MrcUpdateUpmPwrLimits ( + IN OUT MrcParameters * const MrcData, + IN U8 Param, + IN U8 LimitType, + IN S8 Offset + ); + +/** + Calculate Power based on Ron and Rodt + Includes both static power from Ron/Rodt and dynamic power from Cpad/Cline + The power results here are not absolutely correct but give a reasonable estimate (ie: within 2x) with the proper trends + Getting absolutely correct power numbers with simple calculations is fairly difficult given the transmission line nature of the system + Driver power is calculated as the amount of power drawn from the CPU pin (do we want this to be thermal power instead?) based on the Ron and ODTeff + ODTeff is calculated as both the real, resistive ODT on the bus in parallel with the effective impendence of the cap on the line + This effective impedance is how AC power is included in the measurements + This better models the real system behavior where the power consumed due to dynamic power reduces as termination strength increases + ODT power is calculated as a purely DC term based on Ron and Rodt + The final power reported back is a scaled version of the CPU and DRAM power + This allows one to weight the CPU vs. DRAM power differently in the optimization function based on what is more important + CPU power is generally more important since it can be translated into additional performance + + @param[in] MrcData - Include all MRC global data. + @param[out] Results - Results of the Power power calculations + @param[in] RonCpu - RON CPU value (ohm) + @param[in] RonDimm - RON DIMM value (ohm) + @param[in] Rodtcpu - RODT CPU value + @param[in] Rodtdram - RODT DRAM value + @param[in] Wodtdram - WODT DRAM value + + @retval Nothing +**/ +extern +void +CalcPower( + IN MrcParameters *MrcData, + OUT MrcPower *Results, + IN U16 RonCpu, + IN U8 RonDimm, + IN U16 Rodtcpu, + IN U16 Rodtdram, + IN U16 Wodtdram + ); + +/** + This function fill the input array (e.g array[ch][rank]) with the power calculation + per rank/ch for current sys. setting. + + @param[in] MrcData - MRC data struct; + @param[in,out] PwrChRank - Array to fill; + + @retval Nothing +**/ +extern +void +CalcSysPower ( + IN MrcParameters *const MrcData, + IN OUT MrcPower PwrChRank[MAX_CHANNEL][MAX_RANK_IN_CHANNEL] + ); + +/** + Calculate Power Trend line based on Cpu and Dimms Ron and Odt's + + @param[in] MrcData - Include all MRC global data. + @param[in] Channel - Channel to work on. + @param[in] DimmMask - DIMMs to work on. + @param[in,out] DimmOptPoints - Structure of all the DIMM ODT optimal settings. + @param[in] Points2calc - Data to build the trendline on. + @param[in] ArrayLength - Array length of Points2calc. + @param[in] LenMargin - The length of inputMargins we are optimizing (0 - LenMargin -1). + @param[in] TestList - TestList index in Points2cal: WrVref, RdVref, WrT, RdT + @param[in] Scale - Scale to apply per test to Points2calc + @param[in] TestListSize - Size of TestList/Scale + @param[in] PwrCalc1d - Determines if the power test is 1-D or 2-D. + @param[in] PWRTrendSlope - Determines how aggressive the T-line will be.(0%-100%) + + @retval Nothing +**/ +extern +void +CalcPowerTrend( + IN MrcParameters *MrcData, + IN U8 Channel, + IN U8 DimmMask, + IN OUT void *DimmOptPoints, + IN void *Points2calc, + IN U8 ArrayLength, + IN U8 LenMargin, + IN U8 *TestList, + IN U8 *Scale, + IN U8 TestListSize, + IN BOOL PwrCalc1d, + IN U8 PWRTrendSlope + ); + +/** + This function returns the Actual Cpu Driver Impedance (1 segment) in ohm. + + @param[in] MrcData - Pointer to MRC global data. + @param[in] Offset - Vref Offset (+-8). + + @retval Returns the CPU driver impedance value (for 1 segment) +**/ +extern +U16 +CalcDrvImp ( + IN MrcParameters *const MrcData, + IN S8 Offset + ); + +/** + This function returns the Actual Cpu Odt termination in ohm. + + @param[in] MrcData - Pointer to MRC global data. + @param[in] Offset - Vref Offset (+-16). + + @retval Returns the Odt termination value. +**/ +extern +U16 +CalcRdOdt ( + IN MrcParameters *const MrcData, + IN S8 Offset + ); + +/** + Calculate Power for the selected Opt param based on + + @param[in] MrcData - Include all MRC global data. + @param[in] Channel - Channel to work on + @param[in] Rank - Rank to work on + @param[in] Byte - Byte to work on + @param[in] OptParam - The Opt Parameter to work on + @param[in] Offset - The Offset to work on + @param[in] CurrentComp - The current Comp code for OptParam + @param[in] ReadHost - Switch to read current offset and CompCode from Host structure. + + @retval Calc power in mW +**/ +extern +U32 +CalcOptPower( + IN MrcParameters *MrcData, + IN U8 Channel, + IN U8 Rank, + IN U8 Byte, + IN U8 OptParam, + IN S8 Offset, + IN S8 CurrentComp, + IN BOOL ReadHost + ); + +/** + This function implements Write Slew Rate training. + Optimize Write Slew Rate for performance & power + + @param[in] MrcData - Include all MRC global data. + + @retval mrcSuccess +**/ +extern +MrcStatus +MrcWriteSlewRate ( + IN MrcParameters *const MrcData + ); + +/** + This function prints out the Margin eye diagram for ParamT/ParamV. + + + @param[in] MrcData - Include all MRC global data. + @param[in] Channel - Channel to margin. + @param[in] Ranks - Bit mask of Ranks to margin. + @param[in] ParamT - Time parameter to margin. + @param[in] ParamV - Voltage parameter to margin. + @param[in] Start - Starting point for margining. + @param[in] Stop - Stopping point for margining. + @param[in] Repeats - Number of times to repeat the test to average out any noise. + @param[in] NoPrint - Switch to skip printing. + + @retval Nothing +**/ +extern +void +EyeMargin ( + IN MrcParameters *const MrcData, + IN U8 Channel, + IN U8 Ranks, + IN U8 ParamT, + IN U8 ParamV, + IN S8 Start, + IN S8 Stop, + IN U16 SearchLimits, + IN U8 LoopCount, + IN U8 Repeats, + IN BOOL NoPrint + ); + +/** + This function optimize the digital offsets by reducing the digital + offset and apply the difference to the global one. + + @param[in] MrcData - Include all MRC global data. + @param[in] Param - Parameter defining the desired digital compensation offset. + @param[in] UpdateHost - Decides if MrcData is to be updated. + + @retval The new comp value. +**/ +extern +U32 +OptimizeCompOffset ( + IN MrcParameters *const MrcData, + IN const U8 Param, + IN const U8 UpdateHost + ); + +/** + This function implements the Write Drive Strength optimization for performance and power. + + @param[in] MrcData - Include all MRC global data. + @param[in] ChBitMask - Channel mask to perform training on the Opt Param test list. + @param[in] RecenterLC - The loopcount for Write Time recentering. + @param[in] OptParamLC - The loopcount for training the Opt Param test list. + @param[in] Recenter - Switch which determines if the step recenters Write Timing. + + @retval If it succeeds return mrcSuccess +**/ +extern +MrcStatus +TrainWriteDriveStrength ( + IN MrcParameters *const MrcData, + IN const U8 ChBitMask, + IN const U8 RecenterLC, + IN const U8 OptParamLC, + IN const BOOL Recenter + ); + +/** + This step performs Comp Offset optimization on the param list defined in this function. + + @param[in] MrcData - Include all MRC global data. + + @retval MrcStatus - mrcSuccess +**/ +extern +MrcStatus +MrcOptimizeComp ( + IN MrcParameters *const MrcData + ); + +/** + This function calculates the percent of power saving from the power optimization steps and + updates the proper registers in the PCU. To get the correct base line for this calculation, + this routing needs to run first time early in the training in order to update the MrcStruct + with the base line. After the power training steps, it will run again to get the actual + percent of power saving. + + @param[in] MrcData - Include all MRC global data. + + @retval MrcStatus - mrcSuccess + +**/ +extern +MrcStatus +MrcPowerSavingMeter ( + IN MrcParameters *const MrcData + ); + +#endif // _MrcCrosser_h_ diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcDdr3.h b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcDdr3.h new file mode 100644 index 0000000..a1ce4e1 --- /dev/null +++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcDdr3.h @@ -0,0 +1,449 @@ +/** @file + This file includes all the DDR3 specific characteristic definitions. + +@copyright + Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved. + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement. + +**/ +#ifndef _MrcDdr3_h_ +#define _MrcDdr3_h_ + +#include "MrcTypes.h" +#include "MrcApi.h" +#include "McAddress.h" +#include "MrcCommon.h" +#include "MrcDdr3Registers.h" +#include "MrcIoControl.h" +#include "MrcOem.h" +#include "MrcPowerModes.h" +#include "MrcRefreshConfiguration.h" + +#pragma pack (push, 1) +/// +/// in write leveling mode Rtt_Nom = Rtt_Wr +/// +typedef struct { + U8 RttWr; ///< Wa - Write ODT on active rank + U8 RttNom; ///< Wp - ODT on one of the ranks on passive DIMM during Write operation +} TOdtValue; + +typedef enum { + oi1DPC1R = 0, + oi1DPC2R, + oi2DPC1R1R, + oi2DPC1R2R, + oi2DPC2R1R, + oi2DPC2R2R, + oiNotValid +} TOdtIndex; + +typedef enum { + ODIC_RZQ_6, + ODIC_RZQ_7, + ODIC_RSVD_0, + ODIC_RSVD_1 +} TOutputDriverImpedanceControl; + +/// +/// ZQ Calibration types +/// +typedef enum { + MRC_ZQ_INIT, ///< DDR3: ZQCL with tZQinit, LPDDR3: ZQ Init with tZQinit + MRC_ZQ_LONG, ///< DDR3: ZQCL with tZQoper, LPDDR3: ZQ Long with tZQCL + MRC_ZQ_SHORT, ///< DDR3: ZQCS with tZQCS, LPDDR3: ZQ Short with tZQCS + MRC_ZQ_RESET ///< DDR3: not used, LPDDR3: ZQ Reset with tZQreset +} MrcZqType; + +#ifndef tZQinit +#define tZQinit (512) ///< define the tZQinit as define in jedec spec +#endif + +#ifndef tWLMRD +#define tWLMRD (40) ///< First DQS/DQS# rising edge after write leveling mode is programmed. +#endif + +#ifndef tWLOE +#define tWLOE (40) ///< Write leveling output error the time is 2ns ~ 2 nCK +#endif + +#ifndef tZQCS_TIME +#define tZQCS_TIME (64) ///< jedec timing +#endif + +#define MRC_DDR3_SDRAM_TYPE_NUMBER (0x0B) ///< use to know the DDR type that data came from Jedec SPD byte 2 +#define MRC_UDIMM_TYPE_NUMBER (0x02) ///< use to know if the DIMM type is UDIMM define in Jedec SPD byte 3 +#define MRC_SOIMM_TYPE_NUMBER (0x03) ///< use to know if the DIMM type is SO-DIMM define in Jedec SPD byte 3 +#define MRC_SDRAM_DEVICE_WIDTH_8 (0x1) ///< use to know if the DDRAM is 8 bits width +#define MRC_SDRAM_DEVICE_WIDTH_16 (0x2) ///< use to know if the DDRAM is 16 bits width +#define MRC_PRIMARY_BUS_WIDTH_64 (0x3) ///< use to know if the DIMM primary bus width is not 64 +#define MRC_CL_MAX_OFFSET (0xF) ///< in the spd data include cl from bit 0 to bit 15 each bit represent different support CL +#define MRC_CL_IN_NANO_SEC (20) ///< define the nax CL value in nano second + +/** +@brief + this function reverses MA and BA bits for Rank1 + + @param[in] BA - MRS command to be sent + @param[in] MA - Value to be sent + + @retval Proper MA and BA BITS. +**/ +extern +U32 +MrcMirror ( + IN U8 BA, + IN U16 MA + ); + +/** +@brief + this function writes to CADB + + @param[in] MrcData - include all the MRC data + @param[in] Channel - Channel to send command to + @param[in] RankMask - Rank mask for which command will be sent to. + @param[in] CMD - 0: MRS, 1: REF, 2: PRE, 3: ACT, 4: WR, 5: RD, 6: ZQ, 7: NOP + @param[in] BA - MRS command to be sent + @param[in] MA - Value to be sent + @param[in] Delay - Delay in Dclocks + + @retval MrcStatus +**/ +extern +MrcStatus +MrcWriteCADBCmd ( + IN MrcParameters *const MrcData, + IN const U8 Channel, + IN const U8 RankMask, + IN const U8 CMD, + IN const U8 BA, + IN const U16 *const MA, + IN const U8 Delay + ); + +/** +@brief + This function sends the proper MRS command for specific ranks as indicated by RankMask + + @param[in] MrcData - include all the MRC data + @param[in] Channel - Channel to send command to + @param[in] RankMask - Rank mask for which command will be sent to + @param[in] MR - MRS command to be sent + @param[in] DimmValue - Dimm Values to be sent + + @retval MrcStatus +**/ +extern +MrcStatus +MrcWriteMRSAll ( + IN MrcParameters *const MrcData, + IN const U8 Channel, + IN const U8 RankMask, + IN const U8 MR, + IN const U16 *const DimmValue + ); + +/** +@brief + This function sends the proper MRS command for specific ranks as indicated by RankMask + + @param[in] MrcData - Include all the MRC data + @param[in] Channel - Channel to send command to + @param[in] RankMask - Rank mask for which command will be sent to + @param[in] MR - MRS command to be sent + @param[in] Value - Value to be sent + + @retval MrcStatus +**/ +extern +MrcStatus +MrcWriteMRS ( + IN MrcParameters *const MrcData, + IN const U8 Channel, + IN const U8 RankMask, + IN const U8 MR, + IN const U16 Value + ); + +/** +@brief + Issue ZQ calibration command on all ranks. + When done, wait appropriate delay depending on the ZQ type. + + @param[in] MrcData - include all the MRC data + @param[in] chBitMask - Channel bit mask to be sent to. + @param[in] ZqType - Type of ZQ Calibration: see MrcZqType enum + + @retval MrcStatus - mrcSuccess if passes, otherwise an error status +**/ +extern +MrcStatus +MrcIssueZQ ( + IN MrcParameters *const MrcData, + IN const U8 chBitMask, + IN const MrcZqType ZqType + ); + +/** +@brief + This function writes the MR2 register for all the ranks and channels + + @param[in, out] MrcData - general data + @param[in] Pasr - Partial array self refresh bit A0-A2 + + @retval MrcStatus - mrcSuccess if passes, otherwise an error status +**/ +extern +MrcStatus +MrcSetMR2 ( + IN OUT MrcParameters *const MrcData, + IN const U8 Pasr + ); + +/** +@brief + This function writes the MR3 register for all the ranks and channels + + @param[in] MrcData - include all the MRC data + @param[in] MPRLoc - MPR Location bit A0-A1 + @param[in] Mpr - MPR bit A2 + + @retval MrcStatus - mrcSuccess if passes, otherwise an error status +**/ +extern +MrcStatus +MrcSetMR3 ( + IN MrcParameters *const MrcData, + IN const U8 MPRLoc, + IN const U8 Mpr + ) +; + +/** +@brief + This function writes the MR1 register for all the ranks and channels + + @param[in, out] MrcData - include all the MRC data + @param[in] DLLEnable - DLL enable bit A0 + @param[in] Odic - Output driver impedance control A5, A1 + @param[in] AdditiveLatency - Additive latency bit A3-A4 + @param[in] WlEnable - Write leveling enable bit A7 + @param[in] Tdqs - TDQS enable bit A11 + @param[in] Qoff - Qoff bit A12 + + @retval MrcStatus - mrcSuccess if passes, otherwise an error status +**/ +extern +MrcStatus +MrcSetMR1 ( + IN OUT MrcParameters *const MrcData, + IN const U8 DLLEnable, + IN const U8 Odic, + IN const U8 AdditiveLatency, + IN const U8 WlEnable, + IN const U8 Tdqs, + IN const U8 Qoff + ); + +/** +@brief + This function writes the MR0 register for all the ranks + + @param[in, out] MrcData - include all the MRC data + @param[in] CommandControl - include the command control params + @param[in] BurstLength - Burst length bit A0-A1 + @param[in] ReadBurstType - Read burst type bit A3 + @param[in] TestMode - Test mode type bit A7 + @param[in] DllReset - DLL reset bit A8 + + @retval MrcStatus - mrcSuccess if passes, otherwise an error status +**/ +extern +MrcStatus +MrcSetMR0 ( + IN OUT MrcParameters *const MrcData, + IN const U8 Bl, + IN const U8 Rbt, + IN const U8 Tm, + IN const U8 Dll + ); + +/** +@brief + This function return tWLO time. this time is Write leveling output delay. + + @param[in] Frequency - MC frequency. + + @retval tWLO timein nCK. +**/ +extern +U32 +GetTwloTime ( + IN const MrcFrequency Frequency + ); + +/** +@brief + This funtion returns the odt table index for the given Dimm/Channel. + + @param[in] MrcData - Include all the mrc global data. + @param[in] Channel - Channel to work on. + @param[in] Dimm - Rank to work on. + + @retval OdtValue - iThe pointer to the relevant Odt values. +**/ +extern +TOdtValue * +GetOdtTableIndex ( + IN MrcParameters *const MrcData, + IN const U8 Channel, + IN const U8 Dimm + ); + +/** +@brief + This funtion takes the MR1 register value and updates the odt value + inside the register. + + @param[in] MrcData - Include all the MRC general data. + @param[in] OdtValue - Selected odt index. + @param[in] Ddr3ModeRegister - Register to update. + + @retval Ddr3ModeRegister - Updated register +**/ +extern +DDR3_MODE_REGISTER_1_STRUCT +UpdateRttNomValue ( + IN MrcParameters *const MrcData, + IN const U8 OdtValue, + IN DDR3_MODE_REGISTER_1_STRUCT Register + ); + +/** +@brief + This function updates the Rtt value in the MR2 value passed in. + + @param[in] MrcData - Include all the MRC general data. + @param[in] OdtValue - Selected odt index. + @param[in] Ddr3ModeRegister - Register to update. + + @retval Ddr3ModeRegister - Updated MR2 register +**/ +extern +DDR3_MODE_REGISTER_2_STRUCT +UpdateRttWrValue ( + IN MrcParameters *const MrcData, + IN const U8 OdtValue, + IN DDR3_MODE_REGISTER_2_STRUCT Ddr3ModeRegister + ); + +/** +@brief + this funtion select the ODT table according OEM/USER decision. + In the MRC have 4 table type Mb,Dt,User1,User2. + User1,User2 use as internal usage. + + @param[in] MrcData - Include all the MRC general data. + @param[in] Dimm - selected DIMM. + @param[in] OdtIndex - selected odt index. + + @retval TOdtValue * - Pointer to the relevant table. + The return value is NULL if the table could + not be found +**/ +extern +TOdtValue * +SelectTable ( + IN MrcParameters *const MrcData, + IN const U8 Dimm, + IN const TOdtIndex OdtIndex + ); + +#ifdef ULT_FLAG + +/** +@brief + Issue LPDDR MRW (Mode Register Write) command using MRH (Mode Register Handler). + + @param[in] MrcData - Include all MRC global data. + @param[in] Channel - the channel to work on + @param[in] Rank - the rank to work on + @param[in] Address - MRW address + @param[in] Data - MRW Data + @param[in] InitMrw - when TRUE, command is stretched (used before CA training is done) + @param[in] ChipSelect2N - when TRUE, use 2N stretch mode for CS (used before CA training is done) + + @retval mrcSuccess - MRW was sent successfully + @retval mrcDeviceBusy - timed out waiting for MRH +**/ +extern +MrcStatus +MrcIssueMrw ( + IN MrcParameters *const MrcData, + IN U32 Channel, + IN U32 Rank, + IN U32 Address, + IN U32 Data, + IN BOOL InitMrw, + IN BOOL ChipSelect2N + ); + +/** +@brief + Issue LPDDR MRR (Mode Register Read) command using MRH (Mode Register Handler). + Use DQ mapping array to deswizzle the MR data. + + @param[in] MrcData - Include all MRC global data. + @param[in] Channel - the channel to work on + @param[in] Rank - the rank to work on + @param[in] Address - MRR address + @param[out] Data - MRR Data array per SDRAM device + + @retval mrcSuccess - MRR was executed successfully + @retval mrcDeviceBusy - timed out waiting for MRH +**/ +extern +MrcStatus +MrcIssueMrr ( + IN MrcParameters *const MrcData, + IN U32 Channel, + IN U32 Rank, + IN U32 Address, + OUT U8 Data[4] + ); + +/** +@brief + Issue LPDDR PRECHARGE ALL command using CADB. + + @param[in] MrcData - Include all MRC global data. + @param[in] Channel - The channel to work on + @param[in] RankMask - The rank(s) to work on + + @retval none +**/ +void +MrcIssuePrechargeAll ( + IN MrcParameters *const MrcData, + IN const U8 Channel, + IN const U8 RankMask + ); + +#endif // ULT_FLAG + +#pragma pack (pop) +#endif // _MrcDdr3_h_ diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcDdr3Registers.h b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcDdr3Registers.h new file mode 100644 index 0000000..7041495 --- /dev/null +++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcDdr3Registers.h @@ -0,0 +1,249 @@ +/** @file + Include all the DDR3 register definitions. + +@copyright + Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement. +**/ +#ifndef _MrcDdr3Registers_h_ +#define _MrcDdr3Registers_h_ + +#pragma pack(push, 1) + +typedef union { + struct { + U16 BurstLength : 2; ///< Bits 0:1 + U16 CasLatencyLow : 1; ///< Bits 2:2 + U16 ReadBurstType : 1; ///< Bits 3:3 + U16 CasLatencyHigh : 3; ///< Bits 4:6 + U16 TestMode : 1; ///< Bits 7:7 + U16 DllReset : 1; ///< Bits 8:8 + U16 WriteRecovery : 3; ///< Bits 9:11 + U16 PrechargePdDll : 1; ///< Bits 12:12 + U16 : 3; ///< Bits 13:15 + } Bits; + U16 Data; + U8 Data8[2]; +} DDR3_MODE_REGISTER_0_STRUCT; + +typedef union { + struct { + U16 DllEnable : 1; ///< Bits 0:0 + U16 ODImpedanceLow : 1; ///< Bits 1:1 + U16 OdtRttValueLow : 1; ///< Bits 2:2 + U16 AdditiveLatency : 2; ///< Bits 3:4 + U16 ODImpedanceHigh : 1; ///< Bits 5:5 + U16 OdtRttValueMid : 1; ///< Bits 6:6 + U16 WriteLeveling : 1; ///< Bits 7:7 + U16 : 1; ///< Bits 8:8 + U16 OdtRttValueHigh : 1; ///< Bits 9:9 + U16 : 1; ///< Bits 10:10 + U16 Tdqs : 1; ///< Bits 11:11 + U16 Qoff : 1; ///< Bits 12:12 + U16 : 3; ///< Bits 13:15 + } Bits; + U16 Data; + U8 Data8[2]; +} DDR3_MODE_REGISTER_1_STRUCT; + +typedef union { + struct { + U16 PartialArraySR : 3; ///< Bits 0:2 + U16 CasWriteLatency : 3; ///< Bits 3:5 + U16 AutoSelfRefresh : 1; ///< Bits 6:6 + U16 SelfRefreshTemp : 1; ///< Bits 7:7 + U16 : 1; ///< Bits 8:8 + U16 DynamicOdt : 2; ///< Bits 9:10 + U16 : 5; ///< Bits 11:15 + } Bits; + U16 Data; + U8 Data8[2]; +} DDR3_MODE_REGISTER_2_STRUCT; + +typedef union { + struct { + U16 MprLocation : 2; ///< Bits 0:1 + U16 MprOperation : 1; ///< Bits 2:2 + U16 : 13; ///< Bits 3:15 + } Bits; + U16 Data; + U8 Data8[2]; +} DDR3_MODE_REGISTER_3_STRUCT; + +/// +/// MR0 register +/// +#define DDR3_MODE_REGISTER_0_BL_OFF (0) +#define DDR3_MODE_REGISTER_0_BL_WID (2) +#define DDR3_MODE_REGISTER_0_BL_MSK (3) +#define DDR3_MODE_REGISTER_0_BL_MAX (3) +#define DDR3_MODE_REGISTER_0_BL_DEF (0) + +#define DDR3_MODE_REGISTER_0_CL_A2_OFF (2) +#define DDR3_MODE_REGISTER_0_CL_A2_WID (1) +#define DDR3_MODE_REGISTER_0_CL_A2_MSK (1) +#define DDR3_MODE_REGISTER_0_CL_A2_MAX (1) +#define DDR3_MODE_REGISTER_0_CL_A2_DEF (0) + +#define DDR3_MODE_REGISTER_0_RBT_OFF (3) +#define DDR3_MODE_REGISTER_0_RBT_WID (1) +#define DDR3_MODE_REGISTER_0_RBT_MSK (1) +#define DDR3_MODE_REGISTER_0_RBT_MAX (1) +#define DDR3_MODE_REGISTER_0_RBT_DEF (0) + +#define DDR3_MODE_REGISTER_0_CL_OFF (4) +#define DDR3_MODE_REGISTER_0_CL_WID (3) +#define DDR3_MODE_REGISTER_0_CL_MSK (7) +#define DDR3_MODE_REGISTER_0_CL_MAX (7) +#define DDR3_MODE_REGISTER_0_CL_DEF (0) + +#define DDR3_MODE_REGISTER_0_TM_OFF (7) +#define DDR3_MODE_REGISTER_0_TM_WID (1) +#define DDR3_MODE_REGISTER_0_TM_MSK (1) +#define DDR3_MODE_REGISTER_0_TM_MAX (1) +#define DDR3_MODE_REGISTER_0_TM_DEF (0) + +#define DDR3_MODE_REGISTER_0_DLL_OFF (8) +#define DDR3_MODE_REGISTER_0_DLL_WID (1) +#define DDR3_MODE_REGISTER_0_DLL_MSK (1) +#define DDR3_MODE_REGISTER_0_DLL_MAX (1) +#define DDR3_MODE_REGISTER_0_DLL_DEF (0) + +#define DDR3_MODE_REGISTER_0_WR_OFF (9) +#define DDR3_MODE_REGISTER_0_WR_WID (3) +#define DDR3_MODE_REGISTER_0_WR_MSK (7) +#define DDR3_MODE_REGISTER_0_WR_MAX (7) +#define DDR3_MODE_REGISTER_0_WR_DEF (0) + +#define DDR3_MODE_REGISTER_0_PPD_OFF (12) +#define DDR3_MODE_REGISTER_0_PPD_WID (1) +#define DDR3_MODE_REGISTER_0_PPD_MSK (1) +#define DDR3_MODE_REGISTER_0_PPD_MAX (1) +#define DDR3_MODE_REGISTER_0_PPD_DEF (0) + +/// +/// MR1 register +/// +#define DDR3_MODE_REGISTER_1_DLL_OFF (0) +#define DDR3_MODE_REGISTER_1_DLL_WID (1) +#define DDR3_MODE_REGISTER_1_DLL_MSK (1) +#define DDR3_MODE_REGISTER_1_DLL_MAX (1) +#define DDR3_MODE_REGISTER_1_DLL_DEF (0) + +#define DDR3_MODE_REGISTER_1_D_I_C_A1_OFF (1) +#define DDR3_MODE_REGISTER_1_D_I_C_A1_WID (1) +#define DDR3_MODE_REGISTER_1_D_I_C_A1_MSK (1) +#define DDR3_MODE_REGISTER_1_D_I_C_A1_MAX (1) +#define DDR3_MODE_REGISTER_1_D_I_C_A1_DEF (0) + +#define DDR3_MODE_REGISTER_1_Rtt_Nom_A2_OFF (2) +#define DDR3_MODE_REGISTER_1_Rtt_Nom_A2_WID (1) +#define DDR3_MODE_REGISTER_1_Rtt_Nom_A2_MSK (1) +#define DDR3_MODE_REGISTER_1_Rtt_Nom_A2_MAX (1) +#define DDR3_MODE_REGISTER_1_Rtt_Nom_A2_DEF (0) + +#define DDR3_MODE_REGISTER_1_AL_OFF (3) +#define DDR3_MODE_REGISTER_1_AL_WID (2) +#define DDR3_MODE_REGISTER_1_AL_MSK (3) +#define DDR3_MODE_REGISTER_1_AL_MAX (3) +#define DDR3_MODE_REGISTER_1_AL_DEF (0) + +#define DDR3_MODE_REGISTER_1_D_I_C_A5_OFF (5) +#define DDR3_MODE_REGISTER_1_D_I_C_A5_WID (1) +#define DDR3_MODE_REGISTER_1_D_I_C_A5_MSK (1) +#define DDR3_MODE_REGISTER_1_D_I_C_A5_MAX (1) +#define DDR3_MODE_REGISTER_1_D_I_C_A5_DEF (0) + +#define DDR3_MODE_REGISTER_1_Rtt_Nom_A6_OFF (6) +#define DDR3_MODE_REGISTER_1_Rtt_Nom_A6_WID (1) +#define DDR3_MODE_REGISTER_1_Rtt_Nom_A6_MSK (1) +#define DDR3_MODE_REGISTER_1_Rtt_Nom_A6_MAX (1) +#define DDR3_MODE_REGISTER_1_Rtt_Nom_A6_DEF (0) + +#define DDR3_MODE_REGISTER_1_LEVEL_OFF (7) +#define DDR3_MODE_REGISTER_1_LEVEL_WID (1) +#define DDR3_MODE_REGISTER_1_LEVEL_MSK (1) +#define DDR3_MODE_REGISTER_1_LEVEL_MAX (1) +#define DDR3_MODE_REGISTER_1_LEVEL_DEF (0) + +#define DDR3_MODE_REGISTER_1_Rtt_Nom_A9_OFF (9) +#define DDR3_MODE_REGISTER_1_Rtt_Nom_A9_WID (1) +#define DDR3_MODE_REGISTER_1_Rtt_Nom_A9_MSK (1) +#define DDR3_MODE_REGISTER_1_Rtt_Nom_A9_MAX (1) +#define DDR3_MODE_REGISTER_1_Rtt_Nom_A9_DEF (0) + +#define DDR3_MODE_REGISTER_1_TDQS_OFF (11) +#define DDR3_MODE_REGISTER_1_TDQS_WID (1) +#define DDR3_MODE_REGISTER_1_TDQS_MSK (1) +#define DDR3_MODE_REGISTER_1_TDQS_MAX (1) +#define DDR3_MODE_REGISTER_1_TDQS_DEF (0) + +#define DDR3_MODE_REGISTER_1_Qoff_OFF (12) +#define DDR3_MODE_REGISTER_1_Qoff_WID (1) +#define DDR3_MODE_REGISTER_1_Qoff_MSK (1) +#define DDR3_MODE_REGISTER_1_Qoff_MAX (1) +#define DDR3_MODE_REGISTER_1_Qoff_DEF (0) + +/// +/// MR2 register +/// +#define DDR3_MODE_REGISTER_2_PASR_OFF (0) +#define DDR3_MODE_REGISTER_2_PASR_WID (3) +#define DDR3_MODE_REGISTER_2_PASR_MSK (7) +#define DDR3_MODE_REGISTER_2_PASR_MAX (7) +#define DDR3_MODE_REGISTER_2_PASR_DEF (0) + +#define DDR3_MODE_REGISTER_2_CWL_OFF (3) +#define DDR3_MODE_REGISTER_2_CWL_WID (3) +#define DDR3_MODE_REGISTER_2_CWL_MSK (7) +#define DDR3_MODE_REGISTER_2_CWL_MAX (7) +#define DDR3_MODE_REGISTER_2_CWL_DEF (0) + +#define DDR3_MODE_REGISTER_2_ASR_OFF (6) +#define DDR3_MODE_REGISTER_2_ASR_WID (1) +#define DDR3_MODE_REGISTER_2_ASR_MSK (1) +#define DDR3_MODE_REGISTER_2_ASR_MAX (1) +#define DDR3_MODE_REGISTER_2_ASR_DEF (0) + +#define DDR3_MODE_REGISTER_2_STR_OFF (7) +#define DDR3_MODE_REGISTER_2_STR_WID (1) +#define DDR3_MODE_REGISTER_2_STR_MSK (1) +#define DDR3_MODE_REGISTER_2_STR_MAX (1) +#define DDR3_MODE_REGISTER_2_STR_DEF (0) + +#define DDR3_MODE_REGISTER_2_Rtt_WR_OFF (9) +#define DDR3_MODE_REGISTER_2_Rtt_WR_WID (2) +#define DDR3_MODE_REGISTER_2_Rtt_WR_MSK (3) +#define DDR3_MODE_REGISTER_2_Rtt_WR_MAX (3) +#define DDR3_MODE_REGISTER_2_Rtt_WR_DEF (0) + +/// +/// MR3 register +/// +#define DDR3_MODE_REGISTER_3_MPR_LOC_OFF (0) +#define DDR3_MODE_REGISTER_3_MPR_LOC_WID (2) +#define DDR3_MODE_REGISTER_3_MPR_LOC_MSK (3) +#define DDR3_MODE_REGISTER_3_MPR_LOC_MAX (3) +#define DDR3_MODE_REGISTER_3_MPR_LOC_DEF (0) + +#define DDR3_MODE_REGISTER_3_MPR_OFF (2) +#define DDR3_MODE_REGISTER_3_MPR_WID (1) +#define DDR3_MODE_REGISTER_3_MPR_MSK (1) +#define DDR3_MODE_REGISTER_3_MPR_MAX (1) +#define DDR3_MODE_REGISTER_3_MPR_DEF (0) + +#pragma pack (pop) +#endif diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcGlobal.h b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcGlobal.h new file mode 100644 index 0000000..0264c6a --- /dev/null +++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcGlobal.h @@ -0,0 +1,993 @@ +/** @file + This file includes all the data structures that the MRC considers "global data". + +@copyright + Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved. + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +**/ +#ifndef _MrcGlobal_h_ +#define _MrcGlobal_h_ +#pragma pack (push, 1) + +#include "MrcTypes.h" +#include "MrcApi.h" +#include "MrcOemDebugPrint.h" +#include "MrcRmtData.h" +#include "MrcSpdData.h" +#include "McAddress.h" + +/// +///*************************************************** +/// Structures common to all "global data" elements. +///*************************************************** +/// +typedef U8 MrcIteration; +#define MRC_ITERATION_MAX ((1 << ((sizeof (MrcIteration) * 8) - 1)) + ((1 << ((sizeof (MrcIteration) * 8) - 1)) - 1)) + +#define MRC_NUMBER_UPM_PWR_RETRAIN_MARGINS (9) + +typedef struct { + /// + ///< Thermal Options + /// + U8 EnableExtts; + U8 EnableCltm; + U8 EnableOltm; + U8 EnablePwrDn; +#ifdef ULT_FLAG + U8 EnablePwrDnLpddr; +#endif // ULT_FLAG + U8 Refresh2X; + U8 LpddrThermalSensor; + U8 LockPTMregs; + U8 UserPowerWeightsEn; + + U8 EnergyScaleFact; + U8 RaplPwrFl[MAX_CHANNEL]; + + U8 RaplLim2Lock; + U8 RaplLim2WindX; + U8 RaplLim2WindY; + U8 RaplLim2Ena; + U16 RaplLim2Pwr; + U8 RaplLim1WindX; + U8 RaplLim1WindY; + U8 RaplLim1Ena; + U16 RaplLim1Pwr; + + U8 WarmThreshold[MAX_CHANNEL][MAX_DIMMS_IN_CHANNEL]; + U8 HotThreshold[MAX_CHANNEL][MAX_DIMMS_IN_CHANNEL]; + U8 WarmBudget[MAX_CHANNEL][MAX_DIMMS_IN_CHANNEL]; + U8 HotBudget[MAX_CHANNEL][MAX_DIMMS_IN_CHANNEL]; + + U8 IdleEnergy[MAX_CHANNEL][MAX_DIMMS_IN_CHANNEL]; + U8 PdEnergy[MAX_CHANNEL][MAX_DIMMS_IN_CHANNEL]; + U8 ActEnergy[MAX_CHANNEL][MAX_DIMMS_IN_CHANNEL]; + U8 RdEnergy[MAX_CHANNEL][MAX_DIMMS_IN_CHANNEL]; + U8 WrEnergy[MAX_CHANNEL][MAX_DIMMS_IN_CHANNEL]; + U8 SrefCfgEna; + U16 SrefCfgIdleTmr; + U8 ThrtCkeMinDefeat; + U8 ThrtCkeMinTmr; +#ifdef ULT_FLAG + U8 ThrtCkeMinDefeatLpddr; + U8 ThrtCkeMinTmrLpddr; +#endif // ULT_FLAG +#ifdef UPSERVER_SUPPORT + // CLTM and TSOD settings + U8 Altitude; + U8 UserThresholdEn; + U8 UserBudgetEn; + U8 TSOD_TcritMax; + U8 TSOD_EventMode; + U8 TSOD_EventPolarity; + U8 TSOD_CriticalEventOnly; + U8 TSOD_EventOutputControl; + U8 TSOD_AlarmwindowLockBit; + U8 TSOD_CriticaltripLockBit; + U8 TSOD_ShutdownMode; + U8 TSOD_ThigMax; + U8 TSOD_ManEn; + +#endif +} ThermalMngmtEn; + + +typedef struct { + MrcBool GdxcEnable; ///< GDXC MOT enable + U8 GdxcIotSize; ///< IOT size in multiples of 8MEG + U8 GdxcMotSize; ///< MOT size in multiples of 8MEG +} MrcGdxc; + +typedef struct { + U32 ECT : 1; ///< BIT0 - Early Command Training + U32 SOT : 1; ///< BIT1 - Sense Amp Offset Training + U32 RDMPRT : 1; ///< BIT2 - Read MPR Training + U32 RCVET : 1; ///< BIT3 - Read Leveling Training (RcvEn) + U32 JWRL : 1; ///< BIT4 - Jedec Write Leveling + U32 FWRL : 1; ///< BIT5 - Functional Write Leveling + U32 WRTC1D : 1; ///< BIT6 - Write Timing Centerin 1D + U32 RDTC1D : 1; ///< BIT7 - Read Timing Centering 1D + U32 DIMMODTT : 1; ///< BIT8 - Dimm ODT Training + U32 WRDST : 1; ///< BIT9 - Write Drive Strength Training + U32 WREQT : 1; ///< BIT10 - Write Equalization Training + U32 RCVENC1D: 1; ///< BIT11 - Receive Enable Centering 1D + U32 RDODTT : 1; ///< BIT12 - Read ODT Training + U32 RDEQT : 1; ///< BIT13 - Read Equalization Training + U32 RDAPT : 1; ///< BIT14 - Read Amplifier Power Training + U32 WRTC2D : 1; ///< BIT15 - Write Timing Centerin 2D + U32 RDTC2D : 1; ///< BIT16 - Read Timing Centering 2D + U32 CMDVC : 1; ///< BIT17 - Command Voltage Centering + U32 WRVC2D : 1; ///< BIT18 - Write Voltage Centering 2D + U32 RDVC2D : 1; ///< BIT19 - Read Voltage Centering 2D + U32 RMC : 1; ///< BIT20 - Retrain Margin Check + U32 : 1; ///< BIT21 - + U32 LCT : 1; ///< BIT22 - Late Command Training + U32 RTL : 1; ///< BIT23 - Round Trip latency + U32 TAT : 1; ///< BIT24 - Turn Around Timing + U32 RMT : 1; ///< BIT25 - RMT Tool + U32 MEMTST : 1; ///< BIT26 - Memory Test + U32 DIMMODTT1D : 1; ///< BIT27 - DIMMODTT1d + U32 WRSRT : 1; ///< BIT28 - Write Slew Rate Training + U32 DIMMRONT : 1; ///< BIT29 - Dimm Ron Training + U32 ALIASCHK: 1; ///< BIT30 - SPD Alias Check +} TrainingStepsEn; + +typedef enum { + MrcModeFull, + MrcModeMini +} MrcMode; + +typedef enum { + LastRxV, + LastRxT, + LastTxV, + LastTxT, + LastRcvEna, + LastWrLevel, + LastCmdT, + LastCmdV, + MAX_RESULT_TYPE +} MrcMarginResult; + +/// +/// Define the MRC recommended boot modes. +/// +typedef enum { + bmCold, ///< Cold boot + bmWarm, ///< Warm boot + bmS3, ///< S3 resume + bmFast, ///< Fast boot +} MrcBootMode; + +/// +/// DIMM SPD Security Status +/// +typedef enum { + MrcSpdStatusGood, ///< Memory is in a secure state. + MrcSpdStatusAliased, ///< Memory is aliased. + + MrcSpdStatusLast ///< Must be last in the list +} MrcSpdStatus; + +/// +/// Define the virtual channel. +/// +typedef enum { + vcA, ///< Virtual channel A + vcB, ///< Virtual channel B +} MrcVirtualChannel; + +/// +/// Define the board types. +/// +typedef enum { + btCRBMB, ///< 0 - CRB Mobile + btCRBDT, ///< 1 - CRB Desktop + btUser1, ///< 2 - SV mobile + btUser2, ///< 3 - SV desktop + btUser3, ///< 4 - SV server? + btUser4, ///< 5 - Ult + btCRBEMB, ///< 6 - CRB Embedded + btUnknown, ///< 7 - Unknown +} MrcBoardType; + +/// +/// Define the CPU family/model. +/// +typedef enum { + cmHSW = 0x306C0, ///< Haswell + cmHSW_ULT = 0x40650, ///< Haswell-ULT + cmCRW = 0x40660, ///< Crystalwell + cmBDW = 0x306D0 ///< Broadwell +} MrcCpuModel; + +/// +/// Define the CPU stepping number. +/// +typedef enum { + /// + /// Haswell + /// + csHswA0 = 1, + csHswB0 = 2, + csHswC0 = 3, + csHswLast = csHswC0, + + /// + /// Crystalwell + /// + csCrwB0 = 0, + csCrwC0 = 1, + csCrwLast = csCrwC0, + + /// + /// Haswell-ULT + /// + csHswUltB0 = 0, + csHswUltC0 = 1, + csHswUltLast = csHswUltC0, + + /// + /// Broadwell + /// + csBdwA0 = 0, + csBdwLast = csBdwA0 +} MrcCpuStepping; + +typedef enum { + CONTROLLER_NOT_PRESENT, ///< There is no controller present in the system. + CONTROLLER_DISABLED, ///< There is a controller present but it is disabled. + CONTROLLER_PRESENT ///< There is a controller present and it is enabled. +} MrcControllerSts; + +typedef enum { + CHANNEL_NOT_PRESENT, ///< There is no channel present on the controller. + CHANNEL_DISABLED, ///< There is a channel present but it is disabled. + CHANNEL_PRESENT ///< There is a channel present and it is enabled. +} MrcChannelSts; + +typedef enum { + DIMM_ENABLED, ///< DIMM/rank Pair is enabled, presence TBD + DIMM_DISABLED, ///< DIMM/rank Pair is disabled, regardless of presence. + DIMM_PRESENT, ///< There is a DIMM present in the slot/rank pair and it will be used. + DIMM_NOT_PRESENT ///< There is no DIMM present in the slot/rank pair. +} MrcDimmSts; + +typedef enum { + STD_PROFILE, ///< Standard DIMM profile select. + USER_PROFILE, ///< User specifies various override values. + XMP_PROFILE1, ///< XMP enthusiast settings select (XMP profile #1). + XMP_PROFILE2, ///< XMP extreme settings select (XMP profile #2). + MAX_PROFILE ///< Delimiter +} MrcProfile; + +typedef enum { + MRC_REF_CLOCK_133, + MRC_REF_CLOCK_100, + MRC_REF_CLOCK_MAXIMUM ///< Delimiter +} MrcRefClkSelect; ///< This value times the MrcClockRatio determines the MrcFrequency. + +typedef U32 MrcBClkRef; + +typedef enum { + MRC_DDR_TYPE_UNKNOWN, + MRC_DDR_TYPE_DDR3, + MRC_DDR_TYPE_LPDDR3 +} MrcDdrType; + +typedef enum { + MRC_MODULE_TYPE_UNKNOWN, + MRC_MODULE_TYPE_RDIMM, + MRC_MODULE_TYPE_UDIMM, + MRC_MODULE_TYPE_SODIMM, + MRC_MODULE_MICRO_DIMM, + MRC_MODULE_MINI_RDIMM, + MRC_MODULE_MINI_UDIMM, + MRC_MODULE_MINI_CDIMM, + MRC_MODULE_72B_SO_UDIMM, + MRC_MODULE_72B_SO_RDIMM, + MRC_MODULE_72B_SO_CDIMM, + MRC_MODULE_LRDIMM, + MRC_MODULE_16B_SO_DIMM, + MRC_MODULE_32B_SO_DIMM +} MrcModuleType; + +typedef enum { + MrcIterationClock = 0, + MrcIterationCmdN = 1, + MrcIterationCmdS = 2, + MrcIterationCke = 3, + MrcIterationCtl = 4, + MrcIterationCmdV = 5, + MrcIterationMax +} MrcIterationType; + +typedef enum { + UpmLimit, + PowerLimit, + RetrainLimit, + MarginLimitMax +} MRC_MARGIN_LIMIT_TYPE; + +typedef U8 MrcClockRatio; ///< This value times the MrcRefClkSelect determines the MrcFrequency. +typedef U32 MrcGfxDataSize; ///< The size of the stolen graphics data memory, in MBytes. +typedef U32 MrcGfxGttSize; ///< The size of the graphics translation table, in MBytes. + +/// +/// UPM PWR and Retrain Limits +/// +typedef struct { + U8 Param; + U16 ParamLimit[MarginLimitMax]; +} MrcUpmPwrRetrainLimits; + +typedef union { + MrcUpmPwrRetrainLimits *Pointer; + U64 Data; +} MrcUPRLimitPtr; + +typedef union { + U64 Data; + U32 Data32[2]; +} MrcCapId; ///< The memory controller capabilities. + +/// +/// MRC version description. +/// +typedef struct { + U8 Major; ///< Major version number + U8 Minor; ///< Minor version number + U8 Rev; ///< Revision number + U8 Build; ///< Build number +} MrcVersion; + +/// +/// Memory map configuration information. +/// +typedef struct { + U32 TomMinusMe; + U32 ToludBase; + U32 BdsmBase; + U32 GttBase; + U32 GraphicsControlRegister; + U32 TsegBase; + MrcBool ReclaimEnable; + U32 RemapBase; + U32 RemapLimit; + U32 TouudBase; + U32 TotalPhysicalMemorySize; + U32 MeStolenBase; + U32 MeStolenSize; + U32 GdxcMotBase; + U32 GdxcMotSize; + U32 GdxcIotBase; + U32 GdxcIotSize; + U32 DprSize; + U32 FtpmStolenBase; +} MrcMemoryMap; + +/// +/// Real time clock information. +/// +typedef struct { + U8 Seconds; + U8 Minutes; + U8 Hours; + U8 DayOfMonth; + U8 Month; + U16 Year; +} MrcBaseTime; + +/// +/// DIMM timings +/// +typedef struct { + U32 tCK; ///< Memory cycle time, in femtoseconds. + U16 NMode; ///< Number of tCK cycles for the channel DIMM's command rate mode. + U16 tCL; ///< Number of tCK cycles for the channel DIMM's CAS latency. + U16 tCWL; ///< Number of tCK cycles for the channel DIMM's minimum CAS write latency time. + U16 tFAW; ///< Number of tCK cycles for the channel DIMM's minimum four activate window delay time. + U16 tRAS; ///< Number of tCK cycles for the channel DIMM's minimum active to precharge delay time. + U16 tRC; ///< Number of tCK cycles for the channel DIMM's minimum active to active/refresh delay time. + U16 tRCD; ///< Number of tCK cycles for the channel DIMM's minimum RAS# to CAS# delay time. + U16 tREFI; ///< Number of tCK cycles for the channel DIMM's minimum Average Periodic Refresh Interval. + U16 tRFC; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time. + U16 tRFC2; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time. + U16 tRFC4; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time. + U16 tRP; ///< Number of tCK cycles for the channel DIMM's minimum row precharge delay time. + U16 tRPab; ///< Number of tCK cycles for the channel DIMM's minimum row precharge delay time for all banks. + U16 tRRD; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time. + U16 tRRD_L; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for same bank groups. + U16 tRRD_S; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for different bank groups. + U16 tRTP; ///< Number of tCK cycles for the channel DIMM's minimum internal read to precharge command delay time. + U16 tWR; ///< Number of tCK cycles for the channel DIMM's minimum write recovery time. + U16 tWTR; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time. +} MrcTiming; + +typedef struct { + S32 Mtb; ///< Medium time base. + S32 Ftb; ///< Fine time base. +} MrcTimeBase; + +typedef struct { + U8 Left; ///< The left side of the timing eye. + U8 Center; ///< The center of the timing eye. + U8 Right; ///< The right side of the timing eye. +} MrcDqTimeMargin; + +typedef struct { + U8 High; ///< The high side of the Vref eye. + U8 Center; ///< The center of the Vref eye. + U8 Low; ///< The low side of the Vref eye. +} MrcDqVrefMargin; + +typedef struct { + U8 Left; ///< The left side of the command eye. + U8 Right; ///< The right side of the command eye. + U8 High; ///< The high side of the command eye. + U8 Low; ///< The low side of the command eye. +} MrcCommandMargin; + +typedef struct { + U8 Left; ///< The left side of the receive enable eye. + U8 Right; ///< The right side of the receive enableeye. +} MrcRecvEnMargin; + +typedef struct { + U8 Left; ///< The left side of the write leveling eye. + U8 Right; ///< The right side of the write leveling eye. +} MrcWrLevelMargin; + +#ifdef SSA_FLAG +typedef struct { + U8 *BufBase; + U32 BufLimit; + union { + struct { + U8 Occupied : 1; + U8 HeapEnd : 1; + } Bits; + U8 Data; + } BufFlags; +} HeapBufHeader; +#endif // SSA_FLAG + +#if ((defined SSA_FLAG) || (defined MRC_DEBUG_PRINT)) +typedef union { + struct { + U8 Init : 1; ///< 1 is SSA heap initialized. + U8 : 7; + } Bits; + U8 Data; + } SsaHeapFlagType; +#endif + +/// +///***************************************** +/// Output related "global data" structures. +///***************************************** +/// +/// This data structure contains all the "global data" values that are considered output by the MRC. +/// The following are SDRAM level definitions. All ranks on a rank are set to these values. +/// +/* Commented out until needed, in order to save space. +typedef struct { +} MrcSdramOut; +*/ + +/// +/// This data structure contains all the "global data" values that are considered output by the MRC. +/// The following are rank level definitions. All ranks on a DIMM are set to these values. +/// +typedef struct { +//MrcSdramOut Sdram[MAX_SDRAM_IN_DIMM]; + U16 MR[MAX_MR_IN_DIMM]; ///< DRAM mode register value. +#ifdef ULT_FLAG + U16 MR11; ///< LPDDR3 ODT MR +#endif +} MrcRankOut; + +/// +/// This data structure contains all the "global data" values that are considered output by the MRC. +/// The following are DIMM level definitions. All ranks on a DIMM are set to these values. +/// +typedef struct { + MrcDimmSts Status; ///< See MrcDimmSts for the definition of this field. + MrcTiming Timing[MAX_PROFILE]; ///< The DIMMs timing values. + MrcVddSelect VddVoltage[MAX_PROFILE];///< The voltage (VDD) setting for this DIMM, per profile. + MrcBool EccSupport; ///< TRUE if ECC is enabled and supported on this DIMM. + MrcBool IgnoreNonEccDimm; ///< TRUE if a DIMM without ECC capability should be ignored. + MrcBool AddressMirrored; ///< TRUE if the DIMM is address mirrored. + MrcBool SelfRefreshTemp; ///< TRUE if the DIMM supports self refresh extended operating temperature range (SRT). + MrcBool AutoSelfRefresh; ///< TRUE if the DIMM supports automatic self refresh (ASR). + MrcBool PartialSelfRefresh; ///< TRUE if the DIMM supports Partial Array Self Refresh (PASR). + MrcBool OnDieThermalSensor; ///< TRUE if the DIMM supports On-die Thermal Sensor (ODTS) Readout. + MrcBool ExtendedTemperRange; ///< TRUE if the DIMM supports Extended Temperature Range (ETR). + MrcBool ExtendedTemperRefresh; ///< TRUE if the DIMM supports 1x Extended Temperature Refresh rate, FALSE = 2x. + MrcDdrType DdrType; ///< DDR type: DDR3 or LPDDR3 + MrcModuleType ModuleType; ///< Module type: UDIMM, SO-DIMM, etc. + U32 SdramCount; ///< The number of SDRAM components on a DIMM. + U32 DimmCapacity; ///< DIMM size in MBytes. + U32 RowSize; ///< The DIMMs row address size. + U16 ColumnSize; ///< The DIMMs column address size. + U16 Crc; ///< Calculated CRC16 of the DIMM's provided SPD. Can be used to detect DIMM change. + U8 RankInDIMM; ///< The number of ranks in this DIMM. + U8 Banks; ///< Number of banks the DIMM contains. + U8 BankGroups; ///< Number of bank groups the DIMM contains. + U8 PrimaryBusWidth; ///< DIMM primary bus width. + U8 SdramWidth; ///< DIMM SDRAM width. + U8 SdramWidthIndex; ///< DIMM SDRAM width index (0 = x4, 1 = x8, 2 = x16, 3 = x32). + U8 DensityIndex; ///< Total SDRAM capacity index (0 = 256Mb, 1 = 512Mb, 2 = 1Gb, etc). + U8 ReferenceRawCard; ///< Indicates which JEDEC reference design raw card was used as the basis for the module assembly. + U8 XmpSupport; ///< Indicates if XMP profiles are supported. 0 = None, 1 = XMP1 only, 2 = XMP2 only, 3 = All. + U8 XmpRevision; ///< Indicates the XMP revision of this DIMM. 0 = None, 12h = 1.2, 13h = 1.3. + MrcRankOut Rank[MAX_RANK_IN_DIMM]; +} MrcDimmOut; + +/// +/// This data structure contains all the "global data" values that are considered output by the MRC. +/// The following are channel level definitions. All DIMMs on a memory channel are set to these values. +/// +typedef struct { + MrcChannelSts Status; ///< Indicates whether this channel should be used. + MrcVirtualChannel VirtualChannel; ///< define the virtual channel type A or B. + MrcTiming Timing[MAX_PROFILE]; ///< The channel timing values. + MrcTimeBase TimeBase[MAX_DIMMS_IN_CHANNEL][MAX_PROFILE]; + MrcBool EccSupport; ///< TRUE if ECC is enabled and supported on this channel. + U32 Capacity; ///< Amount of memory in this channel, in MBytes. + U32 DimmCount; ///< Number of valid DIMMs that exist in the channel. + U32 DataOffsetTrain[MAX_SDRAM_IN_DIMM];///< DataOffsetTrain CR + U32 DataCompOffset[MAX_SDRAM_IN_DIMM]; ///< DataCompOffset CR + DDRDATA0CH0_CR_DDRCRDATACONTROL0_STRUCT DqControl0; ///< DqControl0 CR + DDRDATA0CH0_CR_DDRCRDATACONTROL1_STRUCT DqControl1[MAX_SDRAM_IN_DIMM]; ///< DqControl1 CR + DDRDATA0CH0_CR_DDRCRDATACONTROL2_STRUCT DqControl2[MAX_SDRAM_IN_DIMM]; ///< DqControl2 CR + U32 CkeCmdPiCode[2]; ///< CKE CmdPiCode CR, per group + U32 CmdsCmdPiCode[2]; ///< CmdS CmdPiCode CR, per group + U32 CmdnCmdPiCode[2]; ///< CmdN CmdPiCode CR, per group + U32 MchbarBANK; ///< tRCD tRP tRAS tRDPRE (tRTP) tWRPRE and tRRD values. + U32 MchbarBANKRANKA; ///< Mchbar TC Read to Read Turnaround CR + U32 MchbarBANKRANKB; ///< Mchbar TC Write to x Turnaround CR + U32 MchbarBANKRANKC; ///< Mchbar TC Read to Write Turnaround CR + U32 MchbarBANKRANKD; ///< Mchbar TC Write /Read Duration + U32 TxXtalk[MAX_SDRAM_IN_DIMM]; ///< TxXtalk Setting + U16 TxDqs[MAX_RANK_IN_CHANNEL][MAX_SDRAM_IN_DIMM]; ///< TxDQS PI Code + U16 TxDq[MAX_RANK_IN_CHANNEL][MAX_SDRAM_IN_DIMM]; ///< TxDQ Pi Code + U16 RcvEn[MAX_RANK_IN_CHANNEL][MAX_SDRAM_IN_DIMM]; ///< RcvEn PI Code + U16 WlDelay[MAX_RANK_IN_CHANNEL][MAX_SDRAM_IN_DIMM]; + U8 ClkPiCode[MAX_RANK_IN_CHANNEL]; ///< CLK ClkPiCode + U8 CtlPiCode[MAX_RANK_IN_CHANNEL]; ///< CTL CtlPiCode + U8 CkePiCode[MAX_RANK_IN_CHANNEL]; ///< CKE CtlPiCode + U8 TxEq[MAX_RANK_IN_CHANNEL][MAX_SDRAM_IN_DIMM]; ///< TxEq Setting + MrcCommandMargin Command[MAX_RANK_IN_CHANNEL]; + MrcDqTimeMargin RxDqPb[MAX_RANK_IN_CHANNEL][MAX_SDRAM_IN_DIMM][MAX_BITS]; ///< Rx PerBit Pi Code + MrcDqTimeMargin TxDqPb[MAX_RANK_IN_CHANNEL][MAX_SDRAM_IN_DIMM][MAX_BITS]; ///< Tx PerBit Pi Code + MrcDqVrefMargin RxDqVrefPb[MAX_RANK_IN_CHANNEL][MAX_SDRAM_IN_DIMM][MAX_BITS]; ///< Rx PerBit Vref + MrcDqVrefMargin TxDqVrefPb[MAX_RANK_IN_CHANNEL][MAX_SDRAM_IN_DIMM][MAX_BITS]; ///< Rx PerBit Vref + MrcRecvEnMargin ReceiveEnable[MAX_RANK_IN_CHANNEL]; ///< Receive enable per rank + MrcWrLevelMargin WriteLevel[MAX_RANK_IN_CHANNEL]; ///< Write leveling per rank + U8 IoLatency[MAX_RANK_IN_CHANNEL]; ///< IOLatency + U8 RTLatency[MAX_RANK_IN_CHANNEL]; ///< RoundTripLatency + U32 RTIoComp; ///< RoundTrip IO Compensation of the Channel + U8 RxVref[MAX_SDRAM_IN_DIMM]; ///< RX Vref in steps of 7.9 mv + U8 RxEq[MAX_RANK_IN_CHANNEL][MAX_SDRAM_IN_DIMM]; ///< RxEQ Setting + U8 RxDqsP[MAX_RANK_IN_CHANNEL][MAX_SDRAM_IN_DIMM];/// RxDQSP PI Code + U8 RxDqsN[MAX_RANK_IN_CHANNEL][MAX_SDRAM_IN_DIMM];/// RxDQSN PI Code + U8 RankInChannel; ///< Number of valid ranks that exist in the channel. + U8 ValidRankBitMask; ///< Bit map of the populated ranks per channel + U8 ValidCkeBitMask; ///< Bit map of the used CKE pins per channel + MrcDimmOut Dimm[MAX_DIMMS_IN_CHANNEL]; +} MrcChannelOut; + +/// +/// This data structure contains all the "global data" values that are considered output by the MRC. +/// The following are memory controller level definitions. All channels on a controller are set to these values. +/// +typedef struct { + MrcControllerSts Status; ///< Indicates whether this controller should be used. + U16 DeviceId; ///< The PCI device id of this memory controller. + U8 RevisionId; ///< The PCI revision id of this memory controller. + U8 ChannelCount; ///< Number of valid channels that exist on the controller. + MrcChannelOut Channel[MAX_CHANNEL]; ///< The following are channel level definitions. +} MrcControllerOut; + +/// +/// This data structure contains all the "DDR power saving data" values that are considered output by the MRC. +/// The following are memory controller level definitions. All channels on a controller are set to these values. +/// +typedef struct { + BOOL BaseFlag; ///< Indicates if the base line of power was already calculated. + U16 BaseSavingRd; ///< Indicates the base line of power consume by the ddr on read. + U16 BaseSavingWr; ///< Indicates the base line of power consume by the ddr on write. + U16 BaseSavingCmd; ///< Indicates the base line of power consume by the ddr on command. + U16 MrcSavingRd; ///< Indicates the power consume by the ddr on read at the end of MRC. + U16 MrcSavingWr; ///< Indicates the power consume by the ddr on write at the end of MRC. + U16 MrcSavingCmd; ///< Indicates the power consume by the ddr on command at the end of MRC. +} MrcOdtPowerSaving; + +/// +/// This data structure contains all the "global data" values that are considered output by the MRC. +/// The following are system level definitions. All memory controllers in the system are set to these values. +/// +typedef struct { + MrcVersion Version; ///< The memory reference code version. + MrcFrequency FreqMax; ///< The requested maximum valid frequency. + MrcFrequency Frequency; ///< The system's common memory controller frequency. + U32 MemoryClockMax; ///< The system's common memory controller maximum clock, in femtoseconds. + U32 MemoryClock; ///< The system's common memory controller clock, in femtoseconds. + MrcRefClkSelect RefClk; ///< The memory controller is going to use this reference clock. + MrcClockRatio Ratio; ///< Request for this memory controller to use this clock ratio. + MrcBootMode BootMode; ///< The system's common memory controller boot mode. + MrcMemoryMap MemoryMapData; ///< The system's memory map data. + MrcGfxDataSize GraphicsStolenSize; ///< Graphics Data Stolen Memory size in MB + MrcGfxGttSize GraphicsGttSize; ///< GTT graphics stolen memory size in MB + MrcVddSelect VddVoltage[MAX_PROFILE]; ///< The currently running voltage (VDD) setting for all DIMMs in the system, per profile. + MrcGdxc Gdxc; ///< GDXC enable and size. + MrcBool VddVoltageDone; ///< To determine if VddVoltageDone update has been done already + MrcBool EccSupport; ///< TRUE if ECC is enabled and supported on this controller. + MrcBool EnDumRd; ///< Enable/Disable Logic Analizer + MrcBool RestoreMRs; ///< Enable/Disable restoring + MrcBool AsyncOdtDis; ///< Enable Asyncronous ODT + MrcBool LpddrEctDone; ///< Set to TRUE once Early Command Training on LPDDR is done, and we can run JEDEC Init + MrcBool LpddrJedecInitDone; ///< Set to TRUE once JEDEC Init on LPDDR is done + MrcBool XmpProfileEnable; ///< XMP capable DIMMs detected in system (0 = no, 1 = yes). + MrcBool Capable100; ///< The MC is capable of 100 reference clock (0 = no, 1 = yes). + MrcBool AutoSelfRefresh; ///< Indicates ASR is supported for all the DIMMS for 2xRefresh + MrcDdrType DdrType; ///< Current memory type: DDR3 or LPDDR3 + MrcSpdStatus SpdSecurityStatus; ///< Status variable to inform BIOS that memory contains an alias. + U32 MrcTotalChannelLimit; ///< The maximum allowed memory size per channel, in MBytes. + U8 SdramCount; ///< The number of SDRAM components on a DIMM. + U32 CompCtl0; ///< CompCtl0 CR + U32 CompCtl1; ///< CompCtl1 CR + U32 DimmVref; ///< DimmVref CR + U32 MiscControl0; ///< MiscCOntrol0 CR + U16 Qclkps; ///< Qclk period in pS + U8 DQPat; ///< Global Variables storing the current DQPat REUT Test + S8 DQPatLC; ///< Global Variables storing the current DQPat Loopcount + U8 ValidRankMask; ///< Rank bit map - includes both channels + U8 ValidChBitMask; ///< Channel bit map of the populated channels + MrcUPRLimitPtr UpmPwrRetrainLimits; ///< Pointer to Global UPM/PWR/RETRAIN Limits on the stack the size of MRC_NUMBER_UPM_PWR_RETRAIN_MARGINS + U32 MarginResult[MAX_RESULT_TYPE][MAX_RANK_IN_CHANNEL][MAX_CHANNEL][MAX_SDRAM_IN_DIMM][MAX_EDGES]; ///< Stores last margin measurement. + MrcControllerOut Controller[MAX_CONTROLLERS]; + MrcOdtPowerSaving OdtPowerSavingData; +#ifdef UPSERVER_SUPPORT + U16 CLTM_SPD_Conf; ///< CLTM SPD Configuration Done(0 = process not executed, 0xFF = process failed, XX = process save CLTM_SPD_Conf +#endif ///< CLTM_SPD_Conf = h=2xRefreshState i = Density , j = Frequency , k1 = Adjacent DIMM prescence in Channel 1, k0 = Adjacent DIMM prescence in Channel 0 +} MrcOutput; + +/// +///**************************************** +/// Input related "global data" structures. +///**************************************** +/// +/// This data structure contains all the "global data" values that are considered input by the MRC. +/// The following are SDRAM level definitions. All ranks on a rank are set to these values. +/// +/* Commented out until needed, in order to save space. +typedef struct { + U8 Placeholder; ///< TODO: Is there anything that needs to go in here? +} MrcSdramIn; +*/ + +/// +/// This data structure contains all the "global data" values that are considered input by the MRC. +/// The following are rank level definitions. All ranks on a DIMM are set to these values. +/// +/* Commented out until needed, in order to save space. +typedef struct { + MrcSdramIn Sdram[MAX_SDRAM_IN_DIMM]; +} MrcRankIn; +*/ + +/// +/// This data structure contains all the "global data" values that are considered input by the MRC. +/// The following are DIMM level definitions. All ranks on a DIMM are set to these values. +/// +typedef struct { + MrcDimmSts Status; ///< Indicates whether this DIMM should be used. + U8 SpdValid[sizeof (MrcSpd) / (CHAR_BITS * sizeof (U8))]; ///< Each valid bit maps to SPD byte. + MrcSpd Spd; ///< The SPD data for each DIMM. SPDGeneral field = 0 when absent. + MrcTiming Timing; ///< The DIMMs requested timing overrides. + U8 SpdAddress; ///< The SMBus address for the DIMM's SPD data. +//MrcRankIn Rank[MAX_RANK_IN_DIMM]; +} MrcDimmIn; + +/// +/// This data structure contains all the "global data" values that are considered input by the MRC. +/// The following are channel level definitions. All DIMMs on a memory channel are set to these values. +/// +typedef struct { + MrcChannelSts Status; ///< Indicates whether this channel should be used. + U32 DimmCount; ///< The maximum number of DIMMs on this channel. + MrcDimmIn Dimm[MAX_DIMMS_IN_CHANNEL]; +#ifdef ULT_FLAG + U8 DqsMapCpu2Dram[8]; ///< Mapping from CPU DQS pins to SDRAM DQS pins + U8 DqMapCpu2Dram[8][MAX_BITS]; ///< Mapping from CPU DQ pins to SDRAM DQ pins + U8 DQByteMap[MrcIterationMax][2]; ///< Maps which PI clocks are used by what LPDDR DQ Bytes (from CPU side), per group + ///< DQByteMap[0] - ClkDQByteMap: + ///< If clock is per rank, program to [0xFF, 0xFF] + ///< If clock is shared by 2 ranks, program to [0xFF, 0] or [0, 0xFF] + ///< If clock is shared by 2 ranks but does not go to all bytes, + ///< Entry[i] defines which DQ bytes Group i services + ///< DQByteMap[1] - CmdNDQByteMap: Entry[0] is CmdN/CAA and Entry[1] is CmdN/CAB + ///< DQByteMap[2] - CmdSDQByteMap: Entry[0] is CmdS/CAA and Entry[1] is CmdS/CAB + ///< DQByteMap[3] - CkeDQByteMap : Entry[0] is CKE /CAA and Entry[1] is CKE /CAB + ///< For DDR, DQByteMap[3:1] = [0xFF, 0] + ///< DQByteMap[4] - CtlDQByteMap : Always program to [0xFF, 0] since we have 1 CTL / rank + ///< Variable only exists to make the code easier to use + ///< DQByteMap[5] - CmdVDQByteMap: Always program to [0xFF, 0] since we have 1 CA Vref + ///< Variable only exists to make the code easier to use +#endif // ULT_FLAG +} MrcChannelIn; + +/// +/// This data structure contains all the "global data" values that are considered input by the MRC. +/// The following are memory controller level definitions. All channels on a controller are set to these values. +/// +typedef struct { + MrcControllerSts Status; ///< Indicates whether this controller should be used. + U8 ChannelCount; ///< Number of valid channels that are requested on the controller. + MrcChannelIn Channel[MAX_CHANNEL]; ///< The following are channel level definitions. +} MrcControllerIn; + +/// +/// This data structure contains all the "global data" values that are considered input by the MRC. +/// The following are system level definitions. All memory controllers in the system are set to these values. +/// +typedef struct { + MrcDebug Debug; + MrcFrequency FreqMax; ///< The requested maximum valid frequency. + MrcClockRatio Ratio; ///< Request for this memory controller to use this clock ratio. + MrcRefClkSelect RefClk; ///< Request for this memory controller to use this reference clock. + MrcBClkRef BClkFrequency; ///< Base reference clock value, in Hertz. + MrcBoardType BoardType; ///< define the board type (CRBMB,CRBDT,User1,User2). the OEM can add more boards. + MrcCpuStepping CpuStepping; ///< define the CPU stepping. + MrcCpuModel CpuModel; ///< define the CPU model. + MrcGfxDataSize GraphicsStolenSize; ///< Graphics Data Stolen Memory size in MB + MrcGfxGttSize GraphicsGttSize; ///< GTT graphics stolen memory size in MB + MrcBaseTime BaseTime; ///< RTC base time. + MrcIteration Iteration; /// + MrcMode MrcMode; ///< The control for full or MiniBIOS MRC. + MrcVddSelect VddVoltage; ///< The requested voltage (VDD) setting. + MrcProfile MemoryProfile; ///< The memory profile requested to be used. + MrcBootMode BootMode; ///< The requested memory controller boot mode. + MrcBool TxtFlag; /// + MrcBool MobilePlatform; ///< define Mobile or Desktop platform. true is mobile. + MrcBool EccSupport; ///< Tell to the MRC if ECC supporting or not. if false the ecc will not be support even if the DIMM will support in ECC. + MrcBool SetRxDqs32; /// + MrcBool GfxIsVersatileAcceleration; ///< iGFX engines are in Versatile Acceleration + MrcBool ScramblerEnable; ///< Enable/Disable scrambling + MrcBool McLock; /// + MrcBool RemapEnable; /// + MrcBool AutoSelfRefreshSupport; ///< FALSE = No auto self refresh support, TRUE = auto self refresh support. + MrcBool ExtTemperatureSupport; ///< FALSE = No extended temperature support, TRUE = extended temperature support. + U32 SaMemCfgAddress; + U32 SaMemCfgSize; + U32 PciEBaseAddress; ///< define the PciE base address. + U32 MchBarBaseAddress; ///< define the MCH bar base address. + U32 SmbusBaseAddress; ///< This field defines the smbus base address. + U32 GdxcBaseAddress; ///< This field defines the GDXC base address. + U32 HpetBaseAddress; ///< This field defines the hpet base address. + U32 MeStolenSize; ///< define the size that the ME need in MB. + U32 MmioSize; ///< define the MMIO size in MB. + U32 TsegSize; ///< TSEG size that require by the system in MB. + U32 IedSize; ///< IED size that require by the system in MB. + U32 DprSize; ///< DPR size required by system in MB. + U32 VddSettleWaitTime; ///< The minimum time in nanoseconds to wait for VDD to settle after being changed. + U16 VccIomV; ///< VccIO logic voltage in mV. + U8 PowerDownMode; ///< Option to select No PD, APD or PPD-DLLoff + U8 PwdwnIdleCounter; ///< Option to select the power down Idle counter. + MrcBool RankInterleave; ///< Option to Enable Rank Interleave. + MrcBool EnhancedInterleave; ///< Option to Enable Enhanced Interleave. + MrcBool WeaklockEn; ///< Option to Enable Weaklock for CMD, CTL and CKE + U8 EnCmdRate; ///< Option to Enable and select the number of CMDs for 1.5NMode + MrcBool CmdTriStateDis; ///< Option to Disable cmd tri-state + MrcBool RefreshRate2x; ///< Tells the MRC to enable 2x Refresh. + MrcBool ChHashEnable; ///< Option to Enable Channel Hash. + U16 ChHashMask; ///< Option to select Address bits[19:6] to include in Channel XOR function. + U8 ChHashInterleaveBit; ///< Option to select interleave Address bit. Valid values are 0 - 3 for BITS 6 - 9. + ThermalMngmtEn ThermalEnables; ///< Options to Enable Thermal management settings + MrcControllerIn Controller[MAX_CONTROLLERS]; +#ifdef SSA_FLAG + U32 SsaCallbackPpi; +#endif // SSA_FLAG +#if ((defined SSA_FLAG) || (defined MRC_DEBUG_PRINT)) + U32 SsaHeapBase; ///< Starting address of the SSA services heap space. + U32 SsaHeapSize; ///< Size of the SSA services heap space, in bytes. + SsaHeapFlagType SsaHeapFlag; ///< Bit 0 = 1 is SSA heap initialized, all other bits reserved. +#endif + MrcGdxc Gdxc; ///< GDXC enable and size. + MrcBool MemoryTrace; ///< Option to Enable Memory Trace to second DDR channel using Stacked Mode + TrainingStepsEn TrainingEnables; ///< Options to Enable individual training steps + MrcBool OemCleanMemory; ///< TRUE to request a memory clean + MrcBool RmtBdatEnable; ///< Option to enable output of training results into BDAT. +#ifdef ULT_FLAG + MrcBool DqPinsInterleaved; ///< Interleaving mode of DQ/DQS pins - depends on board routing + MrcBool LpddrDramOdt; ///< TRUE if LPDDR DRAM ODT is used - depends on board design + U8 CkeRankMapping; ///< [3:0] - Channel 0, [7:4] - Channel 1. + ///< Bit [i] specifies which rank CKE[i] goes to. +#endif + U8 MaxRttWr; ///< Maximum DIMM RTT_WR to use in power training 0 = Off, 1 = 120 ohms +} MrcInput; + +/// +///******************************************** +/// Saved data related "global data" structures. +///******************************************** +/// + +/// +/// This data structure contains all the "global data" values that are considered to be needed +/// by the MRC between power state transitions (S0->S3->S0) and also fast and warm boot modes. +/// The following are channel level definitions. +/// +typedef struct { + MrcChannelSts Status; ///< Indicates whether this channel should be used. + MrcBool EccSupport; ///< TRUE if ECC is enabled and supported on this DIMM. + U32 DimmCount; ///< Number of valid DIMMs that exist in the channel. + U8 ValidRankBitMask; ///< Bit map of the populated ranks per channel + MrcTiming Timing[MAX_PROFILE]; ///< The channel timing values. + MrcDimmOut Dimm[MAX_DIMMS_IN_CHANNEL]; + MrcSpdSave SpdSave[MAX_DIMMS_IN_CHANNEL]; ///< Save SPD information needed for SMBIOS structure creation. +} MrcChannelSave; + +/// +/// This data structure contains all the "global data" values that are considered to be needed +/// by the MRC between power state transitions (S0->S3->S0) and also fast and warm boot modes. +/// The following are controller level definitions. +/// +typedef struct { + MrcControllerSts Status; ///< Indicates whether this controller should be used. + U8 ChannelCount; ///< Number of valid channels that exist on the controller. + MrcChannelSave Channel[MAX_CHANNEL]; +} MrcContSave; + +/// +/// This data structure contains all the "global data" values that are considered to be needed +/// by the MRC between power state transitions (S0->S3->S0) and also fast and warm boot modes. +/// The following are system level definitions. +/// +typedef struct { + U32 Crc; ///< The CRC-32 of the data in this structure. +} MrcSaveHeader; + +// +// ------- IMPORTANT NOTE -------- +// MRC_MC_REGISTER_COUNT in Global.h should match the table in MrcSaveRestore.c. +// Update this define whenever you add/remove registers from this table. +// + #define MRC_MC_REGISTER_COUNT (1 + (2496 / sizeof (U32))) ///< The number of MC registers that need to be saved. + +typedef struct { + MrcCapId McCapId; ///< The memory controller's capabilities. + U32 MeStolenSize; + U32 McRegister[MRC_MC_REGISTER_COUNT]; ///< The memory controllers registers. + MrcCpuStepping CpuStepping; ///< The last cold boot happended with this CPU stepping. + MrcCpuModel CpuModel; ///< The last cold boot happended with this CPU model. + MrcVersion Version; ///< The last cold boot happended with this MRC version. + U32 SaMemCfgCrc; ///< The CRC32 of the system agent memory configuration structure. + MrcContSave Controller[MAX_CONTROLLERS]; + MrcFrequency Frequency; ///< The system's common memory controller frequency. + U32 MemoryClock; ///< The system's common memory controller clock, in femtoseconds. + MrcRefClkSelect RefClk; ///< The memory controller is going to use this reference clock. + MrcClockRatio Ratio; ///< Request for this memory controller to use this clock ratio. + MrcVddSelect VddVoltage[MAX_PROFILE]; ///< The voltage (VDD) setting for all DIMMs in the system, per profile. + MrcBool EccSupport; ///< TRUE if ECC is enabled and supported on this controller. + MrcDdrType DdrType; ///< DDR type: DDR3 or LPDDR3 + MrcBool XmpProfileEnable; ///< XMP capable DIMMs detected in system (0 = no, 1 = yes). +#ifdef UPSERVER_SUPPORT + U16 CLTM_SPD_Conf; ///< CLTM SPD Configuration Done(0 = process not executed, 0xFF = process failed, XX = process save CLTM_SPD_Conf +#endif // UPSERVER_SUPPORT ///< CLTM_SPD_Conf = i = Density , j = Frequency , k1 = Adjacent DIMM prescence in Channel 1, k0 = Adjacent DIMM prescence in Channel 0 +} MrcSaveData; + +typedef struct { + MrcSaveHeader Header; ///< The header portion of the MRC saved data. + MrcSaveData Data; ///< The data portion of the MRC saved data. +} MrcSave; + +typedef struct { + MrcInput Inputs; +} SysInput; + +typedef struct { + MrcOutput Outputs; +} SysOutput; + +typedef struct { + MrcSave Save; +} SysSave; + +/// +/// This data structure contains all of the MRC "global data" values. +/// +typedef struct { + U32 SaveSize; + SysSave SysSave; + SysInput SysIn; + SysOutput SysOut; + U64 Oem; +#ifdef BDAT_SUPPORT + RmtData Rmt; +#endif +} MrcParameters; + +#ifdef UPSERVER_SUPPORT + + + +#define WarmThreshold_1X_MAX_TEMP 83 +#define WarmThreshold_2X_MAX_TEMP 85 +#define HotThreshold_1X_MAX_TEMP 83 +#define HotThreshold_2X_MAX_TEMP 92 + + +#define CRITICAL_TEMP 105 +#define THOT_2X_MAX_TEMP 93 +#define THOT_1X_MAX_TEMP 83 +#define DISABLE_REFRESH2X 0 + +//Power Weight Table Defines +#define WARM_BUDGET_POSITION 6 + +// CLTM Process Status Defines +#define PROCESS_NOT_INITIALIZED 0x0000 +#define PROCESS_FAILED 0xFFFF +#define CONTROLLER_NOT_LOADED 0xFF +#define CLTM_DISABLE 0 + +//CAMARILLO Interrupt Defines +#define TWOX_REFRESH_INTERRUPT_ENABLE 1 +#define FORCEMEMPR_INTERRUPT_ENABLE 1 + +//TSE2002 Thermal Sensor Defines +#define MTS_CAPABILITIES 0 +#define MTS_CFG 1 +#define MTS_THIGH 2 +#define MTS_TLOW 3 +#define MTS_TCRIT 4 +#define TEMPERATURE_REGISTER 5 +#define MTS_MFGID 6 +#define MTS_DID 7 +#define THERMAL_MODULE_MASK 0x30 + +//TSOD definitions +#define HYST_DISABLE 0 + +typedef union { + struct { + U16 EVENT_MODE : 1; // Bits 0:0 + U16 EVENT_POLARITY : 1; // Bits 1:1 + U16 CRICAL_EVENT_ONLY : 1; // Bits 2:2 + U16 EVENT_OUTPUT_CONTROL : 1; // Bits 3:3 + U16 EVENT_STATUS : 1; // Bits 4:4 + U16 CLEAR_EVENT : 1; // Bits 5:5 + U16 ALARM_WINDOW_LOCK : 1; // Bits 6:6 + U16 CRITICAL_LOCK : 1; // Bits 7:7 + U16 SHUTDOWNMODE : 1; // Bits 8:8 + U16 HYST_ENABLE : 1; // Bits 10:9 + U16 : 4; // Bits 15:11 + } Bits; + U16 Data; +} TSOD_CONF_REGISTER_STRUCT; + +//#define MTS_CFG_EVENT ((0x01) | (0x04) | (0x08)) //Bit 0 = 1, Bit 1 = 0, Bit 2 = 1, Bit 3 = 1 , Bit8 = 0, Bit 10 =0 + +#endif //UPSERVER_SUPPORT + + +#pragma pack (pop) +#endif + diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcIoControl.h b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcIoControl.h new file mode 100644 index 0000000..2d00470 --- /dev/null +++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcIoControl.h @@ -0,0 +1,44 @@ +/** @file + Memory controller IO configuration definition header. + +@copyright + Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved. + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement. +**/ +#ifndef _MrcIoControl_h_ +#define _MrcIoControl_h_ + +#include "MrcTypes.h" +#include "McAddress.h" +#include "MrcCommon.h" +#include "MrcGlobal.h" + +/** +@brief + Reset the MC IO module. The MC hardware will handle creating the 20 dclk pulse + after the bit is set and will also clear the bit. + + @param[in] MrcData - Include all MRC global data. + + @retval mrcSuccess - IO Reset was done successfully + @retval mrcDeviceBusy - Timed out waiting for the IO to clear the bit +**/ +MrcStatus +IoReset ( + IN MrcParameters *const MrcData + ); + +#endif // _MrcIoControl_h_ diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcMcConfiguration.h b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcMcConfiguration.h new file mode 100644 index 0000000..6a094d1 --- /dev/null +++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcMcConfiguration.h @@ -0,0 +1,114 @@ +/** @file + Non training specific memory controller configuration definitions. + +@copyright + Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved. + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement. +**/ +#ifndef __MrcMcConfiguration_h__ +#define __MrcMcConfiguration_h__ + +#include "MrcTypes.h" +#include "MrcApi.h" +#include "McAddress.h" +#include "MrcAddressDecodeConfiguration.h" +#include "MrcCommandTraining.h" +#include "MrcCommon.h" +#include "MrcGeneral.h" +#include "MrcGlobal.h" +#include "MrcOem.h" +#include "MrcOemIo.h" +#include "MrcRefreshConfiguration.h" +#include "MrcSchedulerParameters.h" +#include "MrcTimingConfiguration.h" + +#define DISABLE_ODT_STATIC (0) ///< May change in the future +#define CDIEVSSHI (2000) ///< Constant CdieVssHi = 2000 (value in pF) +#define RCMDREF (100) ///< Constant RcmdRef = 100 (value in ohm) + +/** +@brief + This function calculates the two numbers that get you closest to the slope. + + @param[in] Slope - targeted slope (multiplied by 100 for int match) + + @retval Returns the Slope Index to be programmed for VtSlope. +**/ +extern +U8 +MrcCalcVtSlopeCode ( + const U16 Slope + ); + +/** +@brief + This function performs the memory controller configuration non training sequence. + + @param[in, out] MrcData - Include all MRC global data. + + @retval MrcStatus - mrcSuccess if successful or an error status +**/ +extern +MrcStatus +MrcMcConfiguration ( + MrcParameters *const MrcData + ); + +/** +@brief + This function init all the necessary registers for the training. + + @param[in] MrcData - Include all MRC global data. + + @retval mrcSuccess +**/ +extern +MrcStatus +MrcPreTraining ( + MrcParameters *const MrcData + ); + +/** +@brief + This function initializes all the necessary registers after main training steps but before LCT. + + @param[in] MrcData - Include all MRC global data. + + @retval mrcSuccess +**/ +extern +MrcStatus +MrcPostTraining ( + MrcParameters *const MrcData + ); + +/** +@brief + Program PCU_CR_DDR_VOLTAGE register. + + @param[in] MrcData - Include all MRC global data. + @param[in] VddVoltage - Current DDR voltage. + + @retval none +**/ +extern +void +MrcSetPcuDdrVoltage ( + IN OUT MrcParameters *MrcData, + IN MrcVddSelect VddVoltage + ); + +#endif // __MrcMcConfiguration_h__ diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcMemoryMap.h b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcMemoryMap.h new file mode 100644 index 0000000..0ae9534 --- /dev/null +++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcMemoryMap.h @@ -0,0 +1,97 @@ +/** @file + The physical memory map configuration definitions. + +@copyright + Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved. + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement. +**/ +#ifndef _MrcMemoryMap_h_ +#define _MrcMemoryMap_h_ + +#include "MrcTypes.h" +#include "MrcApi.h" +#include "McAddress.h" +#include "MrcCommon.h" +#include "MrcOem.h" + +#define MEM_4GB (0x1000) ///< Define the 4 GB size in 1MB units (1000MB = 1GB). + +/** +@brief + After BIOS determines the total physical memory size. + Determines TOM which is defined by the total physical memory size. + Determines TOM minus the ME memory size. The ME memory size is calculated from MESEG_BASE and MESEG_MASK. + Determines MMIO allocation, which is system configuration dependent. + + Determines TOLUD which is the minimum value by comparing between "4GB minus MMIO size" and "TOM minus ME size". + Determines Graphics Stolen Base, BDSM by subtracting the graphics data stolen memory size from TOLUD. + Graphics Data Stolen Memory size is given by GMS field in GGC register. It must be define before this stage. + Determines Graphics GTT Stolen Base, BGSM by subtracting the GTT graphics stolen memory size from BDSM. + GTT Stolen Memory size is given by GGMS field in GGC register. It must be define before this stage. + Determines TSEG Base, TSEGMB by subtracting TSEG size from BGSM. + TSEG should be defined. + Remove the memory hole caused by aligning TSEG to a 8MB boundary. + Determine whether Memory Reclaim is available. If "TOM minus ME Stolem Memory Size" is greater than the value of TOLUD, then memory reclaim is available to enable. + Determine REMAPBASE if reclaim is enabled. This is the maximum value by comparing between 4GB and "TOM minus ME size". + Determine REMAPLIMIT () if reclaim is enabled. This is the value of REMAPBASE plus "the difference between the value in TOLUD register and the lower of either 4GB or 'TOM minus ME Stolen memory size", and then minus 1 boundary. + Determine TOUUD. TOUUD indicates the address one byte above the maximum DRAM. If relcaim is disabled, this value is calculated by "TOM minus ME stolen size". Otherwise, this value is set to REMAPLIMIT plus 1MB. + + @param[in, out] MrcData - Include all MRC global data. include also the memory map data. + + @retval MrcStatus - if the reset is succeded. +**/ +extern +MrcStatus +MrcSetMemoryMap ( + MrcParameters *const MrcData + ); + +/** + +@brief + This function find the total memory in the system. + and write it to TotalPhysicalMemorySize in MrcData structure. + + @param[in, out] MrcData - Include all MRC global data. + + @retval Nothing +**/ +extern +void +MrcTotalMemory ( + MrcParameters *const MrcData + ); + +/** + +@brief + this function write to the memory init registers. + + @param[in] PciEBaseAddress - Address of the PCI Express BAR + @param[in] GdxcBaseAddress - Address of the GDXC BAR + @param[in] MemoryMap - Include all the memory map definitions + + @retval Nothing +**/ +extern +void +UpdateMemoryMapRegisters ( + const U32 PciEBaseAddress, + const U32 GdxcBaseAddress, + const MrcMemoryMap *const MemoryMap + ); + +#endif // _MrcMemoryMap_h_ diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcOem.h b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcOem.h new file mode 100644 index 0000000..0742d8d --- /dev/null +++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcOem.h @@ -0,0 +1,464 @@ +/** @file + This file is the OEM interface to the MRC core. + This file includes the OEM MRC implementation and can be changed between projects. + Each MRC customer must provide those OEM interfaces. + +@copyright + Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement + +**/ +#ifndef _MrcOem_h_ +#define _MrcOem_h_ + +#include "MrcTypes.h" +#include "MrcApi.h" +#include "MrcGlobal.h" + +// +// OEM MMIO routines +// +#include "MrcOemMmio.h" + +// +////////////////////////////////////////////////////////////////////////////////////// +// OEM debug print routines and types // +////////////////////////////////////////////////////////////////////////////////////// +// +#include "MrcOemDebugPrint.h" + +#ifndef MRC_DEBUG_MSG +#error "MRC_DEBUG_MSG is not defined" +#endif //MRC_DEBUG_MSG +/// +////////////////////////////////////////////////////////////////////////////////////// +/// OEM platform routines and types // +////////////////////////////////////////////////////////////////////////////////////// +/// +/// define the oem check points the OEM can define more point and locate them in the code. +/// +typedef enum { + OemFastBootPermitted, ///< before fast boot. + OemRestoreNonTraining, + OemPrintInputParameters, ///< before printing input parameters + OemSpdProcessingRun, ///< before spd processing code + OemSetOverridePreSpd, ///< before set overrides pre spd + OemMcCapabilityPreSpd, ///< before MC capability pre spd + OemSetOverride, ///< before set overrides + OemMcCapability, ///< before MC capability + OemMcInitRun, ///< before mc init code + OemMcMemoryMap, ///< before memory map + OemMcResetRun, ///< before jedec reset + OemPreTraining, ///< before the training. + OemMcTrainingRun, ///< before training code + OemEarlyCommandTraining, ///< before Early Command training + OemJedecInitLpddr3, ///< before Jedec Init Lpddr3 + OemSenseAmpTraining, ///< before Sense Amp Training + OemReadMprTraining, ///< before Read MPR Training + OemReceiveEnable, ///< before Read Leveling + OemJedecWriteLeveling, ///< before Jedec Write Leveling + OemWriteLeveling, ///< before Functional Write Leveling + OemWriteDqDqs, ///< before Write Timing Centering + OemReadDqDqs, ///< before Read Timing Centering + OemDimmRonTraining, ///< before DIMM Ron algorithm. + OemDimmODTTraining, ///< before DIMM ODT algorithm. + OemDimmODT1dTraining, ///< before DIMM ODT 1d algorithm. + OemWriteDriveStrength, ///< before Write DS + OemWriteSlewRate, ///< before Write SR + OemWriteEQTraining, ///< before Write Equalization Training + OemReadODTTraining, ///< before Read ODT algorithm. + OemReadEQTraining, ///< before Read Equalization Training + OemReadAmplifierPower, ///< before Read Amplifier Power + OemOptimizeComp, ///< before Comp Optimization Training + OemPowerSavingMeter, ///< before PowerSavingMeter step + OemWriteDqDqs2D, ///< before Write Timing Centering 2D + OemReadDqDqs2D, ///< before Read Timing Centering 2D + OemCmdVoltCentering, ///< before Command Voltage Centering + OemWriteVoltCentering2D, ///< before Write Voltage Centering 2D + OemReadVoltCentering2D, ///< before Read Voltage Centering 2D + OemLateCommandTraining, ///< before Late Command training + OemRoundTripLatency, ///< before Round Trip Latency Traiing + OemTurnAroundTimes, ///< before Turn Aorund Times. + OemRcvEnCentering1D, ///< before Receive Enable Centring + OemSaveMCValues, ///< before saving memory controller values + OemRmt, ///< before RMT crosser tool. + OemMemTest, ///< before Memory testing + OemRestoreTraining, ///< before Restoring Training Values + OemSelfRefreshExit, ///< before Self Refresh Exit + OemNormalMode, ///< before Normal Mode on non-cold boots. + OemAliasCheck, ///< before alias checking on cold boots. + OemHwMemInit, + + OemPostTraining, ///< after the training. + OemMrcActivate, ///< before MrcActivate call. + OemMrcDone, ///< call to MrcOemCheckPoint when MRC was done. + OemFrequencySet, ///< do operation before frequency set. + OemFrequencySetDone, ///< do operation after frequency set. + OemStartMemoryConfiguration, + OemBeforeNormalMode, ///< call to MrcOemCheckPoint before normal mode is enalbed + OemAfterNormalMode, ///< call to MrcOemCheckPoint after normal mode is enalbed + OemMrcFillRmt, + OemRetrainMarginCheck, + /// + ///********************************************************************************* + /// + OemNumOfCommands ///< Should always be last in the list! +} MRC_OemStatusCommand; + +/// +/// Define the MRC SMBUS devices type. +/// +typedef enum { + datOemSpd_0_0, ///< use for get the device address for channel 0 dimm 0 + datOemSpd_0_1, ///< use for get the device address for channel 0 dimm 1 + datOemSpd_1_0, ///< use for get the device address for channel 1 dimm 0 + datOemSpd_1_1, ///< use for get the device address for channel 1 dimm 1 + datOemVrefWrite_0, ///< use for get the device address for dimm vref controlled potentiometer channel 0 + datOemVrefWrite_1, ///< use for get the device address for dimm vref controlled potentiometer channel 1 + datOemVrefRead ///< use for get the device address for cpu vref controlled potentiometer +} MRC_OemSmbusDeviceType; + +/// +////////////////////////////////////////////////////////////////////////////////////// +/// OEM IO routines and types // +////////////////////////////////////////////////////////////////////////////////////// +/// + +/** + 8 bit I/O port read. + Needs to be ported for OEM platform requirements. + + @param[in] Address - the IO read address. + + @retval return the read value. +**/ +extern +U8 +MrcOemInPort8 ( + IN U16 IoAddress + ); + +/** + 8 bit I/O port write. + Needs to be ported for OEM platform requirements. + + @param[in] IoAddress - The I/O port read address. + @param[in] Data - The value to write. + + @retval Nothing +**/ +extern +void +MrcOemOutPort8 ( + IN U16 IoAddress, + IN U8 data + ); + +/** + 16 bit I/O port read. + Needs to be ported for OEM platform requirements. + + @param[in] IoAddress - The I/O port read address. + + @retval return the read value. +**/ +extern +U16 +MrcOemInPort16 ( + IN U16 IoAddress + ); + +/** + 16 bit I/O port write. + Needs to be ported for OEM platform requirements. + + @param[in] IoAddress - The I/O port read address. + @param[in] Data - The value to write. + + @retval Nothing +**/ +extern +void +MrcOemOutPort16 ( + IN U16 IoAddress, + IN U16 data + ); + +/** + 32 bit I/O port read. + Needs to be ported for OEM platform requirements. + + @param[in] IoAddress - The I/O port read address. + + @retval The value read. +**/ +extern +U32 +MrcOemInPort32 ( + IN U16 IoAddress + ); + +/** + 32 bit I/O port write. + Needs to be ported for OEM platform requirements. + + @param[in] IoAddress - The I/O port read address. + @param[in] Data - The value to write. + + @retval Nothing +**/ +extern +void +MrcOemOutPort32 ( + IN U16 IoAddress, + IN U32 data + ); + +/** + This function return the PCI index address. + Needs to be ported for OEM platform requirements. + + @param[in] None. + + @retval The PCI index address. +**/ +extern +U16 +MrcOemPciIndex ( + void + ); + +/** + This function return the PCI data address. + Needs to be ported for OEM platform requirements. + + @param[in] None + + @retval The PCI data address. +**/ +extern +U16 +MrcOemPciData ( + void + ); + +/** + This function return the PCI device address. + Needs to be ported for OEM platform requirements. + + @param[in] Bus - PCI bus + @param[in] Device - PCI device + @param[in] Function - PCI function + @param[in] Offset - Offset + + @retval The PCI device address. +**/ +extern +U32 +MrcOemGetPciDeviceAddress ( + IN U8 Bus, + IN U8 Device, + IN U8 Function, + IN U8 Offset + ); + +/** + This function return the PCIE device address. + Needs to be ported for OEM platform requirements. + + @param[in] Bus - PCI bus + @param[in] Device - PCI device + @param[in] Function - PCI function + @param[in] Offset - Offset + + @retval The PCIe device address. +**/ +extern +U32 +MrcOemGetPcieDeviceAddress ( + IN U8 Bus, + IN U8 Device, + IN U8 Function, + IN U8 Offset + ); + +/** + Returns the current time, as determined by reading the Real Time Clock (RTC) on the platform. + Since RTC time is stored in BCD, convert each value to binary. + + @param[out] Seconds - The current second (0-59). + @param[out] Minutes - The current minute (0-59). + @param[out] Hours - The current hour (0-23). + @param[out] DayOfMonth - The current day of the month (1-31). + @param[out] Month - The current month (1-12). + @param[out] Year - The current year (2000-2099). + + @retval Nothing +**/ +extern +void +MrcOemGetRtcTime ( + U8 *Seconds, + U8 *Minutes, + U8 *Hours, + U8 *DayOfMonth, + U8 *Month, + U16*Year + ); + +/// +////////////////////////////////////////////////////////////////////////////////////// +/// OEM Memory routines and types // +////////////////////////////////////////////////////////////////////////////////////// +/// + +/** + Copy the specified number of memory bytes, a byte at a time, from the + specified source to the specified destination. + Needs to be ported for OEM platform requirements. + + @param[in, out] Dest - Destination pointer. + @param[in] Src - Source pointer. + @param[in] NumBytes - The number of bytes to copy. + + @retval Nothing +**/ +extern +void +MrcOemMemoryCpy ( + IN OUT U8 *Dest, + IN U8 *Src, + IN U32 NumBytes + ); + +/** + Sets the specified number of memory bytes, a byte at a time, at the + specified destination. + Needs to be ported for OEM platform requirements. + + @param[in, out] Dest - Destination pointer. + @param[in] Value - The value to set. + @param[in] NumBytes - The number of bytes to set. + + @retval Nothing +**/ +extern +void +MrcOemMemorySet ( + IN OUT U8 *Dest, + IN U32 Value, + IN U32 NumBytes + ); + +/** + Sets the specified number of memory dwords, a dword at a time, at the + specified destination. + + @param[in, out] Dest - Destination pointer. + @param[in] Value - The value to set. + @param[in] NumWords - The number of dwords to set. + + @retval Nothing. +**/ +extern +void +MrcOemMemorySetWord ( + IN OUT U16 *Dest, + IN const U16 Value, + IN U32 NumWords + ); + +/** + Sets the specified number of memory dwords, a dword at a time, at the + specified destination. + + @param[in, out] Dest - Destination pointer. + @param[in] Value - The value to set. + @param[in] NumDwords - The number of dwords to set. + + @retval Nothing. +**/ +extern +void +MrcOemMemorySetDword ( + IN OUT U32 *Dest, + IN const U32 Value, + IN U32 NumDwords + ); + +/** + Shift the specified data value left by the specified count. + Needs to be ported for OEM platform requirements. + + @param[in] Data - 64 bit number to shift left. + @param[in] Count - Number of bits to shift (0..63) + + @retval The number of bits shifted left. +**/ +extern +U64 +MrcOemMemoryLeftShiftU64 ( + IN const U64 Data, + IN const U8 Count + ); + +/** + Shift the specified data value Right by the specified count. + + @param[in] Data - U64 number to shift + @param[in] Count - number of bits to shift (0..63) + + @retval Returns the shifted U64 value. +**/ +extern +U64 +MrcOemMemoryRightShiftU64 ( + IN const U64 Data, + IN const U8 Count + ); + +/** + This function Multiply U64 with a U32 number. Result is <= 64 bits + Needs to be ported for OEM platform requirements. + + @param[in] Multiplicand - U64 number to be multiplied with + @param[in] Multiplier - U32 number to multiply + + @retval Returns the multiplication result of U64 value. +**/ +extern +U64 +MrcOemMemoryMultiplyU64ByU32 ( + IN const U64 Multiplicand, + IN const U32 Multiplier + ); + +/** + Divide U64 with a U64 number. Result is <= 32 bits + + @param[in] Dividend - U64 number to be multiplied with + @param[in] Divisor - U32 number to multiply + + @retval Returns the quotient result of U64 value. +**/ +extern +U64 +MrcOemMemoryDivideU64ByU64 ( + IN const U64 Dividend, + IN const U64 Divisor + ); + +#endif // _MrcOem_h_ diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcRegisters/McGdxcbar.h b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcRegisters/McGdxcbar.h new file mode 100644 index 0000000..fd91eba --- /dev/null +++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcRegisters/McGdxcbar.h @@ -0,0 +1,2849 @@ +/** @file + This file was automatically generated. Modify at your own risk. + +@copyright + Copyright (c) 2010 - 2012 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +**/ +#ifndef __McGdxcbar_h__ +#define __McGdxcbar_h__ + +#pragma pack(push, 1) +#include "MrcTypes.h" + +typedef union { + struct { + U32 Tx_Delay_R0 : 8; // Bits 7:0 + U32 Tx_Delay_R1 : 8; // Bits 15:8 + U32 Tx_Delay_R2 : 8; // Bits 23:16 + U32 Tx_Delay_R3 : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRPL_CR_DDR_TX_DELAY_STRUCT; + +typedef union { + struct { + U32 EN_SW_GDXC : 1; // Bits 0:0 + U32 EN_RING_ADQ : 1; // Bits 1:1 + U32 EN_RING_BLQ : 1; // Bits 2:2 + U32 EN_RING_AKQ : 1; // Bits 3:3 + U32 EN_RING_IVQ : 1; // Bits 4:4 + U32 EN_IDIQ : 1; // Bits 5:5 + U32 EN_mc_UCLKQ : 1; // Bits 6:6 + U32 : 1; // Bits 7:7 + U32 UP_EN_ADQ : 1; // Bits 8:8 + U32 DN_EN_ADQ : 1; // Bits 9:9 + U32 UP_EN_BLQ : 1; // Bits 10:10 + U32 DN_EN_BLQ : 1; // Bits 11:11 + U32 UP_EN_AKQ : 1; // Bits 12:12 + U32 DN_EN_AKQ : 1; // Bits 13:13 + U32 MOTQ_TIMING_SELECT : 1; // Bits 14:14 + U32 : 1; // Bits 15:15 + U32 SPARE : 8; // Bits 23:16 + U32 : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MPCOHTRK_CR_GDXC_SW_ENABLE_STRUCT; + +typedef union { + struct { + U32 EN_Core0_T0 : 1; // Bits 0:0 + U32 EN_Core0_T1 : 1; // Bits 1:1 + U32 EN_Core1_T0 : 1; // Bits 2:2 + U32 EN_Core1_T1 : 1; // Bits 3:3 + U32 EN_Core2_T0 : 1; // Bits 4:4 + U32 EN_Core2_T1 : 1; // Bits 5:5 + U32 EN_Core3_T0 : 1; // Bits 6:6 + U32 EN_Core3_T1 : 1; // Bits 7:7 + U32 EN_GT : 1; // Bits 8:8 + U32 MEM_CHR_RD : 1; // Bits 9:9 + U32 MEM_CHR_WR : 1; // Bits 10:10 + U32 MEM_NC : 1; // Bits 11:11 + U32 EN_CBO_Exp_WB : 1; // Bits 12:12 + U32 SNP_Access : 1; // Bits 13:13 + U32 AD_EODLAT : 1; // Bits 14:14 + U32 : 17; // Bits 31:15 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_STRUCT; + +typedef union { + struct { + U32 CR_CHR_RD : 3; // Bits 2:0 + U32 CHR_RD_STAT_MOD : 1; // Bits 3:3 + U32 CR_CHR_WR : 4; // Bits 7:4 + U32 CR_NC_RD : 3; // Bits 10:8 + U32 NC_RD_STAT_MOD : 1; // Bits 11:11 + U32 CR_NC_WR : 4; // Bits 15:12 + U32 NC_WR_STAT_MOD : 1; // Bits 16:16 + U32 Data_Core0 : 1; // Bits 17:17 + U32 Data_Core1 : 1; // Bits 18:18 + U32 Data_Core2 : 1; // Bits 19:19 + U32 Data_Core3 : 1; // Bits 20:20 + U32 Data_CBO : 1; // Bits 21:21 + U32 Data_GT : 1; // Bits 22:22 + U32 : 9; // Bits 31:23 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MPCOHTRK_CR_GDXC_QUALIFIER_BL_STRUCT; + +typedef union { + struct { + U32 OVF_Global : 1; // Bits 0:0 + U32 OVF_Ring_AD : 1; // Bits 1:1 + U32 OVF_Ring_BL : 1; // Bits 2:2 + U32 OVF_Ring_AK : 1; // Bits 3:3 + U32 OVF_Ring_IV : 1; // Bits 4:4 + U32 : 4; // Bits 8:5 + U32 OVF_IDI_center : 1; // Bits 9:9 + U32 OVF_mcUCLK : 1; // Bits 10:10 + U32 OVF_PWR_mcFCLK : 1; // Bits 11:11 + U32 : 20; // Bits 31:12 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MPCOHTRK_CR_GDXC_OVF_STATUS_STRUCT; + +typedef union { + struct { + U32 MEM_PTR : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MPCOHTRK_CR_GDXC_MOT_ADDRESS_LO_STRUCT; + +typedef union { + struct { + U32 MEM_PTR : 1; // Bits 0:0 + U32 BUFFER_WRAP : 1; // Bits 1:1 + U32 SPARE : 30; // Bits 31:2 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MPCOHTRK_CR_GDXC_MOT_ADDRESS_HI_STRUCT; + +typedef union { + struct { + U32 START_ADDRESS : 16; // Bits 15:0 + U32 END_ADDRESS : 16; // Bits 31:16 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MPCOHTRK_CR_GDXC_MOT_REGION_STRUCT; + +typedef union { + struct { + U32 MEM_PTR : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MPCOHTRK_CR_GDXC_OCLA_ADDRESS_LO_STRUCT; + +typedef union { + struct { + U32 MEM_PTR : 1; // Bits 0:0 + U32 BUFFER_WRAP : 1; // Bits 1:1 + U32 LOCK : 1; // Bits 2:2 + U32 SPARE : 29; // Bits 31:3 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MPCOHTRK_CR_GDXC_OCLA_ADDRESS_HI_STRUCT; + +typedef union { + struct { + U32 START_ADDRESS : 16; // Bits 15:0 + U32 END_ADDRESS : 16; // Bits 31:16 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MPCOHTRK_CR_GDXC_OCLA_REGION_STRUCT; + +typedef union { + struct { + U32 ARM_bits_packet : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} GODLAT_CR_G_ODLAT_ARM_S0L_STRUCT; + +typedef union { + struct { + U32 ARM_bits_packet : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} GODLAT_CR_G_ODLAT_ARM_S0H_STRUCT; + +typedef union { + struct { + U32 Mask_bits : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} GODLAT_CR_G_ODLAT_MASK_S0L_STRUCT; + +typedef union { + struct { + U32 Mask_bits : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} GODLAT_CR_G_ODLAT_MASK_S0H_STRUCT; + +typedef union { + struct { + U32 ARM_bits_packet : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} GODLAT_CR_G_ODLAT_ARM_S1L_STRUCT; + +typedef union { + struct { + U32 ARM_bits_packet : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} GODLAT_CR_G_ODLAT_ARM_S1H_STRUCT; + +typedef union { + struct { + U32 Mask_bits : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} GODLAT_CR_G_ODLAT_MASK_S1L_STRUCT; + +typedef union { + struct { + U32 Mask_bits : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} GODLAT_CR_G_ODLAT_MASK_S1H_STRUCT; + +typedef union { + struct { + U32 ARM_bits_packet : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} GODLAT_CR_G_ODLAT_ARM_S2L_STRUCT; + +typedef union { + struct { + U32 ARM_bits_packet : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} GODLAT_CR_G_ODLAT_ARM_S2H_STRUCT; + +typedef union { + struct { + U32 Mask_bits : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} GODLAT_CR_G_ODLAT_MASK_S2L_STRUCT; + +typedef union { + struct { + U32 Mask_bits : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} GODLAT_CR_G_ODLAT_MASK_S2H_STRUCT; + +typedef union { + struct { + U32 ARM_bits_packet : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} GODLAT_CR_G_ODLAT_ARM_S3L_STRUCT; + +typedef union { + struct { + U32 ARM_bits_packet : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} GODLAT_CR_G_ODLAT_ARM_S3H_STRUCT; + +typedef union { + struct { + U32 Mask_bits : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} GODLAT_CR_G_ODLAT_MASK_S3L_STRUCT; + +typedef union { + struct { + U32 Mask_bits : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} GODLAT_CR_G_ODLAT_MASK_S3H_STRUCT; + +typedef union { + struct { + U32 ARM_bits_packet : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} GODLAT_CR_G_ODLAT_ARM_S4L_STRUCT; + +typedef union { + struct { + U32 ARM_bits_packet : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} GODLAT_CR_G_ODLAT_ARM_S4H_STRUCT; + +typedef union { + struct { + U32 Mask_bits : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} GODLAT_CR_G_ODLAT_MASK_S4L_STRUCT; + +typedef union { + struct { + U32 Mask_bits : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} GODLAT_CR_G_ODLAT_MASK_S4H_STRUCT; + +typedef union { + struct { + U32 ARM_bits_packet : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} GODLAT_CR_G_ODLAT_ARM_S5L_STRUCT; + +typedef union { + struct { + U32 ARM_bits_packet : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} GODLAT_CR_G_ODLAT_ARM_S5H_STRUCT; + +typedef union { + struct { + U32 Mask_bits : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} GODLAT_CR_G_ODLAT_MASK_S5L_STRUCT; + +typedef union { + struct { + U32 Mask_bits : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} GODLAT_CR_G_ODLAT_MASK_S5H_STRUCT; + +typedef union { + struct { + U32 ARM_bits_packet : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} GODLAT_CR_G_ODLAT_ARM_S6L_STRUCT; + +typedef union { + struct { + U32 ARM_bits_packet : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} GODLAT_CR_G_ODLAT_ARM_S6H_STRUCT; + +typedef union { + struct { + U32 Mask_bits : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} GODLAT_CR_G_ODLAT_MASK_S6L_STRUCT; + +typedef union { + struct { + U32 Mask_bits : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} GODLAT_CR_G_ODLAT_MASK_S6H_STRUCT; + +typedef union { + struct { + U32 ARM_bits_packet : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} GODLAT_CR_G_ODLAT_ARM_S7L_STRUCT; + +typedef union { + struct { + U32 ARM_bits_packet : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} GODLAT_CR_G_ODLAT_ARM_S7H_STRUCT; + +typedef union { + struct { + U32 Mask_bits : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} GODLAT_CR_G_ODLAT_MASK_S7L_STRUCT; + +typedef union { + struct { + U32 Mask_bits : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} GODLAT_CR_G_ODLAT_MASK_S7H_STRUCT; + +typedef union { + struct { + U32 UX_TMR_BASE_A : 1; // Bits 0:0 + U32 UX_TMR_BASE_B : 1; // Bits 1:1 + U32 OVF_ARM_IDI : 1; // Bits 2:2 + U32 OVF_ARM_HIGH : 5; // Bits 7:3 + U32 OVF_Mask_HIGH : 5; // Bits 12:8 + U32 : 5; // Bits 17:13 + U32 TimerA_units : 3; // Bits 20:18 + U32 TimerB_units : 3; // Bits 23:21 + U32 Which_Time_Base : 4; // Bits 27:24 + U32 Tmr_Or_Cntr_Mode : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} GODLAT_CR_G_ODLAT_CMD_STRUCT; + +typedef union { + struct { + U32 EN_SW_G_ODLAT : 1; // Bits 0:0 + U32 : 7; // Bits 7:1 + U32 EN_S0 : 1; // Bits 8:8 + U32 EN_S1 : 1; // Bits 9:9 + U32 EN_S2 : 1; // Bits 10:10 + U32 EN_S3 : 1; // Bits 11:11 + U32 EN_S4 : 1; // Bits 12:12 + U32 EN_S5 : 1; // Bits 13:13 + U32 EN_S6 : 1; // Bits 14:14 + U32 EN_S7 : 1; // Bits 15:15 + U32 MBP_Enable : 1; // Bits 16:16 + U32 : 15; // Bits 31:17 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} GODLAT_CR_G_ODLAT_SW_ENABLE_STRUCT; + +typedef union { + struct { + U32 Pulse_or_Sticky_Events : 8; // Bits 7:0 + U32 Pulse_or_Sticky_MBP : 1; // Bits 8:8 + U32 Pulse_or_Sticky_TO : 4; // Bits 12:9 + U32 OVF_ARM_LOW : 3; // Bits 15:13 + U32 OVF_MASK_LOW : 3; // Bits 18:16 + U32 Which_MBP_Pin_A : 3; // Bits 21:19 + U32 Which_MBP_Pin_B : 3; // Bits 24:22 + U32 Which_MBP_Pin_C : 3; // Bits 27:25 + U32 Which_MBP_Pin_D : 3; // Bits 30:28 + U32 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} GODLAT_CR_G_ODLAT_MISC_CMD_STRUCT; + +typedef union { + struct { + U32 Ln0Mask : 8; // Bits 7:0 + U32 Ln1Mask : 8; // Bits 15:8 + U32 AssertMode : 1; // Bits 16:16 + U32 CompEn : 1; // Bits 17:17 + U32 GT_VISA_En : 1; // Bits 18:18 + U32 : 13; // Bits 31:19 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} GDXC_CR_GT_VISA2OCLA_CFG_FILTER_STRUCT; + +typedef union { + struct { + U32 Man_Reset_GDXC : 1; // Bits 0:0 + U32 Man_Reset_G_ODLAT : 1; // Bits 1:1 + U32 IOT_Start : 1; // Bits 2:2 + U32 IOT_Stop : 1; // Bits 3:3 + U32 IOT_Trigger : 1; // Bits 4:4 + U32 IOT_Force_Flush : 1; // Bits 5:5 + U32 : 10; // Bits 15:6 + U32 SPARE : 8; // Bits 23:16 + U32 : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} GDXC_CR_GDXC_MAN_CONFIG_STRUCT; + +typedef union { + struct { + U32 mbpout : 2; // Bits 1:0 + U32 : 30; // Bits 31:2 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} GDXC_CR_GDXC_ALIGN_STRUCT; + +typedef union { + struct { + U32 AD : 6; // Bits 5:0 + U32 BLHDR0 : 7; // Bits 12:6 + U32 BLHDR1ADDR : 6; // Bits 18:13 + U32 AK : 6; // Bits 24:19 + U32 IV : 2; // Bits 26:25 + U32 Wrap : 3; // Bits 29:27 + U32 MOT : 5; // Bits 34:30 + U32 IDI : 5; // Bits 39:35 + U32 FClk : 5; // Bits 44:40 + U32 UClkMsgCh : 5; // Bits 49:45 + U32 : 14; // Bits 63:50 + } Bits; + U64 Data; + U32 Data32[2]; + U16 Data16[4]; + U8 Data8[8]; +} GDXC_CR_GDXC_RR_ARB_THRESH_STRUCT; + +typedef union { + struct { + U32 Start_Status : 1; // Bits 0:0 + U32 Trigger_Status : 1; // Bits 1:1 + U32 Stop_Status : 1; // Bits 2:2 + U32 Muliple_Hit : 1; // Bits 3:3 + U32 Bubbles_Status : 6; // Bits 9:4 + U32 : 22; // Bits 31:10 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} GDXC_CR_G_ODLAT_FIRE_STATUS_STRUCT; + +typedef union { + struct { + U32 Delay_count : 25; // Bits 24:0 + U32 : 7; // Bits 31:25 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} GDXC_CR_TRIGGER_TO_STOP_DELAY_STRUCT; + +typedef union { + struct { + U32 Disabled : 1; // Bits 0:0 + U32 Idle : 1; // Bits 1:1 + U32 Running : 1; // Bits 2:2 + U32 IOT_Triggered : 1; // Bits 3:3 + U32 Sticky_triggered : 1; // Bits 4:4 + U32 : 1; // Bits 5:5 + U32 Remaining_count : 25; // Bits 30:6 + U32 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} GDXC_CR_IOT_STATUS_STRUCT; + +typedef union { + struct { + U32 S0_OclaHdr : 8; // Bits 7:0 + U32 S1_OclaHdr : 8; // Bits 15:8 + U32 S2_OclaHdr : 8; // Bits 23:16 + U32 S3_OclaHdr : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} GODLAT_CR_G_ODLAT_OCLAHDR_S0TO3_STRUCT; + +typedef union { + struct { + U32 S4_OclaHdr : 8; // Bits 7:0 + U32 S5_OclaHdr : 8; // Bits 15:8 + U32 S6_OclaHdr : 8; // Bits 23:16 + U32 S7_OclaHdr : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} GODLAT_CR_G_ODLAT_OCLAHDR_S4TO7_STRUCT; + +typedef union { + struct { + U32 S0_FST : 2; // Bits 1:0 + U32 S1_FST : 2; // Bits 3:2 + U32 S2_FST : 2; // Bits 5:4 + U32 S3_FST : 2; // Bits 7:6 + U32 S4_FST : 2; // Bits 9:8 + U32 S5_FST : 2; // Bits 11:10 + U32 S6_FST : 2; // Bits 13:12 + U32 S7_FST : 2; // Bits 15:14 + U32 : 16; // Bits 31:16 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} GODLAT_CR_G_ODLAT_FST_STRUCT; + +typedef union { + struct { + U32 Arm : 8; // Bits 7:0 + U32 MBP_Arm : 1; // Bits 8:8 + U32 TO_Arm : 4; // Bits 12:9 + U32 : 3; // Bits 15:13 + U32 Mask : 8; // Bits 23:16 + U32 MBP_Mask : 1; // Bits 24:24 + U32 TO_Mask : 4; // Bits 28:25 + U32 : 3; // Bits 31:29 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B0_STRUCT; + +typedef union { + struct { + U32 Arm : 8; // Bits 7:0 + U32 MBP_Arm : 1; // Bits 8:8 + U32 TO_Arm : 4; // Bits 12:9 + U32 : 3; // Bits 15:13 + U32 Mask : 8; // Bits 23:16 + U32 MBP_Mask : 1; // Bits 24:24 + U32 TO_Mask : 4; // Bits 28:25 + U32 : 3; // Bits 31:29 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B1_STRUCT; + +typedef union { + struct { + U32 Arm : 8; // Bits 7:0 + U32 MBP_Arm : 1; // Bits 8:8 + U32 TO_Arm : 4; // Bits 12:9 + U32 : 3; // Bits 15:13 + U32 Mask : 8; // Bits 23:16 + U32 MBP_Mask : 1; // Bits 24:24 + U32 TO_Mask : 4; // Bits 28:25 + U32 : 3; // Bits 31:29 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B2_STRUCT; + +typedef union { + struct { + U32 Arm : 8; // Bits 7:0 + U32 MBP_Arm : 1; // Bits 8:8 + U32 TO_Arm : 4; // Bits 12:9 + U32 : 3; // Bits 15:13 + U32 Mask : 8; // Bits 23:16 + U32 MBP_Mask : 1; // Bits 24:24 + U32 TO_Mask : 4; // Bits 28:25 + U32 : 3; // Bits 31:29 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B3_STRUCT; + +typedef union { + struct { + U32 Arm : 8; // Bits 7:0 + U32 MBP_Arm : 1; // Bits 8:8 + U32 TO_Arm : 4; // Bits 12:9 + U32 : 3; // Bits 15:13 + U32 Mask : 8; // Bits 23:16 + U32 MBP_Mask : 1; // Bits 24:24 + U32 TO_Mask : 4; // Bits 28:25 + U32 : 3; // Bits 31:29 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B4_STRUCT; + +typedef union { + struct { + U32 Arm : 8; // Bits 7:0 + U32 MBP_Arm : 1; // Bits 8:8 + U32 TO_Arm : 4; // Bits 12:9 + U32 : 3; // Bits 15:13 + U32 Mask : 8; // Bits 23:16 + U32 MBP_Mask : 1; // Bits 24:24 + U32 TO_Mask : 4; // Bits 28:25 + U32 : 3; // Bits 31:29 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B5_STRUCT; + +typedef union { + struct { + U32 Arm : 8; // Bits 7:0 + U32 MBP_Arm : 1; // Bits 8:8 + U32 TO_Arm : 4; // Bits 12:9 + U32 Stop : 1; // Bits 13:13 + U32 : 2; // Bits 15:14 + U32 Mask : 8; // Bits 23:16 + U32 MBP_Mask : 1; // Bits 24:24 + U32 TO_Mask : 4; // Bits 28:25 + U32 Col_Rst : 1; // Bits 29:29 + U32 Trigger : 1; // Bits 30:30 + U32 Start : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B0_STRUCT; + +typedef union { + struct { + U32 Arm : 8; // Bits 7:0 + U32 MBP_Arm : 1; // Bits 8:8 + U32 TO_Arm : 4; // Bits 12:9 + U32 : 3; // Bits 15:13 + U32 Mask : 8; // Bits 23:16 + U32 MBP_Mask : 1; // Bits 24:24 + U32 TO_Mask : 4; // Bits 28:25 + U32 : 3; // Bits 31:29 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B0_STRUCT; + +typedef union { + struct { + U32 Arm : 8; // Bits 7:0 + U32 MBP_Arm : 1; // Bits 8:8 + U32 TO_Arm : 4; // Bits 12:9 + U32 : 3; // Bits 15:13 + U32 Mask : 8; // Bits 23:16 + U32 MBP_Mask : 1; // Bits 24:24 + U32 TO_Mask : 4; // Bits 28:25 + U32 : 3; // Bits 31:29 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B1_STRUCT; + +typedef union { + struct { + U32 Arm : 8; // Bits 7:0 + U32 MBP_Arm : 1; // Bits 8:8 + U32 TO_Arm : 4; // Bits 12:9 + U32 : 3; // Bits 15:13 + U32 Mask : 8; // Bits 23:16 + U32 MBP_Mask : 1; // Bits 24:24 + U32 TO_Mask : 4; // Bits 28:25 + U32 : 3; // Bits 31:29 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B2_STRUCT; + +typedef union { + struct { + U32 Arm : 8; // Bits 7:0 + U32 MBP_Arm : 1; // Bits 8:8 + U32 TO_Arm : 4; // Bits 12:9 + U32 : 3; // Bits 15:13 + U32 Mask : 8; // Bits 23:16 + U32 MBP_Mask : 1; // Bits 24:24 + U32 TO_Mask : 4; // Bits 28:25 + U32 : 3; // Bits 31:29 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B3_STRUCT; + +typedef union { + struct { + U32 Arm : 8; // Bits 7:0 + U32 MBP_Arm : 1; // Bits 8:8 + U32 TO_Arm : 4; // Bits 12:9 + U32 : 3; // Bits 15:13 + U32 Mask : 8; // Bits 23:16 + U32 MBP_Mask : 1; // Bits 24:24 + U32 TO_Mask : 4; // Bits 28:25 + U32 : 3; // Bits 31:29 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B4_STRUCT; + +typedef union { + struct { + U32 Arm : 8; // Bits 7:0 + U32 MBP_Arm : 1; // Bits 8:8 + U32 TO_Arm : 4; // Bits 12:9 + U32 : 3; // Bits 15:13 + U32 Mask : 8; // Bits 23:16 + U32 MBP_Mask : 1; // Bits 24:24 + U32 TO_Mask : 4; // Bits 28:25 + U32 : 3; // Bits 31:29 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B5_STRUCT; + +typedef union { + struct { + U32 Arm : 8; // Bits 7:0 + U32 MBP_Arm : 1; // Bits 8:8 + U32 TO_Arm : 4; // Bits 12:9 + U32 Stop : 1; // Bits 13:13 + U32 : 2; // Bits 15:14 + U32 Mask : 8; // Bits 23:16 + U32 MBP_Mask : 1; // Bits 24:24 + U32 TO_Mask : 4; // Bits 28:25 + U32 Col_Rst : 1; // Bits 29:29 + U32 Trigger : 1; // Bits 30:30 + U32 Start : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B1_STRUCT; + +typedef union { + struct { + U32 B0_Set : 6; // Bits 5:0 + U32 B0_Rst : 6; // Bits 11:6 + U32 B1_Set : 6; // Bits 17:12 + U32 B1_Rst : 6; // Bits 23:18 + U32 : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} GODLAT_CR_G_ODLAT_TR_IF_MODE_B0_B1_STRUCT; + +typedef union { + struct { + U32 B2_Set : 6; // Bits 5:0 + U32 B2_Rst : 6; // Bits 11:6 + U32 B3_Set : 6; // Bits 17:12 + U32 B3_Rst : 6; // Bits 23:18 + U32 : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} GODLAT_CR_G_ODLAT_TR_IF_MODE_B2_B3_STRUCT; + +typedef union { + struct { + U32 B4_Set : 6; // Bits 5:0 + U32 B4_Rst : 6; // Bits 11:6 + U32 B5_Set : 6; // Bits 17:12 + U32 B5_Rst : 6; // Bits 23:18 + U32 : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} GODLAT_CR_G_ODLAT_TR_IF_MODE_B4_B5_STRUCT; + +typedef union { + struct { + U32 ElseIf_ElseIf_B0_Set : 6; // Bits 5:0 + U32 ElseIf_ElseIf_B0_Rst : 6; // Bits 11:6 + U32 : 20; // Bits 31:12 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} GODLAT_CR_G_ODLAT_TR_IF_MODE_B6_B7_STRUCT; + +typedef union { + struct { + U32 B0_Set : 6; // Bits 5:0 + U32 B0_Rst : 6; // Bits 11:6 + U32 B1_Set : 6; // Bits 17:12 + U32 B1_Rst : 6; // Bits 23:18 + U32 : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_B0_B1_STRUCT; + +typedef union { + struct { + U32 B2_Set : 6; // Bits 5:0 + U32 B2_Rst : 6; // Bits 11:6 + U32 B3_Set : 6; // Bits 17:12 + U32 B3_Rst : 6; // Bits 23:18 + U32 : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_B2_B3_STRUCT; + +typedef union { + struct { + U32 B4_Set : 6; // Bits 5:0 + U32 B4_Rst : 6; // Bits 11:6 + U32 B5_Set : 6; // Bits 17:12 + U32 B5_Rst : 6; // Bits 23:18 + U32 : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_B4_B5_STRUCT; + +typedef union { + struct { + U32 ElseIf_ElseIf_B1_Set : 6; // Bits 5:0 + U32 ElseIf_ElseIf_B1_Rst : 6; // Bits 11:6 + U32 : 20; // Bits 31:12 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_B6_B7_STRUCT; + +typedef union { + struct { + U32 Init_Bits : 6; // Bits 5:0 + U32 : 26; // Bits 31:6 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} GODLAT_CR_G_ODLAT_INIT_BUBBLES_STRUCT; + +typedef union { + struct { + U32 ColRst : 6; // Bits 5:0 + U32 Start : 6; // Bits 11:6 + U32 Trigger : 6; // Bits 17:12 + U32 Stop : 6; // Bits 23:18 + U32 : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} GODLAT_CR_G_ODLAT_TR_IF_MODE_MISC_STRUCT; + +typedef union { + struct { + U32 ColRst : 6; // Bits 5:0 + U32 Start : 6; // Bits 11:6 + U32 Trigger : 6; // Bits 17:12 + U32 Stop : 6; // Bits 23:18 + U32 : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_MISC_STRUCT; + +typedef union { + struct { + U32 B0_EN : 4; // Bits 3:0 + U32 B1_EN : 4; // Bits 7:4 + U32 B2_EN : 4; // Bits 11:8 + U32 B3_EN : 4; // Bits 15:12 + U32 B4_EN : 4; // Bits 19:16 + U32 B5_EN : 4; // Bits 23:20 + U32 ELSEIF_ELSEIF_B0_EN : 4; // Bits 27:24 + U32 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} GODLAT_CR_G_ODLAT_TR_IF_MODE_TMREN_STRUCT; + +typedef union { + struct { + U32 B0_EN : 4; // Bits 3:0 + U32 B1_EN : 4; // Bits 7:4 + U32 B2_EN : 4; // Bits 11:8 + U32 B3_EN : 4; // Bits 15:12 + U32 B4_EN : 4; // Bits 19:16 + U32 B5_EN : 4; // Bits 23:20 + U32 ELSEIF_ELSEIF_B1_EN : 4; // Bits 27:24 + U32 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_TMREN_STRUCT; + +typedef union { + struct { + U32 Timer0_load : 5; // Bits 4:0 + U32 Timer1_load : 5; // Bits 9:5 + U32 Timer2_load : 5; // Bits 14:10 + U32 Timer3_load : 16; // Bits 30:15 + U32 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} GODLAT_CR_G_ODLAT_TIMER_PRELOAD_STRUCT; + +typedef union { + struct { + U32 MOT_PKT : 8; // Bits 7:0 + U32 : 24; // Bits 31:8 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} GODLAT_CR_G_ODLAT_MOT_HDR_HIT_STRUCT; + +typedef union { + struct { + U32 B0_RST : 4; // Bits 3:0 + U32 B1_RST : 4; // Bits 7:4 + U32 B2_RST : 4; // Bits 11:8 + U32 B3_RST : 4; // Bits 15:12 + U32 B4_RST : 4; // Bits 19:16 + U32 B5_RST : 4; // Bits 23:20 + U32 ELSEIF_ELSEIF_B0_RST : 4; // Bits 27:24 + U32 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} GODLAT_CR_G_ODLAT_TR_IF_MODE_TMRRST_STRUCT; + +typedef union { + struct { + U32 B0_RST : 4; // Bits 3:0 + U32 B1_RST : 4; // Bits 7:4 + U32 B2_RST : 4; // Bits 11:8 + U32 B3_RST : 4; // Bits 15:12 + U32 B4_RST : 4; // Bits 19:16 + U32 B5_RST : 4; // Bits 23:20 + U32 ELSEIF_ELSEIF_B1_RST : 4; // Bits 27:24 + U32 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_TMRRST_STRUCT; + +typedef union { + struct { + U32 SPARE : 8; // Bits 7:0 + U32 : 24; // Bits 31:8 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} GDXC_CR_DEBUP_STRUCT; + +typedef union { + struct { + U32 Ln0Src : 2; // Bits 1:0 + U32 Ln1Src : 2; // Bits 3:2 + U32 DEVisaEn : 1; // Bits 4:4 + U32 : 27; // Bits 31:5 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MSGUTILS_CR_VISA2OCLA_CFG_STRUCT; + +#define DDRPL_CR_DDR_TX_DELAY_REG (0x00000C04) + #define DDRPL_CR_DDR_TX_DELAY_Tx_Delay_R0_OFF ( 0) + #define DDRPL_CR_DDR_TX_DELAY_Tx_Delay_R0_WID ( 8) + #define DDRPL_CR_DDR_TX_DELAY_Tx_Delay_R0_MSK (0x000000FF) + #define DDRPL_CR_DDR_TX_DELAY_Tx_Delay_R0_MAX (0x000000FF) + #define DDRPL_CR_DDR_TX_DELAY_Tx_Delay_R0_DEF (0x00000010) + #define DDRPL_CR_DDR_TX_DELAY_Tx_Delay_R1_OFF ( 8) + #define DDRPL_CR_DDR_TX_DELAY_Tx_Delay_R1_WID ( 8) + #define DDRPL_CR_DDR_TX_DELAY_Tx_Delay_R1_MSK (0x0000FF00) + #define DDRPL_CR_DDR_TX_DELAY_Tx_Delay_R1_MAX (0x000000FF) + #define DDRPL_CR_DDR_TX_DELAY_Tx_Delay_R1_DEF (0x00000010) + #define DDRPL_CR_DDR_TX_DELAY_Tx_Delay_R2_OFF (16) + #define DDRPL_CR_DDR_TX_DELAY_Tx_Delay_R2_WID ( 8) + #define DDRPL_CR_DDR_TX_DELAY_Tx_Delay_R2_MSK (0x00FF0000) + #define DDRPL_CR_DDR_TX_DELAY_Tx_Delay_R2_MAX (0x000000FF) + #define DDRPL_CR_DDR_TX_DELAY_Tx_Delay_R2_DEF (0x00000010) + #define DDRPL_CR_DDR_TX_DELAY_Tx_Delay_R3_OFF (24) + #define DDRPL_CR_DDR_TX_DELAY_Tx_Delay_R3_WID ( 8) + #define DDRPL_CR_DDR_TX_DELAY_Tx_Delay_R3_MSK (0xFF000000) + #define DDRPL_CR_DDR_TX_DELAY_Tx_Delay_R3_MAX (0x000000FF) + #define DDRPL_CR_DDR_TX_DELAY_Tx_Delay_R3_DEF (0x00000010) + +#define MPCOHTRK_CR_GDXC_SW_ENABLE_REG (0x00000000) + #define MPCOHTRK_CR_GDXC_SW_ENABLE_EN_SW_GDXC_OFF ( 0) + #define MPCOHTRK_CR_GDXC_SW_ENABLE_EN_SW_GDXC_WID ( 1) + #define MPCOHTRK_CR_GDXC_SW_ENABLE_EN_SW_GDXC_MSK (0x00000001) + #define MPCOHTRK_CR_GDXC_SW_ENABLE_EN_SW_GDXC_MAX (0x00000001) + #define MPCOHTRK_CR_GDXC_SW_ENABLE_EN_SW_GDXC_DEF (0x00000000) + #define MPCOHTRK_CR_GDXC_SW_ENABLE_EN_RING_ADQ_OFF ( 1) + #define MPCOHTRK_CR_GDXC_SW_ENABLE_EN_RING_ADQ_WID ( 1) + #define MPCOHTRK_CR_GDXC_SW_ENABLE_EN_RING_ADQ_MSK (0x00000002) + #define MPCOHTRK_CR_GDXC_SW_ENABLE_EN_RING_ADQ_MAX (0x00000001) + #define MPCOHTRK_CR_GDXC_SW_ENABLE_EN_RING_ADQ_DEF (0x00000001) + #define MPCOHTRK_CR_GDXC_SW_ENABLE_EN_RING_BLQ_OFF ( 2) + #define MPCOHTRK_CR_GDXC_SW_ENABLE_EN_RING_BLQ_WID ( 1) + #define MPCOHTRK_CR_GDXC_SW_ENABLE_EN_RING_BLQ_MSK (0x00000004) + #define MPCOHTRK_CR_GDXC_SW_ENABLE_EN_RING_BLQ_MAX (0x00000001) + #define MPCOHTRK_CR_GDXC_SW_ENABLE_EN_RING_BLQ_DEF (0x00000001) + #define MPCOHTRK_CR_GDXC_SW_ENABLE_EN_RING_AKQ_OFF ( 3) + #define MPCOHTRK_CR_GDXC_SW_ENABLE_EN_RING_AKQ_WID ( 1) + #define MPCOHTRK_CR_GDXC_SW_ENABLE_EN_RING_AKQ_MSK (0x00000008) + #define MPCOHTRK_CR_GDXC_SW_ENABLE_EN_RING_AKQ_MAX (0x00000001) + #define MPCOHTRK_CR_GDXC_SW_ENABLE_EN_RING_AKQ_DEF (0x00000001) + #define MPCOHTRK_CR_GDXC_SW_ENABLE_EN_RING_IVQ_OFF ( 4) + #define MPCOHTRK_CR_GDXC_SW_ENABLE_EN_RING_IVQ_WID ( 1) + #define MPCOHTRK_CR_GDXC_SW_ENABLE_EN_RING_IVQ_MSK (0x00000010) + #define MPCOHTRK_CR_GDXC_SW_ENABLE_EN_RING_IVQ_MAX (0x00000001) + #define MPCOHTRK_CR_GDXC_SW_ENABLE_EN_RING_IVQ_DEF (0x00000001) + #define MPCOHTRK_CR_GDXC_SW_ENABLE_EN_IDIQ_OFF ( 5) + #define MPCOHTRK_CR_GDXC_SW_ENABLE_EN_IDIQ_WID ( 1) + #define MPCOHTRK_CR_GDXC_SW_ENABLE_EN_IDIQ_MSK (0x00000020) + #define MPCOHTRK_CR_GDXC_SW_ENABLE_EN_IDIQ_MAX (0x00000001) + #define MPCOHTRK_CR_GDXC_SW_ENABLE_EN_IDIQ_DEF (0x00000000) + #define MPCOHTRK_CR_GDXC_SW_ENABLE_EN_mc_UCLKQ_OFF ( 6) + #define MPCOHTRK_CR_GDXC_SW_ENABLE_EN_mc_UCLKQ_WID ( 1) + #define MPCOHTRK_CR_GDXC_SW_ENABLE_EN_mc_UCLKQ_MSK (0x00000040) + #define MPCOHTRK_CR_GDXC_SW_ENABLE_EN_mc_UCLKQ_MAX (0x00000001) + #define MPCOHTRK_CR_GDXC_SW_ENABLE_EN_mc_UCLKQ_DEF (0x00000001) + #define MPCOHTRK_CR_GDXC_SW_ENABLE_UP_EN_ADQ_OFF ( 8) + #define MPCOHTRK_CR_GDXC_SW_ENABLE_UP_EN_ADQ_WID ( 1) + #define MPCOHTRK_CR_GDXC_SW_ENABLE_UP_EN_ADQ_MSK (0x00000100) + #define MPCOHTRK_CR_GDXC_SW_ENABLE_UP_EN_ADQ_MAX (0x00000001) + #define MPCOHTRK_CR_GDXC_SW_ENABLE_UP_EN_ADQ_DEF (0x00000001) + #define MPCOHTRK_CR_GDXC_SW_ENABLE_DN_EN_ADQ_OFF ( 9) + #define MPCOHTRK_CR_GDXC_SW_ENABLE_DN_EN_ADQ_WID ( 1) + #define MPCOHTRK_CR_GDXC_SW_ENABLE_DN_EN_ADQ_MSK (0x00000200) + #define MPCOHTRK_CR_GDXC_SW_ENABLE_DN_EN_ADQ_MAX (0x00000001) + #define MPCOHTRK_CR_GDXC_SW_ENABLE_DN_EN_ADQ_DEF (0x00000001) + #define MPCOHTRK_CR_GDXC_SW_ENABLE_UP_EN_BLQ_OFF (10) + #define MPCOHTRK_CR_GDXC_SW_ENABLE_UP_EN_BLQ_WID ( 1) + #define MPCOHTRK_CR_GDXC_SW_ENABLE_UP_EN_BLQ_MSK (0x00000400) + #define MPCOHTRK_CR_GDXC_SW_ENABLE_UP_EN_BLQ_MAX (0x00000001) + #define MPCOHTRK_CR_GDXC_SW_ENABLE_UP_EN_BLQ_DEF (0x00000001) + #define MPCOHTRK_CR_GDXC_SW_ENABLE_DN_EN_BLQ_OFF (11) + #define MPCOHTRK_CR_GDXC_SW_ENABLE_DN_EN_BLQ_WID ( 1) + #define MPCOHTRK_CR_GDXC_SW_ENABLE_DN_EN_BLQ_MSK (0x00000800) + #define MPCOHTRK_CR_GDXC_SW_ENABLE_DN_EN_BLQ_MAX (0x00000001) + #define MPCOHTRK_CR_GDXC_SW_ENABLE_DN_EN_BLQ_DEF (0x00000001) + #define MPCOHTRK_CR_GDXC_SW_ENABLE_UP_EN_AKQ_OFF (12) + #define MPCOHTRK_CR_GDXC_SW_ENABLE_UP_EN_AKQ_WID ( 1) + #define MPCOHTRK_CR_GDXC_SW_ENABLE_UP_EN_AKQ_MSK (0x00001000) + #define MPCOHTRK_CR_GDXC_SW_ENABLE_UP_EN_AKQ_MAX (0x00000001) + #define MPCOHTRK_CR_GDXC_SW_ENABLE_UP_EN_AKQ_DEF (0x00000001) + #define MPCOHTRK_CR_GDXC_SW_ENABLE_DN_EN_AKQ_OFF (13) + #define MPCOHTRK_CR_GDXC_SW_ENABLE_DN_EN_AKQ_WID ( 1) + #define MPCOHTRK_CR_GDXC_SW_ENABLE_DN_EN_AKQ_MSK (0x00002000) + #define MPCOHTRK_CR_GDXC_SW_ENABLE_DN_EN_AKQ_MAX (0x00000001) + #define MPCOHTRK_CR_GDXC_SW_ENABLE_DN_EN_AKQ_DEF (0x00000001) + #define MPCOHTRK_CR_GDXC_SW_ENABLE_MOTQ_TIMING_SELECT_OFF (14) + #define MPCOHTRK_CR_GDXC_SW_ENABLE_MOTQ_TIMING_SELECT_WID ( 1) + #define MPCOHTRK_CR_GDXC_SW_ENABLE_MOTQ_TIMING_SELECT_MSK (0x00004000) + #define MPCOHTRK_CR_GDXC_SW_ENABLE_MOTQ_TIMING_SELECT_MAX (0x00000001) + #define MPCOHTRK_CR_GDXC_SW_ENABLE_MOTQ_TIMING_SELECT_DEF (0x00000000) + #define MPCOHTRK_CR_GDXC_SW_ENABLE_SPARE_OFF (16) + #define MPCOHTRK_CR_GDXC_SW_ENABLE_SPARE_WID ( 8) + #define MPCOHTRK_CR_GDXC_SW_ENABLE_SPARE_MSK (0x00FF0000) + #define MPCOHTRK_CR_GDXC_SW_ENABLE_SPARE_MAX (0x000000FF) + #define MPCOHTRK_CR_GDXC_SW_ENABLE_SPARE_DEF (0x00000000) + +#define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_REG (0x00000004) + #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_EN_Core0_T0_OFF ( 0) + #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_EN_Core0_T0_WID ( 1) + #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_EN_Core0_T0_MSK (0x00000001) + #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_EN_Core0_T0_MAX (0x00000001) + #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_EN_Core0_T0_DEF (0x00000001) + #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_EN_Core0_T1_OFF ( 1) + #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_EN_Core0_T1_WID ( 1) + #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_EN_Core0_T1_MSK (0x00000002) + #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_EN_Core0_T1_MAX (0x00000001) + #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_EN_Core0_T1_DEF (0x00000001) + #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_EN_Core1_T0_OFF ( 2) + #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_EN_Core1_T0_WID ( 1) + #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_EN_Core1_T0_MSK (0x00000004) + #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_EN_Core1_T0_MAX (0x00000001) + #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_EN_Core1_T0_DEF (0x00000001) + #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_EN_Core1_T1_OFF ( 3) + #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_EN_Core1_T1_WID ( 1) + #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_EN_Core1_T1_MSK (0x00000008) + #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_EN_Core1_T1_MAX (0x00000001) + #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_EN_Core1_T1_DEF (0x00000001) + #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_EN_Core2_T0_OFF ( 4) + #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_EN_Core2_T0_WID ( 1) + #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_EN_Core2_T0_MSK (0x00000010) + #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_EN_Core2_T0_MAX (0x00000001) + #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_EN_Core2_T0_DEF (0x00000001) + #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_EN_Core2_T1_OFF ( 5) + #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_EN_Core2_T1_WID ( 1) + #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_EN_Core2_T1_MSK (0x00000020) + #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_EN_Core2_T1_MAX (0x00000001) + #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_EN_Core2_T1_DEF (0x00000001) + #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_EN_Core3_T0_OFF ( 6) + #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_EN_Core3_T0_WID ( 1) + #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_EN_Core3_T0_MSK (0x00000040) + #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_EN_Core3_T0_MAX (0x00000001) + #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_EN_Core3_T0_DEF (0x00000001) + #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_EN_Core3_T1_OFF ( 7) + #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_EN_Core3_T1_WID ( 1) + #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_EN_Core3_T1_MSK (0x00000080) + #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_EN_Core3_T1_MAX (0x00000001) + #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_EN_Core3_T1_DEF (0x00000001) + #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_EN_GT_OFF ( 8) + #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_EN_GT_WID ( 1) + #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_EN_GT_MSK (0x00000100) + #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_EN_GT_MAX (0x00000001) + #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_EN_GT_DEF (0x00000000) + #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_MEM_CHR_RD_OFF ( 9) + #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_MEM_CHR_RD_WID ( 1) + #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_MEM_CHR_RD_MSK (0x00000200) + #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_MEM_CHR_RD_MAX (0x00000001) + #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_MEM_CHR_RD_DEF (0x00000001) + #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_MEM_CHR_WR_OFF (10) + #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_MEM_CHR_WR_WID ( 1) + #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_MEM_CHR_WR_MSK (0x00000400) + #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_MEM_CHR_WR_MAX (0x00000001) + #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_MEM_CHR_WR_DEF (0x00000001) + #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_MEM_NC_OFF (11) + #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_MEM_NC_WID ( 1) + #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_MEM_NC_MSK (0x00000800) + #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_MEM_NC_MAX (0x00000001) + #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_MEM_NC_DEF (0x00000001) + #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_EN_CBO_Exp_WB_OFF (12) + #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_EN_CBO_Exp_WB_WID ( 1) + #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_EN_CBO_Exp_WB_MSK (0x00001000) + #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_EN_CBO_Exp_WB_MAX (0x00000001) + #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_EN_CBO_Exp_WB_DEF (0x00000000) + #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_SNP_Access_OFF (13) + #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_SNP_Access_WID ( 1) + #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_SNP_Access_MSK (0x00002000) + #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_SNP_Access_MAX (0x00000001) + #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_SNP_Access_DEF (0x00000001) + #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_AD_EODLAT_OFF (14) + #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_AD_EODLAT_WID ( 1) + #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_AD_EODLAT_MSK (0x00004000) + #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_AD_EODLAT_MAX (0x00000001) + #define MPCOHTRK_CR_GDXC_QUALIFIER_GLOBAL_AD_EODLAT_DEF (0x00000001) + +#define MPCOHTRK_CR_GDXC_QUALIFIER_BL_REG (0x00000008) + #define MPCOHTRK_CR_GDXC_QUALIFIER_BL_CR_CHR_RD_OFF ( 0) + #define MPCOHTRK_CR_GDXC_QUALIFIER_BL_CR_CHR_RD_WID ( 3) + #define MPCOHTRK_CR_GDXC_QUALIFIER_BL_CR_CHR_RD_MSK (0x00000007) + #define MPCOHTRK_CR_GDXC_QUALIFIER_BL_CR_CHR_RD_MAX (0x00000007) + #define MPCOHTRK_CR_GDXC_QUALIFIER_BL_CR_CHR_RD_DEF (0x00000000) + #define MPCOHTRK_CR_GDXC_QUALIFIER_BL_CHR_RD_STAT_MOD_OFF ( 3) + #define MPCOHTRK_CR_GDXC_QUALIFIER_BL_CHR_RD_STAT_MOD_WID ( 1) + #define MPCOHTRK_CR_GDXC_QUALIFIER_BL_CHR_RD_STAT_MOD_MSK (0x00000008) + #define MPCOHTRK_CR_GDXC_QUALIFIER_BL_CHR_RD_STAT_MOD_MAX (0x00000001) + #define MPCOHTRK_CR_GDXC_QUALIFIER_BL_CHR_RD_STAT_MOD_DEF (0x00000001) + #define MPCOHTRK_CR_GDXC_QUALIFIER_BL_CR_CHR_WR_OFF ( 4) + #define MPCOHTRK_CR_GDXC_QUALIFIER_BL_CR_CHR_WR_WID ( 4) + #define MPCOHTRK_CR_GDXC_QUALIFIER_BL_CR_CHR_WR_MSK (0x000000F0) + #define MPCOHTRK_CR_GDXC_QUALIFIER_BL_CR_CHR_WR_MAX (0x0000000F) + #define MPCOHTRK_CR_GDXC_QUALIFIER_BL_CR_CHR_WR_DEF (0x00000000) + #define MPCOHTRK_CR_GDXC_QUALIFIER_BL_CR_NC_RD_OFF ( 8) + #define MPCOHTRK_CR_GDXC_QUALIFIER_BL_CR_NC_RD_WID ( 3) + #define MPCOHTRK_CR_GDXC_QUALIFIER_BL_CR_NC_RD_MSK (0x00000700) + #define MPCOHTRK_CR_GDXC_QUALIFIER_BL_CR_NC_RD_MAX (0x00000007) + #define MPCOHTRK_CR_GDXC_QUALIFIER_BL_CR_NC_RD_DEF (0x00000000) + #define MPCOHTRK_CR_GDXC_QUALIFIER_BL_NC_RD_STAT_MOD_OFF (11) + #define MPCOHTRK_CR_GDXC_QUALIFIER_BL_NC_RD_STAT_MOD_WID ( 1) + #define MPCOHTRK_CR_GDXC_QUALIFIER_BL_NC_RD_STAT_MOD_MSK (0x00000800) + #define MPCOHTRK_CR_GDXC_QUALIFIER_BL_NC_RD_STAT_MOD_MAX (0x00000001) + #define MPCOHTRK_CR_GDXC_QUALIFIER_BL_NC_RD_STAT_MOD_DEF (0x00000001) + #define MPCOHTRK_CR_GDXC_QUALIFIER_BL_CR_NC_WR_OFF (12) + #define MPCOHTRK_CR_GDXC_QUALIFIER_BL_CR_NC_WR_WID ( 4) + #define MPCOHTRK_CR_GDXC_QUALIFIER_BL_CR_NC_WR_MSK (0x0000F000) + #define MPCOHTRK_CR_GDXC_QUALIFIER_BL_CR_NC_WR_MAX (0x0000000F) + #define MPCOHTRK_CR_GDXC_QUALIFIER_BL_CR_NC_WR_DEF (0x00000000) + #define MPCOHTRK_CR_GDXC_QUALIFIER_BL_NC_WR_STAT_MOD_OFF (16) + #define MPCOHTRK_CR_GDXC_QUALIFIER_BL_NC_WR_STAT_MOD_WID ( 1) + #define MPCOHTRK_CR_GDXC_QUALIFIER_BL_NC_WR_STAT_MOD_MSK (0x00010000) + #define MPCOHTRK_CR_GDXC_QUALIFIER_BL_NC_WR_STAT_MOD_MAX (0x00000001) + #define MPCOHTRK_CR_GDXC_QUALIFIER_BL_NC_WR_STAT_MOD_DEF (0x00000001) + #define MPCOHTRK_CR_GDXC_QUALIFIER_BL_Data_Core0_OFF (17) + #define MPCOHTRK_CR_GDXC_QUALIFIER_BL_Data_Core0_WID ( 1) + #define MPCOHTRK_CR_GDXC_QUALIFIER_BL_Data_Core0_MSK (0x00020000) + #define MPCOHTRK_CR_GDXC_QUALIFIER_BL_Data_Core0_MAX (0x00000001) + #define MPCOHTRK_CR_GDXC_QUALIFIER_BL_Data_Core0_DEF (0x00000000) + #define MPCOHTRK_CR_GDXC_QUALIFIER_BL_Data_Core1_OFF (18) + #define MPCOHTRK_CR_GDXC_QUALIFIER_BL_Data_Core1_WID ( 1) + #define MPCOHTRK_CR_GDXC_QUALIFIER_BL_Data_Core1_MSK (0x00040000) + #define MPCOHTRK_CR_GDXC_QUALIFIER_BL_Data_Core1_MAX (0x00000001) + #define MPCOHTRK_CR_GDXC_QUALIFIER_BL_Data_Core1_DEF (0x00000000) + #define MPCOHTRK_CR_GDXC_QUALIFIER_BL_Data_Core2_OFF (19) + #define MPCOHTRK_CR_GDXC_QUALIFIER_BL_Data_Core2_WID ( 1) + #define MPCOHTRK_CR_GDXC_QUALIFIER_BL_Data_Core2_MSK (0x00080000) + #define MPCOHTRK_CR_GDXC_QUALIFIER_BL_Data_Core2_MAX (0x00000001) + #define MPCOHTRK_CR_GDXC_QUALIFIER_BL_Data_Core2_DEF (0x00000000) + #define MPCOHTRK_CR_GDXC_QUALIFIER_BL_Data_Core3_OFF (20) + #define MPCOHTRK_CR_GDXC_QUALIFIER_BL_Data_Core3_WID ( 1) + #define MPCOHTRK_CR_GDXC_QUALIFIER_BL_Data_Core3_MSK (0x00100000) + #define MPCOHTRK_CR_GDXC_QUALIFIER_BL_Data_Core3_MAX (0x00000001) + #define MPCOHTRK_CR_GDXC_QUALIFIER_BL_Data_Core3_DEF (0x00000000) + #define MPCOHTRK_CR_GDXC_QUALIFIER_BL_Data_CBO_OFF (21) + #define MPCOHTRK_CR_GDXC_QUALIFIER_BL_Data_CBO_WID ( 1) + #define MPCOHTRK_CR_GDXC_QUALIFIER_BL_Data_CBO_MSK (0x00200000) + #define MPCOHTRK_CR_GDXC_QUALIFIER_BL_Data_CBO_MAX (0x00000001) + #define MPCOHTRK_CR_GDXC_QUALIFIER_BL_Data_CBO_DEF (0x00000000) + #define MPCOHTRK_CR_GDXC_QUALIFIER_BL_Data_GT_OFF (22) + #define MPCOHTRK_CR_GDXC_QUALIFIER_BL_Data_GT_WID ( 1) + #define MPCOHTRK_CR_GDXC_QUALIFIER_BL_Data_GT_MSK (0x00400000) + #define MPCOHTRK_CR_GDXC_QUALIFIER_BL_Data_GT_MAX (0x00000001) + #define MPCOHTRK_CR_GDXC_QUALIFIER_BL_Data_GT_DEF (0x00000000) + +#define MPCOHTRK_CR_GDXC_OVF_STATUS_REG (0x0000000C) + #define MPCOHTRK_CR_GDXC_OVF_STATUS_OVF_Global_OFF ( 0) + #define MPCOHTRK_CR_GDXC_OVF_STATUS_OVF_Global_WID ( 1) + #define MPCOHTRK_CR_GDXC_OVF_STATUS_OVF_Global_MSK (0x00000001) + #define MPCOHTRK_CR_GDXC_OVF_STATUS_OVF_Global_MAX (0x00000001) + #define MPCOHTRK_CR_GDXC_OVF_STATUS_OVF_Global_DEF (0x00000000) + #define MPCOHTRK_CR_GDXC_OVF_STATUS_OVF_Ring_AD_OFF ( 1) + #define MPCOHTRK_CR_GDXC_OVF_STATUS_OVF_Ring_AD_WID ( 1) + #define MPCOHTRK_CR_GDXC_OVF_STATUS_OVF_Ring_AD_MSK (0x00000002) + #define MPCOHTRK_CR_GDXC_OVF_STATUS_OVF_Ring_AD_MAX (0x00000001) + #define MPCOHTRK_CR_GDXC_OVF_STATUS_OVF_Ring_AD_DEF (0x00000000) + #define MPCOHTRK_CR_GDXC_OVF_STATUS_OVF_Ring_BL_OFF ( 2) + #define MPCOHTRK_CR_GDXC_OVF_STATUS_OVF_Ring_BL_WID ( 1) + #define MPCOHTRK_CR_GDXC_OVF_STATUS_OVF_Ring_BL_MSK (0x00000004) + #define MPCOHTRK_CR_GDXC_OVF_STATUS_OVF_Ring_BL_MAX (0x00000001) + #define MPCOHTRK_CR_GDXC_OVF_STATUS_OVF_Ring_BL_DEF (0x00000000) + #define MPCOHTRK_CR_GDXC_OVF_STATUS_OVF_Ring_AK_OFF ( 3) + #define MPCOHTRK_CR_GDXC_OVF_STATUS_OVF_Ring_AK_WID ( 1) + #define MPCOHTRK_CR_GDXC_OVF_STATUS_OVF_Ring_AK_MSK (0x00000008) + #define MPCOHTRK_CR_GDXC_OVF_STATUS_OVF_Ring_AK_MAX (0x00000001) + #define MPCOHTRK_CR_GDXC_OVF_STATUS_OVF_Ring_AK_DEF (0x00000000) + #define MPCOHTRK_CR_GDXC_OVF_STATUS_OVF_Ring_IV_OFF ( 4) + #define MPCOHTRK_CR_GDXC_OVF_STATUS_OVF_Ring_IV_WID ( 1) + #define MPCOHTRK_CR_GDXC_OVF_STATUS_OVF_Ring_IV_MSK (0x00000010) + #define MPCOHTRK_CR_GDXC_OVF_STATUS_OVF_Ring_IV_MAX (0x00000001) + #define MPCOHTRK_CR_GDXC_OVF_STATUS_OVF_Ring_IV_DEF (0x00000000) + #define MPCOHTRK_CR_GDXC_OVF_STATUS_OVF_IDI_center_OFF ( 9) + #define MPCOHTRK_CR_GDXC_OVF_STATUS_OVF_IDI_center_WID ( 1) + #define MPCOHTRK_CR_GDXC_OVF_STATUS_OVF_IDI_center_MSK (0x00000200) + #define MPCOHTRK_CR_GDXC_OVF_STATUS_OVF_IDI_center_MAX (0x00000001) + #define MPCOHTRK_CR_GDXC_OVF_STATUS_OVF_IDI_center_DEF (0x00000000) + #define MPCOHTRK_CR_GDXC_OVF_STATUS_OVF_mcUCLK_OFF (10) + #define MPCOHTRK_CR_GDXC_OVF_STATUS_OVF_mcUCLK_WID ( 1) + #define MPCOHTRK_CR_GDXC_OVF_STATUS_OVF_mcUCLK_MSK (0x00000400) + #define MPCOHTRK_CR_GDXC_OVF_STATUS_OVF_mcUCLK_MAX (0x00000001) + #define MPCOHTRK_CR_GDXC_OVF_STATUS_OVF_mcUCLK_DEF (0x00000000) + #define MPCOHTRK_CR_GDXC_OVF_STATUS_OVF_PWR_mcFCLK_OFF (11) + #define MPCOHTRK_CR_GDXC_OVF_STATUS_OVF_PWR_mcFCLK_WID ( 1) + #define MPCOHTRK_CR_GDXC_OVF_STATUS_OVF_PWR_mcFCLK_MSK (0x00000800) + #define MPCOHTRK_CR_GDXC_OVF_STATUS_OVF_PWR_mcFCLK_MAX (0x00000001) + #define MPCOHTRK_CR_GDXC_OVF_STATUS_OVF_PWR_mcFCLK_DEF (0x00000000) + +#define MPCOHTRK_CR_GDXC_MOT_ADDRESS_LO_REG (0x00000010) + #define MPCOHTRK_CR_GDXC_MOT_ADDRESS_LO_MEM_PTR_OFF ( 0) + #define MPCOHTRK_CR_GDXC_MOT_ADDRESS_LO_MEM_PTR_WID (32) + #define MPCOHTRK_CR_GDXC_MOT_ADDRESS_LO_MEM_PTR_MSK (0xFFFFFFFF) + #define MPCOHTRK_CR_GDXC_MOT_ADDRESS_LO_MEM_PTR_MAX (0xFFFFFFFF) + #define MPCOHTRK_CR_GDXC_MOT_ADDRESS_LO_MEM_PTR_DEF (0x00000000) + +#define MPCOHTRK_CR_GDXC_MOT_ADDRESS_HI_REG (0x00000014) + #define MPCOHTRK_CR_GDXC_MOT_ADDRESS_HI_MEM_PTR_OFF ( 0) + #define MPCOHTRK_CR_GDXC_MOT_ADDRESS_HI_MEM_PTR_WID ( 1) + #define MPCOHTRK_CR_GDXC_MOT_ADDRESS_HI_MEM_PTR_MSK (0x00000001) + #define MPCOHTRK_CR_GDXC_MOT_ADDRESS_HI_MEM_PTR_MAX (0x00000001) + #define MPCOHTRK_CR_GDXC_MOT_ADDRESS_HI_MEM_PTR_DEF (0x00000000) + #define MPCOHTRK_CR_GDXC_MOT_ADDRESS_HI_BUFFER_WRAP_OFF ( 1) + #define MPCOHTRK_CR_GDXC_MOT_ADDRESS_HI_BUFFER_WRAP_WID ( 1) + #define MPCOHTRK_CR_GDXC_MOT_ADDRESS_HI_BUFFER_WRAP_MSK (0x00000002) + #define MPCOHTRK_CR_GDXC_MOT_ADDRESS_HI_BUFFER_WRAP_MAX (0x00000001) + #define MPCOHTRK_CR_GDXC_MOT_ADDRESS_HI_BUFFER_WRAP_DEF (0x00000000) + #define MPCOHTRK_CR_GDXC_MOT_ADDRESS_HI_SPARE_OFF ( 2) + #define MPCOHTRK_CR_GDXC_MOT_ADDRESS_HI_SPARE_WID (30) + #define MPCOHTRK_CR_GDXC_MOT_ADDRESS_HI_SPARE_MSK (0xFFFFFFFC) + #define MPCOHTRK_CR_GDXC_MOT_ADDRESS_HI_SPARE_MAX (0x3FFFFFFF) + #define MPCOHTRK_CR_GDXC_MOT_ADDRESS_HI_SPARE_DEF (0x00000000) + +#define MPCOHTRK_CR_GDXC_MOT_REGION_REG (0x00000018) + #define MPCOHTRK_CR_GDXC_MOT_REGION_START_ADDRESS_OFF ( 0) + #define MPCOHTRK_CR_GDXC_MOT_REGION_START_ADDRESS_WID (16) + #define MPCOHTRK_CR_GDXC_MOT_REGION_START_ADDRESS_MSK (0x0000FFFF) + #define MPCOHTRK_CR_GDXC_MOT_REGION_START_ADDRESS_MAX (0x0000FFFF) + #define MPCOHTRK_CR_GDXC_MOT_REGION_START_ADDRESS_DEF (0x00000000) + #define MPCOHTRK_CR_GDXC_MOT_REGION_END_ADDRESS_OFF (16) + #define MPCOHTRK_CR_GDXC_MOT_REGION_END_ADDRESS_WID (16) + #define MPCOHTRK_CR_GDXC_MOT_REGION_END_ADDRESS_MSK (0xFFFF0000) + #define MPCOHTRK_CR_GDXC_MOT_REGION_END_ADDRESS_MAX (0x0000FFFF) + #define MPCOHTRK_CR_GDXC_MOT_REGION_END_ADDRESS_DEF (0x00000001) + +#define MPCOHTRK_CR_GDXC_OCLA_ADDRESS_LO_REG (0x00000020) + #define MPCOHTRK_CR_GDXC_OCLA_ADDRESS_LO_MEM_PTR_OFF ( 0) + #define MPCOHTRK_CR_GDXC_OCLA_ADDRESS_LO_MEM_PTR_WID (32) + #define MPCOHTRK_CR_GDXC_OCLA_ADDRESS_LO_MEM_PTR_MSK (0xFFFFFFFF) + #define MPCOHTRK_CR_GDXC_OCLA_ADDRESS_LO_MEM_PTR_MAX (0xFFFFFFFF) + #define MPCOHTRK_CR_GDXC_OCLA_ADDRESS_LO_MEM_PTR_DEF (0x00000000) + +#define MPCOHTRK_CR_GDXC_OCLA_ADDRESS_HI_REG (0x00000024) + #define MPCOHTRK_CR_GDXC_OCLA_ADDRESS_HI_MEM_PTR_OFF ( 0) + #define MPCOHTRK_CR_GDXC_OCLA_ADDRESS_HI_MEM_PTR_WID ( 1) + #define MPCOHTRK_CR_GDXC_OCLA_ADDRESS_HI_MEM_PTR_MSK (0x00000001) + #define MPCOHTRK_CR_GDXC_OCLA_ADDRESS_HI_MEM_PTR_MAX (0x00000001) + #define MPCOHTRK_CR_GDXC_OCLA_ADDRESS_HI_MEM_PTR_DEF (0x00000000) + #define MPCOHTRK_CR_GDXC_OCLA_ADDRESS_HI_BUFFER_WRAP_OFF ( 1) + #define MPCOHTRK_CR_GDXC_OCLA_ADDRESS_HI_BUFFER_WRAP_WID ( 1) + #define MPCOHTRK_CR_GDXC_OCLA_ADDRESS_HI_BUFFER_WRAP_MSK (0x00000002) + #define MPCOHTRK_CR_GDXC_OCLA_ADDRESS_HI_BUFFER_WRAP_MAX (0x00000001) + #define MPCOHTRK_CR_GDXC_OCLA_ADDRESS_HI_BUFFER_WRAP_DEF (0x00000000) + #define MPCOHTRK_CR_GDXC_OCLA_ADDRESS_HI_LOCK_OFF ( 2) + #define MPCOHTRK_CR_GDXC_OCLA_ADDRESS_HI_LOCK_WID ( 1) + #define MPCOHTRK_CR_GDXC_OCLA_ADDRESS_HI_LOCK_MSK (0x00000004) + #define MPCOHTRK_CR_GDXC_OCLA_ADDRESS_HI_LOCK_MAX (0x00000001) + #define MPCOHTRK_CR_GDXC_OCLA_ADDRESS_HI_LOCK_DEF (0x00000000) + #define MPCOHTRK_CR_GDXC_OCLA_ADDRESS_HI_SPARE_OFF ( 3) + #define MPCOHTRK_CR_GDXC_OCLA_ADDRESS_HI_SPARE_WID (29) + #define MPCOHTRK_CR_GDXC_OCLA_ADDRESS_HI_SPARE_MSK (0xFFFFFFF8) + #define MPCOHTRK_CR_GDXC_OCLA_ADDRESS_HI_SPARE_MAX (0x1FFFFFFF) + #define MPCOHTRK_CR_GDXC_OCLA_ADDRESS_HI_SPARE_DEF (0x00000000) + +#define MPCOHTRK_CR_GDXC_OCLA_REGION_REG (0x00000028) + #define MPCOHTRK_CR_GDXC_OCLA_REGION_START_ADDRESS_OFF ( 0) + #define MPCOHTRK_CR_GDXC_OCLA_REGION_START_ADDRESS_WID (16) + #define MPCOHTRK_CR_GDXC_OCLA_REGION_START_ADDRESS_MSK (0x0000FFFF) + #define MPCOHTRK_CR_GDXC_OCLA_REGION_START_ADDRESS_MAX (0x0000FFFF) + #define MPCOHTRK_CR_GDXC_OCLA_REGION_START_ADDRESS_DEF (0x00000000) + #define MPCOHTRK_CR_GDXC_OCLA_REGION_END_ADDRESS_OFF (16) + #define MPCOHTRK_CR_GDXC_OCLA_REGION_END_ADDRESS_WID (16) + #define MPCOHTRK_CR_GDXC_OCLA_REGION_END_ADDRESS_MSK (0xFFFF0000) + #define MPCOHTRK_CR_GDXC_OCLA_REGION_END_ADDRESS_MAX (0x0000FFFF) + #define MPCOHTRK_CR_GDXC_OCLA_REGION_END_ADDRESS_DEF (0x00000001) + +#define GODLAT_CR_G_ODLAT_ARM_S0L_REG (0x00000400) + #define GODLAT_CR_G_ODLAT_ARM_S0L_ARM_bits_packet_OFF ( 0) + #define GODLAT_CR_G_ODLAT_ARM_S0L_ARM_bits_packet_WID (32) + #define GODLAT_CR_G_ODLAT_ARM_S0L_ARM_bits_packet_MSK (0xFFFFFFFF) + #define GODLAT_CR_G_ODLAT_ARM_S0L_ARM_bits_packet_MAX (0xFFFFFFFF) + +#define GODLAT_CR_G_ODLAT_ARM_S0H_REG (0x00000404) + #define GODLAT_CR_G_ODLAT_ARM_S0H_ARM_bits_packet_OFF ( 0) + #define GODLAT_CR_G_ODLAT_ARM_S0H_ARM_bits_packet_WID (32) + #define GODLAT_CR_G_ODLAT_ARM_S0H_ARM_bits_packet_MSK (0xFFFFFFFF) + #define GODLAT_CR_G_ODLAT_ARM_S0H_ARM_bits_packet_MAX (0xFFFFFFFF) + +#define GODLAT_CR_G_ODLAT_MASK_S0L_REG (0x00000408) + #define GODLAT_CR_G_ODLAT_MASK_S0L_Mask_bits_OFF ( 0) + #define GODLAT_CR_G_ODLAT_MASK_S0L_Mask_bits_WID (32) + #define GODLAT_CR_G_ODLAT_MASK_S0L_Mask_bits_MSK (0xFFFFFFFF) + #define GODLAT_CR_G_ODLAT_MASK_S0L_Mask_bits_MAX (0xFFFFFFFF) + +#define GODLAT_CR_G_ODLAT_MASK_S0H_REG (0x0000040C) + #define GODLAT_CR_G_ODLAT_MASK_S0H_Mask_bits_OFF ( 0) + #define GODLAT_CR_G_ODLAT_MASK_S0H_Mask_bits_WID (32) + #define GODLAT_CR_G_ODLAT_MASK_S0H_Mask_bits_MSK (0xFFFFFFFF) + #define GODLAT_CR_G_ODLAT_MASK_S0H_Mask_bits_MAX (0xFFFFFFFF) + +#define GODLAT_CR_G_ODLAT_ARM_S1L_REG (0x00000410) + #define GODLAT_CR_G_ODLAT_ARM_S1L_ARM_bits_packet_OFF ( 0) + #define GODLAT_CR_G_ODLAT_ARM_S1L_ARM_bits_packet_WID (32) + #define GODLAT_CR_G_ODLAT_ARM_S1L_ARM_bits_packet_MSK (0xFFFFFFFF) + #define GODLAT_CR_G_ODLAT_ARM_S1L_ARM_bits_packet_MAX (0xFFFFFFFF) + +#define GODLAT_CR_G_ODLAT_ARM_S1H_REG (0x00000414) + #define GODLAT_CR_G_ODLAT_ARM_S1H_ARM_bits_packet_OFF ( 0) + #define GODLAT_CR_G_ODLAT_ARM_S1H_ARM_bits_packet_WID (32) + #define GODLAT_CR_G_ODLAT_ARM_S1H_ARM_bits_packet_MSK (0xFFFFFFFF) + #define GODLAT_CR_G_ODLAT_ARM_S1H_ARM_bits_packet_MAX (0xFFFFFFFF) + +#define GODLAT_CR_G_ODLAT_MASK_S1L_REG (0x00000418) + #define GODLAT_CR_G_ODLAT_MASK_S1L_Mask_bits_OFF ( 0) + #define GODLAT_CR_G_ODLAT_MASK_S1L_Mask_bits_WID (32) + #define GODLAT_CR_G_ODLAT_MASK_S1L_Mask_bits_MSK (0xFFFFFFFF) + #define GODLAT_CR_G_ODLAT_MASK_S1L_Mask_bits_MAX (0xFFFFFFFF) + +#define GODLAT_CR_G_ODLAT_MASK_S1H_REG (0x0000041C) + #define GODLAT_CR_G_ODLAT_MASK_S1H_Mask_bits_OFF ( 0) + #define GODLAT_CR_G_ODLAT_MASK_S1H_Mask_bits_WID (32) + #define GODLAT_CR_G_ODLAT_MASK_S1H_Mask_bits_MSK (0xFFFFFFFF) + #define GODLAT_CR_G_ODLAT_MASK_S1H_Mask_bits_MAX (0xFFFFFFFF) + +#define GODLAT_CR_G_ODLAT_ARM_S2L_REG (0x00000420) + #define GODLAT_CR_G_ODLAT_ARM_S2L_ARM_bits_packet_OFF ( 0) + #define GODLAT_CR_G_ODLAT_ARM_S2L_ARM_bits_packet_WID (32) + #define GODLAT_CR_G_ODLAT_ARM_S2L_ARM_bits_packet_MSK (0xFFFFFFFF) + #define GODLAT_CR_G_ODLAT_ARM_S2L_ARM_bits_packet_MAX (0xFFFFFFFF) + +#define GODLAT_CR_G_ODLAT_ARM_S2H_REG (0x00000424) + #define GODLAT_CR_G_ODLAT_ARM_S2H_ARM_bits_packet_OFF ( 0) + #define GODLAT_CR_G_ODLAT_ARM_S2H_ARM_bits_packet_WID (32) + #define GODLAT_CR_G_ODLAT_ARM_S2H_ARM_bits_packet_MSK (0xFFFFFFFF) + #define GODLAT_CR_G_ODLAT_ARM_S2H_ARM_bits_packet_MAX (0xFFFFFFFF) + +#define GODLAT_CR_G_ODLAT_MASK_S2L_REG (0x00000428) + #define GODLAT_CR_G_ODLAT_MASK_S2L_Mask_bits_OFF ( 0) + #define GODLAT_CR_G_ODLAT_MASK_S2L_Mask_bits_WID (32) + #define GODLAT_CR_G_ODLAT_MASK_S2L_Mask_bits_MSK (0xFFFFFFFF) + #define GODLAT_CR_G_ODLAT_MASK_S2L_Mask_bits_MAX (0xFFFFFFFF) + +#define GODLAT_CR_G_ODLAT_MASK_S2H_REG (0x0000042C) + #define GODLAT_CR_G_ODLAT_MASK_S2H_Mask_bits_OFF ( 0) + #define GODLAT_CR_G_ODLAT_MASK_S2H_Mask_bits_WID (32) + #define GODLAT_CR_G_ODLAT_MASK_S2H_Mask_bits_MSK (0xFFFFFFFF) + #define GODLAT_CR_G_ODLAT_MASK_S2H_Mask_bits_MAX (0xFFFFFFFF) + +#define GODLAT_CR_G_ODLAT_ARM_S3L_REG (0x00000430) + #define GODLAT_CR_G_ODLAT_ARM_S3L_ARM_bits_packet_OFF ( 0) + #define GODLAT_CR_G_ODLAT_ARM_S3L_ARM_bits_packet_WID (32) + #define GODLAT_CR_G_ODLAT_ARM_S3L_ARM_bits_packet_MSK (0xFFFFFFFF) + #define GODLAT_CR_G_ODLAT_ARM_S3L_ARM_bits_packet_MAX (0xFFFFFFFF) + +#define GODLAT_CR_G_ODLAT_ARM_S3H_REG (0x00000434) + #define GODLAT_CR_G_ODLAT_ARM_S3H_ARM_bits_packet_OFF ( 0) + #define GODLAT_CR_G_ODLAT_ARM_S3H_ARM_bits_packet_WID (32) + #define GODLAT_CR_G_ODLAT_ARM_S3H_ARM_bits_packet_MSK (0xFFFFFFFF) + #define GODLAT_CR_G_ODLAT_ARM_S3H_ARM_bits_packet_MAX (0xFFFFFFFF) + +#define GODLAT_CR_G_ODLAT_MASK_S3L_REG (0x00000438) + #define GODLAT_CR_G_ODLAT_MASK_S3L_Mask_bits_OFF ( 0) + #define GODLAT_CR_G_ODLAT_MASK_S3L_Mask_bits_WID (32) + #define GODLAT_CR_G_ODLAT_MASK_S3L_Mask_bits_MSK (0xFFFFFFFF) + #define GODLAT_CR_G_ODLAT_MASK_S3L_Mask_bits_MAX (0xFFFFFFFF) + +#define GODLAT_CR_G_ODLAT_MASK_S3H_REG (0x0000043C) + #define GODLAT_CR_G_ODLAT_MASK_S3H_Mask_bits_OFF ( 0) + #define GODLAT_CR_G_ODLAT_MASK_S3H_Mask_bits_WID (32) + #define GODLAT_CR_G_ODLAT_MASK_S3H_Mask_bits_MSK (0xFFFFFFFF) + #define GODLAT_CR_G_ODLAT_MASK_S3H_Mask_bits_MAX (0xFFFFFFFF) + +#define GODLAT_CR_G_ODLAT_ARM_S4L_REG (0x00000440) + #define GODLAT_CR_G_ODLAT_ARM_S4L_ARM_bits_packet_OFF ( 0) + #define GODLAT_CR_G_ODLAT_ARM_S4L_ARM_bits_packet_WID (32) + #define GODLAT_CR_G_ODLAT_ARM_S4L_ARM_bits_packet_MSK (0xFFFFFFFF) + #define GODLAT_CR_G_ODLAT_ARM_S4L_ARM_bits_packet_MAX (0xFFFFFFFF) + +#define GODLAT_CR_G_ODLAT_ARM_S4H_REG (0x00000444) + #define GODLAT_CR_G_ODLAT_ARM_S4H_ARM_bits_packet_OFF ( 0) + #define GODLAT_CR_G_ODLAT_ARM_S4H_ARM_bits_packet_WID (32) + #define GODLAT_CR_G_ODLAT_ARM_S4H_ARM_bits_packet_MSK (0xFFFFFFFF) + #define GODLAT_CR_G_ODLAT_ARM_S4H_ARM_bits_packet_MAX (0xFFFFFFFF) + +#define GODLAT_CR_G_ODLAT_MASK_S4L_REG (0x00000448) + #define GODLAT_CR_G_ODLAT_MASK_S4L_Mask_bits_OFF ( 0) + #define GODLAT_CR_G_ODLAT_MASK_S4L_Mask_bits_WID (32) + #define GODLAT_CR_G_ODLAT_MASK_S4L_Mask_bits_MSK (0xFFFFFFFF) + #define GODLAT_CR_G_ODLAT_MASK_S4L_Mask_bits_MAX (0xFFFFFFFF) + +#define GODLAT_CR_G_ODLAT_MASK_S4H_REG (0x0000044C) + #define GODLAT_CR_G_ODLAT_MASK_S4H_Mask_bits_OFF ( 0) + #define GODLAT_CR_G_ODLAT_MASK_S4H_Mask_bits_WID (32) + #define GODLAT_CR_G_ODLAT_MASK_S4H_Mask_bits_MSK (0xFFFFFFFF) + #define GODLAT_CR_G_ODLAT_MASK_S4H_Mask_bits_MAX (0xFFFFFFFF) + +#define GODLAT_CR_G_ODLAT_ARM_S5L_REG (0x00000450) + #define GODLAT_CR_G_ODLAT_ARM_S5L_ARM_bits_packet_OFF ( 0) + #define GODLAT_CR_G_ODLAT_ARM_S5L_ARM_bits_packet_WID (32) + #define GODLAT_CR_G_ODLAT_ARM_S5L_ARM_bits_packet_MSK (0xFFFFFFFF) + #define GODLAT_CR_G_ODLAT_ARM_S5L_ARM_bits_packet_MAX (0xFFFFFFFF) + +#define GODLAT_CR_G_ODLAT_ARM_S5H_REG (0x00000454) + #define GODLAT_CR_G_ODLAT_ARM_S5H_ARM_bits_packet_OFF ( 0) + #define GODLAT_CR_G_ODLAT_ARM_S5H_ARM_bits_packet_WID (32) + #define GODLAT_CR_G_ODLAT_ARM_S5H_ARM_bits_packet_MSK (0xFFFFFFFF) + #define GODLAT_CR_G_ODLAT_ARM_S5H_ARM_bits_packet_MAX (0xFFFFFFFF) + +#define GODLAT_CR_G_ODLAT_MASK_S5L_REG (0x00000458) + #define GODLAT_CR_G_ODLAT_MASK_S5L_Mask_bits_OFF ( 0) + #define GODLAT_CR_G_ODLAT_MASK_S5L_Mask_bits_WID (32) + #define GODLAT_CR_G_ODLAT_MASK_S5L_Mask_bits_MSK (0xFFFFFFFF) + #define GODLAT_CR_G_ODLAT_MASK_S5L_Mask_bits_MAX (0xFFFFFFFF) + +#define GODLAT_CR_G_ODLAT_MASK_S5H_REG (0x0000045C) + #define GODLAT_CR_G_ODLAT_MASK_S5H_Mask_bits_OFF ( 0) + #define GODLAT_CR_G_ODLAT_MASK_S5H_Mask_bits_WID (32) + #define GODLAT_CR_G_ODLAT_MASK_S5H_Mask_bits_MSK (0xFFFFFFFF) + #define GODLAT_CR_G_ODLAT_MASK_S5H_Mask_bits_MAX (0xFFFFFFFF) + +#define GODLAT_CR_G_ODLAT_ARM_S6L_REG (0x00000460) + #define GODLAT_CR_G_ODLAT_ARM_S6L_ARM_bits_packet_OFF ( 0) + #define GODLAT_CR_G_ODLAT_ARM_S6L_ARM_bits_packet_WID (32) + #define GODLAT_CR_G_ODLAT_ARM_S6L_ARM_bits_packet_MSK (0xFFFFFFFF) + #define GODLAT_CR_G_ODLAT_ARM_S6L_ARM_bits_packet_MAX (0xFFFFFFFF) + +#define GODLAT_CR_G_ODLAT_ARM_S6H_REG (0x00000464) + #define GODLAT_CR_G_ODLAT_ARM_S6H_ARM_bits_packet_OFF ( 0) + #define GODLAT_CR_G_ODLAT_ARM_S6H_ARM_bits_packet_WID (32) + #define GODLAT_CR_G_ODLAT_ARM_S6H_ARM_bits_packet_MSK (0xFFFFFFFF) + #define GODLAT_CR_G_ODLAT_ARM_S6H_ARM_bits_packet_MAX (0xFFFFFFFF) + +#define GODLAT_CR_G_ODLAT_MASK_S6L_REG (0x00000468) + #define GODLAT_CR_G_ODLAT_MASK_S6L_Mask_bits_OFF ( 0) + #define GODLAT_CR_G_ODLAT_MASK_S6L_Mask_bits_WID (32) + #define GODLAT_CR_G_ODLAT_MASK_S6L_Mask_bits_MSK (0xFFFFFFFF) + #define GODLAT_CR_G_ODLAT_MASK_S6L_Mask_bits_MAX (0xFFFFFFFF) + +#define GODLAT_CR_G_ODLAT_MASK_S6H_REG (0x0000046C) + #define GODLAT_CR_G_ODLAT_MASK_S6H_Mask_bits_OFF ( 0) + #define GODLAT_CR_G_ODLAT_MASK_S6H_Mask_bits_WID (32) + #define GODLAT_CR_G_ODLAT_MASK_S6H_Mask_bits_MSK (0xFFFFFFFF) + #define GODLAT_CR_G_ODLAT_MASK_S6H_Mask_bits_MAX (0xFFFFFFFF) + +#define GODLAT_CR_G_ODLAT_ARM_S7L_REG (0x00000470) + #define GODLAT_CR_G_ODLAT_ARM_S7L_ARM_bits_packet_OFF ( 0) + #define GODLAT_CR_G_ODLAT_ARM_S7L_ARM_bits_packet_WID (32) + #define GODLAT_CR_G_ODLAT_ARM_S7L_ARM_bits_packet_MSK (0xFFFFFFFF) + #define GODLAT_CR_G_ODLAT_ARM_S7L_ARM_bits_packet_MAX (0xFFFFFFFF) + +#define GODLAT_CR_G_ODLAT_ARM_S7H_REG (0x00000474) + #define GODLAT_CR_G_ODLAT_ARM_S7H_ARM_bits_packet_OFF ( 0) + #define GODLAT_CR_G_ODLAT_ARM_S7H_ARM_bits_packet_WID (32) + #define GODLAT_CR_G_ODLAT_ARM_S7H_ARM_bits_packet_MSK (0xFFFFFFFF) + #define GODLAT_CR_G_ODLAT_ARM_S7H_ARM_bits_packet_MAX (0xFFFFFFFF) + +#define GODLAT_CR_G_ODLAT_MASK_S7L_REG (0x00000478) + #define GODLAT_CR_G_ODLAT_MASK_S7L_Mask_bits_OFF ( 0) + #define GODLAT_CR_G_ODLAT_MASK_S7L_Mask_bits_WID (32) + #define GODLAT_CR_G_ODLAT_MASK_S7L_Mask_bits_MSK (0xFFFFFFFF) + #define GODLAT_CR_G_ODLAT_MASK_S7L_Mask_bits_MAX (0xFFFFFFFF) + +#define GODLAT_CR_G_ODLAT_MASK_S7H_REG (0x0000047C) + #define GODLAT_CR_G_ODLAT_MASK_S7H_Mask_bits_OFF ( 0) + #define GODLAT_CR_G_ODLAT_MASK_S7H_Mask_bits_WID (32) + #define GODLAT_CR_G_ODLAT_MASK_S7H_Mask_bits_MSK (0xFFFFFFFF) + #define GODLAT_CR_G_ODLAT_MASK_S7H_Mask_bits_MAX (0xFFFFFFFF) + +#define GODLAT_CR_G_ODLAT_CMD_REG (0x00000480) + #define GODLAT_CR_G_ODLAT_CMD_UX_TMR_BASE_A_OFF ( 0) + #define GODLAT_CR_G_ODLAT_CMD_UX_TMR_BASE_A_WID ( 1) + #define GODLAT_CR_G_ODLAT_CMD_UX_TMR_BASE_A_MSK (0x00000001) + #define GODLAT_CR_G_ODLAT_CMD_UX_TMR_BASE_A_MAX (0x00000001) + #define GODLAT_CR_G_ODLAT_CMD_UX_TMR_BASE_A_DEF (0x00000000) + #define GODLAT_CR_G_ODLAT_CMD_UX_TMR_BASE_B_OFF ( 1) + #define GODLAT_CR_G_ODLAT_CMD_UX_TMR_BASE_B_WID ( 1) + #define GODLAT_CR_G_ODLAT_CMD_UX_TMR_BASE_B_MSK (0x00000002) + #define GODLAT_CR_G_ODLAT_CMD_UX_TMR_BASE_B_MAX (0x00000001) + #define GODLAT_CR_G_ODLAT_CMD_UX_TMR_BASE_B_DEF (0x00000000) + #define GODLAT_CR_G_ODLAT_CMD_OVF_ARM_IDI_OFF ( 2) + #define GODLAT_CR_G_ODLAT_CMD_OVF_ARM_IDI_WID ( 1) + #define GODLAT_CR_G_ODLAT_CMD_OVF_ARM_IDI_MSK (0x00000004) + #define GODLAT_CR_G_ODLAT_CMD_OVF_ARM_IDI_MAX (0x00000001) + #define GODLAT_CR_G_ODLAT_CMD_OVF_ARM_IDI_DEF (0x00000000) + #define GODLAT_CR_G_ODLAT_CMD_OVF_ARM_HIGH_OFF ( 3) + #define GODLAT_CR_G_ODLAT_CMD_OVF_ARM_HIGH_WID ( 5) + #define GODLAT_CR_G_ODLAT_CMD_OVF_ARM_HIGH_MSK (0x000000F8) + #define GODLAT_CR_G_ODLAT_CMD_OVF_ARM_HIGH_MAX (0x0000001F) + #define GODLAT_CR_G_ODLAT_CMD_OVF_ARM_HIGH_DEF (0x00000000) + #define GODLAT_CR_G_ODLAT_CMD_OVF_Mask_HIGH_OFF ( 8) + #define GODLAT_CR_G_ODLAT_CMD_OVF_Mask_HIGH_WID ( 5) + #define GODLAT_CR_G_ODLAT_CMD_OVF_Mask_HIGH_MSK (0x00001F00) + #define GODLAT_CR_G_ODLAT_CMD_OVF_Mask_HIGH_MAX (0x0000001F) + #define GODLAT_CR_G_ODLAT_CMD_OVF_Mask_HIGH_DEF (0x00000000) + #define GODLAT_CR_G_ODLAT_CMD_TimerA_units_OFF (18) + #define GODLAT_CR_G_ODLAT_CMD_TimerA_units_WID ( 3) + #define GODLAT_CR_G_ODLAT_CMD_TimerA_units_MSK (0x001C0000) + #define GODLAT_CR_G_ODLAT_CMD_TimerA_units_MAX (0x00000007) + #define GODLAT_CR_G_ODLAT_CMD_TimerA_units_DEF (0x00000000) + #define GODLAT_CR_G_ODLAT_CMD_TimerB_units_OFF (21) + #define GODLAT_CR_G_ODLAT_CMD_TimerB_units_WID ( 3) + #define GODLAT_CR_G_ODLAT_CMD_TimerB_units_MSK (0x00E00000) + #define GODLAT_CR_G_ODLAT_CMD_TimerB_units_MAX (0x00000007) + #define GODLAT_CR_G_ODLAT_CMD_TimerB_units_DEF (0x00000000) + #define GODLAT_CR_G_ODLAT_CMD_Which_Time_Base_OFF (24) + #define GODLAT_CR_G_ODLAT_CMD_Which_Time_Base_WID ( 4) + #define GODLAT_CR_G_ODLAT_CMD_Which_Time_Base_MSK (0x0F000000) + #define GODLAT_CR_G_ODLAT_CMD_Which_Time_Base_MAX (0x0000000F) + #define GODLAT_CR_G_ODLAT_CMD_Which_Time_Base_DEF (0x00000000) + #define GODLAT_CR_G_ODLAT_CMD_Tmr_Or_Cntr_Mode_OFF (28) + #define GODLAT_CR_G_ODLAT_CMD_Tmr_Or_Cntr_Mode_WID ( 4) + #define GODLAT_CR_G_ODLAT_CMD_Tmr_Or_Cntr_Mode_MSK (0xF0000000) + #define GODLAT_CR_G_ODLAT_CMD_Tmr_Or_Cntr_Mode_MAX (0x0000000F) + #define GODLAT_CR_G_ODLAT_CMD_Tmr_Or_Cntr_Mode_DEF (0x00000000) + +#define GODLAT_CR_G_ODLAT_SW_ENABLE_REG (0x00000484) + #define GODLAT_CR_G_ODLAT_SW_ENABLE_EN_SW_G_ODLAT_OFF ( 0) + #define GODLAT_CR_G_ODLAT_SW_ENABLE_EN_SW_G_ODLAT_WID ( 1) + #define GODLAT_CR_G_ODLAT_SW_ENABLE_EN_SW_G_ODLAT_MSK (0x00000001) + #define GODLAT_CR_G_ODLAT_SW_ENABLE_EN_SW_G_ODLAT_MAX (0x00000001) + #define GODLAT_CR_G_ODLAT_SW_ENABLE_EN_SW_G_ODLAT_DEF (0x00000000) + #define GODLAT_CR_G_ODLAT_SW_ENABLE_EN_S0_OFF ( 8) + #define GODLAT_CR_G_ODLAT_SW_ENABLE_EN_S0_WID ( 1) + #define GODLAT_CR_G_ODLAT_SW_ENABLE_EN_S0_MSK (0x00000100) + #define GODLAT_CR_G_ODLAT_SW_ENABLE_EN_S0_MAX (0x00000001) + #define GODLAT_CR_G_ODLAT_SW_ENABLE_EN_S0_DEF (0x00000000) + #define GODLAT_CR_G_ODLAT_SW_ENABLE_EN_S1_OFF ( 9) + #define GODLAT_CR_G_ODLAT_SW_ENABLE_EN_S1_WID ( 1) + #define GODLAT_CR_G_ODLAT_SW_ENABLE_EN_S1_MSK (0x00000200) + #define GODLAT_CR_G_ODLAT_SW_ENABLE_EN_S1_MAX (0x00000001) + #define GODLAT_CR_G_ODLAT_SW_ENABLE_EN_S1_DEF (0x00000000) + #define GODLAT_CR_G_ODLAT_SW_ENABLE_EN_S2_OFF (10) + #define GODLAT_CR_G_ODLAT_SW_ENABLE_EN_S2_WID ( 1) + #define GODLAT_CR_G_ODLAT_SW_ENABLE_EN_S2_MSK (0x00000400) + #define GODLAT_CR_G_ODLAT_SW_ENABLE_EN_S2_MAX (0x00000001) + #define GODLAT_CR_G_ODLAT_SW_ENABLE_EN_S2_DEF (0x00000000) + #define GODLAT_CR_G_ODLAT_SW_ENABLE_EN_S3_OFF (11) + #define GODLAT_CR_G_ODLAT_SW_ENABLE_EN_S3_WID ( 1) + #define GODLAT_CR_G_ODLAT_SW_ENABLE_EN_S3_MSK (0x00000800) + #define GODLAT_CR_G_ODLAT_SW_ENABLE_EN_S3_MAX (0x00000001) + #define GODLAT_CR_G_ODLAT_SW_ENABLE_EN_S3_DEF (0x00000000) + #define GODLAT_CR_G_ODLAT_SW_ENABLE_EN_S4_OFF (12) + #define GODLAT_CR_G_ODLAT_SW_ENABLE_EN_S4_WID ( 1) + #define GODLAT_CR_G_ODLAT_SW_ENABLE_EN_S4_MSK (0x00001000) + #define GODLAT_CR_G_ODLAT_SW_ENABLE_EN_S4_MAX (0x00000001) + #define GODLAT_CR_G_ODLAT_SW_ENABLE_EN_S4_DEF (0x00000000) + #define GODLAT_CR_G_ODLAT_SW_ENABLE_EN_S5_OFF (13) + #define GODLAT_CR_G_ODLAT_SW_ENABLE_EN_S5_WID ( 1) + #define GODLAT_CR_G_ODLAT_SW_ENABLE_EN_S5_MSK (0x00002000) + #define GODLAT_CR_G_ODLAT_SW_ENABLE_EN_S5_MAX (0x00000001) + #define GODLAT_CR_G_ODLAT_SW_ENABLE_EN_S5_DEF (0x00000000) + #define GODLAT_CR_G_ODLAT_SW_ENABLE_EN_S6_OFF (14) + #define GODLAT_CR_G_ODLAT_SW_ENABLE_EN_S6_WID ( 1) + #define GODLAT_CR_G_ODLAT_SW_ENABLE_EN_S6_MSK (0x00004000) + #define GODLAT_CR_G_ODLAT_SW_ENABLE_EN_S6_MAX (0x00000001) + #define GODLAT_CR_G_ODLAT_SW_ENABLE_EN_S6_DEF (0x00000000) + #define GODLAT_CR_G_ODLAT_SW_ENABLE_EN_S7_OFF (15) + #define GODLAT_CR_G_ODLAT_SW_ENABLE_EN_S7_WID ( 1) + #define GODLAT_CR_G_ODLAT_SW_ENABLE_EN_S7_MSK (0x00008000) + #define GODLAT_CR_G_ODLAT_SW_ENABLE_EN_S7_MAX (0x00000001) + #define GODLAT_CR_G_ODLAT_SW_ENABLE_EN_S7_DEF (0x00000000) + #define GODLAT_CR_G_ODLAT_SW_ENABLE_MBP_Enable_OFF (16) + #define GODLAT_CR_G_ODLAT_SW_ENABLE_MBP_Enable_WID ( 1) + #define GODLAT_CR_G_ODLAT_SW_ENABLE_MBP_Enable_MSK (0x00010000) + #define GODLAT_CR_G_ODLAT_SW_ENABLE_MBP_Enable_MAX (0x00000001) + #define GODLAT_CR_G_ODLAT_SW_ENABLE_MBP_Enable_DEF (0x00000000) + +#define GODLAT_CR_G_ODLAT_MISC_CMD_REG (0x0000048C) + #define GODLAT_CR_G_ODLAT_MISC_CMD_Pulse_or_Sticky_Events_OFF ( 0) + #define GODLAT_CR_G_ODLAT_MISC_CMD_Pulse_or_Sticky_Events_WID ( 8) + #define GODLAT_CR_G_ODLAT_MISC_CMD_Pulse_or_Sticky_Events_MSK (0x000000FF) + #define GODLAT_CR_G_ODLAT_MISC_CMD_Pulse_or_Sticky_Events_MAX (0x000000FF) + #define GODLAT_CR_G_ODLAT_MISC_CMD_Pulse_or_Sticky_Events_DEF (0x00000000) + #define GODLAT_CR_G_ODLAT_MISC_CMD_Pulse_or_Sticky_MBP_OFF ( 8) + #define GODLAT_CR_G_ODLAT_MISC_CMD_Pulse_or_Sticky_MBP_WID ( 1) + #define GODLAT_CR_G_ODLAT_MISC_CMD_Pulse_or_Sticky_MBP_MSK (0x00000100) + #define GODLAT_CR_G_ODLAT_MISC_CMD_Pulse_or_Sticky_MBP_MAX (0x00000001) + #define GODLAT_CR_G_ODLAT_MISC_CMD_Pulse_or_Sticky_MBP_DEF (0x00000000) + #define GODLAT_CR_G_ODLAT_MISC_CMD_Pulse_or_Sticky_TO_OFF ( 9) + #define GODLAT_CR_G_ODLAT_MISC_CMD_Pulse_or_Sticky_TO_WID ( 4) + #define GODLAT_CR_G_ODLAT_MISC_CMD_Pulse_or_Sticky_TO_MSK (0x00001E00) + #define GODLAT_CR_G_ODLAT_MISC_CMD_Pulse_or_Sticky_TO_MAX (0x0000000F) + #define GODLAT_CR_G_ODLAT_MISC_CMD_Pulse_or_Sticky_TO_DEF (0x00000000) + #define GODLAT_CR_G_ODLAT_MISC_CMD_OVF_ARM_LOW_OFF (13) + #define GODLAT_CR_G_ODLAT_MISC_CMD_OVF_ARM_LOW_WID ( 3) + #define GODLAT_CR_G_ODLAT_MISC_CMD_OVF_ARM_LOW_MSK (0x0000E000) + #define GODLAT_CR_G_ODLAT_MISC_CMD_OVF_ARM_LOW_MAX (0x00000007) + #define GODLAT_CR_G_ODLAT_MISC_CMD_OVF_ARM_LOW_DEF (0x00000000) + #define GODLAT_CR_G_ODLAT_MISC_CMD_OVF_MASK_LOW_OFF (16) + #define GODLAT_CR_G_ODLAT_MISC_CMD_OVF_MASK_LOW_WID ( 3) + #define GODLAT_CR_G_ODLAT_MISC_CMD_OVF_MASK_LOW_MSK (0x00070000) + #define GODLAT_CR_G_ODLAT_MISC_CMD_OVF_MASK_LOW_MAX (0x00000007) + #define GODLAT_CR_G_ODLAT_MISC_CMD_OVF_MASK_LOW_DEF (0x00000000) + #define GODLAT_CR_G_ODLAT_MISC_CMD_Which_MBP_Pin_A_OFF (19) + #define GODLAT_CR_G_ODLAT_MISC_CMD_Which_MBP_Pin_A_WID ( 3) + #define GODLAT_CR_G_ODLAT_MISC_CMD_Which_MBP_Pin_A_MSK (0x00380000) + #define GODLAT_CR_G_ODLAT_MISC_CMD_Which_MBP_Pin_A_MAX (0x00000007) + #define GODLAT_CR_G_ODLAT_MISC_CMD_Which_MBP_Pin_A_DEF (0x00000000) + #define GODLAT_CR_G_ODLAT_MISC_CMD_Which_MBP_Pin_B_OFF (22) + #define GODLAT_CR_G_ODLAT_MISC_CMD_Which_MBP_Pin_B_WID ( 3) + #define GODLAT_CR_G_ODLAT_MISC_CMD_Which_MBP_Pin_B_MSK (0x01C00000) + #define GODLAT_CR_G_ODLAT_MISC_CMD_Which_MBP_Pin_B_MAX (0x00000007) + #define GODLAT_CR_G_ODLAT_MISC_CMD_Which_MBP_Pin_B_DEF (0x00000000) + #define GODLAT_CR_G_ODLAT_MISC_CMD_Which_MBP_Pin_C_OFF (25) + #define GODLAT_CR_G_ODLAT_MISC_CMD_Which_MBP_Pin_C_WID ( 3) + #define GODLAT_CR_G_ODLAT_MISC_CMD_Which_MBP_Pin_C_MSK (0x0E000000) + #define GODLAT_CR_G_ODLAT_MISC_CMD_Which_MBP_Pin_C_MAX (0x00000007) + #define GODLAT_CR_G_ODLAT_MISC_CMD_Which_MBP_Pin_C_DEF (0x00000000) + #define GODLAT_CR_G_ODLAT_MISC_CMD_Which_MBP_Pin_D_OFF (28) + #define GODLAT_CR_G_ODLAT_MISC_CMD_Which_MBP_Pin_D_WID ( 3) + #define GODLAT_CR_G_ODLAT_MISC_CMD_Which_MBP_Pin_D_MSK (0x70000000) + #define GODLAT_CR_G_ODLAT_MISC_CMD_Which_MBP_Pin_D_MAX (0x00000007) + #define GODLAT_CR_G_ODLAT_MISC_CMD_Which_MBP_Pin_D_DEF (0x00000000) + +#define GDXC_CR_GT_VISA2OCLA_CFG_FILTER_REG (0x00000500) + #define GDXC_CR_GT_VISA2OCLA_CFG_FILTER_Ln0Mask_OFF ( 0) + #define GDXC_CR_GT_VISA2OCLA_CFG_FILTER_Ln0Mask_WID ( 8) + #define GDXC_CR_GT_VISA2OCLA_CFG_FILTER_Ln0Mask_MSK (0x000000FF) + #define GDXC_CR_GT_VISA2OCLA_CFG_FILTER_Ln0Mask_MAX (0x000000FF) + #define GDXC_CR_GT_VISA2OCLA_CFG_FILTER_Ln0Mask_DEF (0x00000000) + #define GDXC_CR_GT_VISA2OCLA_CFG_FILTER_Ln1Mask_OFF ( 8) + #define GDXC_CR_GT_VISA2OCLA_CFG_FILTER_Ln1Mask_WID ( 8) + #define GDXC_CR_GT_VISA2OCLA_CFG_FILTER_Ln1Mask_MSK (0x0000FF00) + #define GDXC_CR_GT_VISA2OCLA_CFG_FILTER_Ln1Mask_MAX (0x000000FF) + #define GDXC_CR_GT_VISA2OCLA_CFG_FILTER_Ln1Mask_DEF (0x00000000) + #define GDXC_CR_GT_VISA2OCLA_CFG_FILTER_AssertMode_OFF (16) + #define GDXC_CR_GT_VISA2OCLA_CFG_FILTER_AssertMode_WID ( 1) + #define GDXC_CR_GT_VISA2OCLA_CFG_FILTER_AssertMode_MSK (0x00010000) + #define GDXC_CR_GT_VISA2OCLA_CFG_FILTER_AssertMode_MAX (0x00000001) + #define GDXC_CR_GT_VISA2OCLA_CFG_FILTER_AssertMode_DEF (0x00000000) + #define GDXC_CR_GT_VISA2OCLA_CFG_FILTER_CompEn_OFF (17) + #define GDXC_CR_GT_VISA2OCLA_CFG_FILTER_CompEn_WID ( 1) + #define GDXC_CR_GT_VISA2OCLA_CFG_FILTER_CompEn_MSK (0x00020000) + #define GDXC_CR_GT_VISA2OCLA_CFG_FILTER_CompEn_MAX (0x00000001) + #define GDXC_CR_GT_VISA2OCLA_CFG_FILTER_CompEn_DEF (0x00000001) + #define GDXC_CR_GT_VISA2OCLA_CFG_FILTER_GT_VISA_En_OFF (18) + #define GDXC_CR_GT_VISA2OCLA_CFG_FILTER_GT_VISA_En_WID ( 1) + #define GDXC_CR_GT_VISA2OCLA_CFG_FILTER_GT_VISA_En_MSK (0x00040000) + #define GDXC_CR_GT_VISA2OCLA_CFG_FILTER_GT_VISA_En_MAX (0x00000001) + #define GDXC_CR_GT_VISA2OCLA_CFG_FILTER_GT_VISA_En_DEF (0x00000000) + +#define GDXC_CR_GDXC_MAN_CONFIG_REG (0x00000504) + #define GDXC_CR_GDXC_MAN_CONFIG_Man_Reset_GDXC_OFF ( 0) + #define GDXC_CR_GDXC_MAN_CONFIG_Man_Reset_GDXC_WID ( 1) + #define GDXC_CR_GDXC_MAN_CONFIG_Man_Reset_GDXC_MSK (0x00000001) + #define GDXC_CR_GDXC_MAN_CONFIG_Man_Reset_GDXC_MAX (0x00000001) + #define GDXC_CR_GDXC_MAN_CONFIG_Man_Reset_GDXC_DEF (0x00000000) + #define GDXC_CR_GDXC_MAN_CONFIG_Man_Reset_G_ODLAT_OFF ( 1) + #define GDXC_CR_GDXC_MAN_CONFIG_Man_Reset_G_ODLAT_WID ( 1) + #define GDXC_CR_GDXC_MAN_CONFIG_Man_Reset_G_ODLAT_MSK (0x00000002) + #define GDXC_CR_GDXC_MAN_CONFIG_Man_Reset_G_ODLAT_MAX (0x00000001) + #define GDXC_CR_GDXC_MAN_CONFIG_Man_Reset_G_ODLAT_DEF (0x00000000) + #define GDXC_CR_GDXC_MAN_CONFIG_IOT_Start_OFF ( 2) + #define GDXC_CR_GDXC_MAN_CONFIG_IOT_Start_WID ( 1) + #define GDXC_CR_GDXC_MAN_CONFIG_IOT_Start_MSK (0x00000004) + #define GDXC_CR_GDXC_MAN_CONFIG_IOT_Start_MAX (0x00000001) + #define GDXC_CR_GDXC_MAN_CONFIG_IOT_Start_DEF (0x00000000) + #define GDXC_CR_GDXC_MAN_CONFIG_IOT_Stop_OFF ( 3) + #define GDXC_CR_GDXC_MAN_CONFIG_IOT_Stop_WID ( 1) + #define GDXC_CR_GDXC_MAN_CONFIG_IOT_Stop_MSK (0x00000008) + #define GDXC_CR_GDXC_MAN_CONFIG_IOT_Stop_MAX (0x00000001) + #define GDXC_CR_GDXC_MAN_CONFIG_IOT_Stop_DEF (0x00000000) + #define GDXC_CR_GDXC_MAN_CONFIG_IOT_Trigger_OFF ( 4) + #define GDXC_CR_GDXC_MAN_CONFIG_IOT_Trigger_WID ( 1) + #define GDXC_CR_GDXC_MAN_CONFIG_IOT_Trigger_MSK (0x00000010) + #define GDXC_CR_GDXC_MAN_CONFIG_IOT_Trigger_MAX (0x00000001) + #define GDXC_CR_GDXC_MAN_CONFIG_IOT_Trigger_DEF (0x00000000) + #define GDXC_CR_GDXC_MAN_CONFIG_IOT_Force_Flush_OFF ( 5) + #define GDXC_CR_GDXC_MAN_CONFIG_IOT_Force_Flush_WID ( 1) + #define GDXC_CR_GDXC_MAN_CONFIG_IOT_Force_Flush_MSK (0x00000020) + #define GDXC_CR_GDXC_MAN_CONFIG_IOT_Force_Flush_MAX (0x00000001) + #define GDXC_CR_GDXC_MAN_CONFIG_IOT_Force_Flush_DEF (0x00000000) + #define GDXC_CR_GDXC_MAN_CONFIG_SPARE_OFF (16) + #define GDXC_CR_GDXC_MAN_CONFIG_SPARE_WID ( 8) + #define GDXC_CR_GDXC_MAN_CONFIG_SPARE_MSK (0x00FF0000) + #define GDXC_CR_GDXC_MAN_CONFIG_SPARE_MAX (0x000000FF) + #define GDXC_CR_GDXC_MAN_CONFIG_SPARE_DEF (0x00000000) + +#define GDXC_CR_GDXC_ALIGN_REG (0x00000508) + #define GDXC_CR_GDXC_ALIGN_mbpout_OFF ( 0) + #define GDXC_CR_GDXC_ALIGN_mbpout_WID ( 2) + #define GDXC_CR_GDXC_ALIGN_mbpout_MSK (0x00000003) + #define GDXC_CR_GDXC_ALIGN_mbpout_MAX (0x00000003) + #define GDXC_CR_GDXC_ALIGN_mbpout_DEF (0x00000001) + +#define GDXC_CR_GDXC_RR_ARB_THRESH_REG (0x00000510) + #define GDXC_CR_GDXC_RR_ARB_THRESH_AD_OFF ( 0) + #define GDXC_CR_GDXC_RR_ARB_THRESH_AD_WID ( 6) + #define GDXC_CR_GDXC_RR_ARB_THRESH_AD_MSK (0x0000003F) + #define GDXC_CR_GDXC_RR_ARB_THRESH_AD_MAX (0x0000003F) + #define GDXC_CR_GDXC_RR_ARB_THRESH_AD_DEF (0x00000004) + #define GDXC_CR_GDXC_RR_ARB_THRESH_BLHDR0_OFF ( 6) + #define GDXC_CR_GDXC_RR_ARB_THRESH_BLHDR0_WID ( 7) + #define GDXC_CR_GDXC_RR_ARB_THRESH_BLHDR0_MSK (0x00001FC0) + #define GDXC_CR_GDXC_RR_ARB_THRESH_BLHDR0_MAX (0x0000007F) + #define GDXC_CR_GDXC_RR_ARB_THRESH_BLHDR0_DEF (0x00000004) + #define GDXC_CR_GDXC_RR_ARB_THRESH_BLHDR1ADDR_OFF (13) + #define GDXC_CR_GDXC_RR_ARB_THRESH_BLHDR1ADDR_WID ( 6) + #define GDXC_CR_GDXC_RR_ARB_THRESH_BLHDR1ADDR_MSK (0x0007E000) + #define GDXC_CR_GDXC_RR_ARB_THRESH_BLHDR1ADDR_MAX (0x0000003F) + #define GDXC_CR_GDXC_RR_ARB_THRESH_BLHDR1ADDR_DEF (0x00000008) + #define GDXC_CR_GDXC_RR_ARB_THRESH_AK_OFF (19) + #define GDXC_CR_GDXC_RR_ARB_THRESH_AK_WID ( 6) + #define GDXC_CR_GDXC_RR_ARB_THRESH_AK_MSK (0x01F80000) + #define GDXC_CR_GDXC_RR_ARB_THRESH_AK_MAX (0x0000003F) + #define GDXC_CR_GDXC_RR_ARB_THRESH_AK_DEF (0x00000004) + #define GDXC_CR_GDXC_RR_ARB_THRESH_IV_OFF (25) + #define GDXC_CR_GDXC_RR_ARB_THRESH_IV_WID ( 2) + #define GDXC_CR_GDXC_RR_ARB_THRESH_IV_MSK (0x06000000) + #define GDXC_CR_GDXC_RR_ARB_THRESH_IV_MAX (0x00000003) + #define GDXC_CR_GDXC_RR_ARB_THRESH_IV_DEF (0x00000003) + #define GDXC_CR_GDXC_RR_ARB_THRESH_Wrap_OFF (27) + #define GDXC_CR_GDXC_RR_ARB_THRESH_Wrap_WID ( 3) + #define GDXC_CR_GDXC_RR_ARB_THRESH_Wrap_MSK (0x38000000) + #define GDXC_CR_GDXC_RR_ARB_THRESH_Wrap_MAX (0x00000007) + #define GDXC_CR_GDXC_RR_ARB_THRESH_Wrap_DEF (0x00000002) + #define GDXC_CR_GDXC_RR_ARB_THRESH_MOT_OFF (30) + #define GDXC_CR_GDXC_RR_ARB_THRESH_MOT_WID ( 5) + #define GDXC_CR_GDXC_RR_ARB_THRESH_MOT_MSK (0x7C0000000) + #define GDXC_CR_GDXC_RR_ARB_THRESH_MOT_MAX (0x0000001F) + #define GDXC_CR_GDXC_RR_ARB_THRESH_MOT_DEF (0x00000002) + #define GDXC_CR_GDXC_RR_ARB_THRESH_IDI_OFF (35) + #define GDXC_CR_GDXC_RR_ARB_THRESH_IDI_WID ( 5) + #define GDXC_CR_GDXC_RR_ARB_THRESH_IDI_MSK (0xF800000000) + #define GDXC_CR_GDXC_RR_ARB_THRESH_IDI_MAX (0x0000001F) + #define GDXC_CR_GDXC_RR_ARB_THRESH_IDI_DEF (0x00000002) + #define GDXC_CR_GDXC_RR_ARB_THRESH_FClk_OFF (40) + #define GDXC_CR_GDXC_RR_ARB_THRESH_FClk_WID ( 5) + #define GDXC_CR_GDXC_RR_ARB_THRESH_FClk_MSK (0x1F0000000000) + #define GDXC_CR_GDXC_RR_ARB_THRESH_FClk_MAX (0x0000001F) + #define GDXC_CR_GDXC_RR_ARB_THRESH_FClk_DEF (0x00000002) + #define GDXC_CR_GDXC_RR_ARB_THRESH_UClkMsgCh_OFF (45) + #define GDXC_CR_GDXC_RR_ARB_THRESH_UClkMsgCh_WID ( 5) + #define GDXC_CR_GDXC_RR_ARB_THRESH_UClkMsgCh_MSK (0x3E00000000000) + #define GDXC_CR_GDXC_RR_ARB_THRESH_UClkMsgCh_MAX (0x0000001F) + #define GDXC_CR_GDXC_RR_ARB_THRESH_UClkMsgCh_DEF (0x00000002) + +#define GDXC_CR_G_ODLAT_FIRE_STATUS_REG (0x00000518) + #define GDXC_CR_G_ODLAT_FIRE_STATUS_Start_Status_OFF ( 0) + #define GDXC_CR_G_ODLAT_FIRE_STATUS_Start_Status_WID ( 1) + #define GDXC_CR_G_ODLAT_FIRE_STATUS_Start_Status_MSK (0x00000001) + #define GDXC_CR_G_ODLAT_FIRE_STATUS_Start_Status_MAX (0x00000001) + #define GDXC_CR_G_ODLAT_FIRE_STATUS_Start_Status_DEF (0x00000000) + #define GDXC_CR_G_ODLAT_FIRE_STATUS_Trigger_Status_OFF ( 1) + #define GDXC_CR_G_ODLAT_FIRE_STATUS_Trigger_Status_WID ( 1) + #define GDXC_CR_G_ODLAT_FIRE_STATUS_Trigger_Status_MSK (0x00000002) + #define GDXC_CR_G_ODLAT_FIRE_STATUS_Trigger_Status_MAX (0x00000001) + #define GDXC_CR_G_ODLAT_FIRE_STATUS_Trigger_Status_DEF (0x00000000) + #define GDXC_CR_G_ODLAT_FIRE_STATUS_Stop_Status_OFF ( 2) + #define GDXC_CR_G_ODLAT_FIRE_STATUS_Stop_Status_WID ( 1) + #define GDXC_CR_G_ODLAT_FIRE_STATUS_Stop_Status_MSK (0x00000004) + #define GDXC_CR_G_ODLAT_FIRE_STATUS_Stop_Status_MAX (0x00000001) + #define GDXC_CR_G_ODLAT_FIRE_STATUS_Stop_Status_DEF (0x00000000) + #define GDXC_CR_G_ODLAT_FIRE_STATUS_Muliple_Hit_OFF ( 3) + #define GDXC_CR_G_ODLAT_FIRE_STATUS_Muliple_Hit_WID ( 1) + #define GDXC_CR_G_ODLAT_FIRE_STATUS_Muliple_Hit_MSK (0x00000008) + #define GDXC_CR_G_ODLAT_FIRE_STATUS_Muliple_Hit_MAX (0x00000001) + #define GDXC_CR_G_ODLAT_FIRE_STATUS_Muliple_Hit_DEF (0x00000000) + #define GDXC_CR_G_ODLAT_FIRE_STATUS_Bubbles_Status_OFF ( 4) + #define GDXC_CR_G_ODLAT_FIRE_STATUS_Bubbles_Status_WID ( 6) + #define GDXC_CR_G_ODLAT_FIRE_STATUS_Bubbles_Status_MSK (0x000003F0) + #define GDXC_CR_G_ODLAT_FIRE_STATUS_Bubbles_Status_MAX (0x0000003F) + #define GDXC_CR_G_ODLAT_FIRE_STATUS_Bubbles_Status_DEF (0x00000000) + +#define GDXC_CR_TRIGGER_TO_STOP_DELAY_REG (0x00000520) + #define GDXC_CR_TRIGGER_TO_STOP_DELAY_Delay_count_OFF ( 0) + #define GDXC_CR_TRIGGER_TO_STOP_DELAY_Delay_count_WID (25) + #define GDXC_CR_TRIGGER_TO_STOP_DELAY_Delay_count_MSK (0x01FFFFFF) + #define GDXC_CR_TRIGGER_TO_STOP_DELAY_Delay_count_MAX (0x01FFFFFF) + #define GDXC_CR_TRIGGER_TO_STOP_DELAY_Delay_count_DEF (0x00000000) + +#define GDXC_CR_IOT_STATUS_REG (0x00000524) + #define GDXC_CR_IOT_STATUS_Disabled_OFF ( 0) + #define GDXC_CR_IOT_STATUS_Disabled_WID ( 1) + #define GDXC_CR_IOT_STATUS_Disabled_MSK (0x00000001) + #define GDXC_CR_IOT_STATUS_Disabled_MAX (0x00000001) + #define GDXC_CR_IOT_STATUS_Disabled_DEF (0x00000001) + #define GDXC_CR_IOT_STATUS_Idle_OFF ( 1) + #define GDXC_CR_IOT_STATUS_Idle_WID ( 1) + #define GDXC_CR_IOT_STATUS_Idle_MSK (0x00000002) + #define GDXC_CR_IOT_STATUS_Idle_MAX (0x00000001) + #define GDXC_CR_IOT_STATUS_Idle_DEF (0x00000000) + #define GDXC_CR_IOT_STATUS_Running_OFF ( 2) + #define GDXC_CR_IOT_STATUS_Running_WID ( 1) + #define GDXC_CR_IOT_STATUS_Running_MSK (0x00000004) + #define GDXC_CR_IOT_STATUS_Running_MAX (0x00000001) + #define GDXC_CR_IOT_STATUS_Running_DEF (0x00000000) + #define GDXC_CR_IOT_STATUS_IOT_Triggered_OFF ( 3) + #define GDXC_CR_IOT_STATUS_IOT_Triggered_WID ( 1) + #define GDXC_CR_IOT_STATUS_IOT_Triggered_MSK (0x00000008) + #define GDXC_CR_IOT_STATUS_IOT_Triggered_MAX (0x00000001) + #define GDXC_CR_IOT_STATUS_IOT_Triggered_DEF (0x00000000) + #define GDXC_CR_IOT_STATUS_Sticky_triggered_OFF ( 4) + #define GDXC_CR_IOT_STATUS_Sticky_triggered_WID ( 1) + #define GDXC_CR_IOT_STATUS_Sticky_triggered_MSK (0x00000010) + #define GDXC_CR_IOT_STATUS_Sticky_triggered_MAX (0x00000001) + #define GDXC_CR_IOT_STATUS_Sticky_triggered_DEF (0x00000000) + #define GDXC_CR_IOT_STATUS_Remaining_count_OFF ( 6) + #define GDXC_CR_IOT_STATUS_Remaining_count_WID (25) + #define GDXC_CR_IOT_STATUS_Remaining_count_MSK (0x7FFFFFC0) + #define GDXC_CR_IOT_STATUS_Remaining_count_MAX (0x01FFFFFF) + #define GDXC_CR_IOT_STATUS_Remaining_count_DEF (0x00000000) + +#define GODLAT_CR_G_ODLAT_OCLAHDR_S0TO3_REG (0x00000528) + #define GODLAT_CR_G_ODLAT_OCLAHDR_S0TO3_S0_OclaHdr_OFF ( 0) + #define GODLAT_CR_G_ODLAT_OCLAHDR_S0TO3_S0_OclaHdr_WID ( 8) + #define GODLAT_CR_G_ODLAT_OCLAHDR_S0TO3_S0_OclaHdr_MSK (0x000000FF) + #define GODLAT_CR_G_ODLAT_OCLAHDR_S0TO3_S0_OclaHdr_MAX (0x000000FF) + #define GODLAT_CR_G_ODLAT_OCLAHDR_S0TO3_S1_OclaHdr_OFF ( 8) + #define GODLAT_CR_G_ODLAT_OCLAHDR_S0TO3_S1_OclaHdr_WID ( 8) + #define GODLAT_CR_G_ODLAT_OCLAHDR_S0TO3_S1_OclaHdr_MSK (0x0000FF00) + #define GODLAT_CR_G_ODLAT_OCLAHDR_S0TO3_S1_OclaHdr_MAX (0x000000FF) + #define GODLAT_CR_G_ODLAT_OCLAHDR_S0TO3_S2_OclaHdr_OFF (16) + #define GODLAT_CR_G_ODLAT_OCLAHDR_S0TO3_S2_OclaHdr_WID ( 8) + #define GODLAT_CR_G_ODLAT_OCLAHDR_S0TO3_S2_OclaHdr_MSK (0x00FF0000) + #define GODLAT_CR_G_ODLAT_OCLAHDR_S0TO3_S2_OclaHdr_MAX (0x000000FF) + #define GODLAT_CR_G_ODLAT_OCLAHDR_S0TO3_S3_OclaHdr_OFF (24) + #define GODLAT_CR_G_ODLAT_OCLAHDR_S0TO3_S3_OclaHdr_WID ( 8) + #define GODLAT_CR_G_ODLAT_OCLAHDR_S0TO3_S3_OclaHdr_MSK (0xFF000000) + #define GODLAT_CR_G_ODLAT_OCLAHDR_S0TO3_S3_OclaHdr_MAX (0x000000FF) + +#define GODLAT_CR_G_ODLAT_OCLAHDR_S4TO7_REG (0x0000052C) + #define GODLAT_CR_G_ODLAT_OCLAHDR_S4TO7_S4_OclaHdr_OFF ( 0) + #define GODLAT_CR_G_ODLAT_OCLAHDR_S4TO7_S4_OclaHdr_WID ( 8) + #define GODLAT_CR_G_ODLAT_OCLAHDR_S4TO7_S4_OclaHdr_MSK (0x000000FF) + #define GODLAT_CR_G_ODLAT_OCLAHDR_S4TO7_S4_OclaHdr_MAX (0x000000FF) + #define GODLAT_CR_G_ODLAT_OCLAHDR_S4TO7_S5_OclaHdr_OFF ( 8) + #define GODLAT_CR_G_ODLAT_OCLAHDR_S4TO7_S5_OclaHdr_WID ( 8) + #define GODLAT_CR_G_ODLAT_OCLAHDR_S4TO7_S5_OclaHdr_MSK (0x0000FF00) + #define GODLAT_CR_G_ODLAT_OCLAHDR_S4TO7_S5_OclaHdr_MAX (0x000000FF) + #define GODLAT_CR_G_ODLAT_OCLAHDR_S4TO7_S6_OclaHdr_OFF (16) + #define GODLAT_CR_G_ODLAT_OCLAHDR_S4TO7_S6_OclaHdr_WID ( 8) + #define GODLAT_CR_G_ODLAT_OCLAHDR_S4TO7_S6_OclaHdr_MSK (0x00FF0000) + #define GODLAT_CR_G_ODLAT_OCLAHDR_S4TO7_S6_OclaHdr_MAX (0x000000FF) + #define GODLAT_CR_G_ODLAT_OCLAHDR_S4TO7_S7_OclaHdr_OFF (24) + #define GODLAT_CR_G_ODLAT_OCLAHDR_S4TO7_S7_OclaHdr_WID ( 8) + #define GODLAT_CR_G_ODLAT_OCLAHDR_S4TO7_S7_OclaHdr_MSK (0xFF000000) + #define GODLAT_CR_G_ODLAT_OCLAHDR_S4TO7_S7_OclaHdr_MAX (0x000000FF) + +#define GODLAT_CR_G_ODLAT_FST_REG (0x00000530) + #define GODLAT_CR_G_ODLAT_FST_S0_FST_OFF ( 0) + #define GODLAT_CR_G_ODLAT_FST_S0_FST_WID ( 2) + #define GODLAT_CR_G_ODLAT_FST_S0_FST_MSK (0x00000003) + #define GODLAT_CR_G_ODLAT_FST_S0_FST_MAX (0x00000003) + #define GODLAT_CR_G_ODLAT_FST_S1_FST_OFF ( 2) + #define GODLAT_CR_G_ODLAT_FST_S1_FST_WID ( 2) + #define GODLAT_CR_G_ODLAT_FST_S1_FST_MSK (0x0000000C) + #define GODLAT_CR_G_ODLAT_FST_S1_FST_MAX (0x00000003) + #define GODLAT_CR_G_ODLAT_FST_S2_FST_OFF ( 4) + #define GODLAT_CR_G_ODLAT_FST_S2_FST_WID ( 2) + #define GODLAT_CR_G_ODLAT_FST_S2_FST_MSK (0x00000030) + #define GODLAT_CR_G_ODLAT_FST_S2_FST_MAX (0x00000003) + #define GODLAT_CR_G_ODLAT_FST_S3_FST_OFF ( 6) + #define GODLAT_CR_G_ODLAT_FST_S3_FST_WID ( 2) + #define GODLAT_CR_G_ODLAT_FST_S3_FST_MSK (0x000000C0) + #define GODLAT_CR_G_ODLAT_FST_S3_FST_MAX (0x00000003) + #define GODLAT_CR_G_ODLAT_FST_S4_FST_OFF ( 8) + #define GODLAT_CR_G_ODLAT_FST_S4_FST_WID ( 2) + #define GODLAT_CR_G_ODLAT_FST_S4_FST_MSK (0x00000300) + #define GODLAT_CR_G_ODLAT_FST_S4_FST_MAX (0x00000003) + #define GODLAT_CR_G_ODLAT_FST_S5_FST_OFF (10) + #define GODLAT_CR_G_ODLAT_FST_S5_FST_WID ( 2) + #define GODLAT_CR_G_ODLAT_FST_S5_FST_MSK (0x00000C00) + #define GODLAT_CR_G_ODLAT_FST_S5_FST_MAX (0x00000003) + #define GODLAT_CR_G_ODLAT_FST_S6_FST_OFF (12) + #define GODLAT_CR_G_ODLAT_FST_S6_FST_WID ( 2) + #define GODLAT_CR_G_ODLAT_FST_S6_FST_MSK (0x00003000) + #define GODLAT_CR_G_ODLAT_FST_S6_FST_MAX (0x00000003) + #define GODLAT_CR_G_ODLAT_FST_S7_FST_OFF (14) + #define GODLAT_CR_G_ODLAT_FST_S7_FST_WID ( 2) + #define GODLAT_CR_G_ODLAT_FST_S7_FST_MSK (0x0000C000) + #define GODLAT_CR_G_ODLAT_FST_S7_FST_MAX (0x00000003) + +#define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B0_REG (0x00000534) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B0_Arm_OFF ( 0) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B0_Arm_WID ( 8) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B0_Arm_MSK (0x000000FF) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B0_Arm_MAX (0x000000FF) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B0_MBP_Arm_OFF ( 8) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B0_MBP_Arm_WID ( 1) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B0_MBP_Arm_MSK (0x00000100) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B0_MBP_Arm_MAX (0x00000001) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B0_TO_Arm_OFF ( 9) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B0_TO_Arm_WID ( 4) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B0_TO_Arm_MSK (0x00001E00) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B0_TO_Arm_MAX (0x0000000F) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B0_Mask_OFF (16) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B0_Mask_WID ( 8) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B0_Mask_MSK (0x00FF0000) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B0_Mask_MAX (0x000000FF) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B0_MBP_Mask_OFF (24) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B0_MBP_Mask_WID ( 1) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B0_MBP_Mask_MSK (0x01000000) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B0_MBP_Mask_MAX (0x00000001) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B0_TO_Mask_OFF (25) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B0_TO_Mask_WID ( 4) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B0_TO_Mask_MSK (0x1E000000) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B0_TO_Mask_MAX (0x0000000F) + +#define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B1_REG (0x00000538) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B1_Arm_OFF ( 0) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B1_Arm_WID ( 8) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B1_Arm_MSK (0x000000FF) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B1_Arm_MAX (0x000000FF) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B1_MBP_Arm_OFF ( 8) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B1_MBP_Arm_WID ( 1) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B1_MBP_Arm_MSK (0x00000100) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B1_MBP_Arm_MAX (0x00000001) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B1_TO_Arm_OFF ( 9) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B1_TO_Arm_WID ( 4) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B1_TO_Arm_MSK (0x00001E00) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B1_TO_Arm_MAX (0x0000000F) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B1_Mask_OFF (16) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B1_Mask_WID ( 8) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B1_Mask_MSK (0x00FF0000) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B1_Mask_MAX (0x000000FF) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B1_MBP_Mask_OFF (24) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B1_MBP_Mask_WID ( 1) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B1_MBP_Mask_MSK (0x01000000) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B1_MBP_Mask_MAX (0x00000001) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B1_TO_Mask_OFF (25) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B1_TO_Mask_WID ( 4) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B1_TO_Mask_MSK (0x1E000000) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B1_TO_Mask_MAX (0x0000000F) + +#define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B2_REG (0x0000053C) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B2_Arm_OFF ( 0) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B2_Arm_WID ( 8) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B2_Arm_MSK (0x000000FF) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B2_Arm_MAX (0x000000FF) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B2_MBP_Arm_OFF ( 8) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B2_MBP_Arm_WID ( 1) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B2_MBP_Arm_MSK (0x00000100) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B2_MBP_Arm_MAX (0x00000001) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B2_TO_Arm_OFF ( 9) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B2_TO_Arm_WID ( 4) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B2_TO_Arm_MSK (0x00001E00) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B2_TO_Arm_MAX (0x0000000F) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B2_Mask_OFF (16) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B2_Mask_WID ( 8) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B2_Mask_MSK (0x00FF0000) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B2_Mask_MAX (0x000000FF) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B2_MBP_Mask_OFF (24) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B2_MBP_Mask_WID ( 1) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B2_MBP_Mask_MSK (0x01000000) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B2_MBP_Mask_MAX (0x00000001) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B2_TO_Mask_OFF (25) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B2_TO_Mask_WID ( 4) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B2_TO_Mask_MSK (0x1E000000) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B2_TO_Mask_MAX (0x0000000F) + +#define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B3_REG (0x00000540) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B3_Arm_OFF ( 0) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B3_Arm_WID ( 8) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B3_Arm_MSK (0x000000FF) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B3_Arm_MAX (0x000000FF) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B3_MBP_Arm_OFF ( 8) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B3_MBP_Arm_WID ( 1) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B3_MBP_Arm_MSK (0x00000100) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B3_MBP_Arm_MAX (0x00000001) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B3_TO_Arm_OFF ( 9) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B3_TO_Arm_WID ( 4) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B3_TO_Arm_MSK (0x00001E00) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B3_TO_Arm_MAX (0x0000000F) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B3_Mask_OFF (16) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B3_Mask_WID ( 8) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B3_Mask_MSK (0x00FF0000) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B3_Mask_MAX (0x000000FF) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B3_MBP_Mask_OFF (24) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B3_MBP_Mask_WID ( 1) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B3_MBP_Mask_MSK (0x01000000) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B3_MBP_Mask_MAX (0x00000001) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B3_TO_Mask_OFF (25) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B3_TO_Mask_WID ( 4) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B3_TO_Mask_MSK (0x1E000000) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B3_TO_Mask_MAX (0x0000000F) + +#define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B4_REG (0x00000544) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B4_Arm_OFF ( 0) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B4_Arm_WID ( 8) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B4_Arm_MSK (0x000000FF) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B4_Arm_MAX (0x000000FF) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B4_MBP_Arm_OFF ( 8) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B4_MBP_Arm_WID ( 1) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B4_MBP_Arm_MSK (0x00000100) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B4_MBP_Arm_MAX (0x00000001) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B4_TO_Arm_OFF ( 9) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B4_TO_Arm_WID ( 4) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B4_TO_Arm_MSK (0x00001E00) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B4_TO_Arm_MAX (0x0000000F) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B4_Mask_OFF (16) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B4_Mask_WID ( 8) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B4_Mask_MSK (0x00FF0000) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B4_Mask_MAX (0x000000FF) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B4_MBP_Mask_OFF (24) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B4_MBP_Mask_WID ( 1) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B4_MBP_Mask_MSK (0x01000000) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B4_MBP_Mask_MAX (0x00000001) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B4_TO_Mask_OFF (25) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B4_TO_Mask_WID ( 4) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B4_TO_Mask_MSK (0x1E000000) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B4_TO_Mask_MAX (0x0000000F) + +#define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B5_REG (0x00000548) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B5_Arm_OFF ( 0) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B5_Arm_WID ( 8) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B5_Arm_MSK (0x000000FF) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B5_Arm_MAX (0x000000FF) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B5_MBP_Arm_OFF ( 8) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B5_MBP_Arm_WID ( 1) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B5_MBP_Arm_MSK (0x00000100) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B5_MBP_Arm_MAX (0x00000001) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B5_TO_Arm_OFF ( 9) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B5_TO_Arm_WID ( 4) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B5_TO_Arm_MSK (0x00001E00) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B5_TO_Arm_MAX (0x0000000F) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B5_Mask_OFF (16) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B5_Mask_WID ( 8) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B5_Mask_MSK (0x00FF0000) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B5_Mask_MAX (0x000000FF) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B5_MBP_Mask_OFF (24) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B5_MBP_Mask_WID ( 1) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B5_MBP_Mask_MSK (0x01000000) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B5_MBP_Mask_MAX (0x00000001) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B5_TO_Mask_OFF (25) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B5_TO_Mask_WID ( 4) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B5_TO_Mask_MSK (0x1E000000) + #define GODLAT_CR_G_ODLAT_TR_IF_ARM_MASK_B5_TO_Mask_MAX (0x0000000F) + +#define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B0_REG (0x00000550) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B0_Arm_OFF ( 0) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B0_Arm_WID ( 8) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B0_Arm_MSK (0x000000FF) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B0_Arm_MAX (0x000000FF) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B0_MBP_Arm_OFF ( 8) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B0_MBP_Arm_WID ( 1) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B0_MBP_Arm_MSK (0x00000100) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B0_MBP_Arm_MAX (0x00000001) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B0_TO_Arm_OFF ( 9) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B0_TO_Arm_WID ( 4) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B0_TO_Arm_MSK (0x00001E00) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B0_TO_Arm_MAX (0x0000000F) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B0_Stop_OFF (13) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B0_Stop_WID ( 1) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B0_Stop_MSK (0x00002000) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B0_Stop_MAX (0x00000001) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B0_Mask_OFF (16) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B0_Mask_WID ( 8) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B0_Mask_MSK (0x00FF0000) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B0_Mask_MAX (0x000000FF) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B0_MBP_Mask_OFF (24) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B0_MBP_Mask_WID ( 1) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B0_MBP_Mask_MSK (0x01000000) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B0_MBP_Mask_MAX (0x00000001) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B0_TO_Mask_OFF (25) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B0_TO_Mask_WID ( 4) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B0_TO_Mask_MSK (0x1E000000) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B0_TO_Mask_MAX (0x0000000F) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B0_Col_Rst_OFF (29) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B0_Col_Rst_WID ( 1) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B0_Col_Rst_MSK (0x20000000) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B0_Col_Rst_MAX (0x00000001) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B0_Trigger_OFF (30) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B0_Trigger_WID ( 1) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B0_Trigger_MSK (0x40000000) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B0_Trigger_MAX (0x00000001) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B0_Start_OFF (31) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B0_Start_WID ( 1) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B0_Start_MSK (0x80000000) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B0_Start_MAX (0x00000001) + +#define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B0_REG (0x00000554) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B0_Arm_OFF ( 0) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B0_Arm_WID ( 8) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B0_Arm_MSK (0x000000FF) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B0_Arm_MAX (0x000000FF) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B0_MBP_Arm_OFF ( 8) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B0_MBP_Arm_WID ( 1) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B0_MBP_Arm_MSK (0x00000100) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B0_MBP_Arm_MAX (0x00000001) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B0_TO_Arm_OFF ( 9) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B0_TO_Arm_WID ( 4) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B0_TO_Arm_MSK (0x00001E00) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B0_TO_Arm_MAX (0x0000000F) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B0_Mask_OFF (16) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B0_Mask_WID ( 8) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B0_Mask_MSK (0x00FF0000) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B0_Mask_MAX (0x000000FF) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B0_MBP_Mask_OFF (24) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B0_MBP_Mask_WID ( 1) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B0_MBP_Mask_MSK (0x01000000) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B0_MBP_Mask_MAX (0x00000001) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B0_TO_Mask_OFF (25) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B0_TO_Mask_WID ( 4) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B0_TO_Mask_MSK (0x1E000000) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B0_TO_Mask_MAX (0x0000000F) + +#define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B1_REG (0x00000558) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B1_Arm_OFF ( 0) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B1_Arm_WID ( 8) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B1_Arm_MSK (0x000000FF) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B1_Arm_MAX (0x000000FF) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B1_MBP_Arm_OFF ( 8) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B1_MBP_Arm_WID ( 1) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B1_MBP_Arm_MSK (0x00000100) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B1_MBP_Arm_MAX (0x00000001) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B1_TO_Arm_OFF ( 9) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B1_TO_Arm_WID ( 4) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B1_TO_Arm_MSK (0x00001E00) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B1_TO_Arm_MAX (0x0000000F) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B1_Mask_OFF (16) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B1_Mask_WID ( 8) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B1_Mask_MSK (0x00FF0000) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B1_Mask_MAX (0x000000FF) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B1_MBP_Mask_OFF (24) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B1_MBP_Mask_WID ( 1) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B1_MBP_Mask_MSK (0x01000000) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B1_MBP_Mask_MAX (0x00000001) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B1_TO_Mask_OFF (25) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B1_TO_Mask_WID ( 4) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B1_TO_Mask_MSK (0x1E000000) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B1_TO_Mask_MAX (0x0000000F) + +#define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B2_REG (0x0000055C) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B2_Arm_OFF ( 0) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B2_Arm_WID ( 8) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B2_Arm_MSK (0x000000FF) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B2_Arm_MAX (0x000000FF) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B2_MBP_Arm_OFF ( 8) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B2_MBP_Arm_WID ( 1) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B2_MBP_Arm_MSK (0x00000100) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B2_MBP_Arm_MAX (0x00000001) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B2_TO_Arm_OFF ( 9) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B2_TO_Arm_WID ( 4) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B2_TO_Arm_MSK (0x00001E00) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B2_TO_Arm_MAX (0x0000000F) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B2_Mask_OFF (16) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B2_Mask_WID ( 8) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B2_Mask_MSK (0x00FF0000) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B2_Mask_MAX (0x000000FF) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B2_MBP_Mask_OFF (24) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B2_MBP_Mask_WID ( 1) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B2_MBP_Mask_MSK (0x01000000) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B2_MBP_Mask_MAX (0x00000001) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B2_TO_Mask_OFF (25) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B2_TO_Mask_WID ( 4) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B2_TO_Mask_MSK (0x1E000000) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B2_TO_Mask_MAX (0x0000000F) + +#define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B3_REG (0x00000560) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B3_Arm_OFF ( 0) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B3_Arm_WID ( 8) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B3_Arm_MSK (0x000000FF) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B3_Arm_MAX (0x000000FF) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B3_MBP_Arm_OFF ( 8) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B3_MBP_Arm_WID ( 1) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B3_MBP_Arm_MSK (0x00000100) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B3_MBP_Arm_MAX (0x00000001) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B3_TO_Arm_OFF ( 9) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B3_TO_Arm_WID ( 4) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B3_TO_Arm_MSK (0x00001E00) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B3_TO_Arm_MAX (0x0000000F) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B3_Mask_OFF (16) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B3_Mask_WID ( 8) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B3_Mask_MSK (0x00FF0000) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B3_Mask_MAX (0x000000FF) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B3_MBP_Mask_OFF (24) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B3_MBP_Mask_WID ( 1) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B3_MBP_Mask_MSK (0x01000000) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B3_MBP_Mask_MAX (0x00000001) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B3_TO_Mask_OFF (25) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B3_TO_Mask_WID ( 4) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B3_TO_Mask_MSK (0x1E000000) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B3_TO_Mask_MAX (0x0000000F) + +#define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B4_REG (0x00000564) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B4_Arm_OFF ( 0) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B4_Arm_WID ( 8) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B4_Arm_MSK (0x000000FF) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B4_Arm_MAX (0x000000FF) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B4_MBP_Arm_OFF ( 8) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B4_MBP_Arm_WID ( 1) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B4_MBP_Arm_MSK (0x00000100) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B4_MBP_Arm_MAX (0x00000001) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B4_TO_Arm_OFF ( 9) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B4_TO_Arm_WID ( 4) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B4_TO_Arm_MSK (0x00001E00) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B4_TO_Arm_MAX (0x0000000F) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B4_Mask_OFF (16) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B4_Mask_WID ( 8) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B4_Mask_MSK (0x00FF0000) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B4_Mask_MAX (0x000000FF) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B4_MBP_Mask_OFF (24) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B4_MBP_Mask_WID ( 1) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B4_MBP_Mask_MSK (0x01000000) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B4_MBP_Mask_MAX (0x00000001) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B4_TO_Mask_OFF (25) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B4_TO_Mask_WID ( 4) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B4_TO_Mask_MSK (0x1E000000) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B4_TO_Mask_MAX (0x0000000F) + +#define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B5_REG (0x00000568) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B5_Arm_OFF ( 0) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B5_Arm_WID ( 8) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B5_Arm_MSK (0x000000FF) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B5_Arm_MAX (0x000000FF) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B5_MBP_Arm_OFF ( 8) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B5_MBP_Arm_WID ( 1) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B5_MBP_Arm_MSK (0x00000100) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B5_MBP_Arm_MAX (0x00000001) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B5_TO_Arm_OFF ( 9) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B5_TO_Arm_WID ( 4) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B5_TO_Arm_MSK (0x00001E00) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B5_TO_Arm_MAX (0x0000000F) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B5_Mask_OFF (16) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B5_Mask_WID ( 8) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B5_Mask_MSK (0x00FF0000) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B5_Mask_MAX (0x000000FF) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B5_MBP_Mask_OFF (24) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B5_MBP_Mask_WID ( 1) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B5_MBP_Mask_MSK (0x01000000) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B5_MBP_Mask_MAX (0x00000001) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B5_TO_Mask_OFF (25) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B5_TO_Mask_WID ( 4) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B5_TO_Mask_MSK (0x1E000000) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ARM_MASK_B5_TO_Mask_MAX (0x0000000F) + +#define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B1_REG (0x00000570) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B1_Arm_OFF ( 0) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B1_Arm_WID ( 8) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B1_Arm_MSK (0x000000FF) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B1_Arm_MAX (0x000000FF) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B1_MBP_Arm_OFF ( 8) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B1_MBP_Arm_WID ( 1) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B1_MBP_Arm_MSK (0x00000100) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B1_MBP_Arm_MAX (0x00000001) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B1_TO_Arm_OFF ( 9) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B1_TO_Arm_WID ( 4) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B1_TO_Arm_MSK (0x00001E00) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B1_TO_Arm_MAX (0x0000000F) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B1_Stop_OFF (13) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B1_Stop_WID ( 1) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B1_Stop_MSK (0x00002000) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B1_Stop_MAX (0x00000001) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B1_Mask_OFF (16) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B1_Mask_WID ( 8) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B1_Mask_MSK (0x00FF0000) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B1_Mask_MAX (0x000000FF) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B1_MBP_Mask_OFF (24) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B1_MBP_Mask_WID ( 1) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B1_MBP_Mask_MSK (0x01000000) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B1_MBP_Mask_MAX (0x00000001) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B1_TO_Mask_OFF (25) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B1_TO_Mask_WID ( 4) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B1_TO_Mask_MSK (0x1E000000) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B1_TO_Mask_MAX (0x0000000F) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B1_Col_Rst_OFF (29) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B1_Col_Rst_WID ( 1) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B1_Col_Rst_MSK (0x20000000) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B1_Col_Rst_MAX (0x00000001) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B1_Trigger_OFF (30) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B1_Trigger_WID ( 1) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B1_Trigger_MSK (0x40000000) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B1_Trigger_MAX (0x00000001) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B1_Start_OFF (31) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B1_Start_WID ( 1) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B1_Start_MSK (0x80000000) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_ELSEIF_ARM_MASK_B1_Start_MAX (0x00000001) + +#define GODLAT_CR_G_ODLAT_TR_IF_MODE_B0_B1_REG (0x00000574) + #define GODLAT_CR_G_ODLAT_TR_IF_MODE_B0_B1_B0_Set_OFF ( 0) + #define GODLAT_CR_G_ODLAT_TR_IF_MODE_B0_B1_B0_Set_WID ( 6) + #define GODLAT_CR_G_ODLAT_TR_IF_MODE_B0_B1_B0_Set_MSK (0x0000003F) + #define GODLAT_CR_G_ODLAT_TR_IF_MODE_B0_B1_B0_Set_MAX (0x0000003F) + #define GODLAT_CR_G_ODLAT_TR_IF_MODE_B0_B1_B0_Rst_OFF ( 6) + #define GODLAT_CR_G_ODLAT_TR_IF_MODE_B0_B1_B0_Rst_WID ( 6) + #define GODLAT_CR_G_ODLAT_TR_IF_MODE_B0_B1_B0_Rst_MSK (0x00000FC0) + #define GODLAT_CR_G_ODLAT_TR_IF_MODE_B0_B1_B0_Rst_MAX (0x0000003F) + #define GODLAT_CR_G_ODLAT_TR_IF_MODE_B0_B1_B1_Set_OFF (12) + #define GODLAT_CR_G_ODLAT_TR_IF_MODE_B0_B1_B1_Set_WID ( 6) + #define GODLAT_CR_G_ODLAT_TR_IF_MODE_B0_B1_B1_Set_MSK (0x0003F000) + #define GODLAT_CR_G_ODLAT_TR_IF_MODE_B0_B1_B1_Set_MAX (0x0000003F) + #define GODLAT_CR_G_ODLAT_TR_IF_MODE_B0_B1_B1_Rst_OFF (18) + #define GODLAT_CR_G_ODLAT_TR_IF_MODE_B0_B1_B1_Rst_WID ( 6) + #define GODLAT_CR_G_ODLAT_TR_IF_MODE_B0_B1_B1_Rst_MSK (0x00FC0000) + #define GODLAT_CR_G_ODLAT_TR_IF_MODE_B0_B1_B1_Rst_MAX (0x0000003F) + +#define GODLAT_CR_G_ODLAT_TR_IF_MODE_B2_B3_REG (0x00000578) + #define GODLAT_CR_G_ODLAT_TR_IF_MODE_B2_B3_B2_Set_OFF ( 0) + #define GODLAT_CR_G_ODLAT_TR_IF_MODE_B2_B3_B2_Set_WID ( 6) + #define GODLAT_CR_G_ODLAT_TR_IF_MODE_B2_B3_B2_Set_MSK (0x0000003F) + #define GODLAT_CR_G_ODLAT_TR_IF_MODE_B2_B3_B2_Set_MAX (0x0000003F) + #define GODLAT_CR_G_ODLAT_TR_IF_MODE_B2_B3_B2_Rst_OFF ( 6) + #define GODLAT_CR_G_ODLAT_TR_IF_MODE_B2_B3_B2_Rst_WID ( 6) + #define GODLAT_CR_G_ODLAT_TR_IF_MODE_B2_B3_B2_Rst_MSK (0x00000FC0) + #define GODLAT_CR_G_ODLAT_TR_IF_MODE_B2_B3_B2_Rst_MAX (0x0000003F) + #define GODLAT_CR_G_ODLAT_TR_IF_MODE_B2_B3_B3_Set_OFF (12) + #define GODLAT_CR_G_ODLAT_TR_IF_MODE_B2_B3_B3_Set_WID ( 6) + #define GODLAT_CR_G_ODLAT_TR_IF_MODE_B2_B3_B3_Set_MSK (0x0003F000) + #define GODLAT_CR_G_ODLAT_TR_IF_MODE_B2_B3_B3_Set_MAX (0x0000003F) + #define GODLAT_CR_G_ODLAT_TR_IF_MODE_B2_B3_B3_Rst_OFF (18) + #define GODLAT_CR_G_ODLAT_TR_IF_MODE_B2_B3_B3_Rst_WID ( 6) + #define GODLAT_CR_G_ODLAT_TR_IF_MODE_B2_B3_B3_Rst_MSK (0x00FC0000) + #define GODLAT_CR_G_ODLAT_TR_IF_MODE_B2_B3_B3_Rst_MAX (0x0000003F) + +#define GODLAT_CR_G_ODLAT_TR_IF_MODE_B4_B5_REG (0x0000057C) + #define GODLAT_CR_G_ODLAT_TR_IF_MODE_B4_B5_B4_Set_OFF ( 0) + #define GODLAT_CR_G_ODLAT_TR_IF_MODE_B4_B5_B4_Set_WID ( 6) + #define GODLAT_CR_G_ODLAT_TR_IF_MODE_B4_B5_B4_Set_MSK (0x0000003F) + #define GODLAT_CR_G_ODLAT_TR_IF_MODE_B4_B5_B4_Set_MAX (0x0000003F) + #define GODLAT_CR_G_ODLAT_TR_IF_MODE_B4_B5_B4_Rst_OFF ( 6) + #define GODLAT_CR_G_ODLAT_TR_IF_MODE_B4_B5_B4_Rst_WID ( 6) + #define GODLAT_CR_G_ODLAT_TR_IF_MODE_B4_B5_B4_Rst_MSK (0x00000FC0) + #define GODLAT_CR_G_ODLAT_TR_IF_MODE_B4_B5_B4_Rst_MAX (0x0000003F) + #define GODLAT_CR_G_ODLAT_TR_IF_MODE_B4_B5_B5_Set_OFF (12) + #define GODLAT_CR_G_ODLAT_TR_IF_MODE_B4_B5_B5_Set_WID ( 6) + #define GODLAT_CR_G_ODLAT_TR_IF_MODE_B4_B5_B5_Set_MSK (0x0003F000) + #define GODLAT_CR_G_ODLAT_TR_IF_MODE_B4_B5_B5_Set_MAX (0x0000003F) + #define GODLAT_CR_G_ODLAT_TR_IF_MODE_B4_B5_B5_Rst_OFF (18) + #define GODLAT_CR_G_ODLAT_TR_IF_MODE_B4_B5_B5_Rst_WID ( 6) + #define GODLAT_CR_G_ODLAT_TR_IF_MODE_B4_B5_B5_Rst_MSK (0x00FC0000) + #define GODLAT_CR_G_ODLAT_TR_IF_MODE_B4_B5_B5_Rst_MAX (0x0000003F) + +#define GODLAT_CR_G_ODLAT_TR_IF_MODE_B6_B7_REG (0x00000580) + #define GODLAT_CR_G_ODLAT_TR_IF_MODE_B6_B7_ElseIf_ElseIf_B0_Set_OFF ( 0) + #define GODLAT_CR_G_ODLAT_TR_IF_MODE_B6_B7_ElseIf_ElseIf_B0_Set_WID ( 6) + #define GODLAT_CR_G_ODLAT_TR_IF_MODE_B6_B7_ElseIf_ElseIf_B0_Set_MSK (0x0000003F) + #define GODLAT_CR_G_ODLAT_TR_IF_MODE_B6_B7_ElseIf_ElseIf_B0_Set_MAX (0x0000003F) + #define GODLAT_CR_G_ODLAT_TR_IF_MODE_B6_B7_ElseIf_ElseIf_B0_Rst_OFF ( 6) + #define GODLAT_CR_G_ODLAT_TR_IF_MODE_B6_B7_ElseIf_ElseIf_B0_Rst_WID ( 6) + #define GODLAT_CR_G_ODLAT_TR_IF_MODE_B6_B7_ElseIf_ElseIf_B0_Rst_MSK (0x00000FC0) + #define GODLAT_CR_G_ODLAT_TR_IF_MODE_B6_B7_ElseIf_ElseIf_B0_Rst_MAX (0x0000003F) + +#define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_B0_B1_REG (0x00000584) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_B0_B1_B0_Set_OFF ( 0) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_B0_B1_B0_Set_WID ( 6) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_B0_B1_B0_Set_MSK (0x0000003F) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_B0_B1_B0_Set_MAX (0x0000003F) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_B0_B1_B0_Rst_OFF ( 6) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_B0_B1_B0_Rst_WID ( 6) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_B0_B1_B0_Rst_MSK (0x00000FC0) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_B0_B1_B0_Rst_MAX (0x0000003F) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_B0_B1_B1_Set_OFF (12) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_B0_B1_B1_Set_WID ( 6) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_B0_B1_B1_Set_MSK (0x0003F000) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_B0_B1_B1_Set_MAX (0x0000003F) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_B0_B1_B1_Rst_OFF (18) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_B0_B1_B1_Rst_WID ( 6) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_B0_B1_B1_Rst_MSK (0x00FC0000) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_B0_B1_B1_Rst_MAX (0x0000003F) + +#define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_B2_B3_REG (0x00000588) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_B2_B3_B2_Set_OFF ( 0) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_B2_B3_B2_Set_WID ( 6) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_B2_B3_B2_Set_MSK (0x0000003F) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_B2_B3_B2_Set_MAX (0x0000003F) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_B2_B3_B2_Rst_OFF ( 6) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_B2_B3_B2_Rst_WID ( 6) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_B2_B3_B2_Rst_MSK (0x00000FC0) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_B2_B3_B2_Rst_MAX (0x0000003F) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_B2_B3_B3_Set_OFF (12) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_B2_B3_B3_Set_WID ( 6) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_B2_B3_B3_Set_MSK (0x0003F000) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_B2_B3_B3_Set_MAX (0x0000003F) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_B2_B3_B3_Rst_OFF (18) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_B2_B3_B3_Rst_WID ( 6) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_B2_B3_B3_Rst_MSK (0x00FC0000) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_B2_B3_B3_Rst_MAX (0x0000003F) + +#define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_B4_B5_REG (0x0000058C) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_B4_B5_B4_Set_OFF ( 0) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_B4_B5_B4_Set_WID ( 6) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_B4_B5_B4_Set_MSK (0x0000003F) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_B4_B5_B4_Set_MAX (0x0000003F) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_B4_B5_B4_Rst_OFF ( 6) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_B4_B5_B4_Rst_WID ( 6) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_B4_B5_B4_Rst_MSK (0x00000FC0) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_B4_B5_B4_Rst_MAX (0x0000003F) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_B4_B5_B5_Set_OFF (12) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_B4_B5_B5_Set_WID ( 6) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_B4_B5_B5_Set_MSK (0x0003F000) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_B4_B5_B5_Set_MAX (0x0000003F) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_B4_B5_B5_Rst_OFF (18) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_B4_B5_B5_Rst_WID ( 6) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_B4_B5_B5_Rst_MSK (0x00FC0000) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_B4_B5_B5_Rst_MAX (0x0000003F) + +#define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_B6_B7_REG (0x00000590) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_B6_B7_ElseIf_ElseIf_B1_Set_OFF ( 0) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_B6_B7_ElseIf_ElseIf_B1_Set_WID ( 6) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_B6_B7_ElseIf_ElseIf_B1_Set_MSK (0x0000003F) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_B6_B7_ElseIf_ElseIf_B1_Set_MAX (0x0000003F) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_B6_B7_ElseIf_ElseIf_B1_Rst_OFF ( 6) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_B6_B7_ElseIf_ElseIf_B1_Rst_WID ( 6) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_B6_B7_ElseIf_ElseIf_B1_Rst_MSK (0x00000FC0) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_B6_B7_ElseIf_ElseIf_B1_Rst_MAX (0x0000003F) + +#define GODLAT_CR_G_ODLAT_INIT_BUBBLES_REG (0x00000594) + #define GODLAT_CR_G_ODLAT_INIT_BUBBLES_Init_Bits_OFF ( 0) + #define GODLAT_CR_G_ODLAT_INIT_BUBBLES_Init_Bits_WID ( 6) + #define GODLAT_CR_G_ODLAT_INIT_BUBBLES_Init_Bits_MSK (0x0000003F) + #define GODLAT_CR_G_ODLAT_INIT_BUBBLES_Init_Bits_MAX (0x0000003F) + +#define GODLAT_CR_G_ODLAT_TR_IF_MODE_MISC_REG (0x00000598) + #define GODLAT_CR_G_ODLAT_TR_IF_MODE_MISC_ColRst_OFF ( 0) + #define GODLAT_CR_G_ODLAT_TR_IF_MODE_MISC_ColRst_WID ( 6) + #define GODLAT_CR_G_ODLAT_TR_IF_MODE_MISC_ColRst_MSK (0x0000003F) + #define GODLAT_CR_G_ODLAT_TR_IF_MODE_MISC_ColRst_MAX (0x0000003F) + #define GODLAT_CR_G_ODLAT_TR_IF_MODE_MISC_Start_OFF ( 6) + #define GODLAT_CR_G_ODLAT_TR_IF_MODE_MISC_Start_WID ( 6) + #define GODLAT_CR_G_ODLAT_TR_IF_MODE_MISC_Start_MSK (0x00000FC0) + #define GODLAT_CR_G_ODLAT_TR_IF_MODE_MISC_Start_MAX (0x0000003F) + #define GODLAT_CR_G_ODLAT_TR_IF_MODE_MISC_Trigger_OFF (12) + #define GODLAT_CR_G_ODLAT_TR_IF_MODE_MISC_Trigger_WID ( 6) + #define GODLAT_CR_G_ODLAT_TR_IF_MODE_MISC_Trigger_MSK (0x0003F000) + #define GODLAT_CR_G_ODLAT_TR_IF_MODE_MISC_Trigger_MAX (0x0000003F) + #define GODLAT_CR_G_ODLAT_TR_IF_MODE_MISC_Stop_OFF (18) + #define GODLAT_CR_G_ODLAT_TR_IF_MODE_MISC_Stop_WID ( 6) + #define GODLAT_CR_G_ODLAT_TR_IF_MODE_MISC_Stop_MSK (0x00FC0000) + #define GODLAT_CR_G_ODLAT_TR_IF_MODE_MISC_Stop_MAX (0x0000003F) + +#define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_MISC_REG (0x0000059C) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_MISC_ColRst_OFF ( 0) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_MISC_ColRst_WID ( 6) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_MISC_ColRst_MSK (0x0000003F) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_MISC_ColRst_MAX (0x0000003F) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_MISC_Start_OFF ( 6) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_MISC_Start_WID ( 6) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_MISC_Start_MSK (0x00000FC0) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_MISC_Start_MAX (0x0000003F) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_MISC_Trigger_OFF (12) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_MISC_Trigger_WID ( 6) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_MISC_Trigger_MSK (0x0003F000) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_MISC_Trigger_MAX (0x0000003F) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_MISC_Stop_OFF (18) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_MISC_Stop_WID ( 6) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_MISC_Stop_MSK (0x00FC0000) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_MISC_Stop_MAX (0x0000003F) + +#define GODLAT_CR_G_ODLAT_TR_IF_MODE_TMREN_REG (0x00000600) + #define GODLAT_CR_G_ODLAT_TR_IF_MODE_TMREN_B0_EN_OFF ( 0) + #define GODLAT_CR_G_ODLAT_TR_IF_MODE_TMREN_B0_EN_WID ( 4) + #define GODLAT_CR_G_ODLAT_TR_IF_MODE_TMREN_B0_EN_MSK (0x0000000F) + #define GODLAT_CR_G_ODLAT_TR_IF_MODE_TMREN_B0_EN_MAX (0x0000000F) + #define GODLAT_CR_G_ODLAT_TR_IF_MODE_TMREN_B1_EN_OFF ( 4) + #define GODLAT_CR_G_ODLAT_TR_IF_MODE_TMREN_B1_EN_WID ( 4) + #define GODLAT_CR_G_ODLAT_TR_IF_MODE_TMREN_B1_EN_MSK (0x000000F0) + #define GODLAT_CR_G_ODLAT_TR_IF_MODE_TMREN_B1_EN_MAX (0x0000000F) + #define GODLAT_CR_G_ODLAT_TR_IF_MODE_TMREN_B2_EN_OFF ( 8) + #define GODLAT_CR_G_ODLAT_TR_IF_MODE_TMREN_B2_EN_WID ( 4) + #define GODLAT_CR_G_ODLAT_TR_IF_MODE_TMREN_B2_EN_MSK (0x00000F00) + #define GODLAT_CR_G_ODLAT_TR_IF_MODE_TMREN_B2_EN_MAX (0x0000000F) + #define GODLAT_CR_G_ODLAT_TR_IF_MODE_TMREN_B3_EN_OFF (12) + #define GODLAT_CR_G_ODLAT_TR_IF_MODE_TMREN_B3_EN_WID ( 4) + #define GODLAT_CR_G_ODLAT_TR_IF_MODE_TMREN_B3_EN_MSK (0x0000F000) + #define GODLAT_CR_G_ODLAT_TR_IF_MODE_TMREN_B3_EN_MAX (0x0000000F) + #define GODLAT_CR_G_ODLAT_TR_IF_MODE_TMREN_B4_EN_OFF (16) + #define GODLAT_CR_G_ODLAT_TR_IF_MODE_TMREN_B4_EN_WID ( 4) + #define GODLAT_CR_G_ODLAT_TR_IF_MODE_TMREN_B4_EN_MSK (0x000F0000) + #define GODLAT_CR_G_ODLAT_TR_IF_MODE_TMREN_B4_EN_MAX (0x0000000F) + #define GODLAT_CR_G_ODLAT_TR_IF_MODE_TMREN_B5_EN_OFF (20) + #define GODLAT_CR_G_ODLAT_TR_IF_MODE_TMREN_B5_EN_WID ( 4) + #define GODLAT_CR_G_ODLAT_TR_IF_MODE_TMREN_B5_EN_MSK (0x00F00000) + #define GODLAT_CR_G_ODLAT_TR_IF_MODE_TMREN_B5_EN_MAX (0x0000000F) + #define GODLAT_CR_G_ODLAT_TR_IF_MODE_TMREN_ELSEIF_ELSEIF_B0_EN_OFF (24) + #define GODLAT_CR_G_ODLAT_TR_IF_MODE_TMREN_ELSEIF_ELSEIF_B0_EN_WID ( 4) + #define GODLAT_CR_G_ODLAT_TR_IF_MODE_TMREN_ELSEIF_ELSEIF_B0_EN_MSK (0x0F000000) + #define GODLAT_CR_G_ODLAT_TR_IF_MODE_TMREN_ELSEIF_ELSEIF_B0_EN_MAX (0x0000000F) + +#define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_TMREN_REG (0x00000604) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_TMREN_B0_EN_OFF ( 0) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_TMREN_B0_EN_WID ( 4) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_TMREN_B0_EN_MSK (0x0000000F) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_TMREN_B0_EN_MAX (0x0000000F) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_TMREN_B1_EN_OFF ( 4) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_TMREN_B1_EN_WID ( 4) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_TMREN_B1_EN_MSK (0x000000F0) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_TMREN_B1_EN_MAX (0x0000000F) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_TMREN_B2_EN_OFF ( 8) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_TMREN_B2_EN_WID ( 4) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_TMREN_B2_EN_MSK (0x00000F00) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_TMREN_B2_EN_MAX (0x0000000F) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_TMREN_B3_EN_OFF (12) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_TMREN_B3_EN_WID ( 4) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_TMREN_B3_EN_MSK (0x0000F000) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_TMREN_B3_EN_MAX (0x0000000F) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_TMREN_B4_EN_OFF (16) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_TMREN_B4_EN_WID ( 4) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_TMREN_B4_EN_MSK (0x000F0000) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_TMREN_B4_EN_MAX (0x0000000F) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_TMREN_B5_EN_OFF (20) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_TMREN_B5_EN_WID ( 4) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_TMREN_B5_EN_MSK (0x00F00000) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_TMREN_B5_EN_MAX (0x0000000F) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_TMREN_ELSEIF_ELSEIF_B1_EN_OFF (24) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_TMREN_ELSEIF_ELSEIF_B1_EN_WID ( 4) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_TMREN_ELSEIF_ELSEIF_B1_EN_MSK (0x0F000000) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_TMREN_ELSEIF_ELSEIF_B1_EN_MAX (0x0000000F) + +#define GODLAT_CR_G_ODLAT_TIMER_PRELOAD_REG (0x00000608) + #define GODLAT_CR_G_ODLAT_TIMER_PRELOAD_Timer0_load_OFF ( 0) + #define GODLAT_CR_G_ODLAT_TIMER_PRELOAD_Timer0_load_WID ( 5) + #define GODLAT_CR_G_ODLAT_TIMER_PRELOAD_Timer0_load_MSK (0x0000001F) + #define GODLAT_CR_G_ODLAT_TIMER_PRELOAD_Timer0_load_MAX (0x0000001F) + #define GODLAT_CR_G_ODLAT_TIMER_PRELOAD_Timer0_load_DEF (0x00000000) + #define GODLAT_CR_G_ODLAT_TIMER_PRELOAD_Timer1_load_OFF ( 5) + #define GODLAT_CR_G_ODLAT_TIMER_PRELOAD_Timer1_load_WID ( 5) + #define GODLAT_CR_G_ODLAT_TIMER_PRELOAD_Timer1_load_MSK (0x000003E0) + #define GODLAT_CR_G_ODLAT_TIMER_PRELOAD_Timer1_load_MAX (0x0000001F) + #define GODLAT_CR_G_ODLAT_TIMER_PRELOAD_Timer1_load_DEF (0x00000000) + #define GODLAT_CR_G_ODLAT_TIMER_PRELOAD_Timer2_load_OFF (10) + #define GODLAT_CR_G_ODLAT_TIMER_PRELOAD_Timer2_load_WID ( 5) + #define GODLAT_CR_G_ODLAT_TIMER_PRELOAD_Timer2_load_MSK (0x00007C00) + #define GODLAT_CR_G_ODLAT_TIMER_PRELOAD_Timer2_load_MAX (0x0000001F) + #define GODLAT_CR_G_ODLAT_TIMER_PRELOAD_Timer2_load_DEF (0x00000000) + #define GODLAT_CR_G_ODLAT_TIMER_PRELOAD_Timer3_load_OFF (15) + #define GODLAT_CR_G_ODLAT_TIMER_PRELOAD_Timer3_load_WID (16) + #define GODLAT_CR_G_ODLAT_TIMER_PRELOAD_Timer3_load_MSK (0x7FFF8000) + #define GODLAT_CR_G_ODLAT_TIMER_PRELOAD_Timer3_load_MAX (0x0000FFFF) + #define GODLAT_CR_G_ODLAT_TIMER_PRELOAD_Timer3_load_DEF (0x00000000) + +#define GODLAT_CR_G_ODLAT_MOT_HDR_HIT_REG (0x0000060C) + #define GODLAT_CR_G_ODLAT_MOT_HDR_HIT_MOT_PKT_OFF ( 0) + #define GODLAT_CR_G_ODLAT_MOT_HDR_HIT_MOT_PKT_WID ( 8) + #define GODLAT_CR_G_ODLAT_MOT_HDR_HIT_MOT_PKT_MSK (0x000000FF) + #define GODLAT_CR_G_ODLAT_MOT_HDR_HIT_MOT_PKT_MAX (0x000000FF) + +#define GODLAT_CR_G_ODLAT_TR_IF_MODE_TMRRST_REG (0x00000610) + #define GODLAT_CR_G_ODLAT_TR_IF_MODE_TMRRST_B0_RST_OFF ( 0) + #define GODLAT_CR_G_ODLAT_TR_IF_MODE_TMRRST_B0_RST_WID ( 4) + #define GODLAT_CR_G_ODLAT_TR_IF_MODE_TMRRST_B0_RST_MSK (0x0000000F) + #define GODLAT_CR_G_ODLAT_TR_IF_MODE_TMRRST_B0_RST_MAX (0x0000000F) + #define GODLAT_CR_G_ODLAT_TR_IF_MODE_TMRRST_B1_RST_OFF ( 4) + #define GODLAT_CR_G_ODLAT_TR_IF_MODE_TMRRST_B1_RST_WID ( 4) + #define GODLAT_CR_G_ODLAT_TR_IF_MODE_TMRRST_B1_RST_MSK (0x000000F0) + #define GODLAT_CR_G_ODLAT_TR_IF_MODE_TMRRST_B1_RST_MAX (0x0000000F) + #define GODLAT_CR_G_ODLAT_TR_IF_MODE_TMRRST_B2_RST_OFF ( 8) + #define GODLAT_CR_G_ODLAT_TR_IF_MODE_TMRRST_B2_RST_WID ( 4) + #define GODLAT_CR_G_ODLAT_TR_IF_MODE_TMRRST_B2_RST_MSK (0x00000F00) + #define GODLAT_CR_G_ODLAT_TR_IF_MODE_TMRRST_B2_RST_MAX (0x0000000F) + #define GODLAT_CR_G_ODLAT_TR_IF_MODE_TMRRST_B3_RST_OFF (12) + #define GODLAT_CR_G_ODLAT_TR_IF_MODE_TMRRST_B3_RST_WID ( 4) + #define GODLAT_CR_G_ODLAT_TR_IF_MODE_TMRRST_B3_RST_MSK (0x0000F000) + #define GODLAT_CR_G_ODLAT_TR_IF_MODE_TMRRST_B3_RST_MAX (0x0000000F) + #define GODLAT_CR_G_ODLAT_TR_IF_MODE_TMRRST_B4_RST_OFF (16) + #define GODLAT_CR_G_ODLAT_TR_IF_MODE_TMRRST_B4_RST_WID ( 4) + #define GODLAT_CR_G_ODLAT_TR_IF_MODE_TMRRST_B4_RST_MSK (0x000F0000) + #define GODLAT_CR_G_ODLAT_TR_IF_MODE_TMRRST_B4_RST_MAX (0x0000000F) + #define GODLAT_CR_G_ODLAT_TR_IF_MODE_TMRRST_B5_RST_OFF (20) + #define GODLAT_CR_G_ODLAT_TR_IF_MODE_TMRRST_B5_RST_WID ( 4) + #define GODLAT_CR_G_ODLAT_TR_IF_MODE_TMRRST_B5_RST_MSK (0x00F00000) + #define GODLAT_CR_G_ODLAT_TR_IF_MODE_TMRRST_B5_RST_MAX (0x0000000F) + #define GODLAT_CR_G_ODLAT_TR_IF_MODE_TMRRST_ELSEIF_ELSEIF_B0_RST_OFF (24) + #define GODLAT_CR_G_ODLAT_TR_IF_MODE_TMRRST_ELSEIF_ELSEIF_B0_RST_WID ( 4) + #define GODLAT_CR_G_ODLAT_TR_IF_MODE_TMRRST_ELSEIF_ELSEIF_B0_RST_MSK (0x0F000000) + #define GODLAT_CR_G_ODLAT_TR_IF_MODE_TMRRST_ELSEIF_ELSEIF_B0_RST_MAX (0x0000000F) + +#define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_TMRRST_REG (0x00000614) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_TMRRST_B0_RST_OFF ( 0) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_TMRRST_B0_RST_WID ( 4) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_TMRRST_B0_RST_MSK (0x0000000F) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_TMRRST_B0_RST_MAX (0x0000000F) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_TMRRST_B1_RST_OFF ( 4) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_TMRRST_B1_RST_WID ( 4) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_TMRRST_B1_RST_MSK (0x000000F0) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_TMRRST_B1_RST_MAX (0x0000000F) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_TMRRST_B2_RST_OFF ( 8) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_TMRRST_B2_RST_WID ( 4) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_TMRRST_B2_RST_MSK (0x00000F00) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_TMRRST_B2_RST_MAX (0x0000000F) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_TMRRST_B3_RST_OFF (12) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_TMRRST_B3_RST_WID ( 4) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_TMRRST_B3_RST_MSK (0x0000F000) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_TMRRST_B3_RST_MAX (0x0000000F) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_TMRRST_B4_RST_OFF (16) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_TMRRST_B4_RST_WID ( 4) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_TMRRST_B4_RST_MSK (0x000F0000) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_TMRRST_B4_RST_MAX (0x0000000F) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_TMRRST_B5_RST_OFF (20) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_TMRRST_B5_RST_WID ( 4) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_TMRRST_B5_RST_MSK (0x00F00000) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_TMRRST_B5_RST_MAX (0x0000000F) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_TMRRST_ELSEIF_ELSEIF_B1_RST_OFF (24) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_TMRRST_ELSEIF_ELSEIF_B1_RST_WID ( 4) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_TMRRST_ELSEIF_ELSEIF_B1_RST_MSK (0x0F000000) + #define GODLAT_CR_G_ODLAT_TR_ELSEIF_MODE_TMRRST_ELSEIF_ELSEIF_B1_RST_MAX (0x0000000F) + +#define GDXC_CR_DEBUP_REG (0x00000700) + #define GDXC_CR_DEBUP_SPARE_OFF ( 0) + #define GDXC_CR_DEBUP_SPARE_WID ( 8) + #define GDXC_CR_DEBUP_SPARE_MSK (0x000000FF) + #define GDXC_CR_DEBUP_SPARE_MAX (0x000000FF) + #define GDXC_CR_DEBUP_SPARE_DEF (0x00000000) + +#define MSGUTILS_CR_VISA2OCLA_CFG_REG (0x00000A04) + #define MSGUTILS_CR_VISA2OCLA_CFG_Ln0Src_OFF ( 0) + #define MSGUTILS_CR_VISA2OCLA_CFG_Ln0Src_WID ( 2) + #define MSGUTILS_CR_VISA2OCLA_CFG_Ln0Src_MSK (0x00000003) + #define MSGUTILS_CR_VISA2OCLA_CFG_Ln0Src_MAX (0x00000003) + #define MSGUTILS_CR_VISA2OCLA_CFG_Ln0Src_DEF (0x00000002) + #define MSGUTILS_CR_VISA2OCLA_CFG_Ln1Src_OFF ( 2) + #define MSGUTILS_CR_VISA2OCLA_CFG_Ln1Src_WID ( 2) + #define MSGUTILS_CR_VISA2OCLA_CFG_Ln1Src_MSK (0x0000000C) + #define MSGUTILS_CR_VISA2OCLA_CFG_Ln1Src_MAX (0x00000003) + #define MSGUTILS_CR_VISA2OCLA_CFG_Ln1Src_DEF (0x00000002) + #define MSGUTILS_CR_VISA2OCLA_CFG_DEVisaEn_OFF ( 4) + #define MSGUTILS_CR_VISA2OCLA_CFG_DEVisaEn_WID ( 1) + #define MSGUTILS_CR_VISA2OCLA_CFG_DEVisaEn_MSK (0x00000010) + #define MSGUTILS_CR_VISA2OCLA_CFG_DEVisaEn_MAX (0x00000001) + #define MSGUTILS_CR_VISA2OCLA_CFG_DEVisaEn_DEF (0x00000000) + +#pragma pack(pop) +#endif // __McGdxcbar_h__ diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcRegisters/McIoCkeCtl.h b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcRegisters/McIoCkeCtl.h new file mode 100644 index 0000000..45afcc5 --- /dev/null +++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcRegisters/McIoCkeCtl.h @@ -0,0 +1,2594 @@ +/** @file + This file was automatically generated. Modify at your own risk. + +@copyright + Copyright (c) 2010 - 2012 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +**/ +#ifndef __McIoCkeCtl_h__ +#define __McIoCkeCtl_h__ + +#pragma pack(push, 1) +#include "MrcTypes.h" + +typedef union { + struct { + U32 Scomp : 6; // Bits 5:0 + U32 TcoComp : 6; // Bits 11:6 + U32 RcompDrvUp : 6; // Bits 17:12 + U32 RcompDrvDown : 6; // Bits 23:18 + U32 LsComp : 3; // Bits 26:24 + U32 Spare : 5; // Bits 31:27 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRCKECTL_CR_DDRCRCTLCOMP_STRUCT; + +typedef union { + struct { + U32 ScompOffset : 5; // Bits 4:0 + U32 TcoCompOffset : 4; // Bits 8:5 + U32 RcompDrvUpOffset : 4; // Bits 12:9 + U32 RcompDrvDownOffset : 4; // Bits 16:13 + U32 Spare : 15; // Bits 31:17 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRCKECTL_CR_DDRCRCTLCOMPOFFSET_STRUCT; + +typedef union { + struct { + U32 CtlPiCode0 : 7; // Bits 6:0 + U32 CtlPiCode1 : 7; // Bits 13:7 + U32 CtlPiCode2 : 7; // Bits 20:14 + U32 CtlPiCode3 : 7; // Bits 27:21 + U32 CtlXoverEnable : 1; // Bits 28:28 + U32 Spare : 3; // Bits 31:29 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRCKECTL_CR_DDRCRCTLPICODING_STRUCT; + +typedef union { + struct { + U32 RefPi : 4; // Bits 3:0 + U32 DllMask : 2; // Bits 5:4 + U32 DllRsvd1 : 1; // Bits 6:6 + U32 TxOn : 1; // Bits 7:7 + U32 IntClkOn : 1; // Bits 8:8 + U32 RepClkOn : 1; // Bits 9:9 + U32 IOLBCtl : 2; // Bits 11:10 + U32 OdtMode : 1; // Bits 12:12 + U32 CmdTxEq : 2; // Bits 14:13 + U32 EarlyWeakDrive : 2; // Bits 16:15 + U32 CtlTxEq : 2; // Bits 18:17 + U32 CtlSRDrv : 2; // Bits 20:19 + U32 RxVref : 6; // Bits 26:21 + U32 VccddqHi : 1; // Bits 27:27 + U32 DllWeakLock : 1; // Bits 28:28 + U32 LPDDR_Mode : 1; // Bits 29:29 + U32 LaDrvEnOvrd : 1; // Bits 30:30 + U32 LPDdrCAA_Dis : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRCKECTL_CR_DDRCRCTLCONTROLS_STRUCT; + +typedef union { + struct { + U32 RankEn : 4; // Bits 3:0 + U32 OdtDisable : 2; // Bits 5:4 + U32 Spare : 26; // Bits 31:6 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRCKECTL_CR_DDRCRCTLRANKSUSED_STRUCT; + +typedef union { + struct { + U32 RunTest : 1; // Bits 0:0 + U32 Load : 1; // Bits 1:1 + U32 ModeHVM : 1; // Bits 2:2 + U32 ModeDV : 1; // Bits 3:3 + U32 ModeADC : 1; // Bits 4:4 + U32 LoadCount : 10; // Bits 14:5 + U32 CountStatus : 10; // Bits 24:15 + U32 Spare : 7; // Bits 31:25 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRCKECTL_CR_DLLPITESTANDADC_STRUCT; + +typedef union { + struct { + U32 Scomp : 6; // Bits 5:0 + U32 TcoComp : 6; // Bits 11:6 + U32 RcompDrvUp : 6; // Bits 17:12 + U32 RcompDrvDown : 6; // Bits 23:18 + U32 LsComp : 3; // Bits 26:24 + U32 Spare : 5; // Bits 31:27 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRCKECTLCH0_CR_DDRCRCTLCOMP_STRUCT; + +typedef union { + struct { + U32 ScompOffset : 5; // Bits 4:0 + U32 TcoCompOffset : 4; // Bits 8:5 + U32 RcompDrvUpOffset : 4; // Bits 12:9 + U32 RcompDrvDownOffset : 4; // Bits 16:13 + U32 Spare : 15; // Bits 31:17 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRCKECTLCH0_CR_DDRCRCTLCOMPOFFSET_STRUCT; + +typedef union { + struct { + U32 CtlPiCode0 : 7; // Bits 6:0 + U32 CtlPiCode1 : 7; // Bits 13:7 + U32 CtlPiCode2 : 7; // Bits 20:14 + U32 CtlPiCode3 : 7; // Bits 27:21 + U32 CtlXoverEnable : 1; // Bits 28:28 + U32 Spare : 3; // Bits 31:29 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRCKECTLCH0_CR_DDRCRCTLPICODING_STRUCT; + +typedef union { + struct { + U32 RefPi : 4; // Bits 3:0 + U32 DllMask : 2; // Bits 5:4 + U32 DllRsvd1 : 1; // Bits 6:6 + U32 TxOn : 1; // Bits 7:7 + U32 IntClkOn : 1; // Bits 8:8 + U32 RepClkOn : 1; // Bits 9:9 + U32 IOLBCtl : 2; // Bits 11:10 + U32 OdtMode : 1; // Bits 12:12 + U32 CmdTxEq : 2; // Bits 14:13 + U32 EarlyWeakDrive : 2; // Bits 16:15 + U32 CtlTxEq : 2; // Bits 18:17 + U32 CtlSRDrv : 2; // Bits 20:19 + U32 RxVref : 6; // Bits 26:21 + U32 VccddqHi : 1; // Bits 27:27 + U32 DllWeakLock : 1; // Bits 28:28 + U32 LPDDR_Mode : 1; // Bits 29:29 + U32 LaDrvEnOvrd : 1; // Bits 30:30 + U32 LPDdrCAA_Dis : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_STRUCT; + +typedef union { + struct { + U32 RankEn : 4; // Bits 3:0 + U32 OdtDisable : 2; // Bits 5:4 + U32 Spare : 26; // Bits 31:6 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRCKECTLCH0_CR_DDRCRCTLRANKSUSED_STRUCT; + +typedef union { + struct { + U32 RunTest : 1; // Bits 0:0 + U32 Load : 1; // Bits 1:1 + U32 ModeHVM : 1; // Bits 2:2 + U32 ModeDV : 1; // Bits 3:3 + U32 ModeADC : 1; // Bits 4:4 + U32 LoadCount : 10; // Bits 14:5 + U32 CountStatus : 10; // Bits 24:15 + U32 Spare : 7; // Bits 31:25 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRCKECTLCH0_CR_DLLPITESTANDADC_STRUCT; + +typedef union { + struct { + U32 Scomp : 6; // Bits 5:0 + U32 TcoComp : 6; // Bits 11:6 + U32 RcompDrvUp : 6; // Bits 17:12 + U32 RcompDrvDown : 6; // Bits 23:18 + U32 LsComp : 3; // Bits 26:24 + U32 Spare : 5; // Bits 31:27 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRCKECTLCH1_CR_DDRCRCTLCOMP_STRUCT; + +typedef union { + struct { + U32 ScompOffset : 5; // Bits 4:0 + U32 TcoCompOffset : 4; // Bits 8:5 + U32 RcompDrvUpOffset : 4; // Bits 12:9 + U32 RcompDrvDownOffset : 4; // Bits 16:13 + U32 Spare : 15; // Bits 31:17 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRCKECTLCH1_CR_DDRCRCTLCOMPOFFSET_STRUCT; + +typedef union { + struct { + U32 CtlPiCode0 : 7; // Bits 6:0 + U32 CtlPiCode1 : 7; // Bits 13:7 + U32 CtlPiCode2 : 7; // Bits 20:14 + U32 CtlPiCode3 : 7; // Bits 27:21 + U32 CtlXoverEnable : 1; // Bits 28:28 + U32 Spare : 3; // Bits 31:29 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRCKECTLCH1_CR_DDRCRCTLPICODING_STRUCT; + +typedef union { + struct { + U32 RefPi : 4; // Bits 3:0 + U32 DllMask : 2; // Bits 5:4 + U32 DllRsvd1 : 1; // Bits 6:6 + U32 TxOn : 1; // Bits 7:7 + U32 IntClkOn : 1; // Bits 8:8 + U32 RepClkOn : 1; // Bits 9:9 + U32 IOLBCtl : 2; // Bits 11:10 + U32 OdtMode : 1; // Bits 12:12 + U32 CmdTxEq : 2; // Bits 14:13 + U32 EarlyWeakDrive : 2; // Bits 16:15 + U32 CtlTxEq : 2; // Bits 18:17 + U32 CtlSRDrv : 2; // Bits 20:19 + U32 RxVref : 6; // Bits 26:21 + U32 VccddqHi : 1; // Bits 27:27 + U32 DllWeakLock : 1; // Bits 28:28 + U32 LPDDR_Mode : 1; // Bits 29:29 + U32 LaDrvEnOvrd : 1; // Bits 30:30 + U32 LPDdrCAA_Dis : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_STRUCT; + +typedef union { + struct { + U32 RankEn : 4; // Bits 3:0 + U32 OdtDisable : 2; // Bits 5:4 + U32 Spare : 26; // Bits 31:6 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRCKECTLCH1_CR_DDRCRCTLRANKSUSED_STRUCT; + +typedef union { + struct { + U32 RunTest : 1; // Bits 0:0 + U32 Load : 1; // Bits 1:1 + U32 ModeHVM : 1; // Bits 2:2 + U32 ModeDV : 1; // Bits 3:3 + U32 ModeADC : 1; // Bits 4:4 + U32 LoadCount : 10; // Bits 14:5 + U32 CountStatus : 10; // Bits 24:15 + U32 Spare : 7; // Bits 31:25 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRCKECTLCH1_CR_DLLPITESTANDADC_STRUCT; + +typedef union { + struct { + U32 Scomp : 6; // Bits 5:0 + U32 TcoComp : 6; // Bits 11:6 + U32 RcompDrvUp : 6; // Bits 17:12 + U32 RcompDrvDown : 6; // Bits 23:18 + U32 LsComp : 3; // Bits 26:24 + U32 Spare : 5; // Bits 31:27 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRCKECH0_CR_DDRCRCMDCOMP_STRUCT; + +typedef union { + struct { + U32 ScompOffset : 5; // Bits 4:0 + U32 TcoCompOffset : 4; // Bits 8:5 + U32 RcompDrvUpOffset : 4; // Bits 12:9 + U32 RcompDrvDownOffset : 4; // Bits 16:13 + U32 Spare : 15; // Bits 31:17 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRCKECH0_CR_DDRCRCMDCOMPOFFSET_STRUCT; + +typedef union { + struct { + U32 CmdPi0Code : 7; // Bits 6:0 + U32 CmdPi1Code : 7; // Bits 13:7 + U32 Spare : 18; // Bits 31:14 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRCKECH0_CR_DDRCRCMDPICODING_STRUCT; + +typedef union { + struct { + U32 Scomp : 6; // Bits 5:0 + U32 TcoComp : 6; // Bits 11:6 + U32 RcompDrvUp : 6; // Bits 17:12 + U32 RcompDrvDown : 6; // Bits 23:18 + U32 LsComp : 3; // Bits 26:24 + U32 Spare : 5; // Bits 31:27 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRCKECH0_CR_DDRCRCTLCOMP_STRUCT; + +typedef union { + struct { + U32 ScompOffset : 5; // Bits 4:0 + U32 TcoCompOffset : 4; // Bits 8:5 + U32 RcompDrvUpOffset : 4; // Bits 12:9 + U32 RcompDrvDownOffset : 4; // Bits 16:13 + U32 Spare : 15; // Bits 31:17 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRCKECH0_CR_DDRCRCTLCOMPOFFSET_STRUCT; + +typedef union { + struct { + U32 CtlPiCode0 : 7; // Bits 6:0 + U32 CtlPiCode1 : 7; // Bits 13:7 + U32 CtlPiCode2 : 7; // Bits 20:14 + U32 CtlPiCode3 : 7; // Bits 27:21 + U32 CtlXoverEnable : 1; // Bits 28:28 + U32 Spare : 3; // Bits 31:29 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRCKECH0_CR_DDRCRCTLPICODING_STRUCT; + +typedef union { + struct { + U32 RefPi : 4; // Bits 3:0 + U32 DllMask : 2; // Bits 5:4 + U32 DllRsvd1 : 1; // Bits 6:6 + U32 TxOn : 1; // Bits 7:7 + U32 IntClkOn : 1; // Bits 8:8 + U32 RepClkOn : 1; // Bits 9:9 + U32 IOLBCtl : 2; // Bits 11:10 + U32 OdtMode : 1; // Bits 12:12 + U32 CmdTxEq : 2; // Bits 14:13 + U32 EarlyWeakDrive : 2; // Bits 16:15 + U32 CtlTxEq : 2; // Bits 18:17 + U32 CtlSRDrv : 2; // Bits 20:19 + U32 RxVref : 6; // Bits 26:21 + U32 VccddqHi : 1; // Bits 27:27 + U32 DllWeakLock : 1; // Bits 28:28 + U32 LPDDR_Mode : 1; // Bits 29:29 + U32 LaDrvEnOvrd : 1; // Bits 30:30 + U32 LPDdrCAA_Dis : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRCKECH0_CR_DDRCRCTLCONTROLS_STRUCT; + +typedef union { + struct { + U32 RankEn : 4; // Bits 3:0 + U32 OdtDisable : 2; // Bits 5:4 + U32 Spare : 26; // Bits 31:6 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRCKECH0_CR_DDRCRCTLRANKSUSED_STRUCT; + +typedef union { + struct { + U32 RunTest : 1; // Bits 0:0 + U32 Load : 1; // Bits 1:1 + U32 ModeHVM : 1; // Bits 2:2 + U32 ModeDV : 1; // Bits 3:3 + U32 ModeADC : 1; // Bits 4:4 + U32 LoadCount : 10; // Bits 14:5 + U32 CountStatus : 10; // Bits 24:15 + U32 Spare : 7; // Bits 31:25 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRCKECH0_CR_DLLPITESTANDADC_STRUCT; + +typedef union { + struct { + U32 Scomp : 6; // Bits 5:0 + U32 TcoComp : 6; // Bits 11:6 + U32 RcompDrvUp : 6; // Bits 17:12 + U32 RcompDrvDown : 6; // Bits 23:18 + U32 LsComp : 3; // Bits 26:24 + U32 Spare : 5; // Bits 31:27 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRCKECH1_CR_DDRCRCMDCOMP_STRUCT; + +typedef union { + struct { + U32 ScompOffset : 5; // Bits 4:0 + U32 TcoCompOffset : 4; // Bits 8:5 + U32 RcompDrvUpOffset : 4; // Bits 12:9 + U32 RcompDrvDownOffset : 4; // Bits 16:13 + U32 Spare : 15; // Bits 31:17 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRCKECH1_CR_DDRCRCMDCOMPOFFSET_STRUCT; + +typedef union { + struct { + U32 CmdPi0Code : 7; // Bits 6:0 + U32 CmdPi1Code : 7; // Bits 13:7 + U32 Spare : 18; // Bits 31:14 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRCKECH1_CR_DDRCRCMDPICODING_STRUCT; + +typedef union { + struct { + U32 Scomp : 6; // Bits 5:0 + U32 TcoComp : 6; // Bits 11:6 + U32 RcompDrvUp : 6; // Bits 17:12 + U32 RcompDrvDown : 6; // Bits 23:18 + U32 LsComp : 3; // Bits 26:24 + U32 Spare : 5; // Bits 31:27 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRCKECH1_CR_DDRCRCTLCOMP_STRUCT; + +typedef union { + struct { + U32 ScompOffset : 5; // Bits 4:0 + U32 TcoCompOffset : 4; // Bits 8:5 + U32 RcompDrvUpOffset : 4; // Bits 12:9 + U32 RcompDrvDownOffset : 4; // Bits 16:13 + U32 Spare : 15; // Bits 31:17 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRCKECH1_CR_DDRCRCTLCOMPOFFSET_STRUCT; + +typedef union { + struct { + U32 CtlPiCode0 : 7; // Bits 6:0 + U32 CtlPiCode1 : 7; // Bits 13:7 + U32 CtlPiCode2 : 7; // Bits 20:14 + U32 CtlPiCode3 : 7; // Bits 27:21 + U32 CtlXoverEnable : 1; // Bits 28:28 + U32 Spare : 3; // Bits 31:29 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRCKECH1_CR_DDRCRCTLPICODING_STRUCT; + +typedef union { + struct { + U32 RefPi : 4; // Bits 3:0 + U32 DllMask : 2; // Bits 5:4 + U32 DllRsvd1 : 1; // Bits 6:6 + U32 TxOn : 1; // Bits 7:7 + U32 IntClkOn : 1; // Bits 8:8 + U32 RepClkOn : 1; // Bits 9:9 + U32 IOLBCtl : 2; // Bits 11:10 + U32 OdtMode : 1; // Bits 12:12 + U32 CmdTxEq : 2; // Bits 14:13 + U32 EarlyWeakDrive : 2; // Bits 16:15 + U32 CtlTxEq : 2; // Bits 18:17 + U32 CtlSRDrv : 2; // Bits 20:19 + U32 RxVref : 6; // Bits 26:21 + U32 VccddqHi : 1; // Bits 27:27 + U32 DllWeakLock : 1; // Bits 28:28 + U32 LPDDR_Mode : 1; // Bits 29:29 + U32 LaDrvEnOvrd : 1; // Bits 30:30 + U32 LPDdrCAA_Dis : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRCKECH1_CR_DDRCRCTLCONTROLS_STRUCT; + +typedef union { + struct { + U32 RankEn : 4; // Bits 3:0 + U32 OdtDisable : 2; // Bits 5:4 + U32 Spare : 26; // Bits 31:6 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRCKECH1_CR_DDRCRCTLRANKSUSED_STRUCT; + +typedef union { + struct { + U32 RunTest : 1; // Bits 0:0 + U32 Load : 1; // Bits 1:1 + U32 ModeHVM : 1; // Bits 2:2 + U32 ModeDV : 1; // Bits 3:3 + U32 ModeADC : 1; // Bits 4:4 + U32 LoadCount : 10; // Bits 14:5 + U32 CountStatus : 10; // Bits 24:15 + U32 Spare : 7; // Bits 31:25 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRCKECH1_CR_DLLPITESTANDADC_STRUCT; + +typedef union { + struct { + U32 Scomp : 6; // Bits 5:0 + U32 TcoComp : 6; // Bits 11:6 + U32 RcompDrvUp : 6; // Bits 17:12 + U32 RcompDrvDown : 6; // Bits 23:18 + U32 LsComp : 3; // Bits 26:24 + U32 Spare : 5; // Bits 31:27 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRCTLCH0_CR_DDRCRCTLCOMP_STRUCT; + +typedef union { + struct { + U32 ScompOffset : 5; // Bits 4:0 + U32 TcoCompOffset : 4; // Bits 8:5 + U32 RcompDrvUpOffset : 4; // Bits 12:9 + U32 RcompDrvDownOffset : 4; // Bits 16:13 + U32 Spare : 15; // Bits 31:17 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRCTLCH0_CR_DDRCRCTLCOMPOFFSET_STRUCT; + +typedef union { + struct { + U32 CtlPiCode0 : 7; // Bits 6:0 + U32 CtlPiCode1 : 7; // Bits 13:7 + U32 CtlPiCode2 : 7; // Bits 20:14 + U32 CtlPiCode3 : 7; // Bits 27:21 + U32 CtlXoverEnable : 1; // Bits 28:28 + U32 Spare : 3; // Bits 31:29 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRCTLCH0_CR_DDRCRCTLPICODING_STRUCT; + +typedef union { + struct { + U32 RefPi : 4; // Bits 3:0 + U32 DllMask : 2; // Bits 5:4 + U32 DllRsvd1 : 1; // Bits 6:6 + U32 TxOn : 1; // Bits 7:7 + U32 IntClkOn : 1; // Bits 8:8 + U32 RepClkOn : 1; // Bits 9:9 + U32 IOLBCtl : 2; // Bits 11:10 + U32 OdtMode : 1; // Bits 12:12 + U32 CmdTxEq : 2; // Bits 14:13 + U32 EarlyWeakDrive : 2; // Bits 16:15 + U32 CtlTxEq : 2; // Bits 18:17 + U32 CtlSRDrv : 2; // Bits 20:19 + U32 RxVref : 6; // Bits 26:21 + U32 VccddqHi : 1; // Bits 27:27 + U32 DllWeakLock : 1; // Bits 28:28 + U32 LPDDR_Mode : 1; // Bits 29:29 + U32 LaDrvEnOvrd : 1; // Bits 30:30 + U32 LPDdrCAA_Dis : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRCTLCH0_CR_DDRCRCTLCONTROLS_STRUCT; + +typedef union { + struct { + U32 RankEn : 4; // Bits 3:0 + U32 OdtDisable : 2; // Bits 5:4 + U32 Spare : 26; // Bits 31:6 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRCTLCH0_CR_DDRCRCTLRANKSUSED_STRUCT; + +typedef union { + struct { + U32 RunTest : 1; // Bits 0:0 + U32 Load : 1; // Bits 1:1 + U32 ModeHVM : 1; // Bits 2:2 + U32 ModeDV : 1; // Bits 3:3 + U32 ModeADC : 1; // Bits 4:4 + U32 LoadCount : 10; // Bits 14:5 + U32 CountStatus : 10; // Bits 24:15 + U32 Spare : 7; // Bits 31:25 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRCTLCH0_CR_DLLPITESTANDADC_STRUCT; + +typedef union { + struct { + U32 Scomp : 6; // Bits 5:0 + U32 TcoComp : 6; // Bits 11:6 + U32 RcompDrvUp : 6; // Bits 17:12 + U32 RcompDrvDown : 6; // Bits 23:18 + U32 LsComp : 3; // Bits 26:24 + U32 Spare : 5; // Bits 31:27 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRCTLCH1_CR_DDRCRCTLCOMP_STRUCT; + +typedef union { + struct { + U32 ScompOffset : 5; // Bits 4:0 + U32 TcoCompOffset : 4; // Bits 8:5 + U32 RcompDrvUpOffset : 4; // Bits 12:9 + U32 RcompDrvDownOffset : 4; // Bits 16:13 + U32 Spare : 15; // Bits 31:17 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRCTLCH1_CR_DDRCRCTLCOMPOFFSET_STRUCT; + +typedef union { + struct { + U32 CtlPiCode0 : 7; // Bits 6:0 + U32 CtlPiCode1 : 7; // Bits 13:7 + U32 CtlPiCode2 : 7; // Bits 20:14 + U32 CtlPiCode3 : 7; // Bits 27:21 + U32 CtlXoverEnable : 1; // Bits 28:28 + U32 Spare : 3; // Bits 31:29 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRCTLCH1_CR_DDRCRCTLPICODING_STRUCT; + +typedef union { + struct { + U32 RefPi : 4; // Bits 3:0 + U32 DllMask : 2; // Bits 5:4 + U32 DllRsvd1 : 1; // Bits 6:6 + U32 TxOn : 1; // Bits 7:7 + U32 IntClkOn : 1; // Bits 8:8 + U32 RepClkOn : 1; // Bits 9:9 + U32 IOLBCtl : 2; // Bits 11:10 + U32 OdtMode : 1; // Bits 12:12 + U32 CmdTxEq : 2; // Bits 14:13 + U32 EarlyWeakDrive : 2; // Bits 16:15 + U32 CtlTxEq : 2; // Bits 18:17 + U32 CtlSRDrv : 2; // Bits 20:19 + U32 RxVref : 6; // Bits 26:21 + U32 VccddqHi : 1; // Bits 27:27 + U32 DllWeakLock : 1; // Bits 28:28 + U32 LPDDR_Mode : 1; // Bits 29:29 + U32 LaDrvEnOvrd : 1; // Bits 30:30 + U32 LPDdrCAA_Dis : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRCTLCH1_CR_DDRCRCTLCONTROLS_STRUCT; + +typedef union { + struct { + U32 RankEn : 4; // Bits 3:0 + U32 OdtDisable : 2; // Bits 5:4 + U32 Spare : 26; // Bits 31:6 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRCTLCH1_CR_DDRCRCTLRANKSUSED_STRUCT; + +typedef union { + struct { + U32 RunTest : 1; // Bits 0:0 + U32 Load : 1; // Bits 1:1 + U32 ModeHVM : 1; // Bits 2:2 + U32 ModeDV : 1; // Bits 3:3 + U32 ModeADC : 1; // Bits 4:4 + U32 LoadCount : 10; // Bits 14:5 + U32 CountStatus : 10; // Bits 24:15 + U32 Spare : 7; // Bits 31:25 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRCTLCH1_CR_DLLPITESTANDADC_STRUCT; + +#define DDRCKECTL_CR_DDRCRCTLCOMP_REG (0x00003810) + #define DDRCKECTL_CR_DDRCRCTLCOMP_Scomp_OFF ( 0) + #define DDRCKECTL_CR_DDRCRCTLCOMP_Scomp_WID ( 6) + #define DDRCKECTL_CR_DDRCRCTLCOMP_Scomp_MSK (0x0000003F) + #define DDRCKECTL_CR_DDRCRCTLCOMP_Scomp_MAX (0x0000003F) + #define DDRCKECTL_CR_DDRCRCTLCOMP_Scomp_DEF (0x00000000) + #define DDRCKECTL_CR_DDRCRCTLCOMP_TcoComp_OFF ( 6) + #define DDRCKECTL_CR_DDRCRCTLCOMP_TcoComp_WID ( 6) + #define DDRCKECTL_CR_DDRCRCTLCOMP_TcoComp_MSK (0x00000FC0) + #define DDRCKECTL_CR_DDRCRCTLCOMP_TcoComp_MAX (0x0000003F) + #define DDRCKECTL_CR_DDRCRCTLCOMP_TcoComp_DEF (0x00000000) + #define DDRCKECTL_CR_DDRCRCTLCOMP_RcompDrvUp_OFF (12) + #define DDRCKECTL_CR_DDRCRCTLCOMP_RcompDrvUp_WID ( 6) + #define DDRCKECTL_CR_DDRCRCTLCOMP_RcompDrvUp_MSK (0x0003F000) + #define DDRCKECTL_CR_DDRCRCTLCOMP_RcompDrvUp_MAX (0x0000003F) + #define DDRCKECTL_CR_DDRCRCTLCOMP_RcompDrvUp_DEF (0x00000000) + #define DDRCKECTL_CR_DDRCRCTLCOMP_RcompDrvDown_OFF (18) + #define DDRCKECTL_CR_DDRCRCTLCOMP_RcompDrvDown_WID ( 6) + #define DDRCKECTL_CR_DDRCRCTLCOMP_RcompDrvDown_MSK (0x00FC0000) + #define DDRCKECTL_CR_DDRCRCTLCOMP_RcompDrvDown_MAX (0x0000003F) + #define DDRCKECTL_CR_DDRCRCTLCOMP_RcompDrvDown_DEF (0x00000000) + #define DDRCKECTL_CR_DDRCRCTLCOMP_LsComp_OFF (24) + #define DDRCKECTL_CR_DDRCRCTLCOMP_LsComp_WID ( 3) + #define DDRCKECTL_CR_DDRCRCTLCOMP_LsComp_MSK (0x07000000) + #define DDRCKECTL_CR_DDRCRCTLCOMP_LsComp_MAX (0x00000007) + #define DDRCKECTL_CR_DDRCRCTLCOMP_LsComp_DEF (0x00000000) + #define DDRCKECTL_CR_DDRCRCTLCOMP_Spare_OFF (27) + #define DDRCKECTL_CR_DDRCRCTLCOMP_Spare_WID ( 5) + #define DDRCKECTL_CR_DDRCRCTLCOMP_Spare_MSK (0xF8000000) + #define DDRCKECTL_CR_DDRCRCTLCOMP_Spare_MAX (0x0000001F) + #define DDRCKECTL_CR_DDRCRCTLCOMP_Spare_DEF (0x00000000) + +#define DDRCKECTL_CR_DDRCRCTLCOMPOFFSET_REG (0x00003814) + #define DDRCKECTL_CR_DDRCRCTLCOMPOFFSET_ScompOffset_OFF ( 0) + #define DDRCKECTL_CR_DDRCRCTLCOMPOFFSET_ScompOffset_WID ( 5) + #define DDRCKECTL_CR_DDRCRCTLCOMPOFFSET_ScompOffset_MSK (0x0000001F) + #define DDRCKECTL_CR_DDRCRCTLCOMPOFFSET_ScompOffset_MAX (0x0000001F) + #define DDRCKECTL_CR_DDRCRCTLCOMPOFFSET_ScompOffset_DEF (0x00000000) + #define DDRCKECTL_CR_DDRCRCTLCOMPOFFSET_TcoCompOffset_OFF ( 5) + #define DDRCKECTL_CR_DDRCRCTLCOMPOFFSET_TcoCompOffset_WID ( 4) + #define DDRCKECTL_CR_DDRCRCTLCOMPOFFSET_TcoCompOffset_MSK (0x000001E0) + #define DDRCKECTL_CR_DDRCRCTLCOMPOFFSET_TcoCompOffset_MAX (0x0000000F) + #define DDRCKECTL_CR_DDRCRCTLCOMPOFFSET_TcoCompOffset_DEF (0x00000000) + #define DDRCKECTL_CR_DDRCRCTLCOMPOFFSET_RcompDrvUpOffset_OFF ( 9) + #define DDRCKECTL_CR_DDRCRCTLCOMPOFFSET_RcompDrvUpOffset_WID ( 4) + #define DDRCKECTL_CR_DDRCRCTLCOMPOFFSET_RcompDrvUpOffset_MSK (0x00001E00) + #define DDRCKECTL_CR_DDRCRCTLCOMPOFFSET_RcompDrvUpOffset_MAX (0x0000000F) + #define DDRCKECTL_CR_DDRCRCTLCOMPOFFSET_RcompDrvUpOffset_DEF (0x00000000) + #define DDRCKECTL_CR_DDRCRCTLCOMPOFFSET_RcompDrvDownOffset_OFF (13) + #define DDRCKECTL_CR_DDRCRCTLCOMPOFFSET_RcompDrvDownOffset_WID ( 4) + #define DDRCKECTL_CR_DDRCRCTLCOMPOFFSET_RcompDrvDownOffset_MSK (0x0001E000) + #define DDRCKECTL_CR_DDRCRCTLCOMPOFFSET_RcompDrvDownOffset_MAX (0x0000000F) + #define DDRCKECTL_CR_DDRCRCTLCOMPOFFSET_RcompDrvDownOffset_DEF (0x00000000) + #define DDRCKECTL_CR_DDRCRCTLCOMPOFFSET_Spare_OFF (17) + #define DDRCKECTL_CR_DDRCRCTLCOMPOFFSET_Spare_WID (15) + #define DDRCKECTL_CR_DDRCRCTLCOMPOFFSET_Spare_MSK (0xFFFE0000) + #define DDRCKECTL_CR_DDRCRCTLCOMPOFFSET_Spare_MAX (0x00007FFF) + #define DDRCKECTL_CR_DDRCRCTLCOMPOFFSET_Spare_DEF (0x00000000) + +#define DDRCKECTL_CR_DDRCRCTLPICODING_REG (0x00003818) + #define DDRCKECTL_CR_DDRCRCTLPICODING_CtlPiCode0_OFF ( 0) + #define DDRCKECTL_CR_DDRCRCTLPICODING_CtlPiCode0_WID ( 7) + #define DDRCKECTL_CR_DDRCRCTLPICODING_CtlPiCode0_MSK (0x0000007F) + #define DDRCKECTL_CR_DDRCRCTLPICODING_CtlPiCode0_MAX (0x0000007F) + #define DDRCKECTL_CR_DDRCRCTLPICODING_CtlPiCode0_DEF (0x00000000) + #define DDRCKECTL_CR_DDRCRCTLPICODING_CtlPiCode1_OFF ( 7) + #define DDRCKECTL_CR_DDRCRCTLPICODING_CtlPiCode1_WID ( 7) + #define DDRCKECTL_CR_DDRCRCTLPICODING_CtlPiCode1_MSK (0x00003F80) + #define DDRCKECTL_CR_DDRCRCTLPICODING_CtlPiCode1_MAX (0x0000007F) + #define DDRCKECTL_CR_DDRCRCTLPICODING_CtlPiCode1_DEF (0x00000000) + #define DDRCKECTL_CR_DDRCRCTLPICODING_CtlPiCode2_OFF (14) + #define DDRCKECTL_CR_DDRCRCTLPICODING_CtlPiCode2_WID ( 7) + #define DDRCKECTL_CR_DDRCRCTLPICODING_CtlPiCode2_MSK (0x001FC000) + #define DDRCKECTL_CR_DDRCRCTLPICODING_CtlPiCode2_MAX (0x0000007F) + #define DDRCKECTL_CR_DDRCRCTLPICODING_CtlPiCode2_DEF (0x00000000) + #define DDRCKECTL_CR_DDRCRCTLPICODING_CtlPiCode3_OFF (21) + #define DDRCKECTL_CR_DDRCRCTLPICODING_CtlPiCode3_WID ( 7) + #define DDRCKECTL_CR_DDRCRCTLPICODING_CtlPiCode3_MSK (0x0FE00000) + #define DDRCKECTL_CR_DDRCRCTLPICODING_CtlPiCode3_MAX (0x0000007F) + #define DDRCKECTL_CR_DDRCRCTLPICODING_CtlPiCode3_DEF (0x00000000) + #define DDRCKECTL_CR_DDRCRCTLPICODING_CtlXoverEnable_OFF (28) + #define DDRCKECTL_CR_DDRCRCTLPICODING_CtlXoverEnable_WID ( 1) + #define DDRCKECTL_CR_DDRCRCTLPICODING_CtlXoverEnable_MSK (0x10000000) + #define DDRCKECTL_CR_DDRCRCTLPICODING_CtlXoverEnable_MAX (0x00000001) + #define DDRCKECTL_CR_DDRCRCTLPICODING_CtlXoverEnable_DEF (0x00000000) + #define DDRCKECTL_CR_DDRCRCTLPICODING_Spare_OFF (29) + #define DDRCKECTL_CR_DDRCRCTLPICODING_Spare_WID ( 3) + #define DDRCKECTL_CR_DDRCRCTLPICODING_Spare_MSK (0xE0000000) + #define DDRCKECTL_CR_DDRCRCTLPICODING_Spare_MAX (0x00000007) + #define DDRCKECTL_CR_DDRCRCTLPICODING_Spare_DEF (0x00000000) + +#define DDRCKECTL_CR_DDRCRCTLCONTROLS_REG (0x0000381C) + #define DDRCKECTL_CR_DDRCRCTLCONTROLS_RefPi_OFF ( 0) + #define DDRCKECTL_CR_DDRCRCTLCONTROLS_RefPi_WID ( 4) + #define DDRCKECTL_CR_DDRCRCTLCONTROLS_RefPi_MSK (0x0000000F) + #define DDRCKECTL_CR_DDRCRCTLCONTROLS_RefPi_MAX (0x0000000F) + #define DDRCKECTL_CR_DDRCRCTLCONTROLS_RefPi_DEF (0x00000000) + #define DDRCKECTL_CR_DDRCRCTLCONTROLS_DllMask_OFF ( 4) + #define DDRCKECTL_CR_DDRCRCTLCONTROLS_DllMask_WID ( 2) + #define DDRCKECTL_CR_DDRCRCTLCONTROLS_DllMask_MSK (0x00000030) + #define DDRCKECTL_CR_DDRCRCTLCONTROLS_DllMask_MAX (0x00000003) + #define DDRCKECTL_CR_DDRCRCTLCONTROLS_DllMask_DEF (0x00000000) + #define DDRCKECTL_CR_DDRCRCTLCONTROLS_DllRsvd1_OFF ( 6) + #define DDRCKECTL_CR_DDRCRCTLCONTROLS_DllRsvd1_WID ( 1) + #define DDRCKECTL_CR_DDRCRCTLCONTROLS_DllRsvd1_MSK (0x00000040) + #define DDRCKECTL_CR_DDRCRCTLCONTROLS_DllRsvd1_MAX (0x00000001) + #define DDRCKECTL_CR_DDRCRCTLCONTROLS_DllRsvd1_DEF (0x00000000) + #define DDRCKECTL_CR_DDRCRCTLCONTROLS_TxOn_OFF ( 7) + #define DDRCKECTL_CR_DDRCRCTLCONTROLS_TxOn_WID ( 1) + #define DDRCKECTL_CR_DDRCRCTLCONTROLS_TxOn_MSK (0x00000080) + #define DDRCKECTL_CR_DDRCRCTLCONTROLS_TxOn_MAX (0x00000001) + #define DDRCKECTL_CR_DDRCRCTLCONTROLS_TxOn_DEF (0x00000000) + #define DDRCKECTL_CR_DDRCRCTLCONTROLS_IntClkOn_OFF ( 8) + #define DDRCKECTL_CR_DDRCRCTLCONTROLS_IntClkOn_WID ( 1) + #define DDRCKECTL_CR_DDRCRCTLCONTROLS_IntClkOn_MSK (0x00000100) + #define DDRCKECTL_CR_DDRCRCTLCONTROLS_IntClkOn_MAX (0x00000001) + #define DDRCKECTL_CR_DDRCRCTLCONTROLS_IntClkOn_DEF (0x00000000) + #define DDRCKECTL_CR_DDRCRCTLCONTROLS_RepClkOn_OFF ( 9) + #define DDRCKECTL_CR_DDRCRCTLCONTROLS_RepClkOn_WID ( 1) + #define DDRCKECTL_CR_DDRCRCTLCONTROLS_RepClkOn_MSK (0x00000200) + #define DDRCKECTL_CR_DDRCRCTLCONTROLS_RepClkOn_MAX (0x00000001) + #define DDRCKECTL_CR_DDRCRCTLCONTROLS_RepClkOn_DEF (0x00000000) + #define DDRCKECTL_CR_DDRCRCTLCONTROLS_IOLBCtl_OFF (10) + #define DDRCKECTL_CR_DDRCRCTLCONTROLS_IOLBCtl_WID ( 2) + #define DDRCKECTL_CR_DDRCRCTLCONTROLS_IOLBCtl_MSK (0x00000C00) + #define DDRCKECTL_CR_DDRCRCTLCONTROLS_IOLBCtl_MAX (0x00000003) + #define DDRCKECTL_CR_DDRCRCTLCONTROLS_IOLBCtl_DEF (0x00000000) + #define DDRCKECTL_CR_DDRCRCTLCONTROLS_OdtMode_OFF (12) + #define DDRCKECTL_CR_DDRCRCTLCONTROLS_OdtMode_WID ( 1) + #define DDRCKECTL_CR_DDRCRCTLCONTROLS_OdtMode_MSK (0x00001000) + #define DDRCKECTL_CR_DDRCRCTLCONTROLS_OdtMode_MAX (0x00000001) + #define DDRCKECTL_CR_DDRCRCTLCONTROLS_OdtMode_DEF (0x00000000) + #define DDRCKECTL_CR_DDRCRCTLCONTROLS_CmdTxEq_OFF (13) + #define DDRCKECTL_CR_DDRCRCTLCONTROLS_CmdTxEq_WID ( 2) + #define DDRCKECTL_CR_DDRCRCTLCONTROLS_CmdTxEq_MSK (0x00006000) + #define DDRCKECTL_CR_DDRCRCTLCONTROLS_CmdTxEq_MAX (0x00000003) + #define DDRCKECTL_CR_DDRCRCTLCONTROLS_CmdTxEq_DEF (0x00000000) + #define DDRCKECTL_CR_DDRCRCTLCONTROLS_EarlyWeakDrive_OFF (15) + #define DDRCKECTL_CR_DDRCRCTLCONTROLS_EarlyWeakDrive_WID ( 2) + #define DDRCKECTL_CR_DDRCRCTLCONTROLS_EarlyWeakDrive_MSK (0x00018000) + #define DDRCKECTL_CR_DDRCRCTLCONTROLS_EarlyWeakDrive_MAX (0x00000003) + #define DDRCKECTL_CR_DDRCRCTLCONTROLS_EarlyWeakDrive_DEF (0x00000000) + #define DDRCKECTL_CR_DDRCRCTLCONTROLS_CtlTxEq_OFF (17) + #define DDRCKECTL_CR_DDRCRCTLCONTROLS_CtlTxEq_WID ( 2) + #define DDRCKECTL_CR_DDRCRCTLCONTROLS_CtlTxEq_MSK (0x00060000) + #define DDRCKECTL_CR_DDRCRCTLCONTROLS_CtlTxEq_MAX (0x00000003) + #define DDRCKECTL_CR_DDRCRCTLCONTROLS_CtlTxEq_DEF (0x00000000) + #define DDRCKECTL_CR_DDRCRCTLCONTROLS_CtlSRDrv_OFF (19) + #define DDRCKECTL_CR_DDRCRCTLCONTROLS_CtlSRDrv_WID ( 2) + #define DDRCKECTL_CR_DDRCRCTLCONTROLS_CtlSRDrv_MSK (0x00180000) + #define DDRCKECTL_CR_DDRCRCTLCONTROLS_CtlSRDrv_MAX (0x00000003) + #define DDRCKECTL_CR_DDRCRCTLCONTROLS_CtlSRDrv_DEF (0x00000000) + #define DDRCKECTL_CR_DDRCRCTLCONTROLS_RxVref_OFF (21) + #define DDRCKECTL_CR_DDRCRCTLCONTROLS_RxVref_WID ( 6) + #define DDRCKECTL_CR_DDRCRCTLCONTROLS_RxVref_MSK (0x07E00000) + #define DDRCKECTL_CR_DDRCRCTLCONTROLS_RxVref_MAX (0x0000003F) + #define DDRCKECTL_CR_DDRCRCTLCONTROLS_RxVref_DEF (0x00000000) + #define DDRCKECTL_CR_DDRCRCTLCONTROLS_VccddqHi_OFF (27) + #define DDRCKECTL_CR_DDRCRCTLCONTROLS_VccddqHi_WID ( 1) + #define DDRCKECTL_CR_DDRCRCTLCONTROLS_VccddqHi_MSK (0x08000000) + #define DDRCKECTL_CR_DDRCRCTLCONTROLS_VccddqHi_MAX (0x00000001) + #define DDRCKECTL_CR_DDRCRCTLCONTROLS_VccddqHi_DEF (0x00000000) + #define DDRCKECTL_CR_DDRCRCTLCONTROLS_DllWeakLock_OFF (28) + #define DDRCKECTL_CR_DDRCRCTLCONTROLS_DllWeakLock_WID ( 1) + #define DDRCKECTL_CR_DDRCRCTLCONTROLS_DllWeakLock_MSK (0x10000000) + #define DDRCKECTL_CR_DDRCRCTLCONTROLS_DllWeakLock_MAX (0x00000001) + #define DDRCKECTL_CR_DDRCRCTLCONTROLS_DllWeakLock_DEF (0x00000000) + #define DDRCKECTL_CR_DDRCRCTLCONTROLS_LPDDR_Mode_OFF (29) + #define DDRCKECTL_CR_DDRCRCTLCONTROLS_LPDDR_Mode_WID ( 1) + #define DDRCKECTL_CR_DDRCRCTLCONTROLS_LPDDR_Mode_MSK (0x20000000) + #define DDRCKECTL_CR_DDRCRCTLCONTROLS_LPDDR_Mode_MAX (0x00000001) + #define DDRCKECTL_CR_DDRCRCTLCONTROLS_LPDDR_Mode_DEF (0x00000000) + #define DDRCKECTL_CR_DDRCRCTLCONTROLS_LaDrvEnOvrd_OFF (30) + #define DDRCKECTL_CR_DDRCRCTLCONTROLS_LaDrvEnOvrd_WID ( 1) + #define DDRCKECTL_CR_DDRCRCTLCONTROLS_LaDrvEnOvrd_MSK (0x40000000) + #define DDRCKECTL_CR_DDRCRCTLCONTROLS_LaDrvEnOvrd_MAX (0x00000001) + #define DDRCKECTL_CR_DDRCRCTLCONTROLS_LaDrvEnOvrd_DEF (0x00000000) + #define DDRCKECTL_CR_DDRCRCTLCONTROLS_LPDdrCAA_Dis_OFF (31) + #define DDRCKECTL_CR_DDRCRCTLCONTROLS_LPDdrCAA_Dis_WID ( 1) + #define DDRCKECTL_CR_DDRCRCTLCONTROLS_LPDdrCAA_Dis_MSK (0x80000000) + #define DDRCKECTL_CR_DDRCRCTLCONTROLS_LPDdrCAA_Dis_MAX (0x00000001) + #define DDRCKECTL_CR_DDRCRCTLCONTROLS_LPDdrCAA_Dis_DEF (0x00000000) + +#define DDRCKECTL_CR_DDRCRCTLRANKSUSED_REG (0x00003820) + #define DDRCKECTL_CR_DDRCRCTLRANKSUSED_RankEn_OFF ( 0) + #define DDRCKECTL_CR_DDRCRCTLRANKSUSED_RankEn_WID ( 4) + #define DDRCKECTL_CR_DDRCRCTLRANKSUSED_RankEn_MSK (0x0000000F) + #define DDRCKECTL_CR_DDRCRCTLRANKSUSED_RankEn_MAX (0x0000000F) + #define DDRCKECTL_CR_DDRCRCTLRANKSUSED_RankEn_DEF (0x0000000F) + #define DDRCKECTL_CR_DDRCRCTLRANKSUSED_OdtDisable_OFF ( 4) + #define DDRCKECTL_CR_DDRCRCTLRANKSUSED_OdtDisable_WID ( 2) + #define DDRCKECTL_CR_DDRCRCTLRANKSUSED_OdtDisable_MSK (0x00000030) + #define DDRCKECTL_CR_DDRCRCTLRANKSUSED_OdtDisable_MAX (0x00000003) + #define DDRCKECTL_CR_DDRCRCTLRANKSUSED_OdtDisable_DEF (0x00000000) + #define DDRCKECTL_CR_DDRCRCTLRANKSUSED_Spare_OFF ( 6) + #define DDRCKECTL_CR_DDRCRCTLRANKSUSED_Spare_WID (26) + #define DDRCKECTL_CR_DDRCRCTLRANKSUSED_Spare_MSK (0xFFFFFFC0) + #define DDRCKECTL_CR_DDRCRCTLRANKSUSED_Spare_MAX (0x03FFFFFF) + #define DDRCKECTL_CR_DDRCRCTLRANKSUSED_Spare_DEF (0x00000000) + +#define DDRCKECTL_CR_DLLPITESTANDADC_REG (0x00003824) + #define DDRCKECTL_CR_DLLPITESTANDADC_RunTest_OFF ( 0) + #define DDRCKECTL_CR_DLLPITESTANDADC_RunTest_WID ( 1) + #define DDRCKECTL_CR_DLLPITESTANDADC_RunTest_MSK (0x00000001) + #define DDRCKECTL_CR_DLLPITESTANDADC_RunTest_MAX (0x00000001) + #define DDRCKECTL_CR_DLLPITESTANDADC_RunTest_DEF (0x00000000) + #define DDRCKECTL_CR_DLLPITESTANDADC_Load_OFF ( 1) + #define DDRCKECTL_CR_DLLPITESTANDADC_Load_WID ( 1) + #define DDRCKECTL_CR_DLLPITESTANDADC_Load_MSK (0x00000002) + #define DDRCKECTL_CR_DLLPITESTANDADC_Load_MAX (0x00000001) + #define DDRCKECTL_CR_DLLPITESTANDADC_Load_DEF (0x00000000) + #define DDRCKECTL_CR_DLLPITESTANDADC_ModeHVM_OFF ( 2) + #define DDRCKECTL_CR_DLLPITESTANDADC_ModeHVM_WID ( 1) + #define DDRCKECTL_CR_DLLPITESTANDADC_ModeHVM_MSK (0x00000004) + #define DDRCKECTL_CR_DLLPITESTANDADC_ModeHVM_MAX (0x00000001) + #define DDRCKECTL_CR_DLLPITESTANDADC_ModeHVM_DEF (0x00000000) + #define DDRCKECTL_CR_DLLPITESTANDADC_ModeDV_OFF ( 3) + #define DDRCKECTL_CR_DLLPITESTANDADC_ModeDV_WID ( 1) + #define DDRCKECTL_CR_DLLPITESTANDADC_ModeDV_MSK (0x00000008) + #define DDRCKECTL_CR_DLLPITESTANDADC_ModeDV_MAX (0x00000001) + #define DDRCKECTL_CR_DLLPITESTANDADC_ModeDV_DEF (0x00000000) + #define DDRCKECTL_CR_DLLPITESTANDADC_ModeADC_OFF ( 4) + #define DDRCKECTL_CR_DLLPITESTANDADC_ModeADC_WID ( 1) + #define DDRCKECTL_CR_DLLPITESTANDADC_ModeADC_MSK (0x00000010) + #define DDRCKECTL_CR_DLLPITESTANDADC_ModeADC_MAX (0x00000001) + #define DDRCKECTL_CR_DLLPITESTANDADC_ModeADC_DEF (0x00000000) + #define DDRCKECTL_CR_DLLPITESTANDADC_LoadCount_OFF ( 5) + #define DDRCKECTL_CR_DLLPITESTANDADC_LoadCount_WID (10) + #define DDRCKECTL_CR_DLLPITESTANDADC_LoadCount_MSK (0x00007FE0) + #define DDRCKECTL_CR_DLLPITESTANDADC_LoadCount_MAX (0x000003FF) + #define DDRCKECTL_CR_DLLPITESTANDADC_CountStatus_OFF (15) + #define DDRCKECTL_CR_DLLPITESTANDADC_CountStatus_WID (10) + #define DDRCKECTL_CR_DLLPITESTANDADC_CountStatus_MSK (0x01FF8000) + #define DDRCKECTL_CR_DLLPITESTANDADC_CountStatus_MAX (0x000003FF) + #define DDRCKECTL_CR_DLLPITESTANDADC_CountStatus_DEF (0x00000000) + #define DDRCKECTL_CR_DLLPITESTANDADC_Spare_OFF (25) + #define DDRCKECTL_CR_DLLPITESTANDADC_Spare_WID ( 7) + #define DDRCKECTL_CR_DLLPITESTANDADC_Spare_MSK (0xFE000000) + #define DDRCKECTL_CR_DLLPITESTANDADC_Spare_MAX (0x0000007F) + +#define DDRCKECTLCH0_CR_DDRCRCTLCOMP_REG (0x00003410) + #define DDRCKECTLCH0_CR_DDRCRCTLCOMP_Scomp_OFF ( 0) + #define DDRCKECTLCH0_CR_DDRCRCTLCOMP_Scomp_WID ( 6) + #define DDRCKECTLCH0_CR_DDRCRCTLCOMP_Scomp_MSK (0x0000003F) + #define DDRCKECTLCH0_CR_DDRCRCTLCOMP_Scomp_MAX (0x0000003F) + #define DDRCKECTLCH0_CR_DDRCRCTLCOMP_Scomp_DEF (0x00000000) + #define DDRCKECTLCH0_CR_DDRCRCTLCOMP_TcoComp_OFF ( 6) + #define DDRCKECTLCH0_CR_DDRCRCTLCOMP_TcoComp_WID ( 6) + #define DDRCKECTLCH0_CR_DDRCRCTLCOMP_TcoComp_MSK (0x00000FC0) + #define DDRCKECTLCH0_CR_DDRCRCTLCOMP_TcoComp_MAX (0x0000003F) + #define DDRCKECTLCH0_CR_DDRCRCTLCOMP_TcoComp_DEF (0x00000000) + #define DDRCKECTLCH0_CR_DDRCRCTLCOMP_RcompDrvUp_OFF (12) + #define DDRCKECTLCH0_CR_DDRCRCTLCOMP_RcompDrvUp_WID ( 6) + #define DDRCKECTLCH0_CR_DDRCRCTLCOMP_RcompDrvUp_MSK (0x0003F000) + #define DDRCKECTLCH0_CR_DDRCRCTLCOMP_RcompDrvUp_MAX (0x0000003F) + #define DDRCKECTLCH0_CR_DDRCRCTLCOMP_RcompDrvUp_DEF (0x00000000) + #define DDRCKECTLCH0_CR_DDRCRCTLCOMP_RcompDrvDown_OFF (18) + #define DDRCKECTLCH0_CR_DDRCRCTLCOMP_RcompDrvDown_WID ( 6) + #define DDRCKECTLCH0_CR_DDRCRCTLCOMP_RcompDrvDown_MSK (0x00FC0000) + #define DDRCKECTLCH0_CR_DDRCRCTLCOMP_RcompDrvDown_MAX (0x0000003F) + #define DDRCKECTLCH0_CR_DDRCRCTLCOMP_RcompDrvDown_DEF (0x00000000) + #define DDRCKECTLCH0_CR_DDRCRCTLCOMP_LsComp_OFF (24) + #define DDRCKECTLCH0_CR_DDRCRCTLCOMP_LsComp_WID ( 3) + #define DDRCKECTLCH0_CR_DDRCRCTLCOMP_LsComp_MSK (0x07000000) + #define DDRCKECTLCH0_CR_DDRCRCTLCOMP_LsComp_MAX (0x00000007) + #define DDRCKECTLCH0_CR_DDRCRCTLCOMP_LsComp_DEF (0x00000000) + #define DDRCKECTLCH0_CR_DDRCRCTLCOMP_Spare_OFF (27) + #define DDRCKECTLCH0_CR_DDRCRCTLCOMP_Spare_WID ( 5) + #define DDRCKECTLCH0_CR_DDRCRCTLCOMP_Spare_MSK (0xF8000000) + #define DDRCKECTLCH0_CR_DDRCRCTLCOMP_Spare_MAX (0x0000001F) + #define DDRCKECTLCH0_CR_DDRCRCTLCOMP_Spare_DEF (0x00000000) + +#define DDRCKECTLCH0_CR_DDRCRCTLCOMPOFFSET_REG (0x00003414) + #define DDRCKECTLCH0_CR_DDRCRCTLCOMPOFFSET_ScompOffset_OFF ( 0) + #define DDRCKECTLCH0_CR_DDRCRCTLCOMPOFFSET_ScompOffset_WID ( 5) + #define DDRCKECTLCH0_CR_DDRCRCTLCOMPOFFSET_ScompOffset_MSK (0x0000001F) + #define DDRCKECTLCH0_CR_DDRCRCTLCOMPOFFSET_ScompOffset_MAX (0x0000001F) + #define DDRCKECTLCH0_CR_DDRCRCTLCOMPOFFSET_ScompOffset_DEF (0x00000000) + #define DDRCKECTLCH0_CR_DDRCRCTLCOMPOFFSET_TcoCompOffset_OFF ( 5) + #define DDRCKECTLCH0_CR_DDRCRCTLCOMPOFFSET_TcoCompOffset_WID ( 4) + #define DDRCKECTLCH0_CR_DDRCRCTLCOMPOFFSET_TcoCompOffset_MSK (0x000001E0) + #define DDRCKECTLCH0_CR_DDRCRCTLCOMPOFFSET_TcoCompOffset_MAX (0x0000000F) + #define DDRCKECTLCH0_CR_DDRCRCTLCOMPOFFSET_TcoCompOffset_DEF (0x00000000) + #define DDRCKECTLCH0_CR_DDRCRCTLCOMPOFFSET_RcompDrvUpOffset_OFF ( 9) + #define DDRCKECTLCH0_CR_DDRCRCTLCOMPOFFSET_RcompDrvUpOffset_WID ( 4) + #define DDRCKECTLCH0_CR_DDRCRCTLCOMPOFFSET_RcompDrvUpOffset_MSK (0x00001E00) + #define DDRCKECTLCH0_CR_DDRCRCTLCOMPOFFSET_RcompDrvUpOffset_MAX (0x0000000F) + #define DDRCKECTLCH0_CR_DDRCRCTLCOMPOFFSET_RcompDrvUpOffset_DEF (0x00000000) + #define DDRCKECTLCH0_CR_DDRCRCTLCOMPOFFSET_RcompDrvDownOffset_OFF (13) + #define DDRCKECTLCH0_CR_DDRCRCTLCOMPOFFSET_RcompDrvDownOffset_WID ( 4) + #define DDRCKECTLCH0_CR_DDRCRCTLCOMPOFFSET_RcompDrvDownOffset_MSK (0x0001E000) + #define DDRCKECTLCH0_CR_DDRCRCTLCOMPOFFSET_RcompDrvDownOffset_MAX (0x0000000F) + #define DDRCKECTLCH0_CR_DDRCRCTLCOMPOFFSET_RcompDrvDownOffset_DEF (0x00000000) + #define DDRCKECTLCH0_CR_DDRCRCTLCOMPOFFSET_Spare_OFF (17) + #define DDRCKECTLCH0_CR_DDRCRCTLCOMPOFFSET_Spare_WID (15) + #define DDRCKECTLCH0_CR_DDRCRCTLCOMPOFFSET_Spare_MSK (0xFFFE0000) + #define DDRCKECTLCH0_CR_DDRCRCTLCOMPOFFSET_Spare_MAX (0x00007FFF) + #define DDRCKECTLCH0_CR_DDRCRCTLCOMPOFFSET_Spare_DEF (0x00000000) + +#define DDRCKECTLCH0_CR_DDRCRCTLPICODING_REG (0x00003418) + #define DDRCKECTLCH0_CR_DDRCRCTLPICODING_CtlPiCode0_OFF ( 0) + #define DDRCKECTLCH0_CR_DDRCRCTLPICODING_CtlPiCode0_WID ( 7) + #define DDRCKECTLCH0_CR_DDRCRCTLPICODING_CtlPiCode0_MSK (0x0000007F) + #define DDRCKECTLCH0_CR_DDRCRCTLPICODING_CtlPiCode0_MAX (0x0000007F) + #define DDRCKECTLCH0_CR_DDRCRCTLPICODING_CtlPiCode0_DEF (0x00000000) + #define DDRCKECTLCH0_CR_DDRCRCTLPICODING_CtlPiCode1_OFF ( 7) + #define DDRCKECTLCH0_CR_DDRCRCTLPICODING_CtlPiCode1_WID ( 7) + #define DDRCKECTLCH0_CR_DDRCRCTLPICODING_CtlPiCode1_MSK (0x00003F80) + #define DDRCKECTLCH0_CR_DDRCRCTLPICODING_CtlPiCode1_MAX (0x0000007F) + #define DDRCKECTLCH0_CR_DDRCRCTLPICODING_CtlPiCode1_DEF (0x00000000) + #define DDRCKECTLCH0_CR_DDRCRCTLPICODING_CtlPiCode2_OFF (14) + #define DDRCKECTLCH0_CR_DDRCRCTLPICODING_CtlPiCode2_WID ( 7) + #define DDRCKECTLCH0_CR_DDRCRCTLPICODING_CtlPiCode2_MSK (0x001FC000) + #define DDRCKECTLCH0_CR_DDRCRCTLPICODING_CtlPiCode2_MAX (0x0000007F) + #define DDRCKECTLCH0_CR_DDRCRCTLPICODING_CtlPiCode2_DEF (0x00000000) + #define DDRCKECTLCH0_CR_DDRCRCTLPICODING_CtlPiCode3_OFF (21) + #define DDRCKECTLCH0_CR_DDRCRCTLPICODING_CtlPiCode3_WID ( 7) + #define DDRCKECTLCH0_CR_DDRCRCTLPICODING_CtlPiCode3_MSK (0x0FE00000) + #define DDRCKECTLCH0_CR_DDRCRCTLPICODING_CtlPiCode3_MAX (0x0000007F) + #define DDRCKECTLCH0_CR_DDRCRCTLPICODING_CtlPiCode3_DEF (0x00000000) + #define DDRCKECTLCH0_CR_DDRCRCTLPICODING_CtlXoverEnable_OFF (28) + #define DDRCKECTLCH0_CR_DDRCRCTLPICODING_CtlXoverEnable_WID ( 1) + #define DDRCKECTLCH0_CR_DDRCRCTLPICODING_CtlXoverEnable_MSK (0x10000000) + #define DDRCKECTLCH0_CR_DDRCRCTLPICODING_CtlXoverEnable_MAX (0x00000001) + #define DDRCKECTLCH0_CR_DDRCRCTLPICODING_CtlXoverEnable_DEF (0x00000000) + #define DDRCKECTLCH0_CR_DDRCRCTLPICODING_Spare_OFF (29) + #define DDRCKECTLCH0_CR_DDRCRCTLPICODING_Spare_WID ( 3) + #define DDRCKECTLCH0_CR_DDRCRCTLPICODING_Spare_MSK (0xE0000000) + #define DDRCKECTLCH0_CR_DDRCRCTLPICODING_Spare_MAX (0x00000007) + #define DDRCKECTLCH0_CR_DDRCRCTLPICODING_Spare_DEF (0x00000000) + +#define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_REG (0x0000341C) + #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_RefPi_OFF ( 0) + #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_RefPi_WID ( 4) + #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_RefPi_MSK (0x0000000F) + #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_RefPi_MAX (0x0000000F) + #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_RefPi_DEF (0x00000000) + #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_DllMask_OFF ( 4) + #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_DllMask_WID ( 2) + #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_DllMask_MSK (0x00000030) + #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_DllMask_MAX (0x00000003) + #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_DllMask_DEF (0x00000000) + #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_DllRsvd1_OFF ( 6) + #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_DllRsvd1_WID ( 1) + #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_DllRsvd1_MSK (0x00000040) + #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_DllRsvd1_MAX (0x00000001) + #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_DllRsvd1_DEF (0x00000000) + #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_TxOn_OFF ( 7) + #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_TxOn_WID ( 1) + #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_TxOn_MSK (0x00000080) + #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_TxOn_MAX (0x00000001) + #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_TxOn_DEF (0x00000000) + #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_IntClkOn_OFF ( 8) + #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_IntClkOn_WID ( 1) + #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_IntClkOn_MSK (0x00000100) + #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_IntClkOn_MAX (0x00000001) + #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_IntClkOn_DEF (0x00000000) + #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_RepClkOn_OFF ( 9) + #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_RepClkOn_WID ( 1) + #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_RepClkOn_MSK (0x00000200) + #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_RepClkOn_MAX (0x00000001) + #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_RepClkOn_DEF (0x00000000) + #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_IOLBCtl_OFF (10) + #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_IOLBCtl_WID ( 2) + #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_IOLBCtl_MSK (0x00000C00) + #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_IOLBCtl_MAX (0x00000003) + #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_IOLBCtl_DEF (0x00000000) + #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_OdtMode_OFF (12) + #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_OdtMode_WID ( 1) + #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_OdtMode_MSK (0x00001000) + #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_OdtMode_MAX (0x00000001) + #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_OdtMode_DEF (0x00000000) + #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_CmdTxEq_OFF (13) + #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_CmdTxEq_WID ( 2) + #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_CmdTxEq_MSK (0x00006000) + #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_CmdTxEq_MAX (0x00000003) + #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_CmdTxEq_DEF (0x00000000) + #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_EarlyWeakDrive_OFF (15) + #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_EarlyWeakDrive_WID ( 2) + #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_EarlyWeakDrive_MSK (0x00018000) + #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_EarlyWeakDrive_MAX (0x00000003) + #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_EarlyWeakDrive_DEF (0x00000000) + #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_CtlTxEq_OFF (17) + #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_CtlTxEq_WID ( 2) + #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_CtlTxEq_MSK (0x00060000) + #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_CtlTxEq_MAX (0x00000003) + #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_CtlTxEq_DEF (0x00000000) + #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_CtlSRDrv_OFF (19) + #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_CtlSRDrv_WID ( 2) + #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_CtlSRDrv_MSK (0x00180000) + #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_CtlSRDrv_MAX (0x00000003) + #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_CtlSRDrv_DEF (0x00000000) + #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_RxVref_OFF (21) + #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_RxVref_WID ( 6) + #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_RxVref_MSK (0x07E00000) + #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_RxVref_MAX (0x0000003F) + #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_RxVref_DEF (0x00000000) + #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_VccddqHi_OFF (27) + #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_VccddqHi_WID ( 1) + #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_VccddqHi_MSK (0x08000000) + #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_VccddqHi_MAX (0x00000001) + #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_VccddqHi_DEF (0x00000000) + #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_DllWeakLock_OFF (28) + #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_DllWeakLock_WID ( 1) + #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_DllWeakLock_MSK (0x10000000) + #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_DllWeakLock_MAX (0x00000001) + #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_DllWeakLock_DEF (0x00000000) + #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_LPDDR_Mode_OFF (29) + #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_LPDDR_Mode_WID ( 1) + #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_LPDDR_Mode_MSK (0x20000000) + #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_LPDDR_Mode_MAX (0x00000001) + #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_LPDDR_Mode_DEF (0x00000000) + #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_LaDrvEnOvrd_OFF (30) + #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_LaDrvEnOvrd_WID ( 1) + #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_LaDrvEnOvrd_MSK (0x40000000) + #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_LaDrvEnOvrd_MAX (0x00000001) + #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_LaDrvEnOvrd_DEF (0x00000000) + #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_LPDdrCAA_Dis_OFF (31) + #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_LPDdrCAA_Dis_WID ( 1) + #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_LPDdrCAA_Dis_MSK (0x80000000) + #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_LPDdrCAA_Dis_MAX (0x00000001) + #define DDRCKECTLCH0_CR_DDRCRCTLCONTROLS_LPDdrCAA_Dis_DEF (0x00000000) + +#define DDRCKECTLCH0_CR_DDRCRCTLRANKSUSED_REG (0x00003420) + #define DDRCKECTLCH0_CR_DDRCRCTLRANKSUSED_RankEn_OFF ( 0) + #define DDRCKECTLCH0_CR_DDRCRCTLRANKSUSED_RankEn_WID ( 4) + #define DDRCKECTLCH0_CR_DDRCRCTLRANKSUSED_RankEn_MSK (0x0000000F) + #define DDRCKECTLCH0_CR_DDRCRCTLRANKSUSED_RankEn_MAX (0x0000000F) + #define DDRCKECTLCH0_CR_DDRCRCTLRANKSUSED_RankEn_DEF (0x0000000F) + #define DDRCKECTLCH0_CR_DDRCRCTLRANKSUSED_OdtDisable_OFF ( 4) + #define DDRCKECTLCH0_CR_DDRCRCTLRANKSUSED_OdtDisable_WID ( 2) + #define DDRCKECTLCH0_CR_DDRCRCTLRANKSUSED_OdtDisable_MSK (0x00000030) + #define DDRCKECTLCH0_CR_DDRCRCTLRANKSUSED_OdtDisable_MAX (0x00000003) + #define DDRCKECTLCH0_CR_DDRCRCTLRANKSUSED_OdtDisable_DEF (0x00000000) + #define DDRCKECTLCH0_CR_DDRCRCTLRANKSUSED_Spare_OFF ( 6) + #define DDRCKECTLCH0_CR_DDRCRCTLRANKSUSED_Spare_WID (26) + #define DDRCKECTLCH0_CR_DDRCRCTLRANKSUSED_Spare_MSK (0xFFFFFFC0) + #define DDRCKECTLCH0_CR_DDRCRCTLRANKSUSED_Spare_MAX (0x03FFFFFF) + #define DDRCKECTLCH0_CR_DDRCRCTLRANKSUSED_Spare_DEF (0x00000000) + +#define DDRCKECTLCH0_CR_DLLPITESTANDADC_REG (0x00003424) + #define DDRCKECTLCH0_CR_DLLPITESTANDADC_RunTest_OFF ( 0) + #define DDRCKECTLCH0_CR_DLLPITESTANDADC_RunTest_WID ( 1) + #define DDRCKECTLCH0_CR_DLLPITESTANDADC_RunTest_MSK (0x00000001) + #define DDRCKECTLCH0_CR_DLLPITESTANDADC_RunTest_MAX (0x00000001) + #define DDRCKECTLCH0_CR_DLLPITESTANDADC_RunTest_DEF (0x00000000) + #define DDRCKECTLCH0_CR_DLLPITESTANDADC_Load_OFF ( 1) + #define DDRCKECTLCH0_CR_DLLPITESTANDADC_Load_WID ( 1) + #define DDRCKECTLCH0_CR_DLLPITESTANDADC_Load_MSK (0x00000002) + #define DDRCKECTLCH0_CR_DLLPITESTANDADC_Load_MAX (0x00000001) + #define DDRCKECTLCH0_CR_DLLPITESTANDADC_Load_DEF (0x00000000) + #define DDRCKECTLCH0_CR_DLLPITESTANDADC_ModeHVM_OFF ( 2) + #define DDRCKECTLCH0_CR_DLLPITESTANDADC_ModeHVM_WID ( 1) + #define DDRCKECTLCH0_CR_DLLPITESTANDADC_ModeHVM_MSK (0x00000004) + #define DDRCKECTLCH0_CR_DLLPITESTANDADC_ModeHVM_MAX (0x00000001) + #define DDRCKECTLCH0_CR_DLLPITESTANDADC_ModeHVM_DEF (0x00000000) + #define DDRCKECTLCH0_CR_DLLPITESTANDADC_ModeDV_OFF ( 3) + #define DDRCKECTLCH0_CR_DLLPITESTANDADC_ModeDV_WID ( 1) + #define DDRCKECTLCH0_CR_DLLPITESTANDADC_ModeDV_MSK (0x00000008) + #define DDRCKECTLCH0_CR_DLLPITESTANDADC_ModeDV_MAX (0x00000001) + #define DDRCKECTLCH0_CR_DLLPITESTANDADC_ModeDV_DEF (0x00000000) + #define DDRCKECTLCH0_CR_DLLPITESTANDADC_ModeADC_OFF ( 4) + #define DDRCKECTLCH0_CR_DLLPITESTANDADC_ModeADC_WID ( 1) + #define DDRCKECTLCH0_CR_DLLPITESTANDADC_ModeADC_MSK (0x00000010) + #define DDRCKECTLCH0_CR_DLLPITESTANDADC_ModeADC_MAX (0x00000001) + #define DDRCKECTLCH0_CR_DLLPITESTANDADC_ModeADC_DEF (0x00000000) + #define DDRCKECTLCH0_CR_DLLPITESTANDADC_LoadCount_OFF ( 5) + #define DDRCKECTLCH0_CR_DLLPITESTANDADC_LoadCount_WID (10) + #define DDRCKECTLCH0_CR_DLLPITESTANDADC_LoadCount_MSK (0x00007FE0) + #define DDRCKECTLCH0_CR_DLLPITESTANDADC_LoadCount_MAX (0x000003FF) + #define DDRCKECTLCH0_CR_DLLPITESTANDADC_CountStatus_OFF (15) + #define DDRCKECTLCH0_CR_DLLPITESTANDADC_CountStatus_WID (10) + #define DDRCKECTLCH0_CR_DLLPITESTANDADC_CountStatus_MSK (0x01FF8000) + #define DDRCKECTLCH0_CR_DLLPITESTANDADC_CountStatus_MAX (0x000003FF) + #define DDRCKECTLCH0_CR_DLLPITESTANDADC_CountStatus_DEF (0x00000000) + #define DDRCKECTLCH0_CR_DLLPITESTANDADC_Spare_OFF (25) + #define DDRCKECTLCH0_CR_DLLPITESTANDADC_Spare_WID ( 7) + #define DDRCKECTLCH0_CR_DLLPITESTANDADC_Spare_MSK (0xFE000000) + #define DDRCKECTLCH0_CR_DLLPITESTANDADC_Spare_MAX (0x0000007F) + +#define DDRCKECTLCH1_CR_DDRCRCTLCOMP_REG (0x00003510) + #define DDRCKECTLCH1_CR_DDRCRCTLCOMP_Scomp_OFF ( 0) + #define DDRCKECTLCH1_CR_DDRCRCTLCOMP_Scomp_WID ( 6) + #define DDRCKECTLCH1_CR_DDRCRCTLCOMP_Scomp_MSK (0x0000003F) + #define DDRCKECTLCH1_CR_DDRCRCTLCOMP_Scomp_MAX (0x0000003F) + #define DDRCKECTLCH1_CR_DDRCRCTLCOMP_Scomp_DEF (0x00000000) + #define DDRCKECTLCH1_CR_DDRCRCTLCOMP_TcoComp_OFF ( 6) + #define DDRCKECTLCH1_CR_DDRCRCTLCOMP_TcoComp_WID ( 6) + #define DDRCKECTLCH1_CR_DDRCRCTLCOMP_TcoComp_MSK (0x00000FC0) + #define DDRCKECTLCH1_CR_DDRCRCTLCOMP_TcoComp_MAX (0x0000003F) + #define DDRCKECTLCH1_CR_DDRCRCTLCOMP_TcoComp_DEF (0x00000000) + #define DDRCKECTLCH1_CR_DDRCRCTLCOMP_RcompDrvUp_OFF (12) + #define DDRCKECTLCH1_CR_DDRCRCTLCOMP_RcompDrvUp_WID ( 6) + #define DDRCKECTLCH1_CR_DDRCRCTLCOMP_RcompDrvUp_MSK (0x0003F000) + #define DDRCKECTLCH1_CR_DDRCRCTLCOMP_RcompDrvUp_MAX (0x0000003F) + #define DDRCKECTLCH1_CR_DDRCRCTLCOMP_RcompDrvUp_DEF (0x00000000) + #define DDRCKECTLCH1_CR_DDRCRCTLCOMP_RcompDrvDown_OFF (18) + #define DDRCKECTLCH1_CR_DDRCRCTLCOMP_RcompDrvDown_WID ( 6) + #define DDRCKECTLCH1_CR_DDRCRCTLCOMP_RcompDrvDown_MSK (0x00FC0000) + #define DDRCKECTLCH1_CR_DDRCRCTLCOMP_RcompDrvDown_MAX (0x0000003F) + #define DDRCKECTLCH1_CR_DDRCRCTLCOMP_RcompDrvDown_DEF (0x00000000) + #define DDRCKECTLCH1_CR_DDRCRCTLCOMP_LsComp_OFF (24) + #define DDRCKECTLCH1_CR_DDRCRCTLCOMP_LsComp_WID ( 3) + #define DDRCKECTLCH1_CR_DDRCRCTLCOMP_LsComp_MSK (0x07000000) + #define DDRCKECTLCH1_CR_DDRCRCTLCOMP_LsComp_MAX (0x00000007) + #define DDRCKECTLCH1_CR_DDRCRCTLCOMP_LsComp_DEF (0x00000000) + #define DDRCKECTLCH1_CR_DDRCRCTLCOMP_Spare_OFF (27) + #define DDRCKECTLCH1_CR_DDRCRCTLCOMP_Spare_WID ( 5) + #define DDRCKECTLCH1_CR_DDRCRCTLCOMP_Spare_MSK (0xF8000000) + #define DDRCKECTLCH1_CR_DDRCRCTLCOMP_Spare_MAX (0x0000001F) + #define DDRCKECTLCH1_CR_DDRCRCTLCOMP_Spare_DEF (0x00000000) + +#define DDRCKECTLCH1_CR_DDRCRCTLCOMPOFFSET_REG (0x00003514) + #define DDRCKECTLCH1_CR_DDRCRCTLCOMPOFFSET_ScompOffset_OFF ( 0) + #define DDRCKECTLCH1_CR_DDRCRCTLCOMPOFFSET_ScompOffset_WID ( 5) + #define DDRCKECTLCH1_CR_DDRCRCTLCOMPOFFSET_ScompOffset_MSK (0x0000001F) + #define DDRCKECTLCH1_CR_DDRCRCTLCOMPOFFSET_ScompOffset_MAX (0x0000001F) + #define DDRCKECTLCH1_CR_DDRCRCTLCOMPOFFSET_ScompOffset_DEF (0x00000000) + #define DDRCKECTLCH1_CR_DDRCRCTLCOMPOFFSET_TcoCompOffset_OFF ( 5) + #define DDRCKECTLCH1_CR_DDRCRCTLCOMPOFFSET_TcoCompOffset_WID ( 4) + #define DDRCKECTLCH1_CR_DDRCRCTLCOMPOFFSET_TcoCompOffset_MSK (0x000001E0) + #define DDRCKECTLCH1_CR_DDRCRCTLCOMPOFFSET_TcoCompOffset_MAX (0x0000000F) + #define DDRCKECTLCH1_CR_DDRCRCTLCOMPOFFSET_TcoCompOffset_DEF (0x00000000) + #define DDRCKECTLCH1_CR_DDRCRCTLCOMPOFFSET_RcompDrvUpOffset_OFF ( 9) + #define DDRCKECTLCH1_CR_DDRCRCTLCOMPOFFSET_RcompDrvUpOffset_WID ( 4) + #define DDRCKECTLCH1_CR_DDRCRCTLCOMPOFFSET_RcompDrvUpOffset_MSK (0x00001E00) + #define DDRCKECTLCH1_CR_DDRCRCTLCOMPOFFSET_RcompDrvUpOffset_MAX (0x0000000F) + #define DDRCKECTLCH1_CR_DDRCRCTLCOMPOFFSET_RcompDrvUpOffset_DEF (0x00000000) + #define DDRCKECTLCH1_CR_DDRCRCTLCOMPOFFSET_RcompDrvDownOffset_OFF (13) + #define DDRCKECTLCH1_CR_DDRCRCTLCOMPOFFSET_RcompDrvDownOffset_WID ( 4) + #define DDRCKECTLCH1_CR_DDRCRCTLCOMPOFFSET_RcompDrvDownOffset_MSK (0x0001E000) + #define DDRCKECTLCH1_CR_DDRCRCTLCOMPOFFSET_RcompDrvDownOffset_MAX (0x0000000F) + #define DDRCKECTLCH1_CR_DDRCRCTLCOMPOFFSET_RcompDrvDownOffset_DEF (0x00000000) + #define DDRCKECTLCH1_CR_DDRCRCTLCOMPOFFSET_Spare_OFF (17) + #define DDRCKECTLCH1_CR_DDRCRCTLCOMPOFFSET_Spare_WID (15) + #define DDRCKECTLCH1_CR_DDRCRCTLCOMPOFFSET_Spare_MSK (0xFFFE0000) + #define DDRCKECTLCH1_CR_DDRCRCTLCOMPOFFSET_Spare_MAX (0x00007FFF) + #define DDRCKECTLCH1_CR_DDRCRCTLCOMPOFFSET_Spare_DEF (0x00000000) + +#define DDRCKECTLCH1_CR_DDRCRCTLPICODING_REG (0x00003518) + #define DDRCKECTLCH1_CR_DDRCRCTLPICODING_CtlPiCode0_OFF ( 0) + #define DDRCKECTLCH1_CR_DDRCRCTLPICODING_CtlPiCode0_WID ( 7) + #define DDRCKECTLCH1_CR_DDRCRCTLPICODING_CtlPiCode0_MSK (0x0000007F) + #define DDRCKECTLCH1_CR_DDRCRCTLPICODING_CtlPiCode0_MAX (0x0000007F) + #define DDRCKECTLCH1_CR_DDRCRCTLPICODING_CtlPiCode0_DEF (0x00000000) + #define DDRCKECTLCH1_CR_DDRCRCTLPICODING_CtlPiCode1_OFF ( 7) + #define DDRCKECTLCH1_CR_DDRCRCTLPICODING_CtlPiCode1_WID ( 7) + #define DDRCKECTLCH1_CR_DDRCRCTLPICODING_CtlPiCode1_MSK (0x00003F80) + #define DDRCKECTLCH1_CR_DDRCRCTLPICODING_CtlPiCode1_MAX (0x0000007F) + #define DDRCKECTLCH1_CR_DDRCRCTLPICODING_CtlPiCode1_DEF (0x00000000) + #define DDRCKECTLCH1_CR_DDRCRCTLPICODING_CtlPiCode2_OFF (14) + #define DDRCKECTLCH1_CR_DDRCRCTLPICODING_CtlPiCode2_WID ( 7) + #define DDRCKECTLCH1_CR_DDRCRCTLPICODING_CtlPiCode2_MSK (0x001FC000) + #define DDRCKECTLCH1_CR_DDRCRCTLPICODING_CtlPiCode2_MAX (0x0000007F) + #define DDRCKECTLCH1_CR_DDRCRCTLPICODING_CtlPiCode2_DEF (0x00000000) + #define DDRCKECTLCH1_CR_DDRCRCTLPICODING_CtlPiCode3_OFF (21) + #define DDRCKECTLCH1_CR_DDRCRCTLPICODING_CtlPiCode3_WID ( 7) + #define DDRCKECTLCH1_CR_DDRCRCTLPICODING_CtlPiCode3_MSK (0x0FE00000) + #define DDRCKECTLCH1_CR_DDRCRCTLPICODING_CtlPiCode3_MAX (0x0000007F) + #define DDRCKECTLCH1_CR_DDRCRCTLPICODING_CtlPiCode3_DEF (0x00000000) + #define DDRCKECTLCH1_CR_DDRCRCTLPICODING_CtlXoverEnable_OFF (28) + #define DDRCKECTLCH1_CR_DDRCRCTLPICODING_CtlXoverEnable_WID ( 1) + #define DDRCKECTLCH1_CR_DDRCRCTLPICODING_CtlXoverEnable_MSK (0x10000000) + #define DDRCKECTLCH1_CR_DDRCRCTLPICODING_CtlXoverEnable_MAX (0x00000001) + #define DDRCKECTLCH1_CR_DDRCRCTLPICODING_CtlXoverEnable_DEF (0x00000000) + #define DDRCKECTLCH1_CR_DDRCRCTLPICODING_Spare_OFF (29) + #define DDRCKECTLCH1_CR_DDRCRCTLPICODING_Spare_WID ( 3) + #define DDRCKECTLCH1_CR_DDRCRCTLPICODING_Spare_MSK (0xE0000000) + #define DDRCKECTLCH1_CR_DDRCRCTLPICODING_Spare_MAX (0x00000007) + #define DDRCKECTLCH1_CR_DDRCRCTLPICODING_Spare_DEF (0x00000000) + +#define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_REG (0x0000351C) + #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_RefPi_OFF ( 0) + #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_RefPi_WID ( 4) + #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_RefPi_MSK (0x0000000F) + #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_RefPi_MAX (0x0000000F) + #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_RefPi_DEF (0x00000000) + #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_DllMask_OFF ( 4) + #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_DllMask_WID ( 2) + #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_DllMask_MSK (0x00000030) + #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_DllMask_MAX (0x00000003) + #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_DllMask_DEF (0x00000000) + #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_DllRsvd1_OFF ( 6) + #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_DllRsvd1_WID ( 1) + #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_DllRsvd1_MSK (0x00000040) + #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_DllRsvd1_MAX (0x00000001) + #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_DllRsvd1_DEF (0x00000000) + #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_TxOn_OFF ( 7) + #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_TxOn_WID ( 1) + #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_TxOn_MSK (0x00000080) + #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_TxOn_MAX (0x00000001) + #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_TxOn_DEF (0x00000000) + #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_IntClkOn_OFF ( 8) + #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_IntClkOn_WID ( 1) + #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_IntClkOn_MSK (0x00000100) + #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_IntClkOn_MAX (0x00000001) + #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_IntClkOn_DEF (0x00000000) + #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_RepClkOn_OFF ( 9) + #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_RepClkOn_WID ( 1) + #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_RepClkOn_MSK (0x00000200) + #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_RepClkOn_MAX (0x00000001) + #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_RepClkOn_DEF (0x00000000) + #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_IOLBCtl_OFF (10) + #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_IOLBCtl_WID ( 2) + #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_IOLBCtl_MSK (0x00000C00) + #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_IOLBCtl_MAX (0x00000003) + #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_IOLBCtl_DEF (0x00000000) + #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_OdtMode_OFF (12) + #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_OdtMode_WID ( 1) + #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_OdtMode_MSK (0x00001000) + #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_OdtMode_MAX (0x00000001) + #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_OdtMode_DEF (0x00000000) + #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_CmdTxEq_OFF (13) + #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_CmdTxEq_WID ( 2) + #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_CmdTxEq_MSK (0x00006000) + #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_CmdTxEq_MAX (0x00000003) + #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_CmdTxEq_DEF (0x00000000) + #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_EarlyWeakDrive_OFF (15) + #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_EarlyWeakDrive_WID ( 2) + #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_EarlyWeakDrive_MSK (0x00018000) + #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_EarlyWeakDrive_MAX (0x00000003) + #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_EarlyWeakDrive_DEF (0x00000000) + #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_CtlTxEq_OFF (17) + #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_CtlTxEq_WID ( 2) + #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_CtlTxEq_MSK (0x00060000) + #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_CtlTxEq_MAX (0x00000003) + #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_CtlTxEq_DEF (0x00000000) + #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_CtlSRDrv_OFF (19) + #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_CtlSRDrv_WID ( 2) + #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_CtlSRDrv_MSK (0x00180000) + #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_CtlSRDrv_MAX (0x00000003) + #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_CtlSRDrv_DEF (0x00000000) + #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_RxVref_OFF (21) + #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_RxVref_WID ( 6) + #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_RxVref_MSK (0x07E00000) + #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_RxVref_MAX (0x0000003F) + #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_RxVref_DEF (0x00000000) + #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_VccddqHi_OFF (27) + #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_VccddqHi_WID ( 1) + #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_VccddqHi_MSK (0x08000000) + #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_VccddqHi_MAX (0x00000001) + #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_VccddqHi_DEF (0x00000000) + #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_DllWeakLock_OFF (28) + #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_DllWeakLock_WID ( 1) + #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_DllWeakLock_MSK (0x10000000) + #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_DllWeakLock_MAX (0x00000001) + #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_DllWeakLock_DEF (0x00000000) + #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_LPDDR_Mode_OFF (29) + #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_LPDDR_Mode_WID ( 1) + #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_LPDDR_Mode_MSK (0x20000000) + #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_LPDDR_Mode_MAX (0x00000001) + #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_LPDDR_Mode_DEF (0x00000000) + #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_LaDrvEnOvrd_OFF (30) + #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_LaDrvEnOvrd_WID ( 1) + #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_LaDrvEnOvrd_MSK (0x40000000) + #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_LaDrvEnOvrd_MAX (0x00000001) + #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_LaDrvEnOvrd_DEF (0x00000000) + #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_LPDdrCAA_Dis_OFF (31) + #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_LPDdrCAA_Dis_WID ( 1) + #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_LPDdrCAA_Dis_MSK (0x80000000) + #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_LPDdrCAA_Dis_MAX (0x00000001) + #define DDRCKECTLCH1_CR_DDRCRCTLCONTROLS_LPDdrCAA_Dis_DEF (0x00000000) + +#define DDRCKECTLCH1_CR_DDRCRCTLRANKSUSED_REG (0x00003520) + #define DDRCKECTLCH1_CR_DDRCRCTLRANKSUSED_RankEn_OFF ( 0) + #define DDRCKECTLCH1_CR_DDRCRCTLRANKSUSED_RankEn_WID ( 4) + #define DDRCKECTLCH1_CR_DDRCRCTLRANKSUSED_RankEn_MSK (0x0000000F) + #define DDRCKECTLCH1_CR_DDRCRCTLRANKSUSED_RankEn_MAX (0x0000000F) + #define DDRCKECTLCH1_CR_DDRCRCTLRANKSUSED_RankEn_DEF (0x0000000F) + #define DDRCKECTLCH1_CR_DDRCRCTLRANKSUSED_OdtDisable_OFF ( 4) + #define DDRCKECTLCH1_CR_DDRCRCTLRANKSUSED_OdtDisable_WID ( 2) + #define DDRCKECTLCH1_CR_DDRCRCTLRANKSUSED_OdtDisable_MSK (0x00000030) + #define DDRCKECTLCH1_CR_DDRCRCTLRANKSUSED_OdtDisable_MAX (0x00000003) + #define DDRCKECTLCH1_CR_DDRCRCTLRANKSUSED_OdtDisable_DEF (0x00000000) + #define DDRCKECTLCH1_CR_DDRCRCTLRANKSUSED_Spare_OFF ( 6) + #define DDRCKECTLCH1_CR_DDRCRCTLRANKSUSED_Spare_WID (26) + #define DDRCKECTLCH1_CR_DDRCRCTLRANKSUSED_Spare_MSK (0xFFFFFFC0) + #define DDRCKECTLCH1_CR_DDRCRCTLRANKSUSED_Spare_MAX (0x03FFFFFF) + #define DDRCKECTLCH1_CR_DDRCRCTLRANKSUSED_Spare_DEF (0x00000000) + +#define DDRCKECTLCH1_CR_DLLPITESTANDADC_REG (0x00003524) + #define DDRCKECTLCH1_CR_DLLPITESTANDADC_RunTest_OFF ( 0) + #define DDRCKECTLCH1_CR_DLLPITESTANDADC_RunTest_WID ( 1) + #define DDRCKECTLCH1_CR_DLLPITESTANDADC_RunTest_MSK (0x00000001) + #define DDRCKECTLCH1_CR_DLLPITESTANDADC_RunTest_MAX (0x00000001) + #define DDRCKECTLCH1_CR_DLLPITESTANDADC_RunTest_DEF (0x00000000) + #define DDRCKECTLCH1_CR_DLLPITESTANDADC_Load_OFF ( 1) + #define DDRCKECTLCH1_CR_DLLPITESTANDADC_Load_WID ( 1) + #define DDRCKECTLCH1_CR_DLLPITESTANDADC_Load_MSK (0x00000002) + #define DDRCKECTLCH1_CR_DLLPITESTANDADC_Load_MAX (0x00000001) + #define DDRCKECTLCH1_CR_DLLPITESTANDADC_Load_DEF (0x00000000) + #define DDRCKECTLCH1_CR_DLLPITESTANDADC_ModeHVM_OFF ( 2) + #define DDRCKECTLCH1_CR_DLLPITESTANDADC_ModeHVM_WID ( 1) + #define DDRCKECTLCH1_CR_DLLPITESTANDADC_ModeHVM_MSK (0x00000004) + #define DDRCKECTLCH1_CR_DLLPITESTANDADC_ModeHVM_MAX (0x00000001) + #define DDRCKECTLCH1_CR_DLLPITESTANDADC_ModeHVM_DEF (0x00000000) + #define DDRCKECTLCH1_CR_DLLPITESTANDADC_ModeDV_OFF ( 3) + #define DDRCKECTLCH1_CR_DLLPITESTANDADC_ModeDV_WID ( 1) + #define DDRCKECTLCH1_CR_DLLPITESTANDADC_ModeDV_MSK (0x00000008) + #define DDRCKECTLCH1_CR_DLLPITESTANDADC_ModeDV_MAX (0x00000001) + #define DDRCKECTLCH1_CR_DLLPITESTANDADC_ModeDV_DEF (0x00000000) + #define DDRCKECTLCH1_CR_DLLPITESTANDADC_ModeADC_OFF ( 4) + #define DDRCKECTLCH1_CR_DLLPITESTANDADC_ModeADC_WID ( 1) + #define DDRCKECTLCH1_CR_DLLPITESTANDADC_ModeADC_MSK (0x00000010) + #define DDRCKECTLCH1_CR_DLLPITESTANDADC_ModeADC_MAX (0x00000001) + #define DDRCKECTLCH1_CR_DLLPITESTANDADC_ModeADC_DEF (0x00000000) + #define DDRCKECTLCH1_CR_DLLPITESTANDADC_LoadCount_OFF ( 5) + #define DDRCKECTLCH1_CR_DLLPITESTANDADC_LoadCount_WID (10) + #define DDRCKECTLCH1_CR_DLLPITESTANDADC_LoadCount_MSK (0x00007FE0) + #define DDRCKECTLCH1_CR_DLLPITESTANDADC_LoadCount_MAX (0x000003FF) + #define DDRCKECTLCH1_CR_DLLPITESTANDADC_CountStatus_OFF (15) + #define DDRCKECTLCH1_CR_DLLPITESTANDADC_CountStatus_WID (10) + #define DDRCKECTLCH1_CR_DLLPITESTANDADC_CountStatus_MSK (0x01FF8000) + #define DDRCKECTLCH1_CR_DLLPITESTANDADC_CountStatus_MAX (0x000003FF) + #define DDRCKECTLCH1_CR_DLLPITESTANDADC_CountStatus_DEF (0x00000000) + #define DDRCKECTLCH1_CR_DLLPITESTANDADC_Spare_OFF (25) + #define DDRCKECTLCH1_CR_DLLPITESTANDADC_Spare_WID ( 7) + #define DDRCKECTLCH1_CR_DLLPITESTANDADC_Spare_MSK (0xFE000000) + #define DDRCKECTLCH1_CR_DLLPITESTANDADC_Spare_MAX (0x0000007F) + +#define DDRCKECH0_CR_DDRCRCMDCOMP_REG (0x00001200) + #define DDRCKECH0_CR_DDRCRCMDCOMP_Scomp_OFF ( 0) + #define DDRCKECH0_CR_DDRCRCMDCOMP_Scomp_WID ( 6) + #define DDRCKECH0_CR_DDRCRCMDCOMP_Scomp_MSK (0x0000003F) + #define DDRCKECH0_CR_DDRCRCMDCOMP_Scomp_MAX (0x0000003F) + #define DDRCKECH0_CR_DDRCRCMDCOMP_Scomp_DEF (0x00000000) + #define DDRCKECH0_CR_DDRCRCMDCOMP_TcoComp_OFF ( 6) + #define DDRCKECH0_CR_DDRCRCMDCOMP_TcoComp_WID ( 6) + #define DDRCKECH0_CR_DDRCRCMDCOMP_TcoComp_MSK (0x00000FC0) + #define DDRCKECH0_CR_DDRCRCMDCOMP_TcoComp_MAX (0x0000003F) + #define DDRCKECH0_CR_DDRCRCMDCOMP_TcoComp_DEF (0x00000000) + #define DDRCKECH0_CR_DDRCRCMDCOMP_RcompDrvUp_OFF (12) + #define DDRCKECH0_CR_DDRCRCMDCOMP_RcompDrvUp_WID ( 6) + #define DDRCKECH0_CR_DDRCRCMDCOMP_RcompDrvUp_MSK (0x0003F000) + #define DDRCKECH0_CR_DDRCRCMDCOMP_RcompDrvUp_MAX (0x0000003F) + #define DDRCKECH0_CR_DDRCRCMDCOMP_RcompDrvUp_DEF (0x00000000) + #define DDRCKECH0_CR_DDRCRCMDCOMP_RcompDrvDown_OFF (18) + #define DDRCKECH0_CR_DDRCRCMDCOMP_RcompDrvDown_WID ( 6) + #define DDRCKECH0_CR_DDRCRCMDCOMP_RcompDrvDown_MSK (0x00FC0000) + #define DDRCKECH0_CR_DDRCRCMDCOMP_RcompDrvDown_MAX (0x0000003F) + #define DDRCKECH0_CR_DDRCRCMDCOMP_RcompDrvDown_DEF (0x00000000) + #define DDRCKECH0_CR_DDRCRCMDCOMP_LsComp_OFF (24) + #define DDRCKECH0_CR_DDRCRCMDCOMP_LsComp_WID ( 3) + #define DDRCKECH0_CR_DDRCRCMDCOMP_LsComp_MSK (0x07000000) + #define DDRCKECH0_CR_DDRCRCMDCOMP_LsComp_MAX (0x00000007) + #define DDRCKECH0_CR_DDRCRCMDCOMP_LsComp_DEF (0x00000004) + #define DDRCKECH0_CR_DDRCRCMDCOMP_Spare_OFF (27) + #define DDRCKECH0_CR_DDRCRCMDCOMP_Spare_WID ( 5) + #define DDRCKECH0_CR_DDRCRCMDCOMP_Spare_MSK (0xF8000000) + #define DDRCKECH0_CR_DDRCRCMDCOMP_Spare_MAX (0x0000001F) + #define DDRCKECH0_CR_DDRCRCMDCOMP_Spare_DEF (0x00000000) + +#define DDRCKECH0_CR_DDRCRCMDCOMPOFFSET_REG (0x00001204) + #define DDRCKECH0_CR_DDRCRCMDCOMPOFFSET_ScompOffset_OFF ( 0) + #define DDRCKECH0_CR_DDRCRCMDCOMPOFFSET_ScompOffset_WID ( 5) + #define DDRCKECH0_CR_DDRCRCMDCOMPOFFSET_ScompOffset_MSK (0x0000001F) + #define DDRCKECH0_CR_DDRCRCMDCOMPOFFSET_ScompOffset_MAX (0x0000001F) + #define DDRCKECH0_CR_DDRCRCMDCOMPOFFSET_ScompOffset_DEF (0x00000000) + #define DDRCKECH0_CR_DDRCRCMDCOMPOFFSET_TcoCompOffset_OFF ( 5) + #define DDRCKECH0_CR_DDRCRCMDCOMPOFFSET_TcoCompOffset_WID ( 4) + #define DDRCKECH0_CR_DDRCRCMDCOMPOFFSET_TcoCompOffset_MSK (0x000001E0) + #define DDRCKECH0_CR_DDRCRCMDCOMPOFFSET_TcoCompOffset_MAX (0x0000000F) + #define DDRCKECH0_CR_DDRCRCMDCOMPOFFSET_TcoCompOffset_DEF (0x00000000) + #define DDRCKECH0_CR_DDRCRCMDCOMPOFFSET_RcompDrvUpOffset_OFF ( 9) + #define DDRCKECH0_CR_DDRCRCMDCOMPOFFSET_RcompDrvUpOffset_WID ( 4) + #define DDRCKECH0_CR_DDRCRCMDCOMPOFFSET_RcompDrvUpOffset_MSK (0x00001E00) + #define DDRCKECH0_CR_DDRCRCMDCOMPOFFSET_RcompDrvUpOffset_MAX (0x0000000F) + #define DDRCKECH0_CR_DDRCRCMDCOMPOFFSET_RcompDrvUpOffset_DEF (0x00000000) + #define DDRCKECH0_CR_DDRCRCMDCOMPOFFSET_RcompDrvDownOffset_OFF (13) + #define DDRCKECH0_CR_DDRCRCMDCOMPOFFSET_RcompDrvDownOffset_WID ( 4) + #define DDRCKECH0_CR_DDRCRCMDCOMPOFFSET_RcompDrvDownOffset_MSK (0x0001E000) + #define DDRCKECH0_CR_DDRCRCMDCOMPOFFSET_RcompDrvDownOffset_MAX (0x0000000F) + #define DDRCKECH0_CR_DDRCRCMDCOMPOFFSET_RcompDrvDownOffset_DEF (0x00000000) + #define DDRCKECH0_CR_DDRCRCMDCOMPOFFSET_Spare_OFF (17) + #define DDRCKECH0_CR_DDRCRCMDCOMPOFFSET_Spare_WID (15) + #define DDRCKECH0_CR_DDRCRCMDCOMPOFFSET_Spare_MSK (0xFFFE0000) + #define DDRCKECH0_CR_DDRCRCMDCOMPOFFSET_Spare_MAX (0x00007FFF) + #define DDRCKECH0_CR_DDRCRCMDCOMPOFFSET_Spare_DEF (0x00000000) + +#define DDRCKECH0_CR_DDRCRCMDPICODING_REG (0x00001208) + #define DDRCKECH0_CR_DDRCRCMDPICODING_CmdPi0Code_OFF ( 0) + #define DDRCKECH0_CR_DDRCRCMDPICODING_CmdPi0Code_WID ( 7) + #define DDRCKECH0_CR_DDRCRCMDPICODING_CmdPi0Code_MSK (0x0000007F) + #define DDRCKECH0_CR_DDRCRCMDPICODING_CmdPi0Code_MAX (0x0000007F) + #define DDRCKECH0_CR_DDRCRCMDPICODING_CmdPi0Code_DEF (0x00000000) + #define DDRCKECH0_CR_DDRCRCMDPICODING_CmdPi1Code_OFF ( 7) + #define DDRCKECH0_CR_DDRCRCMDPICODING_CmdPi1Code_WID ( 7) + #define DDRCKECH0_CR_DDRCRCMDPICODING_CmdPi1Code_MSK (0x00003F80) + #define DDRCKECH0_CR_DDRCRCMDPICODING_CmdPi1Code_MAX (0x0000007F) + #define DDRCKECH0_CR_DDRCRCMDPICODING_CmdPi1Code_DEF (0x00000000) + #define DDRCKECH0_CR_DDRCRCMDPICODING_Spare_OFF (14) + #define DDRCKECH0_CR_DDRCRCMDPICODING_Spare_WID (18) + #define DDRCKECH0_CR_DDRCRCMDPICODING_Spare_MSK (0xFFFFC000) + #define DDRCKECH0_CR_DDRCRCMDPICODING_Spare_MAX (0x0003FFFF) + #define DDRCKECH0_CR_DDRCRCMDPICODING_Spare_DEF (0x00000000) + +#define DDRCKECH0_CR_DDRCRCTLCOMP_REG (0x00001210) + #define DDRCKECH0_CR_DDRCRCTLCOMP_Scomp_OFF ( 0) + #define DDRCKECH0_CR_DDRCRCTLCOMP_Scomp_WID ( 6) + #define DDRCKECH0_CR_DDRCRCTLCOMP_Scomp_MSK (0x0000003F) + #define DDRCKECH0_CR_DDRCRCTLCOMP_Scomp_MAX (0x0000003F) + #define DDRCKECH0_CR_DDRCRCTLCOMP_Scomp_DEF (0x00000000) + #define DDRCKECH0_CR_DDRCRCTLCOMP_TcoComp_OFF ( 6) + #define DDRCKECH0_CR_DDRCRCTLCOMP_TcoComp_WID ( 6) + #define DDRCKECH0_CR_DDRCRCTLCOMP_TcoComp_MSK (0x00000FC0) + #define DDRCKECH0_CR_DDRCRCTLCOMP_TcoComp_MAX (0x0000003F) + #define DDRCKECH0_CR_DDRCRCTLCOMP_TcoComp_DEF (0x00000000) + #define DDRCKECH0_CR_DDRCRCTLCOMP_RcompDrvUp_OFF (12) + #define DDRCKECH0_CR_DDRCRCTLCOMP_RcompDrvUp_WID ( 6) + #define DDRCKECH0_CR_DDRCRCTLCOMP_RcompDrvUp_MSK (0x0003F000) + #define DDRCKECH0_CR_DDRCRCTLCOMP_RcompDrvUp_MAX (0x0000003F) + #define DDRCKECH0_CR_DDRCRCTLCOMP_RcompDrvUp_DEF (0x00000000) + #define DDRCKECH0_CR_DDRCRCTLCOMP_RcompDrvDown_OFF (18) + #define DDRCKECH0_CR_DDRCRCTLCOMP_RcompDrvDown_WID ( 6) + #define DDRCKECH0_CR_DDRCRCTLCOMP_RcompDrvDown_MSK (0x00FC0000) + #define DDRCKECH0_CR_DDRCRCTLCOMP_RcompDrvDown_MAX (0x0000003F) + #define DDRCKECH0_CR_DDRCRCTLCOMP_RcompDrvDown_DEF (0x00000000) + #define DDRCKECH0_CR_DDRCRCTLCOMP_LsComp_OFF (24) + #define DDRCKECH0_CR_DDRCRCTLCOMP_LsComp_WID ( 3) + #define DDRCKECH0_CR_DDRCRCTLCOMP_LsComp_MSK (0x07000000) + #define DDRCKECH0_CR_DDRCRCTLCOMP_LsComp_MAX (0x00000007) + #define DDRCKECH0_CR_DDRCRCTLCOMP_LsComp_DEF (0x00000000) + #define DDRCKECH0_CR_DDRCRCTLCOMP_Spare_OFF (27) + #define DDRCKECH0_CR_DDRCRCTLCOMP_Spare_WID ( 5) + #define DDRCKECH0_CR_DDRCRCTLCOMP_Spare_MSK (0xF8000000) + #define DDRCKECH0_CR_DDRCRCTLCOMP_Spare_MAX (0x0000001F) + #define DDRCKECH0_CR_DDRCRCTLCOMP_Spare_DEF (0x00000000) + +#define DDRCKECH0_CR_DDRCRCTLCOMPOFFSET_REG (0x00001214) + #define DDRCKECH0_CR_DDRCRCTLCOMPOFFSET_ScompOffset_OFF ( 0) + #define DDRCKECH0_CR_DDRCRCTLCOMPOFFSET_ScompOffset_WID ( 5) + #define DDRCKECH0_CR_DDRCRCTLCOMPOFFSET_ScompOffset_MSK (0x0000001F) + #define DDRCKECH0_CR_DDRCRCTLCOMPOFFSET_ScompOffset_MAX (0x0000001F) + #define DDRCKECH0_CR_DDRCRCTLCOMPOFFSET_ScompOffset_DEF (0x00000000) + #define DDRCKECH0_CR_DDRCRCTLCOMPOFFSET_TcoCompOffset_OFF ( 5) + #define DDRCKECH0_CR_DDRCRCTLCOMPOFFSET_TcoCompOffset_WID ( 4) + #define DDRCKECH0_CR_DDRCRCTLCOMPOFFSET_TcoCompOffset_MSK (0x000001E0) + #define DDRCKECH0_CR_DDRCRCTLCOMPOFFSET_TcoCompOffset_MAX (0x0000000F) + #define DDRCKECH0_CR_DDRCRCTLCOMPOFFSET_TcoCompOffset_DEF (0x00000000) + #define DDRCKECH0_CR_DDRCRCTLCOMPOFFSET_RcompDrvUpOffset_OFF ( 9) + #define DDRCKECH0_CR_DDRCRCTLCOMPOFFSET_RcompDrvUpOffset_WID ( 4) + #define DDRCKECH0_CR_DDRCRCTLCOMPOFFSET_RcompDrvUpOffset_MSK (0x00001E00) + #define DDRCKECH0_CR_DDRCRCTLCOMPOFFSET_RcompDrvUpOffset_MAX (0x0000000F) + #define DDRCKECH0_CR_DDRCRCTLCOMPOFFSET_RcompDrvUpOffset_DEF (0x00000000) + #define DDRCKECH0_CR_DDRCRCTLCOMPOFFSET_RcompDrvDownOffset_OFF (13) + #define DDRCKECH0_CR_DDRCRCTLCOMPOFFSET_RcompDrvDownOffset_WID ( 4) + #define DDRCKECH0_CR_DDRCRCTLCOMPOFFSET_RcompDrvDownOffset_MSK (0x0001E000) + #define DDRCKECH0_CR_DDRCRCTLCOMPOFFSET_RcompDrvDownOffset_MAX (0x0000000F) + #define DDRCKECH0_CR_DDRCRCTLCOMPOFFSET_RcompDrvDownOffset_DEF (0x00000000) + #define DDRCKECH0_CR_DDRCRCTLCOMPOFFSET_Spare_OFF (17) + #define DDRCKECH0_CR_DDRCRCTLCOMPOFFSET_Spare_WID (15) + #define DDRCKECH0_CR_DDRCRCTLCOMPOFFSET_Spare_MSK (0xFFFE0000) + #define DDRCKECH0_CR_DDRCRCTLCOMPOFFSET_Spare_MAX (0x00007FFF) + #define DDRCKECH0_CR_DDRCRCTLCOMPOFFSET_Spare_DEF (0x00000000) + +#define DDRCKECH0_CR_DDRCRCTLPICODING_REG (0x00001218) + #define DDRCKECH0_CR_DDRCRCTLPICODING_CtlPiCode0_OFF ( 0) + #define DDRCKECH0_CR_DDRCRCTLPICODING_CtlPiCode0_WID ( 7) + #define DDRCKECH0_CR_DDRCRCTLPICODING_CtlPiCode0_MSK (0x0000007F) + #define DDRCKECH0_CR_DDRCRCTLPICODING_CtlPiCode0_MAX (0x0000007F) + #define DDRCKECH0_CR_DDRCRCTLPICODING_CtlPiCode0_DEF (0x00000000) + #define DDRCKECH0_CR_DDRCRCTLPICODING_CtlPiCode1_OFF ( 7) + #define DDRCKECH0_CR_DDRCRCTLPICODING_CtlPiCode1_WID ( 7) + #define DDRCKECH0_CR_DDRCRCTLPICODING_CtlPiCode1_MSK (0x00003F80) + #define DDRCKECH0_CR_DDRCRCTLPICODING_CtlPiCode1_MAX (0x0000007F) + #define DDRCKECH0_CR_DDRCRCTLPICODING_CtlPiCode1_DEF (0x00000000) + #define DDRCKECH0_CR_DDRCRCTLPICODING_CtlPiCode2_OFF (14) + #define DDRCKECH0_CR_DDRCRCTLPICODING_CtlPiCode2_WID ( 7) + #define DDRCKECH0_CR_DDRCRCTLPICODING_CtlPiCode2_MSK (0x001FC000) + #define DDRCKECH0_CR_DDRCRCTLPICODING_CtlPiCode2_MAX (0x0000007F) + #define DDRCKECH0_CR_DDRCRCTLPICODING_CtlPiCode2_DEF (0x00000000) + #define DDRCKECH0_CR_DDRCRCTLPICODING_CtlPiCode3_OFF (21) + #define DDRCKECH0_CR_DDRCRCTLPICODING_CtlPiCode3_WID ( 7) + #define DDRCKECH0_CR_DDRCRCTLPICODING_CtlPiCode3_MSK (0x0FE00000) + #define DDRCKECH0_CR_DDRCRCTLPICODING_CtlPiCode3_MAX (0x0000007F) + #define DDRCKECH0_CR_DDRCRCTLPICODING_CtlPiCode3_DEF (0x00000000) + #define DDRCKECH0_CR_DDRCRCTLPICODING_CtlXoverEnable_OFF (28) + #define DDRCKECH0_CR_DDRCRCTLPICODING_CtlXoverEnable_WID ( 1) + #define DDRCKECH0_CR_DDRCRCTLPICODING_CtlXoverEnable_MSK (0x10000000) + #define DDRCKECH0_CR_DDRCRCTLPICODING_CtlXoverEnable_MAX (0x00000001) + #define DDRCKECH0_CR_DDRCRCTLPICODING_CtlXoverEnable_DEF (0x00000000) + #define DDRCKECH0_CR_DDRCRCTLPICODING_Spare_OFF (29) + #define DDRCKECH0_CR_DDRCRCTLPICODING_Spare_WID ( 3) + #define DDRCKECH0_CR_DDRCRCTLPICODING_Spare_MSK (0xE0000000) + #define DDRCKECH0_CR_DDRCRCTLPICODING_Spare_MAX (0x00000007) + #define DDRCKECH0_CR_DDRCRCTLPICODING_Spare_DEF (0x00000000) + +#define DDRCKECH0_CR_DDRCRCTLCONTROLS_REG (0x0000121C) + #define DDRCKECH0_CR_DDRCRCTLCONTROLS_RefPi_OFF ( 0) + #define DDRCKECH0_CR_DDRCRCTLCONTROLS_RefPi_WID ( 4) + #define DDRCKECH0_CR_DDRCRCTLCONTROLS_RefPi_MSK (0x0000000F) + #define DDRCKECH0_CR_DDRCRCTLCONTROLS_RefPi_MAX (0x0000000F) + #define DDRCKECH0_CR_DDRCRCTLCONTROLS_RefPi_DEF (0x00000000) + #define DDRCKECH0_CR_DDRCRCTLCONTROLS_DllMask_OFF ( 4) + #define DDRCKECH0_CR_DDRCRCTLCONTROLS_DllMask_WID ( 2) + #define DDRCKECH0_CR_DDRCRCTLCONTROLS_DllMask_MSK (0x00000030) + #define DDRCKECH0_CR_DDRCRCTLCONTROLS_DllMask_MAX (0x00000003) + #define DDRCKECH0_CR_DDRCRCTLCONTROLS_DllMask_DEF (0x00000000) + #define DDRCKECH0_CR_DDRCRCTLCONTROLS_DllRsvd1_OFF ( 6) + #define DDRCKECH0_CR_DDRCRCTLCONTROLS_DllRsvd1_WID ( 1) + #define DDRCKECH0_CR_DDRCRCTLCONTROLS_DllRsvd1_MSK (0x00000040) + #define DDRCKECH0_CR_DDRCRCTLCONTROLS_DllRsvd1_MAX (0x00000001) + #define DDRCKECH0_CR_DDRCRCTLCONTROLS_DllRsvd1_DEF (0x00000000) + #define DDRCKECH0_CR_DDRCRCTLCONTROLS_TxOn_OFF ( 7) + #define DDRCKECH0_CR_DDRCRCTLCONTROLS_TxOn_WID ( 1) + #define DDRCKECH0_CR_DDRCRCTLCONTROLS_TxOn_MSK (0x00000080) + #define DDRCKECH0_CR_DDRCRCTLCONTROLS_TxOn_MAX (0x00000001) + #define DDRCKECH0_CR_DDRCRCTLCONTROLS_TxOn_DEF (0x00000000) + #define DDRCKECH0_CR_DDRCRCTLCONTROLS_IntClkOn_OFF ( 8) + #define DDRCKECH0_CR_DDRCRCTLCONTROLS_IntClkOn_WID ( 1) + #define DDRCKECH0_CR_DDRCRCTLCONTROLS_IntClkOn_MSK (0x00000100) + #define DDRCKECH0_CR_DDRCRCTLCONTROLS_IntClkOn_MAX (0x00000001) + #define DDRCKECH0_CR_DDRCRCTLCONTROLS_IntClkOn_DEF (0x00000000) + #define DDRCKECH0_CR_DDRCRCTLCONTROLS_RepClkOn_OFF ( 9) + #define DDRCKECH0_CR_DDRCRCTLCONTROLS_RepClkOn_WID ( 1) + #define DDRCKECH0_CR_DDRCRCTLCONTROLS_RepClkOn_MSK (0x00000200) + #define DDRCKECH0_CR_DDRCRCTLCONTROLS_RepClkOn_MAX (0x00000001) + #define DDRCKECH0_CR_DDRCRCTLCONTROLS_RepClkOn_DEF (0x00000000) + #define DDRCKECH0_CR_DDRCRCTLCONTROLS_IOLBCtl_OFF (10) + #define DDRCKECH0_CR_DDRCRCTLCONTROLS_IOLBCtl_WID ( 2) + #define DDRCKECH0_CR_DDRCRCTLCONTROLS_IOLBCtl_MSK (0x00000C00) + #define DDRCKECH0_CR_DDRCRCTLCONTROLS_IOLBCtl_MAX (0x00000003) + #define DDRCKECH0_CR_DDRCRCTLCONTROLS_IOLBCtl_DEF (0x00000000) + #define DDRCKECH0_CR_DDRCRCTLCONTROLS_OdtMode_OFF (12) + #define DDRCKECH0_CR_DDRCRCTLCONTROLS_OdtMode_WID ( 1) + #define DDRCKECH0_CR_DDRCRCTLCONTROLS_OdtMode_MSK (0x00001000) + #define DDRCKECH0_CR_DDRCRCTLCONTROLS_OdtMode_MAX (0x00000001) + #define DDRCKECH0_CR_DDRCRCTLCONTROLS_OdtMode_DEF (0x00000000) + #define DDRCKECH0_CR_DDRCRCTLCONTROLS_CmdTxEq_OFF (13) + #define DDRCKECH0_CR_DDRCRCTLCONTROLS_CmdTxEq_WID ( 2) + #define DDRCKECH0_CR_DDRCRCTLCONTROLS_CmdTxEq_MSK (0x00006000) + #define DDRCKECH0_CR_DDRCRCTLCONTROLS_CmdTxEq_MAX (0x00000003) + #define DDRCKECH0_CR_DDRCRCTLCONTROLS_CmdTxEq_DEF (0x00000000) + #define DDRCKECH0_CR_DDRCRCTLCONTROLS_EarlyWeakDrive_OFF (15) + #define DDRCKECH0_CR_DDRCRCTLCONTROLS_EarlyWeakDrive_WID ( 2) + #define DDRCKECH0_CR_DDRCRCTLCONTROLS_EarlyWeakDrive_MSK (0x00018000) + #define DDRCKECH0_CR_DDRCRCTLCONTROLS_EarlyWeakDrive_MAX (0x00000003) + #define DDRCKECH0_CR_DDRCRCTLCONTROLS_EarlyWeakDrive_DEF (0x00000000) + #define DDRCKECH0_CR_DDRCRCTLCONTROLS_CtlTxEq_OFF (17) + #define DDRCKECH0_CR_DDRCRCTLCONTROLS_CtlTxEq_WID ( 2) + #define DDRCKECH0_CR_DDRCRCTLCONTROLS_CtlTxEq_MSK (0x00060000) + #define DDRCKECH0_CR_DDRCRCTLCONTROLS_CtlTxEq_MAX (0x00000003) + #define DDRCKECH0_CR_DDRCRCTLCONTROLS_CtlTxEq_DEF (0x00000000) + #define DDRCKECH0_CR_DDRCRCTLCONTROLS_CtlSRDrv_OFF (19) + #define DDRCKECH0_CR_DDRCRCTLCONTROLS_CtlSRDrv_WID ( 2) + #define DDRCKECH0_CR_DDRCRCTLCONTROLS_CtlSRDrv_MSK (0x00180000) + #define DDRCKECH0_CR_DDRCRCTLCONTROLS_CtlSRDrv_MAX (0x00000003) + #define DDRCKECH0_CR_DDRCRCTLCONTROLS_CtlSRDrv_DEF (0x00000000) + #define DDRCKECH0_CR_DDRCRCTLCONTROLS_RxVref_OFF (21) + #define DDRCKECH0_CR_DDRCRCTLCONTROLS_RxVref_WID ( 6) + #define DDRCKECH0_CR_DDRCRCTLCONTROLS_RxVref_MSK (0x07E00000) + #define DDRCKECH0_CR_DDRCRCTLCONTROLS_RxVref_MAX (0x0000003F) + #define DDRCKECH0_CR_DDRCRCTLCONTROLS_RxVref_DEF (0x00000000) + #define DDRCKECH0_CR_DDRCRCTLCONTROLS_VccddqHi_OFF (27) + #define DDRCKECH0_CR_DDRCRCTLCONTROLS_VccddqHi_WID ( 1) + #define DDRCKECH0_CR_DDRCRCTLCONTROLS_VccddqHi_MSK (0x08000000) + #define DDRCKECH0_CR_DDRCRCTLCONTROLS_VccddqHi_MAX (0x00000001) + #define DDRCKECH0_CR_DDRCRCTLCONTROLS_VccddqHi_DEF (0x00000000) + #define DDRCKECH0_CR_DDRCRCTLCONTROLS_DllWeakLock_OFF (28) + #define DDRCKECH0_CR_DDRCRCTLCONTROLS_DllWeakLock_WID ( 1) + #define DDRCKECH0_CR_DDRCRCTLCONTROLS_DllWeakLock_MSK (0x10000000) + #define DDRCKECH0_CR_DDRCRCTLCONTROLS_DllWeakLock_MAX (0x00000001) + #define DDRCKECH0_CR_DDRCRCTLCONTROLS_DllWeakLock_DEF (0x00000000) + #define DDRCKECH0_CR_DDRCRCTLCONTROLS_LPDDR_Mode_OFF (29) + #define DDRCKECH0_CR_DDRCRCTLCONTROLS_LPDDR_Mode_WID ( 1) + #define DDRCKECH0_CR_DDRCRCTLCONTROLS_LPDDR_Mode_MSK (0x20000000) + #define DDRCKECH0_CR_DDRCRCTLCONTROLS_LPDDR_Mode_MAX (0x00000001) + #define DDRCKECH0_CR_DDRCRCTLCONTROLS_LPDDR_Mode_DEF (0x00000000) + #define DDRCKECH0_CR_DDRCRCTLCONTROLS_LaDrvEnOvrd_OFF (30) + #define DDRCKECH0_CR_DDRCRCTLCONTROLS_LaDrvEnOvrd_WID ( 1) + #define DDRCKECH0_CR_DDRCRCTLCONTROLS_LaDrvEnOvrd_MSK (0x40000000) + #define DDRCKECH0_CR_DDRCRCTLCONTROLS_LaDrvEnOvrd_MAX (0x00000001) + #define DDRCKECH0_CR_DDRCRCTLCONTROLS_LaDrvEnOvrd_DEF (0x00000000) + #define DDRCKECH0_CR_DDRCRCTLCONTROLS_LPDdrCAA_Dis_OFF (31) + #define DDRCKECH0_CR_DDRCRCTLCONTROLS_LPDdrCAA_Dis_WID ( 1) + #define DDRCKECH0_CR_DDRCRCTLCONTROLS_LPDdrCAA_Dis_MSK (0x80000000) + #define DDRCKECH0_CR_DDRCRCTLCONTROLS_LPDdrCAA_Dis_MAX (0x00000001) + #define DDRCKECH0_CR_DDRCRCTLCONTROLS_LPDdrCAA_Dis_DEF (0x00000000) + +#define DDRCKECH0_CR_DDRCRCTLRANKSUSED_REG (0x00001220) + #define DDRCKECH0_CR_DDRCRCTLRANKSUSED_RankEn_OFF ( 0) + #define DDRCKECH0_CR_DDRCRCTLRANKSUSED_RankEn_WID ( 4) + #define DDRCKECH0_CR_DDRCRCTLRANKSUSED_RankEn_MSK (0x0000000F) + #define DDRCKECH0_CR_DDRCRCTLRANKSUSED_RankEn_MAX (0x0000000F) + #define DDRCKECH0_CR_DDRCRCTLRANKSUSED_RankEn_DEF (0x0000000F) + #define DDRCKECH0_CR_DDRCRCTLRANKSUSED_OdtDisable_OFF ( 4) + #define DDRCKECH0_CR_DDRCRCTLRANKSUSED_OdtDisable_WID ( 2) + #define DDRCKECH0_CR_DDRCRCTLRANKSUSED_OdtDisable_MSK (0x00000030) + #define DDRCKECH0_CR_DDRCRCTLRANKSUSED_OdtDisable_MAX (0x00000003) + #define DDRCKECH0_CR_DDRCRCTLRANKSUSED_OdtDisable_DEF (0x00000000) + #define DDRCKECH0_CR_DDRCRCTLRANKSUSED_Spare_OFF ( 6) + #define DDRCKECH0_CR_DDRCRCTLRANKSUSED_Spare_WID (26) + #define DDRCKECH0_CR_DDRCRCTLRANKSUSED_Spare_MSK (0xFFFFFFC0) + #define DDRCKECH0_CR_DDRCRCTLRANKSUSED_Spare_MAX (0x03FFFFFF) + #define DDRCKECH0_CR_DDRCRCTLRANKSUSED_Spare_DEF (0x00000000) + +#define DDRCKECH0_CR_DLLPITESTANDADC_REG (0x00001224) + #define DDRCKECH0_CR_DLLPITESTANDADC_RunTest_OFF ( 0) + #define DDRCKECH0_CR_DLLPITESTANDADC_RunTest_WID ( 1) + #define DDRCKECH0_CR_DLLPITESTANDADC_RunTest_MSK (0x00000001) + #define DDRCKECH0_CR_DLLPITESTANDADC_RunTest_MAX (0x00000001) + #define DDRCKECH0_CR_DLLPITESTANDADC_RunTest_DEF (0x00000000) + #define DDRCKECH0_CR_DLLPITESTANDADC_Load_OFF ( 1) + #define DDRCKECH0_CR_DLLPITESTANDADC_Load_WID ( 1) + #define DDRCKECH0_CR_DLLPITESTANDADC_Load_MSK (0x00000002) + #define DDRCKECH0_CR_DLLPITESTANDADC_Load_MAX (0x00000001) + #define DDRCKECH0_CR_DLLPITESTANDADC_Load_DEF (0x00000000) + #define DDRCKECH0_CR_DLLPITESTANDADC_ModeHVM_OFF ( 2) + #define DDRCKECH0_CR_DLLPITESTANDADC_ModeHVM_WID ( 1) + #define DDRCKECH0_CR_DLLPITESTANDADC_ModeHVM_MSK (0x00000004) + #define DDRCKECH0_CR_DLLPITESTANDADC_ModeHVM_MAX (0x00000001) + #define DDRCKECH0_CR_DLLPITESTANDADC_ModeHVM_DEF (0x00000000) + #define DDRCKECH0_CR_DLLPITESTANDADC_ModeDV_OFF ( 3) + #define DDRCKECH0_CR_DLLPITESTANDADC_ModeDV_WID ( 1) + #define DDRCKECH0_CR_DLLPITESTANDADC_ModeDV_MSK (0x00000008) + #define DDRCKECH0_CR_DLLPITESTANDADC_ModeDV_MAX (0x00000001) + #define DDRCKECH0_CR_DLLPITESTANDADC_ModeDV_DEF (0x00000000) + #define DDRCKECH0_CR_DLLPITESTANDADC_ModeADC_OFF ( 4) + #define DDRCKECH0_CR_DLLPITESTANDADC_ModeADC_WID ( 1) + #define DDRCKECH0_CR_DLLPITESTANDADC_ModeADC_MSK (0x00000010) + #define DDRCKECH0_CR_DLLPITESTANDADC_ModeADC_MAX (0x00000001) + #define DDRCKECH0_CR_DLLPITESTANDADC_ModeADC_DEF (0x00000000) + #define DDRCKECH0_CR_DLLPITESTANDADC_LoadCount_OFF ( 5) + #define DDRCKECH0_CR_DLLPITESTANDADC_LoadCount_WID (10) + #define DDRCKECH0_CR_DLLPITESTANDADC_LoadCount_MSK (0x00007FE0) + #define DDRCKECH0_CR_DLLPITESTANDADC_LoadCount_MAX (0x000003FF) + #define DDRCKECH0_CR_DLLPITESTANDADC_CountStatus_OFF (15) + #define DDRCKECH0_CR_DLLPITESTANDADC_CountStatus_WID (10) + #define DDRCKECH0_CR_DLLPITESTANDADC_CountStatus_MSK (0x01FF8000) + #define DDRCKECH0_CR_DLLPITESTANDADC_CountStatus_MAX (0x000003FF) + #define DDRCKECH0_CR_DLLPITESTANDADC_CountStatus_DEF (0x00000000) + #define DDRCKECH0_CR_DLLPITESTANDADC_Spare_OFF (25) + #define DDRCKECH0_CR_DLLPITESTANDADC_Spare_WID ( 7) + #define DDRCKECH0_CR_DLLPITESTANDADC_Spare_MSK (0xFE000000) + #define DDRCKECH0_CR_DLLPITESTANDADC_Spare_MAX (0x0000007F) + +#define DDRCKECH1_CR_DDRCRCMDCOMP_REG (0x00001300) + #define DDRCKECH1_CR_DDRCRCMDCOMP_Scomp_OFF ( 0) + #define DDRCKECH1_CR_DDRCRCMDCOMP_Scomp_WID ( 6) + #define DDRCKECH1_CR_DDRCRCMDCOMP_Scomp_MSK (0x0000003F) + #define DDRCKECH1_CR_DDRCRCMDCOMP_Scomp_MAX (0x0000003F) + #define DDRCKECH1_CR_DDRCRCMDCOMP_Scomp_DEF (0x00000000) + #define DDRCKECH1_CR_DDRCRCMDCOMP_TcoComp_OFF ( 6) + #define DDRCKECH1_CR_DDRCRCMDCOMP_TcoComp_WID ( 6) + #define DDRCKECH1_CR_DDRCRCMDCOMP_TcoComp_MSK (0x00000FC0) + #define DDRCKECH1_CR_DDRCRCMDCOMP_TcoComp_MAX (0x0000003F) + #define DDRCKECH1_CR_DDRCRCMDCOMP_TcoComp_DEF (0x00000000) + #define DDRCKECH1_CR_DDRCRCMDCOMP_RcompDrvUp_OFF (12) + #define DDRCKECH1_CR_DDRCRCMDCOMP_RcompDrvUp_WID ( 6) + #define DDRCKECH1_CR_DDRCRCMDCOMP_RcompDrvUp_MSK (0x0003F000) + #define DDRCKECH1_CR_DDRCRCMDCOMP_RcompDrvUp_MAX (0x0000003F) + #define DDRCKECH1_CR_DDRCRCMDCOMP_RcompDrvUp_DEF (0x00000000) + #define DDRCKECH1_CR_DDRCRCMDCOMP_RcompDrvDown_OFF (18) + #define DDRCKECH1_CR_DDRCRCMDCOMP_RcompDrvDown_WID ( 6) + #define DDRCKECH1_CR_DDRCRCMDCOMP_RcompDrvDown_MSK (0x00FC0000) + #define DDRCKECH1_CR_DDRCRCMDCOMP_RcompDrvDown_MAX (0x0000003F) + #define DDRCKECH1_CR_DDRCRCMDCOMP_RcompDrvDown_DEF (0x00000000) + #define DDRCKECH1_CR_DDRCRCMDCOMP_LsComp_OFF (24) + #define DDRCKECH1_CR_DDRCRCMDCOMP_LsComp_WID ( 3) + #define DDRCKECH1_CR_DDRCRCMDCOMP_LsComp_MSK (0x07000000) + #define DDRCKECH1_CR_DDRCRCMDCOMP_LsComp_MAX (0x00000007) + #define DDRCKECH1_CR_DDRCRCMDCOMP_LsComp_DEF (0x00000004) + #define DDRCKECH1_CR_DDRCRCMDCOMP_Spare_OFF (27) + #define DDRCKECH1_CR_DDRCRCMDCOMP_Spare_WID ( 5) + #define DDRCKECH1_CR_DDRCRCMDCOMP_Spare_MSK (0xF8000000) + #define DDRCKECH1_CR_DDRCRCMDCOMP_Spare_MAX (0x0000001F) + #define DDRCKECH1_CR_DDRCRCMDCOMP_Spare_DEF (0x00000000) + +#define DDRCKECH1_CR_DDRCRCMDCOMPOFFSET_REG (0x00001304) + #define DDRCKECH1_CR_DDRCRCMDCOMPOFFSET_ScompOffset_OFF ( 0) + #define DDRCKECH1_CR_DDRCRCMDCOMPOFFSET_ScompOffset_WID ( 5) + #define DDRCKECH1_CR_DDRCRCMDCOMPOFFSET_ScompOffset_MSK (0x0000001F) + #define DDRCKECH1_CR_DDRCRCMDCOMPOFFSET_ScompOffset_MAX (0x0000001F) + #define DDRCKECH1_CR_DDRCRCMDCOMPOFFSET_ScompOffset_DEF (0x00000000) + #define DDRCKECH1_CR_DDRCRCMDCOMPOFFSET_TcoCompOffset_OFF ( 5) + #define DDRCKECH1_CR_DDRCRCMDCOMPOFFSET_TcoCompOffset_WID ( 4) + #define DDRCKECH1_CR_DDRCRCMDCOMPOFFSET_TcoCompOffset_MSK (0x000001E0) + #define DDRCKECH1_CR_DDRCRCMDCOMPOFFSET_TcoCompOffset_MAX (0x0000000F) + #define DDRCKECH1_CR_DDRCRCMDCOMPOFFSET_TcoCompOffset_DEF (0x00000000) + #define DDRCKECH1_CR_DDRCRCMDCOMPOFFSET_RcompDrvUpOffset_OFF ( 9) + #define DDRCKECH1_CR_DDRCRCMDCOMPOFFSET_RcompDrvUpOffset_WID ( 4) + #define DDRCKECH1_CR_DDRCRCMDCOMPOFFSET_RcompDrvUpOffset_MSK (0x00001E00) + #define DDRCKECH1_CR_DDRCRCMDCOMPOFFSET_RcompDrvUpOffset_MAX (0x0000000F) + #define DDRCKECH1_CR_DDRCRCMDCOMPOFFSET_RcompDrvUpOffset_DEF (0x00000000) + #define DDRCKECH1_CR_DDRCRCMDCOMPOFFSET_RcompDrvDownOffset_OFF (13) + #define DDRCKECH1_CR_DDRCRCMDCOMPOFFSET_RcompDrvDownOffset_WID ( 4) + #define DDRCKECH1_CR_DDRCRCMDCOMPOFFSET_RcompDrvDownOffset_MSK (0x0001E000) + #define DDRCKECH1_CR_DDRCRCMDCOMPOFFSET_RcompDrvDownOffset_MAX (0x0000000F) + #define DDRCKECH1_CR_DDRCRCMDCOMPOFFSET_RcompDrvDownOffset_DEF (0x00000000) + #define DDRCKECH1_CR_DDRCRCMDCOMPOFFSET_Spare_OFF (17) + #define DDRCKECH1_CR_DDRCRCMDCOMPOFFSET_Spare_WID (15) + #define DDRCKECH1_CR_DDRCRCMDCOMPOFFSET_Spare_MSK (0xFFFE0000) + #define DDRCKECH1_CR_DDRCRCMDCOMPOFFSET_Spare_MAX (0x00007FFF) + #define DDRCKECH1_CR_DDRCRCMDCOMPOFFSET_Spare_DEF (0x00000000) + +#define DDRCKECH1_CR_DDRCRCMDPICODING_REG (0x00001308) + #define DDRCKECH1_CR_DDRCRCMDPICODING_CmdPi0Code_OFF ( 0) + #define DDRCKECH1_CR_DDRCRCMDPICODING_CmdPi0Code_WID ( 7) + #define DDRCKECH1_CR_DDRCRCMDPICODING_CmdPi0Code_MSK (0x0000007F) + #define DDRCKECH1_CR_DDRCRCMDPICODING_CmdPi0Code_MAX (0x0000007F) + #define DDRCKECH1_CR_DDRCRCMDPICODING_CmdPi0Code_DEF (0x00000000) + #define DDRCKECH1_CR_DDRCRCMDPICODING_CmdPi1Code_OFF ( 7) + #define DDRCKECH1_CR_DDRCRCMDPICODING_CmdPi1Code_WID ( 7) + #define DDRCKECH1_CR_DDRCRCMDPICODING_CmdPi1Code_MSK (0x00003F80) + #define DDRCKECH1_CR_DDRCRCMDPICODING_CmdPi1Code_MAX (0x0000007F) + #define DDRCKECH1_CR_DDRCRCMDPICODING_CmdPi1Code_DEF (0x00000000) + #define DDRCKECH1_CR_DDRCRCMDPICODING_Spare_OFF (14) + #define DDRCKECH1_CR_DDRCRCMDPICODING_Spare_WID (18) + #define DDRCKECH1_CR_DDRCRCMDPICODING_Spare_MSK (0xFFFFC000) + #define DDRCKECH1_CR_DDRCRCMDPICODING_Spare_MAX (0x0003FFFF) + #define DDRCKECH1_CR_DDRCRCMDPICODING_Spare_DEF (0x00000000) + +#define DDRCKECH1_CR_DDRCRCTLCOMP_REG (0x00001310) + #define DDRCKECH1_CR_DDRCRCTLCOMP_Scomp_OFF ( 0) + #define DDRCKECH1_CR_DDRCRCTLCOMP_Scomp_WID ( 6) + #define DDRCKECH1_CR_DDRCRCTLCOMP_Scomp_MSK (0x0000003F) + #define DDRCKECH1_CR_DDRCRCTLCOMP_Scomp_MAX (0x0000003F) + #define DDRCKECH1_CR_DDRCRCTLCOMP_Scomp_DEF (0x00000000) + #define DDRCKECH1_CR_DDRCRCTLCOMP_TcoComp_OFF ( 6) + #define DDRCKECH1_CR_DDRCRCTLCOMP_TcoComp_WID ( 6) + #define DDRCKECH1_CR_DDRCRCTLCOMP_TcoComp_MSK (0x00000FC0) + #define DDRCKECH1_CR_DDRCRCTLCOMP_TcoComp_MAX (0x0000003F) + #define DDRCKECH1_CR_DDRCRCTLCOMP_TcoComp_DEF (0x00000000) + #define DDRCKECH1_CR_DDRCRCTLCOMP_RcompDrvUp_OFF (12) + #define DDRCKECH1_CR_DDRCRCTLCOMP_RcompDrvUp_WID ( 6) + #define DDRCKECH1_CR_DDRCRCTLCOMP_RcompDrvUp_MSK (0x0003F000) + #define DDRCKECH1_CR_DDRCRCTLCOMP_RcompDrvUp_MAX (0x0000003F) + #define DDRCKECH1_CR_DDRCRCTLCOMP_RcompDrvUp_DEF (0x00000000) + #define DDRCKECH1_CR_DDRCRCTLCOMP_RcompDrvDown_OFF (18) + #define DDRCKECH1_CR_DDRCRCTLCOMP_RcompDrvDown_WID ( 6) + #define DDRCKECH1_CR_DDRCRCTLCOMP_RcompDrvDown_MSK (0x00FC0000) + #define DDRCKECH1_CR_DDRCRCTLCOMP_RcompDrvDown_MAX (0x0000003F) + #define DDRCKECH1_CR_DDRCRCTLCOMP_RcompDrvDown_DEF (0x00000000) + #define DDRCKECH1_CR_DDRCRCTLCOMP_LsComp_OFF (24) + #define DDRCKECH1_CR_DDRCRCTLCOMP_LsComp_WID ( 3) + #define DDRCKECH1_CR_DDRCRCTLCOMP_LsComp_MSK (0x07000000) + #define DDRCKECH1_CR_DDRCRCTLCOMP_LsComp_MAX (0x00000007) + #define DDRCKECH1_CR_DDRCRCTLCOMP_LsComp_DEF (0x00000000) + #define DDRCKECH1_CR_DDRCRCTLCOMP_Spare_OFF (27) + #define DDRCKECH1_CR_DDRCRCTLCOMP_Spare_WID ( 5) + #define DDRCKECH1_CR_DDRCRCTLCOMP_Spare_MSK (0xF8000000) + #define DDRCKECH1_CR_DDRCRCTLCOMP_Spare_MAX (0x0000001F) + #define DDRCKECH1_CR_DDRCRCTLCOMP_Spare_DEF (0x00000000) + +#define DDRCKECH1_CR_DDRCRCTLCOMPOFFSET_REG (0x00001314) + #define DDRCKECH1_CR_DDRCRCTLCOMPOFFSET_ScompOffset_OFF ( 0) + #define DDRCKECH1_CR_DDRCRCTLCOMPOFFSET_ScompOffset_WID ( 5) + #define DDRCKECH1_CR_DDRCRCTLCOMPOFFSET_ScompOffset_MSK (0x0000001F) + #define DDRCKECH1_CR_DDRCRCTLCOMPOFFSET_ScompOffset_MAX (0x0000001F) + #define DDRCKECH1_CR_DDRCRCTLCOMPOFFSET_ScompOffset_DEF (0x00000000) + #define DDRCKECH1_CR_DDRCRCTLCOMPOFFSET_TcoCompOffset_OFF ( 5) + #define DDRCKECH1_CR_DDRCRCTLCOMPOFFSET_TcoCompOffset_WID ( 4) + #define DDRCKECH1_CR_DDRCRCTLCOMPOFFSET_TcoCompOffset_MSK (0x000001E0) + #define DDRCKECH1_CR_DDRCRCTLCOMPOFFSET_TcoCompOffset_MAX (0x0000000F) + #define DDRCKECH1_CR_DDRCRCTLCOMPOFFSET_TcoCompOffset_DEF (0x00000000) + #define DDRCKECH1_CR_DDRCRCTLCOMPOFFSET_RcompDrvUpOffset_OFF ( 9) + #define DDRCKECH1_CR_DDRCRCTLCOMPOFFSET_RcompDrvUpOffset_WID ( 4) + #define DDRCKECH1_CR_DDRCRCTLCOMPOFFSET_RcompDrvUpOffset_MSK (0x00001E00) + #define DDRCKECH1_CR_DDRCRCTLCOMPOFFSET_RcompDrvUpOffset_MAX (0x0000000F) + #define DDRCKECH1_CR_DDRCRCTLCOMPOFFSET_RcompDrvUpOffset_DEF (0x00000000) + #define DDRCKECH1_CR_DDRCRCTLCOMPOFFSET_RcompDrvDownOffset_OFF (13) + #define DDRCKECH1_CR_DDRCRCTLCOMPOFFSET_RcompDrvDownOffset_WID ( 4) + #define DDRCKECH1_CR_DDRCRCTLCOMPOFFSET_RcompDrvDownOffset_MSK (0x0001E000) + #define DDRCKECH1_CR_DDRCRCTLCOMPOFFSET_RcompDrvDownOffset_MAX (0x0000000F) + #define DDRCKECH1_CR_DDRCRCTLCOMPOFFSET_RcompDrvDownOffset_DEF (0x00000000) + #define DDRCKECH1_CR_DDRCRCTLCOMPOFFSET_Spare_OFF (17) + #define DDRCKECH1_CR_DDRCRCTLCOMPOFFSET_Spare_WID (15) + #define DDRCKECH1_CR_DDRCRCTLCOMPOFFSET_Spare_MSK (0xFFFE0000) + #define DDRCKECH1_CR_DDRCRCTLCOMPOFFSET_Spare_MAX (0x00007FFF) + #define DDRCKECH1_CR_DDRCRCTLCOMPOFFSET_Spare_DEF (0x00000000) + +#define DDRCKECH1_CR_DDRCRCTLPICODING_REG (0x00001318) + #define DDRCKECH1_CR_DDRCRCTLPICODING_CtlPiCode0_OFF ( 0) + #define DDRCKECH1_CR_DDRCRCTLPICODING_CtlPiCode0_WID ( 7) + #define DDRCKECH1_CR_DDRCRCTLPICODING_CtlPiCode0_MSK (0x0000007F) + #define DDRCKECH1_CR_DDRCRCTLPICODING_CtlPiCode0_MAX (0x0000007F) + #define DDRCKECH1_CR_DDRCRCTLPICODING_CtlPiCode0_DEF (0x00000000) + #define DDRCKECH1_CR_DDRCRCTLPICODING_CtlPiCode1_OFF ( 7) + #define DDRCKECH1_CR_DDRCRCTLPICODING_CtlPiCode1_WID ( 7) + #define DDRCKECH1_CR_DDRCRCTLPICODING_CtlPiCode1_MSK (0x00003F80) + #define DDRCKECH1_CR_DDRCRCTLPICODING_CtlPiCode1_MAX (0x0000007F) + #define DDRCKECH1_CR_DDRCRCTLPICODING_CtlPiCode1_DEF (0x00000000) + #define DDRCKECH1_CR_DDRCRCTLPICODING_CtlPiCode2_OFF (14) + #define DDRCKECH1_CR_DDRCRCTLPICODING_CtlPiCode2_WID ( 7) + #define DDRCKECH1_CR_DDRCRCTLPICODING_CtlPiCode2_MSK (0x001FC000) + #define DDRCKECH1_CR_DDRCRCTLPICODING_CtlPiCode2_MAX (0x0000007F) + #define DDRCKECH1_CR_DDRCRCTLPICODING_CtlPiCode2_DEF (0x00000000) + #define DDRCKECH1_CR_DDRCRCTLPICODING_CtlPiCode3_OFF (21) + #define DDRCKECH1_CR_DDRCRCTLPICODING_CtlPiCode3_WID ( 7) + #define DDRCKECH1_CR_DDRCRCTLPICODING_CtlPiCode3_MSK (0x0FE00000) + #define DDRCKECH1_CR_DDRCRCTLPICODING_CtlPiCode3_MAX (0x0000007F) + #define DDRCKECH1_CR_DDRCRCTLPICODING_CtlPiCode3_DEF (0x00000000) + #define DDRCKECH1_CR_DDRCRCTLPICODING_CtlXoverEnable_OFF (28) + #define DDRCKECH1_CR_DDRCRCTLPICODING_CtlXoverEnable_WID ( 1) + #define DDRCKECH1_CR_DDRCRCTLPICODING_CtlXoverEnable_MSK (0x10000000) + #define DDRCKECH1_CR_DDRCRCTLPICODING_CtlXoverEnable_MAX (0x00000001) + #define DDRCKECH1_CR_DDRCRCTLPICODING_CtlXoverEnable_DEF (0x00000000) + #define DDRCKECH1_CR_DDRCRCTLPICODING_Spare_OFF (29) + #define DDRCKECH1_CR_DDRCRCTLPICODING_Spare_WID ( 3) + #define DDRCKECH1_CR_DDRCRCTLPICODING_Spare_MSK (0xE0000000) + #define DDRCKECH1_CR_DDRCRCTLPICODING_Spare_MAX (0x00000007) + #define DDRCKECH1_CR_DDRCRCTLPICODING_Spare_DEF (0x00000000) + +#define DDRCKECH1_CR_DDRCRCTLCONTROLS_REG (0x0000131C) + #define DDRCKECH1_CR_DDRCRCTLCONTROLS_RefPi_OFF ( 0) + #define DDRCKECH1_CR_DDRCRCTLCONTROLS_RefPi_WID ( 4) + #define DDRCKECH1_CR_DDRCRCTLCONTROLS_RefPi_MSK (0x0000000F) + #define DDRCKECH1_CR_DDRCRCTLCONTROLS_RefPi_MAX (0x0000000F) + #define DDRCKECH1_CR_DDRCRCTLCONTROLS_RefPi_DEF (0x00000000) + #define DDRCKECH1_CR_DDRCRCTLCONTROLS_DllMask_OFF ( 4) + #define DDRCKECH1_CR_DDRCRCTLCONTROLS_DllMask_WID ( 2) + #define DDRCKECH1_CR_DDRCRCTLCONTROLS_DllMask_MSK (0x00000030) + #define DDRCKECH1_CR_DDRCRCTLCONTROLS_DllMask_MAX (0x00000003) + #define DDRCKECH1_CR_DDRCRCTLCONTROLS_DllMask_DEF (0x00000000) + #define DDRCKECH1_CR_DDRCRCTLCONTROLS_DllRsvd1_OFF ( 6) + #define DDRCKECH1_CR_DDRCRCTLCONTROLS_DllRsvd1_WID ( 1) + #define DDRCKECH1_CR_DDRCRCTLCONTROLS_DllRsvd1_MSK (0x00000040) + #define DDRCKECH1_CR_DDRCRCTLCONTROLS_DllRsvd1_MAX (0x00000001) + #define DDRCKECH1_CR_DDRCRCTLCONTROLS_DllRsvd1_DEF (0x00000000) + #define DDRCKECH1_CR_DDRCRCTLCONTROLS_TxOn_OFF ( 7) + #define DDRCKECH1_CR_DDRCRCTLCONTROLS_TxOn_WID ( 1) + #define DDRCKECH1_CR_DDRCRCTLCONTROLS_TxOn_MSK (0x00000080) + #define DDRCKECH1_CR_DDRCRCTLCONTROLS_TxOn_MAX (0x00000001) + #define DDRCKECH1_CR_DDRCRCTLCONTROLS_TxOn_DEF (0x00000000) + #define DDRCKECH1_CR_DDRCRCTLCONTROLS_IntClkOn_OFF ( 8) + #define DDRCKECH1_CR_DDRCRCTLCONTROLS_IntClkOn_WID ( 1) + #define DDRCKECH1_CR_DDRCRCTLCONTROLS_IntClkOn_MSK (0x00000100) + #define DDRCKECH1_CR_DDRCRCTLCONTROLS_IntClkOn_MAX (0x00000001) + #define DDRCKECH1_CR_DDRCRCTLCONTROLS_IntClkOn_DEF (0x00000000) + #define DDRCKECH1_CR_DDRCRCTLCONTROLS_RepClkOn_OFF ( 9) + #define DDRCKECH1_CR_DDRCRCTLCONTROLS_RepClkOn_WID ( 1) + #define DDRCKECH1_CR_DDRCRCTLCONTROLS_RepClkOn_MSK (0x00000200) + #define DDRCKECH1_CR_DDRCRCTLCONTROLS_RepClkOn_MAX (0x00000001) + #define DDRCKECH1_CR_DDRCRCTLCONTROLS_RepClkOn_DEF (0x00000000) + #define DDRCKECH1_CR_DDRCRCTLCONTROLS_IOLBCtl_OFF (10) + #define DDRCKECH1_CR_DDRCRCTLCONTROLS_IOLBCtl_WID ( 2) + #define DDRCKECH1_CR_DDRCRCTLCONTROLS_IOLBCtl_MSK (0x00000C00) + #define DDRCKECH1_CR_DDRCRCTLCONTROLS_IOLBCtl_MAX (0x00000003) + #define DDRCKECH1_CR_DDRCRCTLCONTROLS_IOLBCtl_DEF (0x00000000) + #define DDRCKECH1_CR_DDRCRCTLCONTROLS_OdtMode_OFF (12) + #define DDRCKECH1_CR_DDRCRCTLCONTROLS_OdtMode_WID ( 1) + #define DDRCKECH1_CR_DDRCRCTLCONTROLS_OdtMode_MSK (0x00001000) + #define DDRCKECH1_CR_DDRCRCTLCONTROLS_OdtMode_MAX (0x00000001) + #define DDRCKECH1_CR_DDRCRCTLCONTROLS_OdtMode_DEF (0x00000000) + #define DDRCKECH1_CR_DDRCRCTLCONTROLS_CmdTxEq_OFF (13) + #define DDRCKECH1_CR_DDRCRCTLCONTROLS_CmdTxEq_WID ( 2) + #define DDRCKECH1_CR_DDRCRCTLCONTROLS_CmdTxEq_MSK (0x00006000) + #define DDRCKECH1_CR_DDRCRCTLCONTROLS_CmdTxEq_MAX (0x00000003) + #define DDRCKECH1_CR_DDRCRCTLCONTROLS_CmdTxEq_DEF (0x00000000) + #define DDRCKECH1_CR_DDRCRCTLCONTROLS_EarlyWeakDrive_OFF (15) + #define DDRCKECH1_CR_DDRCRCTLCONTROLS_EarlyWeakDrive_WID ( 2) + #define DDRCKECH1_CR_DDRCRCTLCONTROLS_EarlyWeakDrive_MSK (0x00018000) + #define DDRCKECH1_CR_DDRCRCTLCONTROLS_EarlyWeakDrive_MAX (0x00000003) + #define DDRCKECH1_CR_DDRCRCTLCONTROLS_EarlyWeakDrive_DEF (0x00000000) + #define DDRCKECH1_CR_DDRCRCTLCONTROLS_CtlTxEq_OFF (17) + #define DDRCKECH1_CR_DDRCRCTLCONTROLS_CtlTxEq_WID ( 2) + #define DDRCKECH1_CR_DDRCRCTLCONTROLS_CtlTxEq_MSK (0x00060000) + #define DDRCKECH1_CR_DDRCRCTLCONTROLS_CtlTxEq_MAX (0x00000003) + #define DDRCKECH1_CR_DDRCRCTLCONTROLS_CtlTxEq_DEF (0x00000000) + #define DDRCKECH1_CR_DDRCRCTLCONTROLS_CtlSRDrv_OFF (19) + #define DDRCKECH1_CR_DDRCRCTLCONTROLS_CtlSRDrv_WID ( 2) + #define DDRCKECH1_CR_DDRCRCTLCONTROLS_CtlSRDrv_MSK (0x00180000) + #define DDRCKECH1_CR_DDRCRCTLCONTROLS_CtlSRDrv_MAX (0x00000003) + #define DDRCKECH1_CR_DDRCRCTLCONTROLS_CtlSRDrv_DEF (0x00000000) + #define DDRCKECH1_CR_DDRCRCTLCONTROLS_RxVref_OFF (21) + #define DDRCKECH1_CR_DDRCRCTLCONTROLS_RxVref_WID ( 6) + #define DDRCKECH1_CR_DDRCRCTLCONTROLS_RxVref_MSK (0x07E00000) + #define DDRCKECH1_CR_DDRCRCTLCONTROLS_RxVref_MAX (0x0000003F) + #define DDRCKECH1_CR_DDRCRCTLCONTROLS_RxVref_DEF (0x00000000) + #define DDRCKECH1_CR_DDRCRCTLCONTROLS_VccddqHi_OFF (27) + #define DDRCKECH1_CR_DDRCRCTLCONTROLS_VccddqHi_WID ( 1) + #define DDRCKECH1_CR_DDRCRCTLCONTROLS_VccddqHi_MSK (0x08000000) + #define DDRCKECH1_CR_DDRCRCTLCONTROLS_VccddqHi_MAX (0x00000001) + #define DDRCKECH1_CR_DDRCRCTLCONTROLS_VccddqHi_DEF (0x00000000) + #define DDRCKECH1_CR_DDRCRCTLCONTROLS_DllWeakLock_OFF (28) + #define DDRCKECH1_CR_DDRCRCTLCONTROLS_DllWeakLock_WID ( 1) + #define DDRCKECH1_CR_DDRCRCTLCONTROLS_DllWeakLock_MSK (0x10000000) + #define DDRCKECH1_CR_DDRCRCTLCONTROLS_DllWeakLock_MAX (0x00000001) + #define DDRCKECH1_CR_DDRCRCTLCONTROLS_DllWeakLock_DEF (0x00000000) + #define DDRCKECH1_CR_DDRCRCTLCONTROLS_LPDDR_Mode_OFF (29) + #define DDRCKECH1_CR_DDRCRCTLCONTROLS_LPDDR_Mode_WID ( 1) + #define DDRCKECH1_CR_DDRCRCTLCONTROLS_LPDDR_Mode_MSK (0x20000000) + #define DDRCKECH1_CR_DDRCRCTLCONTROLS_LPDDR_Mode_MAX (0x00000001) + #define DDRCKECH1_CR_DDRCRCTLCONTROLS_LPDDR_Mode_DEF (0x00000000) + #define DDRCKECH1_CR_DDRCRCTLCONTROLS_LaDrvEnOvrd_OFF (30) + #define DDRCKECH1_CR_DDRCRCTLCONTROLS_LaDrvEnOvrd_WID ( 1) + #define DDRCKECH1_CR_DDRCRCTLCONTROLS_LaDrvEnOvrd_MSK (0x40000000) + #define DDRCKECH1_CR_DDRCRCTLCONTROLS_LaDrvEnOvrd_MAX (0x00000001) + #define DDRCKECH1_CR_DDRCRCTLCONTROLS_LaDrvEnOvrd_DEF (0x00000000) + #define DDRCKECH1_CR_DDRCRCTLCONTROLS_LPDdrCAA_Dis_OFF (31) + #define DDRCKECH1_CR_DDRCRCTLCONTROLS_LPDdrCAA_Dis_WID ( 1) + #define DDRCKECH1_CR_DDRCRCTLCONTROLS_LPDdrCAA_Dis_MSK (0x80000000) + #define DDRCKECH1_CR_DDRCRCTLCONTROLS_LPDdrCAA_Dis_MAX (0x00000001) + #define DDRCKECH1_CR_DDRCRCTLCONTROLS_LPDdrCAA_Dis_DEF (0x00000000) + +#define DDRCKECH1_CR_DDRCRCTLRANKSUSED_REG (0x00001320) + #define DDRCKECH1_CR_DDRCRCTLRANKSUSED_RankEn_OFF ( 0) + #define DDRCKECH1_CR_DDRCRCTLRANKSUSED_RankEn_WID ( 4) + #define DDRCKECH1_CR_DDRCRCTLRANKSUSED_RankEn_MSK (0x0000000F) + #define DDRCKECH1_CR_DDRCRCTLRANKSUSED_RankEn_MAX (0x0000000F) + #define DDRCKECH1_CR_DDRCRCTLRANKSUSED_RankEn_DEF (0x0000000F) + #define DDRCKECH1_CR_DDRCRCTLRANKSUSED_OdtDisable_OFF ( 4) + #define DDRCKECH1_CR_DDRCRCTLRANKSUSED_OdtDisable_WID ( 2) + #define DDRCKECH1_CR_DDRCRCTLRANKSUSED_OdtDisable_MSK (0x00000030) + #define DDRCKECH1_CR_DDRCRCTLRANKSUSED_OdtDisable_MAX (0x00000003) + #define DDRCKECH1_CR_DDRCRCTLRANKSUSED_OdtDisable_DEF (0x00000000) + #define DDRCKECH1_CR_DDRCRCTLRANKSUSED_Spare_OFF ( 6) + #define DDRCKECH1_CR_DDRCRCTLRANKSUSED_Spare_WID (26) + #define DDRCKECH1_CR_DDRCRCTLRANKSUSED_Spare_MSK (0xFFFFFFC0) + #define DDRCKECH1_CR_DDRCRCTLRANKSUSED_Spare_MAX (0x03FFFFFF) + #define DDRCKECH1_CR_DDRCRCTLRANKSUSED_Spare_DEF (0x00000000) + +#define DDRCKECH1_CR_DLLPITESTANDADC_REG (0x00001324) + #define DDRCKECH1_CR_DLLPITESTANDADC_RunTest_OFF ( 0) + #define DDRCKECH1_CR_DLLPITESTANDADC_RunTest_WID ( 1) + #define DDRCKECH1_CR_DLLPITESTANDADC_RunTest_MSK (0x00000001) + #define DDRCKECH1_CR_DLLPITESTANDADC_RunTest_MAX (0x00000001) + #define DDRCKECH1_CR_DLLPITESTANDADC_RunTest_DEF (0x00000000) + #define DDRCKECH1_CR_DLLPITESTANDADC_Load_OFF ( 1) + #define DDRCKECH1_CR_DLLPITESTANDADC_Load_WID ( 1) + #define DDRCKECH1_CR_DLLPITESTANDADC_Load_MSK (0x00000002) + #define DDRCKECH1_CR_DLLPITESTANDADC_Load_MAX (0x00000001) + #define DDRCKECH1_CR_DLLPITESTANDADC_Load_DEF (0x00000000) + #define DDRCKECH1_CR_DLLPITESTANDADC_ModeHVM_OFF ( 2) + #define DDRCKECH1_CR_DLLPITESTANDADC_ModeHVM_WID ( 1) + #define DDRCKECH1_CR_DLLPITESTANDADC_ModeHVM_MSK (0x00000004) + #define DDRCKECH1_CR_DLLPITESTANDADC_ModeHVM_MAX (0x00000001) + #define DDRCKECH1_CR_DLLPITESTANDADC_ModeHVM_DEF (0x00000000) + #define DDRCKECH1_CR_DLLPITESTANDADC_ModeDV_OFF ( 3) + #define DDRCKECH1_CR_DLLPITESTANDADC_ModeDV_WID ( 1) + #define DDRCKECH1_CR_DLLPITESTANDADC_ModeDV_MSK (0x00000008) + #define DDRCKECH1_CR_DLLPITESTANDADC_ModeDV_MAX (0x00000001) + #define DDRCKECH1_CR_DLLPITESTANDADC_ModeDV_DEF (0x00000000) + #define DDRCKECH1_CR_DLLPITESTANDADC_ModeADC_OFF ( 4) + #define DDRCKECH1_CR_DLLPITESTANDADC_ModeADC_WID ( 1) + #define DDRCKECH1_CR_DLLPITESTANDADC_ModeADC_MSK (0x00000010) + #define DDRCKECH1_CR_DLLPITESTANDADC_ModeADC_MAX (0x00000001) + #define DDRCKECH1_CR_DLLPITESTANDADC_ModeADC_DEF (0x00000000) + #define DDRCKECH1_CR_DLLPITESTANDADC_LoadCount_OFF ( 5) + #define DDRCKECH1_CR_DLLPITESTANDADC_LoadCount_WID (10) + #define DDRCKECH1_CR_DLLPITESTANDADC_LoadCount_MSK (0x00007FE0) + #define DDRCKECH1_CR_DLLPITESTANDADC_LoadCount_MAX (0x000003FF) + #define DDRCKECH1_CR_DLLPITESTANDADC_CountStatus_OFF (15) + #define DDRCKECH1_CR_DLLPITESTANDADC_CountStatus_WID (10) + #define DDRCKECH1_CR_DLLPITESTANDADC_CountStatus_MSK (0x01FF8000) + #define DDRCKECH1_CR_DLLPITESTANDADC_CountStatus_MAX (0x000003FF) + #define DDRCKECH1_CR_DLLPITESTANDADC_CountStatus_DEF (0x00000000) + #define DDRCKECH1_CR_DLLPITESTANDADC_Spare_OFF (25) + #define DDRCKECH1_CR_DLLPITESTANDADC_Spare_WID ( 7) + #define DDRCKECH1_CR_DLLPITESTANDADC_Spare_MSK (0xFE000000) + #define DDRCKECH1_CR_DLLPITESTANDADC_Spare_MAX (0x0000007F) + +#define DDRCTLCH0_CR_DDRCRCTLCOMP_REG (0x00001C10) + #define DDRCTLCH0_CR_DDRCRCTLCOMP_Scomp_OFF ( 0) + #define DDRCTLCH0_CR_DDRCRCTLCOMP_Scomp_WID ( 6) + #define DDRCTLCH0_CR_DDRCRCTLCOMP_Scomp_MSK (0x0000003F) + #define DDRCTLCH0_CR_DDRCRCTLCOMP_Scomp_MAX (0x0000003F) + #define DDRCTLCH0_CR_DDRCRCTLCOMP_Scomp_DEF (0x00000000) + #define DDRCTLCH0_CR_DDRCRCTLCOMP_TcoComp_OFF ( 6) + #define DDRCTLCH0_CR_DDRCRCTLCOMP_TcoComp_WID ( 6) + #define DDRCTLCH0_CR_DDRCRCTLCOMP_TcoComp_MSK (0x00000FC0) + #define DDRCTLCH0_CR_DDRCRCTLCOMP_TcoComp_MAX (0x0000003F) + #define DDRCTLCH0_CR_DDRCRCTLCOMP_TcoComp_DEF (0x00000000) + #define DDRCTLCH0_CR_DDRCRCTLCOMP_RcompDrvUp_OFF (12) + #define DDRCTLCH0_CR_DDRCRCTLCOMP_RcompDrvUp_WID ( 6) + #define DDRCTLCH0_CR_DDRCRCTLCOMP_RcompDrvUp_MSK (0x0003F000) + #define DDRCTLCH0_CR_DDRCRCTLCOMP_RcompDrvUp_MAX (0x0000003F) + #define DDRCTLCH0_CR_DDRCRCTLCOMP_RcompDrvUp_DEF (0x00000000) + #define DDRCTLCH0_CR_DDRCRCTLCOMP_RcompDrvDown_OFF (18) + #define DDRCTLCH0_CR_DDRCRCTLCOMP_RcompDrvDown_WID ( 6) + #define DDRCTLCH0_CR_DDRCRCTLCOMP_RcompDrvDown_MSK (0x00FC0000) + #define DDRCTLCH0_CR_DDRCRCTLCOMP_RcompDrvDown_MAX (0x0000003F) + #define DDRCTLCH0_CR_DDRCRCTLCOMP_RcompDrvDown_DEF (0x00000000) + #define DDRCTLCH0_CR_DDRCRCTLCOMP_LsComp_OFF (24) + #define DDRCTLCH0_CR_DDRCRCTLCOMP_LsComp_WID ( 3) + #define DDRCTLCH0_CR_DDRCRCTLCOMP_LsComp_MSK (0x07000000) + #define DDRCTLCH0_CR_DDRCRCTLCOMP_LsComp_MAX (0x00000007) + #define DDRCTLCH0_CR_DDRCRCTLCOMP_LsComp_DEF (0x00000000) + #define DDRCTLCH0_CR_DDRCRCTLCOMP_Spare_OFF (27) + #define DDRCTLCH0_CR_DDRCRCTLCOMP_Spare_WID ( 5) + #define DDRCTLCH0_CR_DDRCRCTLCOMP_Spare_MSK (0xF8000000) + #define DDRCTLCH0_CR_DDRCRCTLCOMP_Spare_MAX (0x0000001F) + #define DDRCTLCH0_CR_DDRCRCTLCOMP_Spare_DEF (0x00000000) + +#define DDRCTLCH0_CR_DDRCRCTLCOMPOFFSET_REG (0x00001C14) + #define DDRCTLCH0_CR_DDRCRCTLCOMPOFFSET_ScompOffset_OFF ( 0) + #define DDRCTLCH0_CR_DDRCRCTLCOMPOFFSET_ScompOffset_WID ( 5) + #define DDRCTLCH0_CR_DDRCRCTLCOMPOFFSET_ScompOffset_MSK (0x0000001F) + #define DDRCTLCH0_CR_DDRCRCTLCOMPOFFSET_ScompOffset_MAX (0x0000001F) + #define DDRCTLCH0_CR_DDRCRCTLCOMPOFFSET_ScompOffset_DEF (0x00000000) + #define DDRCTLCH0_CR_DDRCRCTLCOMPOFFSET_TcoCompOffset_OFF ( 5) + #define DDRCTLCH0_CR_DDRCRCTLCOMPOFFSET_TcoCompOffset_WID ( 4) + #define DDRCTLCH0_CR_DDRCRCTLCOMPOFFSET_TcoCompOffset_MSK (0x000001E0) + #define DDRCTLCH0_CR_DDRCRCTLCOMPOFFSET_TcoCompOffset_MAX (0x0000000F) + #define DDRCTLCH0_CR_DDRCRCTLCOMPOFFSET_TcoCompOffset_DEF (0x00000000) + #define DDRCTLCH0_CR_DDRCRCTLCOMPOFFSET_RcompDrvUpOffset_OFF ( 9) + #define DDRCTLCH0_CR_DDRCRCTLCOMPOFFSET_RcompDrvUpOffset_WID ( 4) + #define DDRCTLCH0_CR_DDRCRCTLCOMPOFFSET_RcompDrvUpOffset_MSK (0x00001E00) + #define DDRCTLCH0_CR_DDRCRCTLCOMPOFFSET_RcompDrvUpOffset_MAX (0x0000000F) + #define DDRCTLCH0_CR_DDRCRCTLCOMPOFFSET_RcompDrvUpOffset_DEF (0x00000000) + #define DDRCTLCH0_CR_DDRCRCTLCOMPOFFSET_RcompDrvDownOffset_OFF (13) + #define DDRCTLCH0_CR_DDRCRCTLCOMPOFFSET_RcompDrvDownOffset_WID ( 4) + #define DDRCTLCH0_CR_DDRCRCTLCOMPOFFSET_RcompDrvDownOffset_MSK (0x0001E000) + #define DDRCTLCH0_CR_DDRCRCTLCOMPOFFSET_RcompDrvDownOffset_MAX (0x0000000F) + #define DDRCTLCH0_CR_DDRCRCTLCOMPOFFSET_RcompDrvDownOffset_DEF (0x00000000) + #define DDRCTLCH0_CR_DDRCRCTLCOMPOFFSET_Spare_OFF (17) + #define DDRCTLCH0_CR_DDRCRCTLCOMPOFFSET_Spare_WID (15) + #define DDRCTLCH0_CR_DDRCRCTLCOMPOFFSET_Spare_MSK (0xFFFE0000) + #define DDRCTLCH0_CR_DDRCRCTLCOMPOFFSET_Spare_MAX (0x00007FFF) + #define DDRCTLCH0_CR_DDRCRCTLCOMPOFFSET_Spare_DEF (0x00000000) + +#define DDRCTLCH0_CR_DDRCRCTLPICODING_REG (0x00001C18) + #define DDRCTLCH0_CR_DDRCRCTLPICODING_CtlPiCode0_OFF ( 0) + #define DDRCTLCH0_CR_DDRCRCTLPICODING_CtlPiCode0_WID ( 7) + #define DDRCTLCH0_CR_DDRCRCTLPICODING_CtlPiCode0_MSK (0x0000007F) + #define DDRCTLCH0_CR_DDRCRCTLPICODING_CtlPiCode0_MAX (0x0000007F) + #define DDRCTLCH0_CR_DDRCRCTLPICODING_CtlPiCode0_DEF (0x00000000) + #define DDRCTLCH0_CR_DDRCRCTLPICODING_CtlPiCode1_OFF ( 7) + #define DDRCTLCH0_CR_DDRCRCTLPICODING_CtlPiCode1_WID ( 7) + #define DDRCTLCH0_CR_DDRCRCTLPICODING_CtlPiCode1_MSK (0x00003F80) + #define DDRCTLCH0_CR_DDRCRCTLPICODING_CtlPiCode1_MAX (0x0000007F) + #define DDRCTLCH0_CR_DDRCRCTLPICODING_CtlPiCode1_DEF (0x00000000) + #define DDRCTLCH0_CR_DDRCRCTLPICODING_CtlPiCode2_OFF (14) + #define DDRCTLCH0_CR_DDRCRCTLPICODING_CtlPiCode2_WID ( 7) + #define DDRCTLCH0_CR_DDRCRCTLPICODING_CtlPiCode2_MSK (0x001FC000) + #define DDRCTLCH0_CR_DDRCRCTLPICODING_CtlPiCode2_MAX (0x0000007F) + #define DDRCTLCH0_CR_DDRCRCTLPICODING_CtlPiCode2_DEF (0x00000000) + #define DDRCTLCH0_CR_DDRCRCTLPICODING_CtlPiCode3_OFF (21) + #define DDRCTLCH0_CR_DDRCRCTLPICODING_CtlPiCode3_WID ( 7) + #define DDRCTLCH0_CR_DDRCRCTLPICODING_CtlPiCode3_MSK (0x0FE00000) + #define DDRCTLCH0_CR_DDRCRCTLPICODING_CtlPiCode3_MAX (0x0000007F) + #define DDRCTLCH0_CR_DDRCRCTLPICODING_CtlPiCode3_DEF (0x00000000) + #define DDRCTLCH0_CR_DDRCRCTLPICODING_CtlXoverEnable_OFF (28) + #define DDRCTLCH0_CR_DDRCRCTLPICODING_CtlXoverEnable_WID ( 1) + #define DDRCTLCH0_CR_DDRCRCTLPICODING_CtlXoverEnable_MSK (0x10000000) + #define DDRCTLCH0_CR_DDRCRCTLPICODING_CtlXoverEnable_MAX (0x00000001) + #define DDRCTLCH0_CR_DDRCRCTLPICODING_CtlXoverEnable_DEF (0x00000000) + #define DDRCTLCH0_CR_DDRCRCTLPICODING_Spare_OFF (29) + #define DDRCTLCH0_CR_DDRCRCTLPICODING_Spare_WID ( 3) + #define DDRCTLCH0_CR_DDRCRCTLPICODING_Spare_MSK (0xE0000000) + #define DDRCTLCH0_CR_DDRCRCTLPICODING_Spare_MAX (0x00000007) + #define DDRCTLCH0_CR_DDRCRCTLPICODING_Spare_DEF (0x00000000) + +#define DDRCTLCH0_CR_DDRCRCTLCONTROLS_REG (0x00001C1C) + #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_RefPi_OFF ( 0) + #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_RefPi_WID ( 4) + #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_RefPi_MSK (0x0000000F) + #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_RefPi_MAX (0x0000000F) + #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_RefPi_DEF (0x00000000) + #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_DllMask_OFF ( 4) + #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_DllMask_WID ( 2) + #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_DllMask_MSK (0x00000030) + #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_DllMask_MAX (0x00000003) + #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_DllMask_DEF (0x00000000) + #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_DllRsvd1_OFF ( 6) + #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_DllRsvd1_WID ( 1) + #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_DllRsvd1_MSK (0x00000040) + #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_DllRsvd1_MAX (0x00000001) + #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_DllRsvd1_DEF (0x00000000) + #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_TxOn_OFF ( 7) + #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_TxOn_WID ( 1) + #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_TxOn_MSK (0x00000080) + #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_TxOn_MAX (0x00000001) + #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_TxOn_DEF (0x00000000) + #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_IntClkOn_OFF ( 8) + #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_IntClkOn_WID ( 1) + #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_IntClkOn_MSK (0x00000100) + #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_IntClkOn_MAX (0x00000001) + #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_IntClkOn_DEF (0x00000000) + #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_RepClkOn_OFF ( 9) + #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_RepClkOn_WID ( 1) + #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_RepClkOn_MSK (0x00000200) + #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_RepClkOn_MAX (0x00000001) + #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_RepClkOn_DEF (0x00000000) + #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_IOLBCtl_OFF (10) + #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_IOLBCtl_WID ( 2) + #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_IOLBCtl_MSK (0x00000C00) + #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_IOLBCtl_MAX (0x00000003) + #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_IOLBCtl_DEF (0x00000000) + #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_OdtMode_OFF (12) + #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_OdtMode_WID ( 1) + #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_OdtMode_MSK (0x00001000) + #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_OdtMode_MAX (0x00000001) + #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_OdtMode_DEF (0x00000000) + #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_CmdTxEq_OFF (13) + #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_CmdTxEq_WID ( 2) + #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_CmdTxEq_MSK (0x00006000) + #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_CmdTxEq_MAX (0x00000003) + #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_CmdTxEq_DEF (0x00000000) + #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_EarlyWeakDrive_OFF (15) + #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_EarlyWeakDrive_WID ( 2) + #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_EarlyWeakDrive_MSK (0x00018000) + #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_EarlyWeakDrive_MAX (0x00000003) + #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_EarlyWeakDrive_DEF (0x00000000) + #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_CtlTxEq_OFF (17) + #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_CtlTxEq_WID ( 2) + #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_CtlTxEq_MSK (0x00060000) + #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_CtlTxEq_MAX (0x00000003) + #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_CtlTxEq_DEF (0x00000000) + #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_CtlSRDrv_OFF (19) + #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_CtlSRDrv_WID ( 2) + #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_CtlSRDrv_MSK (0x00180000) + #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_CtlSRDrv_MAX (0x00000003) + #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_CtlSRDrv_DEF (0x00000000) + #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_RxVref_OFF (21) + #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_RxVref_WID ( 6) + #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_RxVref_MSK (0x07E00000) + #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_RxVref_MAX (0x0000003F) + #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_RxVref_DEF (0x00000000) + #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_VccddqHi_OFF (27) + #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_VccddqHi_WID ( 1) + #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_VccddqHi_MSK (0x08000000) + #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_VccddqHi_MAX (0x00000001) + #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_VccddqHi_DEF (0x00000000) + #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_DllWeakLock_OFF (28) + #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_DllWeakLock_WID ( 1) + #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_DllWeakLock_MSK (0x10000000) + #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_DllWeakLock_MAX (0x00000001) + #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_DllWeakLock_DEF (0x00000000) + #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_LPDDR_Mode_OFF (29) + #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_LPDDR_Mode_WID ( 1) + #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_LPDDR_Mode_MSK (0x20000000) + #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_LPDDR_Mode_MAX (0x00000001) + #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_LPDDR_Mode_DEF (0x00000000) + #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_LaDrvEnOvrd_OFF (30) + #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_LaDrvEnOvrd_WID ( 1) + #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_LaDrvEnOvrd_MSK (0x40000000) + #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_LaDrvEnOvrd_MAX (0x00000001) + #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_LaDrvEnOvrd_DEF (0x00000000) + #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_LPDdrCAA_Dis_OFF (31) + #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_LPDdrCAA_Dis_WID ( 1) + #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_LPDdrCAA_Dis_MSK (0x80000000) + #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_LPDdrCAA_Dis_MAX (0x00000001) + #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_LPDdrCAA_Dis_DEF (0x00000000) + +#define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_REG (0x00001C20) + #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_RankEn_OFF ( 0) + #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_RankEn_WID ( 4) + #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_RankEn_MSK (0x0000000F) + #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_RankEn_MAX (0x0000000F) + #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_RankEn_DEF (0x0000000F) + #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_OdtDisable_OFF ( 4) + #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_OdtDisable_WID ( 2) + #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_OdtDisable_MSK (0x00000030) + #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_OdtDisable_MAX (0x00000003) + #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_OdtDisable_DEF (0x00000000) + #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_Spare_OFF ( 6) + #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_Spare_WID (26) + #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_Spare_MSK (0xFFFFFFC0) + #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_Spare_MAX (0x03FFFFFF) + #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_Spare_DEF (0x00000000) + +#define DDRCTLCH0_CR_DLLPITESTANDADC_REG (0x00001C24) + #define DDRCTLCH0_CR_DLLPITESTANDADC_RunTest_OFF ( 0) + #define DDRCTLCH0_CR_DLLPITESTANDADC_RunTest_WID ( 1) + #define DDRCTLCH0_CR_DLLPITESTANDADC_RunTest_MSK (0x00000001) + #define DDRCTLCH0_CR_DLLPITESTANDADC_RunTest_MAX (0x00000001) + #define DDRCTLCH0_CR_DLLPITESTANDADC_RunTest_DEF (0x00000000) + #define DDRCTLCH0_CR_DLLPITESTANDADC_Load_OFF ( 1) + #define DDRCTLCH0_CR_DLLPITESTANDADC_Load_WID ( 1) + #define DDRCTLCH0_CR_DLLPITESTANDADC_Load_MSK (0x00000002) + #define DDRCTLCH0_CR_DLLPITESTANDADC_Load_MAX (0x00000001) + #define DDRCTLCH0_CR_DLLPITESTANDADC_Load_DEF (0x00000000) + #define DDRCTLCH0_CR_DLLPITESTANDADC_ModeHVM_OFF ( 2) + #define DDRCTLCH0_CR_DLLPITESTANDADC_ModeHVM_WID ( 1) + #define DDRCTLCH0_CR_DLLPITESTANDADC_ModeHVM_MSK (0x00000004) + #define DDRCTLCH0_CR_DLLPITESTANDADC_ModeHVM_MAX (0x00000001) + #define DDRCTLCH0_CR_DLLPITESTANDADC_ModeHVM_DEF (0x00000000) + #define DDRCTLCH0_CR_DLLPITESTANDADC_ModeDV_OFF ( 3) + #define DDRCTLCH0_CR_DLLPITESTANDADC_ModeDV_WID ( 1) + #define DDRCTLCH0_CR_DLLPITESTANDADC_ModeDV_MSK (0x00000008) + #define DDRCTLCH0_CR_DLLPITESTANDADC_ModeDV_MAX (0x00000001) + #define DDRCTLCH0_CR_DLLPITESTANDADC_ModeDV_DEF (0x00000000) + #define DDRCTLCH0_CR_DLLPITESTANDADC_ModeADC_OFF ( 4) + #define DDRCTLCH0_CR_DLLPITESTANDADC_ModeADC_WID ( 1) + #define DDRCTLCH0_CR_DLLPITESTANDADC_ModeADC_MSK (0x00000010) + #define DDRCTLCH0_CR_DLLPITESTANDADC_ModeADC_MAX (0x00000001) + #define DDRCTLCH0_CR_DLLPITESTANDADC_ModeADC_DEF (0x00000000) + #define DDRCTLCH0_CR_DLLPITESTANDADC_LoadCount_OFF ( 5) + #define DDRCTLCH0_CR_DLLPITESTANDADC_LoadCount_WID (10) + #define DDRCTLCH0_CR_DLLPITESTANDADC_LoadCount_MSK (0x00007FE0) + #define DDRCTLCH0_CR_DLLPITESTANDADC_LoadCount_MAX (0x000003FF) + #define DDRCTLCH0_CR_DLLPITESTANDADC_CountStatus_OFF (15) + #define DDRCTLCH0_CR_DLLPITESTANDADC_CountStatus_WID (10) + #define DDRCTLCH0_CR_DLLPITESTANDADC_CountStatus_MSK (0x01FF8000) + #define DDRCTLCH0_CR_DLLPITESTANDADC_CountStatus_MAX (0x000003FF) + #define DDRCTLCH0_CR_DLLPITESTANDADC_CountStatus_DEF (0x00000000) + #define DDRCTLCH0_CR_DLLPITESTANDADC_Spare_OFF (25) + #define DDRCTLCH0_CR_DLLPITESTANDADC_Spare_WID ( 7) + #define DDRCTLCH0_CR_DLLPITESTANDADC_Spare_MSK (0xFE000000) + #define DDRCTLCH0_CR_DLLPITESTANDADC_Spare_MAX (0x0000007F) + +#define DDRCTLCH1_CR_DDRCRCTLCOMP_REG (0x00001D10) + #define DDRCTLCH1_CR_DDRCRCTLCOMP_Scomp_OFF ( 0) + #define DDRCTLCH1_CR_DDRCRCTLCOMP_Scomp_WID ( 6) + #define DDRCTLCH1_CR_DDRCRCTLCOMP_Scomp_MSK (0x0000003F) + #define DDRCTLCH1_CR_DDRCRCTLCOMP_Scomp_MAX (0x0000003F) + #define DDRCTLCH1_CR_DDRCRCTLCOMP_Scomp_DEF (0x00000000) + #define DDRCTLCH1_CR_DDRCRCTLCOMP_TcoComp_OFF ( 6) + #define DDRCTLCH1_CR_DDRCRCTLCOMP_TcoComp_WID ( 6) + #define DDRCTLCH1_CR_DDRCRCTLCOMP_TcoComp_MSK (0x00000FC0) + #define DDRCTLCH1_CR_DDRCRCTLCOMP_TcoComp_MAX (0x0000003F) + #define DDRCTLCH1_CR_DDRCRCTLCOMP_TcoComp_DEF (0x00000000) + #define DDRCTLCH1_CR_DDRCRCTLCOMP_RcompDrvUp_OFF (12) + #define DDRCTLCH1_CR_DDRCRCTLCOMP_RcompDrvUp_WID ( 6) + #define DDRCTLCH1_CR_DDRCRCTLCOMP_RcompDrvUp_MSK (0x0003F000) + #define DDRCTLCH1_CR_DDRCRCTLCOMP_RcompDrvUp_MAX (0x0000003F) + #define DDRCTLCH1_CR_DDRCRCTLCOMP_RcompDrvUp_DEF (0x00000000) + #define DDRCTLCH1_CR_DDRCRCTLCOMP_RcompDrvDown_OFF (18) + #define DDRCTLCH1_CR_DDRCRCTLCOMP_RcompDrvDown_WID ( 6) + #define DDRCTLCH1_CR_DDRCRCTLCOMP_RcompDrvDown_MSK (0x00FC0000) + #define DDRCTLCH1_CR_DDRCRCTLCOMP_RcompDrvDown_MAX (0x0000003F) + #define DDRCTLCH1_CR_DDRCRCTLCOMP_RcompDrvDown_DEF (0x00000000) + #define DDRCTLCH1_CR_DDRCRCTLCOMP_LsComp_OFF (24) + #define DDRCTLCH1_CR_DDRCRCTLCOMP_LsComp_WID ( 3) + #define DDRCTLCH1_CR_DDRCRCTLCOMP_LsComp_MSK (0x07000000) + #define DDRCTLCH1_CR_DDRCRCTLCOMP_LsComp_MAX (0x00000007) + #define DDRCTLCH1_CR_DDRCRCTLCOMP_LsComp_DEF (0x00000000) + #define DDRCTLCH1_CR_DDRCRCTLCOMP_Spare_OFF (27) + #define DDRCTLCH1_CR_DDRCRCTLCOMP_Spare_WID ( 5) + #define DDRCTLCH1_CR_DDRCRCTLCOMP_Spare_MSK (0xF8000000) + #define DDRCTLCH1_CR_DDRCRCTLCOMP_Spare_MAX (0x0000001F) + #define DDRCTLCH1_CR_DDRCRCTLCOMP_Spare_DEF (0x00000000) + +#define DDRCTLCH1_CR_DDRCRCTLCOMPOFFSET_REG (0x00001D14) + #define DDRCTLCH1_CR_DDRCRCTLCOMPOFFSET_ScompOffset_OFF ( 0) + #define DDRCTLCH1_CR_DDRCRCTLCOMPOFFSET_ScompOffset_WID ( 5) + #define DDRCTLCH1_CR_DDRCRCTLCOMPOFFSET_ScompOffset_MSK (0x0000001F) + #define DDRCTLCH1_CR_DDRCRCTLCOMPOFFSET_ScompOffset_MAX (0x0000001F) + #define DDRCTLCH1_CR_DDRCRCTLCOMPOFFSET_ScompOffset_DEF (0x00000000) + #define DDRCTLCH1_CR_DDRCRCTLCOMPOFFSET_TcoCompOffset_OFF ( 5) + #define DDRCTLCH1_CR_DDRCRCTLCOMPOFFSET_TcoCompOffset_WID ( 4) + #define DDRCTLCH1_CR_DDRCRCTLCOMPOFFSET_TcoCompOffset_MSK (0x000001E0) + #define DDRCTLCH1_CR_DDRCRCTLCOMPOFFSET_TcoCompOffset_MAX (0x0000000F) + #define DDRCTLCH1_CR_DDRCRCTLCOMPOFFSET_TcoCompOffset_DEF (0x00000000) + #define DDRCTLCH1_CR_DDRCRCTLCOMPOFFSET_RcompDrvUpOffset_OFF ( 9) + #define DDRCTLCH1_CR_DDRCRCTLCOMPOFFSET_RcompDrvUpOffset_WID ( 4) + #define DDRCTLCH1_CR_DDRCRCTLCOMPOFFSET_RcompDrvUpOffset_MSK (0x00001E00) + #define DDRCTLCH1_CR_DDRCRCTLCOMPOFFSET_RcompDrvUpOffset_MAX (0x0000000F) + #define DDRCTLCH1_CR_DDRCRCTLCOMPOFFSET_RcompDrvUpOffset_DEF (0x00000000) + #define DDRCTLCH1_CR_DDRCRCTLCOMPOFFSET_RcompDrvDownOffset_OFF (13) + #define DDRCTLCH1_CR_DDRCRCTLCOMPOFFSET_RcompDrvDownOffset_WID ( 4) + #define DDRCTLCH1_CR_DDRCRCTLCOMPOFFSET_RcompDrvDownOffset_MSK (0x0001E000) + #define DDRCTLCH1_CR_DDRCRCTLCOMPOFFSET_RcompDrvDownOffset_MAX (0x0000000F) + #define DDRCTLCH1_CR_DDRCRCTLCOMPOFFSET_RcompDrvDownOffset_DEF (0x00000000) + #define DDRCTLCH1_CR_DDRCRCTLCOMPOFFSET_Spare_OFF (17) + #define DDRCTLCH1_CR_DDRCRCTLCOMPOFFSET_Spare_WID (15) + #define DDRCTLCH1_CR_DDRCRCTLCOMPOFFSET_Spare_MSK (0xFFFE0000) + #define DDRCTLCH1_CR_DDRCRCTLCOMPOFFSET_Spare_MAX (0x00007FFF) + #define DDRCTLCH1_CR_DDRCRCTLCOMPOFFSET_Spare_DEF (0x00000000) + +#define DDRCTLCH1_CR_DDRCRCTLPICODING_REG (0x00001D18) + #define DDRCTLCH1_CR_DDRCRCTLPICODING_CtlPiCode0_OFF ( 0) + #define DDRCTLCH1_CR_DDRCRCTLPICODING_CtlPiCode0_WID ( 7) + #define DDRCTLCH1_CR_DDRCRCTLPICODING_CtlPiCode0_MSK (0x0000007F) + #define DDRCTLCH1_CR_DDRCRCTLPICODING_CtlPiCode0_MAX (0x0000007F) + #define DDRCTLCH1_CR_DDRCRCTLPICODING_CtlPiCode0_DEF (0x00000000) + #define DDRCTLCH1_CR_DDRCRCTLPICODING_CtlPiCode1_OFF ( 7) + #define DDRCTLCH1_CR_DDRCRCTLPICODING_CtlPiCode1_WID ( 7) + #define DDRCTLCH1_CR_DDRCRCTLPICODING_CtlPiCode1_MSK (0x00003F80) + #define DDRCTLCH1_CR_DDRCRCTLPICODING_CtlPiCode1_MAX (0x0000007F) + #define DDRCTLCH1_CR_DDRCRCTLPICODING_CtlPiCode1_DEF (0x00000000) + #define DDRCTLCH1_CR_DDRCRCTLPICODING_CtlPiCode2_OFF (14) + #define DDRCTLCH1_CR_DDRCRCTLPICODING_CtlPiCode2_WID ( 7) + #define DDRCTLCH1_CR_DDRCRCTLPICODING_CtlPiCode2_MSK (0x001FC000) + #define DDRCTLCH1_CR_DDRCRCTLPICODING_CtlPiCode2_MAX (0x0000007F) + #define DDRCTLCH1_CR_DDRCRCTLPICODING_CtlPiCode2_DEF (0x00000000) + #define DDRCTLCH1_CR_DDRCRCTLPICODING_CtlPiCode3_OFF (21) + #define DDRCTLCH1_CR_DDRCRCTLPICODING_CtlPiCode3_WID ( 7) + #define DDRCTLCH1_CR_DDRCRCTLPICODING_CtlPiCode3_MSK (0x0FE00000) + #define DDRCTLCH1_CR_DDRCRCTLPICODING_CtlPiCode3_MAX (0x0000007F) + #define DDRCTLCH1_CR_DDRCRCTLPICODING_CtlPiCode3_DEF (0x00000000) + #define DDRCTLCH1_CR_DDRCRCTLPICODING_CtlXoverEnable_OFF (28) + #define DDRCTLCH1_CR_DDRCRCTLPICODING_CtlXoverEnable_WID ( 1) + #define DDRCTLCH1_CR_DDRCRCTLPICODING_CtlXoverEnable_MSK (0x10000000) + #define DDRCTLCH1_CR_DDRCRCTLPICODING_CtlXoverEnable_MAX (0x00000001) + #define DDRCTLCH1_CR_DDRCRCTLPICODING_CtlXoverEnable_DEF (0x00000000) + #define DDRCTLCH1_CR_DDRCRCTLPICODING_Spare_OFF (29) + #define DDRCTLCH1_CR_DDRCRCTLPICODING_Spare_WID ( 3) + #define DDRCTLCH1_CR_DDRCRCTLPICODING_Spare_MSK (0xE0000000) + #define DDRCTLCH1_CR_DDRCRCTLPICODING_Spare_MAX (0x00000007) + #define DDRCTLCH1_CR_DDRCRCTLPICODING_Spare_DEF (0x00000000) + +#define DDRCTLCH1_CR_DDRCRCTLCONTROLS_REG (0x00001D1C) + #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_RefPi_OFF ( 0) + #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_RefPi_WID ( 4) + #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_RefPi_MSK (0x0000000F) + #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_RefPi_MAX (0x0000000F) + #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_RefPi_DEF (0x00000000) + #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_DllMask_OFF ( 4) + #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_DllMask_WID ( 2) + #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_DllMask_MSK (0x00000030) + #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_DllMask_MAX (0x00000003) + #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_DllMask_DEF (0x00000000) + #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_DllRsvd1_OFF ( 6) + #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_DllRsvd1_WID ( 1) + #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_DllRsvd1_MSK (0x00000040) + #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_DllRsvd1_MAX (0x00000001) + #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_DllRsvd1_DEF (0x00000000) + #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_TxOn_OFF ( 7) + #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_TxOn_WID ( 1) + #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_TxOn_MSK (0x00000080) + #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_TxOn_MAX (0x00000001) + #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_TxOn_DEF (0x00000000) + #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_IntClkOn_OFF ( 8) + #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_IntClkOn_WID ( 1) + #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_IntClkOn_MSK (0x00000100) + #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_IntClkOn_MAX (0x00000001) + #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_IntClkOn_DEF (0x00000000) + #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_RepClkOn_OFF ( 9) + #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_RepClkOn_WID ( 1) + #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_RepClkOn_MSK (0x00000200) + #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_RepClkOn_MAX (0x00000001) + #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_RepClkOn_DEF (0x00000000) + #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_IOLBCtl_OFF (10) + #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_IOLBCtl_WID ( 2) + #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_IOLBCtl_MSK (0x00000C00) + #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_IOLBCtl_MAX (0x00000003) + #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_IOLBCtl_DEF (0x00000000) + #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_OdtMode_OFF (12) + #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_OdtMode_WID ( 1) + #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_OdtMode_MSK (0x00001000) + #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_OdtMode_MAX (0x00000001) + #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_OdtMode_DEF (0x00000000) + #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_CmdTxEq_OFF (13) + #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_CmdTxEq_WID ( 2) + #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_CmdTxEq_MSK (0x00006000) + #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_CmdTxEq_MAX (0x00000003) + #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_CmdTxEq_DEF (0x00000000) + #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_EarlyWeakDrive_OFF (15) + #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_EarlyWeakDrive_WID ( 2) + #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_EarlyWeakDrive_MSK (0x00018000) + #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_EarlyWeakDrive_MAX (0x00000003) + #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_EarlyWeakDrive_DEF (0x00000000) + #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_CtlTxEq_OFF (17) + #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_CtlTxEq_WID ( 2) + #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_CtlTxEq_MSK (0x00060000) + #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_CtlTxEq_MAX (0x00000003) + #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_CtlTxEq_DEF (0x00000000) + #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_CtlSRDrv_OFF (19) + #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_CtlSRDrv_WID ( 2) + #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_CtlSRDrv_MSK (0x00180000) + #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_CtlSRDrv_MAX (0x00000003) + #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_CtlSRDrv_DEF (0x00000000) + #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_RxVref_OFF (21) + #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_RxVref_WID ( 6) + #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_RxVref_MSK (0x07E00000) + #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_RxVref_MAX (0x0000003F) + #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_RxVref_DEF (0x00000000) + #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_VccddqHi_OFF (27) + #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_VccddqHi_WID ( 1) + #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_VccddqHi_MSK (0x08000000) + #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_VccddqHi_MAX (0x00000001) + #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_VccddqHi_DEF (0x00000000) + #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_DllWeakLock_OFF (28) + #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_DllWeakLock_WID ( 1) + #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_DllWeakLock_MSK (0x10000000) + #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_DllWeakLock_MAX (0x00000001) + #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_DllWeakLock_DEF (0x00000000) + #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_LPDDR_Mode_OFF (29) + #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_LPDDR_Mode_WID ( 1) + #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_LPDDR_Mode_MSK (0x20000000) + #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_LPDDR_Mode_MAX (0x00000001) + #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_LPDDR_Mode_DEF (0x00000000) + #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_LaDrvEnOvrd_OFF (30) + #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_LaDrvEnOvrd_WID ( 1) + #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_LaDrvEnOvrd_MSK (0x40000000) + #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_LaDrvEnOvrd_MAX (0x00000001) + #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_LaDrvEnOvrd_DEF (0x00000000) + #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_LPDdrCAA_Dis_OFF (31) + #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_LPDdrCAA_Dis_WID ( 1) + #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_LPDdrCAA_Dis_MSK (0x80000000) + #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_LPDdrCAA_Dis_MAX (0x00000001) + #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_LPDdrCAA_Dis_DEF (0x00000000) + +#define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_REG (0x00001D20) + #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_RankEn_OFF ( 0) + #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_RankEn_WID ( 4) + #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_RankEn_MSK (0x0000000F) + #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_RankEn_MAX (0x0000000F) + #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_RankEn_DEF (0x0000000F) + #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_OdtDisable_OFF ( 4) + #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_OdtDisable_WID ( 2) + #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_OdtDisable_MSK (0x00000030) + #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_OdtDisable_MAX (0x00000003) + #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_OdtDisable_DEF (0x00000000) + #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_Spare_OFF ( 6) + #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_Spare_WID (26) + #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_Spare_MSK (0xFFFFFFC0) + #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_Spare_MAX (0x03FFFFFF) + #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_Spare_DEF (0x00000000) + +#define DDRCTLCH1_CR_DLLPITESTANDADC_REG (0x00001D24) + #define DDRCTLCH1_CR_DLLPITESTANDADC_RunTest_OFF ( 0) + #define DDRCTLCH1_CR_DLLPITESTANDADC_RunTest_WID ( 1) + #define DDRCTLCH1_CR_DLLPITESTANDADC_RunTest_MSK (0x00000001) + #define DDRCTLCH1_CR_DLLPITESTANDADC_RunTest_MAX (0x00000001) + #define DDRCTLCH1_CR_DLLPITESTANDADC_RunTest_DEF (0x00000000) + #define DDRCTLCH1_CR_DLLPITESTANDADC_Load_OFF ( 1) + #define DDRCTLCH1_CR_DLLPITESTANDADC_Load_WID ( 1) + #define DDRCTLCH1_CR_DLLPITESTANDADC_Load_MSK (0x00000002) + #define DDRCTLCH1_CR_DLLPITESTANDADC_Load_MAX (0x00000001) + #define DDRCTLCH1_CR_DLLPITESTANDADC_Load_DEF (0x00000000) + #define DDRCTLCH1_CR_DLLPITESTANDADC_ModeHVM_OFF ( 2) + #define DDRCTLCH1_CR_DLLPITESTANDADC_ModeHVM_WID ( 1) + #define DDRCTLCH1_CR_DLLPITESTANDADC_ModeHVM_MSK (0x00000004) + #define DDRCTLCH1_CR_DLLPITESTANDADC_ModeHVM_MAX (0x00000001) + #define DDRCTLCH1_CR_DLLPITESTANDADC_ModeHVM_DEF (0x00000000) + #define DDRCTLCH1_CR_DLLPITESTANDADC_ModeDV_OFF ( 3) + #define DDRCTLCH1_CR_DLLPITESTANDADC_ModeDV_WID ( 1) + #define DDRCTLCH1_CR_DLLPITESTANDADC_ModeDV_MSK (0x00000008) + #define DDRCTLCH1_CR_DLLPITESTANDADC_ModeDV_MAX (0x00000001) + #define DDRCTLCH1_CR_DLLPITESTANDADC_ModeDV_DEF (0x00000000) + #define DDRCTLCH1_CR_DLLPITESTANDADC_ModeADC_OFF ( 4) + #define DDRCTLCH1_CR_DLLPITESTANDADC_ModeADC_WID ( 1) + #define DDRCTLCH1_CR_DLLPITESTANDADC_ModeADC_MSK (0x00000010) + #define DDRCTLCH1_CR_DLLPITESTANDADC_ModeADC_MAX (0x00000001) + #define DDRCTLCH1_CR_DLLPITESTANDADC_ModeADC_DEF (0x00000000) + #define DDRCTLCH1_CR_DLLPITESTANDADC_LoadCount_OFF ( 5) + #define DDRCTLCH1_CR_DLLPITESTANDADC_LoadCount_WID (10) + #define DDRCTLCH1_CR_DLLPITESTANDADC_LoadCount_MSK (0x00007FE0) + #define DDRCTLCH1_CR_DLLPITESTANDADC_LoadCount_MAX (0x000003FF) + #define DDRCTLCH1_CR_DLLPITESTANDADC_CountStatus_OFF (15) + #define DDRCTLCH1_CR_DLLPITESTANDADC_CountStatus_WID (10) + #define DDRCTLCH1_CR_DLLPITESTANDADC_CountStatus_MSK (0x01FF8000) + #define DDRCTLCH1_CR_DLLPITESTANDADC_CountStatus_MAX (0x000003FF) + #define DDRCTLCH1_CR_DLLPITESTANDADC_CountStatus_DEF (0x00000000) + #define DDRCTLCH1_CR_DLLPITESTANDADC_Spare_OFF (25) + #define DDRCTLCH1_CR_DLLPITESTANDADC_Spare_WID ( 7) + #define DDRCTLCH1_CR_DLLPITESTANDADC_Spare_MSK (0xFE000000) + #define DDRCTLCH1_CR_DLLPITESTANDADC_Spare_MAX (0x0000007F) + +#pragma pack(pop) +#endif // __McIoCkeCtl_h__ diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcRegisters/McIoClk.h b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcRegisters/McIoClk.h new file mode 100644 index 0000000..a190ed0 --- /dev/null +++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcRegisters/McIoClk.h @@ -0,0 +1,988 @@ +/** @file + This file was automatically generated. Modify at your own risk. + +@copyright + Copyright (c) 2010 - 2012 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +**/ +#ifndef __McIoClk_h__ +#define __McIoClk_h__ + +#pragma pack(push, 1) +#include "MrcTypes.h" + +typedef union { + struct { + U32 RankEn : 4; // Bits 3:0 + U32 Spare : 28; // Bits 31:4 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRCLK_CR_DDRCRCLKRANKSUSED_STRUCT; + +typedef union { + struct { + U32 Scomp : 5; // Bits 4:0 + U32 TcoComp : 6; // Bits 10:5 + U32 RcompDrvUp : 6; // Bits 16:11 + U32 RcompDrvDown : 6; // Bits 22:17 + U32 LsComp : 3; // Bits 25:23 + U32 Spare : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRCLK_CR_DDRCRCLKCOMP_STRUCT; + +typedef union { + struct { + U32 ScompOffset : 4; // Bits 3:0 + U32 TcoCompOffset : 4; // Bits 7:4 + U32 RcompDrvUpOffset : 4; // Bits 11:8 + U32 RcompDrvDownOffset : 4; // Bits 15:12 + U32 Spare : 16; // Bits 31:16 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRCLK_CR_DDRCRCLKCOMPOFFSET_STRUCT; + +typedef union { + struct { + U32 PiSettingRank0 : 7; // Bits 6:0 + U32 PiSettingRank1 : 7; // Bits 13:7 + U32 PiSettingRank2 : 7; // Bits 20:14 + U32 PiSettingRank3 : 7; // Bits 27:21 + U32 Spare : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRCLK_CR_DDRCRCLKPICODE_STRUCT; + +typedef union { + struct { + U32 RefPi : 4; // Bits 3:0 + U32 DllMask : 2; // Bits 5:4 + U32 DllRsvd1 : 1; // Bits 6:6 + U32 TxOn : 1; // Bits 7:7 + U32 IntClkOn : 1; // Bits 8:8 + U32 RepClkOn : 1; // Bits 9:9 + U32 IOLBCtl : 2; // Bits 11:10 + U32 OdtMode : 1; // Bits 12:12 + U32 Reserved : 8; // Bits 20:13 + U32 RxVref : 6; // Bits 26:21 + U32 VccddqHi : 1; // Bits 27:27 + U32 DllWeakLock : 1; // Bits 28:28 + U32 LPDDR_Mode : 1; // Bits 29:29 + U32 Spare : 2; // Bits 31:30 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRCLK_CR_DDRCRCLKCONTROLS_STRUCT; + +typedef union { + struct { + U32 RunTest : 1; // Bits 0:0 + U32 Load : 1; // Bits 1:1 + U32 ModeHVM : 1; // Bits 2:2 + U32 ModeDV : 1; // Bits 3:3 + U32 ModeADC : 1; // Bits 4:4 + U32 LoadCount : 10; // Bits 14:5 + U32 CountStatus : 10; // Bits 24:15 + U32 Spare : 7; // Bits 31:25 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRCLK_CR_DLLPITESTANDADC_STRUCT; + +typedef union { + struct { + U32 DllCB : 2; // Bits 1:0 + U32 Spare : 30; // Bits 31:2 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRCLK_CR_DDRCBSTATUS_STRUCT; + +typedef union { + struct { + U32 RankEn : 4; // Bits 3:0 + U32 Spare : 28; // Bits 31:4 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRCLKCH0_CR_DDRCRCLKRANKSUSED_STRUCT; + +typedef union { + struct { + U32 Scomp : 5; // Bits 4:0 + U32 TcoComp : 6; // Bits 10:5 + U32 RcompDrvUp : 6; // Bits 16:11 + U32 RcompDrvDown : 6; // Bits 22:17 + U32 LsComp : 3; // Bits 25:23 + U32 Spare : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRCLKCH0_CR_DDRCRCLKCOMP_STRUCT; + +typedef union { + struct { + U32 ScompOffset : 4; // Bits 3:0 + U32 TcoCompOffset : 4; // Bits 7:4 + U32 RcompDrvUpOffset : 4; // Bits 11:8 + U32 RcompDrvDownOffset : 4; // Bits 15:12 + U32 Spare : 16; // Bits 31:16 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRCLKCH0_CR_DDRCRCLKCOMPOFFSET_STRUCT; + +typedef union { + struct { + U32 PiSettingRank0 : 7; // Bits 6:0 + U32 PiSettingRank1 : 7; // Bits 13:7 + U32 PiSettingRank2 : 7; // Bits 20:14 + U32 PiSettingRank3 : 7; // Bits 27:21 + U32 Spare : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRCLKCH0_CR_DDRCRCLKPICODE_STRUCT; + +typedef union { + struct { + U32 RefPi : 4; // Bits 3:0 + U32 DllMask : 2; // Bits 5:4 + U32 DllRsvd1 : 1; // Bits 6:6 + U32 TxOn : 1; // Bits 7:7 + U32 IntClkOn : 1; // Bits 8:8 + U32 RepClkOn : 1; // Bits 9:9 + U32 IOLBCtl : 2; // Bits 11:10 + U32 OdtMode : 1; // Bits 12:12 + U32 Reserved : 8; // Bits 20:13 + U32 RxVref : 6; // Bits 26:21 + U32 VccddqHi : 1; // Bits 27:27 + U32 DllWeakLock : 1; // Bits 28:28 + U32 LPDDR_Mode : 1; // Bits 29:29 + U32 Spare : 2; // Bits 31:30 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRCLKCH0_CR_DDRCRCLKCONTROLS_STRUCT; + +typedef union { + struct { + U32 RunTest : 1; // Bits 0:0 + U32 Load : 1; // Bits 1:1 + U32 ModeHVM : 1; // Bits 2:2 + U32 ModeDV : 1; // Bits 3:3 + U32 ModeADC : 1; // Bits 4:4 + U32 LoadCount : 10; // Bits 14:5 + U32 CountStatus : 10; // Bits 24:15 + U32 Spare : 7; // Bits 31:25 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRCLKCH0_CR_DLLPITESTANDADC_STRUCT; + +typedef union { + struct { + U32 DllCB : 2; // Bits 1:0 + U32 Spare : 30; // Bits 31:2 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRCLKCH0_CR_DDRCBSTATUS_STRUCT; + +typedef union { + struct { + U32 RankEn : 4; // Bits 3:0 + U32 Spare : 28; // Bits 31:4 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRCLKCH1_CR_DDRCRCLKRANKSUSED_STRUCT; + +typedef union { + struct { + U32 Scomp : 5; // Bits 4:0 + U32 TcoComp : 6; // Bits 10:5 + U32 RcompDrvUp : 6; // Bits 16:11 + U32 RcompDrvDown : 6; // Bits 22:17 + U32 LsComp : 3; // Bits 25:23 + U32 Spare : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRCLKCH1_CR_DDRCRCLKCOMP_STRUCT; + +typedef union { + struct { + U32 ScompOffset : 4; // Bits 3:0 + U32 TcoCompOffset : 4; // Bits 7:4 + U32 RcompDrvUpOffset : 4; // Bits 11:8 + U32 RcompDrvDownOffset : 4; // Bits 15:12 + U32 Spare : 16; // Bits 31:16 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRCLKCH1_CR_DDRCRCLKCOMPOFFSET_STRUCT; + +typedef union { + struct { + U32 PiSettingRank0 : 7; // Bits 6:0 + U32 PiSettingRank1 : 7; // Bits 13:7 + U32 PiSettingRank2 : 7; // Bits 20:14 + U32 PiSettingRank3 : 7; // Bits 27:21 + U32 Spare : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRCLKCH1_CR_DDRCRCLKPICODE_STRUCT; + +typedef union { + struct { + U32 RefPi : 4; // Bits 3:0 + U32 DllMask : 2; // Bits 5:4 + U32 DllRsvd1 : 1; // Bits 6:6 + U32 TxOn : 1; // Bits 7:7 + U32 IntClkOn : 1; // Bits 8:8 + U32 RepClkOn : 1; // Bits 9:9 + U32 IOLBCtl : 2; // Bits 11:10 + U32 OdtMode : 1; // Bits 12:12 + U32 Reserved : 8; // Bits 20:13 + U32 RxVref : 6; // Bits 26:21 + U32 VccddqHi : 1; // Bits 27:27 + U32 DllWeakLock : 1; // Bits 28:28 + U32 LPDDR_Mode : 1; // Bits 29:29 + U32 Spare : 2; // Bits 31:30 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRCLKCH1_CR_DDRCRCLKCONTROLS_STRUCT; + +typedef union { + struct { + U32 RunTest : 1; // Bits 0:0 + U32 Load : 1; // Bits 1:1 + U32 ModeHVM : 1; // Bits 2:2 + U32 ModeDV : 1; // Bits 3:3 + U32 ModeADC : 1; // Bits 4:4 + U32 LoadCount : 10; // Bits 14:5 + U32 CountStatus : 10; // Bits 24:15 + U32 Spare : 7; // Bits 31:25 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRCLKCH1_CR_DLLPITESTANDADC_STRUCT; + +typedef union { + struct { + U32 DllCB : 2; // Bits 1:0 + U32 Spare : 30; // Bits 31:2 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRCLKCH1_CR_DDRCBSTATUS_STRUCT; + +#define DDRCLK_CR_DDRCRCLKRANKSUSED_REG (0x00003900) + #define DDRCLK_CR_DDRCRCLKRANKSUSED_RankEn_OFF ( 0) + #define DDRCLK_CR_DDRCRCLKRANKSUSED_RankEn_WID ( 4) + #define DDRCLK_CR_DDRCRCLKRANKSUSED_RankEn_MSK (0x0000000F) + #define DDRCLK_CR_DDRCRCLKRANKSUSED_RankEn_MAX (0x0000000F) + #define DDRCLK_CR_DDRCRCLKRANKSUSED_RankEn_DEF (0x0000000F) + #define DDRCLK_CR_DDRCRCLKRANKSUSED_Spare_OFF ( 4) + #define DDRCLK_CR_DDRCRCLKRANKSUSED_Spare_WID (28) + #define DDRCLK_CR_DDRCRCLKRANKSUSED_Spare_MSK (0xFFFFFFF0) + #define DDRCLK_CR_DDRCRCLKRANKSUSED_Spare_MAX (0x0FFFFFFF) + #define DDRCLK_CR_DDRCRCLKRANKSUSED_Spare_DEF (0x00000000) + +#define DDRCLK_CR_DDRCRCLKCOMP_REG (0x00003904) + #define DDRCLK_CR_DDRCRCLKCOMP_Scomp_OFF ( 0) + #define DDRCLK_CR_DDRCRCLKCOMP_Scomp_WID ( 5) + #define DDRCLK_CR_DDRCRCLKCOMP_Scomp_MSK (0x0000001F) + #define DDRCLK_CR_DDRCRCLKCOMP_Scomp_MAX (0x0000001F) + #define DDRCLK_CR_DDRCRCLKCOMP_Scomp_DEF (0x00000000) + #define DDRCLK_CR_DDRCRCLKCOMP_TcoComp_OFF ( 5) + #define DDRCLK_CR_DDRCRCLKCOMP_TcoComp_WID ( 6) + #define DDRCLK_CR_DDRCRCLKCOMP_TcoComp_MSK (0x000007E0) + #define DDRCLK_CR_DDRCRCLKCOMP_TcoComp_MAX (0x0000003F) + #define DDRCLK_CR_DDRCRCLKCOMP_TcoComp_DEF (0x00000000) + #define DDRCLK_CR_DDRCRCLKCOMP_RcompDrvUp_OFF (11) + #define DDRCLK_CR_DDRCRCLKCOMP_RcompDrvUp_WID ( 6) + #define DDRCLK_CR_DDRCRCLKCOMP_RcompDrvUp_MSK (0x0001F800) + #define DDRCLK_CR_DDRCRCLKCOMP_RcompDrvUp_MAX (0x0000003F) + #define DDRCLK_CR_DDRCRCLKCOMP_RcompDrvUp_DEF (0x00000000) + #define DDRCLK_CR_DDRCRCLKCOMP_RcompDrvDown_OFF (17) + #define DDRCLK_CR_DDRCRCLKCOMP_RcompDrvDown_WID ( 6) + #define DDRCLK_CR_DDRCRCLKCOMP_RcompDrvDown_MSK (0x007E0000) + #define DDRCLK_CR_DDRCRCLKCOMP_RcompDrvDown_MAX (0x0000003F) + #define DDRCLK_CR_DDRCRCLKCOMP_RcompDrvDown_DEF (0x00000000) + #define DDRCLK_CR_DDRCRCLKCOMP_LsComp_OFF (23) + #define DDRCLK_CR_DDRCRCLKCOMP_LsComp_WID ( 3) + #define DDRCLK_CR_DDRCRCLKCOMP_LsComp_MSK (0x03800000) + #define DDRCLK_CR_DDRCRCLKCOMP_LsComp_MAX (0x00000007) + #define DDRCLK_CR_DDRCRCLKCOMP_LsComp_DEF (0x00000004) + #define DDRCLK_CR_DDRCRCLKCOMP_Spare_OFF (26) + #define DDRCLK_CR_DDRCRCLKCOMP_Spare_WID ( 6) + #define DDRCLK_CR_DDRCRCLKCOMP_Spare_MSK (0xFC000000) + #define DDRCLK_CR_DDRCRCLKCOMP_Spare_MAX (0x0000003F) + #define DDRCLK_CR_DDRCRCLKCOMP_Spare_DEF (0x00000000) + +#define DDRCLK_CR_DDRCRCLKCOMPOFFSET_REG (0x00003908) + #define DDRCLK_CR_DDRCRCLKCOMPOFFSET_ScompOffset_OFF ( 0) + #define DDRCLK_CR_DDRCRCLKCOMPOFFSET_ScompOffset_WID ( 4) + #define DDRCLK_CR_DDRCRCLKCOMPOFFSET_ScompOffset_MSK (0x0000000F) + #define DDRCLK_CR_DDRCRCLKCOMPOFFSET_ScompOffset_MAX (0x0000000F) + #define DDRCLK_CR_DDRCRCLKCOMPOFFSET_ScompOffset_DEF (0x00000000) + #define DDRCLK_CR_DDRCRCLKCOMPOFFSET_TcoCompOffset_OFF ( 4) + #define DDRCLK_CR_DDRCRCLKCOMPOFFSET_TcoCompOffset_WID ( 4) + #define DDRCLK_CR_DDRCRCLKCOMPOFFSET_TcoCompOffset_MSK (0x000000F0) + #define DDRCLK_CR_DDRCRCLKCOMPOFFSET_TcoCompOffset_MAX (0x0000000F) + #define DDRCLK_CR_DDRCRCLKCOMPOFFSET_TcoCompOffset_DEF (0x00000000) + #define DDRCLK_CR_DDRCRCLKCOMPOFFSET_RcompDrvUpOffset_OFF ( 8) + #define DDRCLK_CR_DDRCRCLKCOMPOFFSET_RcompDrvUpOffset_WID ( 4) + #define DDRCLK_CR_DDRCRCLKCOMPOFFSET_RcompDrvUpOffset_MSK (0x00000F00) + #define DDRCLK_CR_DDRCRCLKCOMPOFFSET_RcompDrvUpOffset_MAX (0x0000000F) + #define DDRCLK_CR_DDRCRCLKCOMPOFFSET_RcompDrvUpOffset_DEF (0x00000000) + #define DDRCLK_CR_DDRCRCLKCOMPOFFSET_RcompDrvDownOffset_OFF (12) + #define DDRCLK_CR_DDRCRCLKCOMPOFFSET_RcompDrvDownOffset_WID ( 4) + #define DDRCLK_CR_DDRCRCLKCOMPOFFSET_RcompDrvDownOffset_MSK (0x0000F000) + #define DDRCLK_CR_DDRCRCLKCOMPOFFSET_RcompDrvDownOffset_MAX (0x0000000F) + #define DDRCLK_CR_DDRCRCLKCOMPOFFSET_RcompDrvDownOffset_DEF (0x00000000) + #define DDRCLK_CR_DDRCRCLKCOMPOFFSET_Spare_OFF (16) + #define DDRCLK_CR_DDRCRCLKCOMPOFFSET_Spare_WID (16) + #define DDRCLK_CR_DDRCRCLKCOMPOFFSET_Spare_MSK (0xFFFF0000) + #define DDRCLK_CR_DDRCRCLKCOMPOFFSET_Spare_MAX (0x0000FFFF) + #define DDRCLK_CR_DDRCRCLKCOMPOFFSET_Spare_DEF (0x00000000) + +#define DDRCLK_CR_DDRCRCLKPICODE_REG (0x0000390C) + #define DDRCLK_CR_DDRCRCLKPICODE_PiSettingRank0_OFF ( 0) + #define DDRCLK_CR_DDRCRCLKPICODE_PiSettingRank0_WID ( 7) + #define DDRCLK_CR_DDRCRCLKPICODE_PiSettingRank0_MSK (0x0000007F) + #define DDRCLK_CR_DDRCRCLKPICODE_PiSettingRank0_MAX (0x0000007F) + #define DDRCLK_CR_DDRCRCLKPICODE_PiSettingRank0_DEF (0x00000000) + #define DDRCLK_CR_DDRCRCLKPICODE_PiSettingRank1_OFF ( 7) + #define DDRCLK_CR_DDRCRCLKPICODE_PiSettingRank1_WID ( 7) + #define DDRCLK_CR_DDRCRCLKPICODE_PiSettingRank1_MSK (0x00003F80) + #define DDRCLK_CR_DDRCRCLKPICODE_PiSettingRank1_MAX (0x0000007F) + #define DDRCLK_CR_DDRCRCLKPICODE_PiSettingRank1_DEF (0x00000000) + #define DDRCLK_CR_DDRCRCLKPICODE_PiSettingRank2_OFF (14) + #define DDRCLK_CR_DDRCRCLKPICODE_PiSettingRank2_WID ( 7) + #define DDRCLK_CR_DDRCRCLKPICODE_PiSettingRank2_MSK (0x001FC000) + #define DDRCLK_CR_DDRCRCLKPICODE_PiSettingRank2_MAX (0x0000007F) + #define DDRCLK_CR_DDRCRCLKPICODE_PiSettingRank2_DEF (0x00000000) + #define DDRCLK_CR_DDRCRCLKPICODE_PiSettingRank3_OFF (21) + #define DDRCLK_CR_DDRCRCLKPICODE_PiSettingRank3_WID ( 7) + #define DDRCLK_CR_DDRCRCLKPICODE_PiSettingRank3_MSK (0x0FE00000) + #define DDRCLK_CR_DDRCRCLKPICODE_PiSettingRank3_MAX (0x0000007F) + #define DDRCLK_CR_DDRCRCLKPICODE_PiSettingRank3_DEF (0x00000000) + #define DDRCLK_CR_DDRCRCLKPICODE_Spare_OFF (28) + #define DDRCLK_CR_DDRCRCLKPICODE_Spare_WID ( 4) + #define DDRCLK_CR_DDRCRCLKPICODE_Spare_MSK (0xF0000000) + #define DDRCLK_CR_DDRCRCLKPICODE_Spare_MAX (0x0000000F) + #define DDRCLK_CR_DDRCRCLKPICODE_Spare_DEF (0x00000000) + +#define DDRCLK_CR_DDRCRCLKCONTROLS_REG (0x00003910) + #define DDRCLK_CR_DDRCRCLKCONTROLS_RefPi_OFF ( 0) + #define DDRCLK_CR_DDRCRCLKCONTROLS_RefPi_WID ( 4) + #define DDRCLK_CR_DDRCRCLKCONTROLS_RefPi_MSK (0x0000000F) + #define DDRCLK_CR_DDRCRCLKCONTROLS_RefPi_MAX (0x0000000F) + #define DDRCLK_CR_DDRCRCLKCONTROLS_RefPi_DEF (0x00000000) + #define DDRCLK_CR_DDRCRCLKCONTROLS_DllMask_OFF ( 4) + #define DDRCLK_CR_DDRCRCLKCONTROLS_DllMask_WID ( 2) + #define DDRCLK_CR_DDRCRCLKCONTROLS_DllMask_MSK (0x00000030) + #define DDRCLK_CR_DDRCRCLKCONTROLS_DllMask_MAX (0x00000003) + #define DDRCLK_CR_DDRCRCLKCONTROLS_DllMask_DEF (0x00000000) + #define DDRCLK_CR_DDRCRCLKCONTROLS_DllRsvd1_OFF ( 6) + #define DDRCLK_CR_DDRCRCLKCONTROLS_DllRsvd1_WID ( 1) + #define DDRCLK_CR_DDRCRCLKCONTROLS_DllRsvd1_MSK (0x00000040) + #define DDRCLK_CR_DDRCRCLKCONTROLS_DllRsvd1_MAX (0x00000001) + #define DDRCLK_CR_DDRCRCLKCONTROLS_DllRsvd1_DEF (0x00000000) + #define DDRCLK_CR_DDRCRCLKCONTROLS_TxOn_OFF ( 7) + #define DDRCLK_CR_DDRCRCLKCONTROLS_TxOn_WID ( 1) + #define DDRCLK_CR_DDRCRCLKCONTROLS_TxOn_MSK (0x00000080) + #define DDRCLK_CR_DDRCRCLKCONTROLS_TxOn_MAX (0x00000001) + #define DDRCLK_CR_DDRCRCLKCONTROLS_TxOn_DEF (0x00000000) + #define DDRCLK_CR_DDRCRCLKCONTROLS_IntClkOn_OFF ( 8) + #define DDRCLK_CR_DDRCRCLKCONTROLS_IntClkOn_WID ( 1) + #define DDRCLK_CR_DDRCRCLKCONTROLS_IntClkOn_MSK (0x00000100) + #define DDRCLK_CR_DDRCRCLKCONTROLS_IntClkOn_MAX (0x00000001) + #define DDRCLK_CR_DDRCRCLKCONTROLS_IntClkOn_DEF (0x00000000) + #define DDRCLK_CR_DDRCRCLKCONTROLS_RepClkOn_OFF ( 9) + #define DDRCLK_CR_DDRCRCLKCONTROLS_RepClkOn_WID ( 1) + #define DDRCLK_CR_DDRCRCLKCONTROLS_RepClkOn_MSK (0x00000200) + #define DDRCLK_CR_DDRCRCLKCONTROLS_RepClkOn_MAX (0x00000001) + #define DDRCLK_CR_DDRCRCLKCONTROLS_RepClkOn_DEF (0x00000000) + #define DDRCLK_CR_DDRCRCLKCONTROLS_IOLBCtl_OFF (10) + #define DDRCLK_CR_DDRCRCLKCONTROLS_IOLBCtl_WID ( 2) + #define DDRCLK_CR_DDRCRCLKCONTROLS_IOLBCtl_MSK (0x00000C00) + #define DDRCLK_CR_DDRCRCLKCONTROLS_IOLBCtl_MAX (0x00000003) + #define DDRCLK_CR_DDRCRCLKCONTROLS_IOLBCtl_DEF (0x00000000) + #define DDRCLK_CR_DDRCRCLKCONTROLS_OdtMode_OFF (12) + #define DDRCLK_CR_DDRCRCLKCONTROLS_OdtMode_WID ( 1) + #define DDRCLK_CR_DDRCRCLKCONTROLS_OdtMode_MSK (0x00001000) + #define DDRCLK_CR_DDRCRCLKCONTROLS_OdtMode_MAX (0x00000001) + #define DDRCLK_CR_DDRCRCLKCONTROLS_OdtMode_DEF (0x00000000) + #define DDRCLK_CR_DDRCRCLKCONTROLS_Reserved_OFF (13) + #define DDRCLK_CR_DDRCRCLKCONTROLS_Reserved_WID ( 8) + #define DDRCLK_CR_DDRCRCLKCONTROLS_Reserved_MSK (0x001FE000) + #define DDRCLK_CR_DDRCRCLKCONTROLS_Reserved_MAX (0x000000FF) + #define DDRCLK_CR_DDRCRCLKCONTROLS_Reserved_DEF (0x00000000) + #define DDRCLK_CR_DDRCRCLKCONTROLS_RxVref_OFF (21) + #define DDRCLK_CR_DDRCRCLKCONTROLS_RxVref_WID ( 6) + #define DDRCLK_CR_DDRCRCLKCONTROLS_RxVref_MSK (0x07E00000) + #define DDRCLK_CR_DDRCRCLKCONTROLS_RxVref_MAX (0x0000003F) + #define DDRCLK_CR_DDRCRCLKCONTROLS_RxVref_DEF (0x00000000) + #define DDRCLK_CR_DDRCRCLKCONTROLS_VccddqHi_OFF (27) + #define DDRCLK_CR_DDRCRCLKCONTROLS_VccddqHi_WID ( 1) + #define DDRCLK_CR_DDRCRCLKCONTROLS_VccddqHi_MSK (0x08000000) + #define DDRCLK_CR_DDRCRCLKCONTROLS_VccddqHi_MAX (0x00000001) + #define DDRCLK_CR_DDRCRCLKCONTROLS_VccddqHi_DEF (0x00000000) + #define DDRCLK_CR_DDRCRCLKCONTROLS_DllWeakLock_OFF (28) + #define DDRCLK_CR_DDRCRCLKCONTROLS_DllWeakLock_WID ( 1) + #define DDRCLK_CR_DDRCRCLKCONTROLS_DllWeakLock_MSK (0x10000000) + #define DDRCLK_CR_DDRCRCLKCONTROLS_DllWeakLock_MAX (0x00000001) + #define DDRCLK_CR_DDRCRCLKCONTROLS_DllWeakLock_DEF (0x00000000) + #define DDRCLK_CR_DDRCRCLKCONTROLS_LPDDR_Mode_OFF (29) + #define DDRCLK_CR_DDRCRCLKCONTROLS_LPDDR_Mode_WID ( 1) + #define DDRCLK_CR_DDRCRCLKCONTROLS_LPDDR_Mode_MSK (0x20000000) + #define DDRCLK_CR_DDRCRCLKCONTROLS_LPDDR_Mode_MAX (0x00000001) + #define DDRCLK_CR_DDRCRCLKCONTROLS_LPDDR_Mode_DEF (0x00000000) + #define DDRCLK_CR_DDRCRCLKCONTROLS_Spare_OFF (30) + #define DDRCLK_CR_DDRCRCLKCONTROLS_Spare_WID ( 2) + #define DDRCLK_CR_DDRCRCLKCONTROLS_Spare_MSK (0xC0000000) + #define DDRCLK_CR_DDRCRCLKCONTROLS_Spare_MAX (0x00000003) + #define DDRCLK_CR_DDRCRCLKCONTROLS_Spare_DEF (0x00000000) + +#define DDRCLK_CR_DLLPITESTANDADC_REG (0x00003914) + #define DDRCLK_CR_DLLPITESTANDADC_RunTest_OFF ( 0) + #define DDRCLK_CR_DLLPITESTANDADC_RunTest_WID ( 1) + #define DDRCLK_CR_DLLPITESTANDADC_RunTest_MSK (0x00000001) + #define DDRCLK_CR_DLLPITESTANDADC_RunTest_MAX (0x00000001) + #define DDRCLK_CR_DLLPITESTANDADC_RunTest_DEF (0x00000000) + #define DDRCLK_CR_DLLPITESTANDADC_Load_OFF ( 1) + #define DDRCLK_CR_DLLPITESTANDADC_Load_WID ( 1) + #define DDRCLK_CR_DLLPITESTANDADC_Load_MSK (0x00000002) + #define DDRCLK_CR_DLLPITESTANDADC_Load_MAX (0x00000001) + #define DDRCLK_CR_DLLPITESTANDADC_Load_DEF (0x00000000) + #define DDRCLK_CR_DLLPITESTANDADC_ModeHVM_OFF ( 2) + #define DDRCLK_CR_DLLPITESTANDADC_ModeHVM_WID ( 1) + #define DDRCLK_CR_DLLPITESTANDADC_ModeHVM_MSK (0x00000004) + #define DDRCLK_CR_DLLPITESTANDADC_ModeHVM_MAX (0x00000001) + #define DDRCLK_CR_DLLPITESTANDADC_ModeHVM_DEF (0x00000000) + #define DDRCLK_CR_DLLPITESTANDADC_ModeDV_OFF ( 3) + #define DDRCLK_CR_DLLPITESTANDADC_ModeDV_WID ( 1) + #define DDRCLK_CR_DLLPITESTANDADC_ModeDV_MSK (0x00000008) + #define DDRCLK_CR_DLLPITESTANDADC_ModeDV_MAX (0x00000001) + #define DDRCLK_CR_DLLPITESTANDADC_ModeDV_DEF (0x00000000) + #define DDRCLK_CR_DLLPITESTANDADC_ModeADC_OFF ( 4) + #define DDRCLK_CR_DLLPITESTANDADC_ModeADC_WID ( 1) + #define DDRCLK_CR_DLLPITESTANDADC_ModeADC_MSK (0x00000010) + #define DDRCLK_CR_DLLPITESTANDADC_ModeADC_MAX (0x00000001) + #define DDRCLK_CR_DLLPITESTANDADC_ModeADC_DEF (0x00000000) + #define DDRCLK_CR_DLLPITESTANDADC_LoadCount_OFF ( 5) + #define DDRCLK_CR_DLLPITESTANDADC_LoadCount_WID (10) + #define DDRCLK_CR_DLLPITESTANDADC_LoadCount_MSK (0x00007FE0) + #define DDRCLK_CR_DLLPITESTANDADC_LoadCount_MAX (0x000003FF) + #define DDRCLK_CR_DLLPITESTANDADC_CountStatus_OFF (15) + #define DDRCLK_CR_DLLPITESTANDADC_CountStatus_WID (10) + #define DDRCLK_CR_DLLPITESTANDADC_CountStatus_MSK (0x01FF8000) + #define DDRCLK_CR_DLLPITESTANDADC_CountStatus_MAX (0x000003FF) + #define DDRCLK_CR_DLLPITESTANDADC_CountStatus_DEF (0x00000000) + #define DDRCLK_CR_DLLPITESTANDADC_Spare_OFF (25) + #define DDRCLK_CR_DLLPITESTANDADC_Spare_WID ( 7) + #define DDRCLK_CR_DLLPITESTANDADC_Spare_MSK (0xFE000000) + #define DDRCLK_CR_DLLPITESTANDADC_Spare_MAX (0x0000007F) + +#define DDRCLK_CR_DDRCBSTATUS_REG (0x00003918) + #define DDRCLK_CR_DDRCBSTATUS_DllCB_OFF ( 0) + #define DDRCLK_CR_DDRCBSTATUS_DllCB_WID ( 2) + #define DDRCLK_CR_DDRCBSTATUS_DllCB_MSK (0x00000003) + #define DDRCLK_CR_DDRCBSTATUS_DllCB_MAX (0x00000003) + #define DDRCLK_CR_DDRCBSTATUS_DllCB_DEF (0x00000000) + #define DDRCLK_CR_DDRCBSTATUS_Spare_OFF ( 2) + #define DDRCLK_CR_DDRCBSTATUS_Spare_WID (30) + #define DDRCLK_CR_DDRCBSTATUS_Spare_MSK (0xFFFFFFFC) + #define DDRCLK_CR_DDRCBSTATUS_Spare_MAX (0x3FFFFFFF) + #define DDRCLK_CR_DDRCBSTATUS_Spare_DEF (0x00000000) + +#define DDRCLKCH0_CR_DDRCRCLKRANKSUSED_REG (0x00001800) + #define DDRCLKCH0_CR_DDRCRCLKRANKSUSED_RankEn_OFF ( 0) + #define DDRCLKCH0_CR_DDRCRCLKRANKSUSED_RankEn_WID ( 4) + #define DDRCLKCH0_CR_DDRCRCLKRANKSUSED_RankEn_MSK (0x0000000F) + #define DDRCLKCH0_CR_DDRCRCLKRANKSUSED_RankEn_MAX (0x0000000F) + #define DDRCLKCH0_CR_DDRCRCLKRANKSUSED_RankEn_DEF (0x0000000F) + #define DDRCLKCH0_CR_DDRCRCLKRANKSUSED_Spare_OFF ( 4) + #define DDRCLKCH0_CR_DDRCRCLKRANKSUSED_Spare_WID (28) + #define DDRCLKCH0_CR_DDRCRCLKRANKSUSED_Spare_MSK (0xFFFFFFF0) + #define DDRCLKCH0_CR_DDRCRCLKRANKSUSED_Spare_MAX (0x0FFFFFFF) + #define DDRCLKCH0_CR_DDRCRCLKRANKSUSED_Spare_DEF (0x00000000) + +#define DDRCLKCH0_CR_DDRCRCLKCOMP_REG (0x00001804) + #define DDRCLKCH0_CR_DDRCRCLKCOMP_Scomp_OFF ( 0) + #define DDRCLKCH0_CR_DDRCRCLKCOMP_Scomp_WID ( 5) + #define DDRCLKCH0_CR_DDRCRCLKCOMP_Scomp_MSK (0x0000001F) + #define DDRCLKCH0_CR_DDRCRCLKCOMP_Scomp_MAX (0x0000001F) + #define DDRCLKCH0_CR_DDRCRCLKCOMP_Scomp_DEF (0x00000000) + #define DDRCLKCH0_CR_DDRCRCLKCOMP_TcoComp_OFF ( 5) + #define DDRCLKCH0_CR_DDRCRCLKCOMP_TcoComp_WID ( 6) + #define DDRCLKCH0_CR_DDRCRCLKCOMP_TcoComp_MSK (0x000007E0) + #define DDRCLKCH0_CR_DDRCRCLKCOMP_TcoComp_MAX (0x0000003F) + #define DDRCLKCH0_CR_DDRCRCLKCOMP_TcoComp_DEF (0x00000000) + #define DDRCLKCH0_CR_DDRCRCLKCOMP_RcompDrvUp_OFF (11) + #define DDRCLKCH0_CR_DDRCRCLKCOMP_RcompDrvUp_WID ( 6) + #define DDRCLKCH0_CR_DDRCRCLKCOMP_RcompDrvUp_MSK (0x0001F800) + #define DDRCLKCH0_CR_DDRCRCLKCOMP_RcompDrvUp_MAX (0x0000003F) + #define DDRCLKCH0_CR_DDRCRCLKCOMP_RcompDrvUp_DEF (0x00000000) + #define DDRCLKCH0_CR_DDRCRCLKCOMP_RcompDrvDown_OFF (17) + #define DDRCLKCH0_CR_DDRCRCLKCOMP_RcompDrvDown_WID ( 6) + #define DDRCLKCH0_CR_DDRCRCLKCOMP_RcompDrvDown_MSK (0x007E0000) + #define DDRCLKCH0_CR_DDRCRCLKCOMP_RcompDrvDown_MAX (0x0000003F) + #define DDRCLKCH0_CR_DDRCRCLKCOMP_RcompDrvDown_DEF (0x00000000) + #define DDRCLKCH0_CR_DDRCRCLKCOMP_LsComp_OFF (23) + #define DDRCLKCH0_CR_DDRCRCLKCOMP_LsComp_WID ( 3) + #define DDRCLKCH0_CR_DDRCRCLKCOMP_LsComp_MSK (0x03800000) + #define DDRCLKCH0_CR_DDRCRCLKCOMP_LsComp_MAX (0x00000007) + #define DDRCLKCH0_CR_DDRCRCLKCOMP_LsComp_DEF (0x00000004) + #define DDRCLKCH0_CR_DDRCRCLKCOMP_Spare_OFF (26) + #define DDRCLKCH0_CR_DDRCRCLKCOMP_Spare_WID ( 6) + #define DDRCLKCH0_CR_DDRCRCLKCOMP_Spare_MSK (0xFC000000) + #define DDRCLKCH0_CR_DDRCRCLKCOMP_Spare_MAX (0x0000003F) + #define DDRCLKCH0_CR_DDRCRCLKCOMP_Spare_DEF (0x00000000) + +#define DDRCLKCH0_CR_DDRCRCLKCOMPOFFSET_REG (0x00001808) + #define DDRCLKCH0_CR_DDRCRCLKCOMPOFFSET_ScompOffset_OFF ( 0) + #define DDRCLKCH0_CR_DDRCRCLKCOMPOFFSET_ScompOffset_WID ( 4) + #define DDRCLKCH0_CR_DDRCRCLKCOMPOFFSET_ScompOffset_MSK (0x0000000F) + #define DDRCLKCH0_CR_DDRCRCLKCOMPOFFSET_ScompOffset_MAX (0x0000000F) + #define DDRCLKCH0_CR_DDRCRCLKCOMPOFFSET_ScompOffset_DEF (0x00000000) + #define DDRCLKCH0_CR_DDRCRCLKCOMPOFFSET_TcoCompOffset_OFF ( 4) + #define DDRCLKCH0_CR_DDRCRCLKCOMPOFFSET_TcoCompOffset_WID ( 4) + #define DDRCLKCH0_CR_DDRCRCLKCOMPOFFSET_TcoCompOffset_MSK (0x000000F0) + #define DDRCLKCH0_CR_DDRCRCLKCOMPOFFSET_TcoCompOffset_MAX (0x0000000F) + #define DDRCLKCH0_CR_DDRCRCLKCOMPOFFSET_TcoCompOffset_DEF (0x00000000) + #define DDRCLKCH0_CR_DDRCRCLKCOMPOFFSET_RcompDrvUpOffset_OFF ( 8) + #define DDRCLKCH0_CR_DDRCRCLKCOMPOFFSET_RcompDrvUpOffset_WID ( 4) + #define DDRCLKCH0_CR_DDRCRCLKCOMPOFFSET_RcompDrvUpOffset_MSK (0x00000F00) + #define DDRCLKCH0_CR_DDRCRCLKCOMPOFFSET_RcompDrvUpOffset_MAX (0x0000000F) + #define DDRCLKCH0_CR_DDRCRCLKCOMPOFFSET_RcompDrvUpOffset_DEF (0x00000000) + #define DDRCLKCH0_CR_DDRCRCLKCOMPOFFSET_RcompDrvDownOffset_OFF (12) + #define DDRCLKCH0_CR_DDRCRCLKCOMPOFFSET_RcompDrvDownOffset_WID ( 4) + #define DDRCLKCH0_CR_DDRCRCLKCOMPOFFSET_RcompDrvDownOffset_MSK (0x0000F000) + #define DDRCLKCH0_CR_DDRCRCLKCOMPOFFSET_RcompDrvDownOffset_MAX (0x0000000F) + #define DDRCLKCH0_CR_DDRCRCLKCOMPOFFSET_RcompDrvDownOffset_DEF (0x00000000) + #define DDRCLKCH0_CR_DDRCRCLKCOMPOFFSET_Spare_OFF (16) + #define DDRCLKCH0_CR_DDRCRCLKCOMPOFFSET_Spare_WID (16) + #define DDRCLKCH0_CR_DDRCRCLKCOMPOFFSET_Spare_MSK (0xFFFF0000) + #define DDRCLKCH0_CR_DDRCRCLKCOMPOFFSET_Spare_MAX (0x0000FFFF) + #define DDRCLKCH0_CR_DDRCRCLKCOMPOFFSET_Spare_DEF (0x00000000) + +#define DDRCLKCH0_CR_DDRCRCLKPICODE_REG (0x0000180C) + #define DDRCLKCH0_CR_DDRCRCLKPICODE_PiSettingRank0_OFF ( 0) + #define DDRCLKCH0_CR_DDRCRCLKPICODE_PiSettingRank0_WID ( 7) + #define DDRCLKCH0_CR_DDRCRCLKPICODE_PiSettingRank0_MSK (0x0000007F) + #define DDRCLKCH0_CR_DDRCRCLKPICODE_PiSettingRank0_MAX (0x0000007F) + #define DDRCLKCH0_CR_DDRCRCLKPICODE_PiSettingRank0_DEF (0x00000000) + #define DDRCLKCH0_CR_DDRCRCLKPICODE_PiSettingRank1_OFF ( 7) + #define DDRCLKCH0_CR_DDRCRCLKPICODE_PiSettingRank1_WID ( 7) + #define DDRCLKCH0_CR_DDRCRCLKPICODE_PiSettingRank1_MSK (0x00003F80) + #define DDRCLKCH0_CR_DDRCRCLKPICODE_PiSettingRank1_MAX (0x0000007F) + #define DDRCLKCH0_CR_DDRCRCLKPICODE_PiSettingRank1_DEF (0x00000000) + #define DDRCLKCH0_CR_DDRCRCLKPICODE_PiSettingRank2_OFF (14) + #define DDRCLKCH0_CR_DDRCRCLKPICODE_PiSettingRank2_WID ( 7) + #define DDRCLKCH0_CR_DDRCRCLKPICODE_PiSettingRank2_MSK (0x001FC000) + #define DDRCLKCH0_CR_DDRCRCLKPICODE_PiSettingRank2_MAX (0x0000007F) + #define DDRCLKCH0_CR_DDRCRCLKPICODE_PiSettingRank2_DEF (0x00000000) + #define DDRCLKCH0_CR_DDRCRCLKPICODE_PiSettingRank3_OFF (21) + #define DDRCLKCH0_CR_DDRCRCLKPICODE_PiSettingRank3_WID ( 7) + #define DDRCLKCH0_CR_DDRCRCLKPICODE_PiSettingRank3_MSK (0x0FE00000) + #define DDRCLKCH0_CR_DDRCRCLKPICODE_PiSettingRank3_MAX (0x0000007F) + #define DDRCLKCH0_CR_DDRCRCLKPICODE_PiSettingRank3_DEF (0x00000000) + #define DDRCLKCH0_CR_DDRCRCLKPICODE_Spare_OFF (28) + #define DDRCLKCH0_CR_DDRCRCLKPICODE_Spare_WID ( 4) + #define DDRCLKCH0_CR_DDRCRCLKPICODE_Spare_MSK (0xF0000000) + #define DDRCLKCH0_CR_DDRCRCLKPICODE_Spare_MAX (0x0000000F) + #define DDRCLKCH0_CR_DDRCRCLKPICODE_Spare_DEF (0x00000000) + +#define DDRCLKCH0_CR_DDRCRCLKCONTROLS_REG (0x00001810) + #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_RefPi_OFF ( 0) + #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_RefPi_WID ( 4) + #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_RefPi_MSK (0x0000000F) + #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_RefPi_MAX (0x0000000F) + #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_RefPi_DEF (0x00000000) + #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_DllMask_OFF ( 4) + #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_DllMask_WID ( 2) + #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_DllMask_MSK (0x00000030) + #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_DllMask_MAX (0x00000003) + #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_DllMask_DEF (0x00000000) + #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_DllRsvd1_OFF ( 6) + #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_DllRsvd1_WID ( 1) + #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_DllRsvd1_MSK (0x00000040) + #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_DllRsvd1_MAX (0x00000001) + #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_DllRsvd1_DEF (0x00000000) + #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_TxOn_OFF ( 7) + #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_TxOn_WID ( 1) + #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_TxOn_MSK (0x00000080) + #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_TxOn_MAX (0x00000001) + #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_TxOn_DEF (0x00000000) + #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_IntClkOn_OFF ( 8) + #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_IntClkOn_WID ( 1) + #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_IntClkOn_MSK (0x00000100) + #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_IntClkOn_MAX (0x00000001) + #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_IntClkOn_DEF (0x00000000) + #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_RepClkOn_OFF ( 9) + #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_RepClkOn_WID ( 1) + #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_RepClkOn_MSK (0x00000200) + #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_RepClkOn_MAX (0x00000001) + #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_RepClkOn_DEF (0x00000000) + #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_IOLBCtl_OFF (10) + #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_IOLBCtl_WID ( 2) + #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_IOLBCtl_MSK (0x00000C00) + #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_IOLBCtl_MAX (0x00000003) + #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_IOLBCtl_DEF (0x00000000) + #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_OdtMode_OFF (12) + #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_OdtMode_WID ( 1) + #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_OdtMode_MSK (0x00001000) + #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_OdtMode_MAX (0x00000001) + #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_OdtMode_DEF (0x00000000) + #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_Reserved_OFF (13) + #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_Reserved_WID ( 8) + #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_Reserved_MSK (0x001FE000) + #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_Reserved_MAX (0x000000FF) + #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_Reserved_DEF (0x00000000) + #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_RxVref_OFF (21) + #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_RxVref_WID ( 6) + #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_RxVref_MSK (0x07E00000) + #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_RxVref_MAX (0x0000003F) + #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_RxVref_DEF (0x00000000) + #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_VccddqHi_OFF (27) + #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_VccddqHi_WID ( 1) + #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_VccddqHi_MSK (0x08000000) + #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_VccddqHi_MAX (0x00000001) + #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_VccddqHi_DEF (0x00000000) + #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_DllWeakLock_OFF (28) + #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_DllWeakLock_WID ( 1) + #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_DllWeakLock_MSK (0x10000000) + #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_DllWeakLock_MAX (0x00000001) + #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_DllWeakLock_DEF (0x00000000) + #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_LPDDR_Mode_OFF (29) + #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_LPDDR_Mode_WID ( 1) + #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_LPDDR_Mode_MSK (0x20000000) + #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_LPDDR_Mode_MAX (0x00000001) + #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_LPDDR_Mode_DEF (0x00000000) + #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_Spare_OFF (30) + #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_Spare_WID ( 2) + #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_Spare_MSK (0xC0000000) + #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_Spare_MAX (0x00000003) + #define DDRCLKCH0_CR_DDRCRCLKCONTROLS_Spare_DEF (0x00000000) + +#define DDRCLKCH0_CR_DLLPITESTANDADC_REG (0x00001814) + #define DDRCLKCH0_CR_DLLPITESTANDADC_RunTest_OFF ( 0) + #define DDRCLKCH0_CR_DLLPITESTANDADC_RunTest_WID ( 1) + #define DDRCLKCH0_CR_DLLPITESTANDADC_RunTest_MSK (0x00000001) + #define DDRCLKCH0_CR_DLLPITESTANDADC_RunTest_MAX (0x00000001) + #define DDRCLKCH0_CR_DLLPITESTANDADC_RunTest_DEF (0x00000000) + #define DDRCLKCH0_CR_DLLPITESTANDADC_Load_OFF ( 1) + #define DDRCLKCH0_CR_DLLPITESTANDADC_Load_WID ( 1) + #define DDRCLKCH0_CR_DLLPITESTANDADC_Load_MSK (0x00000002) + #define DDRCLKCH0_CR_DLLPITESTANDADC_Load_MAX (0x00000001) + #define DDRCLKCH0_CR_DLLPITESTANDADC_Load_DEF (0x00000000) + #define DDRCLKCH0_CR_DLLPITESTANDADC_ModeHVM_OFF ( 2) + #define DDRCLKCH0_CR_DLLPITESTANDADC_ModeHVM_WID ( 1) + #define DDRCLKCH0_CR_DLLPITESTANDADC_ModeHVM_MSK (0x00000004) + #define DDRCLKCH0_CR_DLLPITESTANDADC_ModeHVM_MAX (0x00000001) + #define DDRCLKCH0_CR_DLLPITESTANDADC_ModeHVM_DEF (0x00000000) + #define DDRCLKCH0_CR_DLLPITESTANDADC_ModeDV_OFF ( 3) + #define DDRCLKCH0_CR_DLLPITESTANDADC_ModeDV_WID ( 1) + #define DDRCLKCH0_CR_DLLPITESTANDADC_ModeDV_MSK (0x00000008) + #define DDRCLKCH0_CR_DLLPITESTANDADC_ModeDV_MAX (0x00000001) + #define DDRCLKCH0_CR_DLLPITESTANDADC_ModeDV_DEF (0x00000000) + #define DDRCLKCH0_CR_DLLPITESTANDADC_ModeADC_OFF ( 4) + #define DDRCLKCH0_CR_DLLPITESTANDADC_ModeADC_WID ( 1) + #define DDRCLKCH0_CR_DLLPITESTANDADC_ModeADC_MSK (0x00000010) + #define DDRCLKCH0_CR_DLLPITESTANDADC_ModeADC_MAX (0x00000001) + #define DDRCLKCH0_CR_DLLPITESTANDADC_ModeADC_DEF (0x00000000) + #define DDRCLKCH0_CR_DLLPITESTANDADC_LoadCount_OFF ( 5) + #define DDRCLKCH0_CR_DLLPITESTANDADC_LoadCount_WID (10) + #define DDRCLKCH0_CR_DLLPITESTANDADC_LoadCount_MSK (0x00007FE0) + #define DDRCLKCH0_CR_DLLPITESTANDADC_LoadCount_MAX (0x000003FF) + #define DDRCLKCH0_CR_DLLPITESTANDADC_CountStatus_OFF (15) + #define DDRCLKCH0_CR_DLLPITESTANDADC_CountStatus_WID (10) + #define DDRCLKCH0_CR_DLLPITESTANDADC_CountStatus_MSK (0x01FF8000) + #define DDRCLKCH0_CR_DLLPITESTANDADC_CountStatus_MAX (0x000003FF) + #define DDRCLKCH0_CR_DLLPITESTANDADC_CountStatus_DEF (0x00000000) + #define DDRCLKCH0_CR_DLLPITESTANDADC_Spare_OFF (25) + #define DDRCLKCH0_CR_DLLPITESTANDADC_Spare_WID ( 7) + #define DDRCLKCH0_CR_DLLPITESTANDADC_Spare_MSK (0xFE000000) + #define DDRCLKCH0_CR_DLLPITESTANDADC_Spare_MAX (0x0000007F) + +#define DDRCLKCH0_CR_DDRCBSTATUS_REG (0x00001818) + #define DDRCLKCH0_CR_DDRCBSTATUS_DllCB_OFF ( 0) + #define DDRCLKCH0_CR_DDRCBSTATUS_DllCB_WID ( 2) + #define DDRCLKCH0_CR_DDRCBSTATUS_DllCB_MSK (0x00000003) + #define DDRCLKCH0_CR_DDRCBSTATUS_DllCB_MAX (0x00000003) + #define DDRCLKCH0_CR_DDRCBSTATUS_DllCB_DEF (0x00000000) + #define DDRCLKCH0_CR_DDRCBSTATUS_Spare_OFF ( 2) + #define DDRCLKCH0_CR_DDRCBSTATUS_Spare_WID (30) + #define DDRCLKCH0_CR_DDRCBSTATUS_Spare_MSK (0xFFFFFFFC) + #define DDRCLKCH0_CR_DDRCBSTATUS_Spare_MAX (0x3FFFFFFF) + #define DDRCLKCH0_CR_DDRCBSTATUS_Spare_DEF (0x00000000) + +#define DDRCLKCH1_CR_DDRCRCLKRANKSUSED_REG (0x00001900) + #define DDRCLKCH1_CR_DDRCRCLKRANKSUSED_RankEn_OFF ( 0) + #define DDRCLKCH1_CR_DDRCRCLKRANKSUSED_RankEn_WID ( 4) + #define DDRCLKCH1_CR_DDRCRCLKRANKSUSED_RankEn_MSK (0x0000000F) + #define DDRCLKCH1_CR_DDRCRCLKRANKSUSED_RankEn_MAX (0x0000000F) + #define DDRCLKCH1_CR_DDRCRCLKRANKSUSED_RankEn_DEF (0x0000000F) + #define DDRCLKCH1_CR_DDRCRCLKRANKSUSED_Spare_OFF ( 4) + #define DDRCLKCH1_CR_DDRCRCLKRANKSUSED_Spare_WID (28) + #define DDRCLKCH1_CR_DDRCRCLKRANKSUSED_Spare_MSK (0xFFFFFFF0) + #define DDRCLKCH1_CR_DDRCRCLKRANKSUSED_Spare_MAX (0x0FFFFFFF) + #define DDRCLKCH1_CR_DDRCRCLKRANKSUSED_Spare_DEF (0x00000000) + +#define DDRCLKCH1_CR_DDRCRCLKCOMP_REG (0x00001904) + #define DDRCLKCH1_CR_DDRCRCLKCOMP_Scomp_OFF ( 0) + #define DDRCLKCH1_CR_DDRCRCLKCOMP_Scomp_WID ( 5) + #define DDRCLKCH1_CR_DDRCRCLKCOMP_Scomp_MSK (0x0000001F) + #define DDRCLKCH1_CR_DDRCRCLKCOMP_Scomp_MAX (0x0000001F) + #define DDRCLKCH1_CR_DDRCRCLKCOMP_Scomp_DEF (0x00000000) + #define DDRCLKCH1_CR_DDRCRCLKCOMP_TcoComp_OFF ( 5) + #define DDRCLKCH1_CR_DDRCRCLKCOMP_TcoComp_WID ( 6) + #define DDRCLKCH1_CR_DDRCRCLKCOMP_TcoComp_MSK (0x000007E0) + #define DDRCLKCH1_CR_DDRCRCLKCOMP_TcoComp_MAX (0x0000003F) + #define DDRCLKCH1_CR_DDRCRCLKCOMP_TcoComp_DEF (0x00000000) + #define DDRCLKCH1_CR_DDRCRCLKCOMP_RcompDrvUp_OFF (11) + #define DDRCLKCH1_CR_DDRCRCLKCOMP_RcompDrvUp_WID ( 6) + #define DDRCLKCH1_CR_DDRCRCLKCOMP_RcompDrvUp_MSK (0x0001F800) + #define DDRCLKCH1_CR_DDRCRCLKCOMP_RcompDrvUp_MAX (0x0000003F) + #define DDRCLKCH1_CR_DDRCRCLKCOMP_RcompDrvUp_DEF (0x00000000) + #define DDRCLKCH1_CR_DDRCRCLKCOMP_RcompDrvDown_OFF (17) + #define DDRCLKCH1_CR_DDRCRCLKCOMP_RcompDrvDown_WID ( 6) + #define DDRCLKCH1_CR_DDRCRCLKCOMP_RcompDrvDown_MSK (0x007E0000) + #define DDRCLKCH1_CR_DDRCRCLKCOMP_RcompDrvDown_MAX (0x0000003F) + #define DDRCLKCH1_CR_DDRCRCLKCOMP_RcompDrvDown_DEF (0x00000000) + #define DDRCLKCH1_CR_DDRCRCLKCOMP_LsComp_OFF (23) + #define DDRCLKCH1_CR_DDRCRCLKCOMP_LsComp_WID ( 3) + #define DDRCLKCH1_CR_DDRCRCLKCOMP_LsComp_MSK (0x03800000) + #define DDRCLKCH1_CR_DDRCRCLKCOMP_LsComp_MAX (0x00000007) + #define DDRCLKCH1_CR_DDRCRCLKCOMP_LsComp_DEF (0x00000004) + #define DDRCLKCH1_CR_DDRCRCLKCOMP_Spare_OFF (26) + #define DDRCLKCH1_CR_DDRCRCLKCOMP_Spare_WID ( 6) + #define DDRCLKCH1_CR_DDRCRCLKCOMP_Spare_MSK (0xFC000000) + #define DDRCLKCH1_CR_DDRCRCLKCOMP_Spare_MAX (0x0000003F) + #define DDRCLKCH1_CR_DDRCRCLKCOMP_Spare_DEF (0x00000000) + +#define DDRCLKCH1_CR_DDRCRCLKCOMPOFFSET_REG (0x00001908) + #define DDRCLKCH1_CR_DDRCRCLKCOMPOFFSET_ScompOffset_OFF ( 0) + #define DDRCLKCH1_CR_DDRCRCLKCOMPOFFSET_ScompOffset_WID ( 4) + #define DDRCLKCH1_CR_DDRCRCLKCOMPOFFSET_ScompOffset_MSK (0x0000000F) + #define DDRCLKCH1_CR_DDRCRCLKCOMPOFFSET_ScompOffset_MAX (0x0000000F) + #define DDRCLKCH1_CR_DDRCRCLKCOMPOFFSET_ScompOffset_DEF (0x00000000) + #define DDRCLKCH1_CR_DDRCRCLKCOMPOFFSET_TcoCompOffset_OFF ( 4) + #define DDRCLKCH1_CR_DDRCRCLKCOMPOFFSET_TcoCompOffset_WID ( 4) + #define DDRCLKCH1_CR_DDRCRCLKCOMPOFFSET_TcoCompOffset_MSK (0x000000F0) + #define DDRCLKCH1_CR_DDRCRCLKCOMPOFFSET_TcoCompOffset_MAX (0x0000000F) + #define DDRCLKCH1_CR_DDRCRCLKCOMPOFFSET_TcoCompOffset_DEF (0x00000000) + #define DDRCLKCH1_CR_DDRCRCLKCOMPOFFSET_RcompDrvUpOffset_OFF ( 8) + #define DDRCLKCH1_CR_DDRCRCLKCOMPOFFSET_RcompDrvUpOffset_WID ( 4) + #define DDRCLKCH1_CR_DDRCRCLKCOMPOFFSET_RcompDrvUpOffset_MSK (0x00000F00) + #define DDRCLKCH1_CR_DDRCRCLKCOMPOFFSET_RcompDrvUpOffset_MAX (0x0000000F) + #define DDRCLKCH1_CR_DDRCRCLKCOMPOFFSET_RcompDrvUpOffset_DEF (0x00000000) + #define DDRCLKCH1_CR_DDRCRCLKCOMPOFFSET_RcompDrvDownOffset_OFF (12) + #define DDRCLKCH1_CR_DDRCRCLKCOMPOFFSET_RcompDrvDownOffset_WID ( 4) + #define DDRCLKCH1_CR_DDRCRCLKCOMPOFFSET_RcompDrvDownOffset_MSK (0x0000F000) + #define DDRCLKCH1_CR_DDRCRCLKCOMPOFFSET_RcompDrvDownOffset_MAX (0x0000000F) + #define DDRCLKCH1_CR_DDRCRCLKCOMPOFFSET_RcompDrvDownOffset_DEF (0x00000000) + #define DDRCLKCH1_CR_DDRCRCLKCOMPOFFSET_Spare_OFF (16) + #define DDRCLKCH1_CR_DDRCRCLKCOMPOFFSET_Spare_WID (16) + #define DDRCLKCH1_CR_DDRCRCLKCOMPOFFSET_Spare_MSK (0xFFFF0000) + #define DDRCLKCH1_CR_DDRCRCLKCOMPOFFSET_Spare_MAX (0x0000FFFF) + #define DDRCLKCH1_CR_DDRCRCLKCOMPOFFSET_Spare_DEF (0x00000000) + +#define DDRCLKCH1_CR_DDRCRCLKPICODE_REG (0x0000190C) + #define DDRCLKCH1_CR_DDRCRCLKPICODE_PiSettingRank0_OFF ( 0) + #define DDRCLKCH1_CR_DDRCRCLKPICODE_PiSettingRank0_WID ( 7) + #define DDRCLKCH1_CR_DDRCRCLKPICODE_PiSettingRank0_MSK (0x0000007F) + #define DDRCLKCH1_CR_DDRCRCLKPICODE_PiSettingRank0_MAX (0x0000007F) + #define DDRCLKCH1_CR_DDRCRCLKPICODE_PiSettingRank0_DEF (0x00000000) + #define DDRCLKCH1_CR_DDRCRCLKPICODE_PiSettingRank1_OFF ( 7) + #define DDRCLKCH1_CR_DDRCRCLKPICODE_PiSettingRank1_WID ( 7) + #define DDRCLKCH1_CR_DDRCRCLKPICODE_PiSettingRank1_MSK (0x00003F80) + #define DDRCLKCH1_CR_DDRCRCLKPICODE_PiSettingRank1_MAX (0x0000007F) + #define DDRCLKCH1_CR_DDRCRCLKPICODE_PiSettingRank1_DEF (0x00000000) + #define DDRCLKCH1_CR_DDRCRCLKPICODE_PiSettingRank2_OFF (14) + #define DDRCLKCH1_CR_DDRCRCLKPICODE_PiSettingRank2_WID ( 7) + #define DDRCLKCH1_CR_DDRCRCLKPICODE_PiSettingRank2_MSK (0x001FC000) + #define DDRCLKCH1_CR_DDRCRCLKPICODE_PiSettingRank2_MAX (0x0000007F) + #define DDRCLKCH1_CR_DDRCRCLKPICODE_PiSettingRank2_DEF (0x00000000) + #define DDRCLKCH1_CR_DDRCRCLKPICODE_PiSettingRank3_OFF (21) + #define DDRCLKCH1_CR_DDRCRCLKPICODE_PiSettingRank3_WID ( 7) + #define DDRCLKCH1_CR_DDRCRCLKPICODE_PiSettingRank3_MSK (0x0FE00000) + #define DDRCLKCH1_CR_DDRCRCLKPICODE_PiSettingRank3_MAX (0x0000007F) + #define DDRCLKCH1_CR_DDRCRCLKPICODE_PiSettingRank3_DEF (0x00000000) + #define DDRCLKCH1_CR_DDRCRCLKPICODE_Spare_OFF (28) + #define DDRCLKCH1_CR_DDRCRCLKPICODE_Spare_WID ( 4) + #define DDRCLKCH1_CR_DDRCRCLKPICODE_Spare_MSK (0xF0000000) + #define DDRCLKCH1_CR_DDRCRCLKPICODE_Spare_MAX (0x0000000F) + #define DDRCLKCH1_CR_DDRCRCLKPICODE_Spare_DEF (0x00000000) + +#define DDRCLKCH1_CR_DDRCRCLKCONTROLS_REG (0x00001910) + #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_RefPi_OFF ( 0) + #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_RefPi_WID ( 4) + #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_RefPi_MSK (0x0000000F) + #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_RefPi_MAX (0x0000000F) + #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_RefPi_DEF (0x00000000) + #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_DllMask_OFF ( 4) + #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_DllMask_WID ( 2) + #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_DllMask_MSK (0x00000030) + #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_DllMask_MAX (0x00000003) + #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_DllMask_DEF (0x00000000) + #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_DllRsvd1_OFF ( 6) + #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_DllRsvd1_WID ( 1) + #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_DllRsvd1_MSK (0x00000040) + #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_DllRsvd1_MAX (0x00000001) + #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_DllRsvd1_DEF (0x00000000) + #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_TxOn_OFF ( 7) + #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_TxOn_WID ( 1) + #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_TxOn_MSK (0x00000080) + #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_TxOn_MAX (0x00000001) + #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_TxOn_DEF (0x00000000) + #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_IntClkOn_OFF ( 8) + #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_IntClkOn_WID ( 1) + #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_IntClkOn_MSK (0x00000100) + #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_IntClkOn_MAX (0x00000001) + #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_IntClkOn_DEF (0x00000000) + #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_RepClkOn_OFF ( 9) + #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_RepClkOn_WID ( 1) + #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_RepClkOn_MSK (0x00000200) + #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_RepClkOn_MAX (0x00000001) + #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_RepClkOn_DEF (0x00000000) + #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_IOLBCtl_OFF (10) + #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_IOLBCtl_WID ( 2) + #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_IOLBCtl_MSK (0x00000C00) + #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_IOLBCtl_MAX (0x00000003) + #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_IOLBCtl_DEF (0x00000000) + #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_OdtMode_OFF (12) + #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_OdtMode_WID ( 1) + #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_OdtMode_MSK (0x00001000) + #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_OdtMode_MAX (0x00000001) + #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_OdtMode_DEF (0x00000000) + #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_Reserved_OFF (13) + #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_Reserved_WID ( 8) + #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_Reserved_MSK (0x001FE000) + #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_Reserved_MAX (0x000000FF) + #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_Reserved_DEF (0x00000000) + #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_RxVref_OFF (21) + #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_RxVref_WID ( 6) + #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_RxVref_MSK (0x07E00000) + #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_RxVref_MAX (0x0000003F) + #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_RxVref_DEF (0x00000000) + #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_VccddqHi_OFF (27) + #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_VccddqHi_WID ( 1) + #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_VccddqHi_MSK (0x08000000) + #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_VccddqHi_MAX (0x00000001) + #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_VccddqHi_DEF (0x00000000) + #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_DllWeakLock_OFF (28) + #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_DllWeakLock_WID ( 1) + #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_DllWeakLock_MSK (0x10000000) + #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_DllWeakLock_MAX (0x00000001) + #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_DllWeakLock_DEF (0x00000000) + #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_LPDDR_Mode_OFF (29) + #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_LPDDR_Mode_WID ( 1) + #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_LPDDR_Mode_MSK (0x20000000) + #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_LPDDR_Mode_MAX (0x00000001) + #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_LPDDR_Mode_DEF (0x00000000) + #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_Spare_OFF (30) + #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_Spare_WID ( 2) + #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_Spare_MSK (0xC0000000) + #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_Spare_MAX (0x00000003) + #define DDRCLKCH1_CR_DDRCRCLKCONTROLS_Spare_DEF (0x00000000) + +#define DDRCLKCH1_CR_DLLPITESTANDADC_REG (0x00001914) + #define DDRCLKCH1_CR_DLLPITESTANDADC_RunTest_OFF ( 0) + #define DDRCLKCH1_CR_DLLPITESTANDADC_RunTest_WID ( 1) + #define DDRCLKCH1_CR_DLLPITESTANDADC_RunTest_MSK (0x00000001) + #define DDRCLKCH1_CR_DLLPITESTANDADC_RunTest_MAX (0x00000001) + #define DDRCLKCH1_CR_DLLPITESTANDADC_RunTest_DEF (0x00000000) + #define DDRCLKCH1_CR_DLLPITESTANDADC_Load_OFF ( 1) + #define DDRCLKCH1_CR_DLLPITESTANDADC_Load_WID ( 1) + #define DDRCLKCH1_CR_DLLPITESTANDADC_Load_MSK (0x00000002) + #define DDRCLKCH1_CR_DLLPITESTANDADC_Load_MAX (0x00000001) + #define DDRCLKCH1_CR_DLLPITESTANDADC_Load_DEF (0x00000000) + #define DDRCLKCH1_CR_DLLPITESTANDADC_ModeHVM_OFF ( 2) + #define DDRCLKCH1_CR_DLLPITESTANDADC_ModeHVM_WID ( 1) + #define DDRCLKCH1_CR_DLLPITESTANDADC_ModeHVM_MSK (0x00000004) + #define DDRCLKCH1_CR_DLLPITESTANDADC_ModeHVM_MAX (0x00000001) + #define DDRCLKCH1_CR_DLLPITESTANDADC_ModeHVM_DEF (0x00000000) + #define DDRCLKCH1_CR_DLLPITESTANDADC_ModeDV_OFF ( 3) + #define DDRCLKCH1_CR_DLLPITESTANDADC_ModeDV_WID ( 1) + #define DDRCLKCH1_CR_DLLPITESTANDADC_ModeDV_MSK (0x00000008) + #define DDRCLKCH1_CR_DLLPITESTANDADC_ModeDV_MAX (0x00000001) + #define DDRCLKCH1_CR_DLLPITESTANDADC_ModeDV_DEF (0x00000000) + #define DDRCLKCH1_CR_DLLPITESTANDADC_ModeADC_OFF ( 4) + #define DDRCLKCH1_CR_DLLPITESTANDADC_ModeADC_WID ( 1) + #define DDRCLKCH1_CR_DLLPITESTANDADC_ModeADC_MSK (0x00000010) + #define DDRCLKCH1_CR_DLLPITESTANDADC_ModeADC_MAX (0x00000001) + #define DDRCLKCH1_CR_DLLPITESTANDADC_ModeADC_DEF (0x00000000) + #define DDRCLKCH1_CR_DLLPITESTANDADC_LoadCount_OFF ( 5) + #define DDRCLKCH1_CR_DLLPITESTANDADC_LoadCount_WID (10) + #define DDRCLKCH1_CR_DLLPITESTANDADC_LoadCount_MSK (0x00007FE0) + #define DDRCLKCH1_CR_DLLPITESTANDADC_LoadCount_MAX (0x000003FF) + #define DDRCLKCH1_CR_DLLPITESTANDADC_CountStatus_OFF (15) + #define DDRCLKCH1_CR_DLLPITESTANDADC_CountStatus_WID (10) + #define DDRCLKCH1_CR_DLLPITESTANDADC_CountStatus_MSK (0x01FF8000) + #define DDRCLKCH1_CR_DLLPITESTANDADC_CountStatus_MAX (0x000003FF) + #define DDRCLKCH1_CR_DLLPITESTANDADC_CountStatus_DEF (0x00000000) + #define DDRCLKCH1_CR_DLLPITESTANDADC_Spare_OFF (25) + #define DDRCLKCH1_CR_DLLPITESTANDADC_Spare_WID ( 7) + #define DDRCLKCH1_CR_DLLPITESTANDADC_Spare_MSK (0xFE000000) + #define DDRCLKCH1_CR_DLLPITESTANDADC_Spare_MAX (0x0000007F) + +#define DDRCLKCH1_CR_DDRCBSTATUS_REG (0x00001918) + #define DDRCLKCH1_CR_DDRCBSTATUS_DllCB_OFF ( 0) + #define DDRCLKCH1_CR_DDRCBSTATUS_DllCB_WID ( 2) + #define DDRCLKCH1_CR_DDRCBSTATUS_DllCB_MSK (0x00000003) + #define DDRCLKCH1_CR_DDRCBSTATUS_DllCB_MAX (0x00000003) + #define DDRCLKCH1_CR_DDRCBSTATUS_DllCB_DEF (0x00000000) + #define DDRCLKCH1_CR_DDRCBSTATUS_Spare_OFF ( 2) + #define DDRCLKCH1_CR_DDRCBSTATUS_Spare_WID (30) + #define DDRCLKCH1_CR_DDRCBSTATUS_Spare_MSK (0xFFFFFFFC) + #define DDRCLKCH1_CR_DDRCBSTATUS_Spare_MAX (0x3FFFFFFF) + #define DDRCLKCH1_CR_DDRCBSTATUS_Spare_DEF (0x00000000) + +#pragma pack(pop) +#endif // __McIoClk_h__ diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcRegisters/McIoCmd.h b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcRegisters/McIoCmd.h new file mode 100644 index 0000000..79c6146 --- /dev/null +++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcRegisters/McIoCmd.h @@ -0,0 +1,2002 @@ +/** @file + This file was automatically generated. Modify at your own risk. + +@copyright + Copyright (c) 2010 - 2012 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +**/ +#ifndef __McIoCmd_h__ +#define __McIoCmd_h__ + +#pragma pack(push, 1) +#include "MrcTypes.h" + +typedef union { + struct { + U32 Scomp : 6; // Bits 5:0 + U32 TcoComp : 6; // Bits 11:6 + U32 RcompDrvUp : 6; // Bits 17:12 + U32 RcompDrvDown : 6; // Bits 23:18 + U32 LsComp : 3; // Bits 26:24 + U32 Spare : 5; // Bits 31:27 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRCMD_CR_DDRCRCMDCOMP_STRUCT; + +typedef union { + struct { + U32 ScompOffset : 5; // Bits 4:0 + U32 TcoCompOffset : 4; // Bits 8:5 + U32 RcompDrvUpOffset : 4; // Bits 12:9 + U32 RcompDrvDownOffset : 4; // Bits 16:13 + U32 Spare : 15; // Bits 31:17 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRCMD_CR_DDRCRCMDCOMPOFFSET_STRUCT; + +typedef union { + struct { + U32 CmdPi0Code : 7; // Bits 6:0 + U32 CmdPi1Code : 7; // Bits 13:7 + U32 Spare : 18; // Bits 31:14 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRCMD_CR_DDRCRCMDPICODING_STRUCT; + +typedef union { + struct { + U32 RefPi : 4; // Bits 3:0 + U32 DllMask : 2; // Bits 5:4 + U32 DllRsvd1 : 1; // Bits 6:6 + U32 TxOn : 1; // Bits 7:7 + U32 IntClkOn : 1; // Bits 8:8 + U32 RepClkOn : 1; // Bits 9:9 + U32 IOLBCtl : 2; // Bits 11:10 + U32 OdtMode : 1; // Bits 12:12 + U32 CmdTxEq : 2; // Bits 14:13 + U32 EarlyWeakDrive : 2; // Bits 16:15 + U32 Reserved : 4; // Bits 20:17 + U32 RxVref : 6; // Bits 26:21 + U32 VccddqHi : 1; // Bits 27:27 + U32 DllWeakLock : 1; // Bits 28:28 + U32 LPDDR_Mode : 1; // Bits 29:29 + U32 LPDdrCAA_Dis : 1; // Bits 30:30 + U32 LPDdrCAB_Dis : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRCMD_CR_DDRCRCMDCONTROLS_STRUCT; + +typedef union { + struct { + U32 RunTest : 1; // Bits 0:0 + U32 Load : 1; // Bits 1:1 + U32 ModeHVM : 1; // Bits 2:2 + U32 ModeDV : 1; // Bits 3:3 + U32 ModeADC : 1; // Bits 4:4 + U32 LoadCount : 10; // Bits 14:5 + U32 CountStatus : 10; // Bits 24:15 + U32 Spare : 7; // Bits 31:25 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRCMD_CR_DLLPITESTANDADC_STRUCT; + +typedef union { + struct { + U32 Scomp : 6; // Bits 5:0 + U32 TcoComp : 6; // Bits 11:6 + U32 RcompDrvUp : 6; // Bits 17:12 + U32 RcompDrvDown : 6; // Bits 23:18 + U32 LsComp : 3; // Bits 26:24 + U32 Spare : 5; // Bits 31:27 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRCMDNCH0_CR_DDRCRCMDCOMP_STRUCT; + +typedef union { + struct { + U32 ScompOffset : 5; // Bits 4:0 + U32 TcoCompOffset : 4; // Bits 8:5 + U32 RcompDrvUpOffset : 4; // Bits 12:9 + U32 RcompDrvDownOffset : 4; // Bits 16:13 + U32 Spare : 15; // Bits 31:17 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRCMDNCH0_CR_DDRCRCMDCOMPOFFSET_STRUCT; + +typedef union { + struct { + U32 CmdPi0Code : 7; // Bits 6:0 + U32 CmdPi1Code : 7; // Bits 13:7 + U32 Spare : 18; // Bits 31:14 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRCMDNCH0_CR_DDRCRCMDPICODING_STRUCT; + +typedef union { + struct { + U32 RefPi : 4; // Bits 3:0 + U32 DllMask : 2; // Bits 5:4 + U32 DllRsvd1 : 1; // Bits 6:6 + U32 TxOn : 1; // Bits 7:7 + U32 IntClkOn : 1; // Bits 8:8 + U32 RepClkOn : 1; // Bits 9:9 + U32 IOLBCtl : 2; // Bits 11:10 + U32 OdtMode : 1; // Bits 12:12 + U32 CmdTxEq : 2; // Bits 14:13 + U32 EarlyWeakDrive : 2; // Bits 16:15 + U32 Reserved : 4; // Bits 20:17 + U32 RxVref : 6; // Bits 26:21 + U32 VccddqHi : 1; // Bits 27:27 + U32 DllWeakLock : 1; // Bits 28:28 + U32 LPDDR_Mode : 1; // Bits 29:29 + U32 LPDdrCAA_Dis : 1; // Bits 30:30 + U32 LPDdrCAB_Dis : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRCMDNCH0_CR_DDRCRCMDCONTROLS_STRUCT; + +typedef union { + struct { + U32 RunTest : 1; // Bits 0:0 + U32 Load : 1; // Bits 1:1 + U32 ModeHVM : 1; // Bits 2:2 + U32 ModeDV : 1; // Bits 3:3 + U32 ModeADC : 1; // Bits 4:4 + U32 LoadCount : 10; // Bits 14:5 + U32 CountStatus : 10; // Bits 24:15 + U32 Spare : 7; // Bits 31:25 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRCMDNCH0_CR_DLLPITESTANDADC_STRUCT; + +typedef union { + struct { + U32 Scomp : 6; // Bits 5:0 + U32 TcoComp : 6; // Bits 11:6 + U32 RcompDrvUp : 6; // Bits 17:12 + U32 RcompDrvDown : 6; // Bits 23:18 + U32 LsComp : 3; // Bits 26:24 + U32 Spare : 5; // Bits 31:27 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRCMDNCH1_CR_DDRCRCMDCOMP_STRUCT; + +typedef union { + struct { + U32 ScompOffset : 5; // Bits 4:0 + U32 TcoCompOffset : 4; // Bits 8:5 + U32 RcompDrvUpOffset : 4; // Bits 12:9 + U32 RcompDrvDownOffset : 4; // Bits 16:13 + U32 Spare : 15; // Bits 31:17 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRCMDNCH1_CR_DDRCRCMDCOMPOFFSET_STRUCT; + +typedef union { + struct { + U32 CmdPi0Code : 7; // Bits 6:0 + U32 CmdPi1Code : 7; // Bits 13:7 + U32 Spare : 18; // Bits 31:14 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRCMDNCH1_CR_DDRCRCMDPICODING_STRUCT; + +typedef union { + struct { + U32 RefPi : 4; // Bits 3:0 + U32 DllMask : 2; // Bits 5:4 + U32 DllRsvd1 : 1; // Bits 6:6 + U32 TxOn : 1; // Bits 7:7 + U32 IntClkOn : 1; // Bits 8:8 + U32 RepClkOn : 1; // Bits 9:9 + U32 IOLBCtl : 2; // Bits 11:10 + U32 OdtMode : 1; // Bits 12:12 + U32 CmdTxEq : 2; // Bits 14:13 + U32 EarlyWeakDrive : 2; // Bits 16:15 + U32 Reserved : 4; // Bits 20:17 + U32 RxVref : 6; // Bits 26:21 + U32 VccddqHi : 1; // Bits 27:27 + U32 DllWeakLock : 1; // Bits 28:28 + U32 LPDDR_Mode : 1; // Bits 29:29 + U32 LPDdrCAA_Dis : 1; // Bits 30:30 + U32 LPDdrCAB_Dis : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRCMDNCH1_CR_DDRCRCMDCONTROLS_STRUCT; + +typedef union { + struct { + U32 RunTest : 1; // Bits 0:0 + U32 Load : 1; // Bits 1:1 + U32 ModeHVM : 1; // Bits 2:2 + U32 ModeDV : 1; // Bits 3:3 + U32 ModeADC : 1; // Bits 4:4 + U32 LoadCount : 10; // Bits 14:5 + U32 CountStatus : 10; // Bits 24:15 + U32 Spare : 7; // Bits 31:25 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRCMDNCH1_CR_DLLPITESTANDADC_STRUCT; + +typedef union { + struct { + U32 Scomp : 6; // Bits 5:0 + U32 TcoComp : 6; // Bits 11:6 + U32 RcompDrvUp : 6; // Bits 17:12 + U32 RcompDrvDown : 6; // Bits 23:18 + U32 LsComp : 3; // Bits 26:24 + U32 Spare : 5; // Bits 31:27 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRCMDSCH0_CR_DDRCRCMDCOMP_STRUCT; + +typedef union { + struct { + U32 ScompOffset : 5; // Bits 4:0 + U32 TcoCompOffset : 4; // Bits 8:5 + U32 RcompDrvUpOffset : 4; // Bits 12:9 + U32 RcompDrvDownOffset : 4; // Bits 16:13 + U32 Spare : 15; // Bits 31:17 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRCMDSCH0_CR_DDRCRCMDCOMPOFFSET_STRUCT; + +typedef union { + struct { + U32 CmdPi0Code : 7; // Bits 6:0 + U32 CmdPi1Code : 7; // Bits 13:7 + U32 Spare : 18; // Bits 31:14 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRCMDSCH0_CR_DDRCRCMDPICODING_STRUCT; + +typedef union { + struct { + U32 RefPi : 4; // Bits 3:0 + U32 DllMask : 2; // Bits 5:4 + U32 DllRsvd1 : 1; // Bits 6:6 + U32 TxOn : 1; // Bits 7:7 + U32 IntClkOn : 1; // Bits 8:8 + U32 RepClkOn : 1; // Bits 9:9 + U32 IOLBCtl : 2; // Bits 11:10 + U32 OdtMode : 1; // Bits 12:12 + U32 CmdTxEq : 2; // Bits 14:13 + U32 EarlyWeakDrive : 2; // Bits 16:15 + U32 Reserved : 4; // Bits 20:17 + U32 RxVref : 6; // Bits 26:21 + U32 VccddqHi : 1; // Bits 27:27 + U32 DllWeakLock : 1; // Bits 28:28 + U32 LPDDR_Mode : 1; // Bits 29:29 + U32 LPDdrCAA_Dis : 1; // Bits 30:30 + U32 LPDdrCAB_Dis : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRCMDSCH0_CR_DDRCRCMDCONTROLS_STRUCT; + +typedef union { + struct { + U32 RunTest : 1; // Bits 0:0 + U32 Load : 1; // Bits 1:1 + U32 ModeHVM : 1; // Bits 2:2 + U32 ModeDV : 1; // Bits 3:3 + U32 ModeADC : 1; // Bits 4:4 + U32 LoadCount : 10; // Bits 14:5 + U32 CountStatus : 10; // Bits 24:15 + U32 Spare : 7; // Bits 31:25 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRCMDSCH0_CR_DLLPITESTANDADC_STRUCT; + +typedef union { + struct { + U32 Scomp : 6; // Bits 5:0 + U32 TcoComp : 6; // Bits 11:6 + U32 RcompDrvUp : 6; // Bits 17:12 + U32 RcompDrvDown : 6; // Bits 23:18 + U32 LsComp : 3; // Bits 26:24 + U32 Spare : 5; // Bits 31:27 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRCMDSCH1_CR_DDRCRCMDCOMP_STRUCT; + +typedef union { + struct { + U32 ScompOffset : 5; // Bits 4:0 + U32 TcoCompOffset : 4; // Bits 8:5 + U32 RcompDrvUpOffset : 4; // Bits 12:9 + U32 RcompDrvDownOffset : 4; // Bits 16:13 + U32 Spare : 15; // Bits 31:17 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRCMDSCH1_CR_DDRCRCMDCOMPOFFSET_STRUCT; + +typedef union { + struct { + U32 CmdPi0Code : 7; // Bits 6:0 + U32 CmdPi1Code : 7; // Bits 13:7 + U32 Spare : 18; // Bits 31:14 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRCMDSCH1_CR_DDRCRCMDPICODING_STRUCT; + +typedef union { + struct { + U32 RefPi : 4; // Bits 3:0 + U32 DllMask : 2; // Bits 5:4 + U32 DllRsvd1 : 1; // Bits 6:6 + U32 TxOn : 1; // Bits 7:7 + U32 IntClkOn : 1; // Bits 8:8 + U32 RepClkOn : 1; // Bits 9:9 + U32 IOLBCtl : 2; // Bits 11:10 + U32 OdtMode : 1; // Bits 12:12 + U32 CmdTxEq : 2; // Bits 14:13 + U32 EarlyWeakDrive : 2; // Bits 16:15 + U32 Reserved : 4; // Bits 20:17 + U32 RxVref : 6; // Bits 26:21 + U32 VccddqHi : 1; // Bits 27:27 + U32 DllWeakLock : 1; // Bits 28:28 + U32 LPDDR_Mode : 1; // Bits 29:29 + U32 LPDdrCAA_Dis : 1; // Bits 30:30 + U32 LPDdrCAB_Dis : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRCMDSCH1_CR_DDRCRCMDCONTROLS_STRUCT; + +typedef union { + struct { + U32 RunTest : 1; // Bits 0:0 + U32 Load : 1; // Bits 1:1 + U32 ModeHVM : 1; // Bits 2:2 + U32 ModeDV : 1; // Bits 3:3 + U32 ModeADC : 1; // Bits 4:4 + U32 LoadCount : 10; // Bits 14:5 + U32 CountStatus : 10; // Bits 24:15 + U32 Spare : 7; // Bits 31:25 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRCMDSCH1_CR_DLLPITESTANDADC_STRUCT; + +typedef union { + struct { + U32 Scomp : 6; // Bits 5:0 + U32 TcoComp : 6; // Bits 11:6 + U32 RcompDrvUp : 6; // Bits 17:12 + U32 RcompDrvDown : 6; // Bits 23:18 + U32 LsComp : 3; // Bits 26:24 + U32 Spare : 5; // Bits 31:27 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRCMDCH0_CR_DDRCRCMDCOMP_STRUCT; + +typedef union { + struct { + U32 ScompOffset : 5; // Bits 4:0 + U32 TcoCompOffset : 4; // Bits 8:5 + U32 RcompDrvUpOffset : 4; // Bits 12:9 + U32 RcompDrvDownOffset : 4; // Bits 16:13 + U32 Spare : 15; // Bits 31:17 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRCMDCH0_CR_DDRCRCMDCOMPOFFSET_STRUCT; + +typedef union { + struct { + U32 CmdPi0Code : 7; // Bits 6:0 + U32 CmdPi1Code : 7; // Bits 13:7 + U32 Spare : 18; // Bits 31:14 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRCMDCH0_CR_DDRCRCMDPICODING_STRUCT; + +typedef union { + struct { + U32 RefPi : 4; // Bits 3:0 + U32 DllMask : 2; // Bits 5:4 + U32 DllRsvd1 : 1; // Bits 6:6 + U32 TxOn : 1; // Bits 7:7 + U32 IntClkOn : 1; // Bits 8:8 + U32 RepClkOn : 1; // Bits 9:9 + U32 IOLBCtl : 2; // Bits 11:10 + U32 OdtMode : 1; // Bits 12:12 + U32 CmdTxEq : 2; // Bits 14:13 + U32 EarlyWeakDrive : 2; // Bits 16:15 + U32 Reserved : 4; // Bits 20:17 + U32 RxVref : 6; // Bits 26:21 + U32 VccddqHi : 1; // Bits 27:27 + U32 DllWeakLock : 1; // Bits 28:28 + U32 LPDDR_Mode : 1; // Bits 29:29 + U32 LPDdrCAA_Dis : 1; // Bits 30:30 + U32 LPDdrCAB_Dis : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRCMDCH0_CR_DDRCRCMDCONTROLS_STRUCT; + +typedef union { + struct { + U32 RunTest : 1; // Bits 0:0 + U32 Load : 1; // Bits 1:1 + U32 ModeHVM : 1; // Bits 2:2 + U32 ModeDV : 1; // Bits 3:3 + U32 ModeADC : 1; // Bits 4:4 + U32 LoadCount : 10; // Bits 14:5 + U32 CountStatus : 10; // Bits 24:15 + U32 Spare : 7; // Bits 31:25 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRCMDCH0_CR_DLLPITESTANDADC_STRUCT; + +typedef union { + struct { + U32 Scomp : 6; // Bits 5:0 + U32 TcoComp : 6; // Bits 11:6 + U32 RcompDrvUp : 6; // Bits 17:12 + U32 RcompDrvDown : 6; // Bits 23:18 + U32 LsComp : 3; // Bits 26:24 + U32 Spare : 5; // Bits 31:27 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRCMDCH1_CR_DDRCRCMDCOMP_STRUCT; + +typedef union { + struct { + U32 ScompOffset : 5; // Bits 4:0 + U32 TcoCompOffset : 4; // Bits 8:5 + U32 RcompDrvUpOffset : 4; // Bits 12:9 + U32 RcompDrvDownOffset : 4; // Bits 16:13 + U32 Spare : 15; // Bits 31:17 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRCMDCH1_CR_DDRCRCMDCOMPOFFSET_STRUCT; + +typedef union { + struct { + U32 CmdPi0Code : 7; // Bits 6:0 + U32 CmdPi1Code : 7; // Bits 13:7 + U32 Spare : 18; // Bits 31:14 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRCMDCH1_CR_DDRCRCMDPICODING_STRUCT; + +typedef union { + struct { + U32 RefPi : 4; // Bits 3:0 + U32 DllMask : 2; // Bits 5:4 + U32 DllRsvd1 : 1; // Bits 6:6 + U32 TxOn : 1; // Bits 7:7 + U32 IntClkOn : 1; // Bits 8:8 + U32 RepClkOn : 1; // Bits 9:9 + U32 IOLBCtl : 2; // Bits 11:10 + U32 OdtMode : 1; // Bits 12:12 + U32 CmdTxEq : 2; // Bits 14:13 + U32 EarlyWeakDrive : 2; // Bits 16:15 + U32 Reserved : 4; // Bits 20:17 + U32 RxVref : 6; // Bits 26:21 + U32 VccddqHi : 1; // Bits 27:27 + U32 DllWeakLock : 1; // Bits 28:28 + U32 LPDDR_Mode : 1; // Bits 29:29 + U32 LPDdrCAA_Dis : 1; // Bits 30:30 + U32 LPDdrCAB_Dis : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRCMDCH1_CR_DDRCRCMDCONTROLS_STRUCT; + +typedef union { + struct { + U32 RunTest : 1; // Bits 0:0 + U32 Load : 1; // Bits 1:1 + U32 ModeHVM : 1; // Bits 2:2 + U32 ModeDV : 1; // Bits 3:3 + U32 ModeADC : 1; // Bits 4:4 + U32 LoadCount : 10; // Bits 14:5 + U32 CountStatus : 10; // Bits 24:15 + U32 Spare : 7; // Bits 31:25 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRCMDCH1_CR_DLLPITESTANDADC_STRUCT; + +#define DDRCMD_CR_DDRCRCMDCOMP_REG (0x00003700) + #define DDRCMD_CR_DDRCRCMDCOMP_Scomp_OFF ( 0) + #define DDRCMD_CR_DDRCRCMDCOMP_Scomp_WID ( 6) + #define DDRCMD_CR_DDRCRCMDCOMP_Scomp_MSK (0x0000003F) + #define DDRCMD_CR_DDRCRCMDCOMP_Scomp_MAX (0x0000003F) + #define DDRCMD_CR_DDRCRCMDCOMP_Scomp_DEF (0x00000000) + #define DDRCMD_CR_DDRCRCMDCOMP_TcoComp_OFF ( 6) + #define DDRCMD_CR_DDRCRCMDCOMP_TcoComp_WID ( 6) + #define DDRCMD_CR_DDRCRCMDCOMP_TcoComp_MSK (0x00000FC0) + #define DDRCMD_CR_DDRCRCMDCOMP_TcoComp_MAX (0x0000003F) + #define DDRCMD_CR_DDRCRCMDCOMP_TcoComp_DEF (0x00000000) + #define DDRCMD_CR_DDRCRCMDCOMP_RcompDrvUp_OFF (12) + #define DDRCMD_CR_DDRCRCMDCOMP_RcompDrvUp_WID ( 6) + #define DDRCMD_CR_DDRCRCMDCOMP_RcompDrvUp_MSK (0x0003F000) + #define DDRCMD_CR_DDRCRCMDCOMP_RcompDrvUp_MAX (0x0000003F) + #define DDRCMD_CR_DDRCRCMDCOMP_RcompDrvUp_DEF (0x00000000) + #define DDRCMD_CR_DDRCRCMDCOMP_RcompDrvDown_OFF (18) + #define DDRCMD_CR_DDRCRCMDCOMP_RcompDrvDown_WID ( 6) + #define DDRCMD_CR_DDRCRCMDCOMP_RcompDrvDown_MSK (0x00FC0000) + #define DDRCMD_CR_DDRCRCMDCOMP_RcompDrvDown_MAX (0x0000003F) + #define DDRCMD_CR_DDRCRCMDCOMP_RcompDrvDown_DEF (0x00000000) + #define DDRCMD_CR_DDRCRCMDCOMP_LsComp_OFF (24) + #define DDRCMD_CR_DDRCRCMDCOMP_LsComp_WID ( 3) + #define DDRCMD_CR_DDRCRCMDCOMP_LsComp_MSK (0x07000000) + #define DDRCMD_CR_DDRCRCMDCOMP_LsComp_MAX (0x00000007) + #define DDRCMD_CR_DDRCRCMDCOMP_LsComp_DEF (0x00000004) + #define DDRCMD_CR_DDRCRCMDCOMP_Spare_OFF (27) + #define DDRCMD_CR_DDRCRCMDCOMP_Spare_WID ( 5) + #define DDRCMD_CR_DDRCRCMDCOMP_Spare_MSK (0xF8000000) + #define DDRCMD_CR_DDRCRCMDCOMP_Spare_MAX (0x0000001F) + #define DDRCMD_CR_DDRCRCMDCOMP_Spare_DEF (0x00000000) + +#define DDRCMD_CR_DDRCRCMDCOMPOFFSET_REG (0x00003704) + #define DDRCMD_CR_DDRCRCMDCOMPOFFSET_ScompOffset_OFF ( 0) + #define DDRCMD_CR_DDRCRCMDCOMPOFFSET_ScompOffset_WID ( 5) + #define DDRCMD_CR_DDRCRCMDCOMPOFFSET_ScompOffset_MSK (0x0000001F) + #define DDRCMD_CR_DDRCRCMDCOMPOFFSET_ScompOffset_MAX (0x0000001F) + #define DDRCMD_CR_DDRCRCMDCOMPOFFSET_ScompOffset_DEF (0x00000000) + #define DDRCMD_CR_DDRCRCMDCOMPOFFSET_TcoCompOffset_OFF ( 5) + #define DDRCMD_CR_DDRCRCMDCOMPOFFSET_TcoCompOffset_WID ( 4) + #define DDRCMD_CR_DDRCRCMDCOMPOFFSET_TcoCompOffset_MSK (0x000001E0) + #define DDRCMD_CR_DDRCRCMDCOMPOFFSET_TcoCompOffset_MAX (0x0000000F) + #define DDRCMD_CR_DDRCRCMDCOMPOFFSET_TcoCompOffset_DEF (0x00000000) + #define DDRCMD_CR_DDRCRCMDCOMPOFFSET_RcompDrvUpOffset_OFF ( 9) + #define DDRCMD_CR_DDRCRCMDCOMPOFFSET_RcompDrvUpOffset_WID ( 4) + #define DDRCMD_CR_DDRCRCMDCOMPOFFSET_RcompDrvUpOffset_MSK (0x00001E00) + #define DDRCMD_CR_DDRCRCMDCOMPOFFSET_RcompDrvUpOffset_MAX (0x0000000F) + #define DDRCMD_CR_DDRCRCMDCOMPOFFSET_RcompDrvUpOffset_DEF (0x00000000) + #define DDRCMD_CR_DDRCRCMDCOMPOFFSET_RcompDrvDownOffset_OFF (13) + #define DDRCMD_CR_DDRCRCMDCOMPOFFSET_RcompDrvDownOffset_WID ( 4) + #define DDRCMD_CR_DDRCRCMDCOMPOFFSET_RcompDrvDownOffset_MSK (0x0001E000) + #define DDRCMD_CR_DDRCRCMDCOMPOFFSET_RcompDrvDownOffset_MAX (0x0000000F) + #define DDRCMD_CR_DDRCRCMDCOMPOFFSET_RcompDrvDownOffset_DEF (0x00000000) + #define DDRCMD_CR_DDRCRCMDCOMPOFFSET_Spare_OFF (17) + #define DDRCMD_CR_DDRCRCMDCOMPOFFSET_Spare_WID (15) + #define DDRCMD_CR_DDRCRCMDCOMPOFFSET_Spare_MSK (0xFFFE0000) + #define DDRCMD_CR_DDRCRCMDCOMPOFFSET_Spare_MAX (0x00007FFF) + #define DDRCMD_CR_DDRCRCMDCOMPOFFSET_Spare_DEF (0x00000000) + +#define DDRCMD_CR_DDRCRCMDPICODING_REG (0x00003708) + #define DDRCMD_CR_DDRCRCMDPICODING_CmdPi0Code_OFF ( 0) + #define DDRCMD_CR_DDRCRCMDPICODING_CmdPi0Code_WID ( 7) + #define DDRCMD_CR_DDRCRCMDPICODING_CmdPi0Code_MSK (0x0000007F) + #define DDRCMD_CR_DDRCRCMDPICODING_CmdPi0Code_MAX (0x0000007F) + #define DDRCMD_CR_DDRCRCMDPICODING_CmdPi0Code_DEF (0x00000000) + #define DDRCMD_CR_DDRCRCMDPICODING_CmdPi1Code_OFF ( 7) + #define DDRCMD_CR_DDRCRCMDPICODING_CmdPi1Code_WID ( 7) + #define DDRCMD_CR_DDRCRCMDPICODING_CmdPi1Code_MSK (0x00003F80) + #define DDRCMD_CR_DDRCRCMDPICODING_CmdPi1Code_MAX (0x0000007F) + #define DDRCMD_CR_DDRCRCMDPICODING_CmdPi1Code_DEF (0x00000000) + #define DDRCMD_CR_DDRCRCMDPICODING_Spare_OFF (14) + #define DDRCMD_CR_DDRCRCMDPICODING_Spare_WID (18) + #define DDRCMD_CR_DDRCRCMDPICODING_Spare_MSK (0xFFFFC000) + #define DDRCMD_CR_DDRCRCMDPICODING_Spare_MAX (0x0003FFFF) + #define DDRCMD_CR_DDRCRCMDPICODING_Spare_DEF (0x00000000) + +#define DDRCMD_CR_DDRCRCMDCONTROLS_REG (0x0000370C) + #define DDRCMD_CR_DDRCRCMDCONTROLS_RefPi_OFF ( 0) + #define DDRCMD_CR_DDRCRCMDCONTROLS_RefPi_WID ( 4) + #define DDRCMD_CR_DDRCRCMDCONTROLS_RefPi_MSK (0x0000000F) + #define DDRCMD_CR_DDRCRCMDCONTROLS_RefPi_MAX (0x0000000F) + #define DDRCMD_CR_DDRCRCMDCONTROLS_RefPi_DEF (0x00000000) + #define DDRCMD_CR_DDRCRCMDCONTROLS_DllMask_OFF ( 4) + #define DDRCMD_CR_DDRCRCMDCONTROLS_DllMask_WID ( 2) + #define DDRCMD_CR_DDRCRCMDCONTROLS_DllMask_MSK (0x00000030) + #define DDRCMD_CR_DDRCRCMDCONTROLS_DllMask_MAX (0x00000003) + #define DDRCMD_CR_DDRCRCMDCONTROLS_DllMask_DEF (0x00000000) + #define DDRCMD_CR_DDRCRCMDCONTROLS_DllRsvd1_OFF ( 6) + #define DDRCMD_CR_DDRCRCMDCONTROLS_DllRsvd1_WID ( 1) + #define DDRCMD_CR_DDRCRCMDCONTROLS_DllRsvd1_MSK (0x00000040) + #define DDRCMD_CR_DDRCRCMDCONTROLS_DllRsvd1_MAX (0x00000001) + #define DDRCMD_CR_DDRCRCMDCONTROLS_DllRsvd1_DEF (0x00000000) + #define DDRCMD_CR_DDRCRCMDCONTROLS_TxOn_OFF ( 7) + #define DDRCMD_CR_DDRCRCMDCONTROLS_TxOn_WID ( 1) + #define DDRCMD_CR_DDRCRCMDCONTROLS_TxOn_MSK (0x00000080) + #define DDRCMD_CR_DDRCRCMDCONTROLS_TxOn_MAX (0x00000001) + #define DDRCMD_CR_DDRCRCMDCONTROLS_TxOn_DEF (0x00000000) + #define DDRCMD_CR_DDRCRCMDCONTROLS_IntClkOn_OFF ( 8) + #define DDRCMD_CR_DDRCRCMDCONTROLS_IntClkOn_WID ( 1) + #define DDRCMD_CR_DDRCRCMDCONTROLS_IntClkOn_MSK (0x00000100) + #define DDRCMD_CR_DDRCRCMDCONTROLS_IntClkOn_MAX (0x00000001) + #define DDRCMD_CR_DDRCRCMDCONTROLS_IntClkOn_DEF (0x00000000) + #define DDRCMD_CR_DDRCRCMDCONTROLS_RepClkOn_OFF ( 9) + #define DDRCMD_CR_DDRCRCMDCONTROLS_RepClkOn_WID ( 1) + #define DDRCMD_CR_DDRCRCMDCONTROLS_RepClkOn_MSK (0x00000200) + #define DDRCMD_CR_DDRCRCMDCONTROLS_RepClkOn_MAX (0x00000001) + #define DDRCMD_CR_DDRCRCMDCONTROLS_RepClkOn_DEF (0x00000000) + #define DDRCMD_CR_DDRCRCMDCONTROLS_IOLBCtl_OFF (10) + #define DDRCMD_CR_DDRCRCMDCONTROLS_IOLBCtl_WID ( 2) + #define DDRCMD_CR_DDRCRCMDCONTROLS_IOLBCtl_MSK (0x00000C00) + #define DDRCMD_CR_DDRCRCMDCONTROLS_IOLBCtl_MAX (0x00000003) + #define DDRCMD_CR_DDRCRCMDCONTROLS_IOLBCtl_DEF (0x00000000) + #define DDRCMD_CR_DDRCRCMDCONTROLS_OdtMode_OFF (12) + #define DDRCMD_CR_DDRCRCMDCONTROLS_OdtMode_WID ( 1) + #define DDRCMD_CR_DDRCRCMDCONTROLS_OdtMode_MSK (0x00001000) + #define DDRCMD_CR_DDRCRCMDCONTROLS_OdtMode_MAX (0x00000001) + #define DDRCMD_CR_DDRCRCMDCONTROLS_OdtMode_DEF (0x00000000) + #define DDRCMD_CR_DDRCRCMDCONTROLS_CmdTxEq_OFF (13) + #define DDRCMD_CR_DDRCRCMDCONTROLS_CmdTxEq_WID ( 2) + #define DDRCMD_CR_DDRCRCMDCONTROLS_CmdTxEq_MSK (0x00006000) + #define DDRCMD_CR_DDRCRCMDCONTROLS_CmdTxEq_MAX (0x00000003) + #define DDRCMD_CR_DDRCRCMDCONTROLS_CmdTxEq_DEF (0x00000000) + #define DDRCMD_CR_DDRCRCMDCONTROLS_EarlyWeakDrive_OFF (15) + #define DDRCMD_CR_DDRCRCMDCONTROLS_EarlyWeakDrive_WID ( 2) + #define DDRCMD_CR_DDRCRCMDCONTROLS_EarlyWeakDrive_MSK (0x00018000) + #define DDRCMD_CR_DDRCRCMDCONTROLS_EarlyWeakDrive_MAX (0x00000003) + #define DDRCMD_CR_DDRCRCMDCONTROLS_EarlyWeakDrive_DEF (0x00000000) + #define DDRCMD_CR_DDRCRCMDCONTROLS_Reserved_OFF (17) + #define DDRCMD_CR_DDRCRCMDCONTROLS_Reserved_WID ( 4) + #define DDRCMD_CR_DDRCRCMDCONTROLS_Reserved_MSK (0x001E0000) + #define DDRCMD_CR_DDRCRCMDCONTROLS_Reserved_MAX (0x0000000F) + #define DDRCMD_CR_DDRCRCMDCONTROLS_Reserved_DEF (0x00000000) + #define DDRCMD_CR_DDRCRCMDCONTROLS_RxVref_OFF (21) + #define DDRCMD_CR_DDRCRCMDCONTROLS_RxVref_WID ( 6) + #define DDRCMD_CR_DDRCRCMDCONTROLS_RxVref_MSK (0x07E00000) + #define DDRCMD_CR_DDRCRCMDCONTROLS_RxVref_MAX (0x0000003F) + #define DDRCMD_CR_DDRCRCMDCONTROLS_RxVref_DEF (0x00000000) + #define DDRCMD_CR_DDRCRCMDCONTROLS_VccddqHi_OFF (27) + #define DDRCMD_CR_DDRCRCMDCONTROLS_VccddqHi_WID ( 1) + #define DDRCMD_CR_DDRCRCMDCONTROLS_VccddqHi_MSK (0x08000000) + #define DDRCMD_CR_DDRCRCMDCONTROLS_VccddqHi_MAX (0x00000001) + #define DDRCMD_CR_DDRCRCMDCONTROLS_VccddqHi_DEF (0x00000000) + #define DDRCMD_CR_DDRCRCMDCONTROLS_DllWeakLock_OFF (28) + #define DDRCMD_CR_DDRCRCMDCONTROLS_DllWeakLock_WID ( 1) + #define DDRCMD_CR_DDRCRCMDCONTROLS_DllWeakLock_MSK (0x10000000) + #define DDRCMD_CR_DDRCRCMDCONTROLS_DllWeakLock_MAX (0x00000001) + #define DDRCMD_CR_DDRCRCMDCONTROLS_DllWeakLock_DEF (0x00000000) + #define DDRCMD_CR_DDRCRCMDCONTROLS_LPDDR_Mode_OFF (29) + #define DDRCMD_CR_DDRCRCMDCONTROLS_LPDDR_Mode_WID ( 1) + #define DDRCMD_CR_DDRCRCMDCONTROLS_LPDDR_Mode_MSK (0x20000000) + #define DDRCMD_CR_DDRCRCMDCONTROLS_LPDDR_Mode_MAX (0x00000001) + #define DDRCMD_CR_DDRCRCMDCONTROLS_LPDDR_Mode_DEF (0x00000000) + #define DDRCMD_CR_DDRCRCMDCONTROLS_LPDdrCAA_Dis_OFF (30) + #define DDRCMD_CR_DDRCRCMDCONTROLS_LPDdrCAA_Dis_WID ( 1) + #define DDRCMD_CR_DDRCRCMDCONTROLS_LPDdrCAA_Dis_MSK (0x40000000) + #define DDRCMD_CR_DDRCRCMDCONTROLS_LPDdrCAA_Dis_MAX (0x00000001) + #define DDRCMD_CR_DDRCRCMDCONTROLS_LPDdrCAA_Dis_DEF (0x00000000) + #define DDRCMD_CR_DDRCRCMDCONTROLS_LPDdrCAB_Dis_OFF (31) + #define DDRCMD_CR_DDRCRCMDCONTROLS_LPDdrCAB_Dis_WID ( 1) + #define DDRCMD_CR_DDRCRCMDCONTROLS_LPDdrCAB_Dis_MSK (0x80000000) + #define DDRCMD_CR_DDRCRCMDCONTROLS_LPDdrCAB_Dis_MAX (0x00000001) + #define DDRCMD_CR_DDRCRCMDCONTROLS_LPDdrCAB_Dis_DEF (0x00000000) + +#define DDRCMD_CR_DLLPITESTANDADC_REG (0x00003724) + #define DDRCMD_CR_DLLPITESTANDADC_RunTest_OFF ( 0) + #define DDRCMD_CR_DLLPITESTANDADC_RunTest_WID ( 1) + #define DDRCMD_CR_DLLPITESTANDADC_RunTest_MSK (0x00000001) + #define DDRCMD_CR_DLLPITESTANDADC_RunTest_MAX (0x00000001) + #define DDRCMD_CR_DLLPITESTANDADC_RunTest_DEF (0x00000000) + #define DDRCMD_CR_DLLPITESTANDADC_Load_OFF ( 1) + #define DDRCMD_CR_DLLPITESTANDADC_Load_WID ( 1) + #define DDRCMD_CR_DLLPITESTANDADC_Load_MSK (0x00000002) + #define DDRCMD_CR_DLLPITESTANDADC_Load_MAX (0x00000001) + #define DDRCMD_CR_DLLPITESTANDADC_Load_DEF (0x00000000) + #define DDRCMD_CR_DLLPITESTANDADC_ModeHVM_OFF ( 2) + #define DDRCMD_CR_DLLPITESTANDADC_ModeHVM_WID ( 1) + #define DDRCMD_CR_DLLPITESTANDADC_ModeHVM_MSK (0x00000004) + #define DDRCMD_CR_DLLPITESTANDADC_ModeHVM_MAX (0x00000001) + #define DDRCMD_CR_DLLPITESTANDADC_ModeHVM_DEF (0x00000000) + #define DDRCMD_CR_DLLPITESTANDADC_ModeDV_OFF ( 3) + #define DDRCMD_CR_DLLPITESTANDADC_ModeDV_WID ( 1) + #define DDRCMD_CR_DLLPITESTANDADC_ModeDV_MSK (0x00000008) + #define DDRCMD_CR_DLLPITESTANDADC_ModeDV_MAX (0x00000001) + #define DDRCMD_CR_DLLPITESTANDADC_ModeDV_DEF (0x00000000) + #define DDRCMD_CR_DLLPITESTANDADC_ModeADC_OFF ( 4) + #define DDRCMD_CR_DLLPITESTANDADC_ModeADC_WID ( 1) + #define DDRCMD_CR_DLLPITESTANDADC_ModeADC_MSK (0x00000010) + #define DDRCMD_CR_DLLPITESTANDADC_ModeADC_MAX (0x00000001) + #define DDRCMD_CR_DLLPITESTANDADC_ModeADC_DEF (0x00000000) + #define DDRCMD_CR_DLLPITESTANDADC_LoadCount_OFF ( 5) + #define DDRCMD_CR_DLLPITESTANDADC_LoadCount_WID (10) + #define DDRCMD_CR_DLLPITESTANDADC_LoadCount_MSK (0x00007FE0) + #define DDRCMD_CR_DLLPITESTANDADC_LoadCount_MAX (0x000003FF) + #define DDRCMD_CR_DLLPITESTANDADC_CountStatus_OFF (15) + #define DDRCMD_CR_DLLPITESTANDADC_CountStatus_WID (10) + #define DDRCMD_CR_DLLPITESTANDADC_CountStatus_MSK (0x01FF8000) + #define DDRCMD_CR_DLLPITESTANDADC_CountStatus_MAX (0x000003FF) + #define DDRCMD_CR_DLLPITESTANDADC_CountStatus_DEF (0x00000000) + #define DDRCMD_CR_DLLPITESTANDADC_Spare_OFF (25) + #define DDRCMD_CR_DLLPITESTANDADC_Spare_WID ( 7) + #define DDRCMD_CR_DLLPITESTANDADC_Spare_MSK (0xFE000000) + #define DDRCMD_CR_DLLPITESTANDADC_Spare_MAX (0x0000007F) + +#define DDRCMDNCH0_CR_DDRCRCMDCOMP_REG (0x00001400) + #define DDRCMDNCH0_CR_DDRCRCMDCOMP_Scomp_OFF ( 0) + #define DDRCMDNCH0_CR_DDRCRCMDCOMP_Scomp_WID ( 6) + #define DDRCMDNCH0_CR_DDRCRCMDCOMP_Scomp_MSK (0x0000003F) + #define DDRCMDNCH0_CR_DDRCRCMDCOMP_Scomp_MAX (0x0000003F) + #define DDRCMDNCH0_CR_DDRCRCMDCOMP_Scomp_DEF (0x00000000) + #define DDRCMDNCH0_CR_DDRCRCMDCOMP_TcoComp_OFF ( 6) + #define DDRCMDNCH0_CR_DDRCRCMDCOMP_TcoComp_WID ( 6) + #define DDRCMDNCH0_CR_DDRCRCMDCOMP_TcoComp_MSK (0x00000FC0) + #define DDRCMDNCH0_CR_DDRCRCMDCOMP_TcoComp_MAX (0x0000003F) + #define DDRCMDNCH0_CR_DDRCRCMDCOMP_TcoComp_DEF (0x00000000) + #define DDRCMDNCH0_CR_DDRCRCMDCOMP_RcompDrvUp_OFF (12) + #define DDRCMDNCH0_CR_DDRCRCMDCOMP_RcompDrvUp_WID ( 6) + #define DDRCMDNCH0_CR_DDRCRCMDCOMP_RcompDrvUp_MSK (0x0003F000) + #define DDRCMDNCH0_CR_DDRCRCMDCOMP_RcompDrvUp_MAX (0x0000003F) + #define DDRCMDNCH0_CR_DDRCRCMDCOMP_RcompDrvUp_DEF (0x00000000) + #define DDRCMDNCH0_CR_DDRCRCMDCOMP_RcompDrvDown_OFF (18) + #define DDRCMDNCH0_CR_DDRCRCMDCOMP_RcompDrvDown_WID ( 6) + #define DDRCMDNCH0_CR_DDRCRCMDCOMP_RcompDrvDown_MSK (0x00FC0000) + #define DDRCMDNCH0_CR_DDRCRCMDCOMP_RcompDrvDown_MAX (0x0000003F) + #define DDRCMDNCH0_CR_DDRCRCMDCOMP_RcompDrvDown_DEF (0x00000000) + #define DDRCMDNCH0_CR_DDRCRCMDCOMP_LsComp_OFF (24) + #define DDRCMDNCH0_CR_DDRCRCMDCOMP_LsComp_WID ( 3) + #define DDRCMDNCH0_CR_DDRCRCMDCOMP_LsComp_MSK (0x07000000) + #define DDRCMDNCH0_CR_DDRCRCMDCOMP_LsComp_MAX (0x00000007) + #define DDRCMDNCH0_CR_DDRCRCMDCOMP_LsComp_DEF (0x00000004) + #define DDRCMDNCH0_CR_DDRCRCMDCOMP_Spare_OFF (27) + #define DDRCMDNCH0_CR_DDRCRCMDCOMP_Spare_WID ( 5) + #define DDRCMDNCH0_CR_DDRCRCMDCOMP_Spare_MSK (0xF8000000) + #define DDRCMDNCH0_CR_DDRCRCMDCOMP_Spare_MAX (0x0000001F) + #define DDRCMDNCH0_CR_DDRCRCMDCOMP_Spare_DEF (0x00000000) + +#define DDRCMDNCH0_CR_DDRCRCMDCOMPOFFSET_REG (0x00001404) + #define DDRCMDNCH0_CR_DDRCRCMDCOMPOFFSET_ScompOffset_OFF ( 0) + #define DDRCMDNCH0_CR_DDRCRCMDCOMPOFFSET_ScompOffset_WID ( 5) + #define DDRCMDNCH0_CR_DDRCRCMDCOMPOFFSET_ScompOffset_MSK (0x0000001F) + #define DDRCMDNCH0_CR_DDRCRCMDCOMPOFFSET_ScompOffset_MAX (0x0000001F) + #define DDRCMDNCH0_CR_DDRCRCMDCOMPOFFSET_ScompOffset_DEF (0x00000000) + #define DDRCMDNCH0_CR_DDRCRCMDCOMPOFFSET_TcoCompOffset_OFF ( 5) + #define DDRCMDNCH0_CR_DDRCRCMDCOMPOFFSET_TcoCompOffset_WID ( 4) + #define DDRCMDNCH0_CR_DDRCRCMDCOMPOFFSET_TcoCompOffset_MSK (0x000001E0) + #define DDRCMDNCH0_CR_DDRCRCMDCOMPOFFSET_TcoCompOffset_MAX (0x0000000F) + #define DDRCMDNCH0_CR_DDRCRCMDCOMPOFFSET_TcoCompOffset_DEF (0x00000000) + #define DDRCMDNCH0_CR_DDRCRCMDCOMPOFFSET_RcompDrvUpOffset_OFF ( 9) + #define DDRCMDNCH0_CR_DDRCRCMDCOMPOFFSET_RcompDrvUpOffset_WID ( 4) + #define DDRCMDNCH0_CR_DDRCRCMDCOMPOFFSET_RcompDrvUpOffset_MSK (0x00001E00) + #define DDRCMDNCH0_CR_DDRCRCMDCOMPOFFSET_RcompDrvUpOffset_MAX (0x0000000F) + #define DDRCMDNCH0_CR_DDRCRCMDCOMPOFFSET_RcompDrvUpOffset_DEF (0x00000000) + #define DDRCMDNCH0_CR_DDRCRCMDCOMPOFFSET_RcompDrvDownOffset_OFF (13) + #define DDRCMDNCH0_CR_DDRCRCMDCOMPOFFSET_RcompDrvDownOffset_WID ( 4) + #define DDRCMDNCH0_CR_DDRCRCMDCOMPOFFSET_RcompDrvDownOffset_MSK (0x0001E000) + #define DDRCMDNCH0_CR_DDRCRCMDCOMPOFFSET_RcompDrvDownOffset_MAX (0x0000000F) + #define DDRCMDNCH0_CR_DDRCRCMDCOMPOFFSET_RcompDrvDownOffset_DEF (0x00000000) + #define DDRCMDNCH0_CR_DDRCRCMDCOMPOFFSET_Spare_OFF (17) + #define DDRCMDNCH0_CR_DDRCRCMDCOMPOFFSET_Spare_WID (15) + #define DDRCMDNCH0_CR_DDRCRCMDCOMPOFFSET_Spare_MSK (0xFFFE0000) + #define DDRCMDNCH0_CR_DDRCRCMDCOMPOFFSET_Spare_MAX (0x00007FFF) + #define DDRCMDNCH0_CR_DDRCRCMDCOMPOFFSET_Spare_DEF (0x00000000) + +#define DDRCMDNCH0_CR_DDRCRCMDPICODING_REG (0x00001408) + #define DDRCMDNCH0_CR_DDRCRCMDPICODING_CmdPi0Code_OFF ( 0) + #define DDRCMDNCH0_CR_DDRCRCMDPICODING_CmdPi0Code_WID ( 7) + #define DDRCMDNCH0_CR_DDRCRCMDPICODING_CmdPi0Code_MSK (0x0000007F) + #define DDRCMDNCH0_CR_DDRCRCMDPICODING_CmdPi0Code_MAX (0x0000007F) + #define DDRCMDNCH0_CR_DDRCRCMDPICODING_CmdPi0Code_DEF (0x00000000) + #define DDRCMDNCH0_CR_DDRCRCMDPICODING_CmdPi1Code_OFF ( 7) + #define DDRCMDNCH0_CR_DDRCRCMDPICODING_CmdPi1Code_WID ( 7) + #define DDRCMDNCH0_CR_DDRCRCMDPICODING_CmdPi1Code_MSK (0x00003F80) + #define DDRCMDNCH0_CR_DDRCRCMDPICODING_CmdPi1Code_MAX (0x0000007F) + #define DDRCMDNCH0_CR_DDRCRCMDPICODING_CmdPi1Code_DEF (0x00000000) + #define DDRCMDNCH0_CR_DDRCRCMDPICODING_Spare_OFF (14) + #define DDRCMDNCH0_CR_DDRCRCMDPICODING_Spare_WID (18) + #define DDRCMDNCH0_CR_DDRCRCMDPICODING_Spare_MSK (0xFFFFC000) + #define DDRCMDNCH0_CR_DDRCRCMDPICODING_Spare_MAX (0x0003FFFF) + #define DDRCMDNCH0_CR_DDRCRCMDPICODING_Spare_DEF (0x00000000) + +#define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_REG (0x0000140C) + #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_RefPi_OFF ( 0) + #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_RefPi_WID ( 4) + #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_RefPi_MSK (0x0000000F) + #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_RefPi_MAX (0x0000000F) + #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_RefPi_DEF (0x00000000) + #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_DllMask_OFF ( 4) + #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_DllMask_WID ( 2) + #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_DllMask_MSK (0x00000030) + #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_DllMask_MAX (0x00000003) + #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_DllMask_DEF (0x00000000) + #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_DllRsvd1_OFF ( 6) + #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_DllRsvd1_WID ( 1) + #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_DllRsvd1_MSK (0x00000040) + #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_DllRsvd1_MAX (0x00000001) + #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_DllRsvd1_DEF (0x00000000) + #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_TxOn_OFF ( 7) + #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_TxOn_WID ( 1) + #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_TxOn_MSK (0x00000080) + #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_TxOn_MAX (0x00000001) + #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_TxOn_DEF (0x00000000) + #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_IntClkOn_OFF ( 8) + #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_IntClkOn_WID ( 1) + #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_IntClkOn_MSK (0x00000100) + #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_IntClkOn_MAX (0x00000001) + #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_IntClkOn_DEF (0x00000000) + #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_RepClkOn_OFF ( 9) + #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_RepClkOn_WID ( 1) + #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_RepClkOn_MSK (0x00000200) + #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_RepClkOn_MAX (0x00000001) + #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_RepClkOn_DEF (0x00000000) + #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_IOLBCtl_OFF (10) + #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_IOLBCtl_WID ( 2) + #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_IOLBCtl_MSK (0x00000C00) + #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_IOLBCtl_MAX (0x00000003) + #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_IOLBCtl_DEF (0x00000000) + #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_OdtMode_OFF (12) + #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_OdtMode_WID ( 1) + #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_OdtMode_MSK (0x00001000) + #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_OdtMode_MAX (0x00000001) + #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_OdtMode_DEF (0x00000000) + #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_CmdTxEq_OFF (13) + #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_CmdTxEq_WID ( 2) + #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_CmdTxEq_MSK (0x00006000) + #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_CmdTxEq_MAX (0x00000003) + #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_CmdTxEq_DEF (0x00000000) + #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_EarlyWeakDrive_OFF (15) + #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_EarlyWeakDrive_WID ( 2) + #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_EarlyWeakDrive_MSK (0x00018000) + #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_EarlyWeakDrive_MAX (0x00000003) + #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_EarlyWeakDrive_DEF (0x00000000) + #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_Reserved_OFF (17) + #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_Reserved_WID ( 4) + #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_Reserved_MSK (0x001E0000) + #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_Reserved_MAX (0x0000000F) + #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_Reserved_DEF (0x00000000) + #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_RxVref_OFF (21) + #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_RxVref_WID ( 6) + #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_RxVref_MSK (0x07E00000) + #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_RxVref_MAX (0x0000003F) + #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_RxVref_DEF (0x00000000) + #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_VccddqHi_OFF (27) + #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_VccddqHi_WID ( 1) + #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_VccddqHi_MSK (0x08000000) + #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_VccddqHi_MAX (0x00000001) + #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_VccddqHi_DEF (0x00000000) + #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_DllWeakLock_OFF (28) + #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_DllWeakLock_WID ( 1) + #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_DllWeakLock_MSK (0x10000000) + #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_DllWeakLock_MAX (0x00000001) + #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_DllWeakLock_DEF (0x00000000) + #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_LPDDR_Mode_OFF (29) + #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_LPDDR_Mode_WID ( 1) + #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_LPDDR_Mode_MSK (0x20000000) + #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_LPDDR_Mode_MAX (0x00000001) + #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_LPDDR_Mode_DEF (0x00000000) + #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_LPDdrCAA_Dis_OFF (30) + #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_LPDdrCAA_Dis_WID ( 1) + #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_LPDdrCAA_Dis_MSK (0x40000000) + #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_LPDdrCAA_Dis_MAX (0x00000001) + #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_LPDdrCAA_Dis_DEF (0x00000000) + #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_LPDdrCAB_Dis_OFF (31) + #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_LPDdrCAB_Dis_WID ( 1) + #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_LPDdrCAB_Dis_MSK (0x80000000) + #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_LPDdrCAB_Dis_MAX (0x00000001) + #define DDRCMDNCH0_CR_DDRCRCMDCONTROLS_LPDdrCAB_Dis_DEF (0x00000000) + +#define DDRCMDNCH0_CR_DLLPITESTANDADC_REG (0x00001424) + #define DDRCMDNCH0_CR_DLLPITESTANDADC_RunTest_OFF ( 0) + #define DDRCMDNCH0_CR_DLLPITESTANDADC_RunTest_WID ( 1) + #define DDRCMDNCH0_CR_DLLPITESTANDADC_RunTest_MSK (0x00000001) + #define DDRCMDNCH0_CR_DLLPITESTANDADC_RunTest_MAX (0x00000001) + #define DDRCMDNCH0_CR_DLLPITESTANDADC_RunTest_DEF (0x00000000) + #define DDRCMDNCH0_CR_DLLPITESTANDADC_Load_OFF ( 1) + #define DDRCMDNCH0_CR_DLLPITESTANDADC_Load_WID ( 1) + #define DDRCMDNCH0_CR_DLLPITESTANDADC_Load_MSK (0x00000002) + #define DDRCMDNCH0_CR_DLLPITESTANDADC_Load_MAX (0x00000001) + #define DDRCMDNCH0_CR_DLLPITESTANDADC_Load_DEF (0x00000000) + #define DDRCMDNCH0_CR_DLLPITESTANDADC_ModeHVM_OFF ( 2) + #define DDRCMDNCH0_CR_DLLPITESTANDADC_ModeHVM_WID ( 1) + #define DDRCMDNCH0_CR_DLLPITESTANDADC_ModeHVM_MSK (0x00000004) + #define DDRCMDNCH0_CR_DLLPITESTANDADC_ModeHVM_MAX (0x00000001) + #define DDRCMDNCH0_CR_DLLPITESTANDADC_ModeHVM_DEF (0x00000000) + #define DDRCMDNCH0_CR_DLLPITESTANDADC_ModeDV_OFF ( 3) + #define DDRCMDNCH0_CR_DLLPITESTANDADC_ModeDV_WID ( 1) + #define DDRCMDNCH0_CR_DLLPITESTANDADC_ModeDV_MSK (0x00000008) + #define DDRCMDNCH0_CR_DLLPITESTANDADC_ModeDV_MAX (0x00000001) + #define DDRCMDNCH0_CR_DLLPITESTANDADC_ModeDV_DEF (0x00000000) + #define DDRCMDNCH0_CR_DLLPITESTANDADC_ModeADC_OFF ( 4) + #define DDRCMDNCH0_CR_DLLPITESTANDADC_ModeADC_WID ( 1) + #define DDRCMDNCH0_CR_DLLPITESTANDADC_ModeADC_MSK (0x00000010) + #define DDRCMDNCH0_CR_DLLPITESTANDADC_ModeADC_MAX (0x00000001) + #define DDRCMDNCH0_CR_DLLPITESTANDADC_ModeADC_DEF (0x00000000) + #define DDRCMDNCH0_CR_DLLPITESTANDADC_LoadCount_OFF ( 5) + #define DDRCMDNCH0_CR_DLLPITESTANDADC_LoadCount_WID (10) + #define DDRCMDNCH0_CR_DLLPITESTANDADC_LoadCount_MSK (0x00007FE0) + #define DDRCMDNCH0_CR_DLLPITESTANDADC_LoadCount_MAX (0x000003FF) + #define DDRCMDNCH0_CR_DLLPITESTANDADC_CountStatus_OFF (15) + #define DDRCMDNCH0_CR_DLLPITESTANDADC_CountStatus_WID (10) + #define DDRCMDNCH0_CR_DLLPITESTANDADC_CountStatus_MSK (0x01FF8000) + #define DDRCMDNCH0_CR_DLLPITESTANDADC_CountStatus_MAX (0x000003FF) + #define DDRCMDNCH0_CR_DLLPITESTANDADC_CountStatus_DEF (0x00000000) + #define DDRCMDNCH0_CR_DLLPITESTANDADC_Spare_OFF (25) + #define DDRCMDNCH0_CR_DLLPITESTANDADC_Spare_WID ( 7) + #define DDRCMDNCH0_CR_DLLPITESTANDADC_Spare_MSK (0xFE000000) + #define DDRCMDNCH0_CR_DLLPITESTANDADC_Spare_MAX (0x0000007F) + +#define DDRCMDNCH1_CR_DDRCRCMDCOMP_REG (0x00001500) + #define DDRCMDNCH1_CR_DDRCRCMDCOMP_Scomp_OFF ( 0) + #define DDRCMDNCH1_CR_DDRCRCMDCOMP_Scomp_WID ( 6) + #define DDRCMDNCH1_CR_DDRCRCMDCOMP_Scomp_MSK (0x0000003F) + #define DDRCMDNCH1_CR_DDRCRCMDCOMP_Scomp_MAX (0x0000003F) + #define DDRCMDNCH1_CR_DDRCRCMDCOMP_Scomp_DEF (0x00000000) + #define DDRCMDNCH1_CR_DDRCRCMDCOMP_TcoComp_OFF ( 6) + #define DDRCMDNCH1_CR_DDRCRCMDCOMP_TcoComp_WID ( 6) + #define DDRCMDNCH1_CR_DDRCRCMDCOMP_TcoComp_MSK (0x00000FC0) + #define DDRCMDNCH1_CR_DDRCRCMDCOMP_TcoComp_MAX (0x0000003F) + #define DDRCMDNCH1_CR_DDRCRCMDCOMP_TcoComp_DEF (0x00000000) + #define DDRCMDNCH1_CR_DDRCRCMDCOMP_RcompDrvUp_OFF (12) + #define DDRCMDNCH1_CR_DDRCRCMDCOMP_RcompDrvUp_WID ( 6) + #define DDRCMDNCH1_CR_DDRCRCMDCOMP_RcompDrvUp_MSK (0x0003F000) + #define DDRCMDNCH1_CR_DDRCRCMDCOMP_RcompDrvUp_MAX (0x0000003F) + #define DDRCMDNCH1_CR_DDRCRCMDCOMP_RcompDrvUp_DEF (0x00000000) + #define DDRCMDNCH1_CR_DDRCRCMDCOMP_RcompDrvDown_OFF (18) + #define DDRCMDNCH1_CR_DDRCRCMDCOMP_RcompDrvDown_WID ( 6) + #define DDRCMDNCH1_CR_DDRCRCMDCOMP_RcompDrvDown_MSK (0x00FC0000) + #define DDRCMDNCH1_CR_DDRCRCMDCOMP_RcompDrvDown_MAX (0x0000003F) + #define DDRCMDNCH1_CR_DDRCRCMDCOMP_RcompDrvDown_DEF (0x00000000) + #define DDRCMDNCH1_CR_DDRCRCMDCOMP_LsComp_OFF (24) + #define DDRCMDNCH1_CR_DDRCRCMDCOMP_LsComp_WID ( 3) + #define DDRCMDNCH1_CR_DDRCRCMDCOMP_LsComp_MSK (0x07000000) + #define DDRCMDNCH1_CR_DDRCRCMDCOMP_LsComp_MAX (0x00000007) + #define DDRCMDNCH1_CR_DDRCRCMDCOMP_LsComp_DEF (0x00000004) + #define DDRCMDNCH1_CR_DDRCRCMDCOMP_Spare_OFF (27) + #define DDRCMDNCH1_CR_DDRCRCMDCOMP_Spare_WID ( 5) + #define DDRCMDNCH1_CR_DDRCRCMDCOMP_Spare_MSK (0xF8000000) + #define DDRCMDNCH1_CR_DDRCRCMDCOMP_Spare_MAX (0x0000001F) + #define DDRCMDNCH1_CR_DDRCRCMDCOMP_Spare_DEF (0x00000000) + +#define DDRCMDNCH1_CR_DDRCRCMDCOMPOFFSET_REG (0x00001504) + #define DDRCMDNCH1_CR_DDRCRCMDCOMPOFFSET_ScompOffset_OFF ( 0) + #define DDRCMDNCH1_CR_DDRCRCMDCOMPOFFSET_ScompOffset_WID ( 5) + #define DDRCMDNCH1_CR_DDRCRCMDCOMPOFFSET_ScompOffset_MSK (0x0000001F) + #define DDRCMDNCH1_CR_DDRCRCMDCOMPOFFSET_ScompOffset_MAX (0x0000001F) + #define DDRCMDNCH1_CR_DDRCRCMDCOMPOFFSET_ScompOffset_DEF (0x00000000) + #define DDRCMDNCH1_CR_DDRCRCMDCOMPOFFSET_TcoCompOffset_OFF ( 5) + #define DDRCMDNCH1_CR_DDRCRCMDCOMPOFFSET_TcoCompOffset_WID ( 4) + #define DDRCMDNCH1_CR_DDRCRCMDCOMPOFFSET_TcoCompOffset_MSK (0x000001E0) + #define DDRCMDNCH1_CR_DDRCRCMDCOMPOFFSET_TcoCompOffset_MAX (0x0000000F) + #define DDRCMDNCH1_CR_DDRCRCMDCOMPOFFSET_TcoCompOffset_DEF (0x00000000) + #define DDRCMDNCH1_CR_DDRCRCMDCOMPOFFSET_RcompDrvUpOffset_OFF ( 9) + #define DDRCMDNCH1_CR_DDRCRCMDCOMPOFFSET_RcompDrvUpOffset_WID ( 4) + #define DDRCMDNCH1_CR_DDRCRCMDCOMPOFFSET_RcompDrvUpOffset_MSK (0x00001E00) + #define DDRCMDNCH1_CR_DDRCRCMDCOMPOFFSET_RcompDrvUpOffset_MAX (0x0000000F) + #define DDRCMDNCH1_CR_DDRCRCMDCOMPOFFSET_RcompDrvUpOffset_DEF (0x00000000) + #define DDRCMDNCH1_CR_DDRCRCMDCOMPOFFSET_RcompDrvDownOffset_OFF (13) + #define DDRCMDNCH1_CR_DDRCRCMDCOMPOFFSET_RcompDrvDownOffset_WID ( 4) + #define DDRCMDNCH1_CR_DDRCRCMDCOMPOFFSET_RcompDrvDownOffset_MSK (0x0001E000) + #define DDRCMDNCH1_CR_DDRCRCMDCOMPOFFSET_RcompDrvDownOffset_MAX (0x0000000F) + #define DDRCMDNCH1_CR_DDRCRCMDCOMPOFFSET_RcompDrvDownOffset_DEF (0x00000000) + #define DDRCMDNCH1_CR_DDRCRCMDCOMPOFFSET_Spare_OFF (17) + #define DDRCMDNCH1_CR_DDRCRCMDCOMPOFFSET_Spare_WID (15) + #define DDRCMDNCH1_CR_DDRCRCMDCOMPOFFSET_Spare_MSK (0xFFFE0000) + #define DDRCMDNCH1_CR_DDRCRCMDCOMPOFFSET_Spare_MAX (0x00007FFF) + #define DDRCMDNCH1_CR_DDRCRCMDCOMPOFFSET_Spare_DEF (0x00000000) + +#define DDRCMDNCH1_CR_DDRCRCMDPICODING_REG (0x00001508) + #define DDRCMDNCH1_CR_DDRCRCMDPICODING_CmdPi0Code_OFF ( 0) + #define DDRCMDNCH1_CR_DDRCRCMDPICODING_CmdPi0Code_WID ( 7) + #define DDRCMDNCH1_CR_DDRCRCMDPICODING_CmdPi0Code_MSK (0x0000007F) + #define DDRCMDNCH1_CR_DDRCRCMDPICODING_CmdPi0Code_MAX (0x0000007F) + #define DDRCMDNCH1_CR_DDRCRCMDPICODING_CmdPi0Code_DEF (0x00000000) + #define DDRCMDNCH1_CR_DDRCRCMDPICODING_CmdPi1Code_OFF ( 7) + #define DDRCMDNCH1_CR_DDRCRCMDPICODING_CmdPi1Code_WID ( 7) + #define DDRCMDNCH1_CR_DDRCRCMDPICODING_CmdPi1Code_MSK (0x00003F80) + #define DDRCMDNCH1_CR_DDRCRCMDPICODING_CmdPi1Code_MAX (0x0000007F) + #define DDRCMDNCH1_CR_DDRCRCMDPICODING_CmdPi1Code_DEF (0x00000000) + #define DDRCMDNCH1_CR_DDRCRCMDPICODING_Spare_OFF (14) + #define DDRCMDNCH1_CR_DDRCRCMDPICODING_Spare_WID (18) + #define DDRCMDNCH1_CR_DDRCRCMDPICODING_Spare_MSK (0xFFFFC000) + #define DDRCMDNCH1_CR_DDRCRCMDPICODING_Spare_MAX (0x0003FFFF) + #define DDRCMDNCH1_CR_DDRCRCMDPICODING_Spare_DEF (0x00000000) + +#define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_REG (0x0000150C) + #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_RefPi_OFF ( 0) + #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_RefPi_WID ( 4) + #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_RefPi_MSK (0x0000000F) + #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_RefPi_MAX (0x0000000F) + #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_RefPi_DEF (0x00000000) + #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_DllMask_OFF ( 4) + #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_DllMask_WID ( 2) + #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_DllMask_MSK (0x00000030) + #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_DllMask_MAX (0x00000003) + #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_DllMask_DEF (0x00000000) + #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_DllRsvd1_OFF ( 6) + #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_DllRsvd1_WID ( 1) + #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_DllRsvd1_MSK (0x00000040) + #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_DllRsvd1_MAX (0x00000001) + #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_DllRsvd1_DEF (0x00000000) + #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_TxOn_OFF ( 7) + #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_TxOn_WID ( 1) + #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_TxOn_MSK (0x00000080) + #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_TxOn_MAX (0x00000001) + #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_TxOn_DEF (0x00000000) + #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_IntClkOn_OFF ( 8) + #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_IntClkOn_WID ( 1) + #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_IntClkOn_MSK (0x00000100) + #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_IntClkOn_MAX (0x00000001) + #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_IntClkOn_DEF (0x00000000) + #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_RepClkOn_OFF ( 9) + #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_RepClkOn_WID ( 1) + #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_RepClkOn_MSK (0x00000200) + #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_RepClkOn_MAX (0x00000001) + #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_RepClkOn_DEF (0x00000000) + #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_IOLBCtl_OFF (10) + #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_IOLBCtl_WID ( 2) + #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_IOLBCtl_MSK (0x00000C00) + #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_IOLBCtl_MAX (0x00000003) + #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_IOLBCtl_DEF (0x00000000) + #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_OdtMode_OFF (12) + #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_OdtMode_WID ( 1) + #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_OdtMode_MSK (0x00001000) + #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_OdtMode_MAX (0x00000001) + #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_OdtMode_DEF (0x00000000) + #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_CmdTxEq_OFF (13) + #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_CmdTxEq_WID ( 2) + #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_CmdTxEq_MSK (0x00006000) + #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_CmdTxEq_MAX (0x00000003) + #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_CmdTxEq_DEF (0x00000000) + #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_EarlyWeakDrive_OFF (15) + #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_EarlyWeakDrive_WID ( 2) + #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_EarlyWeakDrive_MSK (0x00018000) + #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_EarlyWeakDrive_MAX (0x00000003) + #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_EarlyWeakDrive_DEF (0x00000000) + #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_Reserved_OFF (17) + #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_Reserved_WID ( 4) + #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_Reserved_MSK (0x001E0000) + #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_Reserved_MAX (0x0000000F) + #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_Reserved_DEF (0x00000000) + #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_RxVref_OFF (21) + #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_RxVref_WID ( 6) + #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_RxVref_MSK (0x07E00000) + #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_RxVref_MAX (0x0000003F) + #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_RxVref_DEF (0x00000000) + #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_VccddqHi_OFF (27) + #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_VccddqHi_WID ( 1) + #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_VccddqHi_MSK (0x08000000) + #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_VccddqHi_MAX (0x00000001) + #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_VccddqHi_DEF (0x00000000) + #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_DllWeakLock_OFF (28) + #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_DllWeakLock_WID ( 1) + #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_DllWeakLock_MSK (0x10000000) + #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_DllWeakLock_MAX (0x00000001) + #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_DllWeakLock_DEF (0x00000000) + #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_LPDDR_Mode_OFF (29) + #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_LPDDR_Mode_WID ( 1) + #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_LPDDR_Mode_MSK (0x20000000) + #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_LPDDR_Mode_MAX (0x00000001) + #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_LPDDR_Mode_DEF (0x00000000) + #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_LPDdrCAA_Dis_OFF (30) + #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_LPDdrCAA_Dis_WID ( 1) + #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_LPDdrCAA_Dis_MSK (0x40000000) + #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_LPDdrCAA_Dis_MAX (0x00000001) + #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_LPDdrCAA_Dis_DEF (0x00000000) + #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_LPDdrCAB_Dis_OFF (31) + #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_LPDdrCAB_Dis_WID ( 1) + #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_LPDdrCAB_Dis_MSK (0x80000000) + #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_LPDdrCAB_Dis_MAX (0x00000001) + #define DDRCMDNCH1_CR_DDRCRCMDCONTROLS_LPDdrCAB_Dis_DEF (0x00000000) + +#define DDRCMDNCH1_CR_DLLPITESTANDADC_REG (0x00001524) + #define DDRCMDNCH1_CR_DLLPITESTANDADC_RunTest_OFF ( 0) + #define DDRCMDNCH1_CR_DLLPITESTANDADC_RunTest_WID ( 1) + #define DDRCMDNCH1_CR_DLLPITESTANDADC_RunTest_MSK (0x00000001) + #define DDRCMDNCH1_CR_DLLPITESTANDADC_RunTest_MAX (0x00000001) + #define DDRCMDNCH1_CR_DLLPITESTANDADC_RunTest_DEF (0x00000000) + #define DDRCMDNCH1_CR_DLLPITESTANDADC_Load_OFF ( 1) + #define DDRCMDNCH1_CR_DLLPITESTANDADC_Load_WID ( 1) + #define DDRCMDNCH1_CR_DLLPITESTANDADC_Load_MSK (0x00000002) + #define DDRCMDNCH1_CR_DLLPITESTANDADC_Load_MAX (0x00000001) + #define DDRCMDNCH1_CR_DLLPITESTANDADC_Load_DEF (0x00000000) + #define DDRCMDNCH1_CR_DLLPITESTANDADC_ModeHVM_OFF ( 2) + #define DDRCMDNCH1_CR_DLLPITESTANDADC_ModeHVM_WID ( 1) + #define DDRCMDNCH1_CR_DLLPITESTANDADC_ModeHVM_MSK (0x00000004) + #define DDRCMDNCH1_CR_DLLPITESTANDADC_ModeHVM_MAX (0x00000001) + #define DDRCMDNCH1_CR_DLLPITESTANDADC_ModeHVM_DEF (0x00000000) + #define DDRCMDNCH1_CR_DLLPITESTANDADC_ModeDV_OFF ( 3) + #define DDRCMDNCH1_CR_DLLPITESTANDADC_ModeDV_WID ( 1) + #define DDRCMDNCH1_CR_DLLPITESTANDADC_ModeDV_MSK (0x00000008) + #define DDRCMDNCH1_CR_DLLPITESTANDADC_ModeDV_MAX (0x00000001) + #define DDRCMDNCH1_CR_DLLPITESTANDADC_ModeDV_DEF (0x00000000) + #define DDRCMDNCH1_CR_DLLPITESTANDADC_ModeADC_OFF ( 4) + #define DDRCMDNCH1_CR_DLLPITESTANDADC_ModeADC_WID ( 1) + #define DDRCMDNCH1_CR_DLLPITESTANDADC_ModeADC_MSK (0x00000010) + #define DDRCMDNCH1_CR_DLLPITESTANDADC_ModeADC_MAX (0x00000001) + #define DDRCMDNCH1_CR_DLLPITESTANDADC_ModeADC_DEF (0x00000000) + #define DDRCMDNCH1_CR_DLLPITESTANDADC_LoadCount_OFF ( 5) + #define DDRCMDNCH1_CR_DLLPITESTANDADC_LoadCount_WID (10) + #define DDRCMDNCH1_CR_DLLPITESTANDADC_LoadCount_MSK (0x00007FE0) + #define DDRCMDNCH1_CR_DLLPITESTANDADC_LoadCount_MAX (0x000003FF) + #define DDRCMDNCH1_CR_DLLPITESTANDADC_CountStatus_OFF (15) + #define DDRCMDNCH1_CR_DLLPITESTANDADC_CountStatus_WID (10) + #define DDRCMDNCH1_CR_DLLPITESTANDADC_CountStatus_MSK (0x01FF8000) + #define DDRCMDNCH1_CR_DLLPITESTANDADC_CountStatus_MAX (0x000003FF) + #define DDRCMDNCH1_CR_DLLPITESTANDADC_CountStatus_DEF (0x00000000) + #define DDRCMDNCH1_CR_DLLPITESTANDADC_Spare_OFF (25) + #define DDRCMDNCH1_CR_DLLPITESTANDADC_Spare_WID ( 7) + #define DDRCMDNCH1_CR_DLLPITESTANDADC_Spare_MSK (0xFE000000) + #define DDRCMDNCH1_CR_DLLPITESTANDADC_Spare_MAX (0x0000007F) + +#define DDRCMDSCH0_CR_DDRCRCMDCOMP_REG (0x00001A00) + #define DDRCMDSCH0_CR_DDRCRCMDCOMP_Scomp_OFF ( 0) + #define DDRCMDSCH0_CR_DDRCRCMDCOMP_Scomp_WID ( 6) + #define DDRCMDSCH0_CR_DDRCRCMDCOMP_Scomp_MSK (0x0000003F) + #define DDRCMDSCH0_CR_DDRCRCMDCOMP_Scomp_MAX (0x0000003F) + #define DDRCMDSCH0_CR_DDRCRCMDCOMP_Scomp_DEF (0x00000000) + #define DDRCMDSCH0_CR_DDRCRCMDCOMP_TcoComp_OFF ( 6) + #define DDRCMDSCH0_CR_DDRCRCMDCOMP_TcoComp_WID ( 6) + #define DDRCMDSCH0_CR_DDRCRCMDCOMP_TcoComp_MSK (0x00000FC0) + #define DDRCMDSCH0_CR_DDRCRCMDCOMP_TcoComp_MAX (0x0000003F) + #define DDRCMDSCH0_CR_DDRCRCMDCOMP_TcoComp_DEF (0x00000000) + #define DDRCMDSCH0_CR_DDRCRCMDCOMP_RcompDrvUp_OFF (12) + #define DDRCMDSCH0_CR_DDRCRCMDCOMP_RcompDrvUp_WID ( 6) + #define DDRCMDSCH0_CR_DDRCRCMDCOMP_RcompDrvUp_MSK (0x0003F000) + #define DDRCMDSCH0_CR_DDRCRCMDCOMP_RcompDrvUp_MAX (0x0000003F) + #define DDRCMDSCH0_CR_DDRCRCMDCOMP_RcompDrvUp_DEF (0x00000000) + #define DDRCMDSCH0_CR_DDRCRCMDCOMP_RcompDrvDown_OFF (18) + #define DDRCMDSCH0_CR_DDRCRCMDCOMP_RcompDrvDown_WID ( 6) + #define DDRCMDSCH0_CR_DDRCRCMDCOMP_RcompDrvDown_MSK (0x00FC0000) + #define DDRCMDSCH0_CR_DDRCRCMDCOMP_RcompDrvDown_MAX (0x0000003F) + #define DDRCMDSCH0_CR_DDRCRCMDCOMP_RcompDrvDown_DEF (0x00000000) + #define DDRCMDSCH0_CR_DDRCRCMDCOMP_LsComp_OFF (24) + #define DDRCMDSCH0_CR_DDRCRCMDCOMP_LsComp_WID ( 3) + #define DDRCMDSCH0_CR_DDRCRCMDCOMP_LsComp_MSK (0x07000000) + #define DDRCMDSCH0_CR_DDRCRCMDCOMP_LsComp_MAX (0x00000007) + #define DDRCMDSCH0_CR_DDRCRCMDCOMP_LsComp_DEF (0x00000004) + #define DDRCMDSCH0_CR_DDRCRCMDCOMP_Spare_OFF (27) + #define DDRCMDSCH0_CR_DDRCRCMDCOMP_Spare_WID ( 5) + #define DDRCMDSCH0_CR_DDRCRCMDCOMP_Spare_MSK (0xF8000000) + #define DDRCMDSCH0_CR_DDRCRCMDCOMP_Spare_MAX (0x0000001F) + #define DDRCMDSCH0_CR_DDRCRCMDCOMP_Spare_DEF (0x00000000) + +#define DDRCMDSCH0_CR_DDRCRCMDCOMPOFFSET_REG (0x00001A04) + #define DDRCMDSCH0_CR_DDRCRCMDCOMPOFFSET_ScompOffset_OFF ( 0) + #define DDRCMDSCH0_CR_DDRCRCMDCOMPOFFSET_ScompOffset_WID ( 5) + #define DDRCMDSCH0_CR_DDRCRCMDCOMPOFFSET_ScompOffset_MSK (0x0000001F) + #define DDRCMDSCH0_CR_DDRCRCMDCOMPOFFSET_ScompOffset_MAX (0x0000001F) + #define DDRCMDSCH0_CR_DDRCRCMDCOMPOFFSET_ScompOffset_DEF (0x00000000) + #define DDRCMDSCH0_CR_DDRCRCMDCOMPOFFSET_TcoCompOffset_OFF ( 5) + #define DDRCMDSCH0_CR_DDRCRCMDCOMPOFFSET_TcoCompOffset_WID ( 4) + #define DDRCMDSCH0_CR_DDRCRCMDCOMPOFFSET_TcoCompOffset_MSK (0x000001E0) + #define DDRCMDSCH0_CR_DDRCRCMDCOMPOFFSET_TcoCompOffset_MAX (0x0000000F) + #define DDRCMDSCH0_CR_DDRCRCMDCOMPOFFSET_TcoCompOffset_DEF (0x00000000) + #define DDRCMDSCH0_CR_DDRCRCMDCOMPOFFSET_RcompDrvUpOffset_OFF ( 9) + #define DDRCMDSCH0_CR_DDRCRCMDCOMPOFFSET_RcompDrvUpOffset_WID ( 4) + #define DDRCMDSCH0_CR_DDRCRCMDCOMPOFFSET_RcompDrvUpOffset_MSK (0x00001E00) + #define DDRCMDSCH0_CR_DDRCRCMDCOMPOFFSET_RcompDrvUpOffset_MAX (0x0000000F) + #define DDRCMDSCH0_CR_DDRCRCMDCOMPOFFSET_RcompDrvUpOffset_DEF (0x00000000) + #define DDRCMDSCH0_CR_DDRCRCMDCOMPOFFSET_RcompDrvDownOffset_OFF (13) + #define DDRCMDSCH0_CR_DDRCRCMDCOMPOFFSET_RcompDrvDownOffset_WID ( 4) + #define DDRCMDSCH0_CR_DDRCRCMDCOMPOFFSET_RcompDrvDownOffset_MSK (0x0001E000) + #define DDRCMDSCH0_CR_DDRCRCMDCOMPOFFSET_RcompDrvDownOffset_MAX (0x0000000F) + #define DDRCMDSCH0_CR_DDRCRCMDCOMPOFFSET_RcompDrvDownOffset_DEF (0x00000000) + #define DDRCMDSCH0_CR_DDRCRCMDCOMPOFFSET_Spare_OFF (17) + #define DDRCMDSCH0_CR_DDRCRCMDCOMPOFFSET_Spare_WID (15) + #define DDRCMDSCH0_CR_DDRCRCMDCOMPOFFSET_Spare_MSK (0xFFFE0000) + #define DDRCMDSCH0_CR_DDRCRCMDCOMPOFFSET_Spare_MAX (0x00007FFF) + #define DDRCMDSCH0_CR_DDRCRCMDCOMPOFFSET_Spare_DEF (0x00000000) + +#define DDRCMDSCH0_CR_DDRCRCMDPICODING_REG (0x00001A08) + #define DDRCMDSCH0_CR_DDRCRCMDPICODING_CmdPi0Code_OFF ( 0) + #define DDRCMDSCH0_CR_DDRCRCMDPICODING_CmdPi0Code_WID ( 7) + #define DDRCMDSCH0_CR_DDRCRCMDPICODING_CmdPi0Code_MSK (0x0000007F) + #define DDRCMDSCH0_CR_DDRCRCMDPICODING_CmdPi0Code_MAX (0x0000007F) + #define DDRCMDSCH0_CR_DDRCRCMDPICODING_CmdPi0Code_DEF (0x00000000) + #define DDRCMDSCH0_CR_DDRCRCMDPICODING_CmdPi1Code_OFF ( 7) + #define DDRCMDSCH0_CR_DDRCRCMDPICODING_CmdPi1Code_WID ( 7) + #define DDRCMDSCH0_CR_DDRCRCMDPICODING_CmdPi1Code_MSK (0x00003F80) + #define DDRCMDSCH0_CR_DDRCRCMDPICODING_CmdPi1Code_MAX (0x0000007F) + #define DDRCMDSCH0_CR_DDRCRCMDPICODING_CmdPi1Code_DEF (0x00000000) + #define DDRCMDSCH0_CR_DDRCRCMDPICODING_Spare_OFF (14) + #define DDRCMDSCH0_CR_DDRCRCMDPICODING_Spare_WID (18) + #define DDRCMDSCH0_CR_DDRCRCMDPICODING_Spare_MSK (0xFFFFC000) + #define DDRCMDSCH0_CR_DDRCRCMDPICODING_Spare_MAX (0x0003FFFF) + #define DDRCMDSCH0_CR_DDRCRCMDPICODING_Spare_DEF (0x00000000) + +#define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_REG (0x00001A0C) + #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_RefPi_OFF ( 0) + #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_RefPi_WID ( 4) + #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_RefPi_MSK (0x0000000F) + #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_RefPi_MAX (0x0000000F) + #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_RefPi_DEF (0x00000000) + #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_DllMask_OFF ( 4) + #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_DllMask_WID ( 2) + #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_DllMask_MSK (0x00000030) + #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_DllMask_MAX (0x00000003) + #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_DllMask_DEF (0x00000000) + #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_DllRsvd1_OFF ( 6) + #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_DllRsvd1_WID ( 1) + #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_DllRsvd1_MSK (0x00000040) + #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_DllRsvd1_MAX (0x00000001) + #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_DllRsvd1_DEF (0x00000000) + #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_TxOn_OFF ( 7) + #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_TxOn_WID ( 1) + #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_TxOn_MSK (0x00000080) + #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_TxOn_MAX (0x00000001) + #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_TxOn_DEF (0x00000000) + #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_IntClkOn_OFF ( 8) + #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_IntClkOn_WID ( 1) + #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_IntClkOn_MSK (0x00000100) + #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_IntClkOn_MAX (0x00000001) + #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_IntClkOn_DEF (0x00000000) + #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_RepClkOn_OFF ( 9) + #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_RepClkOn_WID ( 1) + #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_RepClkOn_MSK (0x00000200) + #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_RepClkOn_MAX (0x00000001) + #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_RepClkOn_DEF (0x00000000) + #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_IOLBCtl_OFF (10) + #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_IOLBCtl_WID ( 2) + #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_IOLBCtl_MSK (0x00000C00) + #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_IOLBCtl_MAX (0x00000003) + #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_IOLBCtl_DEF (0x00000000) + #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_OdtMode_OFF (12) + #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_OdtMode_WID ( 1) + #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_OdtMode_MSK (0x00001000) + #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_OdtMode_MAX (0x00000001) + #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_OdtMode_DEF (0x00000000) + #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_CmdTxEq_OFF (13) + #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_CmdTxEq_WID ( 2) + #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_CmdTxEq_MSK (0x00006000) + #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_CmdTxEq_MAX (0x00000003) + #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_CmdTxEq_DEF (0x00000000) + #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_EarlyWeakDrive_OFF (15) + #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_EarlyWeakDrive_WID ( 2) + #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_EarlyWeakDrive_MSK (0x00018000) + #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_EarlyWeakDrive_MAX (0x00000003) + #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_EarlyWeakDrive_DEF (0x00000000) + #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_Reserved_OFF (17) + #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_Reserved_WID ( 4) + #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_Reserved_MSK (0x001E0000) + #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_Reserved_MAX (0x0000000F) + #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_Reserved_DEF (0x00000000) + #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_RxVref_OFF (21) + #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_RxVref_WID ( 6) + #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_RxVref_MSK (0x07E00000) + #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_RxVref_MAX (0x0000003F) + #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_RxVref_DEF (0x00000000) + #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_VccddqHi_OFF (27) + #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_VccddqHi_WID ( 1) + #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_VccddqHi_MSK (0x08000000) + #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_VccddqHi_MAX (0x00000001) + #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_VccddqHi_DEF (0x00000000) + #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_DllWeakLock_OFF (28) + #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_DllWeakLock_WID ( 1) + #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_DllWeakLock_MSK (0x10000000) + #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_DllWeakLock_MAX (0x00000001) + #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_DllWeakLock_DEF (0x00000000) + #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_LPDDR_Mode_OFF (29) + #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_LPDDR_Mode_WID ( 1) + #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_LPDDR_Mode_MSK (0x20000000) + #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_LPDDR_Mode_MAX (0x00000001) + #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_LPDDR_Mode_DEF (0x00000000) + #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_LPDdrCAA_Dis_OFF (30) + #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_LPDdrCAA_Dis_WID ( 1) + #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_LPDdrCAA_Dis_MSK (0x40000000) + #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_LPDdrCAA_Dis_MAX (0x00000001) + #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_LPDdrCAA_Dis_DEF (0x00000000) + #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_LPDdrCAB_Dis_OFF (31) + #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_LPDdrCAB_Dis_WID ( 1) + #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_LPDdrCAB_Dis_MSK (0x80000000) + #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_LPDdrCAB_Dis_MAX (0x00000001) + #define DDRCMDSCH0_CR_DDRCRCMDCONTROLS_LPDdrCAB_Dis_DEF (0x00000000) + +#define DDRCMDSCH0_CR_DLLPITESTANDADC_REG (0x00001A24) + #define DDRCMDSCH0_CR_DLLPITESTANDADC_RunTest_OFF ( 0) + #define DDRCMDSCH0_CR_DLLPITESTANDADC_RunTest_WID ( 1) + #define DDRCMDSCH0_CR_DLLPITESTANDADC_RunTest_MSK (0x00000001) + #define DDRCMDSCH0_CR_DLLPITESTANDADC_RunTest_MAX (0x00000001) + #define DDRCMDSCH0_CR_DLLPITESTANDADC_RunTest_DEF (0x00000000) + #define DDRCMDSCH0_CR_DLLPITESTANDADC_Load_OFF ( 1) + #define DDRCMDSCH0_CR_DLLPITESTANDADC_Load_WID ( 1) + #define DDRCMDSCH0_CR_DLLPITESTANDADC_Load_MSK (0x00000002) + #define DDRCMDSCH0_CR_DLLPITESTANDADC_Load_MAX (0x00000001) + #define DDRCMDSCH0_CR_DLLPITESTANDADC_Load_DEF (0x00000000) + #define DDRCMDSCH0_CR_DLLPITESTANDADC_ModeHVM_OFF ( 2) + #define DDRCMDSCH0_CR_DLLPITESTANDADC_ModeHVM_WID ( 1) + #define DDRCMDSCH0_CR_DLLPITESTANDADC_ModeHVM_MSK (0x00000004) + #define DDRCMDSCH0_CR_DLLPITESTANDADC_ModeHVM_MAX (0x00000001) + #define DDRCMDSCH0_CR_DLLPITESTANDADC_ModeHVM_DEF (0x00000000) + #define DDRCMDSCH0_CR_DLLPITESTANDADC_ModeDV_OFF ( 3) + #define DDRCMDSCH0_CR_DLLPITESTANDADC_ModeDV_WID ( 1) + #define DDRCMDSCH0_CR_DLLPITESTANDADC_ModeDV_MSK (0x00000008) + #define DDRCMDSCH0_CR_DLLPITESTANDADC_ModeDV_MAX (0x00000001) + #define DDRCMDSCH0_CR_DLLPITESTANDADC_ModeDV_DEF (0x00000000) + #define DDRCMDSCH0_CR_DLLPITESTANDADC_ModeADC_OFF ( 4) + #define DDRCMDSCH0_CR_DLLPITESTANDADC_ModeADC_WID ( 1) + #define DDRCMDSCH0_CR_DLLPITESTANDADC_ModeADC_MSK (0x00000010) + #define DDRCMDSCH0_CR_DLLPITESTANDADC_ModeADC_MAX (0x00000001) + #define DDRCMDSCH0_CR_DLLPITESTANDADC_ModeADC_DEF (0x00000000) + #define DDRCMDSCH0_CR_DLLPITESTANDADC_LoadCount_OFF ( 5) + #define DDRCMDSCH0_CR_DLLPITESTANDADC_LoadCount_WID (10) + #define DDRCMDSCH0_CR_DLLPITESTANDADC_LoadCount_MSK (0x00007FE0) + #define DDRCMDSCH0_CR_DLLPITESTANDADC_LoadCount_MAX (0x000003FF) + #define DDRCMDSCH0_CR_DLLPITESTANDADC_CountStatus_OFF (15) + #define DDRCMDSCH0_CR_DLLPITESTANDADC_CountStatus_WID (10) + #define DDRCMDSCH0_CR_DLLPITESTANDADC_CountStatus_MSK (0x01FF8000) + #define DDRCMDSCH0_CR_DLLPITESTANDADC_CountStatus_MAX (0x000003FF) + #define DDRCMDSCH0_CR_DLLPITESTANDADC_CountStatus_DEF (0x00000000) + #define DDRCMDSCH0_CR_DLLPITESTANDADC_Spare_OFF (25) + #define DDRCMDSCH0_CR_DLLPITESTANDADC_Spare_WID ( 7) + #define DDRCMDSCH0_CR_DLLPITESTANDADC_Spare_MSK (0xFE000000) + #define DDRCMDSCH0_CR_DLLPITESTANDADC_Spare_MAX (0x0000007F) + +#define DDRCMDSCH1_CR_DDRCRCMDCOMP_REG (0x00001B00) + #define DDRCMDSCH1_CR_DDRCRCMDCOMP_Scomp_OFF ( 0) + #define DDRCMDSCH1_CR_DDRCRCMDCOMP_Scomp_WID ( 6) + #define DDRCMDSCH1_CR_DDRCRCMDCOMP_Scomp_MSK (0x0000003F) + #define DDRCMDSCH1_CR_DDRCRCMDCOMP_Scomp_MAX (0x0000003F) + #define DDRCMDSCH1_CR_DDRCRCMDCOMP_Scomp_DEF (0x00000000) + #define DDRCMDSCH1_CR_DDRCRCMDCOMP_TcoComp_OFF ( 6) + #define DDRCMDSCH1_CR_DDRCRCMDCOMP_TcoComp_WID ( 6) + #define DDRCMDSCH1_CR_DDRCRCMDCOMP_TcoComp_MSK (0x00000FC0) + #define DDRCMDSCH1_CR_DDRCRCMDCOMP_TcoComp_MAX (0x0000003F) + #define DDRCMDSCH1_CR_DDRCRCMDCOMP_TcoComp_DEF (0x00000000) + #define DDRCMDSCH1_CR_DDRCRCMDCOMP_RcompDrvUp_OFF (12) + #define DDRCMDSCH1_CR_DDRCRCMDCOMP_RcompDrvUp_WID ( 6) + #define DDRCMDSCH1_CR_DDRCRCMDCOMP_RcompDrvUp_MSK (0x0003F000) + #define DDRCMDSCH1_CR_DDRCRCMDCOMP_RcompDrvUp_MAX (0x0000003F) + #define DDRCMDSCH1_CR_DDRCRCMDCOMP_RcompDrvUp_DEF (0x00000000) + #define DDRCMDSCH1_CR_DDRCRCMDCOMP_RcompDrvDown_OFF (18) + #define DDRCMDSCH1_CR_DDRCRCMDCOMP_RcompDrvDown_WID ( 6) + #define DDRCMDSCH1_CR_DDRCRCMDCOMP_RcompDrvDown_MSK (0x00FC0000) + #define DDRCMDSCH1_CR_DDRCRCMDCOMP_RcompDrvDown_MAX (0x0000003F) + #define DDRCMDSCH1_CR_DDRCRCMDCOMP_RcompDrvDown_DEF (0x00000000) + #define DDRCMDSCH1_CR_DDRCRCMDCOMP_LsComp_OFF (24) + #define DDRCMDSCH1_CR_DDRCRCMDCOMP_LsComp_WID ( 3) + #define DDRCMDSCH1_CR_DDRCRCMDCOMP_LsComp_MSK (0x07000000) + #define DDRCMDSCH1_CR_DDRCRCMDCOMP_LsComp_MAX (0x00000007) + #define DDRCMDSCH1_CR_DDRCRCMDCOMP_LsComp_DEF (0x00000004) + #define DDRCMDSCH1_CR_DDRCRCMDCOMP_Spare_OFF (27) + #define DDRCMDSCH1_CR_DDRCRCMDCOMP_Spare_WID ( 5) + #define DDRCMDSCH1_CR_DDRCRCMDCOMP_Spare_MSK (0xF8000000) + #define DDRCMDSCH1_CR_DDRCRCMDCOMP_Spare_MAX (0x0000001F) + #define DDRCMDSCH1_CR_DDRCRCMDCOMP_Spare_DEF (0x00000000) + +#define DDRCMDSCH1_CR_DDRCRCMDCOMPOFFSET_REG (0x00001B04) + #define DDRCMDSCH1_CR_DDRCRCMDCOMPOFFSET_ScompOffset_OFF ( 0) + #define DDRCMDSCH1_CR_DDRCRCMDCOMPOFFSET_ScompOffset_WID ( 5) + #define DDRCMDSCH1_CR_DDRCRCMDCOMPOFFSET_ScompOffset_MSK (0x0000001F) + #define DDRCMDSCH1_CR_DDRCRCMDCOMPOFFSET_ScompOffset_MAX (0x0000001F) + #define DDRCMDSCH1_CR_DDRCRCMDCOMPOFFSET_ScompOffset_DEF (0x00000000) + #define DDRCMDSCH1_CR_DDRCRCMDCOMPOFFSET_TcoCompOffset_OFF ( 5) + #define DDRCMDSCH1_CR_DDRCRCMDCOMPOFFSET_TcoCompOffset_WID ( 4) + #define DDRCMDSCH1_CR_DDRCRCMDCOMPOFFSET_TcoCompOffset_MSK (0x000001E0) + #define DDRCMDSCH1_CR_DDRCRCMDCOMPOFFSET_TcoCompOffset_MAX (0x0000000F) + #define DDRCMDSCH1_CR_DDRCRCMDCOMPOFFSET_TcoCompOffset_DEF (0x00000000) + #define DDRCMDSCH1_CR_DDRCRCMDCOMPOFFSET_RcompDrvUpOffset_OFF ( 9) + #define DDRCMDSCH1_CR_DDRCRCMDCOMPOFFSET_RcompDrvUpOffset_WID ( 4) + #define DDRCMDSCH1_CR_DDRCRCMDCOMPOFFSET_RcompDrvUpOffset_MSK (0x00001E00) + #define DDRCMDSCH1_CR_DDRCRCMDCOMPOFFSET_RcompDrvUpOffset_MAX (0x0000000F) + #define DDRCMDSCH1_CR_DDRCRCMDCOMPOFFSET_RcompDrvUpOffset_DEF (0x00000000) + #define DDRCMDSCH1_CR_DDRCRCMDCOMPOFFSET_RcompDrvDownOffset_OFF (13) + #define DDRCMDSCH1_CR_DDRCRCMDCOMPOFFSET_RcompDrvDownOffset_WID ( 4) + #define DDRCMDSCH1_CR_DDRCRCMDCOMPOFFSET_RcompDrvDownOffset_MSK (0x0001E000) + #define DDRCMDSCH1_CR_DDRCRCMDCOMPOFFSET_RcompDrvDownOffset_MAX (0x0000000F) + #define DDRCMDSCH1_CR_DDRCRCMDCOMPOFFSET_RcompDrvDownOffset_DEF (0x00000000) + #define DDRCMDSCH1_CR_DDRCRCMDCOMPOFFSET_Spare_OFF (17) + #define DDRCMDSCH1_CR_DDRCRCMDCOMPOFFSET_Spare_WID (15) + #define DDRCMDSCH1_CR_DDRCRCMDCOMPOFFSET_Spare_MSK (0xFFFE0000) + #define DDRCMDSCH1_CR_DDRCRCMDCOMPOFFSET_Spare_MAX (0x00007FFF) + #define DDRCMDSCH1_CR_DDRCRCMDCOMPOFFSET_Spare_DEF (0x00000000) + +#define DDRCMDSCH1_CR_DDRCRCMDPICODING_REG (0x00001B08) + #define DDRCMDSCH1_CR_DDRCRCMDPICODING_CmdPi0Code_OFF ( 0) + #define DDRCMDSCH1_CR_DDRCRCMDPICODING_CmdPi0Code_WID ( 7) + #define DDRCMDSCH1_CR_DDRCRCMDPICODING_CmdPi0Code_MSK (0x0000007F) + #define DDRCMDSCH1_CR_DDRCRCMDPICODING_CmdPi0Code_MAX (0x0000007F) + #define DDRCMDSCH1_CR_DDRCRCMDPICODING_CmdPi0Code_DEF (0x00000000) + #define DDRCMDSCH1_CR_DDRCRCMDPICODING_CmdPi1Code_OFF ( 7) + #define DDRCMDSCH1_CR_DDRCRCMDPICODING_CmdPi1Code_WID ( 7) + #define DDRCMDSCH1_CR_DDRCRCMDPICODING_CmdPi1Code_MSK (0x00003F80) + #define DDRCMDSCH1_CR_DDRCRCMDPICODING_CmdPi1Code_MAX (0x0000007F) + #define DDRCMDSCH1_CR_DDRCRCMDPICODING_CmdPi1Code_DEF (0x00000000) + #define DDRCMDSCH1_CR_DDRCRCMDPICODING_Spare_OFF (14) + #define DDRCMDSCH1_CR_DDRCRCMDPICODING_Spare_WID (18) + #define DDRCMDSCH1_CR_DDRCRCMDPICODING_Spare_MSK (0xFFFFC000) + #define DDRCMDSCH1_CR_DDRCRCMDPICODING_Spare_MAX (0x0003FFFF) + #define DDRCMDSCH1_CR_DDRCRCMDPICODING_Spare_DEF (0x00000000) + +#define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_REG (0x00001B0C) + #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_RefPi_OFF ( 0) + #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_RefPi_WID ( 4) + #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_RefPi_MSK (0x0000000F) + #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_RefPi_MAX (0x0000000F) + #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_RefPi_DEF (0x00000000) + #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_DllMask_OFF ( 4) + #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_DllMask_WID ( 2) + #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_DllMask_MSK (0x00000030) + #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_DllMask_MAX (0x00000003) + #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_DllMask_DEF (0x00000000) + #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_DllRsvd1_OFF ( 6) + #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_DllRsvd1_WID ( 1) + #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_DllRsvd1_MSK (0x00000040) + #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_DllRsvd1_MAX (0x00000001) + #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_DllRsvd1_DEF (0x00000000) + #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_TxOn_OFF ( 7) + #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_TxOn_WID ( 1) + #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_TxOn_MSK (0x00000080) + #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_TxOn_MAX (0x00000001) + #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_TxOn_DEF (0x00000000) + #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_IntClkOn_OFF ( 8) + #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_IntClkOn_WID ( 1) + #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_IntClkOn_MSK (0x00000100) + #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_IntClkOn_MAX (0x00000001) + #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_IntClkOn_DEF (0x00000000) + #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_RepClkOn_OFF ( 9) + #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_RepClkOn_WID ( 1) + #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_RepClkOn_MSK (0x00000200) + #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_RepClkOn_MAX (0x00000001) + #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_RepClkOn_DEF (0x00000000) + #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_IOLBCtl_OFF (10) + #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_IOLBCtl_WID ( 2) + #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_IOLBCtl_MSK (0x00000C00) + #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_IOLBCtl_MAX (0x00000003) + #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_IOLBCtl_DEF (0x00000000) + #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_OdtMode_OFF (12) + #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_OdtMode_WID ( 1) + #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_OdtMode_MSK (0x00001000) + #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_OdtMode_MAX (0x00000001) + #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_OdtMode_DEF (0x00000000) + #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_CmdTxEq_OFF (13) + #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_CmdTxEq_WID ( 2) + #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_CmdTxEq_MSK (0x00006000) + #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_CmdTxEq_MAX (0x00000003) + #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_CmdTxEq_DEF (0x00000000) + #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_EarlyWeakDrive_OFF (15) + #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_EarlyWeakDrive_WID ( 2) + #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_EarlyWeakDrive_MSK (0x00018000) + #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_EarlyWeakDrive_MAX (0x00000003) + #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_EarlyWeakDrive_DEF (0x00000000) + #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_Reserved_OFF (17) + #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_Reserved_WID ( 4) + #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_Reserved_MSK (0x001E0000) + #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_Reserved_MAX (0x0000000F) + #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_Reserved_DEF (0x00000000) + #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_RxVref_OFF (21) + #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_RxVref_WID ( 6) + #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_RxVref_MSK (0x07E00000) + #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_RxVref_MAX (0x0000003F) + #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_RxVref_DEF (0x00000000) + #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_VccddqHi_OFF (27) + #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_VccddqHi_WID ( 1) + #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_VccddqHi_MSK (0x08000000) + #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_VccddqHi_MAX (0x00000001) + #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_VccddqHi_DEF (0x00000000) + #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_DllWeakLock_OFF (28) + #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_DllWeakLock_WID ( 1) + #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_DllWeakLock_MSK (0x10000000) + #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_DllWeakLock_MAX (0x00000001) + #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_DllWeakLock_DEF (0x00000000) + #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_LPDDR_Mode_OFF (29) + #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_LPDDR_Mode_WID ( 1) + #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_LPDDR_Mode_MSK (0x20000000) + #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_LPDDR_Mode_MAX (0x00000001) + #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_LPDDR_Mode_DEF (0x00000000) + #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_LPDdrCAA_Dis_OFF (30) + #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_LPDdrCAA_Dis_WID ( 1) + #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_LPDdrCAA_Dis_MSK (0x40000000) + #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_LPDdrCAA_Dis_MAX (0x00000001) + #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_LPDdrCAA_Dis_DEF (0x00000000) + #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_LPDdrCAB_Dis_OFF (31) + #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_LPDdrCAB_Dis_WID ( 1) + #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_LPDdrCAB_Dis_MSK (0x80000000) + #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_LPDdrCAB_Dis_MAX (0x00000001) + #define DDRCMDSCH1_CR_DDRCRCMDCONTROLS_LPDdrCAB_Dis_DEF (0x00000000) + +#define DDRCMDSCH1_CR_DLLPITESTANDADC_REG (0x00001B24) + #define DDRCMDSCH1_CR_DLLPITESTANDADC_RunTest_OFF ( 0) + #define DDRCMDSCH1_CR_DLLPITESTANDADC_RunTest_WID ( 1) + #define DDRCMDSCH1_CR_DLLPITESTANDADC_RunTest_MSK (0x00000001) + #define DDRCMDSCH1_CR_DLLPITESTANDADC_RunTest_MAX (0x00000001) + #define DDRCMDSCH1_CR_DLLPITESTANDADC_RunTest_DEF (0x00000000) + #define DDRCMDSCH1_CR_DLLPITESTANDADC_Load_OFF ( 1) + #define DDRCMDSCH1_CR_DLLPITESTANDADC_Load_WID ( 1) + #define DDRCMDSCH1_CR_DLLPITESTANDADC_Load_MSK (0x00000002) + #define DDRCMDSCH1_CR_DLLPITESTANDADC_Load_MAX (0x00000001) + #define DDRCMDSCH1_CR_DLLPITESTANDADC_Load_DEF (0x00000000) + #define DDRCMDSCH1_CR_DLLPITESTANDADC_ModeHVM_OFF ( 2) + #define DDRCMDSCH1_CR_DLLPITESTANDADC_ModeHVM_WID ( 1) + #define DDRCMDSCH1_CR_DLLPITESTANDADC_ModeHVM_MSK (0x00000004) + #define DDRCMDSCH1_CR_DLLPITESTANDADC_ModeHVM_MAX (0x00000001) + #define DDRCMDSCH1_CR_DLLPITESTANDADC_ModeHVM_DEF (0x00000000) + #define DDRCMDSCH1_CR_DLLPITESTANDADC_ModeDV_OFF ( 3) + #define DDRCMDSCH1_CR_DLLPITESTANDADC_ModeDV_WID ( 1) + #define DDRCMDSCH1_CR_DLLPITESTANDADC_ModeDV_MSK (0x00000008) + #define DDRCMDSCH1_CR_DLLPITESTANDADC_ModeDV_MAX (0x00000001) + #define DDRCMDSCH1_CR_DLLPITESTANDADC_ModeDV_DEF (0x00000000) + #define DDRCMDSCH1_CR_DLLPITESTANDADC_ModeADC_OFF ( 4) + #define DDRCMDSCH1_CR_DLLPITESTANDADC_ModeADC_WID ( 1) + #define DDRCMDSCH1_CR_DLLPITESTANDADC_ModeADC_MSK (0x00000010) + #define DDRCMDSCH1_CR_DLLPITESTANDADC_ModeADC_MAX (0x00000001) + #define DDRCMDSCH1_CR_DLLPITESTANDADC_ModeADC_DEF (0x00000000) + #define DDRCMDSCH1_CR_DLLPITESTANDADC_LoadCount_OFF ( 5) + #define DDRCMDSCH1_CR_DLLPITESTANDADC_LoadCount_WID (10) + #define DDRCMDSCH1_CR_DLLPITESTANDADC_LoadCount_MSK (0x00007FE0) + #define DDRCMDSCH1_CR_DLLPITESTANDADC_LoadCount_MAX (0x000003FF) + #define DDRCMDSCH1_CR_DLLPITESTANDADC_CountStatus_OFF (15) + #define DDRCMDSCH1_CR_DLLPITESTANDADC_CountStatus_WID (10) + #define DDRCMDSCH1_CR_DLLPITESTANDADC_CountStatus_MSK (0x01FF8000) + #define DDRCMDSCH1_CR_DLLPITESTANDADC_CountStatus_MAX (0x000003FF) + #define DDRCMDSCH1_CR_DLLPITESTANDADC_CountStatus_DEF (0x00000000) + #define DDRCMDSCH1_CR_DLLPITESTANDADC_Spare_OFF (25) + #define DDRCMDSCH1_CR_DLLPITESTANDADC_Spare_WID ( 7) + #define DDRCMDSCH1_CR_DLLPITESTANDADC_Spare_MSK (0xFE000000) + #define DDRCMDSCH1_CR_DLLPITESTANDADC_Spare_MAX (0x0000007F) + +#define DDRCMDCH0_CR_DDRCRCMDCOMP_REG (0x00003200) + #define DDRCMDCH0_CR_DDRCRCMDCOMP_Scomp_OFF ( 0) + #define DDRCMDCH0_CR_DDRCRCMDCOMP_Scomp_WID ( 6) + #define DDRCMDCH0_CR_DDRCRCMDCOMP_Scomp_MSK (0x0000003F) + #define DDRCMDCH0_CR_DDRCRCMDCOMP_Scomp_MAX (0x0000003F) + #define DDRCMDCH0_CR_DDRCRCMDCOMP_Scomp_DEF (0x00000000) + #define DDRCMDCH0_CR_DDRCRCMDCOMP_TcoComp_OFF ( 6) + #define DDRCMDCH0_CR_DDRCRCMDCOMP_TcoComp_WID ( 6) + #define DDRCMDCH0_CR_DDRCRCMDCOMP_TcoComp_MSK (0x00000FC0) + #define DDRCMDCH0_CR_DDRCRCMDCOMP_TcoComp_MAX (0x0000003F) + #define DDRCMDCH0_CR_DDRCRCMDCOMP_TcoComp_DEF (0x00000000) + #define DDRCMDCH0_CR_DDRCRCMDCOMP_RcompDrvUp_OFF (12) + #define DDRCMDCH0_CR_DDRCRCMDCOMP_RcompDrvUp_WID ( 6) + #define DDRCMDCH0_CR_DDRCRCMDCOMP_RcompDrvUp_MSK (0x0003F000) + #define DDRCMDCH0_CR_DDRCRCMDCOMP_RcompDrvUp_MAX (0x0000003F) + #define DDRCMDCH0_CR_DDRCRCMDCOMP_RcompDrvUp_DEF (0x00000000) + #define DDRCMDCH0_CR_DDRCRCMDCOMP_RcompDrvDown_OFF (18) + #define DDRCMDCH0_CR_DDRCRCMDCOMP_RcompDrvDown_WID ( 6) + #define DDRCMDCH0_CR_DDRCRCMDCOMP_RcompDrvDown_MSK (0x00FC0000) + #define DDRCMDCH0_CR_DDRCRCMDCOMP_RcompDrvDown_MAX (0x0000003F) + #define DDRCMDCH0_CR_DDRCRCMDCOMP_RcompDrvDown_DEF (0x00000000) + #define DDRCMDCH0_CR_DDRCRCMDCOMP_LsComp_OFF (24) + #define DDRCMDCH0_CR_DDRCRCMDCOMP_LsComp_WID ( 3) + #define DDRCMDCH0_CR_DDRCRCMDCOMP_LsComp_MSK (0x07000000) + #define DDRCMDCH0_CR_DDRCRCMDCOMP_LsComp_MAX (0x00000007) + #define DDRCMDCH0_CR_DDRCRCMDCOMP_LsComp_DEF (0x00000004) + #define DDRCMDCH0_CR_DDRCRCMDCOMP_Spare_OFF (27) + #define DDRCMDCH0_CR_DDRCRCMDCOMP_Spare_WID ( 5) + #define DDRCMDCH0_CR_DDRCRCMDCOMP_Spare_MSK (0xF8000000) + #define DDRCMDCH0_CR_DDRCRCMDCOMP_Spare_MAX (0x0000001F) + #define DDRCMDCH0_CR_DDRCRCMDCOMP_Spare_DEF (0x00000000) + +#define DDRCMDCH0_CR_DDRCRCMDCOMPOFFSET_REG (0x00003204) + #define DDRCMDCH0_CR_DDRCRCMDCOMPOFFSET_ScompOffset_OFF ( 0) + #define DDRCMDCH0_CR_DDRCRCMDCOMPOFFSET_ScompOffset_WID ( 5) + #define DDRCMDCH0_CR_DDRCRCMDCOMPOFFSET_ScompOffset_MSK (0x0000001F) + #define DDRCMDCH0_CR_DDRCRCMDCOMPOFFSET_ScompOffset_MAX (0x0000001F) + #define DDRCMDCH0_CR_DDRCRCMDCOMPOFFSET_ScompOffset_DEF (0x00000000) + #define DDRCMDCH0_CR_DDRCRCMDCOMPOFFSET_TcoCompOffset_OFF ( 5) + #define DDRCMDCH0_CR_DDRCRCMDCOMPOFFSET_TcoCompOffset_WID ( 4) + #define DDRCMDCH0_CR_DDRCRCMDCOMPOFFSET_TcoCompOffset_MSK (0x000001E0) + #define DDRCMDCH0_CR_DDRCRCMDCOMPOFFSET_TcoCompOffset_MAX (0x0000000F) + #define DDRCMDCH0_CR_DDRCRCMDCOMPOFFSET_TcoCompOffset_DEF (0x00000000) + #define DDRCMDCH0_CR_DDRCRCMDCOMPOFFSET_RcompDrvUpOffset_OFF ( 9) + #define DDRCMDCH0_CR_DDRCRCMDCOMPOFFSET_RcompDrvUpOffset_WID ( 4) + #define DDRCMDCH0_CR_DDRCRCMDCOMPOFFSET_RcompDrvUpOffset_MSK (0x00001E00) + #define DDRCMDCH0_CR_DDRCRCMDCOMPOFFSET_RcompDrvUpOffset_MAX (0x0000000F) + #define DDRCMDCH0_CR_DDRCRCMDCOMPOFFSET_RcompDrvUpOffset_DEF (0x00000000) + #define DDRCMDCH0_CR_DDRCRCMDCOMPOFFSET_RcompDrvDownOffset_OFF (13) + #define DDRCMDCH0_CR_DDRCRCMDCOMPOFFSET_RcompDrvDownOffset_WID ( 4) + #define DDRCMDCH0_CR_DDRCRCMDCOMPOFFSET_RcompDrvDownOffset_MSK (0x0001E000) + #define DDRCMDCH0_CR_DDRCRCMDCOMPOFFSET_RcompDrvDownOffset_MAX (0x0000000F) + #define DDRCMDCH0_CR_DDRCRCMDCOMPOFFSET_RcompDrvDownOffset_DEF (0x00000000) + #define DDRCMDCH0_CR_DDRCRCMDCOMPOFFSET_Spare_OFF (17) + #define DDRCMDCH0_CR_DDRCRCMDCOMPOFFSET_Spare_WID (15) + #define DDRCMDCH0_CR_DDRCRCMDCOMPOFFSET_Spare_MSK (0xFFFE0000) + #define DDRCMDCH0_CR_DDRCRCMDCOMPOFFSET_Spare_MAX (0x00007FFF) + #define DDRCMDCH0_CR_DDRCRCMDCOMPOFFSET_Spare_DEF (0x00000000) + +#define DDRCMDCH0_CR_DDRCRCMDPICODING_REG (0x00003208) + #define DDRCMDCH0_CR_DDRCRCMDPICODING_CmdPi0Code_OFF ( 0) + #define DDRCMDCH0_CR_DDRCRCMDPICODING_CmdPi0Code_WID ( 7) + #define DDRCMDCH0_CR_DDRCRCMDPICODING_CmdPi0Code_MSK (0x0000007F) + #define DDRCMDCH0_CR_DDRCRCMDPICODING_CmdPi0Code_MAX (0x0000007F) + #define DDRCMDCH0_CR_DDRCRCMDPICODING_CmdPi0Code_DEF (0x00000000) + #define DDRCMDCH0_CR_DDRCRCMDPICODING_CmdPi1Code_OFF ( 7) + #define DDRCMDCH0_CR_DDRCRCMDPICODING_CmdPi1Code_WID ( 7) + #define DDRCMDCH0_CR_DDRCRCMDPICODING_CmdPi1Code_MSK (0x00003F80) + #define DDRCMDCH0_CR_DDRCRCMDPICODING_CmdPi1Code_MAX (0x0000007F) + #define DDRCMDCH0_CR_DDRCRCMDPICODING_CmdPi1Code_DEF (0x00000000) + #define DDRCMDCH0_CR_DDRCRCMDPICODING_Spare_OFF (14) + #define DDRCMDCH0_CR_DDRCRCMDPICODING_Spare_WID (18) + #define DDRCMDCH0_CR_DDRCRCMDPICODING_Spare_MSK (0xFFFFC000) + #define DDRCMDCH0_CR_DDRCRCMDPICODING_Spare_MAX (0x0003FFFF) + #define DDRCMDCH0_CR_DDRCRCMDPICODING_Spare_DEF (0x00000000) + +#define DDRCMDCH0_CR_DDRCRCMDCONTROLS_REG (0x0000320C) + #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_RefPi_OFF ( 0) + #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_RefPi_WID ( 4) + #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_RefPi_MSK (0x0000000F) + #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_RefPi_MAX (0x0000000F) + #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_RefPi_DEF (0x00000000) + #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_DllMask_OFF ( 4) + #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_DllMask_WID ( 2) + #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_DllMask_MSK (0x00000030) + #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_DllMask_MAX (0x00000003) + #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_DllMask_DEF (0x00000000) + #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_DllRsvd1_OFF ( 6) + #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_DllRsvd1_WID ( 1) + #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_DllRsvd1_MSK (0x00000040) + #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_DllRsvd1_MAX (0x00000001) + #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_DllRsvd1_DEF (0x00000000) + #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_TxOn_OFF ( 7) + #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_TxOn_WID ( 1) + #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_TxOn_MSK (0x00000080) + #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_TxOn_MAX (0x00000001) + #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_TxOn_DEF (0x00000000) + #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_IntClkOn_OFF ( 8) + #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_IntClkOn_WID ( 1) + #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_IntClkOn_MSK (0x00000100) + #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_IntClkOn_MAX (0x00000001) + #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_IntClkOn_DEF (0x00000000) + #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_RepClkOn_OFF ( 9) + #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_RepClkOn_WID ( 1) + #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_RepClkOn_MSK (0x00000200) + #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_RepClkOn_MAX (0x00000001) + #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_RepClkOn_DEF (0x00000000) + #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_IOLBCtl_OFF (10) + #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_IOLBCtl_WID ( 2) + #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_IOLBCtl_MSK (0x00000C00) + #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_IOLBCtl_MAX (0x00000003) + #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_IOLBCtl_DEF (0x00000000) + #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_OdtMode_OFF (12) + #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_OdtMode_WID ( 1) + #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_OdtMode_MSK (0x00001000) + #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_OdtMode_MAX (0x00000001) + #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_OdtMode_DEF (0x00000000) + #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_CmdTxEq_OFF (13) + #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_CmdTxEq_WID ( 2) + #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_CmdTxEq_MSK (0x00006000) + #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_CmdTxEq_MAX (0x00000003) + #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_CmdTxEq_DEF (0x00000000) + #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_EarlyWeakDrive_OFF (15) + #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_EarlyWeakDrive_WID ( 2) + #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_EarlyWeakDrive_MSK (0x00018000) + #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_EarlyWeakDrive_MAX (0x00000003) + #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_EarlyWeakDrive_DEF (0x00000000) + #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_Reserved_OFF (17) + #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_Reserved_WID ( 4) + #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_Reserved_MSK (0x001E0000) + #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_Reserved_MAX (0x0000000F) + #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_Reserved_DEF (0x00000000) + #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_RxVref_OFF (21) + #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_RxVref_WID ( 6) + #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_RxVref_MSK (0x07E00000) + #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_RxVref_MAX (0x0000003F) + #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_RxVref_DEF (0x00000000) + #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_VccddqHi_OFF (27) + #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_VccddqHi_WID ( 1) + #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_VccddqHi_MSK (0x08000000) + #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_VccddqHi_MAX (0x00000001) + #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_VccddqHi_DEF (0x00000000) + #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_DllWeakLock_OFF (28) + #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_DllWeakLock_WID ( 1) + #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_DllWeakLock_MSK (0x10000000) + #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_DllWeakLock_MAX (0x00000001) + #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_DllWeakLock_DEF (0x00000000) + #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_LPDDR_Mode_OFF (29) + #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_LPDDR_Mode_WID ( 1) + #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_LPDDR_Mode_MSK (0x20000000) + #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_LPDDR_Mode_MAX (0x00000001) + #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_LPDDR_Mode_DEF (0x00000000) + #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_LPDdrCAA_Dis_OFF (30) + #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_LPDdrCAA_Dis_WID ( 1) + #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_LPDdrCAA_Dis_MSK (0x40000000) + #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_LPDdrCAA_Dis_MAX (0x00000001) + #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_LPDdrCAA_Dis_DEF (0x00000000) + #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_LPDdrCAB_Dis_OFF (31) + #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_LPDdrCAB_Dis_WID ( 1) + #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_LPDdrCAB_Dis_MSK (0x80000000) + #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_LPDdrCAB_Dis_MAX (0x00000001) + #define DDRCMDCH0_CR_DDRCRCMDCONTROLS_LPDdrCAB_Dis_DEF (0x00000000) + +#define DDRCMDCH0_CR_DLLPITESTANDADC_REG (0x00003224) + #define DDRCMDCH0_CR_DLLPITESTANDADC_RunTest_OFF ( 0) + #define DDRCMDCH0_CR_DLLPITESTANDADC_RunTest_WID ( 1) + #define DDRCMDCH0_CR_DLLPITESTANDADC_RunTest_MSK (0x00000001) + #define DDRCMDCH0_CR_DLLPITESTANDADC_RunTest_MAX (0x00000001) + #define DDRCMDCH0_CR_DLLPITESTANDADC_RunTest_DEF (0x00000000) + #define DDRCMDCH0_CR_DLLPITESTANDADC_Load_OFF ( 1) + #define DDRCMDCH0_CR_DLLPITESTANDADC_Load_WID ( 1) + #define DDRCMDCH0_CR_DLLPITESTANDADC_Load_MSK (0x00000002) + #define DDRCMDCH0_CR_DLLPITESTANDADC_Load_MAX (0x00000001) + #define DDRCMDCH0_CR_DLLPITESTANDADC_Load_DEF (0x00000000) + #define DDRCMDCH0_CR_DLLPITESTANDADC_ModeHVM_OFF ( 2) + #define DDRCMDCH0_CR_DLLPITESTANDADC_ModeHVM_WID ( 1) + #define DDRCMDCH0_CR_DLLPITESTANDADC_ModeHVM_MSK (0x00000004) + #define DDRCMDCH0_CR_DLLPITESTANDADC_ModeHVM_MAX (0x00000001) + #define DDRCMDCH0_CR_DLLPITESTANDADC_ModeHVM_DEF (0x00000000) + #define DDRCMDCH0_CR_DLLPITESTANDADC_ModeDV_OFF ( 3) + #define DDRCMDCH0_CR_DLLPITESTANDADC_ModeDV_WID ( 1) + #define DDRCMDCH0_CR_DLLPITESTANDADC_ModeDV_MSK (0x00000008) + #define DDRCMDCH0_CR_DLLPITESTANDADC_ModeDV_MAX (0x00000001) + #define DDRCMDCH0_CR_DLLPITESTANDADC_ModeDV_DEF (0x00000000) + #define DDRCMDCH0_CR_DLLPITESTANDADC_ModeADC_OFF ( 4) + #define DDRCMDCH0_CR_DLLPITESTANDADC_ModeADC_WID ( 1) + #define DDRCMDCH0_CR_DLLPITESTANDADC_ModeADC_MSK (0x00000010) + #define DDRCMDCH0_CR_DLLPITESTANDADC_ModeADC_MAX (0x00000001) + #define DDRCMDCH0_CR_DLLPITESTANDADC_ModeADC_DEF (0x00000000) + #define DDRCMDCH0_CR_DLLPITESTANDADC_LoadCount_OFF ( 5) + #define DDRCMDCH0_CR_DLLPITESTANDADC_LoadCount_WID (10) + #define DDRCMDCH0_CR_DLLPITESTANDADC_LoadCount_MSK (0x00007FE0) + #define DDRCMDCH0_CR_DLLPITESTANDADC_LoadCount_MAX (0x000003FF) + #define DDRCMDCH0_CR_DLLPITESTANDADC_CountStatus_OFF (15) + #define DDRCMDCH0_CR_DLLPITESTANDADC_CountStatus_WID (10) + #define DDRCMDCH0_CR_DLLPITESTANDADC_CountStatus_MSK (0x01FF8000) + #define DDRCMDCH0_CR_DLLPITESTANDADC_CountStatus_MAX (0x000003FF) + #define DDRCMDCH0_CR_DLLPITESTANDADC_CountStatus_DEF (0x00000000) + #define DDRCMDCH0_CR_DLLPITESTANDADC_Spare_OFF (25) + #define DDRCMDCH0_CR_DLLPITESTANDADC_Spare_WID ( 7) + #define DDRCMDCH0_CR_DLLPITESTANDADC_Spare_MSK (0xFE000000) + #define DDRCMDCH0_CR_DLLPITESTANDADC_Spare_MAX (0x0000007F) + +#define DDRCMDCH1_CR_DDRCRCMDCOMP_REG (0x00003300) + #define DDRCMDCH1_CR_DDRCRCMDCOMP_Scomp_OFF ( 0) + #define DDRCMDCH1_CR_DDRCRCMDCOMP_Scomp_WID ( 6) + #define DDRCMDCH1_CR_DDRCRCMDCOMP_Scomp_MSK (0x0000003F) + #define DDRCMDCH1_CR_DDRCRCMDCOMP_Scomp_MAX (0x0000003F) + #define DDRCMDCH1_CR_DDRCRCMDCOMP_Scomp_DEF (0x00000000) + #define DDRCMDCH1_CR_DDRCRCMDCOMP_TcoComp_OFF ( 6) + #define DDRCMDCH1_CR_DDRCRCMDCOMP_TcoComp_WID ( 6) + #define DDRCMDCH1_CR_DDRCRCMDCOMP_TcoComp_MSK (0x00000FC0) + #define DDRCMDCH1_CR_DDRCRCMDCOMP_TcoComp_MAX (0x0000003F) + #define DDRCMDCH1_CR_DDRCRCMDCOMP_TcoComp_DEF (0x00000000) + #define DDRCMDCH1_CR_DDRCRCMDCOMP_RcompDrvUp_OFF (12) + #define DDRCMDCH1_CR_DDRCRCMDCOMP_RcompDrvUp_WID ( 6) + #define DDRCMDCH1_CR_DDRCRCMDCOMP_RcompDrvUp_MSK (0x0003F000) + #define DDRCMDCH1_CR_DDRCRCMDCOMP_RcompDrvUp_MAX (0x0000003F) + #define DDRCMDCH1_CR_DDRCRCMDCOMP_RcompDrvUp_DEF (0x00000000) + #define DDRCMDCH1_CR_DDRCRCMDCOMP_RcompDrvDown_OFF (18) + #define DDRCMDCH1_CR_DDRCRCMDCOMP_RcompDrvDown_WID ( 6) + #define DDRCMDCH1_CR_DDRCRCMDCOMP_RcompDrvDown_MSK (0x00FC0000) + #define DDRCMDCH1_CR_DDRCRCMDCOMP_RcompDrvDown_MAX (0x0000003F) + #define DDRCMDCH1_CR_DDRCRCMDCOMP_RcompDrvDown_DEF (0x00000000) + #define DDRCMDCH1_CR_DDRCRCMDCOMP_LsComp_OFF (24) + #define DDRCMDCH1_CR_DDRCRCMDCOMP_LsComp_WID ( 3) + #define DDRCMDCH1_CR_DDRCRCMDCOMP_LsComp_MSK (0x07000000) + #define DDRCMDCH1_CR_DDRCRCMDCOMP_LsComp_MAX (0x00000007) + #define DDRCMDCH1_CR_DDRCRCMDCOMP_LsComp_DEF (0x00000004) + #define DDRCMDCH1_CR_DDRCRCMDCOMP_Spare_OFF (27) + #define DDRCMDCH1_CR_DDRCRCMDCOMP_Spare_WID ( 5) + #define DDRCMDCH1_CR_DDRCRCMDCOMP_Spare_MSK (0xF8000000) + #define DDRCMDCH1_CR_DDRCRCMDCOMP_Spare_MAX (0x0000001F) + #define DDRCMDCH1_CR_DDRCRCMDCOMP_Spare_DEF (0x00000000) + +#define DDRCMDCH1_CR_DDRCRCMDCOMPOFFSET_REG (0x00003304) + #define DDRCMDCH1_CR_DDRCRCMDCOMPOFFSET_ScompOffset_OFF ( 0) + #define DDRCMDCH1_CR_DDRCRCMDCOMPOFFSET_ScompOffset_WID ( 5) + #define DDRCMDCH1_CR_DDRCRCMDCOMPOFFSET_ScompOffset_MSK (0x0000001F) + #define DDRCMDCH1_CR_DDRCRCMDCOMPOFFSET_ScompOffset_MAX (0x0000001F) + #define DDRCMDCH1_CR_DDRCRCMDCOMPOFFSET_ScompOffset_DEF (0x00000000) + #define DDRCMDCH1_CR_DDRCRCMDCOMPOFFSET_TcoCompOffset_OFF ( 5) + #define DDRCMDCH1_CR_DDRCRCMDCOMPOFFSET_TcoCompOffset_WID ( 4) + #define DDRCMDCH1_CR_DDRCRCMDCOMPOFFSET_TcoCompOffset_MSK (0x000001E0) + #define DDRCMDCH1_CR_DDRCRCMDCOMPOFFSET_TcoCompOffset_MAX (0x0000000F) + #define DDRCMDCH1_CR_DDRCRCMDCOMPOFFSET_TcoCompOffset_DEF (0x00000000) + #define DDRCMDCH1_CR_DDRCRCMDCOMPOFFSET_RcompDrvUpOffset_OFF ( 9) + #define DDRCMDCH1_CR_DDRCRCMDCOMPOFFSET_RcompDrvUpOffset_WID ( 4) + #define DDRCMDCH1_CR_DDRCRCMDCOMPOFFSET_RcompDrvUpOffset_MSK (0x00001E00) + #define DDRCMDCH1_CR_DDRCRCMDCOMPOFFSET_RcompDrvUpOffset_MAX (0x0000000F) + #define DDRCMDCH1_CR_DDRCRCMDCOMPOFFSET_RcompDrvUpOffset_DEF (0x00000000) + #define DDRCMDCH1_CR_DDRCRCMDCOMPOFFSET_RcompDrvDownOffset_OFF (13) + #define DDRCMDCH1_CR_DDRCRCMDCOMPOFFSET_RcompDrvDownOffset_WID ( 4) + #define DDRCMDCH1_CR_DDRCRCMDCOMPOFFSET_RcompDrvDownOffset_MSK (0x0001E000) + #define DDRCMDCH1_CR_DDRCRCMDCOMPOFFSET_RcompDrvDownOffset_MAX (0x0000000F) + #define DDRCMDCH1_CR_DDRCRCMDCOMPOFFSET_RcompDrvDownOffset_DEF (0x00000000) + #define DDRCMDCH1_CR_DDRCRCMDCOMPOFFSET_Spare_OFF (17) + #define DDRCMDCH1_CR_DDRCRCMDCOMPOFFSET_Spare_WID (15) + #define DDRCMDCH1_CR_DDRCRCMDCOMPOFFSET_Spare_MSK (0xFFFE0000) + #define DDRCMDCH1_CR_DDRCRCMDCOMPOFFSET_Spare_MAX (0x00007FFF) + #define DDRCMDCH1_CR_DDRCRCMDCOMPOFFSET_Spare_DEF (0x00000000) + +#define DDRCMDCH1_CR_DDRCRCMDPICODING_REG (0x00003308) + #define DDRCMDCH1_CR_DDRCRCMDPICODING_CmdPi0Code_OFF ( 0) + #define DDRCMDCH1_CR_DDRCRCMDPICODING_CmdPi0Code_WID ( 7) + #define DDRCMDCH1_CR_DDRCRCMDPICODING_CmdPi0Code_MSK (0x0000007F) + #define DDRCMDCH1_CR_DDRCRCMDPICODING_CmdPi0Code_MAX (0x0000007F) + #define DDRCMDCH1_CR_DDRCRCMDPICODING_CmdPi0Code_DEF (0x00000000) + #define DDRCMDCH1_CR_DDRCRCMDPICODING_CmdPi1Code_OFF ( 7) + #define DDRCMDCH1_CR_DDRCRCMDPICODING_CmdPi1Code_WID ( 7) + #define DDRCMDCH1_CR_DDRCRCMDPICODING_CmdPi1Code_MSK (0x00003F80) + #define DDRCMDCH1_CR_DDRCRCMDPICODING_CmdPi1Code_MAX (0x0000007F) + #define DDRCMDCH1_CR_DDRCRCMDPICODING_CmdPi1Code_DEF (0x00000000) + #define DDRCMDCH1_CR_DDRCRCMDPICODING_Spare_OFF (14) + #define DDRCMDCH1_CR_DDRCRCMDPICODING_Spare_WID (18) + #define DDRCMDCH1_CR_DDRCRCMDPICODING_Spare_MSK (0xFFFFC000) + #define DDRCMDCH1_CR_DDRCRCMDPICODING_Spare_MAX (0x0003FFFF) + #define DDRCMDCH1_CR_DDRCRCMDPICODING_Spare_DEF (0x00000000) + +#define DDRCMDCH1_CR_DDRCRCMDCONTROLS_REG (0x0000330C) + #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_RefPi_OFF ( 0) + #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_RefPi_WID ( 4) + #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_RefPi_MSK (0x0000000F) + #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_RefPi_MAX (0x0000000F) + #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_RefPi_DEF (0x00000000) + #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_DllMask_OFF ( 4) + #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_DllMask_WID ( 2) + #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_DllMask_MSK (0x00000030) + #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_DllMask_MAX (0x00000003) + #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_DllMask_DEF (0x00000000) + #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_DllRsvd1_OFF ( 6) + #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_DllRsvd1_WID ( 1) + #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_DllRsvd1_MSK (0x00000040) + #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_DllRsvd1_MAX (0x00000001) + #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_DllRsvd1_DEF (0x00000000) + #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_TxOn_OFF ( 7) + #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_TxOn_WID ( 1) + #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_TxOn_MSK (0x00000080) + #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_TxOn_MAX (0x00000001) + #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_TxOn_DEF (0x00000000) + #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_IntClkOn_OFF ( 8) + #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_IntClkOn_WID ( 1) + #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_IntClkOn_MSK (0x00000100) + #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_IntClkOn_MAX (0x00000001) + #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_IntClkOn_DEF (0x00000000) + #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_RepClkOn_OFF ( 9) + #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_RepClkOn_WID ( 1) + #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_RepClkOn_MSK (0x00000200) + #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_RepClkOn_MAX (0x00000001) + #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_RepClkOn_DEF (0x00000000) + #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_IOLBCtl_OFF (10) + #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_IOLBCtl_WID ( 2) + #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_IOLBCtl_MSK (0x00000C00) + #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_IOLBCtl_MAX (0x00000003) + #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_IOLBCtl_DEF (0x00000000) + #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_OdtMode_OFF (12) + #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_OdtMode_WID ( 1) + #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_OdtMode_MSK (0x00001000) + #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_OdtMode_MAX (0x00000001) + #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_OdtMode_DEF (0x00000000) + #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_CmdTxEq_OFF (13) + #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_CmdTxEq_WID ( 2) + #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_CmdTxEq_MSK (0x00006000) + #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_CmdTxEq_MAX (0x00000003) + #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_CmdTxEq_DEF (0x00000000) + #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_EarlyWeakDrive_OFF (15) + #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_EarlyWeakDrive_WID ( 2) + #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_EarlyWeakDrive_MSK (0x00018000) + #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_EarlyWeakDrive_MAX (0x00000003) + #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_EarlyWeakDrive_DEF (0x00000000) + #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_Reserved_OFF (17) + #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_Reserved_WID ( 4) + #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_Reserved_MSK (0x001E0000) + #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_Reserved_MAX (0x0000000F) + #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_Reserved_DEF (0x00000000) + #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_RxVref_OFF (21) + #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_RxVref_WID ( 6) + #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_RxVref_MSK (0x07E00000) + #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_RxVref_MAX (0x0000003F) + #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_RxVref_DEF (0x00000000) + #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_VccddqHi_OFF (27) + #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_VccddqHi_WID ( 1) + #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_VccddqHi_MSK (0x08000000) + #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_VccddqHi_MAX (0x00000001) + #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_VccddqHi_DEF (0x00000000) + #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_DllWeakLock_OFF (28) + #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_DllWeakLock_WID ( 1) + #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_DllWeakLock_MSK (0x10000000) + #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_DllWeakLock_MAX (0x00000001) + #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_DllWeakLock_DEF (0x00000000) + #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_LPDDR_Mode_OFF (29) + #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_LPDDR_Mode_WID ( 1) + #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_LPDDR_Mode_MSK (0x20000000) + #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_LPDDR_Mode_MAX (0x00000001) + #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_LPDDR_Mode_DEF (0x00000000) + #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_LPDdrCAA_Dis_OFF (30) + #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_LPDdrCAA_Dis_WID ( 1) + #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_LPDdrCAA_Dis_MSK (0x40000000) + #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_LPDdrCAA_Dis_MAX (0x00000001) + #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_LPDdrCAA_Dis_DEF (0x00000000) + #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_LPDdrCAB_Dis_OFF (31) + #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_LPDdrCAB_Dis_WID ( 1) + #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_LPDdrCAB_Dis_MSK (0x80000000) + #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_LPDdrCAB_Dis_MAX (0x00000001) + #define DDRCMDCH1_CR_DDRCRCMDCONTROLS_LPDdrCAB_Dis_DEF (0x00000000) + +#define DDRCMDCH1_CR_DLLPITESTANDADC_REG (0x00003324) + #define DDRCMDCH1_CR_DLLPITESTANDADC_RunTest_OFF ( 0) + #define DDRCMDCH1_CR_DLLPITESTANDADC_RunTest_WID ( 1) + #define DDRCMDCH1_CR_DLLPITESTANDADC_RunTest_MSK (0x00000001) + #define DDRCMDCH1_CR_DLLPITESTANDADC_RunTest_MAX (0x00000001) + #define DDRCMDCH1_CR_DLLPITESTANDADC_RunTest_DEF (0x00000000) + #define DDRCMDCH1_CR_DLLPITESTANDADC_Load_OFF ( 1) + #define DDRCMDCH1_CR_DLLPITESTANDADC_Load_WID ( 1) + #define DDRCMDCH1_CR_DLLPITESTANDADC_Load_MSK (0x00000002) + #define DDRCMDCH1_CR_DLLPITESTANDADC_Load_MAX (0x00000001) + #define DDRCMDCH1_CR_DLLPITESTANDADC_Load_DEF (0x00000000) + #define DDRCMDCH1_CR_DLLPITESTANDADC_ModeHVM_OFF ( 2) + #define DDRCMDCH1_CR_DLLPITESTANDADC_ModeHVM_WID ( 1) + #define DDRCMDCH1_CR_DLLPITESTANDADC_ModeHVM_MSK (0x00000004) + #define DDRCMDCH1_CR_DLLPITESTANDADC_ModeHVM_MAX (0x00000001) + #define DDRCMDCH1_CR_DLLPITESTANDADC_ModeHVM_DEF (0x00000000) + #define DDRCMDCH1_CR_DLLPITESTANDADC_ModeDV_OFF ( 3) + #define DDRCMDCH1_CR_DLLPITESTANDADC_ModeDV_WID ( 1) + #define DDRCMDCH1_CR_DLLPITESTANDADC_ModeDV_MSK (0x00000008) + #define DDRCMDCH1_CR_DLLPITESTANDADC_ModeDV_MAX (0x00000001) + #define DDRCMDCH1_CR_DLLPITESTANDADC_ModeDV_DEF (0x00000000) + #define DDRCMDCH1_CR_DLLPITESTANDADC_ModeADC_OFF ( 4) + #define DDRCMDCH1_CR_DLLPITESTANDADC_ModeADC_WID ( 1) + #define DDRCMDCH1_CR_DLLPITESTANDADC_ModeADC_MSK (0x00000010) + #define DDRCMDCH1_CR_DLLPITESTANDADC_ModeADC_MAX (0x00000001) + #define DDRCMDCH1_CR_DLLPITESTANDADC_ModeADC_DEF (0x00000000) + #define DDRCMDCH1_CR_DLLPITESTANDADC_LoadCount_OFF ( 5) + #define DDRCMDCH1_CR_DLLPITESTANDADC_LoadCount_WID (10) + #define DDRCMDCH1_CR_DLLPITESTANDADC_LoadCount_MSK (0x00007FE0) + #define DDRCMDCH1_CR_DLLPITESTANDADC_LoadCount_MAX (0x000003FF) + #define DDRCMDCH1_CR_DLLPITESTANDADC_CountStatus_OFF (15) + #define DDRCMDCH1_CR_DLLPITESTANDADC_CountStatus_WID (10) + #define DDRCMDCH1_CR_DLLPITESTANDADC_CountStatus_MSK (0x01FF8000) + #define DDRCMDCH1_CR_DLLPITESTANDADC_CountStatus_MAX (0x000003FF) + #define DDRCMDCH1_CR_DLLPITESTANDADC_CountStatus_DEF (0x00000000) + #define DDRCMDCH1_CR_DLLPITESTANDADC_Spare_OFF (25) + #define DDRCMDCH1_CR_DLLPITESTANDADC_Spare_WID ( 7) + #define DDRCMDCH1_CR_DLLPITESTANDADC_Spare_MSK (0xFE000000) + #define DDRCMDCH1_CR_DLLPITESTANDADC_Spare_MAX (0x0000007F) + +#pragma pack(pop) +#endif // __McIoCmd_h__ diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcRegisters/McIoComp.h b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcRegisters/McIoComp.h new file mode 100644 index 0000000..94eb0f0 --- /dev/null +++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcRegisters/McIoComp.h @@ -0,0 +1,648 @@ +/** @file + This file was automatically generated. Modify at your own risk. + +@copyright + Copyright (c) 2010 - 2012 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +**/ +#ifndef __McIoComp_h__ +#define __McIoComp_h__ + +#pragma pack(push, 1) +#include "MrcTypes.h" + +typedef union { + struct { + U32 RcompDrvUp : 6; // Bits 5:0 + U32 Spare0 : 3; // Bits 8:6 + U32 RcompDrvDown : 6; // Bits 14:9 + U32 VTComp : 5; // Bits 19:15 + U32 TcoComp : 6; // Bits 25:20 + U32 SlewRateComp : 5; // Bits 30:26 + U32 Spare2 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRCOMP_CR_DDRCRDATACOMP0_STRUCT; + +typedef union { + struct { + U32 RcompOdtUp : 6; // Bits 5:0 + U32 Spare0 : 3; // Bits 8:6 + U32 RcompOdtDown : 6; // Bits 14:9 + U32 Spare1 : 1; // Bits 15:15 + U32 PanicDrvDn : 6; // Bits 21:16 + U32 PanicDrvUp : 6; // Bits 27:22 + U32 LevelShifterComp : 3; // Bits 30:28 + U32 Spare2 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRCOMP_CR_DDRCRDATACOMP1_STRUCT; + +typedef union { + struct { + U32 Scomp : 6; // Bits 5:0 + U32 TcoComp : 6; // Bits 11:6 + U32 RcompDrvUp : 6; // Bits 17:12 + U32 RcompDrvDown : 6; // Bits 23:18 + U32 LsComp : 3; // Bits 26:24 + U32 Spare : 5; // Bits 31:27 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRCOMP_CR_DDRCRCMDCOMP_STRUCT; + +typedef union { + struct { + U32 Scomp : 6; // Bits 5:0 + U32 TcoComp : 6; // Bits 11:6 + U32 RcompDrvUp : 6; // Bits 17:12 + U32 RcompDrvDown : 6; // Bits 23:18 + U32 LsComp : 4; // Bits 27:24 + U32 Spare : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRCOMP_CR_DDRCRCTLCOMP_STRUCT; + +typedef union { + struct { + U32 Scomp : 5; // Bits 4:0 + U32 TcoComp : 6; // Bits 10:5 + U32 RcompDrvUp : 6; // Bits 16:11 + U32 RcompDrvDown : 6; // Bits 22:17 + U32 LsComp : 4; // Bits 26:23 + U32 Spare : 5; // Bits 31:27 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRCOMP_CR_DDRCRCLKCOMP_STRUCT; + +typedef union { + struct { + U32 Rsvd : 3; // Bits 2:0 + U32 DisableOdtStatic : 1; // Bits 3:3 + U32 DqOdtUpDnOff : 6; // Bits 9:4 + U32 FixOdtD : 1; // Bits 10:10 + U32 DqDrvVref : 4; // Bits 14:11 + U32 DqOdtVref : 5; // Bits 19:15 + U32 CmdDrvVref : 4; // Bits 23:20 + U32 CtlDrvVref : 4; // Bits 27:24 + U32 ClkDrvVref : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRCOMP_CR_DDRCRCOMPCTL0_STRUCT; + +typedef union { + struct { + U32 DqScompCells : 4; // Bits 3:0 + U32 DqScompPC : 1; // Bits 4:4 + U32 CmdScompCells : 4; // Bits 8:5 + U32 CmdScompPC : 1; // Bits 9:9 + U32 CtlScompCells : 4; // Bits 13:10 + U32 CtlScompPC : 1; // Bits 14:14 + U32 ClkScompCells : 4; // Bits 18:15 + U32 ClkScompPC : 1; // Bits 19:19 + U32 TcoCmdOffset : 4; // Bits 23:20 + U32 CompClkOn : 1; // Bits 24:24 + U32 VccddqHi : 1; // Bits 25:25 + U32 spare : 3; // Bits 28:26 + U32 DisableQuickComp : 1; // Bits 29:29 + U32 SinStep : 1; // Bits 30:30 + U32 SinStepAdv : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRCOMP_CR_DDRCRCOMPCTL1_STRUCT; + +typedef union { + struct { + U32 PanicDrvDnVref : 6; // Bits 5:0 + U32 PanicDrvUpVref : 6; // Bits 11:6 + U32 VtOffset : 5; // Bits 16:12 + U32 VtSlopeA : 3; // Bits 19:17 + U32 VtSlopeB : 3; // Bits 22:20 + U32 Spare : 9; // Bits 31:23 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRCOMP_CR_DDRCRCOMPVSSHI_STRUCT; + +typedef union { + struct { + U32 DqDrvU : 1; // Bits 0:0 + U32 DqDrvD : 1; // Bits 1:1 + U32 DqOdtU : 1; // Bits 2:2 + U32 DqOdtD : 1; // Bits 3:3 + U32 CmdDrvU : 1; // Bits 4:4 + U32 CmdDrvD : 1; // Bits 5:5 + U32 CtlDrvU : 1; // Bits 6:6 + U32 CtlDrvD : 1; // Bits 7:7 + U32 ClkDrvU : 1; // Bits 8:8 + U32 ClkDrvD : 1; // Bits 9:9 + U32 DqSR : 1; // Bits 10:10 + U32 CmdSR : 1; // Bits 11:11 + U32 CtlSR : 1; // Bits 12:12 + U32 ClkSR : 1; // Bits 13:13 + U32 DqTcoOff : 1; // Bits 14:14 + U32 CmdTcoOff : 1; // Bits 15:15 + U32 DqTco : 1; // Bits 16:16 + U32 CmdTco : 1; // Bits 17:17 + U32 CtlTco : 1; // Bits 18:18 + U32 ClkTco : 1; // Bits 19:19 + U32 Spare1 : 1; // Bits 20:20 + U32 PanicDrvUp : 1; // Bits 21:21 + U32 PanicDrvDn : 1; // Bits 22:22 + U32 VTComp : 1; // Bits 23:23 + U32 LsComp : 3; // Bits 26:24 + U32 Spare2 : 5; // Bits 31:27 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRCOMP_CR_DDRCRCOMPOVR_STRUCT; + +typedef union { + struct { + U32 Target : 6; // Bits 5:0 + U32 HiBWDivider : 2; // Bits 7:6 + U32 LoBWDivider : 2; // Bits 9:8 + U32 SampleDivider : 3; // Bits 12:10 + U32 OpenLoop : 1; // Bits 13:13 + U32 BWError : 2; // Bits 15:14 + U32 PanicEn : 1; // Bits 16:16 + U32 Rsvd : 1; // Bits 17:17 + U32 PanicVoltage : 4; // Bits 21:18 + U32 GainBoost : 1; // Bits 22:22 + U32 SelCode : 1; // Bits 23:23 + U32 OutputCode : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRCOMP_CR_DDRCRCOMPVSSHICONTROL_STRUCT; + +#define DDRCOMP_CR_DDRCRDATACOMP0_REG (0x00003A00) + #define DDRCOMP_CR_DDRCRDATACOMP0_RcompDrvUp_OFF ( 0) + #define DDRCOMP_CR_DDRCRDATACOMP0_RcompDrvUp_WID ( 6) + #define DDRCOMP_CR_DDRCRDATACOMP0_RcompDrvUp_MSK (0x0000003F) + #define DDRCOMP_CR_DDRCRDATACOMP0_RcompDrvUp_MAX (0x0000003F) + #define DDRCOMP_CR_DDRCRDATACOMP0_Spare0_OFF ( 6) + #define DDRCOMP_CR_DDRCRDATACOMP0_Spare0_WID ( 3) + #define DDRCOMP_CR_DDRCRDATACOMP0_Spare0_MSK (0x000001C0) + #define DDRCOMP_CR_DDRCRDATACOMP0_Spare0_MAX (0x00000007) + #define DDRCOMP_CR_DDRCRDATACOMP0_RcompDrvDown_OFF ( 9) + #define DDRCOMP_CR_DDRCRDATACOMP0_RcompDrvDown_WID ( 6) + #define DDRCOMP_CR_DDRCRDATACOMP0_RcompDrvDown_MSK (0x00007E00) + #define DDRCOMP_CR_DDRCRDATACOMP0_RcompDrvDown_MAX (0x0000003F) + #define DDRCOMP_CR_DDRCRDATACOMP0_VTComp_OFF (15) + #define DDRCOMP_CR_DDRCRDATACOMP0_VTComp_WID ( 5) + #define DDRCOMP_CR_DDRCRDATACOMP0_VTComp_MSK (0x000F8000) + #define DDRCOMP_CR_DDRCRDATACOMP0_VTComp_MAX (0x0000001F) + #define DDRCOMP_CR_DDRCRDATACOMP0_VTComp_DEF (0x00000005) + #define DDRCOMP_CR_DDRCRDATACOMP0_TcoComp_OFF (20) + #define DDRCOMP_CR_DDRCRDATACOMP0_TcoComp_WID ( 6) + #define DDRCOMP_CR_DDRCRDATACOMP0_TcoComp_MSK (0x03F00000) + #define DDRCOMP_CR_DDRCRDATACOMP0_TcoComp_MAX (0x0000003F) + #define DDRCOMP_CR_DDRCRDATACOMP0_SlewRateComp_OFF (26) + #define DDRCOMP_CR_DDRCRDATACOMP0_SlewRateComp_WID ( 5) + #define DDRCOMP_CR_DDRCRDATACOMP0_SlewRateComp_MSK (0x7C000000) + #define DDRCOMP_CR_DDRCRDATACOMP0_SlewRateComp_MAX (0x0000001F) + #define DDRCOMP_CR_DDRCRDATACOMP0_Spare2_OFF (31) + #define DDRCOMP_CR_DDRCRDATACOMP0_Spare2_WID ( 1) + #define DDRCOMP_CR_DDRCRDATACOMP0_Spare2_MSK (0x80000000) + #define DDRCOMP_CR_DDRCRDATACOMP0_Spare2_MAX (0x00000001) + +#define DDRCOMP_CR_DDRCRDATACOMP1_REG (0x00003A04) + #define DDRCOMP_CR_DDRCRDATACOMP1_RcompOdtUp_OFF ( 0) + #define DDRCOMP_CR_DDRCRDATACOMP1_RcompOdtUp_WID ( 6) + #define DDRCOMP_CR_DDRCRDATACOMP1_RcompOdtUp_MSK (0x0000003F) + #define DDRCOMP_CR_DDRCRDATACOMP1_RcompOdtUp_MAX (0x0000003F) + #define DDRCOMP_CR_DDRCRDATACOMP1_Spare0_OFF ( 6) + #define DDRCOMP_CR_DDRCRDATACOMP1_Spare0_WID ( 3) + #define DDRCOMP_CR_DDRCRDATACOMP1_Spare0_MSK (0x000001C0) + #define DDRCOMP_CR_DDRCRDATACOMP1_Spare0_MAX (0x00000007) + #define DDRCOMP_CR_DDRCRDATACOMP1_RcompOdtDown_OFF ( 9) + #define DDRCOMP_CR_DDRCRDATACOMP1_RcompOdtDown_WID ( 6) + #define DDRCOMP_CR_DDRCRDATACOMP1_RcompOdtDown_MSK (0x00007E00) + #define DDRCOMP_CR_DDRCRDATACOMP1_RcompOdtDown_MAX (0x0000003F) + #define DDRCOMP_CR_DDRCRDATACOMP1_Spare1_OFF (15) + #define DDRCOMP_CR_DDRCRDATACOMP1_Spare1_WID ( 1) + #define DDRCOMP_CR_DDRCRDATACOMP1_Spare1_MSK (0x00008000) + #define DDRCOMP_CR_DDRCRDATACOMP1_Spare1_MAX (0x00000001) + #define DDRCOMP_CR_DDRCRDATACOMP1_PanicDrvDn_OFF (16) + #define DDRCOMP_CR_DDRCRDATACOMP1_PanicDrvDn_WID ( 6) + #define DDRCOMP_CR_DDRCRDATACOMP1_PanicDrvDn_MSK (0x003F0000) + #define DDRCOMP_CR_DDRCRDATACOMP1_PanicDrvDn_MAX (0x0000003F) + #define DDRCOMP_CR_DDRCRDATACOMP1_PanicDrvDn_DEF (0x00000010) + #define DDRCOMP_CR_DDRCRDATACOMP1_PanicDrvUp_OFF (22) + #define DDRCOMP_CR_DDRCRDATACOMP1_PanicDrvUp_WID ( 6) + #define DDRCOMP_CR_DDRCRDATACOMP1_PanicDrvUp_MSK (0x0FC00000) + #define DDRCOMP_CR_DDRCRDATACOMP1_PanicDrvUp_MAX (0x0000003F) + #define DDRCOMP_CR_DDRCRDATACOMP1_PanicDrvUp_DEF (0x00000010) + #define DDRCOMP_CR_DDRCRDATACOMP1_LevelShifterComp_OFF (28) + #define DDRCOMP_CR_DDRCRDATACOMP1_LevelShifterComp_WID ( 3) + #define DDRCOMP_CR_DDRCRDATACOMP1_LevelShifterComp_MSK (0x70000000) + #define DDRCOMP_CR_DDRCRDATACOMP1_LevelShifterComp_MAX (0x00000007) + #define DDRCOMP_CR_DDRCRDATACOMP1_LevelShifterComp_DEF (0x00000004) + #define DDRCOMP_CR_DDRCRDATACOMP1_Spare2_OFF (31) + #define DDRCOMP_CR_DDRCRDATACOMP1_Spare2_WID ( 1) + #define DDRCOMP_CR_DDRCRDATACOMP1_Spare2_MSK (0x80000000) + #define DDRCOMP_CR_DDRCRDATACOMP1_Spare2_MAX (0x00000001) + +#define DDRCOMP_CR_DDRCRCMDCOMP_REG (0x00003A08) + #define DDRCOMP_CR_DDRCRCMDCOMP_Scomp_OFF ( 0) + #define DDRCOMP_CR_DDRCRCMDCOMP_Scomp_WID ( 6) + #define DDRCOMP_CR_DDRCRCMDCOMP_Scomp_MSK (0x0000003F) + #define DDRCOMP_CR_DDRCRCMDCOMP_Scomp_MAX (0x0000003F) + #define DDRCOMP_CR_DDRCRCMDCOMP_TcoComp_OFF ( 6) + #define DDRCOMP_CR_DDRCRCMDCOMP_TcoComp_WID ( 6) + #define DDRCOMP_CR_DDRCRCMDCOMP_TcoComp_MSK (0x00000FC0) + #define DDRCOMP_CR_DDRCRCMDCOMP_TcoComp_MAX (0x0000003F) + #define DDRCOMP_CR_DDRCRCMDCOMP_RcompDrvUp_OFF (12) + #define DDRCOMP_CR_DDRCRCMDCOMP_RcompDrvUp_WID ( 6) + #define DDRCOMP_CR_DDRCRCMDCOMP_RcompDrvUp_MSK (0x0003F000) + #define DDRCOMP_CR_DDRCRCMDCOMP_RcompDrvUp_MAX (0x0000003F) + #define DDRCOMP_CR_DDRCRCMDCOMP_RcompDrvDown_OFF (18) + #define DDRCOMP_CR_DDRCRCMDCOMP_RcompDrvDown_WID ( 6) + #define DDRCOMP_CR_DDRCRCMDCOMP_RcompDrvDown_MSK (0x00FC0000) + #define DDRCOMP_CR_DDRCRCMDCOMP_RcompDrvDown_MAX (0x0000003F) + #define DDRCOMP_CR_DDRCRCMDCOMP_LsComp_OFF (24) + #define DDRCOMP_CR_DDRCRCMDCOMP_LsComp_WID ( 3) + #define DDRCOMP_CR_DDRCRCMDCOMP_LsComp_MSK (0x07000000) + #define DDRCOMP_CR_DDRCRCMDCOMP_LsComp_MAX (0x00000007) + #define DDRCOMP_CR_DDRCRCMDCOMP_LsComp_DEF (0x00000004) + #define DDRCOMP_CR_DDRCRCMDCOMP_Spare_OFF (27) + #define DDRCOMP_CR_DDRCRCMDCOMP_Spare_WID ( 5) + #define DDRCOMP_CR_DDRCRCMDCOMP_Spare_MSK (0xF8000000) + #define DDRCOMP_CR_DDRCRCMDCOMP_Spare_MAX (0x0000001F) + +#define DDRCOMP_CR_DDRCRCTLCOMP_REG (0x00003A0C) + #define DDRCOMP_CR_DDRCRCTLCOMP_Scomp_OFF ( 0) + #define DDRCOMP_CR_DDRCRCTLCOMP_Scomp_WID ( 6) + #define DDRCOMP_CR_DDRCRCTLCOMP_Scomp_MSK (0x0000003F) + #define DDRCOMP_CR_DDRCRCTLCOMP_Scomp_MAX (0x0000003F) + #define DDRCOMP_CR_DDRCRCTLCOMP_TcoComp_OFF ( 6) + #define DDRCOMP_CR_DDRCRCTLCOMP_TcoComp_WID ( 6) + #define DDRCOMP_CR_DDRCRCTLCOMP_TcoComp_MSK (0x00000FC0) + #define DDRCOMP_CR_DDRCRCTLCOMP_TcoComp_MAX (0x0000003F) + #define DDRCOMP_CR_DDRCRCTLCOMP_RcompDrvUp_OFF (12) + #define DDRCOMP_CR_DDRCRCTLCOMP_RcompDrvUp_WID ( 6) + #define DDRCOMP_CR_DDRCRCTLCOMP_RcompDrvUp_MSK (0x0003F000) + #define DDRCOMP_CR_DDRCRCTLCOMP_RcompDrvUp_MAX (0x0000003F) + #define DDRCOMP_CR_DDRCRCTLCOMP_RcompDrvDown_OFF (18) + #define DDRCOMP_CR_DDRCRCTLCOMP_RcompDrvDown_WID ( 6) + #define DDRCOMP_CR_DDRCRCTLCOMP_RcompDrvDown_MSK (0x00FC0000) + #define DDRCOMP_CR_DDRCRCTLCOMP_RcompDrvDown_MAX (0x0000003F) + #define DDRCOMP_CR_DDRCRCTLCOMP_LsComp_OFF (24) + #define DDRCOMP_CR_DDRCRCTLCOMP_LsComp_WID ( 4) + #define DDRCOMP_CR_DDRCRCTLCOMP_LsComp_MSK (0x0F000000) + #define DDRCOMP_CR_DDRCRCTLCOMP_LsComp_MAX (0x0000000F) + #define DDRCOMP_CR_DDRCRCTLCOMP_LsComp_DEF (0x00000004) + #define DDRCOMP_CR_DDRCRCTLCOMP_Spare_OFF (28) + #define DDRCOMP_CR_DDRCRCTLCOMP_Spare_WID ( 4) + #define DDRCOMP_CR_DDRCRCTLCOMP_Spare_MSK (0xF0000000) + #define DDRCOMP_CR_DDRCRCTLCOMP_Spare_MAX (0x0000000F) + +#define DDRCOMP_CR_DDRCRCLKCOMP_REG (0x00003A10) + #define DDRCOMP_CR_DDRCRCLKCOMP_Scomp_OFF ( 0) + #define DDRCOMP_CR_DDRCRCLKCOMP_Scomp_WID ( 5) + #define DDRCOMP_CR_DDRCRCLKCOMP_Scomp_MSK (0x0000001F) + #define DDRCOMP_CR_DDRCRCLKCOMP_Scomp_MAX (0x0000001F) + #define DDRCOMP_CR_DDRCRCLKCOMP_TcoComp_OFF ( 5) + #define DDRCOMP_CR_DDRCRCLKCOMP_TcoComp_WID ( 6) + #define DDRCOMP_CR_DDRCRCLKCOMP_TcoComp_MSK (0x000007E0) + #define DDRCOMP_CR_DDRCRCLKCOMP_TcoComp_MAX (0x0000003F) + #define DDRCOMP_CR_DDRCRCLKCOMP_RcompDrvUp_OFF (11) + #define DDRCOMP_CR_DDRCRCLKCOMP_RcompDrvUp_WID ( 6) + #define DDRCOMP_CR_DDRCRCLKCOMP_RcompDrvUp_MSK (0x0001F800) + #define DDRCOMP_CR_DDRCRCLKCOMP_RcompDrvUp_MAX (0x0000003F) + #define DDRCOMP_CR_DDRCRCLKCOMP_RcompDrvDown_OFF (17) + #define DDRCOMP_CR_DDRCRCLKCOMP_RcompDrvDown_WID ( 6) + #define DDRCOMP_CR_DDRCRCLKCOMP_RcompDrvDown_MSK (0x007E0000) + #define DDRCOMP_CR_DDRCRCLKCOMP_RcompDrvDown_MAX (0x0000003F) + #define DDRCOMP_CR_DDRCRCLKCOMP_LsComp_OFF (23) + #define DDRCOMP_CR_DDRCRCLKCOMP_LsComp_WID ( 4) + #define DDRCOMP_CR_DDRCRCLKCOMP_LsComp_MSK (0x07800000) + #define DDRCOMP_CR_DDRCRCLKCOMP_LsComp_MAX (0x0000000F) + #define DDRCOMP_CR_DDRCRCLKCOMP_LsComp_DEF (0x00000004) + #define DDRCOMP_CR_DDRCRCLKCOMP_Spare_OFF (27) + #define DDRCOMP_CR_DDRCRCLKCOMP_Spare_WID ( 5) + #define DDRCOMP_CR_DDRCRCLKCOMP_Spare_MSK (0xF8000000) + #define DDRCOMP_CR_DDRCRCLKCOMP_Spare_MAX (0x0000001F) + +#define DDRCOMP_CR_DDRCRCOMPCTL0_REG (0x00003A14) + #define DDRCOMP_CR_DDRCRCOMPCTL0_Rsvd_OFF ( 0) + #define DDRCOMP_CR_DDRCRCOMPCTL0_Rsvd_WID ( 3) + #define DDRCOMP_CR_DDRCRCOMPCTL0_Rsvd_MSK (0x00000007) + #define DDRCOMP_CR_DDRCRCOMPCTL0_Rsvd_MAX (0x00000007) + #define DDRCOMP_CR_DDRCRCOMPCTL0_DisableOdtStatic_OFF ( 3) + #define DDRCOMP_CR_DDRCRCOMPCTL0_DisableOdtStatic_WID ( 1) + #define DDRCOMP_CR_DDRCRCOMPCTL0_DisableOdtStatic_MSK (0x00000008) + #define DDRCOMP_CR_DDRCRCOMPCTL0_DisableOdtStatic_MAX (0x00000001) + #define DDRCOMP_CR_DDRCRCOMPCTL0_DqOdtUpDnOff_OFF ( 4) + #define DDRCOMP_CR_DDRCRCOMPCTL0_DqOdtUpDnOff_WID ( 6) + #define DDRCOMP_CR_DDRCRCOMPCTL0_DqOdtUpDnOff_MSK (0x000003F0) + #define DDRCOMP_CR_DDRCRCOMPCTL0_DqOdtUpDnOff_MAX (0x0000003F) + #define DDRCOMP_CR_DDRCRCOMPCTL0_FixOdtD_OFF (10) + #define DDRCOMP_CR_DDRCRCOMPCTL0_FixOdtD_WID ( 1) + #define DDRCOMP_CR_DDRCRCOMPCTL0_FixOdtD_MSK (0x00000400) + #define DDRCOMP_CR_DDRCRCOMPCTL0_FixOdtD_MAX (0x00000001) + #define DDRCOMP_CR_DDRCRCOMPCTL0_DqDrvVref_OFF (11) + #define DDRCOMP_CR_DDRCRCOMPCTL0_DqDrvVref_WID ( 4) + #define DDRCOMP_CR_DDRCRCOMPCTL0_DqDrvVref_MSK (0x00007800) + #define DDRCOMP_CR_DDRCRCOMPCTL0_DqDrvVref_MAX (0x0000000F) + #define DDRCOMP_CR_DDRCRCOMPCTL0_DqOdtVref_OFF (15) + #define DDRCOMP_CR_DDRCRCOMPCTL0_DqOdtVref_WID ( 5) + #define DDRCOMP_CR_DDRCRCOMPCTL0_DqOdtVref_MSK (0x000F8000) + #define DDRCOMP_CR_DDRCRCOMPCTL0_DqOdtVref_MAX (0x0000001F) + #define DDRCOMP_CR_DDRCRCOMPCTL0_CmdDrvVref_OFF (20) + #define DDRCOMP_CR_DDRCRCOMPCTL0_CmdDrvVref_WID ( 4) + #define DDRCOMP_CR_DDRCRCOMPCTL0_CmdDrvVref_MSK (0x00F00000) + #define DDRCOMP_CR_DDRCRCOMPCTL0_CmdDrvVref_MAX (0x0000000F) + #define DDRCOMP_CR_DDRCRCOMPCTL0_CtlDrvVref_OFF (24) + #define DDRCOMP_CR_DDRCRCOMPCTL0_CtlDrvVref_WID ( 4) + #define DDRCOMP_CR_DDRCRCOMPCTL0_CtlDrvVref_MSK (0x0F000000) + #define DDRCOMP_CR_DDRCRCOMPCTL0_CtlDrvVref_MAX (0x0000000F) + #define DDRCOMP_CR_DDRCRCOMPCTL0_ClkDrvVref_OFF (28) + #define DDRCOMP_CR_DDRCRCOMPCTL0_ClkDrvVref_WID ( 4) + #define DDRCOMP_CR_DDRCRCOMPCTL0_ClkDrvVref_MSK (0xF0000000) + #define DDRCOMP_CR_DDRCRCOMPCTL0_ClkDrvVref_MAX (0x0000000F) + +#define DDRCOMP_CR_DDRCRCOMPCTL1_REG (0x00003A18) + #define DDRCOMP_CR_DDRCRCOMPCTL1_DqScompCells_OFF ( 0) + #define DDRCOMP_CR_DDRCRCOMPCTL1_DqScompCells_WID ( 4) + #define DDRCOMP_CR_DDRCRCOMPCTL1_DqScompCells_MSK (0x0000000F) + #define DDRCOMP_CR_DDRCRCOMPCTL1_DqScompCells_MAX (0x0000000F) + #define DDRCOMP_CR_DDRCRCOMPCTL1_DqScompPC_OFF ( 4) + #define DDRCOMP_CR_DDRCRCOMPCTL1_DqScompPC_WID ( 1) + #define DDRCOMP_CR_DDRCRCOMPCTL1_DqScompPC_MSK (0x00000010) + #define DDRCOMP_CR_DDRCRCOMPCTL1_DqScompPC_MAX (0x00000001) + #define DDRCOMP_CR_DDRCRCOMPCTL1_CmdScompCells_OFF ( 5) + #define DDRCOMP_CR_DDRCRCOMPCTL1_CmdScompCells_WID ( 4) + #define DDRCOMP_CR_DDRCRCOMPCTL1_CmdScompCells_MSK (0x000001E0) + #define DDRCOMP_CR_DDRCRCOMPCTL1_CmdScompCells_MAX (0x0000000F) + #define DDRCOMP_CR_DDRCRCOMPCTL1_CmdScompPC_OFF ( 9) + #define DDRCOMP_CR_DDRCRCOMPCTL1_CmdScompPC_WID ( 1) + #define DDRCOMP_CR_DDRCRCOMPCTL1_CmdScompPC_MSK (0x00000200) + #define DDRCOMP_CR_DDRCRCOMPCTL1_CmdScompPC_MAX (0x00000001) + #define DDRCOMP_CR_DDRCRCOMPCTL1_CtlScompCells_OFF (10) + #define DDRCOMP_CR_DDRCRCOMPCTL1_CtlScompCells_WID ( 4) + #define DDRCOMP_CR_DDRCRCOMPCTL1_CtlScompCells_MSK (0x00003C00) + #define DDRCOMP_CR_DDRCRCOMPCTL1_CtlScompCells_MAX (0x0000000F) + #define DDRCOMP_CR_DDRCRCOMPCTL1_CtlScompPC_OFF (14) + #define DDRCOMP_CR_DDRCRCOMPCTL1_CtlScompPC_WID ( 1) + #define DDRCOMP_CR_DDRCRCOMPCTL1_CtlScompPC_MSK (0x00004000) + #define DDRCOMP_CR_DDRCRCOMPCTL1_CtlScompPC_MAX (0x00000001) + #define DDRCOMP_CR_DDRCRCOMPCTL1_ClkScompCells_OFF (15) + #define DDRCOMP_CR_DDRCRCOMPCTL1_ClkScompCells_WID ( 4) + #define DDRCOMP_CR_DDRCRCOMPCTL1_ClkScompCells_MSK (0x00078000) + #define DDRCOMP_CR_DDRCRCOMPCTL1_ClkScompCells_MAX (0x0000000F) + #define DDRCOMP_CR_DDRCRCOMPCTL1_ClkScompPC_OFF (19) + #define DDRCOMP_CR_DDRCRCOMPCTL1_ClkScompPC_WID ( 1) + #define DDRCOMP_CR_DDRCRCOMPCTL1_ClkScompPC_MSK (0x00080000) + #define DDRCOMP_CR_DDRCRCOMPCTL1_ClkScompPC_MAX (0x00000001) + #define DDRCOMP_CR_DDRCRCOMPCTL1_TcoCmdOffset_OFF (20) + #define DDRCOMP_CR_DDRCRCOMPCTL1_TcoCmdOffset_WID ( 4) + #define DDRCOMP_CR_DDRCRCOMPCTL1_TcoCmdOffset_MSK (0x00F00000) + #define DDRCOMP_CR_DDRCRCOMPCTL1_TcoCmdOffset_MAX (0x0000000F) + #define DDRCOMP_CR_DDRCRCOMPCTL1_CompClkOn_OFF (24) + #define DDRCOMP_CR_DDRCRCOMPCTL1_CompClkOn_WID ( 1) + #define DDRCOMP_CR_DDRCRCOMPCTL1_CompClkOn_MSK (0x01000000) + #define DDRCOMP_CR_DDRCRCOMPCTL1_CompClkOn_MAX (0x00000001) + #define DDRCOMP_CR_DDRCRCOMPCTL1_VccddqHi_OFF (25) + #define DDRCOMP_CR_DDRCRCOMPCTL1_VccddqHi_WID ( 1) + #define DDRCOMP_CR_DDRCRCOMPCTL1_VccddqHi_MSK (0x02000000) + #define DDRCOMP_CR_DDRCRCOMPCTL1_VccddqHi_MAX (0x00000001) + #define DDRCOMP_CR_DDRCRCOMPCTL1_spare_OFF (26) + #define DDRCOMP_CR_DDRCRCOMPCTL1_spare_WID ( 3) + #define DDRCOMP_CR_DDRCRCOMPCTL1_spare_MSK (0x1C000000) + #define DDRCOMP_CR_DDRCRCOMPCTL1_spare_MAX (0x00000007) + #define DDRCOMP_CR_DDRCRCOMPCTL1_DisableQuickComp_OFF (29) + #define DDRCOMP_CR_DDRCRCOMPCTL1_DisableQuickComp_WID ( 1) + #define DDRCOMP_CR_DDRCRCOMPCTL1_DisableQuickComp_MSK (0x20000000) + #define DDRCOMP_CR_DDRCRCOMPCTL1_DisableQuickComp_MAX (0x00000001) + #define DDRCOMP_CR_DDRCRCOMPCTL1_SinStep_OFF (30) + #define DDRCOMP_CR_DDRCRCOMPCTL1_SinStep_WID ( 1) + #define DDRCOMP_CR_DDRCRCOMPCTL1_SinStep_MSK (0x40000000) + #define DDRCOMP_CR_DDRCRCOMPCTL1_SinStep_MAX (0x00000001) + #define DDRCOMP_CR_DDRCRCOMPCTL1_SinStepAdv_OFF (31) + #define DDRCOMP_CR_DDRCRCOMPCTL1_SinStepAdv_WID ( 1) + #define DDRCOMP_CR_DDRCRCOMPCTL1_SinStepAdv_MSK (0x80000000) + #define DDRCOMP_CR_DDRCRCOMPCTL1_SinStepAdv_MAX (0x00000001) + +#define DDRCOMP_CR_DDRCRCOMPVSSHI_REG (0x00003A1C) + #define DDRCOMP_CR_DDRCRCOMPVSSHI_PanicDrvDnVref_OFF ( 0) + #define DDRCOMP_CR_DDRCRCOMPVSSHI_PanicDrvDnVref_WID ( 6) + #define DDRCOMP_CR_DDRCRCOMPVSSHI_PanicDrvDnVref_MSK (0x0000003F) + #define DDRCOMP_CR_DDRCRCOMPVSSHI_PanicDrvDnVref_MAX (0x0000003F) + #define DDRCOMP_CR_DDRCRCOMPVSSHI_PanicDrvUpVref_OFF ( 6) + #define DDRCOMP_CR_DDRCRCOMPVSSHI_PanicDrvUpVref_WID ( 6) + #define DDRCOMP_CR_DDRCRCOMPVSSHI_PanicDrvUpVref_MSK (0x00000FC0) + #define DDRCOMP_CR_DDRCRCOMPVSSHI_PanicDrvUpVref_MAX (0x0000003F) + #define DDRCOMP_CR_DDRCRCOMPVSSHI_VtOffset_OFF (12) + #define DDRCOMP_CR_DDRCRCOMPVSSHI_VtOffset_WID ( 5) + #define DDRCOMP_CR_DDRCRCOMPVSSHI_VtOffset_MSK (0x0001F000) + #define DDRCOMP_CR_DDRCRCOMPVSSHI_VtOffset_MAX (0x0000001F) + #define DDRCOMP_CR_DDRCRCOMPVSSHI_VtSlopeA_OFF (17) + #define DDRCOMP_CR_DDRCRCOMPVSSHI_VtSlopeA_WID ( 3) + #define DDRCOMP_CR_DDRCRCOMPVSSHI_VtSlopeA_MSK (0x000E0000) + #define DDRCOMP_CR_DDRCRCOMPVSSHI_VtSlopeA_MAX (0x00000007) + #define DDRCOMP_CR_DDRCRCOMPVSSHI_VtSlopeB_OFF (20) + #define DDRCOMP_CR_DDRCRCOMPVSSHI_VtSlopeB_WID ( 3) + #define DDRCOMP_CR_DDRCRCOMPVSSHI_VtSlopeB_MSK (0x00700000) + #define DDRCOMP_CR_DDRCRCOMPVSSHI_VtSlopeB_MAX (0x00000007) + #define DDRCOMP_CR_DDRCRCOMPVSSHI_Spare_OFF (23) + #define DDRCOMP_CR_DDRCRCOMPVSSHI_Spare_WID ( 9) + #define DDRCOMP_CR_DDRCRCOMPVSSHI_Spare_MSK (0xFF800000) + #define DDRCOMP_CR_DDRCRCOMPVSSHI_Spare_MAX (0x000001FF) + +#define DDRCOMP_CR_DDRCRCOMPOVR_REG (0x00003A20) + #define DDRCOMP_CR_DDRCRCOMPOVR_DqDrvU_OFF ( 0) + #define DDRCOMP_CR_DDRCRCOMPOVR_DqDrvU_WID ( 1) + #define DDRCOMP_CR_DDRCRCOMPOVR_DqDrvU_MSK (0x00000001) + #define DDRCOMP_CR_DDRCRCOMPOVR_DqDrvU_MAX (0x00000001) + #define DDRCOMP_CR_DDRCRCOMPOVR_DqDrvD_OFF ( 1) + #define DDRCOMP_CR_DDRCRCOMPOVR_DqDrvD_WID ( 1) + #define DDRCOMP_CR_DDRCRCOMPOVR_DqDrvD_MSK (0x00000002) + #define DDRCOMP_CR_DDRCRCOMPOVR_DqDrvD_MAX (0x00000001) + #define DDRCOMP_CR_DDRCRCOMPOVR_DqOdtU_OFF ( 2) + #define DDRCOMP_CR_DDRCRCOMPOVR_DqOdtU_WID ( 1) + #define DDRCOMP_CR_DDRCRCOMPOVR_DqOdtU_MSK (0x00000004) + #define DDRCOMP_CR_DDRCRCOMPOVR_DqOdtU_MAX (0x00000001) + #define DDRCOMP_CR_DDRCRCOMPOVR_DqOdtD_OFF ( 3) + #define DDRCOMP_CR_DDRCRCOMPOVR_DqOdtD_WID ( 1) + #define DDRCOMP_CR_DDRCRCOMPOVR_DqOdtD_MSK (0x00000008) + #define DDRCOMP_CR_DDRCRCOMPOVR_DqOdtD_MAX (0x00000001) + #define DDRCOMP_CR_DDRCRCOMPOVR_CmdDrvU_OFF ( 4) + #define DDRCOMP_CR_DDRCRCOMPOVR_CmdDrvU_WID ( 1) + #define DDRCOMP_CR_DDRCRCOMPOVR_CmdDrvU_MSK (0x00000010) + #define DDRCOMP_CR_DDRCRCOMPOVR_CmdDrvU_MAX (0x00000001) + #define DDRCOMP_CR_DDRCRCOMPOVR_CmdDrvD_OFF ( 5) + #define DDRCOMP_CR_DDRCRCOMPOVR_CmdDrvD_WID ( 1) + #define DDRCOMP_CR_DDRCRCOMPOVR_CmdDrvD_MSK (0x00000020) + #define DDRCOMP_CR_DDRCRCOMPOVR_CmdDrvD_MAX (0x00000001) + #define DDRCOMP_CR_DDRCRCOMPOVR_CtlDrvU_OFF ( 6) + #define DDRCOMP_CR_DDRCRCOMPOVR_CtlDrvU_WID ( 1) + #define DDRCOMP_CR_DDRCRCOMPOVR_CtlDrvU_MSK (0x00000040) + #define DDRCOMP_CR_DDRCRCOMPOVR_CtlDrvU_MAX (0x00000001) + #define DDRCOMP_CR_DDRCRCOMPOVR_CtlDrvD_OFF ( 7) + #define DDRCOMP_CR_DDRCRCOMPOVR_CtlDrvD_WID ( 1) + #define DDRCOMP_CR_DDRCRCOMPOVR_CtlDrvD_MSK (0x00000080) + #define DDRCOMP_CR_DDRCRCOMPOVR_CtlDrvD_MAX (0x00000001) + #define DDRCOMP_CR_DDRCRCOMPOVR_ClkDrvU_OFF ( 8) + #define DDRCOMP_CR_DDRCRCOMPOVR_ClkDrvU_WID ( 1) + #define DDRCOMP_CR_DDRCRCOMPOVR_ClkDrvU_MSK (0x00000100) + #define DDRCOMP_CR_DDRCRCOMPOVR_ClkDrvU_MAX (0x00000001) + #define DDRCOMP_CR_DDRCRCOMPOVR_ClkDrvD_OFF ( 9) + #define DDRCOMP_CR_DDRCRCOMPOVR_ClkDrvD_WID ( 1) + #define DDRCOMP_CR_DDRCRCOMPOVR_ClkDrvD_MSK (0x00000200) + #define DDRCOMP_CR_DDRCRCOMPOVR_ClkDrvD_MAX (0x00000001) + #define DDRCOMP_CR_DDRCRCOMPOVR_DqSR_OFF (10) + #define DDRCOMP_CR_DDRCRCOMPOVR_DqSR_WID ( 1) + #define DDRCOMP_CR_DDRCRCOMPOVR_DqSR_MSK (0x00000400) + #define DDRCOMP_CR_DDRCRCOMPOVR_DqSR_MAX (0x00000001) + #define DDRCOMP_CR_DDRCRCOMPOVR_CmdSR_OFF (11) + #define DDRCOMP_CR_DDRCRCOMPOVR_CmdSR_WID ( 1) + #define DDRCOMP_CR_DDRCRCOMPOVR_CmdSR_MSK (0x00000800) + #define DDRCOMP_CR_DDRCRCOMPOVR_CmdSR_MAX (0x00000001) + #define DDRCOMP_CR_DDRCRCOMPOVR_CtlSR_OFF (12) + #define DDRCOMP_CR_DDRCRCOMPOVR_CtlSR_WID ( 1) + #define DDRCOMP_CR_DDRCRCOMPOVR_CtlSR_MSK (0x00001000) + #define DDRCOMP_CR_DDRCRCOMPOVR_CtlSR_MAX (0x00000001) + #define DDRCOMP_CR_DDRCRCOMPOVR_ClkSR_OFF (13) + #define DDRCOMP_CR_DDRCRCOMPOVR_ClkSR_WID ( 1) + #define DDRCOMP_CR_DDRCRCOMPOVR_ClkSR_MSK (0x00002000) + #define DDRCOMP_CR_DDRCRCOMPOVR_ClkSR_MAX (0x00000001) + #define DDRCOMP_CR_DDRCRCOMPOVR_DqTcoOff_OFF (14) + #define DDRCOMP_CR_DDRCRCOMPOVR_DqTcoOff_WID ( 1) + #define DDRCOMP_CR_DDRCRCOMPOVR_DqTcoOff_MSK (0x00004000) + #define DDRCOMP_CR_DDRCRCOMPOVR_DqTcoOff_MAX (0x00000001) + #define DDRCOMP_CR_DDRCRCOMPOVR_CmdTcoOff_OFF (15) + #define DDRCOMP_CR_DDRCRCOMPOVR_CmdTcoOff_WID ( 1) + #define DDRCOMP_CR_DDRCRCOMPOVR_CmdTcoOff_MSK (0x00008000) + #define DDRCOMP_CR_DDRCRCOMPOVR_CmdTcoOff_MAX (0x00000001) + #define DDRCOMP_CR_DDRCRCOMPOVR_DqTco_OFF (16) + #define DDRCOMP_CR_DDRCRCOMPOVR_DqTco_WID ( 1) + #define DDRCOMP_CR_DDRCRCOMPOVR_DqTco_MSK (0x00010000) + #define DDRCOMP_CR_DDRCRCOMPOVR_DqTco_MAX (0x00000001) + #define DDRCOMP_CR_DDRCRCOMPOVR_CmdTco_OFF (17) + #define DDRCOMP_CR_DDRCRCOMPOVR_CmdTco_WID ( 1) + #define DDRCOMP_CR_DDRCRCOMPOVR_CmdTco_MSK (0x00020000) + #define DDRCOMP_CR_DDRCRCOMPOVR_CmdTco_MAX (0x00000001) + #define DDRCOMP_CR_DDRCRCOMPOVR_CtlTco_OFF (18) + #define DDRCOMP_CR_DDRCRCOMPOVR_CtlTco_WID ( 1) + #define DDRCOMP_CR_DDRCRCOMPOVR_CtlTco_MSK (0x00040000) + #define DDRCOMP_CR_DDRCRCOMPOVR_CtlTco_MAX (0x00000001) + #define DDRCOMP_CR_DDRCRCOMPOVR_ClkTco_OFF (19) + #define DDRCOMP_CR_DDRCRCOMPOVR_ClkTco_WID ( 1) + #define DDRCOMP_CR_DDRCRCOMPOVR_ClkTco_MSK (0x00080000) + #define DDRCOMP_CR_DDRCRCOMPOVR_ClkTco_MAX (0x00000001) + #define DDRCOMP_CR_DDRCRCOMPOVR_Spare1_OFF (20) + #define DDRCOMP_CR_DDRCRCOMPOVR_Spare1_WID ( 1) + #define DDRCOMP_CR_DDRCRCOMPOVR_Spare1_MSK (0x00100000) + #define DDRCOMP_CR_DDRCRCOMPOVR_Spare1_MAX (0x00000001) + #define DDRCOMP_CR_DDRCRCOMPOVR_PanicDrvUp_OFF (21) + #define DDRCOMP_CR_DDRCRCOMPOVR_PanicDrvUp_WID ( 1) + #define DDRCOMP_CR_DDRCRCOMPOVR_PanicDrvUp_MSK (0x00200000) + #define DDRCOMP_CR_DDRCRCOMPOVR_PanicDrvUp_MAX (0x00000001) + #define DDRCOMP_CR_DDRCRCOMPOVR_PanicDrvDn_OFF (22) + #define DDRCOMP_CR_DDRCRCOMPOVR_PanicDrvDn_WID ( 1) + #define DDRCOMP_CR_DDRCRCOMPOVR_PanicDrvDn_MSK (0x00400000) + #define DDRCOMP_CR_DDRCRCOMPOVR_PanicDrvDn_MAX (0x00000001) + #define DDRCOMP_CR_DDRCRCOMPOVR_VTComp_OFF (23) + #define DDRCOMP_CR_DDRCRCOMPOVR_VTComp_WID ( 1) + #define DDRCOMP_CR_DDRCRCOMPOVR_VTComp_MSK (0x00800000) + #define DDRCOMP_CR_DDRCRCOMPOVR_VTComp_MAX (0x00000001) + #define DDRCOMP_CR_DDRCRCOMPOVR_LsComp_OFF (24) + #define DDRCOMP_CR_DDRCRCOMPOVR_LsComp_WID ( 3) + #define DDRCOMP_CR_DDRCRCOMPOVR_LsComp_MSK (0x07000000) + #define DDRCOMP_CR_DDRCRCOMPOVR_LsComp_MAX (0x00000007) + #define DDRCOMP_CR_DDRCRCOMPOVR_LsComp_DEF (0x00000004) + #define DDRCOMP_CR_DDRCRCOMPOVR_Spare2_OFF (27) + #define DDRCOMP_CR_DDRCRCOMPOVR_Spare2_WID ( 5) + #define DDRCOMP_CR_DDRCRCOMPOVR_Spare2_MSK (0xF8000000) + #define DDRCOMP_CR_DDRCRCOMPOVR_Spare2_MAX (0x0000001F) + +#define DDRCOMP_CR_DDRCRCOMPVSSHICONTROL_REG (0x00003A24) + #define DDRCOMP_CR_DDRCRCOMPVSSHICONTROL_Target_OFF ( 0) + #define DDRCOMP_CR_DDRCRCOMPVSSHICONTROL_Target_WID ( 6) + #define DDRCOMP_CR_DDRCRCOMPVSSHICONTROL_Target_MSK (0x0000003F) + #define DDRCOMP_CR_DDRCRCOMPVSSHICONTROL_Target_MAX (0x0000003F) + #define DDRCOMP_CR_DDRCRCOMPVSSHICONTROL_Target_DEF (0x00000038) + #define DDRCOMP_CR_DDRCRCOMPVSSHICONTROL_HiBWDivider_OFF ( 6) + #define DDRCOMP_CR_DDRCRCOMPVSSHICONTROL_HiBWDivider_WID ( 2) + #define DDRCOMP_CR_DDRCRCOMPVSSHICONTROL_HiBWDivider_MSK (0x000000C0) + #define DDRCOMP_CR_DDRCRCOMPVSSHICONTROL_HiBWDivider_MAX (0x00000003) + #define DDRCOMP_CR_DDRCRCOMPVSSHICONTROL_HiBWDivider_DEF (0x00000000) + #define DDRCOMP_CR_DDRCRCOMPVSSHICONTROL_LoBWDivider_OFF ( 8) + #define DDRCOMP_CR_DDRCRCOMPVSSHICONTROL_LoBWDivider_WID ( 2) + #define DDRCOMP_CR_DDRCRCOMPVSSHICONTROL_LoBWDivider_MSK (0x00000300) + #define DDRCOMP_CR_DDRCRCOMPVSSHICONTROL_LoBWDivider_MAX (0x00000003) + #define DDRCOMP_CR_DDRCRCOMPVSSHICONTROL_LoBWDivider_DEF (0x00000002) + #define DDRCOMP_CR_DDRCRCOMPVSSHICONTROL_SampleDivider_OFF (10) + #define DDRCOMP_CR_DDRCRCOMPVSSHICONTROL_SampleDivider_WID ( 3) + #define DDRCOMP_CR_DDRCRCOMPVSSHICONTROL_SampleDivider_MSK (0x00001C00) + #define DDRCOMP_CR_DDRCRCOMPVSSHICONTROL_SampleDivider_MAX (0x00000007) + #define DDRCOMP_CR_DDRCRCOMPVSSHICONTROL_OpenLoop_OFF (13) + #define DDRCOMP_CR_DDRCRCOMPVSSHICONTROL_OpenLoop_WID ( 1) + #define DDRCOMP_CR_DDRCRCOMPVSSHICONTROL_OpenLoop_MSK (0x00002000) + #define DDRCOMP_CR_DDRCRCOMPVSSHICONTROL_OpenLoop_MAX (0x00000001) + #define DDRCOMP_CR_DDRCRCOMPVSSHICONTROL_BWError_OFF (14) + #define DDRCOMP_CR_DDRCRCOMPVSSHICONTROL_BWError_WID ( 2) + #define DDRCOMP_CR_DDRCRCOMPVSSHICONTROL_BWError_MSK (0x0000C000) + #define DDRCOMP_CR_DDRCRCOMPVSSHICONTROL_BWError_MAX (0x00000003) + #define DDRCOMP_CR_DDRCRCOMPVSSHICONTROL_BWError_DEF (0x00000002) + #define DDRCOMP_CR_DDRCRCOMPVSSHICONTROL_PanicEn_OFF (16) + #define DDRCOMP_CR_DDRCRCOMPVSSHICONTROL_PanicEn_WID ( 1) + #define DDRCOMP_CR_DDRCRCOMPVSSHICONTROL_PanicEn_MSK (0x00010000) + #define DDRCOMP_CR_DDRCRCOMPVSSHICONTROL_PanicEn_MAX (0x00000001) + #define DDRCOMP_CR_DDRCRCOMPVSSHICONTROL_PanicEn_DEF (0x00000001) + #define DDRCOMP_CR_DDRCRCOMPVSSHICONTROL_Rsvd_OFF (17) + #define DDRCOMP_CR_DDRCRCOMPVSSHICONTROL_Rsvd_WID ( 1) + #define DDRCOMP_CR_DDRCRCOMPVSSHICONTROL_Rsvd_MSK (0x00020000) + #define DDRCOMP_CR_DDRCRCOMPVSSHICONTROL_Rsvd_MAX (0x00000001) + #define DDRCOMP_CR_DDRCRCOMPVSSHICONTROL_PanicVoltage_OFF (18) + #define DDRCOMP_CR_DDRCRCOMPVSSHICONTROL_PanicVoltage_WID ( 4) + #define DDRCOMP_CR_DDRCRCOMPVSSHICONTROL_PanicVoltage_MSK (0x003C0000) + #define DDRCOMP_CR_DDRCRCOMPVSSHICONTROL_PanicVoltage_MAX (0x0000000F) + #define DDRCOMP_CR_DDRCRCOMPVSSHICONTROL_PanicVoltage_DEF (0x00000003) + #define DDRCOMP_CR_DDRCRCOMPVSSHICONTROL_GainBoost_OFF (22) + #define DDRCOMP_CR_DDRCRCOMPVSSHICONTROL_GainBoost_WID ( 1) + #define DDRCOMP_CR_DDRCRCOMPVSSHICONTROL_GainBoost_MSK (0x00400000) + #define DDRCOMP_CR_DDRCRCOMPVSSHICONTROL_GainBoost_MAX (0x00000001) + #define DDRCOMP_CR_DDRCRCOMPVSSHICONTROL_GainBoost_DEF (0x00000001) + #define DDRCOMP_CR_DDRCRCOMPVSSHICONTROL_SelCode_OFF (23) + #define DDRCOMP_CR_DDRCRCOMPVSSHICONTROL_SelCode_WID ( 1) + #define DDRCOMP_CR_DDRCRCOMPVSSHICONTROL_SelCode_MSK (0x00800000) + #define DDRCOMP_CR_DDRCRCOMPVSSHICONTROL_SelCode_MAX (0x00000001) + #define DDRCOMP_CR_DDRCRCOMPVSSHICONTROL_OutputCode_OFF (24) + #define DDRCOMP_CR_DDRCRCOMPVSSHICONTROL_OutputCode_WID ( 8) + #define DDRCOMP_CR_DDRCRCOMPVSSHICONTROL_OutputCode_MSK (0xFF000000) + #define DDRCOMP_CR_DDRCRCOMPVSSHICONTROL_OutputCode_MAX (0x000000FF) + +#pragma pack(pop) +#endif // __McIoComp_h__ diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcRegisters/McIoData.h b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcRegisters/McIoData.h new file mode 100644 index 0000000..4e6e898 --- /dev/null +++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcRegisters/McIoData.h @@ -0,0 +1,31196 @@ +/** @file + This file was automatically generated. Modify at your own risk. + +@copyright + Copyright (c) 2010 - 2012 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +**/ +#ifndef __McIoData_h__ +#define __McIoData_h__ + +#pragma pack(push, 1) +#include "MrcTypes.h" + +typedef union { + struct { + U32 RxRcvEnPi : 9; // Bits 8:0 + U32 RxDqsPPi : 6; // Bits 14:9 + U32 RxEq : 5; // Bits 19:15 + U32 RxDqsNPi : 6; // Bits 25:20 + U32 RxVref : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA_CR_RXTRAINRANK0_STRUCT; + +typedef union { + struct { + U32 RxRcvEnPi : 9; // Bits 8:0 + U32 RxDqsPPi : 6; // Bits 14:9 + U32 RxEq : 5; // Bits 19:15 + U32 RxDqsNPi : 6; // Bits 25:20 + U32 RxVref : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA_CR_RXTRAINRANK1_STRUCT; + +typedef union { + struct { + U32 RxRcvEnPi : 9; // Bits 8:0 + U32 RxDqsPPi : 6; // Bits 14:9 + U32 RxEq : 5; // Bits 19:15 + U32 RxDqsNPi : 6; // Bits 25:20 + U32 RxVref : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA_CR_RXTRAINRANK2_STRUCT; + +typedef union { + struct { + U32 RxRcvEnPi : 9; // Bits 8:0 + U32 RxDqsPPi : 6; // Bits 14:9 + U32 RxEq : 5; // Bits 19:15 + U32 RxDqsNPi : 6; // Bits 25:20 + U32 RxVref : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA_CR_RXTRAINRANK3_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA_CR_RXPERBITRANK0_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA_CR_RXPERBITRANK1_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA_CR_RXPERBITRANK2_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA_CR_RXPERBITRANK3_STRUCT; + +typedef union { + struct { + U32 TxDqDelay : 9; // Bits 8:0 + U32 TxDqsDelay : 9; // Bits 17:9 + U32 Spare0 : 2; // Bits 19:18 + U32 TxEqualization : 6; // Bits 25:20 + U32 Spare1 : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA_CR_TXTRAINRANK0_STRUCT; + +typedef union { + struct { + U32 TxDqDelay : 9; // Bits 8:0 + U32 TxDqsDelay : 9; // Bits 17:9 + U32 Spare0 : 2; // Bits 19:18 + U32 TxEqualization : 6; // Bits 25:20 + U32 Spare1 : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA_CR_TXTRAINRANK1_STRUCT; + +typedef union { + struct { + U32 TxDqDelay : 9; // Bits 8:0 + U32 TxDqsDelay : 9; // Bits 17:9 + U32 Spare0 : 2; // Bits 19:18 + U32 TxEqualization : 6; // Bits 25:20 + U32 Spare1 : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA_CR_TXTRAINRANK2_STRUCT; + +typedef union { + struct { + U32 TxDqDelay : 9; // Bits 8:0 + U32 TxDqsDelay : 9; // Bits 17:9 + U32 Spare0 : 2; // Bits 19:18 + U32 TxEqualization : 6; // Bits 25:20 + U32 Spare1 : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA_CR_TXTRAINRANK3_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA_CR_TXPERBITRANK0_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA_CR_TXPERBITRANK1_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA_CR_TXPERBITRANK2_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA_CR_TXPERBITRANK3_STRUCT; + +typedef union { + struct { + U32 RcompDrvUp : 6; // Bits 5:0 + U32 Spare0 : 3; // Bits 8:6 + U32 RcompDrvDown : 6; // Bits 14:9 + U32 VTComp : 5; // Bits 19:15 + U32 TcoComp : 6; // Bits 25:20 + U32 SlewRateComp : 5; // Bits 30:26 + U32 Spare2 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA_CR_RCOMPDATA0_STRUCT; + +typedef union { + struct { + U32 RcompOdtUp : 6; // Bits 5:0 + U32 Spare0 : 3; // Bits 8:6 + U32 RcompOdtDown : 6; // Bits 14:9 + U32 Spare1 : 1; // Bits 15:15 + U32 PanicDrvDn : 6; // Bits 21:16 + U32 PanicDrvUp : 6; // Bits 27:22 + U32 LevelShifterComp : 3; // Bits 30:28 + U32 Spare2 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA_CR_RCOMPDATA1_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA_CR_TXXTALK_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA_CR_RXOFFSETVDQ_STRUCT; + +typedef union { + struct { + U32 Spare : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA_CR_DDRDATARESERVED_STRUCT; + +typedef union { + struct { + U32 DataTrainFeedback : 9; // Bits 8:0 + U32 Spare : 23; // Bits 31:9 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA_CR_DATATRAINFEEDBACK_STRUCT; + +typedef union { + struct { + U32 RunTest : 1; // Bits 0:0 + U32 Load : 1; // Bits 1:1 + U32 ModeHVM : 1; // Bits 2:2 + U32 ModeDV : 1; // Bits 3:3 + U32 ModeADC : 1; // Bits 4:4 + U32 LoadCount : 10; // Bits 14:5 + U32 CountStatus : 10; // Bits 24:15 + U32 Spare : 7; // Bits 31:25 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA_CR_DLLPITESTANDADC_STRUCT; + +typedef union { + struct { + U32 DqDrvUpCompOffset : 6; // Bits 5:0 + U32 DqDrvDownCompOffset : 6; // Bits 11:6 + U32 DqOdtUpCompOffset : 5; // Bits 16:12 + U32 DqOdtDownCompOffset : 5; // Bits 21:17 + U32 DqTcoCompOffset : 5; // Bits 26:22 + U32 DqSlewRateCompOffset : 5; // Bits 31:27 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA_CR_DDRCRDATAOFFSETCOMP_STRUCT; + +typedef union { + struct { + U32 RefPi : 4; // Bits 3:0 + U32 DllMask : 2; // Bits 5:4 + U32 DllWeakLock : 1; // Bits 6:6 + U32 SdllSegmentDisable : 3; // Bits 9:7 + U32 RxBiasCtl : 3; // Bits 12:10 + U32 OdtDelay : 4; // Bits 16:13 + U32 OdtDuration : 3; // Bits 19:17 + U32 SenseAmpDelay : 4; // Bits 23:20 + U32 SenseAmpDuration : 3; // Bits 26:24 + U32 BurstEndODTDelay : 3; // Bits 29:27 + U32 LpDdrLongOdtEn : 1; // Bits 30:30 + U32 Rsvd1 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA_CR_DDRCRDATACONTROL1_STRUCT; + +typedef union { + struct { + U32 RxStaggerCtl : 5; // Bits 4:0 + U32 ForceBiasOn : 1; // Bits 5:5 + U32 ForceRxOn : 1; // Bits 6:6 + U32 LeakerComp : 2; // Bits 8:7 + U32 RxDqsAmpOffset : 4; // Bits 12:9 + U32 RxClkStgNum : 5; // Bits 17:13 + U32 WlLongDelEn : 1; // Bits 18:18 + U32 Spare : 13; // Bits 31:19 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA_CR_DDRCRDATACONTROL2_STRUCT; + +typedef union { + struct { + U32 VrefCtl : 24; // Bits 23:0 + U32 OutputCode : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA_CR_DDRCRVREFCONTROL_STRUCT; + +typedef union { + struct { + U32 VssHiCtl : 24; // Bits 23:0 + U32 OutputCode : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA_CR_DDRCRVSSHICONTROL_STRUCT; + +typedef union { + struct { + U32 VssHiOrVrefCtl : 24; // Bits 23:0 + U32 OutputCode : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA_CR_DDRCRVSSHIORVREFCONTROL_STRUCT; + +typedef union { + struct { + U32 RcvEnOffset : 6; // Bits 5:0 + U32 RxDqsOffset : 6; // Bits 11:6 + U32 TxDqOffset : 6; // Bits 17:12 + U32 TxDqsOffset : 6; // Bits 23:18 + U32 VrefOffset : 7; // Bits 30:24 + U32 Spare : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA_CR_DDRCRDATAOFFSETTRAIN_STRUCT; + +typedef union { + struct { + U32 RxTrainingMode : 1; // Bits 0:0 + U32 WLTrainingMode : 1; // Bits 1:1 + U32 RLTrainingMode : 1; // Bits 2:2 + U32 SenseampTrainingMode : 1; // Bits 3:3 + U32 TxOn : 1; // Bits 4:4 + U32 RfOn : 1; // Bits 5:5 + U32 RxPiOn : 1; // Bits 6:6 + U32 TxPiOn : 1; // Bits 7:7 + U32 InternalClocksOn : 1; // Bits 8:8 + U32 RepeaterClocksOn : 1; // Bits 9:9 + U32 TxDisable : 1; // Bits 10:10 + U32 RxDisable : 1; // Bits 11:11 + U32 TxLong : 1; // Bits 12:12 + U32 RxDqsCtle : 2; // Bits 14:13 + U32 RxReadPointer : 3; // Bits 17:15 + U32 DriverSegmentEnable : 1; // Bits 18:18 + U32 DataVccddqHi : 1; // Bits 19:19 + U32 ReadRFRd : 1; // Bits 20:20 + U32 ReadRFWr : 1; // Bits 21:21 + U32 ReadRFRank : 2; // Bits 23:22 + U32 ForceOdtOn : 1; // Bits 24:24 + U32 OdtSampOff : 1; // Bits 25:25 + U32 DisableOdtStatic : 1; // Bits 26:26 + U32 DdrCRForceODTOn : 1; // Bits 27:27 + U32 LPDDR_Mode : 1; // Bits 28:28 + U32 EnReadPreamble : 1; // Bits 29:29 + U32 OdtSampExtendEn : 1; // Bits 30:30 + U32 EarlyRleakEn : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA_CR_DDRCRDATACONTROL0_STRUCT; + +typedef union { + struct { + U32 CAVrefCtl : 7; // Bits 6:0 + U32 Ch1VrefCtl : 7; // Bits 13:7 + U32 Ch0VrefCtl : 7; // Bits 20:14 + U32 EnDimmVrefCA : 1; // Bits 21:21 + U32 EnDimmVrefCh1 : 1; // Bits 22:22 + U32 EnDimmVrefCh0 : 1; // Bits 23:23 + U32 HiZTimerCtrl : 2; // Bits 25:24 + U32 VccddqHiQnnnH : 1; // Bits 26:26 + U32 Rsvd : 2; // Bits 28:27 + U32 caSlowBW : 1; // Bits 29:29 + U32 ch0SlowBW : 1; // Bits 30:30 + U32 ch1SlowBW : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA_CR_DDRCRVREFADJUST1_STRUCT; + +typedef union { + struct { + U32 RxRcvEnPi : 9; // Bits 8:0 + U32 RxDqsPPi : 6; // Bits 14:9 + U32 RxEq : 5; // Bits 19:15 + U32 RxDqsNPi : 6; // Bits 25:20 + U32 RxVref : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATACH0_CR_RXTRAINRANK0_STRUCT; + +typedef union { + struct { + U32 RxRcvEnPi : 9; // Bits 8:0 + U32 RxDqsPPi : 6; // Bits 14:9 + U32 RxEq : 5; // Bits 19:15 + U32 RxDqsNPi : 6; // Bits 25:20 + U32 RxVref : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATACH0_CR_RXTRAINRANK1_STRUCT; + +typedef union { + struct { + U32 RxRcvEnPi : 9; // Bits 8:0 + U32 RxDqsPPi : 6; // Bits 14:9 + U32 RxEq : 5; // Bits 19:15 + U32 RxDqsNPi : 6; // Bits 25:20 + U32 RxVref : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATACH0_CR_RXTRAINRANK2_STRUCT; + +typedef union { + struct { + U32 RxRcvEnPi : 9; // Bits 8:0 + U32 RxDqsPPi : 6; // Bits 14:9 + U32 RxEq : 5; // Bits 19:15 + U32 RxDqsNPi : 6; // Bits 25:20 + U32 RxVref : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATACH0_CR_RXTRAINRANK3_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATACH0_CR_RXPERBITRANK0_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATACH0_CR_RXPERBITRANK1_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATACH0_CR_RXPERBITRANK2_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATACH0_CR_RXPERBITRANK3_STRUCT; + +typedef union { + struct { + U32 TxDqDelay : 9; // Bits 8:0 + U32 TxDqsDelay : 9; // Bits 17:9 + U32 Spare0 : 2; // Bits 19:18 + U32 TxEqualization : 6; // Bits 25:20 + U32 Spare1 : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATACH0_CR_TXTRAINRANK0_STRUCT; + +typedef union { + struct { + U32 TxDqDelay : 9; // Bits 8:0 + U32 TxDqsDelay : 9; // Bits 17:9 + U32 Spare0 : 2; // Bits 19:18 + U32 TxEqualization : 6; // Bits 25:20 + U32 Spare1 : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATACH0_CR_TXTRAINRANK1_STRUCT; + +typedef union { + struct { + U32 TxDqDelay : 9; // Bits 8:0 + U32 TxDqsDelay : 9; // Bits 17:9 + U32 Spare0 : 2; // Bits 19:18 + U32 TxEqualization : 6; // Bits 25:20 + U32 Spare1 : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATACH0_CR_TXTRAINRANK2_STRUCT; + +typedef union { + struct { + U32 TxDqDelay : 9; // Bits 8:0 + U32 TxDqsDelay : 9; // Bits 17:9 + U32 Spare0 : 2; // Bits 19:18 + U32 TxEqualization : 6; // Bits 25:20 + U32 Spare1 : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATACH0_CR_TXTRAINRANK3_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATACH0_CR_TXPERBITRANK0_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATACH0_CR_TXPERBITRANK1_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATACH0_CR_TXPERBITRANK2_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATACH0_CR_TXPERBITRANK3_STRUCT; + +typedef union { + struct { + U32 RcompDrvUp : 6; // Bits 5:0 + U32 Spare0 : 3; // Bits 8:6 + U32 RcompDrvDown : 6; // Bits 14:9 + U32 VTComp : 5; // Bits 19:15 + U32 TcoComp : 6; // Bits 25:20 + U32 SlewRateComp : 5; // Bits 30:26 + U32 Spare2 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATACH0_CR_RCOMPDATA0_STRUCT; + +typedef union { + struct { + U32 RcompOdtUp : 6; // Bits 5:0 + U32 Spare0 : 3; // Bits 8:6 + U32 RcompOdtDown : 6; // Bits 14:9 + U32 Spare1 : 1; // Bits 15:15 + U32 PanicDrvDn : 6; // Bits 21:16 + U32 PanicDrvUp : 6; // Bits 27:22 + U32 LevelShifterComp : 3; // Bits 30:28 + U32 Spare2 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATACH0_CR_RCOMPDATA1_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATACH0_CR_TXXTALK_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATACH0_CR_RXOFFSETVDQ_STRUCT; + +typedef union { + struct { + U32 Spare : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATACH0_CR_DDRDATARESERVED_STRUCT; + +typedef union { + struct { + U32 DataTrainFeedback : 9; // Bits 8:0 + U32 Spare : 23; // Bits 31:9 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATACH0_CR_DATATRAINFEEDBACK_STRUCT; + +typedef union { + struct { + U32 RunTest : 1; // Bits 0:0 + U32 Load : 1; // Bits 1:1 + U32 ModeHVM : 1; // Bits 2:2 + U32 ModeDV : 1; // Bits 3:3 + U32 ModeADC : 1; // Bits 4:4 + U32 LoadCount : 10; // Bits 14:5 + U32 CountStatus : 10; // Bits 24:15 + U32 Spare : 7; // Bits 31:25 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATACH0_CR_DLLPITESTANDADC_STRUCT; + +typedef union { + struct { + U32 DqDrvUpCompOffset : 6; // Bits 5:0 + U32 DqDrvDownCompOffset : 6; // Bits 11:6 + U32 DqOdtUpCompOffset : 5; // Bits 16:12 + U32 DqOdtDownCompOffset : 5; // Bits 21:17 + U32 DqTcoCompOffset : 5; // Bits 26:22 + U32 DqSlewRateCompOffset : 5; // Bits 31:27 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATACH0_CR_DDRCRDATAOFFSETCOMP_STRUCT; + +typedef union { + struct { + U32 RefPi : 4; // Bits 3:0 + U32 DllMask : 2; // Bits 5:4 + U32 DllWeakLock : 1; // Bits 6:6 + U32 SdllSegmentDisable : 3; // Bits 9:7 + U32 RxBiasCtl : 3; // Bits 12:10 + U32 OdtDelay : 4; // Bits 16:13 + U32 OdtDuration : 3; // Bits 19:17 + U32 SenseAmpDelay : 4; // Bits 23:20 + U32 SenseAmpDuration : 3; // Bits 26:24 + U32 BurstEndODTDelay : 3; // Bits 29:27 + U32 LpDdrLongOdtEn : 1; // Bits 30:30 + U32 Rsvd1 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATACH0_CR_DDRCRDATACONTROL1_STRUCT; + +typedef union { + struct { + U32 RxStaggerCtl : 5; // Bits 4:0 + U32 ForceBiasOn : 1; // Bits 5:5 + U32 ForceRxOn : 1; // Bits 6:6 + U32 LeakerComp : 2; // Bits 8:7 + U32 RxDqsAmpOffset : 4; // Bits 12:9 + U32 RxClkStgNum : 5; // Bits 17:13 + U32 WlLongDelEn : 1; // Bits 18:18 + U32 Spare : 13; // Bits 31:19 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATACH0_CR_DDRCRDATACONTROL2_STRUCT; + +typedef union { + struct { + U32 VssHiOrVrefCtl : 24; // Bits 23:0 + U32 OutputCode : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATACH0_CR_DDRCRVSSHIORVREFCONTROL_STRUCT; + +typedef union { + struct { + U32 RcvEnOffset : 6; // Bits 5:0 + U32 RxDqsOffset : 6; // Bits 11:6 + U32 TxDqOffset : 6; // Bits 17:12 + U32 TxDqsOffset : 6; // Bits 23:18 + U32 VrefOffset : 7; // Bits 30:24 + U32 Spare : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN_STRUCT; + +typedef union { + struct { + U32 RxTrainingMode : 1; // Bits 0:0 + U32 WLTrainingMode : 1; // Bits 1:1 + U32 RLTrainingMode : 1; // Bits 2:2 + U32 SenseampTrainingMode : 1; // Bits 3:3 + U32 TxOn : 1; // Bits 4:4 + U32 RfOn : 1; // Bits 5:5 + U32 RxPiOn : 1; // Bits 6:6 + U32 TxPiOn : 1; // Bits 7:7 + U32 InternalClocksOn : 1; // Bits 8:8 + U32 RepeaterClocksOn : 1; // Bits 9:9 + U32 TxDisable : 1; // Bits 10:10 + U32 RxDisable : 1; // Bits 11:11 + U32 TxLong : 1; // Bits 12:12 + U32 RxDqsCtle : 2; // Bits 14:13 + U32 RxReadPointer : 3; // Bits 17:15 + U32 DriverSegmentEnable : 1; // Bits 18:18 + U32 DataVccddqHi : 1; // Bits 19:19 + U32 ReadRFRd : 1; // Bits 20:20 + U32 ReadRFWr : 1; // Bits 21:21 + U32 ReadRFRank : 2; // Bits 23:22 + U32 ForceOdtOn : 1; // Bits 24:24 + U32 OdtSampOff : 1; // Bits 25:25 + U32 DisableOdtStatic : 1; // Bits 26:26 + U32 DdrCRForceODTOn : 1; // Bits 27:27 + U32 LPDDR_Mode : 1; // Bits 28:28 + U32 EnReadPreamble : 1; // Bits 29:29 + U32 OdtSampExtendEn : 1; // Bits 30:30 + U32 EarlyRleakEn : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATACH0_CR_DDRCRDATACONTROL0_STRUCT; + +typedef union { + struct { + U32 CAVrefCtl : 7; // Bits 6:0 + U32 Ch1VrefCtl : 7; // Bits 13:7 + U32 Ch0VrefCtl : 7; // Bits 20:14 + U32 EnDimmVrefCA : 1; // Bits 21:21 + U32 EnDimmVrefCh1 : 1; // Bits 22:22 + U32 EnDimmVrefCh0 : 1; // Bits 23:23 + U32 HiZTimerCtrl : 2; // Bits 25:24 + U32 VccddqHiQnnnH : 1; // Bits 26:26 + U32 Rsvd : 2; // Bits 28:27 + U32 caSlowBW : 1; // Bits 29:29 + U32 ch0SlowBW : 1; // Bits 30:30 + U32 ch1SlowBW : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATACH0_CR_DDRCRVREFADJUST1_STRUCT; + +typedef union { + struct { + U32 RxRcvEnPi : 9; // Bits 8:0 + U32 RxDqsPPi : 6; // Bits 14:9 + U32 RxEq : 5; // Bits 19:15 + U32 RxDqsNPi : 6; // Bits 25:20 + U32 RxVref : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATACH1_CR_RXTRAINRANK0_STRUCT; + +typedef union { + struct { + U32 RxRcvEnPi : 9; // Bits 8:0 + U32 RxDqsPPi : 6; // Bits 14:9 + U32 RxEq : 5; // Bits 19:15 + U32 RxDqsNPi : 6; // Bits 25:20 + U32 RxVref : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATACH1_CR_RXTRAINRANK1_STRUCT; + +typedef union { + struct { + U32 RxRcvEnPi : 9; // Bits 8:0 + U32 RxDqsPPi : 6; // Bits 14:9 + U32 RxEq : 5; // Bits 19:15 + U32 RxDqsNPi : 6; // Bits 25:20 + U32 RxVref : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATACH1_CR_RXTRAINRANK2_STRUCT; + +typedef union { + struct { + U32 RxRcvEnPi : 9; // Bits 8:0 + U32 RxDqsPPi : 6; // Bits 14:9 + U32 RxEq : 5; // Bits 19:15 + U32 RxDqsNPi : 6; // Bits 25:20 + U32 RxVref : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATACH1_CR_RXTRAINRANK3_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATACH1_CR_RXPERBITRANK0_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATACH1_CR_RXPERBITRANK1_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATACH1_CR_RXPERBITRANK2_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATACH1_CR_RXPERBITRANK3_STRUCT; + +typedef union { + struct { + U32 TxDqDelay : 9; // Bits 8:0 + U32 TxDqsDelay : 9; // Bits 17:9 + U32 Spare0 : 2; // Bits 19:18 + U32 TxEqualization : 6; // Bits 25:20 + U32 Spare1 : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATACH1_CR_TXTRAINRANK0_STRUCT; + +typedef union { + struct { + U32 TxDqDelay : 9; // Bits 8:0 + U32 TxDqsDelay : 9; // Bits 17:9 + U32 Spare0 : 2; // Bits 19:18 + U32 TxEqualization : 6; // Bits 25:20 + U32 Spare1 : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATACH1_CR_TXTRAINRANK1_STRUCT; + +typedef union { + struct { + U32 TxDqDelay : 9; // Bits 8:0 + U32 TxDqsDelay : 9; // Bits 17:9 + U32 Spare0 : 2; // Bits 19:18 + U32 TxEqualization : 6; // Bits 25:20 + U32 Spare1 : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATACH1_CR_TXTRAINRANK2_STRUCT; + +typedef union { + struct { + U32 TxDqDelay : 9; // Bits 8:0 + U32 TxDqsDelay : 9; // Bits 17:9 + U32 Spare0 : 2; // Bits 19:18 + U32 TxEqualization : 6; // Bits 25:20 + U32 Spare1 : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATACH1_CR_TXTRAINRANK3_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATACH1_CR_TXPERBITRANK0_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATACH1_CR_TXPERBITRANK1_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATACH1_CR_TXPERBITRANK2_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATACH1_CR_TXPERBITRANK3_STRUCT; + +typedef union { + struct { + U32 RcompDrvUp : 6; // Bits 5:0 + U32 Spare0 : 3; // Bits 8:6 + U32 RcompDrvDown : 6; // Bits 14:9 + U32 VTComp : 5; // Bits 19:15 + U32 TcoComp : 6; // Bits 25:20 + U32 SlewRateComp : 5; // Bits 30:26 + U32 Spare2 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATACH1_CR_RCOMPDATA0_STRUCT; + +typedef union { + struct { + U32 RcompOdtUp : 6; // Bits 5:0 + U32 Spare0 : 3; // Bits 8:6 + U32 RcompOdtDown : 6; // Bits 14:9 + U32 Spare1 : 1; // Bits 15:15 + U32 PanicDrvDn : 6; // Bits 21:16 + U32 PanicDrvUp : 6; // Bits 27:22 + U32 LevelShifterComp : 3; // Bits 30:28 + U32 Spare2 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATACH1_CR_RCOMPDATA1_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATACH1_CR_TXXTALK_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATACH1_CR_RXOFFSETVDQ_STRUCT; + +typedef union { + struct { + U32 Spare : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATACH1_CR_DDRDATARESERVED_STRUCT; + +typedef union { + struct { + U32 DataTrainFeedback : 9; // Bits 8:0 + U32 Spare : 23; // Bits 31:9 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATACH1_CR_DATATRAINFEEDBACK_STRUCT; + +typedef union { + struct { + U32 RunTest : 1; // Bits 0:0 + U32 Load : 1; // Bits 1:1 + U32 ModeHVM : 1; // Bits 2:2 + U32 ModeDV : 1; // Bits 3:3 + U32 ModeADC : 1; // Bits 4:4 + U32 LoadCount : 10; // Bits 14:5 + U32 CountStatus : 10; // Bits 24:15 + U32 Spare : 7; // Bits 31:25 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATACH1_CR_DLLPITESTANDADC_STRUCT; + +typedef union { + struct { + U32 DqDrvUpCompOffset : 6; // Bits 5:0 + U32 DqDrvDownCompOffset : 6; // Bits 11:6 + U32 DqOdtUpCompOffset : 5; // Bits 16:12 + U32 DqOdtDownCompOffset : 5; // Bits 21:17 + U32 DqTcoCompOffset : 5; // Bits 26:22 + U32 DqSlewRateCompOffset : 5; // Bits 31:27 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATACH1_CR_DDRCRDATAOFFSETCOMP_STRUCT; + +typedef union { + struct { + U32 RefPi : 4; // Bits 3:0 + U32 DllMask : 2; // Bits 5:4 + U32 DllWeakLock : 1; // Bits 6:6 + U32 SdllSegmentDisable : 3; // Bits 9:7 + U32 RxBiasCtl : 3; // Bits 12:10 + U32 OdtDelay : 4; // Bits 16:13 + U32 OdtDuration : 3; // Bits 19:17 + U32 SenseAmpDelay : 4; // Bits 23:20 + U32 SenseAmpDuration : 3; // Bits 26:24 + U32 BurstEndODTDelay : 3; // Bits 29:27 + U32 LpDdrLongOdtEn : 1; // Bits 30:30 + U32 Rsvd1 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATACH1_CR_DDRCRDATACONTROL1_STRUCT; + +typedef union { + struct { + U32 RxStaggerCtl : 5; // Bits 4:0 + U32 ForceBiasOn : 1; // Bits 5:5 + U32 ForceRxOn : 1; // Bits 6:6 + U32 LeakerComp : 2; // Bits 8:7 + U32 RxDqsAmpOffset : 4; // Bits 12:9 + U32 RxClkStgNum : 5; // Bits 17:13 + U32 WlLongDelEn : 1; // Bits 18:18 + U32 Spare : 13; // Bits 31:19 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATACH1_CR_DDRCRDATACONTROL2_STRUCT; + +typedef union { + struct { + U32 VssHiOrVrefCtl : 24; // Bits 23:0 + U32 OutputCode : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATACH1_CR_DDRCRVSSHIORVREFCONTROL_STRUCT; + +typedef union { + struct { + U32 RcvEnOffset : 6; // Bits 5:0 + U32 RxDqsOffset : 6; // Bits 11:6 + U32 TxDqOffset : 6; // Bits 17:12 + U32 TxDqsOffset : 6; // Bits 23:18 + U32 VrefOffset : 7; // Bits 30:24 + U32 Spare : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATACH1_CR_DDRCRDATAOFFSETTRAIN_STRUCT; + +typedef union { + struct { + U32 RxTrainingMode : 1; // Bits 0:0 + U32 WLTrainingMode : 1; // Bits 1:1 + U32 RLTrainingMode : 1; // Bits 2:2 + U32 SenseampTrainingMode : 1; // Bits 3:3 + U32 TxOn : 1; // Bits 4:4 + U32 RfOn : 1; // Bits 5:5 + U32 RxPiOn : 1; // Bits 6:6 + U32 TxPiOn : 1; // Bits 7:7 + U32 InternalClocksOn : 1; // Bits 8:8 + U32 RepeaterClocksOn : 1; // Bits 9:9 + U32 TxDisable : 1; // Bits 10:10 + U32 RxDisable : 1; // Bits 11:11 + U32 TxLong : 1; // Bits 12:12 + U32 RxDqsCtle : 2; // Bits 14:13 + U32 RxReadPointer : 3; // Bits 17:15 + U32 DriverSegmentEnable : 1; // Bits 18:18 + U32 DataVccddqHi : 1; // Bits 19:19 + U32 ReadRFRd : 1; // Bits 20:20 + U32 ReadRFWr : 1; // Bits 21:21 + U32 ReadRFRank : 2; // Bits 23:22 + U32 ForceOdtOn : 1; // Bits 24:24 + U32 OdtSampOff : 1; // Bits 25:25 + U32 DisableOdtStatic : 1; // Bits 26:26 + U32 DdrCRForceODTOn : 1; // Bits 27:27 + U32 LPDDR_Mode : 1; // Bits 28:28 + U32 EnReadPreamble : 1; // Bits 29:29 + U32 OdtSampExtendEn : 1; // Bits 30:30 + U32 EarlyRleakEn : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATACH1_CR_DDRCRDATACONTROL0_STRUCT; + +typedef union { + struct { + U32 CAVrefCtl : 7; // Bits 6:0 + U32 Ch1VrefCtl : 7; // Bits 13:7 + U32 Ch0VrefCtl : 7; // Bits 20:14 + U32 EnDimmVrefCA : 1; // Bits 21:21 + U32 EnDimmVrefCh1 : 1; // Bits 22:22 + U32 EnDimmVrefCh0 : 1; // Bits 23:23 + U32 HiZTimerCtrl : 2; // Bits 25:24 + U32 VccddqHiQnnnH : 1; // Bits 26:26 + U32 Rsvd : 2; // Bits 28:27 + U32 caSlowBW : 1; // Bits 29:29 + U32 ch0SlowBW : 1; // Bits 30:30 + U32 ch1SlowBW : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATACH1_CR_DDRCRVREFADJUST1_STRUCT; + +typedef union { + struct { + U32 RxRcvEnPi : 9; // Bits 8:0 + U32 RxDqsPPi : 6; // Bits 14:9 + U32 RxEq : 5; // Bits 19:15 + U32 RxDqsNPi : 6; // Bits 25:20 + U32 RxVref : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA0CH0_CR_RXTRAINRANK0_STRUCT; + +typedef union { + struct { + U32 RxRcvEnPi : 9; // Bits 8:0 + U32 RxDqsPPi : 6; // Bits 14:9 + U32 RxEq : 5; // Bits 19:15 + U32 RxDqsNPi : 6; // Bits 25:20 + U32 RxVref : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA0CH0_CR_RXTRAINRANK1_STRUCT; + +typedef union { + struct { + U32 RxRcvEnPi : 9; // Bits 8:0 + U32 RxDqsPPi : 6; // Bits 14:9 + U32 RxEq : 5; // Bits 19:15 + U32 RxDqsNPi : 6; // Bits 25:20 + U32 RxVref : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA0CH0_CR_RXTRAINRANK2_STRUCT; + +typedef union { + struct { + U32 RxRcvEnPi : 9; // Bits 8:0 + U32 RxDqsPPi : 6; // Bits 14:9 + U32 RxEq : 5; // Bits 19:15 + U32 RxDqsNPi : 6; // Bits 25:20 + U32 RxVref : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA0CH0_CR_RXTRAINRANK3_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA0CH0_CR_RXPERBITRANK0_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA0CH0_CR_RXPERBITRANK1_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA0CH0_CR_RXPERBITRANK2_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA0CH0_CR_RXPERBITRANK3_STRUCT; + +typedef union { + struct { + U32 TxDqDelay : 9; // Bits 8:0 + U32 TxDqsDelay : 9; // Bits 17:9 + U32 Spare0 : 2; // Bits 19:18 + U32 TxEqualization : 6; // Bits 25:20 + U32 Spare1 : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA0CH0_CR_TXTRAINRANK0_STRUCT; + +typedef union { + struct { + U32 TxDqDelay : 9; // Bits 8:0 + U32 TxDqsDelay : 9; // Bits 17:9 + U32 Spare0 : 2; // Bits 19:18 + U32 TxEqualization : 6; // Bits 25:20 + U32 Spare1 : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA0CH0_CR_TXTRAINRANK1_STRUCT; + +typedef union { + struct { + U32 TxDqDelay : 9; // Bits 8:0 + U32 TxDqsDelay : 9; // Bits 17:9 + U32 Spare0 : 2; // Bits 19:18 + U32 TxEqualization : 6; // Bits 25:20 + U32 Spare1 : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA0CH0_CR_TXTRAINRANK2_STRUCT; + +typedef union { + struct { + U32 TxDqDelay : 9; // Bits 8:0 + U32 TxDqsDelay : 9; // Bits 17:9 + U32 Spare0 : 2; // Bits 19:18 + U32 TxEqualization : 6; // Bits 25:20 + U32 Spare1 : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA0CH0_CR_TXTRAINRANK3_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA0CH0_CR_TXPERBITRANK0_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA0CH0_CR_TXPERBITRANK1_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA0CH0_CR_TXPERBITRANK2_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA0CH0_CR_TXPERBITRANK3_STRUCT; + +typedef union { + struct { + U32 RcompDrvUp : 6; // Bits 5:0 + U32 Spare0 : 3; // Bits 8:6 + U32 RcompDrvDown : 6; // Bits 14:9 + U32 VTComp : 5; // Bits 19:15 + U32 TcoComp : 6; // Bits 25:20 + U32 SlewRateComp : 5; // Bits 30:26 + U32 Spare2 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA0CH0_CR_RCOMPDATA0_STRUCT; + +typedef union { + struct { + U32 RcompOdtUp : 6; // Bits 5:0 + U32 Spare0 : 3; // Bits 8:6 + U32 RcompOdtDown : 6; // Bits 14:9 + U32 Spare1 : 1; // Bits 15:15 + U32 PanicDrvDn : 6; // Bits 21:16 + U32 PanicDrvUp : 6; // Bits 27:22 + U32 LevelShifterComp : 3; // Bits 30:28 + U32 Spare2 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA0CH0_CR_RCOMPDATA1_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA0CH0_CR_TXXTALK_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA0CH0_CR_RXOFFSETVDQ_STRUCT; + +typedef union { + struct { + U32 Spare : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA0CH0_CR_DDRDATARESERVED_STRUCT; + +typedef union { + struct { + U32 DataTrainFeedback : 9; // Bits 8:0 + U32 Spare : 23; // Bits 31:9 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA0CH0_CR_DATATRAINFEEDBACK_STRUCT; + +typedef union { + struct { + U32 RunTest : 1; // Bits 0:0 + U32 Load : 1; // Bits 1:1 + U32 ModeHVM : 1; // Bits 2:2 + U32 ModeDV : 1; // Bits 3:3 + U32 ModeADC : 1; // Bits 4:4 + U32 LoadCount : 10; // Bits 14:5 + U32 CountStatus : 10; // Bits 24:15 + U32 Spare : 7; // Bits 31:25 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA0CH0_CR_DLLPITESTANDADC_STRUCT; + +typedef union { + struct { + U32 DqDrvUpCompOffset : 6; // Bits 5:0 + U32 DqDrvDownCompOffset : 6; // Bits 11:6 + U32 DqOdtUpCompOffset : 5; // Bits 16:12 + U32 DqOdtDownCompOffset : 5; // Bits 21:17 + U32 DqTcoCompOffset : 5; // Bits 26:22 + U32 DqSlewRateCompOffset : 5; // Bits 31:27 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_STRUCT; + +typedef union { + struct { + U32 RefPi : 4; // Bits 3:0 + U32 DllMask : 2; // Bits 5:4 + U32 DllWeakLock : 1; // Bits 6:6 + U32 SdllSegmentDisable : 3; // Bits 9:7 + U32 RxBiasCtl : 3; // Bits 12:10 + U32 OdtDelay : 4; // Bits 16:13 + U32 OdtDuration : 3; // Bits 19:17 + U32 SenseAmpDelay : 4; // Bits 23:20 + U32 SenseAmpDuration : 3; // Bits 26:24 + U32 BurstEndODTDelay : 3; // Bits 29:27 + U32 LpDdrLongOdtEn : 1; // Bits 30:30 + U32 Rsvd1 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA0CH0_CR_DDRCRDATACONTROL1_STRUCT; + +typedef union { + struct { + U32 RxStaggerCtl : 5; // Bits 4:0 + U32 ForceBiasOn : 1; // Bits 5:5 + U32 ForceRxOn : 1; // Bits 6:6 + U32 LeakerComp : 2; // Bits 8:7 + U32 RxDqsAmpOffset : 4; // Bits 12:9 + U32 RxClkStgNum : 5; // Bits 17:13 + U32 WlLongDelEn : 1; // Bits 18:18 + U32 Spare : 13; // Bits 31:19 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA0CH0_CR_DDRCRDATACONTROL2_STRUCT; + +typedef union { + struct { + U32 VssHiOrVrefCtl : 24; // Bits 23:0 + U32 OutputCode : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA0CH0_CR_DDRCRVSSHIORVREFCONTROL_STRUCT; + +typedef union { + struct { + U32 RcvEnOffset : 6; // Bits 5:0 + U32 RxDqsOffset : 6; // Bits 11:6 + U32 TxDqOffset : 6; // Bits 17:12 + U32 TxDqsOffset : 6; // Bits 23:18 + U32 VrefOffset : 7; // Bits 30:24 + U32 Spare : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_STRUCT; + +typedef union { + struct { + U32 RxTrainingMode : 1; // Bits 0:0 + U32 WLTrainingMode : 1; // Bits 1:1 + U32 RLTrainingMode : 1; // Bits 2:2 + U32 SenseampTrainingMode : 1; // Bits 3:3 + U32 TxOn : 1; // Bits 4:4 + U32 RfOn : 1; // Bits 5:5 + U32 RxPiOn : 1; // Bits 6:6 + U32 TxPiOn : 1; // Bits 7:7 + U32 InternalClocksOn : 1; // Bits 8:8 + U32 RepeaterClocksOn : 1; // Bits 9:9 + U32 TxDisable : 1; // Bits 10:10 + U32 RxDisable : 1; // Bits 11:11 + U32 TxLong : 1; // Bits 12:12 + U32 RxDqsCtle : 2; // Bits 14:13 + U32 RxReadPointer : 3; // Bits 17:15 + U32 DriverSegmentEnable : 1; // Bits 18:18 + U32 DataVccddqHi : 1; // Bits 19:19 + U32 ReadRFRd : 1; // Bits 20:20 + U32 ReadRFWr : 1; // Bits 21:21 + U32 ReadRFRank : 2; // Bits 23:22 + U32 ForceOdtOn : 1; // Bits 24:24 + U32 OdtSampOff : 1; // Bits 25:25 + U32 DisableOdtStatic : 1; // Bits 26:26 + U32 DdrCRForceODTOn : 1; // Bits 27:27 + U32 LPDDR_Mode : 1; // Bits 28:28 + U32 EnReadPreamble : 1; // Bits 29:29 + U32 OdtSampExtendEn : 1; // Bits 30:30 + U32 EarlyRleakEn : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA0CH0_CR_DDRCRDATACONTROL0_STRUCT; + +typedef union { + struct { + U32 CAVrefCtl : 7; // Bits 6:0 + U32 Ch1VrefCtl : 7; // Bits 13:7 + U32 Ch0VrefCtl : 7; // Bits 20:14 + U32 EnDimmVrefCA : 1; // Bits 21:21 + U32 EnDimmVrefCh1 : 1; // Bits 22:22 + U32 EnDimmVrefCh0 : 1; // Bits 23:23 + U32 HiZTimerCtrl : 2; // Bits 25:24 + U32 VccddqHiQnnnH : 1; // Bits 26:26 + U32 Rsvd : 2; // Bits 28:27 + U32 caSlowBW : 1; // Bits 29:29 + U32 ch0SlowBW : 1; // Bits 30:30 + U32 ch1SlowBW : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA0CH0_CR_DDRCRVREFADJUST1_STRUCT; + +typedef union { + struct { + U32 RxRcvEnPi : 9; // Bits 8:0 + U32 RxDqsPPi : 6; // Bits 14:9 + U32 RxEq : 5; // Bits 19:15 + U32 RxDqsNPi : 6; // Bits 25:20 + U32 RxVref : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA0CH1_CR_RXTRAINRANK0_STRUCT; + +typedef union { + struct { + U32 RxRcvEnPi : 9; // Bits 8:0 + U32 RxDqsPPi : 6; // Bits 14:9 + U32 RxEq : 5; // Bits 19:15 + U32 RxDqsNPi : 6; // Bits 25:20 + U32 RxVref : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA0CH1_CR_RXTRAINRANK1_STRUCT; + +typedef union { + struct { + U32 RxRcvEnPi : 9; // Bits 8:0 + U32 RxDqsPPi : 6; // Bits 14:9 + U32 RxEq : 5; // Bits 19:15 + U32 RxDqsNPi : 6; // Bits 25:20 + U32 RxVref : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA0CH1_CR_RXTRAINRANK2_STRUCT; + +typedef union { + struct { + U32 RxRcvEnPi : 9; // Bits 8:0 + U32 RxDqsPPi : 6; // Bits 14:9 + U32 RxEq : 5; // Bits 19:15 + U32 RxDqsNPi : 6; // Bits 25:20 + U32 RxVref : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA0CH1_CR_RXTRAINRANK3_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA0CH1_CR_RXPERBITRANK0_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA0CH1_CR_RXPERBITRANK1_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA0CH1_CR_RXPERBITRANK2_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA0CH1_CR_RXPERBITRANK3_STRUCT; + +typedef union { + struct { + U32 TxDqDelay : 9; // Bits 8:0 + U32 TxDqsDelay : 9; // Bits 17:9 + U32 Spare0 : 2; // Bits 19:18 + U32 TxEqualization : 6; // Bits 25:20 + U32 Spare1 : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA0CH1_CR_TXTRAINRANK0_STRUCT; + +typedef union { + struct { + U32 TxDqDelay : 9; // Bits 8:0 + U32 TxDqsDelay : 9; // Bits 17:9 + U32 Spare0 : 2; // Bits 19:18 + U32 TxEqualization : 6; // Bits 25:20 + U32 Spare1 : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA0CH1_CR_TXTRAINRANK1_STRUCT; + +typedef union { + struct { + U32 TxDqDelay : 9; // Bits 8:0 + U32 TxDqsDelay : 9; // Bits 17:9 + U32 Spare0 : 2; // Bits 19:18 + U32 TxEqualization : 6; // Bits 25:20 + U32 Spare1 : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA0CH1_CR_TXTRAINRANK2_STRUCT; + +typedef union { + struct { + U32 TxDqDelay : 9; // Bits 8:0 + U32 TxDqsDelay : 9; // Bits 17:9 + U32 Spare0 : 2; // Bits 19:18 + U32 TxEqualization : 6; // Bits 25:20 + U32 Spare1 : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA0CH1_CR_TXTRAINRANK3_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA0CH1_CR_TXPERBITRANK0_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA0CH1_CR_TXPERBITRANK1_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA0CH1_CR_TXPERBITRANK2_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA0CH1_CR_TXPERBITRANK3_STRUCT; + +typedef union { + struct { + U32 RcompDrvUp : 6; // Bits 5:0 + U32 Spare0 : 3; // Bits 8:6 + U32 RcompDrvDown : 6; // Bits 14:9 + U32 VTComp : 5; // Bits 19:15 + U32 TcoComp : 6; // Bits 25:20 + U32 SlewRateComp : 5; // Bits 30:26 + U32 Spare2 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA0CH1_CR_RCOMPDATA0_STRUCT; + +typedef union { + struct { + U32 RcompOdtUp : 6; // Bits 5:0 + U32 Spare0 : 3; // Bits 8:6 + U32 RcompOdtDown : 6; // Bits 14:9 + U32 Spare1 : 1; // Bits 15:15 + U32 PanicDrvDn : 6; // Bits 21:16 + U32 PanicDrvUp : 6; // Bits 27:22 + U32 LevelShifterComp : 3; // Bits 30:28 + U32 Spare2 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA0CH1_CR_RCOMPDATA1_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA0CH1_CR_TXXTALK_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA0CH1_CR_RXOFFSETVDQ_STRUCT; + +typedef union { + struct { + U32 Spare : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA0CH1_CR_DDRDATARESERVED_STRUCT; + +typedef union { + struct { + U32 DataTrainFeedback : 9; // Bits 8:0 + U32 Spare : 23; // Bits 31:9 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA0CH1_CR_DATATRAINFEEDBACK_STRUCT; + +typedef union { + struct { + U32 RunTest : 1; // Bits 0:0 + U32 Load : 1; // Bits 1:1 + U32 ModeHVM : 1; // Bits 2:2 + U32 ModeDV : 1; // Bits 3:3 + U32 ModeADC : 1; // Bits 4:4 + U32 LoadCount : 10; // Bits 14:5 + U32 CountStatus : 10; // Bits 24:15 + U32 Spare : 7; // Bits 31:25 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA0CH1_CR_DLLPITESTANDADC_STRUCT; + +typedef union { + struct { + U32 DqDrvUpCompOffset : 6; // Bits 5:0 + U32 DqDrvDownCompOffset : 6; // Bits 11:6 + U32 DqOdtUpCompOffset : 5; // Bits 16:12 + U32 DqOdtDownCompOffset : 5; // Bits 21:17 + U32 DqTcoCompOffset : 5; // Bits 26:22 + U32 DqSlewRateCompOffset : 5; // Bits 31:27 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_STRUCT; + +typedef union { + struct { + U32 RefPi : 4; // Bits 3:0 + U32 DllMask : 2; // Bits 5:4 + U32 DllWeakLock : 1; // Bits 6:6 + U32 SdllSegmentDisable : 3; // Bits 9:7 + U32 RxBiasCtl : 3; // Bits 12:10 + U32 OdtDelay : 4; // Bits 16:13 + U32 OdtDuration : 3; // Bits 19:17 + U32 SenseAmpDelay : 4; // Bits 23:20 + U32 SenseAmpDuration : 3; // Bits 26:24 + U32 BurstEndODTDelay : 3; // Bits 29:27 + U32 LpDdrLongOdtEn : 1; // Bits 30:30 + U32 Rsvd1 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA0CH1_CR_DDRCRDATACONTROL1_STRUCT; + +typedef union { + struct { + U32 RxStaggerCtl : 5; // Bits 4:0 + U32 ForceBiasOn : 1; // Bits 5:5 + U32 ForceRxOn : 1; // Bits 6:6 + U32 LeakerComp : 2; // Bits 8:7 + U32 RxDqsAmpOffset : 4; // Bits 12:9 + U32 RxClkStgNum : 5; // Bits 17:13 + U32 WlLongDelEn : 1; // Bits 18:18 + U32 Spare : 13; // Bits 31:19 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA0CH1_CR_DDRCRDATACONTROL2_STRUCT; + +typedef union { + struct { + U32 VssHiOrVrefCtl : 24; // Bits 23:0 + U32 OutputCode : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA0CH1_CR_DDRCRVSSHIORVREFCONTROL_STRUCT; + +typedef union { + struct { + U32 RcvEnOffset : 6; // Bits 5:0 + U32 RxDqsOffset : 6; // Bits 11:6 + U32 TxDqOffset : 6; // Bits 17:12 + U32 TxDqsOffset : 6; // Bits 23:18 + U32 VrefOffset : 7; // Bits 30:24 + U32 Spare : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_STRUCT; + +typedef union { + struct { + U32 RxTrainingMode : 1; // Bits 0:0 + U32 WLTrainingMode : 1; // Bits 1:1 + U32 RLTrainingMode : 1; // Bits 2:2 + U32 SenseampTrainingMode : 1; // Bits 3:3 + U32 TxOn : 1; // Bits 4:4 + U32 RfOn : 1; // Bits 5:5 + U32 RxPiOn : 1; // Bits 6:6 + U32 TxPiOn : 1; // Bits 7:7 + U32 InternalClocksOn : 1; // Bits 8:8 + U32 RepeaterClocksOn : 1; // Bits 9:9 + U32 TxDisable : 1; // Bits 10:10 + U32 RxDisable : 1; // Bits 11:11 + U32 TxLong : 1; // Bits 12:12 + U32 RxDqsCtle : 2; // Bits 14:13 + U32 RxReadPointer : 3; // Bits 17:15 + U32 DriverSegmentEnable : 1; // Bits 18:18 + U32 DataVccddqHi : 1; // Bits 19:19 + U32 ReadRFRd : 1; // Bits 20:20 + U32 ReadRFWr : 1; // Bits 21:21 + U32 ReadRFRank : 2; // Bits 23:22 + U32 ForceOdtOn : 1; // Bits 24:24 + U32 OdtSampOff : 1; // Bits 25:25 + U32 DisableOdtStatic : 1; // Bits 26:26 + U32 DdrCRForceODTOn : 1; // Bits 27:27 + U32 LPDDR_Mode : 1; // Bits 28:28 + U32 EnReadPreamble : 1; // Bits 29:29 + U32 OdtSampExtendEn : 1; // Bits 30:30 + U32 EarlyRleakEn : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA0CH1_CR_DDRCRDATACONTROL0_STRUCT; + +typedef union { + struct { + U32 CAVrefCtl : 7; // Bits 6:0 + U32 Ch1VrefCtl : 7; // Bits 13:7 + U32 Ch0VrefCtl : 7; // Bits 20:14 + U32 EnDimmVrefCA : 1; // Bits 21:21 + U32 EnDimmVrefCh1 : 1; // Bits 22:22 + U32 EnDimmVrefCh0 : 1; // Bits 23:23 + U32 HiZTimerCtrl : 2; // Bits 25:24 + U32 VccddqHiQnnnH : 1; // Bits 26:26 + U32 Rsvd : 2; // Bits 28:27 + U32 caSlowBW : 1; // Bits 29:29 + U32 ch0SlowBW : 1; // Bits 30:30 + U32 ch1SlowBW : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA0CH1_CR_DDRCRVREFADJUST1_STRUCT; + +typedef union { + struct { + U32 RxRcvEnPi : 9; // Bits 8:0 + U32 RxDqsPPi : 6; // Bits 14:9 + U32 RxEq : 5; // Bits 19:15 + U32 RxDqsNPi : 6; // Bits 25:20 + U32 RxVref : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA1CH0_CR_RXTRAINRANK0_STRUCT; + +typedef union { + struct { + U32 RxRcvEnPi : 9; // Bits 8:0 + U32 RxDqsPPi : 6; // Bits 14:9 + U32 RxEq : 5; // Bits 19:15 + U32 RxDqsNPi : 6; // Bits 25:20 + U32 RxVref : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA1CH0_CR_RXTRAINRANK1_STRUCT; + +typedef union { + struct { + U32 RxRcvEnPi : 9; // Bits 8:0 + U32 RxDqsPPi : 6; // Bits 14:9 + U32 RxEq : 5; // Bits 19:15 + U32 RxDqsNPi : 6; // Bits 25:20 + U32 RxVref : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA1CH0_CR_RXTRAINRANK2_STRUCT; + +typedef union { + struct { + U32 RxRcvEnPi : 9; // Bits 8:0 + U32 RxDqsPPi : 6; // Bits 14:9 + U32 RxEq : 5; // Bits 19:15 + U32 RxDqsNPi : 6; // Bits 25:20 + U32 RxVref : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA1CH0_CR_RXTRAINRANK3_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA1CH0_CR_RXPERBITRANK0_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA1CH0_CR_RXPERBITRANK1_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA1CH0_CR_RXPERBITRANK2_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA1CH0_CR_RXPERBITRANK3_STRUCT; + +typedef union { + struct { + U32 TxDqDelay : 9; // Bits 8:0 + U32 TxDqsDelay : 9; // Bits 17:9 + U32 Spare0 : 2; // Bits 19:18 + U32 TxEqualization : 6; // Bits 25:20 + U32 Spare1 : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA1CH0_CR_TXTRAINRANK0_STRUCT; + +typedef union { + struct { + U32 TxDqDelay : 9; // Bits 8:0 + U32 TxDqsDelay : 9; // Bits 17:9 + U32 Spare0 : 2; // Bits 19:18 + U32 TxEqualization : 6; // Bits 25:20 + U32 Spare1 : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA1CH0_CR_TXTRAINRANK1_STRUCT; + +typedef union { + struct { + U32 TxDqDelay : 9; // Bits 8:0 + U32 TxDqsDelay : 9; // Bits 17:9 + U32 Spare0 : 2; // Bits 19:18 + U32 TxEqualization : 6; // Bits 25:20 + U32 Spare1 : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA1CH0_CR_TXTRAINRANK2_STRUCT; + +typedef union { + struct { + U32 TxDqDelay : 9; // Bits 8:0 + U32 TxDqsDelay : 9; // Bits 17:9 + U32 Spare0 : 2; // Bits 19:18 + U32 TxEqualization : 6; // Bits 25:20 + U32 Spare1 : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA1CH0_CR_TXTRAINRANK3_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA1CH0_CR_TXPERBITRANK0_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA1CH0_CR_TXPERBITRANK1_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA1CH0_CR_TXPERBITRANK2_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA1CH0_CR_TXPERBITRANK3_STRUCT; + +typedef union { + struct { + U32 RcompDrvUp : 6; // Bits 5:0 + U32 Spare0 : 3; // Bits 8:6 + U32 RcompDrvDown : 6; // Bits 14:9 + U32 VTComp : 5; // Bits 19:15 + U32 TcoComp : 6; // Bits 25:20 + U32 SlewRateComp : 5; // Bits 30:26 + U32 Spare2 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA1CH0_CR_RCOMPDATA0_STRUCT; + +typedef union { + struct { + U32 RcompOdtUp : 6; // Bits 5:0 + U32 Spare0 : 3; // Bits 8:6 + U32 RcompOdtDown : 6; // Bits 14:9 + U32 Spare1 : 1; // Bits 15:15 + U32 PanicDrvDn : 6; // Bits 21:16 + U32 PanicDrvUp : 6; // Bits 27:22 + U32 LevelShifterComp : 3; // Bits 30:28 + U32 Spare2 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA1CH0_CR_RCOMPDATA1_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA1CH0_CR_TXXTALK_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA1CH0_CR_RXOFFSETVDQ_STRUCT; + +typedef union { + struct { + U32 Spare : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA1CH0_CR_DDRDATARESERVED_STRUCT; + +typedef union { + struct { + U32 DataTrainFeedback : 9; // Bits 8:0 + U32 Spare : 23; // Bits 31:9 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA1CH0_CR_DATATRAINFEEDBACK_STRUCT; + +typedef union { + struct { + U32 RunTest : 1; // Bits 0:0 + U32 Load : 1; // Bits 1:1 + U32 ModeHVM : 1; // Bits 2:2 + U32 ModeDV : 1; // Bits 3:3 + U32 ModeADC : 1; // Bits 4:4 + U32 LoadCount : 10; // Bits 14:5 + U32 CountStatus : 10; // Bits 24:15 + U32 Spare : 7; // Bits 31:25 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA1CH0_CR_DLLPITESTANDADC_STRUCT; + +typedef union { + struct { + U32 DqDrvUpCompOffset : 6; // Bits 5:0 + U32 DqDrvDownCompOffset : 6; // Bits 11:6 + U32 DqOdtUpCompOffset : 5; // Bits 16:12 + U32 DqOdtDownCompOffset : 5; // Bits 21:17 + U32 DqTcoCompOffset : 5; // Bits 26:22 + U32 DqSlewRateCompOffset : 5; // Bits 31:27 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_STRUCT; + +typedef union { + struct { + U32 RefPi : 4; // Bits 3:0 + U32 DllMask : 2; // Bits 5:4 + U32 DllWeakLock : 1; // Bits 6:6 + U32 SdllSegmentDisable : 3; // Bits 9:7 + U32 RxBiasCtl : 3; // Bits 12:10 + U32 OdtDelay : 4; // Bits 16:13 + U32 OdtDuration : 3; // Bits 19:17 + U32 SenseAmpDelay : 4; // Bits 23:20 + U32 SenseAmpDuration : 3; // Bits 26:24 + U32 BurstEndODTDelay : 3; // Bits 29:27 + U32 LpDdrLongOdtEn : 1; // Bits 30:30 + U32 Rsvd1 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA1CH0_CR_DDRCRDATACONTROL1_STRUCT; + +typedef union { + struct { + U32 RxStaggerCtl : 5; // Bits 4:0 + U32 ForceBiasOn : 1; // Bits 5:5 + U32 ForceRxOn : 1; // Bits 6:6 + U32 LeakerComp : 2; // Bits 8:7 + U32 RxDqsAmpOffset : 4; // Bits 12:9 + U32 RxClkStgNum : 5; // Bits 17:13 + U32 WlLongDelEn : 1; // Bits 18:18 + U32 Spare : 13; // Bits 31:19 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA1CH0_CR_DDRCRDATACONTROL2_STRUCT; + +typedef union { + struct { + U32 VssHiOrVrefCtl : 24; // Bits 23:0 + U32 OutputCode : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA1CH0_CR_DDRCRVSSHIORVREFCONTROL_STRUCT; + +typedef union { + struct { + U32 RcvEnOffset : 6; // Bits 5:0 + U32 RxDqsOffset : 6; // Bits 11:6 + U32 TxDqOffset : 6; // Bits 17:12 + U32 TxDqsOffset : 6; // Bits 23:18 + U32 VrefOffset : 7; // Bits 30:24 + U32 Spare : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_STRUCT; + +typedef union { + struct { + U32 RxTrainingMode : 1; // Bits 0:0 + U32 WLTrainingMode : 1; // Bits 1:1 + U32 RLTrainingMode : 1; // Bits 2:2 + U32 SenseampTrainingMode : 1; // Bits 3:3 + U32 TxOn : 1; // Bits 4:4 + U32 RfOn : 1; // Bits 5:5 + U32 RxPiOn : 1; // Bits 6:6 + U32 TxPiOn : 1; // Bits 7:7 + U32 InternalClocksOn : 1; // Bits 8:8 + U32 RepeaterClocksOn : 1; // Bits 9:9 + U32 TxDisable : 1; // Bits 10:10 + U32 RxDisable : 1; // Bits 11:11 + U32 TxLong : 1; // Bits 12:12 + U32 RxDqsCtle : 2; // Bits 14:13 + U32 RxReadPointer : 3; // Bits 17:15 + U32 DriverSegmentEnable : 1; // Bits 18:18 + U32 DataVccddqHi : 1; // Bits 19:19 + U32 ReadRFRd : 1; // Bits 20:20 + U32 ReadRFWr : 1; // Bits 21:21 + U32 ReadRFRank : 2; // Bits 23:22 + U32 ForceOdtOn : 1; // Bits 24:24 + U32 OdtSampOff : 1; // Bits 25:25 + U32 DisableOdtStatic : 1; // Bits 26:26 + U32 DdrCRForceODTOn : 1; // Bits 27:27 + U32 LPDDR_Mode : 1; // Bits 28:28 + U32 EnReadPreamble : 1; // Bits 29:29 + U32 OdtSampExtendEn : 1; // Bits 30:30 + U32 EarlyRleakEn : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA1CH0_CR_DDRCRDATACONTROL0_STRUCT; + +typedef union { + struct { + U32 CAVrefCtl : 7; // Bits 6:0 + U32 Ch1VrefCtl : 7; // Bits 13:7 + U32 Ch0VrefCtl : 7; // Bits 20:14 + U32 EnDimmVrefCA : 1; // Bits 21:21 + U32 EnDimmVrefCh1 : 1; // Bits 22:22 + U32 EnDimmVrefCh0 : 1; // Bits 23:23 + U32 HiZTimerCtrl : 2; // Bits 25:24 + U32 VccddqHiQnnnH : 1; // Bits 26:26 + U32 Rsvd : 2; // Bits 28:27 + U32 caSlowBW : 1; // Bits 29:29 + U32 ch0SlowBW : 1; // Bits 30:30 + U32 ch1SlowBW : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA1CH0_CR_DDRCRVREFADJUST1_STRUCT; + +typedef union { + struct { + U32 RxRcvEnPi : 9; // Bits 8:0 + U32 RxDqsPPi : 6; // Bits 14:9 + U32 RxEq : 5; // Bits 19:15 + U32 RxDqsNPi : 6; // Bits 25:20 + U32 RxVref : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA1CH1_CR_RXTRAINRANK0_STRUCT; + +typedef union { + struct { + U32 RxRcvEnPi : 9; // Bits 8:0 + U32 RxDqsPPi : 6; // Bits 14:9 + U32 RxEq : 5; // Bits 19:15 + U32 RxDqsNPi : 6; // Bits 25:20 + U32 RxVref : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA1CH1_CR_RXTRAINRANK1_STRUCT; + +typedef union { + struct { + U32 RxRcvEnPi : 9; // Bits 8:0 + U32 RxDqsPPi : 6; // Bits 14:9 + U32 RxEq : 5; // Bits 19:15 + U32 RxDqsNPi : 6; // Bits 25:20 + U32 RxVref : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA1CH1_CR_RXTRAINRANK2_STRUCT; + +typedef union { + struct { + U32 RxRcvEnPi : 9; // Bits 8:0 + U32 RxDqsPPi : 6; // Bits 14:9 + U32 RxEq : 5; // Bits 19:15 + U32 RxDqsNPi : 6; // Bits 25:20 + U32 RxVref : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA1CH1_CR_RXTRAINRANK3_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA1CH1_CR_RXPERBITRANK0_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA1CH1_CR_RXPERBITRANK1_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA1CH1_CR_RXPERBITRANK2_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA1CH1_CR_RXPERBITRANK3_STRUCT; + +typedef union { + struct { + U32 TxDqDelay : 9; // Bits 8:0 + U32 TxDqsDelay : 9; // Bits 17:9 + U32 Spare0 : 2; // Bits 19:18 + U32 TxEqualization : 6; // Bits 25:20 + U32 Spare1 : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA1CH1_CR_TXTRAINRANK0_STRUCT; + +typedef union { + struct { + U32 TxDqDelay : 9; // Bits 8:0 + U32 TxDqsDelay : 9; // Bits 17:9 + U32 Spare0 : 2; // Bits 19:18 + U32 TxEqualization : 6; // Bits 25:20 + U32 Spare1 : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA1CH1_CR_TXTRAINRANK1_STRUCT; + +typedef union { + struct { + U32 TxDqDelay : 9; // Bits 8:0 + U32 TxDqsDelay : 9; // Bits 17:9 + U32 Spare0 : 2; // Bits 19:18 + U32 TxEqualization : 6; // Bits 25:20 + U32 Spare1 : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA1CH1_CR_TXTRAINRANK2_STRUCT; + +typedef union { + struct { + U32 TxDqDelay : 9; // Bits 8:0 + U32 TxDqsDelay : 9; // Bits 17:9 + U32 Spare0 : 2; // Bits 19:18 + U32 TxEqualization : 6; // Bits 25:20 + U32 Spare1 : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA1CH1_CR_TXTRAINRANK3_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA1CH1_CR_TXPERBITRANK0_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA1CH1_CR_TXPERBITRANK1_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA1CH1_CR_TXPERBITRANK2_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA1CH1_CR_TXPERBITRANK3_STRUCT; + +typedef union { + struct { + U32 RcompDrvUp : 6; // Bits 5:0 + U32 Spare0 : 3; // Bits 8:6 + U32 RcompDrvDown : 6; // Bits 14:9 + U32 VTComp : 5; // Bits 19:15 + U32 TcoComp : 6; // Bits 25:20 + U32 SlewRateComp : 5; // Bits 30:26 + U32 Spare2 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA1CH1_CR_RCOMPDATA0_STRUCT; + +typedef union { + struct { + U32 RcompOdtUp : 6; // Bits 5:0 + U32 Spare0 : 3; // Bits 8:6 + U32 RcompOdtDown : 6; // Bits 14:9 + U32 Spare1 : 1; // Bits 15:15 + U32 PanicDrvDn : 6; // Bits 21:16 + U32 PanicDrvUp : 6; // Bits 27:22 + U32 LevelShifterComp : 3; // Bits 30:28 + U32 Spare2 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA1CH1_CR_RCOMPDATA1_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA1CH1_CR_TXXTALK_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA1CH1_CR_RXOFFSETVDQ_STRUCT; + +typedef union { + struct { + U32 Spare : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA1CH1_CR_DDRDATARESERVED_STRUCT; + +typedef union { + struct { + U32 DataTrainFeedback : 9; // Bits 8:0 + U32 Spare : 23; // Bits 31:9 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA1CH1_CR_DATATRAINFEEDBACK_STRUCT; + +typedef union { + struct { + U32 RunTest : 1; // Bits 0:0 + U32 Load : 1; // Bits 1:1 + U32 ModeHVM : 1; // Bits 2:2 + U32 ModeDV : 1; // Bits 3:3 + U32 ModeADC : 1; // Bits 4:4 + U32 LoadCount : 10; // Bits 14:5 + U32 CountStatus : 10; // Bits 24:15 + U32 Spare : 7; // Bits 31:25 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA1CH1_CR_DLLPITESTANDADC_STRUCT; + +typedef union { + struct { + U32 DqDrvUpCompOffset : 6; // Bits 5:0 + U32 DqDrvDownCompOffset : 6; // Bits 11:6 + U32 DqOdtUpCompOffset : 5; // Bits 16:12 + U32 DqOdtDownCompOffset : 5; // Bits 21:17 + U32 DqTcoCompOffset : 5; // Bits 26:22 + U32 DqSlewRateCompOffset : 5; // Bits 31:27 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_STRUCT; + +typedef union { + struct { + U32 RefPi : 4; // Bits 3:0 + U32 DllMask : 2; // Bits 5:4 + U32 DllWeakLock : 1; // Bits 6:6 + U32 SdllSegmentDisable : 3; // Bits 9:7 + U32 RxBiasCtl : 3; // Bits 12:10 + U32 OdtDelay : 4; // Bits 16:13 + U32 OdtDuration : 3; // Bits 19:17 + U32 SenseAmpDelay : 4; // Bits 23:20 + U32 SenseAmpDuration : 3; // Bits 26:24 + U32 BurstEndODTDelay : 3; // Bits 29:27 + U32 LpDdrLongOdtEn : 1; // Bits 30:30 + U32 Rsvd1 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA1CH1_CR_DDRCRDATACONTROL1_STRUCT; + +typedef union { + struct { + U32 RxStaggerCtl : 5; // Bits 4:0 + U32 ForceBiasOn : 1; // Bits 5:5 + U32 ForceRxOn : 1; // Bits 6:6 + U32 LeakerComp : 2; // Bits 8:7 + U32 RxDqsAmpOffset : 4; // Bits 12:9 + U32 RxClkStgNum : 5; // Bits 17:13 + U32 WlLongDelEn : 1; // Bits 18:18 + U32 Spare : 13; // Bits 31:19 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA1CH1_CR_DDRCRDATACONTROL2_STRUCT; + +typedef union { + struct { + U32 VssHiOrVrefCtl : 24; // Bits 23:0 + U32 OutputCode : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA1CH1_CR_DDRCRVSSHIORVREFCONTROL_STRUCT; + +typedef union { + struct { + U32 RcvEnOffset : 6; // Bits 5:0 + U32 RxDqsOffset : 6; // Bits 11:6 + U32 TxDqOffset : 6; // Bits 17:12 + U32 TxDqsOffset : 6; // Bits 23:18 + U32 VrefOffset : 7; // Bits 30:24 + U32 Spare : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA1CH1_CR_DDRCRDATAOFFSETTRAIN_STRUCT; + +typedef union { + struct { + U32 RxTrainingMode : 1; // Bits 0:0 + U32 WLTrainingMode : 1; // Bits 1:1 + U32 RLTrainingMode : 1; // Bits 2:2 + U32 SenseampTrainingMode : 1; // Bits 3:3 + U32 TxOn : 1; // Bits 4:4 + U32 RfOn : 1; // Bits 5:5 + U32 RxPiOn : 1; // Bits 6:6 + U32 TxPiOn : 1; // Bits 7:7 + U32 InternalClocksOn : 1; // Bits 8:8 + U32 RepeaterClocksOn : 1; // Bits 9:9 + U32 TxDisable : 1; // Bits 10:10 + U32 RxDisable : 1; // Bits 11:11 + U32 TxLong : 1; // Bits 12:12 + U32 RxDqsCtle : 2; // Bits 14:13 + U32 RxReadPointer : 3; // Bits 17:15 + U32 DriverSegmentEnable : 1; // Bits 18:18 + U32 DataVccddqHi : 1; // Bits 19:19 + U32 ReadRFRd : 1; // Bits 20:20 + U32 ReadRFWr : 1; // Bits 21:21 + U32 ReadRFRank : 2; // Bits 23:22 + U32 ForceOdtOn : 1; // Bits 24:24 + U32 OdtSampOff : 1; // Bits 25:25 + U32 DisableOdtStatic : 1; // Bits 26:26 + U32 DdrCRForceODTOn : 1; // Bits 27:27 + U32 LPDDR_Mode : 1; // Bits 28:28 + U32 EnReadPreamble : 1; // Bits 29:29 + U32 OdtSampExtendEn : 1; // Bits 30:30 + U32 EarlyRleakEn : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA1CH1_CR_DDRCRDATACONTROL0_STRUCT; + +typedef union { + struct { + U32 CAVrefCtl : 7; // Bits 6:0 + U32 Ch1VrefCtl : 7; // Bits 13:7 + U32 Ch0VrefCtl : 7; // Bits 20:14 + U32 EnDimmVrefCA : 1; // Bits 21:21 + U32 EnDimmVrefCh1 : 1; // Bits 22:22 + U32 EnDimmVrefCh0 : 1; // Bits 23:23 + U32 HiZTimerCtrl : 2; // Bits 25:24 + U32 VccddqHiQnnnH : 1; // Bits 26:26 + U32 Rsvd : 2; // Bits 28:27 + U32 caSlowBW : 1; // Bits 29:29 + U32 ch0SlowBW : 1; // Bits 30:30 + U32 ch1SlowBW : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA1CH1_CR_DDRCRVREFADJUST1_STRUCT; + +typedef union { + struct { + U32 RxRcvEnPi : 9; // Bits 8:0 + U32 RxDqsPPi : 6; // Bits 14:9 + U32 RxEq : 5; // Bits 19:15 + U32 RxDqsNPi : 6; // Bits 25:20 + U32 RxVref : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA2CH0_CR_RXTRAINRANK0_STRUCT; + +typedef union { + struct { + U32 RxRcvEnPi : 9; // Bits 8:0 + U32 RxDqsPPi : 6; // Bits 14:9 + U32 RxEq : 5; // Bits 19:15 + U32 RxDqsNPi : 6; // Bits 25:20 + U32 RxVref : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA2CH0_CR_RXTRAINRANK1_STRUCT; + +typedef union { + struct { + U32 RxRcvEnPi : 9; // Bits 8:0 + U32 RxDqsPPi : 6; // Bits 14:9 + U32 RxEq : 5; // Bits 19:15 + U32 RxDqsNPi : 6; // Bits 25:20 + U32 RxVref : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA2CH0_CR_RXTRAINRANK2_STRUCT; + +typedef union { + struct { + U32 RxRcvEnPi : 9; // Bits 8:0 + U32 RxDqsPPi : 6; // Bits 14:9 + U32 RxEq : 5; // Bits 19:15 + U32 RxDqsNPi : 6; // Bits 25:20 + U32 RxVref : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA2CH0_CR_RXTRAINRANK3_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA2CH0_CR_RXPERBITRANK0_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA2CH0_CR_RXPERBITRANK1_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA2CH0_CR_RXPERBITRANK2_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA2CH0_CR_RXPERBITRANK3_STRUCT; + +typedef union { + struct { + U32 TxDqDelay : 9; // Bits 8:0 + U32 TxDqsDelay : 9; // Bits 17:9 + U32 Spare0 : 2; // Bits 19:18 + U32 TxEqualization : 6; // Bits 25:20 + U32 Spare1 : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA2CH0_CR_TXTRAINRANK0_STRUCT; + +typedef union { + struct { + U32 TxDqDelay : 9; // Bits 8:0 + U32 TxDqsDelay : 9; // Bits 17:9 + U32 Spare0 : 2; // Bits 19:18 + U32 TxEqualization : 6; // Bits 25:20 + U32 Spare1 : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA2CH0_CR_TXTRAINRANK1_STRUCT; + +typedef union { + struct { + U32 TxDqDelay : 9; // Bits 8:0 + U32 TxDqsDelay : 9; // Bits 17:9 + U32 Spare0 : 2; // Bits 19:18 + U32 TxEqualization : 6; // Bits 25:20 + U32 Spare1 : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA2CH0_CR_TXTRAINRANK2_STRUCT; + +typedef union { + struct { + U32 TxDqDelay : 9; // Bits 8:0 + U32 TxDqsDelay : 9; // Bits 17:9 + U32 Spare0 : 2; // Bits 19:18 + U32 TxEqualization : 6; // Bits 25:20 + U32 Spare1 : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA2CH0_CR_TXTRAINRANK3_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA2CH0_CR_TXPERBITRANK0_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA2CH0_CR_TXPERBITRANK1_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA2CH0_CR_TXPERBITRANK2_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA2CH0_CR_TXPERBITRANK3_STRUCT; + +typedef union { + struct { + U32 RcompDrvUp : 6; // Bits 5:0 + U32 Spare0 : 3; // Bits 8:6 + U32 RcompDrvDown : 6; // Bits 14:9 + U32 VTComp : 5; // Bits 19:15 + U32 TcoComp : 6; // Bits 25:20 + U32 SlewRateComp : 5; // Bits 30:26 + U32 Spare2 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA2CH0_CR_RCOMPDATA0_STRUCT; + +typedef union { + struct { + U32 RcompOdtUp : 6; // Bits 5:0 + U32 Spare0 : 3; // Bits 8:6 + U32 RcompOdtDown : 6; // Bits 14:9 + U32 Spare1 : 1; // Bits 15:15 + U32 PanicDrvDn : 6; // Bits 21:16 + U32 PanicDrvUp : 6; // Bits 27:22 + U32 LevelShifterComp : 3; // Bits 30:28 + U32 Spare2 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA2CH0_CR_RCOMPDATA1_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA2CH0_CR_TXXTALK_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA2CH0_CR_RXOFFSETVDQ_STRUCT; + +typedef union { + struct { + U32 Spare : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA2CH0_CR_DDRDATARESERVED_STRUCT; + +typedef union { + struct { + U32 DataTrainFeedback : 9; // Bits 8:0 + U32 Spare : 23; // Bits 31:9 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA2CH0_CR_DATATRAINFEEDBACK_STRUCT; + +typedef union { + struct { + U32 RunTest : 1; // Bits 0:0 + U32 Load : 1; // Bits 1:1 + U32 ModeHVM : 1; // Bits 2:2 + U32 ModeDV : 1; // Bits 3:3 + U32 ModeADC : 1; // Bits 4:4 + U32 LoadCount : 10; // Bits 14:5 + U32 CountStatus : 10; // Bits 24:15 + U32 Spare : 7; // Bits 31:25 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA2CH0_CR_DLLPITESTANDADC_STRUCT; + +typedef union { + struct { + U32 DqDrvUpCompOffset : 6; // Bits 5:0 + U32 DqDrvDownCompOffset : 6; // Bits 11:6 + U32 DqOdtUpCompOffset : 5; // Bits 16:12 + U32 DqOdtDownCompOffset : 5; // Bits 21:17 + U32 DqTcoCompOffset : 5; // Bits 26:22 + U32 DqSlewRateCompOffset : 5; // Bits 31:27 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_STRUCT; + +typedef union { + struct { + U32 RefPi : 4; // Bits 3:0 + U32 DllMask : 2; // Bits 5:4 + U32 DllWeakLock : 1; // Bits 6:6 + U32 SdllSegmentDisable : 3; // Bits 9:7 + U32 RxBiasCtl : 3; // Bits 12:10 + U32 OdtDelay : 4; // Bits 16:13 + U32 OdtDuration : 3; // Bits 19:17 + U32 SenseAmpDelay : 4; // Bits 23:20 + U32 SenseAmpDuration : 3; // Bits 26:24 + U32 BurstEndODTDelay : 3; // Bits 29:27 + U32 LpDdrLongOdtEn : 1; // Bits 30:30 + U32 Rsvd1 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA2CH0_CR_DDRCRDATACONTROL1_STRUCT; + +typedef union { + struct { + U32 RxStaggerCtl : 5; // Bits 4:0 + U32 ForceBiasOn : 1; // Bits 5:5 + U32 ForceRxOn : 1; // Bits 6:6 + U32 LeakerComp : 2; // Bits 8:7 + U32 RxDqsAmpOffset : 4; // Bits 12:9 + U32 RxClkStgNum : 5; // Bits 17:13 + U32 WlLongDelEn : 1; // Bits 18:18 + U32 Spare : 13; // Bits 31:19 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA2CH0_CR_DDRCRDATACONTROL2_STRUCT; + +typedef union { + struct { + U32 VssHiOrVrefCtl : 24; // Bits 23:0 + U32 OutputCode : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA2CH0_CR_DDRCRVSSHIORVREFCONTROL_STRUCT; + +typedef union { + struct { + U32 RcvEnOffset : 6; // Bits 5:0 + U32 RxDqsOffset : 6; // Bits 11:6 + U32 TxDqOffset : 6; // Bits 17:12 + U32 TxDqsOffset : 6; // Bits 23:18 + U32 VrefOffset : 7; // Bits 30:24 + U32 Spare : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA2CH0_CR_DDRCRDATAOFFSETTRAIN_STRUCT; + +typedef union { + struct { + U32 RxTrainingMode : 1; // Bits 0:0 + U32 WLTrainingMode : 1; // Bits 1:1 + U32 RLTrainingMode : 1; // Bits 2:2 + U32 SenseampTrainingMode : 1; // Bits 3:3 + U32 TxOn : 1; // Bits 4:4 + U32 RfOn : 1; // Bits 5:5 + U32 RxPiOn : 1; // Bits 6:6 + U32 TxPiOn : 1; // Bits 7:7 + U32 InternalClocksOn : 1; // Bits 8:8 + U32 RepeaterClocksOn : 1; // Bits 9:9 + U32 TxDisable : 1; // Bits 10:10 + U32 RxDisable : 1; // Bits 11:11 + U32 TxLong : 1; // Bits 12:12 + U32 RxDqsCtle : 2; // Bits 14:13 + U32 RxReadPointer : 3; // Bits 17:15 + U32 DriverSegmentEnable : 1; // Bits 18:18 + U32 DataVccddqHi : 1; // Bits 19:19 + U32 ReadRFRd : 1; // Bits 20:20 + U32 ReadRFWr : 1; // Bits 21:21 + U32 ReadRFRank : 2; // Bits 23:22 + U32 ForceOdtOn : 1; // Bits 24:24 + U32 OdtSampOff : 1; // Bits 25:25 + U32 DisableOdtStatic : 1; // Bits 26:26 + U32 DdrCRForceODTOn : 1; // Bits 27:27 + U32 LPDDR_Mode : 1; // Bits 28:28 + U32 EnReadPreamble : 1; // Bits 29:29 + U32 OdtSampExtendEn : 1; // Bits 30:30 + U32 EarlyRleakEn : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA2CH0_CR_DDRCRDATACONTROL0_STRUCT; + +typedef union { + struct { + U32 CAVrefCtl : 7; // Bits 6:0 + U32 Ch1VrefCtl : 7; // Bits 13:7 + U32 Ch0VrefCtl : 7; // Bits 20:14 + U32 EnDimmVrefCA : 1; // Bits 21:21 + U32 EnDimmVrefCh1 : 1; // Bits 22:22 + U32 EnDimmVrefCh0 : 1; // Bits 23:23 + U32 HiZTimerCtrl : 2; // Bits 25:24 + U32 VccddqHiQnnnH : 1; // Bits 26:26 + U32 Rsvd : 2; // Bits 28:27 + U32 caSlowBW : 1; // Bits 29:29 + U32 ch0SlowBW : 1; // Bits 30:30 + U32 ch1SlowBW : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA2CH0_CR_DDRCRVREFADJUST1_STRUCT; + +typedef union { + struct { + U32 RxRcvEnPi : 9; // Bits 8:0 + U32 RxDqsPPi : 6; // Bits 14:9 + U32 RxEq : 5; // Bits 19:15 + U32 RxDqsNPi : 6; // Bits 25:20 + U32 RxVref : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA2CH1_CR_RXTRAINRANK0_STRUCT; + +typedef union { + struct { + U32 RxRcvEnPi : 9; // Bits 8:0 + U32 RxDqsPPi : 6; // Bits 14:9 + U32 RxEq : 5; // Bits 19:15 + U32 RxDqsNPi : 6; // Bits 25:20 + U32 RxVref : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA2CH1_CR_RXTRAINRANK1_STRUCT; + +typedef union { + struct { + U32 RxRcvEnPi : 9; // Bits 8:0 + U32 RxDqsPPi : 6; // Bits 14:9 + U32 RxEq : 5; // Bits 19:15 + U32 RxDqsNPi : 6; // Bits 25:20 + U32 RxVref : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA2CH1_CR_RXTRAINRANK2_STRUCT; + +typedef union { + struct { + U32 RxRcvEnPi : 9; // Bits 8:0 + U32 RxDqsPPi : 6; // Bits 14:9 + U32 RxEq : 5; // Bits 19:15 + U32 RxDqsNPi : 6; // Bits 25:20 + U32 RxVref : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA2CH1_CR_RXTRAINRANK3_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA2CH1_CR_RXPERBITRANK0_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA2CH1_CR_RXPERBITRANK1_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA2CH1_CR_RXPERBITRANK2_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA2CH1_CR_RXPERBITRANK3_STRUCT; + +typedef union { + struct { + U32 TxDqDelay : 9; // Bits 8:0 + U32 TxDqsDelay : 9; // Bits 17:9 + U32 Spare0 : 2; // Bits 19:18 + U32 TxEqualization : 6; // Bits 25:20 + U32 Spare1 : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA2CH1_CR_TXTRAINRANK0_STRUCT; + +typedef union { + struct { + U32 TxDqDelay : 9; // Bits 8:0 + U32 TxDqsDelay : 9; // Bits 17:9 + U32 Spare0 : 2; // Bits 19:18 + U32 TxEqualization : 6; // Bits 25:20 + U32 Spare1 : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA2CH1_CR_TXTRAINRANK1_STRUCT; + +typedef union { + struct { + U32 TxDqDelay : 9; // Bits 8:0 + U32 TxDqsDelay : 9; // Bits 17:9 + U32 Spare0 : 2; // Bits 19:18 + U32 TxEqualization : 6; // Bits 25:20 + U32 Spare1 : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA2CH1_CR_TXTRAINRANK2_STRUCT; + +typedef union { + struct { + U32 TxDqDelay : 9; // Bits 8:0 + U32 TxDqsDelay : 9; // Bits 17:9 + U32 Spare0 : 2; // Bits 19:18 + U32 TxEqualization : 6; // Bits 25:20 + U32 Spare1 : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA2CH1_CR_TXTRAINRANK3_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA2CH1_CR_TXPERBITRANK0_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA2CH1_CR_TXPERBITRANK1_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA2CH1_CR_TXPERBITRANK2_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA2CH1_CR_TXPERBITRANK3_STRUCT; + +typedef union { + struct { + U32 RcompDrvUp : 6; // Bits 5:0 + U32 Spare0 : 3; // Bits 8:6 + U32 RcompDrvDown : 6; // Bits 14:9 + U32 VTComp : 5; // Bits 19:15 + U32 TcoComp : 6; // Bits 25:20 + U32 SlewRateComp : 5; // Bits 30:26 + U32 Spare2 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA2CH1_CR_RCOMPDATA0_STRUCT; + +typedef union { + struct { + U32 RcompOdtUp : 6; // Bits 5:0 + U32 Spare0 : 3; // Bits 8:6 + U32 RcompOdtDown : 6; // Bits 14:9 + U32 Spare1 : 1; // Bits 15:15 + U32 PanicDrvDn : 6; // Bits 21:16 + U32 PanicDrvUp : 6; // Bits 27:22 + U32 LevelShifterComp : 3; // Bits 30:28 + U32 Spare2 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA2CH1_CR_RCOMPDATA1_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA2CH1_CR_TXXTALK_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA2CH1_CR_RXOFFSETVDQ_STRUCT; + +typedef union { + struct { + U32 Spare : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA2CH1_CR_DDRDATARESERVED_STRUCT; + +typedef union { + struct { + U32 DataTrainFeedback : 9; // Bits 8:0 + U32 Spare : 23; // Bits 31:9 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA2CH1_CR_DATATRAINFEEDBACK_STRUCT; + +typedef union { + struct { + U32 RunTest : 1; // Bits 0:0 + U32 Load : 1; // Bits 1:1 + U32 ModeHVM : 1; // Bits 2:2 + U32 ModeDV : 1; // Bits 3:3 + U32 ModeADC : 1; // Bits 4:4 + U32 LoadCount : 10; // Bits 14:5 + U32 CountStatus : 10; // Bits 24:15 + U32 Spare : 7; // Bits 31:25 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA2CH1_CR_DLLPITESTANDADC_STRUCT; + +typedef union { + struct { + U32 DqDrvUpCompOffset : 6; // Bits 5:0 + U32 DqDrvDownCompOffset : 6; // Bits 11:6 + U32 DqOdtUpCompOffset : 5; // Bits 16:12 + U32 DqOdtDownCompOffset : 5; // Bits 21:17 + U32 DqTcoCompOffset : 5; // Bits 26:22 + U32 DqSlewRateCompOffset : 5; // Bits 31:27 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_STRUCT; + +typedef union { + struct { + U32 RefPi : 4; // Bits 3:0 + U32 DllMask : 2; // Bits 5:4 + U32 DllWeakLock : 1; // Bits 6:6 + U32 SdllSegmentDisable : 3; // Bits 9:7 + U32 RxBiasCtl : 3; // Bits 12:10 + U32 OdtDelay : 4; // Bits 16:13 + U32 OdtDuration : 3; // Bits 19:17 + U32 SenseAmpDelay : 4; // Bits 23:20 + U32 SenseAmpDuration : 3; // Bits 26:24 + U32 BurstEndODTDelay : 3; // Bits 29:27 + U32 LpDdrLongOdtEn : 1; // Bits 30:30 + U32 Rsvd1 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA2CH1_CR_DDRCRDATACONTROL1_STRUCT; + +typedef union { + struct { + U32 RxStaggerCtl : 5; // Bits 4:0 + U32 ForceBiasOn : 1; // Bits 5:5 + U32 ForceRxOn : 1; // Bits 6:6 + U32 LeakerComp : 2; // Bits 8:7 + U32 RxDqsAmpOffset : 4; // Bits 12:9 + U32 RxClkStgNum : 5; // Bits 17:13 + U32 WlLongDelEn : 1; // Bits 18:18 + U32 Spare : 13; // Bits 31:19 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA2CH1_CR_DDRCRDATACONTROL2_STRUCT; + +typedef union { + struct { + U32 VssHiOrVrefCtl : 24; // Bits 23:0 + U32 OutputCode : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA2CH1_CR_DDRCRVSSHIORVREFCONTROL_STRUCT; + +typedef union { + struct { + U32 RcvEnOffset : 6; // Bits 5:0 + U32 RxDqsOffset : 6; // Bits 11:6 + U32 TxDqOffset : 6; // Bits 17:12 + U32 TxDqsOffset : 6; // Bits 23:18 + U32 VrefOffset : 7; // Bits 30:24 + U32 Spare : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA2CH1_CR_DDRCRDATAOFFSETTRAIN_STRUCT; + +typedef union { + struct { + U32 RxTrainingMode : 1; // Bits 0:0 + U32 WLTrainingMode : 1; // Bits 1:1 + U32 RLTrainingMode : 1; // Bits 2:2 + U32 SenseampTrainingMode : 1; // Bits 3:3 + U32 TxOn : 1; // Bits 4:4 + U32 RfOn : 1; // Bits 5:5 + U32 RxPiOn : 1; // Bits 6:6 + U32 TxPiOn : 1; // Bits 7:7 + U32 InternalClocksOn : 1; // Bits 8:8 + U32 RepeaterClocksOn : 1; // Bits 9:9 + U32 TxDisable : 1; // Bits 10:10 + U32 RxDisable : 1; // Bits 11:11 + U32 TxLong : 1; // Bits 12:12 + U32 RxDqsCtle : 2; // Bits 14:13 + U32 RxReadPointer : 3; // Bits 17:15 + U32 DriverSegmentEnable : 1; // Bits 18:18 + U32 DataVccddqHi : 1; // Bits 19:19 + U32 ReadRFRd : 1; // Bits 20:20 + U32 ReadRFWr : 1; // Bits 21:21 + U32 ReadRFRank : 2; // Bits 23:22 + U32 ForceOdtOn : 1; // Bits 24:24 + U32 OdtSampOff : 1; // Bits 25:25 + U32 DisableOdtStatic : 1; // Bits 26:26 + U32 DdrCRForceODTOn : 1; // Bits 27:27 + U32 LPDDR_Mode : 1; // Bits 28:28 + U32 EnReadPreamble : 1; // Bits 29:29 + U32 OdtSampExtendEn : 1; // Bits 30:30 + U32 EarlyRleakEn : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA2CH1_CR_DDRCRDATACONTROL0_STRUCT; + +typedef union { + struct { + U32 CAVrefCtl : 7; // Bits 6:0 + U32 Ch1VrefCtl : 7; // Bits 13:7 + U32 Ch0VrefCtl : 7; // Bits 20:14 + U32 EnDimmVrefCA : 1; // Bits 21:21 + U32 EnDimmVrefCh1 : 1; // Bits 22:22 + U32 EnDimmVrefCh0 : 1; // Bits 23:23 + U32 HiZTimerCtrl : 2; // Bits 25:24 + U32 VccddqHiQnnnH : 1; // Bits 26:26 + U32 Rsvd : 2; // Bits 28:27 + U32 caSlowBW : 1; // Bits 29:29 + U32 ch0SlowBW : 1; // Bits 30:30 + U32 ch1SlowBW : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA2CH1_CR_DDRCRVREFADJUST1_STRUCT; + +typedef union { + struct { + U32 RxRcvEnPi : 9; // Bits 8:0 + U32 RxDqsPPi : 6; // Bits 14:9 + U32 RxEq : 5; // Bits 19:15 + U32 RxDqsNPi : 6; // Bits 25:20 + U32 RxVref : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA3CH0_CR_RXTRAINRANK0_STRUCT; + +typedef union { + struct { + U32 RxRcvEnPi : 9; // Bits 8:0 + U32 RxDqsPPi : 6; // Bits 14:9 + U32 RxEq : 5; // Bits 19:15 + U32 RxDqsNPi : 6; // Bits 25:20 + U32 RxVref : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA3CH0_CR_RXTRAINRANK1_STRUCT; + +typedef union { + struct { + U32 RxRcvEnPi : 9; // Bits 8:0 + U32 RxDqsPPi : 6; // Bits 14:9 + U32 RxEq : 5; // Bits 19:15 + U32 RxDqsNPi : 6; // Bits 25:20 + U32 RxVref : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA3CH0_CR_RXTRAINRANK2_STRUCT; + +typedef union { + struct { + U32 RxRcvEnPi : 9; // Bits 8:0 + U32 RxDqsPPi : 6; // Bits 14:9 + U32 RxEq : 5; // Bits 19:15 + U32 RxDqsNPi : 6; // Bits 25:20 + U32 RxVref : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA3CH0_CR_RXTRAINRANK3_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA3CH0_CR_RXPERBITRANK0_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA3CH0_CR_RXPERBITRANK1_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA3CH0_CR_RXPERBITRANK2_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA3CH0_CR_RXPERBITRANK3_STRUCT; + +typedef union { + struct { + U32 TxDqDelay : 9; // Bits 8:0 + U32 TxDqsDelay : 9; // Bits 17:9 + U32 Spare0 : 2; // Bits 19:18 + U32 TxEqualization : 6; // Bits 25:20 + U32 Spare1 : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA3CH0_CR_TXTRAINRANK0_STRUCT; + +typedef union { + struct { + U32 TxDqDelay : 9; // Bits 8:0 + U32 TxDqsDelay : 9; // Bits 17:9 + U32 Spare0 : 2; // Bits 19:18 + U32 TxEqualization : 6; // Bits 25:20 + U32 Spare1 : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA3CH0_CR_TXTRAINRANK1_STRUCT; + +typedef union { + struct { + U32 TxDqDelay : 9; // Bits 8:0 + U32 TxDqsDelay : 9; // Bits 17:9 + U32 Spare0 : 2; // Bits 19:18 + U32 TxEqualization : 6; // Bits 25:20 + U32 Spare1 : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA3CH0_CR_TXTRAINRANK2_STRUCT; + +typedef union { + struct { + U32 TxDqDelay : 9; // Bits 8:0 + U32 TxDqsDelay : 9; // Bits 17:9 + U32 Spare0 : 2; // Bits 19:18 + U32 TxEqualization : 6; // Bits 25:20 + U32 Spare1 : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA3CH0_CR_TXTRAINRANK3_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA3CH0_CR_TXPERBITRANK0_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA3CH0_CR_TXPERBITRANK1_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA3CH0_CR_TXPERBITRANK2_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA3CH0_CR_TXPERBITRANK3_STRUCT; + +typedef union { + struct { + U32 RcompDrvUp : 6; // Bits 5:0 + U32 Spare0 : 3; // Bits 8:6 + U32 RcompDrvDown : 6; // Bits 14:9 + U32 VTComp : 5; // Bits 19:15 + U32 TcoComp : 6; // Bits 25:20 + U32 SlewRateComp : 5; // Bits 30:26 + U32 Spare2 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA3CH0_CR_RCOMPDATA0_STRUCT; + +typedef union { + struct { + U32 RcompOdtUp : 6; // Bits 5:0 + U32 Spare0 : 3; // Bits 8:6 + U32 RcompOdtDown : 6; // Bits 14:9 + U32 Spare1 : 1; // Bits 15:15 + U32 PanicDrvDn : 6; // Bits 21:16 + U32 PanicDrvUp : 6; // Bits 27:22 + U32 LevelShifterComp : 3; // Bits 30:28 + U32 Spare2 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA3CH0_CR_RCOMPDATA1_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA3CH0_CR_TXXTALK_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA3CH0_CR_RXOFFSETVDQ_STRUCT; + +typedef union { + struct { + U32 Spare : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA3CH0_CR_DDRDATARESERVED_STRUCT; + +typedef union { + struct { + U32 DataTrainFeedback : 9; // Bits 8:0 + U32 Spare : 23; // Bits 31:9 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA3CH0_CR_DATATRAINFEEDBACK_STRUCT; + +typedef union { + struct { + U32 RunTest : 1; // Bits 0:0 + U32 Load : 1; // Bits 1:1 + U32 ModeHVM : 1; // Bits 2:2 + U32 ModeDV : 1; // Bits 3:3 + U32 ModeADC : 1; // Bits 4:4 + U32 LoadCount : 10; // Bits 14:5 + U32 CountStatus : 10; // Bits 24:15 + U32 Spare : 7; // Bits 31:25 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA3CH0_CR_DLLPITESTANDADC_STRUCT; + +typedef union { + struct { + U32 DqDrvUpCompOffset : 6; // Bits 5:0 + U32 DqDrvDownCompOffset : 6; // Bits 11:6 + U32 DqOdtUpCompOffset : 5; // Bits 16:12 + U32 DqOdtDownCompOffset : 5; // Bits 21:17 + U32 DqTcoCompOffset : 5; // Bits 26:22 + U32 DqSlewRateCompOffset : 5; // Bits 31:27 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_STRUCT; + +typedef union { + struct { + U32 RefPi : 4; // Bits 3:0 + U32 DllMask : 2; // Bits 5:4 + U32 DllWeakLock : 1; // Bits 6:6 + U32 SdllSegmentDisable : 3; // Bits 9:7 + U32 RxBiasCtl : 3; // Bits 12:10 + U32 OdtDelay : 4; // Bits 16:13 + U32 OdtDuration : 3; // Bits 19:17 + U32 SenseAmpDelay : 4; // Bits 23:20 + U32 SenseAmpDuration : 3; // Bits 26:24 + U32 BurstEndODTDelay : 3; // Bits 29:27 + U32 LpDdrLongOdtEn : 1; // Bits 30:30 + U32 Rsvd1 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA3CH0_CR_DDRCRDATACONTROL1_STRUCT; + +typedef union { + struct { + U32 RxStaggerCtl : 5; // Bits 4:0 + U32 ForceBiasOn : 1; // Bits 5:5 + U32 ForceRxOn : 1; // Bits 6:6 + U32 LeakerComp : 2; // Bits 8:7 + U32 RxDqsAmpOffset : 4; // Bits 12:9 + U32 RxClkStgNum : 5; // Bits 17:13 + U32 WlLongDelEn : 1; // Bits 18:18 + U32 Spare : 13; // Bits 31:19 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA3CH0_CR_DDRCRDATACONTROL2_STRUCT; + +typedef union { + struct { + U32 VssHiOrVrefCtl : 24; // Bits 23:0 + U32 OutputCode : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA3CH0_CR_DDRCRVSSHIORVREFCONTROL_STRUCT; + +typedef union { + struct { + U32 RcvEnOffset : 6; // Bits 5:0 + U32 RxDqsOffset : 6; // Bits 11:6 + U32 TxDqOffset : 6; // Bits 17:12 + U32 TxDqsOffset : 6; // Bits 23:18 + U32 VrefOffset : 7; // Bits 30:24 + U32 Spare : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA3CH0_CR_DDRCRDATAOFFSETTRAIN_STRUCT; + +typedef union { + struct { + U32 RxTrainingMode : 1; // Bits 0:0 + U32 WLTrainingMode : 1; // Bits 1:1 + U32 RLTrainingMode : 1; // Bits 2:2 + U32 SenseampTrainingMode : 1; // Bits 3:3 + U32 TxOn : 1; // Bits 4:4 + U32 RfOn : 1; // Bits 5:5 + U32 RxPiOn : 1; // Bits 6:6 + U32 TxPiOn : 1; // Bits 7:7 + U32 InternalClocksOn : 1; // Bits 8:8 + U32 RepeaterClocksOn : 1; // Bits 9:9 + U32 TxDisable : 1; // Bits 10:10 + U32 RxDisable : 1; // Bits 11:11 + U32 TxLong : 1; // Bits 12:12 + U32 RxDqsCtle : 2; // Bits 14:13 + U32 RxReadPointer : 3; // Bits 17:15 + U32 DriverSegmentEnable : 1; // Bits 18:18 + U32 DataVccddqHi : 1; // Bits 19:19 + U32 ReadRFRd : 1; // Bits 20:20 + U32 ReadRFWr : 1; // Bits 21:21 + U32 ReadRFRank : 2; // Bits 23:22 + U32 ForceOdtOn : 1; // Bits 24:24 + U32 OdtSampOff : 1; // Bits 25:25 + U32 DisableOdtStatic : 1; // Bits 26:26 + U32 DdrCRForceODTOn : 1; // Bits 27:27 + U32 LPDDR_Mode : 1; // Bits 28:28 + U32 EnReadPreamble : 1; // Bits 29:29 + U32 OdtSampExtendEn : 1; // Bits 30:30 + U32 EarlyRleakEn : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA3CH0_CR_DDRCRDATACONTROL0_STRUCT; + +typedef union { + struct { + U32 CAVrefCtl : 7; // Bits 6:0 + U32 Ch1VrefCtl : 7; // Bits 13:7 + U32 Ch0VrefCtl : 7; // Bits 20:14 + U32 EnDimmVrefCA : 1; // Bits 21:21 + U32 EnDimmVrefCh1 : 1; // Bits 22:22 + U32 EnDimmVrefCh0 : 1; // Bits 23:23 + U32 HiZTimerCtrl : 2; // Bits 25:24 + U32 VccddqHiQnnnH : 1; // Bits 26:26 + U32 Rsvd : 2; // Bits 28:27 + U32 caSlowBW : 1; // Bits 29:29 + U32 ch0SlowBW : 1; // Bits 30:30 + U32 ch1SlowBW : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA3CH0_CR_DDRCRVREFADJUST1_STRUCT; + +typedef union { + struct { + U32 RxRcvEnPi : 9; // Bits 8:0 + U32 RxDqsPPi : 6; // Bits 14:9 + U32 RxEq : 5; // Bits 19:15 + U32 RxDqsNPi : 6; // Bits 25:20 + U32 RxVref : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA3CH1_CR_RXTRAINRANK0_STRUCT; + +typedef union { + struct { + U32 RxRcvEnPi : 9; // Bits 8:0 + U32 RxDqsPPi : 6; // Bits 14:9 + U32 RxEq : 5; // Bits 19:15 + U32 RxDqsNPi : 6; // Bits 25:20 + U32 RxVref : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA3CH1_CR_RXTRAINRANK1_STRUCT; + +typedef union { + struct { + U32 RxRcvEnPi : 9; // Bits 8:0 + U32 RxDqsPPi : 6; // Bits 14:9 + U32 RxEq : 5; // Bits 19:15 + U32 RxDqsNPi : 6; // Bits 25:20 + U32 RxVref : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA3CH1_CR_RXTRAINRANK2_STRUCT; + +typedef union { + struct { + U32 RxRcvEnPi : 9; // Bits 8:0 + U32 RxDqsPPi : 6; // Bits 14:9 + U32 RxEq : 5; // Bits 19:15 + U32 RxDqsNPi : 6; // Bits 25:20 + U32 RxVref : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA3CH1_CR_RXTRAINRANK3_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA3CH1_CR_RXPERBITRANK0_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA3CH1_CR_RXPERBITRANK1_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA3CH1_CR_RXPERBITRANK2_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA3CH1_CR_RXPERBITRANK3_STRUCT; + +typedef union { + struct { + U32 TxDqDelay : 9; // Bits 8:0 + U32 TxDqsDelay : 9; // Bits 17:9 + U32 Spare0 : 2; // Bits 19:18 + U32 TxEqualization : 6; // Bits 25:20 + U32 Spare1 : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA3CH1_CR_TXTRAINRANK0_STRUCT; + +typedef union { + struct { + U32 TxDqDelay : 9; // Bits 8:0 + U32 TxDqsDelay : 9; // Bits 17:9 + U32 Spare0 : 2; // Bits 19:18 + U32 TxEqualization : 6; // Bits 25:20 + U32 Spare1 : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA3CH1_CR_TXTRAINRANK1_STRUCT; + +typedef union { + struct { + U32 TxDqDelay : 9; // Bits 8:0 + U32 TxDqsDelay : 9; // Bits 17:9 + U32 Spare0 : 2; // Bits 19:18 + U32 TxEqualization : 6; // Bits 25:20 + U32 Spare1 : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA3CH1_CR_TXTRAINRANK2_STRUCT; + +typedef union { + struct { + U32 TxDqDelay : 9; // Bits 8:0 + U32 TxDqsDelay : 9; // Bits 17:9 + U32 Spare0 : 2; // Bits 19:18 + U32 TxEqualization : 6; // Bits 25:20 + U32 Spare1 : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA3CH1_CR_TXTRAINRANK3_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA3CH1_CR_TXPERBITRANK0_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA3CH1_CR_TXPERBITRANK1_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA3CH1_CR_TXPERBITRANK2_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA3CH1_CR_TXPERBITRANK3_STRUCT; + +typedef union { + struct { + U32 RcompDrvUp : 6; // Bits 5:0 + U32 Spare0 : 3; // Bits 8:6 + U32 RcompDrvDown : 6; // Bits 14:9 + U32 VTComp : 5; // Bits 19:15 + U32 TcoComp : 6; // Bits 25:20 + U32 SlewRateComp : 5; // Bits 30:26 + U32 Spare2 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA3CH1_CR_RCOMPDATA0_STRUCT; + +typedef union { + struct { + U32 RcompOdtUp : 6; // Bits 5:0 + U32 Spare0 : 3; // Bits 8:6 + U32 RcompOdtDown : 6; // Bits 14:9 + U32 Spare1 : 1; // Bits 15:15 + U32 PanicDrvDn : 6; // Bits 21:16 + U32 PanicDrvUp : 6; // Bits 27:22 + U32 LevelShifterComp : 3; // Bits 30:28 + U32 Spare2 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA3CH1_CR_RCOMPDATA1_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA3CH1_CR_TXXTALK_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA3CH1_CR_RXOFFSETVDQ_STRUCT; + +typedef union { + struct { + U32 Spare : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA3CH1_CR_DDRDATARESERVED_STRUCT; + +typedef union { + struct { + U32 DataTrainFeedback : 9; // Bits 8:0 + U32 Spare : 23; // Bits 31:9 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA3CH1_CR_DATATRAINFEEDBACK_STRUCT; + +typedef union { + struct { + U32 RunTest : 1; // Bits 0:0 + U32 Load : 1; // Bits 1:1 + U32 ModeHVM : 1; // Bits 2:2 + U32 ModeDV : 1; // Bits 3:3 + U32 ModeADC : 1; // Bits 4:4 + U32 LoadCount : 10; // Bits 14:5 + U32 CountStatus : 10; // Bits 24:15 + U32 Spare : 7; // Bits 31:25 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA3CH1_CR_DLLPITESTANDADC_STRUCT; + +typedef union { + struct { + U32 DqDrvUpCompOffset : 6; // Bits 5:0 + U32 DqDrvDownCompOffset : 6; // Bits 11:6 + U32 DqOdtUpCompOffset : 5; // Bits 16:12 + U32 DqOdtDownCompOffset : 5; // Bits 21:17 + U32 DqTcoCompOffset : 5; // Bits 26:22 + U32 DqSlewRateCompOffset : 5; // Bits 31:27 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_STRUCT; + +typedef union { + struct { + U32 RefPi : 4; // Bits 3:0 + U32 DllMask : 2; // Bits 5:4 + U32 DllWeakLock : 1; // Bits 6:6 + U32 SdllSegmentDisable : 3; // Bits 9:7 + U32 RxBiasCtl : 3; // Bits 12:10 + U32 OdtDelay : 4; // Bits 16:13 + U32 OdtDuration : 3; // Bits 19:17 + U32 SenseAmpDelay : 4; // Bits 23:20 + U32 SenseAmpDuration : 3; // Bits 26:24 + U32 BurstEndODTDelay : 3; // Bits 29:27 + U32 LpDdrLongOdtEn : 1; // Bits 30:30 + U32 Rsvd1 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA3CH1_CR_DDRCRDATACONTROL1_STRUCT; + +typedef union { + struct { + U32 RxStaggerCtl : 5; // Bits 4:0 + U32 ForceBiasOn : 1; // Bits 5:5 + U32 ForceRxOn : 1; // Bits 6:6 + U32 LeakerComp : 2; // Bits 8:7 + U32 RxDqsAmpOffset : 4; // Bits 12:9 + U32 RxClkStgNum : 5; // Bits 17:13 + U32 WlLongDelEn : 1; // Bits 18:18 + U32 Spare : 13; // Bits 31:19 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA3CH1_CR_DDRCRDATACONTROL2_STRUCT; + +typedef union { + struct { + U32 VssHiOrVrefCtl : 24; // Bits 23:0 + U32 OutputCode : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA3CH1_CR_DDRCRVSSHIORVREFCONTROL_STRUCT; + +typedef union { + struct { + U32 RcvEnOffset : 6; // Bits 5:0 + U32 RxDqsOffset : 6; // Bits 11:6 + U32 TxDqOffset : 6; // Bits 17:12 + U32 TxDqsOffset : 6; // Bits 23:18 + U32 VrefOffset : 7; // Bits 30:24 + U32 Spare : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA3CH1_CR_DDRCRDATAOFFSETTRAIN_STRUCT; + +typedef union { + struct { + U32 RxTrainingMode : 1; // Bits 0:0 + U32 WLTrainingMode : 1; // Bits 1:1 + U32 RLTrainingMode : 1; // Bits 2:2 + U32 SenseampTrainingMode : 1; // Bits 3:3 + U32 TxOn : 1; // Bits 4:4 + U32 RfOn : 1; // Bits 5:5 + U32 RxPiOn : 1; // Bits 6:6 + U32 TxPiOn : 1; // Bits 7:7 + U32 InternalClocksOn : 1; // Bits 8:8 + U32 RepeaterClocksOn : 1; // Bits 9:9 + U32 TxDisable : 1; // Bits 10:10 + U32 RxDisable : 1; // Bits 11:11 + U32 TxLong : 1; // Bits 12:12 + U32 RxDqsCtle : 2; // Bits 14:13 + U32 RxReadPointer : 3; // Bits 17:15 + U32 DriverSegmentEnable : 1; // Bits 18:18 + U32 DataVccddqHi : 1; // Bits 19:19 + U32 ReadRFRd : 1; // Bits 20:20 + U32 ReadRFWr : 1; // Bits 21:21 + U32 ReadRFRank : 2; // Bits 23:22 + U32 ForceOdtOn : 1; // Bits 24:24 + U32 OdtSampOff : 1; // Bits 25:25 + U32 DisableOdtStatic : 1; // Bits 26:26 + U32 DdrCRForceODTOn : 1; // Bits 27:27 + U32 LPDDR_Mode : 1; // Bits 28:28 + U32 EnReadPreamble : 1; // Bits 29:29 + U32 OdtSampExtendEn : 1; // Bits 30:30 + U32 EarlyRleakEn : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA3CH1_CR_DDRCRDATACONTROL0_STRUCT; + +typedef union { + struct { + U32 CAVrefCtl : 7; // Bits 6:0 + U32 Ch1VrefCtl : 7; // Bits 13:7 + U32 Ch0VrefCtl : 7; // Bits 20:14 + U32 EnDimmVrefCA : 1; // Bits 21:21 + U32 EnDimmVrefCh1 : 1; // Bits 22:22 + U32 EnDimmVrefCh0 : 1; // Bits 23:23 + U32 HiZTimerCtrl : 2; // Bits 25:24 + U32 VccddqHiQnnnH : 1; // Bits 26:26 + U32 Rsvd : 2; // Bits 28:27 + U32 caSlowBW : 1; // Bits 29:29 + U32 ch0SlowBW : 1; // Bits 30:30 + U32 ch1SlowBW : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA3CH1_CR_DDRCRVREFADJUST1_STRUCT; + +typedef union { + struct { + U32 RxRcvEnPi : 9; // Bits 8:0 + U32 RxDqsPPi : 6; // Bits 14:9 + U32 RxEq : 5; // Bits 19:15 + U32 RxDqsNPi : 6; // Bits 25:20 + U32 RxVref : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA4CH0_CR_RXTRAINRANK0_STRUCT; + +typedef union { + struct { + U32 RxRcvEnPi : 9; // Bits 8:0 + U32 RxDqsPPi : 6; // Bits 14:9 + U32 RxEq : 5; // Bits 19:15 + U32 RxDqsNPi : 6; // Bits 25:20 + U32 RxVref : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA4CH0_CR_RXTRAINRANK1_STRUCT; + +typedef union { + struct { + U32 RxRcvEnPi : 9; // Bits 8:0 + U32 RxDqsPPi : 6; // Bits 14:9 + U32 RxEq : 5; // Bits 19:15 + U32 RxDqsNPi : 6; // Bits 25:20 + U32 RxVref : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA4CH0_CR_RXTRAINRANK2_STRUCT; + +typedef union { + struct { + U32 RxRcvEnPi : 9; // Bits 8:0 + U32 RxDqsPPi : 6; // Bits 14:9 + U32 RxEq : 5; // Bits 19:15 + U32 RxDqsNPi : 6; // Bits 25:20 + U32 RxVref : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA4CH0_CR_RXTRAINRANK3_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA4CH0_CR_RXPERBITRANK0_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA4CH0_CR_RXPERBITRANK1_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA4CH0_CR_RXPERBITRANK2_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA4CH0_CR_RXPERBITRANK3_STRUCT; + +typedef union { + struct { + U32 TxDqDelay : 9; // Bits 8:0 + U32 TxDqsDelay : 9; // Bits 17:9 + U32 Spare0 : 2; // Bits 19:18 + U32 TxEqualization : 6; // Bits 25:20 + U32 Spare1 : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA4CH0_CR_TXTRAINRANK0_STRUCT; + +typedef union { + struct { + U32 TxDqDelay : 9; // Bits 8:0 + U32 TxDqsDelay : 9; // Bits 17:9 + U32 Spare0 : 2; // Bits 19:18 + U32 TxEqualization : 6; // Bits 25:20 + U32 Spare1 : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA4CH0_CR_TXTRAINRANK1_STRUCT; + +typedef union { + struct { + U32 TxDqDelay : 9; // Bits 8:0 + U32 TxDqsDelay : 9; // Bits 17:9 + U32 Spare0 : 2; // Bits 19:18 + U32 TxEqualization : 6; // Bits 25:20 + U32 Spare1 : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA4CH0_CR_TXTRAINRANK2_STRUCT; + +typedef union { + struct { + U32 TxDqDelay : 9; // Bits 8:0 + U32 TxDqsDelay : 9; // Bits 17:9 + U32 Spare0 : 2; // Bits 19:18 + U32 TxEqualization : 6; // Bits 25:20 + U32 Spare1 : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA4CH0_CR_TXTRAINRANK3_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA4CH0_CR_TXPERBITRANK0_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA4CH0_CR_TXPERBITRANK1_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA4CH0_CR_TXPERBITRANK2_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA4CH0_CR_TXPERBITRANK3_STRUCT; + +typedef union { + struct { + U32 RcompDrvUp : 6; // Bits 5:0 + U32 Spare0 : 3; // Bits 8:6 + U32 RcompDrvDown : 6; // Bits 14:9 + U32 VTComp : 5; // Bits 19:15 + U32 TcoComp : 6; // Bits 25:20 + U32 SlewRateComp : 5; // Bits 30:26 + U32 Spare2 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA4CH0_CR_RCOMPDATA0_STRUCT; + +typedef union { + struct { + U32 RcompOdtUp : 6; // Bits 5:0 + U32 Spare0 : 3; // Bits 8:6 + U32 RcompOdtDown : 6; // Bits 14:9 + U32 Spare1 : 1; // Bits 15:15 + U32 PanicDrvDn : 6; // Bits 21:16 + U32 PanicDrvUp : 6; // Bits 27:22 + U32 LevelShifterComp : 3; // Bits 30:28 + U32 Spare2 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA4CH0_CR_RCOMPDATA1_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA4CH0_CR_TXXTALK_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA4CH0_CR_RXOFFSETVDQ_STRUCT; + +typedef union { + struct { + U32 Spare : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA4CH0_CR_DDRDATARESERVED_STRUCT; + +typedef union { + struct { + U32 DataTrainFeedback : 9; // Bits 8:0 + U32 Spare : 23; // Bits 31:9 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA4CH0_CR_DATATRAINFEEDBACK_STRUCT; + +typedef union { + struct { + U32 RunTest : 1; // Bits 0:0 + U32 Load : 1; // Bits 1:1 + U32 ModeHVM : 1; // Bits 2:2 + U32 ModeDV : 1; // Bits 3:3 + U32 ModeADC : 1; // Bits 4:4 + U32 LoadCount : 10; // Bits 14:5 + U32 CountStatus : 10; // Bits 24:15 + U32 Spare : 7; // Bits 31:25 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA4CH0_CR_DLLPITESTANDADC_STRUCT; + +typedef union { + struct { + U32 DqDrvUpCompOffset : 6; // Bits 5:0 + U32 DqDrvDownCompOffset : 6; // Bits 11:6 + U32 DqOdtUpCompOffset : 5; // Bits 16:12 + U32 DqOdtDownCompOffset : 5; // Bits 21:17 + U32 DqTcoCompOffset : 5; // Bits 26:22 + U32 DqSlewRateCompOffset : 5; // Bits 31:27 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_STRUCT; + +typedef union { + struct { + U32 RefPi : 4; // Bits 3:0 + U32 DllMask : 2; // Bits 5:4 + U32 DllWeakLock : 1; // Bits 6:6 + U32 SdllSegmentDisable : 3; // Bits 9:7 + U32 RxBiasCtl : 3; // Bits 12:10 + U32 OdtDelay : 4; // Bits 16:13 + U32 OdtDuration : 3; // Bits 19:17 + U32 SenseAmpDelay : 4; // Bits 23:20 + U32 SenseAmpDuration : 3; // Bits 26:24 + U32 BurstEndODTDelay : 3; // Bits 29:27 + U32 LpDdrLongOdtEn : 1; // Bits 30:30 + U32 Rsvd1 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA4CH0_CR_DDRCRDATACONTROL1_STRUCT; + +typedef union { + struct { + U32 RxStaggerCtl : 5; // Bits 4:0 + U32 ForceBiasOn : 1; // Bits 5:5 + U32 ForceRxOn : 1; // Bits 6:6 + U32 LeakerComp : 2; // Bits 8:7 + U32 RxDqsAmpOffset : 4; // Bits 12:9 + U32 RxClkStgNum : 5; // Bits 17:13 + U32 WlLongDelEn : 1; // Bits 18:18 + U32 Spare : 13; // Bits 31:19 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA4CH0_CR_DDRCRDATACONTROL2_STRUCT; + +typedef union { + struct { + U32 VssHiOrVrefCtl : 24; // Bits 23:0 + U32 OutputCode : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA4CH0_CR_DDRCRVSSHIORVREFCONTROL_STRUCT; + +typedef union { + struct { + U32 RcvEnOffset : 6; // Bits 5:0 + U32 RxDqsOffset : 6; // Bits 11:6 + U32 TxDqOffset : 6; // Bits 17:12 + U32 TxDqsOffset : 6; // Bits 23:18 + U32 VrefOffset : 7; // Bits 30:24 + U32 Spare : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA4CH0_CR_DDRCRDATAOFFSETTRAIN_STRUCT; + +typedef union { + struct { + U32 RxTrainingMode : 1; // Bits 0:0 + U32 WLTrainingMode : 1; // Bits 1:1 + U32 RLTrainingMode : 1; // Bits 2:2 + U32 SenseampTrainingMode : 1; // Bits 3:3 + U32 TxOn : 1; // Bits 4:4 + U32 RfOn : 1; // Bits 5:5 + U32 RxPiOn : 1; // Bits 6:6 + U32 TxPiOn : 1; // Bits 7:7 + U32 InternalClocksOn : 1; // Bits 8:8 + U32 RepeaterClocksOn : 1; // Bits 9:9 + U32 TxDisable : 1; // Bits 10:10 + U32 RxDisable : 1; // Bits 11:11 + U32 TxLong : 1; // Bits 12:12 + U32 RxDqsCtle : 2; // Bits 14:13 + U32 RxReadPointer : 3; // Bits 17:15 + U32 DriverSegmentEnable : 1; // Bits 18:18 + U32 DataVccddqHi : 1; // Bits 19:19 + U32 ReadRFRd : 1; // Bits 20:20 + U32 ReadRFWr : 1; // Bits 21:21 + U32 ReadRFRank : 2; // Bits 23:22 + U32 ForceOdtOn : 1; // Bits 24:24 + U32 OdtSampOff : 1; // Bits 25:25 + U32 DisableOdtStatic : 1; // Bits 26:26 + U32 DdrCRForceODTOn : 1; // Bits 27:27 + U32 LPDDR_Mode : 1; // Bits 28:28 + U32 EnReadPreamble : 1; // Bits 29:29 + U32 OdtSampExtendEn : 1; // Bits 30:30 + U32 EarlyRleakEn : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA4CH0_CR_DDRCRDATACONTROL0_STRUCT; + +typedef union { + struct { + U32 CAVrefCtl : 7; // Bits 6:0 + U32 Ch1VrefCtl : 7; // Bits 13:7 + U32 Ch0VrefCtl : 7; // Bits 20:14 + U32 EnDimmVrefCA : 1; // Bits 21:21 + U32 EnDimmVrefCh1 : 1; // Bits 22:22 + U32 EnDimmVrefCh0 : 1; // Bits 23:23 + U32 HiZTimerCtrl : 2; // Bits 25:24 + U32 VccddqHiQnnnH : 1; // Bits 26:26 + U32 Rsvd : 2; // Bits 28:27 + U32 caSlowBW : 1; // Bits 29:29 + U32 ch0SlowBW : 1; // Bits 30:30 + U32 ch1SlowBW : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA4CH0_CR_DDRCRVREFADJUST1_STRUCT; + +typedef union { + struct { + U32 RxRcvEnPi : 9; // Bits 8:0 + U32 RxDqsPPi : 6; // Bits 14:9 + U32 RxEq : 5; // Bits 19:15 + U32 RxDqsNPi : 6; // Bits 25:20 + U32 RxVref : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA4CH1_CR_RXTRAINRANK0_STRUCT; + +typedef union { + struct { + U32 RxRcvEnPi : 9; // Bits 8:0 + U32 RxDqsPPi : 6; // Bits 14:9 + U32 RxEq : 5; // Bits 19:15 + U32 RxDqsNPi : 6; // Bits 25:20 + U32 RxVref : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA4CH1_CR_RXTRAINRANK1_STRUCT; + +typedef union { + struct { + U32 RxRcvEnPi : 9; // Bits 8:0 + U32 RxDqsPPi : 6; // Bits 14:9 + U32 RxEq : 5; // Bits 19:15 + U32 RxDqsNPi : 6; // Bits 25:20 + U32 RxVref : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA4CH1_CR_RXTRAINRANK2_STRUCT; + +typedef union { + struct { + U32 RxRcvEnPi : 9; // Bits 8:0 + U32 RxDqsPPi : 6; // Bits 14:9 + U32 RxEq : 5; // Bits 19:15 + U32 RxDqsNPi : 6; // Bits 25:20 + U32 RxVref : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA4CH1_CR_RXTRAINRANK3_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA4CH1_CR_RXPERBITRANK0_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA4CH1_CR_RXPERBITRANK1_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA4CH1_CR_RXPERBITRANK2_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA4CH1_CR_RXPERBITRANK3_STRUCT; + +typedef union { + struct { + U32 TxDqDelay : 9; // Bits 8:0 + U32 TxDqsDelay : 9; // Bits 17:9 + U32 Spare0 : 2; // Bits 19:18 + U32 TxEqualization : 6; // Bits 25:20 + U32 Spare1 : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA4CH1_CR_TXTRAINRANK0_STRUCT; + +typedef union { + struct { + U32 TxDqDelay : 9; // Bits 8:0 + U32 TxDqsDelay : 9; // Bits 17:9 + U32 Spare0 : 2; // Bits 19:18 + U32 TxEqualization : 6; // Bits 25:20 + U32 Spare1 : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA4CH1_CR_TXTRAINRANK1_STRUCT; + +typedef union { + struct { + U32 TxDqDelay : 9; // Bits 8:0 + U32 TxDqsDelay : 9; // Bits 17:9 + U32 Spare0 : 2; // Bits 19:18 + U32 TxEqualization : 6; // Bits 25:20 + U32 Spare1 : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA4CH1_CR_TXTRAINRANK2_STRUCT; + +typedef union { + struct { + U32 TxDqDelay : 9; // Bits 8:0 + U32 TxDqsDelay : 9; // Bits 17:9 + U32 Spare0 : 2; // Bits 19:18 + U32 TxEqualization : 6; // Bits 25:20 + U32 Spare1 : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA4CH1_CR_TXTRAINRANK3_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA4CH1_CR_TXPERBITRANK0_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA4CH1_CR_TXPERBITRANK1_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA4CH1_CR_TXPERBITRANK2_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA4CH1_CR_TXPERBITRANK3_STRUCT; + +typedef union { + struct { + U32 RcompDrvUp : 6; // Bits 5:0 + U32 Spare0 : 3; // Bits 8:6 + U32 RcompDrvDown : 6; // Bits 14:9 + U32 VTComp : 5; // Bits 19:15 + U32 TcoComp : 6; // Bits 25:20 + U32 SlewRateComp : 5; // Bits 30:26 + U32 Spare2 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA4CH1_CR_RCOMPDATA0_STRUCT; + +typedef union { + struct { + U32 RcompOdtUp : 6; // Bits 5:0 + U32 Spare0 : 3; // Bits 8:6 + U32 RcompOdtDown : 6; // Bits 14:9 + U32 Spare1 : 1; // Bits 15:15 + U32 PanicDrvDn : 6; // Bits 21:16 + U32 PanicDrvUp : 6; // Bits 27:22 + U32 LevelShifterComp : 3; // Bits 30:28 + U32 Spare2 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA4CH1_CR_RCOMPDATA1_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA4CH1_CR_TXXTALK_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA4CH1_CR_RXOFFSETVDQ_STRUCT; + +typedef union { + struct { + U32 Spare : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA4CH1_CR_DDRDATARESERVED_STRUCT; + +typedef union { + struct { + U32 DataTrainFeedback : 9; // Bits 8:0 + U32 Spare : 23; // Bits 31:9 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA4CH1_CR_DATATRAINFEEDBACK_STRUCT; + +typedef union { + struct { + U32 RunTest : 1; // Bits 0:0 + U32 Load : 1; // Bits 1:1 + U32 ModeHVM : 1; // Bits 2:2 + U32 ModeDV : 1; // Bits 3:3 + U32 ModeADC : 1; // Bits 4:4 + U32 LoadCount : 10; // Bits 14:5 + U32 CountStatus : 10; // Bits 24:15 + U32 Spare : 7; // Bits 31:25 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA4CH1_CR_DLLPITESTANDADC_STRUCT; + +typedef union { + struct { + U32 DqDrvUpCompOffset : 6; // Bits 5:0 + U32 DqDrvDownCompOffset : 6; // Bits 11:6 + U32 DqOdtUpCompOffset : 5; // Bits 16:12 + U32 DqOdtDownCompOffset : 5; // Bits 21:17 + U32 DqTcoCompOffset : 5; // Bits 26:22 + U32 DqSlewRateCompOffset : 5; // Bits 31:27 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_STRUCT; + +typedef union { + struct { + U32 RefPi : 4; // Bits 3:0 + U32 DllMask : 2; // Bits 5:4 + U32 DllWeakLock : 1; // Bits 6:6 + U32 SdllSegmentDisable : 3; // Bits 9:7 + U32 RxBiasCtl : 3; // Bits 12:10 + U32 OdtDelay : 4; // Bits 16:13 + U32 OdtDuration : 3; // Bits 19:17 + U32 SenseAmpDelay : 4; // Bits 23:20 + U32 SenseAmpDuration : 3; // Bits 26:24 + U32 BurstEndODTDelay : 3; // Bits 29:27 + U32 LpDdrLongOdtEn : 1; // Bits 30:30 + U32 Rsvd1 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA4CH1_CR_DDRCRDATACONTROL1_STRUCT; + +typedef union { + struct { + U32 RxStaggerCtl : 5; // Bits 4:0 + U32 ForceBiasOn : 1; // Bits 5:5 + U32 ForceRxOn : 1; // Bits 6:6 + U32 LeakerComp : 2; // Bits 8:7 + U32 RxDqsAmpOffset : 4; // Bits 12:9 + U32 RxClkStgNum : 5; // Bits 17:13 + U32 WlLongDelEn : 1; // Bits 18:18 + U32 Spare : 13; // Bits 31:19 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA4CH1_CR_DDRCRDATACONTROL2_STRUCT; + +typedef union { + struct { + U32 VssHiOrVrefCtl : 24; // Bits 23:0 + U32 OutputCode : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA4CH1_CR_DDRCRVSSHIORVREFCONTROL_STRUCT; + +typedef union { + struct { + U32 RcvEnOffset : 6; // Bits 5:0 + U32 RxDqsOffset : 6; // Bits 11:6 + U32 TxDqOffset : 6; // Bits 17:12 + U32 TxDqsOffset : 6; // Bits 23:18 + U32 VrefOffset : 7; // Bits 30:24 + U32 Spare : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA4CH1_CR_DDRCRDATAOFFSETTRAIN_STRUCT; + +typedef union { + struct { + U32 RxTrainingMode : 1; // Bits 0:0 + U32 WLTrainingMode : 1; // Bits 1:1 + U32 RLTrainingMode : 1; // Bits 2:2 + U32 SenseampTrainingMode : 1; // Bits 3:3 + U32 TxOn : 1; // Bits 4:4 + U32 RfOn : 1; // Bits 5:5 + U32 RxPiOn : 1; // Bits 6:6 + U32 TxPiOn : 1; // Bits 7:7 + U32 InternalClocksOn : 1; // Bits 8:8 + U32 RepeaterClocksOn : 1; // Bits 9:9 + U32 TxDisable : 1; // Bits 10:10 + U32 RxDisable : 1; // Bits 11:11 + U32 TxLong : 1; // Bits 12:12 + U32 RxDqsCtle : 2; // Bits 14:13 + U32 RxReadPointer : 3; // Bits 17:15 + U32 DriverSegmentEnable : 1; // Bits 18:18 + U32 DataVccddqHi : 1; // Bits 19:19 + U32 ReadRFRd : 1; // Bits 20:20 + U32 ReadRFWr : 1; // Bits 21:21 + U32 ReadRFRank : 2; // Bits 23:22 + U32 ForceOdtOn : 1; // Bits 24:24 + U32 OdtSampOff : 1; // Bits 25:25 + U32 DisableOdtStatic : 1; // Bits 26:26 + U32 DdrCRForceODTOn : 1; // Bits 27:27 + U32 LPDDR_Mode : 1; // Bits 28:28 + U32 EnReadPreamble : 1; // Bits 29:29 + U32 OdtSampExtendEn : 1; // Bits 30:30 + U32 EarlyRleakEn : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA4CH1_CR_DDRCRDATACONTROL0_STRUCT; + +typedef union { + struct { + U32 CAVrefCtl : 7; // Bits 6:0 + U32 Ch1VrefCtl : 7; // Bits 13:7 + U32 Ch0VrefCtl : 7; // Bits 20:14 + U32 EnDimmVrefCA : 1; // Bits 21:21 + U32 EnDimmVrefCh1 : 1; // Bits 22:22 + U32 EnDimmVrefCh0 : 1; // Bits 23:23 + U32 HiZTimerCtrl : 2; // Bits 25:24 + U32 VccddqHiQnnnH : 1; // Bits 26:26 + U32 Rsvd : 2; // Bits 28:27 + U32 caSlowBW : 1; // Bits 29:29 + U32 ch0SlowBW : 1; // Bits 30:30 + U32 ch1SlowBW : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA4CH1_CR_DDRCRVREFADJUST1_STRUCT; + +typedef union { + struct { + U32 RxRcvEnPi : 9; // Bits 8:0 + U32 RxDqsPPi : 6; // Bits 14:9 + U32 RxEq : 5; // Bits 19:15 + U32 RxDqsNPi : 6; // Bits 25:20 + U32 RxVref : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA5CH0_CR_RXTRAINRANK0_STRUCT; + +typedef union { + struct { + U32 RxRcvEnPi : 9; // Bits 8:0 + U32 RxDqsPPi : 6; // Bits 14:9 + U32 RxEq : 5; // Bits 19:15 + U32 RxDqsNPi : 6; // Bits 25:20 + U32 RxVref : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA5CH0_CR_RXTRAINRANK1_STRUCT; + +typedef union { + struct { + U32 RxRcvEnPi : 9; // Bits 8:0 + U32 RxDqsPPi : 6; // Bits 14:9 + U32 RxEq : 5; // Bits 19:15 + U32 RxDqsNPi : 6; // Bits 25:20 + U32 RxVref : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA5CH0_CR_RXTRAINRANK2_STRUCT; + +typedef union { + struct { + U32 RxRcvEnPi : 9; // Bits 8:0 + U32 RxDqsPPi : 6; // Bits 14:9 + U32 RxEq : 5; // Bits 19:15 + U32 RxDqsNPi : 6; // Bits 25:20 + U32 RxVref : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA5CH0_CR_RXTRAINRANK3_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA5CH0_CR_RXPERBITRANK0_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA5CH0_CR_RXPERBITRANK1_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA5CH0_CR_RXPERBITRANK2_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA5CH0_CR_RXPERBITRANK3_STRUCT; + +typedef union { + struct { + U32 TxDqDelay : 9; // Bits 8:0 + U32 TxDqsDelay : 9; // Bits 17:9 + U32 Spare0 : 2; // Bits 19:18 + U32 TxEqualization : 6; // Bits 25:20 + U32 Spare1 : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA5CH0_CR_TXTRAINRANK0_STRUCT; + +typedef union { + struct { + U32 TxDqDelay : 9; // Bits 8:0 + U32 TxDqsDelay : 9; // Bits 17:9 + U32 Spare0 : 2; // Bits 19:18 + U32 TxEqualization : 6; // Bits 25:20 + U32 Spare1 : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA5CH0_CR_TXTRAINRANK1_STRUCT; + +typedef union { + struct { + U32 TxDqDelay : 9; // Bits 8:0 + U32 TxDqsDelay : 9; // Bits 17:9 + U32 Spare0 : 2; // Bits 19:18 + U32 TxEqualization : 6; // Bits 25:20 + U32 Spare1 : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA5CH0_CR_TXTRAINRANK2_STRUCT; + +typedef union { + struct { + U32 TxDqDelay : 9; // Bits 8:0 + U32 TxDqsDelay : 9; // Bits 17:9 + U32 Spare0 : 2; // Bits 19:18 + U32 TxEqualization : 6; // Bits 25:20 + U32 Spare1 : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA5CH0_CR_TXTRAINRANK3_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA5CH0_CR_TXPERBITRANK0_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA5CH0_CR_TXPERBITRANK1_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA5CH0_CR_TXPERBITRANK2_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA5CH0_CR_TXPERBITRANK3_STRUCT; + +typedef union { + struct { + U32 RcompDrvUp : 6; // Bits 5:0 + U32 Spare0 : 3; // Bits 8:6 + U32 RcompDrvDown : 6; // Bits 14:9 + U32 VTComp : 5; // Bits 19:15 + U32 TcoComp : 6; // Bits 25:20 + U32 SlewRateComp : 5; // Bits 30:26 + U32 Spare2 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA5CH0_CR_RCOMPDATA0_STRUCT; + +typedef union { + struct { + U32 RcompOdtUp : 6; // Bits 5:0 + U32 Spare0 : 3; // Bits 8:6 + U32 RcompOdtDown : 6; // Bits 14:9 + U32 Spare1 : 1; // Bits 15:15 + U32 PanicDrvDn : 6; // Bits 21:16 + U32 PanicDrvUp : 6; // Bits 27:22 + U32 LevelShifterComp : 3; // Bits 30:28 + U32 Spare2 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA5CH0_CR_RCOMPDATA1_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA5CH0_CR_TXXTALK_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA5CH0_CR_RXOFFSETVDQ_STRUCT; + +typedef union { + struct { + U32 Spare : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA5CH0_CR_DDRDATARESERVED_STRUCT; + +typedef union { + struct { + U32 DataTrainFeedback : 9; // Bits 8:0 + U32 Spare : 23; // Bits 31:9 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA5CH0_CR_DATATRAINFEEDBACK_STRUCT; + +typedef union { + struct { + U32 RunTest : 1; // Bits 0:0 + U32 Load : 1; // Bits 1:1 + U32 ModeHVM : 1; // Bits 2:2 + U32 ModeDV : 1; // Bits 3:3 + U32 ModeADC : 1; // Bits 4:4 + U32 LoadCount : 10; // Bits 14:5 + U32 CountStatus : 10; // Bits 24:15 + U32 Spare : 7; // Bits 31:25 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA5CH0_CR_DLLPITESTANDADC_STRUCT; + +typedef union { + struct { + U32 DqDrvUpCompOffset : 6; // Bits 5:0 + U32 DqDrvDownCompOffset : 6; // Bits 11:6 + U32 DqOdtUpCompOffset : 5; // Bits 16:12 + U32 DqOdtDownCompOffset : 5; // Bits 21:17 + U32 DqTcoCompOffset : 5; // Bits 26:22 + U32 DqSlewRateCompOffset : 5; // Bits 31:27 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_STRUCT; + +typedef union { + struct { + U32 RefPi : 4; // Bits 3:0 + U32 DllMask : 2; // Bits 5:4 + U32 DllWeakLock : 1; // Bits 6:6 + U32 SdllSegmentDisable : 3; // Bits 9:7 + U32 RxBiasCtl : 3; // Bits 12:10 + U32 OdtDelay : 4; // Bits 16:13 + U32 OdtDuration : 3; // Bits 19:17 + U32 SenseAmpDelay : 4; // Bits 23:20 + U32 SenseAmpDuration : 3; // Bits 26:24 + U32 BurstEndODTDelay : 3; // Bits 29:27 + U32 LpDdrLongOdtEn : 1; // Bits 30:30 + U32 Rsvd1 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA5CH0_CR_DDRCRDATACONTROL1_STRUCT; + +typedef union { + struct { + U32 RxStaggerCtl : 5; // Bits 4:0 + U32 ForceBiasOn : 1; // Bits 5:5 + U32 ForceRxOn : 1; // Bits 6:6 + U32 LeakerComp : 2; // Bits 8:7 + U32 RxDqsAmpOffset : 4; // Bits 12:9 + U32 RxClkStgNum : 5; // Bits 17:13 + U32 WlLongDelEn : 1; // Bits 18:18 + U32 Spare : 13; // Bits 31:19 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA5CH0_CR_DDRCRDATACONTROL2_STRUCT; + +typedef union { + struct { + U32 VssHiOrVrefCtl : 24; // Bits 23:0 + U32 OutputCode : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA5CH0_CR_DDRCRVSSHIORVREFCONTROL_STRUCT; + +typedef union { + struct { + U32 RcvEnOffset : 6; // Bits 5:0 + U32 RxDqsOffset : 6; // Bits 11:6 + U32 TxDqOffset : 6; // Bits 17:12 + U32 TxDqsOffset : 6; // Bits 23:18 + U32 VrefOffset : 7; // Bits 30:24 + U32 Spare : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA5CH0_CR_DDRCRDATAOFFSETTRAIN_STRUCT; + +typedef union { + struct { + U32 RxTrainingMode : 1; // Bits 0:0 + U32 WLTrainingMode : 1; // Bits 1:1 + U32 RLTrainingMode : 1; // Bits 2:2 + U32 SenseampTrainingMode : 1; // Bits 3:3 + U32 TxOn : 1; // Bits 4:4 + U32 RfOn : 1; // Bits 5:5 + U32 RxPiOn : 1; // Bits 6:6 + U32 TxPiOn : 1; // Bits 7:7 + U32 InternalClocksOn : 1; // Bits 8:8 + U32 RepeaterClocksOn : 1; // Bits 9:9 + U32 TxDisable : 1; // Bits 10:10 + U32 RxDisable : 1; // Bits 11:11 + U32 TxLong : 1; // Bits 12:12 + U32 RxDqsCtle : 2; // Bits 14:13 + U32 RxReadPointer : 3; // Bits 17:15 + U32 DriverSegmentEnable : 1; // Bits 18:18 + U32 DataVccddqHi : 1; // Bits 19:19 + U32 ReadRFRd : 1; // Bits 20:20 + U32 ReadRFWr : 1; // Bits 21:21 + U32 ReadRFRank : 2; // Bits 23:22 + U32 ForceOdtOn : 1; // Bits 24:24 + U32 OdtSampOff : 1; // Bits 25:25 + U32 DisableOdtStatic : 1; // Bits 26:26 + U32 DdrCRForceODTOn : 1; // Bits 27:27 + U32 LPDDR_Mode : 1; // Bits 28:28 + U32 EnReadPreamble : 1; // Bits 29:29 + U32 OdtSampExtendEn : 1; // Bits 30:30 + U32 EarlyRleakEn : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA5CH0_CR_DDRCRDATACONTROL0_STRUCT; + +typedef union { + struct { + U32 CAVrefCtl : 7; // Bits 6:0 + U32 Ch1VrefCtl : 7; // Bits 13:7 + U32 Ch0VrefCtl : 7; // Bits 20:14 + U32 EnDimmVrefCA : 1; // Bits 21:21 + U32 EnDimmVrefCh1 : 1; // Bits 22:22 + U32 EnDimmVrefCh0 : 1; // Bits 23:23 + U32 HiZTimerCtrl : 2; // Bits 25:24 + U32 VccddqHiQnnnH : 1; // Bits 26:26 + U32 Rsvd : 2; // Bits 28:27 + U32 caSlowBW : 1; // Bits 29:29 + U32 ch0SlowBW : 1; // Bits 30:30 + U32 ch1SlowBW : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA5CH0_CR_DDRCRVREFADJUST1_STRUCT; + +typedef union { + struct { + U32 RxRcvEnPi : 9; // Bits 8:0 + U32 RxDqsPPi : 6; // Bits 14:9 + U32 RxEq : 5; // Bits 19:15 + U32 RxDqsNPi : 6; // Bits 25:20 + U32 RxVref : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA5CH1_CR_RXTRAINRANK0_STRUCT; + +typedef union { + struct { + U32 RxRcvEnPi : 9; // Bits 8:0 + U32 RxDqsPPi : 6; // Bits 14:9 + U32 RxEq : 5; // Bits 19:15 + U32 RxDqsNPi : 6; // Bits 25:20 + U32 RxVref : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA5CH1_CR_RXTRAINRANK1_STRUCT; + +typedef union { + struct { + U32 RxRcvEnPi : 9; // Bits 8:0 + U32 RxDqsPPi : 6; // Bits 14:9 + U32 RxEq : 5; // Bits 19:15 + U32 RxDqsNPi : 6; // Bits 25:20 + U32 RxVref : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA5CH1_CR_RXTRAINRANK2_STRUCT; + +typedef union { + struct { + U32 RxRcvEnPi : 9; // Bits 8:0 + U32 RxDqsPPi : 6; // Bits 14:9 + U32 RxEq : 5; // Bits 19:15 + U32 RxDqsNPi : 6; // Bits 25:20 + U32 RxVref : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA5CH1_CR_RXTRAINRANK3_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA5CH1_CR_RXPERBITRANK0_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA5CH1_CR_RXPERBITRANK1_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA5CH1_CR_RXPERBITRANK2_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA5CH1_CR_RXPERBITRANK3_STRUCT; + +typedef union { + struct { + U32 TxDqDelay : 9; // Bits 8:0 + U32 TxDqsDelay : 9; // Bits 17:9 + U32 Spare0 : 2; // Bits 19:18 + U32 TxEqualization : 6; // Bits 25:20 + U32 Spare1 : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA5CH1_CR_TXTRAINRANK0_STRUCT; + +typedef union { + struct { + U32 TxDqDelay : 9; // Bits 8:0 + U32 TxDqsDelay : 9; // Bits 17:9 + U32 Spare0 : 2; // Bits 19:18 + U32 TxEqualization : 6; // Bits 25:20 + U32 Spare1 : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA5CH1_CR_TXTRAINRANK1_STRUCT; + +typedef union { + struct { + U32 TxDqDelay : 9; // Bits 8:0 + U32 TxDqsDelay : 9; // Bits 17:9 + U32 Spare0 : 2; // Bits 19:18 + U32 TxEqualization : 6; // Bits 25:20 + U32 Spare1 : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA5CH1_CR_TXTRAINRANK2_STRUCT; + +typedef union { + struct { + U32 TxDqDelay : 9; // Bits 8:0 + U32 TxDqsDelay : 9; // Bits 17:9 + U32 Spare0 : 2; // Bits 19:18 + U32 TxEqualization : 6; // Bits 25:20 + U32 Spare1 : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA5CH1_CR_TXTRAINRANK3_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA5CH1_CR_TXPERBITRANK0_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA5CH1_CR_TXPERBITRANK1_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA5CH1_CR_TXPERBITRANK2_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA5CH1_CR_TXPERBITRANK3_STRUCT; + +typedef union { + struct { + U32 RcompDrvUp : 6; // Bits 5:0 + U32 Spare0 : 3; // Bits 8:6 + U32 RcompDrvDown : 6; // Bits 14:9 + U32 VTComp : 5; // Bits 19:15 + U32 TcoComp : 6; // Bits 25:20 + U32 SlewRateComp : 5; // Bits 30:26 + U32 Spare2 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA5CH1_CR_RCOMPDATA0_STRUCT; + +typedef union { + struct { + U32 RcompOdtUp : 6; // Bits 5:0 + U32 Spare0 : 3; // Bits 8:6 + U32 RcompOdtDown : 6; // Bits 14:9 + U32 Spare1 : 1; // Bits 15:15 + U32 PanicDrvDn : 6; // Bits 21:16 + U32 PanicDrvUp : 6; // Bits 27:22 + U32 LevelShifterComp : 3; // Bits 30:28 + U32 Spare2 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA5CH1_CR_RCOMPDATA1_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA5CH1_CR_TXXTALK_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA5CH1_CR_RXOFFSETVDQ_STRUCT; + +typedef union { + struct { + U32 Spare : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA5CH1_CR_DDRDATARESERVED_STRUCT; + +typedef union { + struct { + U32 DataTrainFeedback : 9; // Bits 8:0 + U32 Spare : 23; // Bits 31:9 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA5CH1_CR_DATATRAINFEEDBACK_STRUCT; + +typedef union { + struct { + U32 RunTest : 1; // Bits 0:0 + U32 Load : 1; // Bits 1:1 + U32 ModeHVM : 1; // Bits 2:2 + U32 ModeDV : 1; // Bits 3:3 + U32 ModeADC : 1; // Bits 4:4 + U32 LoadCount : 10; // Bits 14:5 + U32 CountStatus : 10; // Bits 24:15 + U32 Spare : 7; // Bits 31:25 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA5CH1_CR_DLLPITESTANDADC_STRUCT; + +typedef union { + struct { + U32 DqDrvUpCompOffset : 6; // Bits 5:0 + U32 DqDrvDownCompOffset : 6; // Bits 11:6 + U32 DqOdtUpCompOffset : 5; // Bits 16:12 + U32 DqOdtDownCompOffset : 5; // Bits 21:17 + U32 DqTcoCompOffset : 5; // Bits 26:22 + U32 DqSlewRateCompOffset : 5; // Bits 31:27 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_STRUCT; + +typedef union { + struct { + U32 RefPi : 4; // Bits 3:0 + U32 DllMask : 2; // Bits 5:4 + U32 DllWeakLock : 1; // Bits 6:6 + U32 SdllSegmentDisable : 3; // Bits 9:7 + U32 RxBiasCtl : 3; // Bits 12:10 + U32 OdtDelay : 4; // Bits 16:13 + U32 OdtDuration : 3; // Bits 19:17 + U32 SenseAmpDelay : 4; // Bits 23:20 + U32 SenseAmpDuration : 3; // Bits 26:24 + U32 BurstEndODTDelay : 3; // Bits 29:27 + U32 LpDdrLongOdtEn : 1; // Bits 30:30 + U32 Rsvd1 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA5CH1_CR_DDRCRDATACONTROL1_STRUCT; + +typedef union { + struct { + U32 RxStaggerCtl : 5; // Bits 4:0 + U32 ForceBiasOn : 1; // Bits 5:5 + U32 ForceRxOn : 1; // Bits 6:6 + U32 LeakerComp : 2; // Bits 8:7 + U32 RxDqsAmpOffset : 4; // Bits 12:9 + U32 RxClkStgNum : 5; // Bits 17:13 + U32 WlLongDelEn : 1; // Bits 18:18 + U32 Spare : 13; // Bits 31:19 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA5CH1_CR_DDRCRDATACONTROL2_STRUCT; + +typedef union { + struct { + U32 VssHiOrVrefCtl : 24; // Bits 23:0 + U32 OutputCode : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA5CH1_CR_DDRCRVSSHIORVREFCONTROL_STRUCT; + +typedef union { + struct { + U32 RcvEnOffset : 6; // Bits 5:0 + U32 RxDqsOffset : 6; // Bits 11:6 + U32 TxDqOffset : 6; // Bits 17:12 + U32 TxDqsOffset : 6; // Bits 23:18 + U32 VrefOffset : 7; // Bits 30:24 + U32 Spare : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA5CH1_CR_DDRCRDATAOFFSETTRAIN_STRUCT; + +typedef union { + struct { + U32 RxTrainingMode : 1; // Bits 0:0 + U32 WLTrainingMode : 1; // Bits 1:1 + U32 RLTrainingMode : 1; // Bits 2:2 + U32 SenseampTrainingMode : 1; // Bits 3:3 + U32 TxOn : 1; // Bits 4:4 + U32 RfOn : 1; // Bits 5:5 + U32 RxPiOn : 1; // Bits 6:6 + U32 TxPiOn : 1; // Bits 7:7 + U32 InternalClocksOn : 1; // Bits 8:8 + U32 RepeaterClocksOn : 1; // Bits 9:9 + U32 TxDisable : 1; // Bits 10:10 + U32 RxDisable : 1; // Bits 11:11 + U32 TxLong : 1; // Bits 12:12 + U32 RxDqsCtle : 2; // Bits 14:13 + U32 RxReadPointer : 3; // Bits 17:15 + U32 DriverSegmentEnable : 1; // Bits 18:18 + U32 DataVccddqHi : 1; // Bits 19:19 + U32 ReadRFRd : 1; // Bits 20:20 + U32 ReadRFWr : 1; // Bits 21:21 + U32 ReadRFRank : 2; // Bits 23:22 + U32 ForceOdtOn : 1; // Bits 24:24 + U32 OdtSampOff : 1; // Bits 25:25 + U32 DisableOdtStatic : 1; // Bits 26:26 + U32 DdrCRForceODTOn : 1; // Bits 27:27 + U32 LPDDR_Mode : 1; // Bits 28:28 + U32 EnReadPreamble : 1; // Bits 29:29 + U32 OdtSampExtendEn : 1; // Bits 30:30 + U32 EarlyRleakEn : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA5CH1_CR_DDRCRDATACONTROL0_STRUCT; + +typedef union { + struct { + U32 CAVrefCtl : 7; // Bits 6:0 + U32 Ch1VrefCtl : 7; // Bits 13:7 + U32 Ch0VrefCtl : 7; // Bits 20:14 + U32 EnDimmVrefCA : 1; // Bits 21:21 + U32 EnDimmVrefCh1 : 1; // Bits 22:22 + U32 EnDimmVrefCh0 : 1; // Bits 23:23 + U32 HiZTimerCtrl : 2; // Bits 25:24 + U32 VccddqHiQnnnH : 1; // Bits 26:26 + U32 Rsvd : 2; // Bits 28:27 + U32 caSlowBW : 1; // Bits 29:29 + U32 ch0SlowBW : 1; // Bits 30:30 + U32 ch1SlowBW : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA5CH1_CR_DDRCRVREFADJUST1_STRUCT; + +typedef union { + struct { + U32 RxRcvEnPi : 9; // Bits 8:0 + U32 RxDqsPPi : 6; // Bits 14:9 + U32 RxEq : 5; // Bits 19:15 + U32 RxDqsNPi : 6; // Bits 25:20 + U32 RxVref : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA6CH0_CR_RXTRAINRANK0_STRUCT; + +typedef union { + struct { + U32 RxRcvEnPi : 9; // Bits 8:0 + U32 RxDqsPPi : 6; // Bits 14:9 + U32 RxEq : 5; // Bits 19:15 + U32 RxDqsNPi : 6; // Bits 25:20 + U32 RxVref : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA6CH0_CR_RXTRAINRANK1_STRUCT; + +typedef union { + struct { + U32 RxRcvEnPi : 9; // Bits 8:0 + U32 RxDqsPPi : 6; // Bits 14:9 + U32 RxEq : 5; // Bits 19:15 + U32 RxDqsNPi : 6; // Bits 25:20 + U32 RxVref : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA6CH0_CR_RXTRAINRANK2_STRUCT; + +typedef union { + struct { + U32 RxRcvEnPi : 9; // Bits 8:0 + U32 RxDqsPPi : 6; // Bits 14:9 + U32 RxEq : 5; // Bits 19:15 + U32 RxDqsNPi : 6; // Bits 25:20 + U32 RxVref : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA6CH0_CR_RXTRAINRANK3_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA6CH0_CR_RXPERBITRANK0_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA6CH0_CR_RXPERBITRANK1_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA6CH0_CR_RXPERBITRANK2_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA6CH0_CR_RXPERBITRANK3_STRUCT; + +typedef union { + struct { + U32 TxDqDelay : 9; // Bits 8:0 + U32 TxDqsDelay : 9; // Bits 17:9 + U32 Spare0 : 2; // Bits 19:18 + U32 TxEqualization : 6; // Bits 25:20 + U32 Spare1 : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA6CH0_CR_TXTRAINRANK0_STRUCT; + +typedef union { + struct { + U32 TxDqDelay : 9; // Bits 8:0 + U32 TxDqsDelay : 9; // Bits 17:9 + U32 Spare0 : 2; // Bits 19:18 + U32 TxEqualization : 6; // Bits 25:20 + U32 Spare1 : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA6CH0_CR_TXTRAINRANK1_STRUCT; + +typedef union { + struct { + U32 TxDqDelay : 9; // Bits 8:0 + U32 TxDqsDelay : 9; // Bits 17:9 + U32 Spare0 : 2; // Bits 19:18 + U32 TxEqualization : 6; // Bits 25:20 + U32 Spare1 : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA6CH0_CR_TXTRAINRANK2_STRUCT; + +typedef union { + struct { + U32 TxDqDelay : 9; // Bits 8:0 + U32 TxDqsDelay : 9; // Bits 17:9 + U32 Spare0 : 2; // Bits 19:18 + U32 TxEqualization : 6; // Bits 25:20 + U32 Spare1 : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA6CH0_CR_TXTRAINRANK3_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA6CH0_CR_TXPERBITRANK0_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA6CH0_CR_TXPERBITRANK1_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA6CH0_CR_TXPERBITRANK2_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA6CH0_CR_TXPERBITRANK3_STRUCT; + +typedef union { + struct { + U32 RcompDrvUp : 6; // Bits 5:0 + U32 Spare0 : 3; // Bits 8:6 + U32 RcompDrvDown : 6; // Bits 14:9 + U32 VTComp : 5; // Bits 19:15 + U32 TcoComp : 6; // Bits 25:20 + U32 SlewRateComp : 5; // Bits 30:26 + U32 Spare2 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA6CH0_CR_RCOMPDATA0_STRUCT; + +typedef union { + struct { + U32 RcompOdtUp : 6; // Bits 5:0 + U32 Spare0 : 3; // Bits 8:6 + U32 RcompOdtDown : 6; // Bits 14:9 + U32 Spare1 : 1; // Bits 15:15 + U32 PanicDrvDn : 6; // Bits 21:16 + U32 PanicDrvUp : 6; // Bits 27:22 + U32 LevelShifterComp : 3; // Bits 30:28 + U32 Spare2 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA6CH0_CR_RCOMPDATA1_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA6CH0_CR_TXXTALK_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA6CH0_CR_RXOFFSETVDQ_STRUCT; + +typedef union { + struct { + U32 Spare : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA6CH0_CR_DDRDATARESERVED_STRUCT; + +typedef union { + struct { + U32 DataTrainFeedback : 9; // Bits 8:0 + U32 Spare : 23; // Bits 31:9 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA6CH0_CR_DATATRAINFEEDBACK_STRUCT; + +typedef union { + struct { + U32 RunTest : 1; // Bits 0:0 + U32 Load : 1; // Bits 1:1 + U32 ModeHVM : 1; // Bits 2:2 + U32 ModeDV : 1; // Bits 3:3 + U32 ModeADC : 1; // Bits 4:4 + U32 LoadCount : 10; // Bits 14:5 + U32 CountStatus : 10; // Bits 24:15 + U32 Spare : 7; // Bits 31:25 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA6CH0_CR_DLLPITESTANDADC_STRUCT; + +typedef union { + struct { + U32 DqDrvUpCompOffset : 6; // Bits 5:0 + U32 DqDrvDownCompOffset : 6; // Bits 11:6 + U32 DqOdtUpCompOffset : 5; // Bits 16:12 + U32 DqOdtDownCompOffset : 5; // Bits 21:17 + U32 DqTcoCompOffset : 5; // Bits 26:22 + U32 DqSlewRateCompOffset : 5; // Bits 31:27 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_STRUCT; + +typedef union { + struct { + U32 RefPi : 4; // Bits 3:0 + U32 DllMask : 2; // Bits 5:4 + U32 DllWeakLock : 1; // Bits 6:6 + U32 SdllSegmentDisable : 3; // Bits 9:7 + U32 RxBiasCtl : 3; // Bits 12:10 + U32 OdtDelay : 4; // Bits 16:13 + U32 OdtDuration : 3; // Bits 19:17 + U32 SenseAmpDelay : 4; // Bits 23:20 + U32 SenseAmpDuration : 3; // Bits 26:24 + U32 BurstEndODTDelay : 3; // Bits 29:27 + U32 LpDdrLongOdtEn : 1; // Bits 30:30 + U32 Rsvd1 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA6CH0_CR_DDRCRDATACONTROL1_STRUCT; + +typedef union { + struct { + U32 RxStaggerCtl : 5; // Bits 4:0 + U32 ForceBiasOn : 1; // Bits 5:5 + U32 ForceRxOn : 1; // Bits 6:6 + U32 LeakerComp : 2; // Bits 8:7 + U32 RxDqsAmpOffset : 4; // Bits 12:9 + U32 RxClkStgNum : 5; // Bits 17:13 + U32 WlLongDelEn : 1; // Bits 18:18 + U32 Spare : 13; // Bits 31:19 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA6CH0_CR_DDRCRDATACONTROL2_STRUCT; + +typedef union { + struct { + U32 VssHiOrVrefCtl : 24; // Bits 23:0 + U32 OutputCode : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA6CH0_CR_DDRCRVSSHIORVREFCONTROL_STRUCT; + +typedef union { + struct { + U32 RcvEnOffset : 6; // Bits 5:0 + U32 RxDqsOffset : 6; // Bits 11:6 + U32 TxDqOffset : 6; // Bits 17:12 + U32 TxDqsOffset : 6; // Bits 23:18 + U32 VrefOffset : 7; // Bits 30:24 + U32 Spare : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA6CH0_CR_DDRCRDATAOFFSETTRAIN_STRUCT; + +typedef union { + struct { + U32 RxTrainingMode : 1; // Bits 0:0 + U32 WLTrainingMode : 1; // Bits 1:1 + U32 RLTrainingMode : 1; // Bits 2:2 + U32 SenseampTrainingMode : 1; // Bits 3:3 + U32 TxOn : 1; // Bits 4:4 + U32 RfOn : 1; // Bits 5:5 + U32 RxPiOn : 1; // Bits 6:6 + U32 TxPiOn : 1; // Bits 7:7 + U32 InternalClocksOn : 1; // Bits 8:8 + U32 RepeaterClocksOn : 1; // Bits 9:9 + U32 TxDisable : 1; // Bits 10:10 + U32 RxDisable : 1; // Bits 11:11 + U32 TxLong : 1; // Bits 12:12 + U32 RxDqsCtle : 2; // Bits 14:13 + U32 RxReadPointer : 3; // Bits 17:15 + U32 DriverSegmentEnable : 1; // Bits 18:18 + U32 DataVccddqHi : 1; // Bits 19:19 + U32 ReadRFRd : 1; // Bits 20:20 + U32 ReadRFWr : 1; // Bits 21:21 + U32 ReadRFRank : 2; // Bits 23:22 + U32 ForceOdtOn : 1; // Bits 24:24 + U32 OdtSampOff : 1; // Bits 25:25 + U32 DisableOdtStatic : 1; // Bits 26:26 + U32 DdrCRForceODTOn : 1; // Bits 27:27 + U32 LPDDR_Mode : 1; // Bits 28:28 + U32 EnReadPreamble : 1; // Bits 29:29 + U32 OdtSampExtendEn : 1; // Bits 30:30 + U32 EarlyRleakEn : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA6CH0_CR_DDRCRDATACONTROL0_STRUCT; + +typedef union { + struct { + U32 CAVrefCtl : 7; // Bits 6:0 + U32 Ch1VrefCtl : 7; // Bits 13:7 + U32 Ch0VrefCtl : 7; // Bits 20:14 + U32 EnDimmVrefCA : 1; // Bits 21:21 + U32 EnDimmVrefCh1 : 1; // Bits 22:22 + U32 EnDimmVrefCh0 : 1; // Bits 23:23 + U32 HiZTimerCtrl : 2; // Bits 25:24 + U32 VccddqHiQnnnH : 1; // Bits 26:26 + U32 Rsvd : 2; // Bits 28:27 + U32 caSlowBW : 1; // Bits 29:29 + U32 ch0SlowBW : 1; // Bits 30:30 + U32 ch1SlowBW : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA6CH0_CR_DDRCRVREFADJUST1_STRUCT; + +typedef union { + struct { + U32 RxRcvEnPi : 9; // Bits 8:0 + U32 RxDqsPPi : 6; // Bits 14:9 + U32 RxEq : 5; // Bits 19:15 + U32 RxDqsNPi : 6; // Bits 25:20 + U32 RxVref : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA6CH1_CR_RXTRAINRANK0_STRUCT; + +typedef union { + struct { + U32 RxRcvEnPi : 9; // Bits 8:0 + U32 RxDqsPPi : 6; // Bits 14:9 + U32 RxEq : 5; // Bits 19:15 + U32 RxDqsNPi : 6; // Bits 25:20 + U32 RxVref : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA6CH1_CR_RXTRAINRANK1_STRUCT; + +typedef union { + struct { + U32 RxRcvEnPi : 9; // Bits 8:0 + U32 RxDqsPPi : 6; // Bits 14:9 + U32 RxEq : 5; // Bits 19:15 + U32 RxDqsNPi : 6; // Bits 25:20 + U32 RxVref : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA6CH1_CR_RXTRAINRANK2_STRUCT; + +typedef union { + struct { + U32 RxRcvEnPi : 9; // Bits 8:0 + U32 RxDqsPPi : 6; // Bits 14:9 + U32 RxEq : 5; // Bits 19:15 + U32 RxDqsNPi : 6; // Bits 25:20 + U32 RxVref : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA6CH1_CR_RXTRAINRANK3_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA6CH1_CR_RXPERBITRANK0_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA6CH1_CR_RXPERBITRANK1_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA6CH1_CR_RXPERBITRANK2_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA6CH1_CR_RXPERBITRANK3_STRUCT; + +typedef union { + struct { + U32 TxDqDelay : 9; // Bits 8:0 + U32 TxDqsDelay : 9; // Bits 17:9 + U32 Spare0 : 2; // Bits 19:18 + U32 TxEqualization : 6; // Bits 25:20 + U32 Spare1 : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA6CH1_CR_TXTRAINRANK0_STRUCT; + +typedef union { + struct { + U32 TxDqDelay : 9; // Bits 8:0 + U32 TxDqsDelay : 9; // Bits 17:9 + U32 Spare0 : 2; // Bits 19:18 + U32 TxEqualization : 6; // Bits 25:20 + U32 Spare1 : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA6CH1_CR_TXTRAINRANK1_STRUCT; + +typedef union { + struct { + U32 TxDqDelay : 9; // Bits 8:0 + U32 TxDqsDelay : 9; // Bits 17:9 + U32 Spare0 : 2; // Bits 19:18 + U32 TxEqualization : 6; // Bits 25:20 + U32 Spare1 : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA6CH1_CR_TXTRAINRANK2_STRUCT; + +typedef union { + struct { + U32 TxDqDelay : 9; // Bits 8:0 + U32 TxDqsDelay : 9; // Bits 17:9 + U32 Spare0 : 2; // Bits 19:18 + U32 TxEqualization : 6; // Bits 25:20 + U32 Spare1 : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA6CH1_CR_TXTRAINRANK3_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA6CH1_CR_TXPERBITRANK0_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA6CH1_CR_TXPERBITRANK1_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA6CH1_CR_TXPERBITRANK2_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA6CH1_CR_TXPERBITRANK3_STRUCT; + +typedef union { + struct { + U32 RcompDrvUp : 6; // Bits 5:0 + U32 Spare0 : 3; // Bits 8:6 + U32 RcompDrvDown : 6; // Bits 14:9 + U32 VTComp : 5; // Bits 19:15 + U32 TcoComp : 6; // Bits 25:20 + U32 SlewRateComp : 5; // Bits 30:26 + U32 Spare2 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA6CH1_CR_RCOMPDATA0_STRUCT; + +typedef union { + struct { + U32 RcompOdtUp : 6; // Bits 5:0 + U32 Spare0 : 3; // Bits 8:6 + U32 RcompOdtDown : 6; // Bits 14:9 + U32 Spare1 : 1; // Bits 15:15 + U32 PanicDrvDn : 6; // Bits 21:16 + U32 PanicDrvUp : 6; // Bits 27:22 + U32 LevelShifterComp : 3; // Bits 30:28 + U32 Spare2 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA6CH1_CR_RCOMPDATA1_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA6CH1_CR_TXXTALK_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA6CH1_CR_RXOFFSETVDQ_STRUCT; + +typedef union { + struct { + U32 Spare : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA6CH1_CR_DDRDATARESERVED_STRUCT; + +typedef union { + struct { + U32 DataTrainFeedback : 9; // Bits 8:0 + U32 Spare : 23; // Bits 31:9 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA6CH1_CR_DATATRAINFEEDBACK_STRUCT; + +typedef union { + struct { + U32 RunTest : 1; // Bits 0:0 + U32 Load : 1; // Bits 1:1 + U32 ModeHVM : 1; // Bits 2:2 + U32 ModeDV : 1; // Bits 3:3 + U32 ModeADC : 1; // Bits 4:4 + U32 LoadCount : 10; // Bits 14:5 + U32 CountStatus : 10; // Bits 24:15 + U32 Spare : 7; // Bits 31:25 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA6CH1_CR_DLLPITESTANDADC_STRUCT; + +typedef union { + struct { + U32 DqDrvUpCompOffset : 6; // Bits 5:0 + U32 DqDrvDownCompOffset : 6; // Bits 11:6 + U32 DqOdtUpCompOffset : 5; // Bits 16:12 + U32 DqOdtDownCompOffset : 5; // Bits 21:17 + U32 DqTcoCompOffset : 5; // Bits 26:22 + U32 DqSlewRateCompOffset : 5; // Bits 31:27 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_STRUCT; + +typedef union { + struct { + U32 RefPi : 4; // Bits 3:0 + U32 DllMask : 2; // Bits 5:4 + U32 DllWeakLock : 1; // Bits 6:6 + U32 SdllSegmentDisable : 3; // Bits 9:7 + U32 RxBiasCtl : 3; // Bits 12:10 + U32 OdtDelay : 4; // Bits 16:13 + U32 OdtDuration : 3; // Bits 19:17 + U32 SenseAmpDelay : 4; // Bits 23:20 + U32 SenseAmpDuration : 3; // Bits 26:24 + U32 BurstEndODTDelay : 3; // Bits 29:27 + U32 LpDdrLongOdtEn : 1; // Bits 30:30 + U32 Rsvd1 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA6CH1_CR_DDRCRDATACONTROL1_STRUCT; + +typedef union { + struct { + U32 RxStaggerCtl : 5; // Bits 4:0 + U32 ForceBiasOn : 1; // Bits 5:5 + U32 ForceRxOn : 1; // Bits 6:6 + U32 LeakerComp : 2; // Bits 8:7 + U32 RxDqsAmpOffset : 4; // Bits 12:9 + U32 RxClkStgNum : 5; // Bits 17:13 + U32 WlLongDelEn : 1; // Bits 18:18 + U32 Spare : 13; // Bits 31:19 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA6CH1_CR_DDRCRDATACONTROL2_STRUCT; + +typedef union { + struct { + U32 VssHiOrVrefCtl : 24; // Bits 23:0 + U32 OutputCode : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA6CH1_CR_DDRCRVSSHIORVREFCONTROL_STRUCT; + +typedef union { + struct { + U32 RcvEnOffset : 6; // Bits 5:0 + U32 RxDqsOffset : 6; // Bits 11:6 + U32 TxDqOffset : 6; // Bits 17:12 + U32 TxDqsOffset : 6; // Bits 23:18 + U32 VrefOffset : 7; // Bits 30:24 + U32 Spare : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA6CH1_CR_DDRCRDATAOFFSETTRAIN_STRUCT; + +typedef union { + struct { + U32 RxTrainingMode : 1; // Bits 0:0 + U32 WLTrainingMode : 1; // Bits 1:1 + U32 RLTrainingMode : 1; // Bits 2:2 + U32 SenseampTrainingMode : 1; // Bits 3:3 + U32 TxOn : 1; // Bits 4:4 + U32 RfOn : 1; // Bits 5:5 + U32 RxPiOn : 1; // Bits 6:6 + U32 TxPiOn : 1; // Bits 7:7 + U32 InternalClocksOn : 1; // Bits 8:8 + U32 RepeaterClocksOn : 1; // Bits 9:9 + U32 TxDisable : 1; // Bits 10:10 + U32 RxDisable : 1; // Bits 11:11 + U32 TxLong : 1; // Bits 12:12 + U32 RxDqsCtle : 2; // Bits 14:13 + U32 RxReadPointer : 3; // Bits 17:15 + U32 DriverSegmentEnable : 1; // Bits 18:18 + U32 DataVccddqHi : 1; // Bits 19:19 + U32 ReadRFRd : 1; // Bits 20:20 + U32 ReadRFWr : 1; // Bits 21:21 + U32 ReadRFRank : 2; // Bits 23:22 + U32 ForceOdtOn : 1; // Bits 24:24 + U32 OdtSampOff : 1; // Bits 25:25 + U32 DisableOdtStatic : 1; // Bits 26:26 + U32 DdrCRForceODTOn : 1; // Bits 27:27 + U32 LPDDR_Mode : 1; // Bits 28:28 + U32 EnReadPreamble : 1; // Bits 29:29 + U32 OdtSampExtendEn : 1; // Bits 30:30 + U32 EarlyRleakEn : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA6CH1_CR_DDRCRDATACONTROL0_STRUCT; + +typedef union { + struct { + U32 CAVrefCtl : 7; // Bits 6:0 + U32 Ch1VrefCtl : 7; // Bits 13:7 + U32 Ch0VrefCtl : 7; // Bits 20:14 + U32 EnDimmVrefCA : 1; // Bits 21:21 + U32 EnDimmVrefCh1 : 1; // Bits 22:22 + U32 EnDimmVrefCh0 : 1; // Bits 23:23 + U32 HiZTimerCtrl : 2; // Bits 25:24 + U32 VccddqHiQnnnH : 1; // Bits 26:26 + U32 Rsvd : 2; // Bits 28:27 + U32 caSlowBW : 1; // Bits 29:29 + U32 ch0SlowBW : 1; // Bits 30:30 + U32 ch1SlowBW : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA6CH1_CR_DDRCRVREFADJUST1_STRUCT; + +typedef union { + struct { + U32 RxRcvEnPi : 9; // Bits 8:0 + U32 RxDqsPPi : 6; // Bits 14:9 + U32 RxEq : 5; // Bits 19:15 + U32 RxDqsNPi : 6; // Bits 25:20 + U32 RxVref : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA7CH0_CR_RXTRAINRANK0_STRUCT; + +typedef union { + struct { + U32 RxRcvEnPi : 9; // Bits 8:0 + U32 RxDqsPPi : 6; // Bits 14:9 + U32 RxEq : 5; // Bits 19:15 + U32 RxDqsNPi : 6; // Bits 25:20 + U32 RxVref : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA7CH0_CR_RXTRAINRANK1_STRUCT; + +typedef union { + struct { + U32 RxRcvEnPi : 9; // Bits 8:0 + U32 RxDqsPPi : 6; // Bits 14:9 + U32 RxEq : 5; // Bits 19:15 + U32 RxDqsNPi : 6; // Bits 25:20 + U32 RxVref : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA7CH0_CR_RXTRAINRANK2_STRUCT; + +typedef union { + struct { + U32 RxRcvEnPi : 9; // Bits 8:0 + U32 RxDqsPPi : 6; // Bits 14:9 + U32 RxEq : 5; // Bits 19:15 + U32 RxDqsNPi : 6; // Bits 25:20 + U32 RxVref : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA7CH0_CR_RXTRAINRANK3_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA7CH0_CR_RXPERBITRANK0_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA7CH0_CR_RXPERBITRANK1_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA7CH0_CR_RXPERBITRANK2_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA7CH0_CR_RXPERBITRANK3_STRUCT; + +typedef union { + struct { + U32 TxDqDelay : 9; // Bits 8:0 + U32 TxDqsDelay : 9; // Bits 17:9 + U32 Spare0 : 2; // Bits 19:18 + U32 TxEqualization : 6; // Bits 25:20 + U32 Spare1 : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA7CH0_CR_TXTRAINRANK0_STRUCT; + +typedef union { + struct { + U32 TxDqDelay : 9; // Bits 8:0 + U32 TxDqsDelay : 9; // Bits 17:9 + U32 Spare0 : 2; // Bits 19:18 + U32 TxEqualization : 6; // Bits 25:20 + U32 Spare1 : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA7CH0_CR_TXTRAINRANK1_STRUCT; + +typedef union { + struct { + U32 TxDqDelay : 9; // Bits 8:0 + U32 TxDqsDelay : 9; // Bits 17:9 + U32 Spare0 : 2; // Bits 19:18 + U32 TxEqualization : 6; // Bits 25:20 + U32 Spare1 : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA7CH0_CR_TXTRAINRANK2_STRUCT; + +typedef union { + struct { + U32 TxDqDelay : 9; // Bits 8:0 + U32 TxDqsDelay : 9; // Bits 17:9 + U32 Spare0 : 2; // Bits 19:18 + U32 TxEqualization : 6; // Bits 25:20 + U32 Spare1 : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA7CH0_CR_TXTRAINRANK3_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA7CH0_CR_TXPERBITRANK0_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA7CH0_CR_TXPERBITRANK1_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA7CH0_CR_TXPERBITRANK2_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA7CH0_CR_TXPERBITRANK3_STRUCT; + +typedef union { + struct { + U32 RcompDrvUp : 6; // Bits 5:0 + U32 Spare0 : 3; // Bits 8:6 + U32 RcompDrvDown : 6; // Bits 14:9 + U32 VTComp : 5; // Bits 19:15 + U32 TcoComp : 6; // Bits 25:20 + U32 SlewRateComp : 5; // Bits 30:26 + U32 Spare2 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA7CH0_CR_RCOMPDATA0_STRUCT; + +typedef union { + struct { + U32 RcompOdtUp : 6; // Bits 5:0 + U32 Spare0 : 3; // Bits 8:6 + U32 RcompOdtDown : 6; // Bits 14:9 + U32 Spare1 : 1; // Bits 15:15 + U32 PanicDrvDn : 6; // Bits 21:16 + U32 PanicDrvUp : 6; // Bits 27:22 + U32 LevelShifterComp : 3; // Bits 30:28 + U32 Spare2 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA7CH0_CR_RCOMPDATA1_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA7CH0_CR_TXXTALK_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA7CH0_CR_RXOFFSETVDQ_STRUCT; + +typedef union { + struct { + U32 Spare : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA7CH0_CR_DDRDATARESERVED_STRUCT; + +typedef union { + struct { + U32 DataTrainFeedback : 9; // Bits 8:0 + U32 Spare : 23; // Bits 31:9 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA7CH0_CR_DATATRAINFEEDBACK_STRUCT; + +typedef union { + struct { + U32 RunTest : 1; // Bits 0:0 + U32 Load : 1; // Bits 1:1 + U32 ModeHVM : 1; // Bits 2:2 + U32 ModeDV : 1; // Bits 3:3 + U32 ModeADC : 1; // Bits 4:4 + U32 LoadCount : 10; // Bits 14:5 + U32 CountStatus : 10; // Bits 24:15 + U32 Spare : 7; // Bits 31:25 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA7CH0_CR_DLLPITESTANDADC_STRUCT; + +typedef union { + struct { + U32 DqDrvUpCompOffset : 6; // Bits 5:0 + U32 DqDrvDownCompOffset : 6; // Bits 11:6 + U32 DqOdtUpCompOffset : 5; // Bits 16:12 + U32 DqOdtDownCompOffset : 5; // Bits 21:17 + U32 DqTcoCompOffset : 5; // Bits 26:22 + U32 DqSlewRateCompOffset : 5; // Bits 31:27 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_STRUCT; + +typedef union { + struct { + U32 RefPi : 4; // Bits 3:0 + U32 DllMask : 2; // Bits 5:4 + U32 DllWeakLock : 1; // Bits 6:6 + U32 SdllSegmentDisable : 3; // Bits 9:7 + U32 RxBiasCtl : 3; // Bits 12:10 + U32 OdtDelay : 4; // Bits 16:13 + U32 OdtDuration : 3; // Bits 19:17 + U32 SenseAmpDelay : 4; // Bits 23:20 + U32 SenseAmpDuration : 3; // Bits 26:24 + U32 BurstEndODTDelay : 3; // Bits 29:27 + U32 LpDdrLongOdtEn : 1; // Bits 30:30 + U32 Rsvd1 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA7CH0_CR_DDRCRDATACONTROL1_STRUCT; + +typedef union { + struct { + U32 RxStaggerCtl : 5; // Bits 4:0 + U32 ForceBiasOn : 1; // Bits 5:5 + U32 ForceRxOn : 1; // Bits 6:6 + U32 LeakerComp : 2; // Bits 8:7 + U32 RxDqsAmpOffset : 4; // Bits 12:9 + U32 RxClkStgNum : 5; // Bits 17:13 + U32 WlLongDelEn : 1; // Bits 18:18 + U32 Spare : 13; // Bits 31:19 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA7CH0_CR_DDRCRDATACONTROL2_STRUCT; + +typedef union { + struct { + U32 VssHiOrVrefCtl : 24; // Bits 23:0 + U32 OutputCode : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA7CH0_CR_DDRCRVSSHIORVREFCONTROL_STRUCT; + +typedef union { + struct { + U32 RcvEnOffset : 6; // Bits 5:0 + U32 RxDqsOffset : 6; // Bits 11:6 + U32 TxDqOffset : 6; // Bits 17:12 + U32 TxDqsOffset : 6; // Bits 23:18 + U32 VrefOffset : 7; // Bits 30:24 + U32 Spare : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA7CH0_CR_DDRCRDATAOFFSETTRAIN_STRUCT; + +typedef union { + struct { + U32 RxTrainingMode : 1; // Bits 0:0 + U32 WLTrainingMode : 1; // Bits 1:1 + U32 RLTrainingMode : 1; // Bits 2:2 + U32 SenseampTrainingMode : 1; // Bits 3:3 + U32 TxOn : 1; // Bits 4:4 + U32 RfOn : 1; // Bits 5:5 + U32 RxPiOn : 1; // Bits 6:6 + U32 TxPiOn : 1; // Bits 7:7 + U32 InternalClocksOn : 1; // Bits 8:8 + U32 RepeaterClocksOn : 1; // Bits 9:9 + U32 TxDisable : 1; // Bits 10:10 + U32 RxDisable : 1; // Bits 11:11 + U32 TxLong : 1; // Bits 12:12 + U32 RxDqsCtle : 2; // Bits 14:13 + U32 RxReadPointer : 3; // Bits 17:15 + U32 DriverSegmentEnable : 1; // Bits 18:18 + U32 DataVccddqHi : 1; // Bits 19:19 + U32 ReadRFRd : 1; // Bits 20:20 + U32 ReadRFWr : 1; // Bits 21:21 + U32 ReadRFRank : 2; // Bits 23:22 + U32 ForceOdtOn : 1; // Bits 24:24 + U32 OdtSampOff : 1; // Bits 25:25 + U32 DisableOdtStatic : 1; // Bits 26:26 + U32 DdrCRForceODTOn : 1; // Bits 27:27 + U32 LPDDR_Mode : 1; // Bits 28:28 + U32 EnReadPreamble : 1; // Bits 29:29 + U32 OdtSampExtendEn : 1; // Bits 30:30 + U32 EarlyRleakEn : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA7CH0_CR_DDRCRDATACONTROL0_STRUCT; + +typedef union { + struct { + U32 CAVrefCtl : 7; // Bits 6:0 + U32 Ch1VrefCtl : 7; // Bits 13:7 + U32 Ch0VrefCtl : 7; // Bits 20:14 + U32 EnDimmVrefCA : 1; // Bits 21:21 + U32 EnDimmVrefCh1 : 1; // Bits 22:22 + U32 EnDimmVrefCh0 : 1; // Bits 23:23 + U32 HiZTimerCtrl : 2; // Bits 25:24 + U32 VccddqHiQnnnH : 1; // Bits 26:26 + U32 Rsvd : 2; // Bits 28:27 + U32 caSlowBW : 1; // Bits 29:29 + U32 ch0SlowBW : 1; // Bits 30:30 + U32 ch1SlowBW : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA7CH0_CR_DDRCRVREFADJUST1_STRUCT; + +typedef union { + struct { + U32 RxRcvEnPi : 9; // Bits 8:0 + U32 RxDqsPPi : 6; // Bits 14:9 + U32 RxEq : 5; // Bits 19:15 + U32 RxDqsNPi : 6; // Bits 25:20 + U32 RxVref : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA7CH1_CR_RXTRAINRANK0_STRUCT; + +typedef union { + struct { + U32 RxRcvEnPi : 9; // Bits 8:0 + U32 RxDqsPPi : 6; // Bits 14:9 + U32 RxEq : 5; // Bits 19:15 + U32 RxDqsNPi : 6; // Bits 25:20 + U32 RxVref : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA7CH1_CR_RXTRAINRANK1_STRUCT; + +typedef union { + struct { + U32 RxRcvEnPi : 9; // Bits 8:0 + U32 RxDqsPPi : 6; // Bits 14:9 + U32 RxEq : 5; // Bits 19:15 + U32 RxDqsNPi : 6; // Bits 25:20 + U32 RxVref : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA7CH1_CR_RXTRAINRANK2_STRUCT; + +typedef union { + struct { + U32 RxRcvEnPi : 9; // Bits 8:0 + U32 RxDqsPPi : 6; // Bits 14:9 + U32 RxEq : 5; // Bits 19:15 + U32 RxDqsNPi : 6; // Bits 25:20 + U32 RxVref : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA7CH1_CR_RXTRAINRANK3_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA7CH1_CR_RXPERBITRANK0_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA7CH1_CR_RXPERBITRANK1_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA7CH1_CR_RXPERBITRANK2_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA7CH1_CR_RXPERBITRANK3_STRUCT; + +typedef union { + struct { + U32 TxDqDelay : 9; // Bits 8:0 + U32 TxDqsDelay : 9; // Bits 17:9 + U32 Spare0 : 2; // Bits 19:18 + U32 TxEqualization : 6; // Bits 25:20 + U32 Spare1 : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA7CH1_CR_TXTRAINRANK0_STRUCT; + +typedef union { + struct { + U32 TxDqDelay : 9; // Bits 8:0 + U32 TxDqsDelay : 9; // Bits 17:9 + U32 Spare0 : 2; // Bits 19:18 + U32 TxEqualization : 6; // Bits 25:20 + U32 Spare1 : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA7CH1_CR_TXTRAINRANK1_STRUCT; + +typedef union { + struct { + U32 TxDqDelay : 9; // Bits 8:0 + U32 TxDqsDelay : 9; // Bits 17:9 + U32 Spare0 : 2; // Bits 19:18 + U32 TxEqualization : 6; // Bits 25:20 + U32 Spare1 : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA7CH1_CR_TXTRAINRANK2_STRUCT; + +typedef union { + struct { + U32 TxDqDelay : 9; // Bits 8:0 + U32 TxDqsDelay : 9; // Bits 17:9 + U32 Spare0 : 2; // Bits 19:18 + U32 TxEqualization : 6; // Bits 25:20 + U32 Spare1 : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA7CH1_CR_TXTRAINRANK3_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA7CH1_CR_TXPERBITRANK0_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA7CH1_CR_TXPERBITRANK1_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA7CH1_CR_TXPERBITRANK2_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA7CH1_CR_TXPERBITRANK3_STRUCT; + +typedef union { + struct { + U32 RcompDrvUp : 6; // Bits 5:0 + U32 Spare0 : 3; // Bits 8:6 + U32 RcompDrvDown : 6; // Bits 14:9 + U32 VTComp : 5; // Bits 19:15 + U32 TcoComp : 6; // Bits 25:20 + U32 SlewRateComp : 5; // Bits 30:26 + U32 Spare2 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA7CH1_CR_RCOMPDATA0_STRUCT; + +typedef union { + struct { + U32 RcompOdtUp : 6; // Bits 5:0 + U32 Spare0 : 3; // Bits 8:6 + U32 RcompOdtDown : 6; // Bits 14:9 + U32 Spare1 : 1; // Bits 15:15 + U32 PanicDrvDn : 6; // Bits 21:16 + U32 PanicDrvUp : 6; // Bits 27:22 + U32 LevelShifterComp : 3; // Bits 30:28 + U32 Spare2 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA7CH1_CR_RCOMPDATA1_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA7CH1_CR_TXXTALK_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA7CH1_CR_RXOFFSETVDQ_STRUCT; + +typedef union { + struct { + U32 Spare : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA7CH1_CR_DDRDATARESERVED_STRUCT; + +typedef union { + struct { + U32 DataTrainFeedback : 9; // Bits 8:0 + U32 Spare : 23; // Bits 31:9 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA7CH1_CR_DATATRAINFEEDBACK_STRUCT; + +typedef union { + struct { + U32 RunTest : 1; // Bits 0:0 + U32 Load : 1; // Bits 1:1 + U32 ModeHVM : 1; // Bits 2:2 + U32 ModeDV : 1; // Bits 3:3 + U32 ModeADC : 1; // Bits 4:4 + U32 LoadCount : 10; // Bits 14:5 + U32 CountStatus : 10; // Bits 24:15 + U32 Spare : 7; // Bits 31:25 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA7CH1_CR_DLLPITESTANDADC_STRUCT; + +typedef union { + struct { + U32 DqDrvUpCompOffset : 6; // Bits 5:0 + U32 DqDrvDownCompOffset : 6; // Bits 11:6 + U32 DqOdtUpCompOffset : 5; // Bits 16:12 + U32 DqOdtDownCompOffset : 5; // Bits 21:17 + U32 DqTcoCompOffset : 5; // Bits 26:22 + U32 DqSlewRateCompOffset : 5; // Bits 31:27 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_STRUCT; + +typedef union { + struct { + U32 RefPi : 4; // Bits 3:0 + U32 DllMask : 2; // Bits 5:4 + U32 DllWeakLock : 1; // Bits 6:6 + U32 SdllSegmentDisable : 3; // Bits 9:7 + U32 RxBiasCtl : 3; // Bits 12:10 + U32 OdtDelay : 4; // Bits 16:13 + U32 OdtDuration : 3; // Bits 19:17 + U32 SenseAmpDelay : 4; // Bits 23:20 + U32 SenseAmpDuration : 3; // Bits 26:24 + U32 BurstEndODTDelay : 3; // Bits 29:27 + U32 LpDdrLongOdtEn : 1; // Bits 30:30 + U32 Rsvd1 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA7CH1_CR_DDRCRDATACONTROL1_STRUCT; + +typedef union { + struct { + U32 RxStaggerCtl : 5; // Bits 4:0 + U32 ForceBiasOn : 1; // Bits 5:5 + U32 ForceRxOn : 1; // Bits 6:6 + U32 LeakerComp : 2; // Bits 8:7 + U32 RxDqsAmpOffset : 4; // Bits 12:9 + U32 RxClkStgNum : 5; // Bits 17:13 + U32 WlLongDelEn : 1; // Bits 18:18 + U32 Spare : 13; // Bits 31:19 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA7CH1_CR_DDRCRDATACONTROL2_STRUCT; + +typedef union { + struct { + U32 VrefCtl : 24; // Bits 23:0 + U32 OutputCode : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA7CH1_CR_DDRCRVREFCONTROL_STRUCT; + +typedef union { + struct { + U32 VssHiCtl : 24; // Bits 23:0 + U32 OutputCode : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA7CH1_CR_DDRCRVSSHICONTROL_STRUCT; + +typedef union { + struct { + U32 VssHiOrVrefCtl : 24; // Bits 23:0 + U32 OutputCode : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA7CH1_CR_DDRCRVSSHIORVREFCONTROL_STRUCT; + +typedef union { + struct { + U32 RcvEnOffset : 6; // Bits 5:0 + U32 RxDqsOffset : 6; // Bits 11:6 + U32 TxDqOffset : 6; // Bits 17:12 + U32 TxDqsOffset : 6; // Bits 23:18 + U32 VrefOffset : 7; // Bits 30:24 + U32 Spare : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA7CH1_CR_DDRCRDATAOFFSETTRAIN_STRUCT; + +typedef union { + struct { + U32 RxTrainingMode : 1; // Bits 0:0 + U32 WLTrainingMode : 1; // Bits 1:1 + U32 RLTrainingMode : 1; // Bits 2:2 + U32 SenseampTrainingMode : 1; // Bits 3:3 + U32 TxOn : 1; // Bits 4:4 + U32 RfOn : 1; // Bits 5:5 + U32 RxPiOn : 1; // Bits 6:6 + U32 TxPiOn : 1; // Bits 7:7 + U32 InternalClocksOn : 1; // Bits 8:8 + U32 RepeaterClocksOn : 1; // Bits 9:9 + U32 TxDisable : 1; // Bits 10:10 + U32 RxDisable : 1; // Bits 11:11 + U32 TxLong : 1; // Bits 12:12 + U32 RxDqsCtle : 2; // Bits 14:13 + U32 RxReadPointer : 3; // Bits 17:15 + U32 DriverSegmentEnable : 1; // Bits 18:18 + U32 DataVccddqHi : 1; // Bits 19:19 + U32 ReadRFRd : 1; // Bits 20:20 + U32 ReadRFWr : 1; // Bits 21:21 + U32 ReadRFRank : 2; // Bits 23:22 + U32 ForceOdtOn : 1; // Bits 24:24 + U32 OdtSampOff : 1; // Bits 25:25 + U32 DisableOdtStatic : 1; // Bits 26:26 + U32 DdrCRForceODTOn : 1; // Bits 27:27 + U32 LPDDR_Mode : 1; // Bits 28:28 + U32 EnReadPreamble : 1; // Bits 29:29 + U32 OdtSampExtendEn : 1; // Bits 30:30 + U32 EarlyRleakEn : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA7CH1_CR_DDRCRDATACONTROL0_STRUCT; + +typedef union { + struct { + U32 CAVrefCtl : 7; // Bits 6:0 + U32 Ch1VrefCtl : 7; // Bits 13:7 + U32 Ch0VrefCtl : 7; // Bits 20:14 + U32 EnDimmVrefCA : 1; // Bits 21:21 + U32 EnDimmVrefCh1 : 1; // Bits 22:22 + U32 EnDimmVrefCh0 : 1; // Bits 23:23 + U32 HiZTimerCtrl : 2; // Bits 25:24 + U32 VccddqHiQnnnH : 1; // Bits 26:26 + U32 Rsvd : 2; // Bits 28:27 + U32 caSlowBW : 1; // Bits 29:29 + U32 ch0SlowBW : 1; // Bits 30:30 + U32 ch1SlowBW : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA7CH1_CR_DDRCRVREFADJUST1_STRUCT; + +typedef union { + struct { + U32 RxRcvEnPi : 9; // Bits 8:0 + U32 RxDqsPPi : 6; // Bits 14:9 + U32 RxEq : 5; // Bits 19:15 + U32 RxDqsNPi : 6; // Bits 25:20 + U32 RxVref : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA8CH0_CR_RXTRAINRANK0_STRUCT; + +typedef union { + struct { + U32 RxRcvEnPi : 9; // Bits 8:0 + U32 RxDqsPPi : 6; // Bits 14:9 + U32 RxEq : 5; // Bits 19:15 + U32 RxDqsNPi : 6; // Bits 25:20 + U32 RxVref : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA8CH0_CR_RXTRAINRANK1_STRUCT; + +typedef union { + struct { + U32 RxRcvEnPi : 9; // Bits 8:0 + U32 RxDqsPPi : 6; // Bits 14:9 + U32 RxEq : 5; // Bits 19:15 + U32 RxDqsNPi : 6; // Bits 25:20 + U32 RxVref : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA8CH0_CR_RXTRAINRANK2_STRUCT; + +typedef union { + struct { + U32 RxRcvEnPi : 9; // Bits 8:0 + U32 RxDqsPPi : 6; // Bits 14:9 + U32 RxEq : 5; // Bits 19:15 + U32 RxDqsNPi : 6; // Bits 25:20 + U32 RxVref : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA8CH0_CR_RXTRAINRANK3_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA8CH0_CR_RXPERBITRANK0_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA8CH0_CR_RXPERBITRANK1_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA8CH0_CR_RXPERBITRANK2_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA8CH0_CR_RXPERBITRANK3_STRUCT; + +typedef union { + struct { + U32 TxDqDelay : 9; // Bits 8:0 + U32 TxDqsDelay : 9; // Bits 17:9 + U32 Spare0 : 2; // Bits 19:18 + U32 TxEqualization : 6; // Bits 25:20 + U32 Spare1 : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA8CH0_CR_TXTRAINRANK0_STRUCT; + +typedef union { + struct { + U32 TxDqDelay : 9; // Bits 8:0 + U32 TxDqsDelay : 9; // Bits 17:9 + U32 Spare0 : 2; // Bits 19:18 + U32 TxEqualization : 6; // Bits 25:20 + U32 Spare1 : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA8CH0_CR_TXTRAINRANK1_STRUCT; + +typedef union { + struct { + U32 TxDqDelay : 9; // Bits 8:0 + U32 TxDqsDelay : 9; // Bits 17:9 + U32 Spare0 : 2; // Bits 19:18 + U32 TxEqualization : 6; // Bits 25:20 + U32 Spare1 : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA8CH0_CR_TXTRAINRANK2_STRUCT; + +typedef union { + struct { + U32 TxDqDelay : 9; // Bits 8:0 + U32 TxDqsDelay : 9; // Bits 17:9 + U32 Spare0 : 2; // Bits 19:18 + U32 TxEqualization : 6; // Bits 25:20 + U32 Spare1 : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA8CH0_CR_TXTRAINRANK3_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA8CH0_CR_TXPERBITRANK0_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA8CH0_CR_TXPERBITRANK1_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA8CH0_CR_TXPERBITRANK2_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA8CH0_CR_TXPERBITRANK3_STRUCT; + +typedef union { + struct { + U32 RcompDrvUp : 6; // Bits 5:0 + U32 Spare0 : 3; // Bits 8:6 + U32 RcompDrvDown : 6; // Bits 14:9 + U32 VTComp : 5; // Bits 19:15 + U32 TcoComp : 6; // Bits 25:20 + U32 SlewRateComp : 5; // Bits 30:26 + U32 Spare2 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA8CH0_CR_RCOMPDATA0_STRUCT; + +typedef union { + struct { + U32 RcompOdtUp : 6; // Bits 5:0 + U32 Spare0 : 3; // Bits 8:6 + U32 RcompOdtDown : 6; // Bits 14:9 + U32 Spare1 : 1; // Bits 15:15 + U32 PanicDrvDn : 6; // Bits 21:16 + U32 PanicDrvUp : 6; // Bits 27:22 + U32 LevelShifterComp : 3; // Bits 30:28 + U32 Spare2 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA8CH0_CR_RCOMPDATA1_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA8CH0_CR_TXXTALK_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA8CH0_CR_RXOFFSETVDQ_STRUCT; + +typedef union { + struct { + U32 Spare : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA8CH0_CR_DDRDATARESERVED_STRUCT; + +typedef union { + struct { + U32 DataTrainFeedback : 9; // Bits 8:0 + U32 Spare : 23; // Bits 31:9 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA8CH0_CR_DATATRAINFEEDBACK_STRUCT; + +typedef union { + struct { + U32 RunTest : 1; // Bits 0:0 + U32 Load : 1; // Bits 1:1 + U32 ModeHVM : 1; // Bits 2:2 + U32 ModeDV : 1; // Bits 3:3 + U32 ModeADC : 1; // Bits 4:4 + U32 LoadCount : 10; // Bits 14:5 + U32 CountStatus : 10; // Bits 24:15 + U32 Spare : 7; // Bits 31:25 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA8CH0_CR_DLLPITESTANDADC_STRUCT; + +typedef union { + struct { + U32 DqDrvUpCompOffset : 6; // Bits 5:0 + U32 DqDrvDownCompOffset : 6; // Bits 11:6 + U32 DqOdtUpCompOffset : 5; // Bits 16:12 + U32 DqOdtDownCompOffset : 5; // Bits 21:17 + U32 DqTcoCompOffset : 5; // Bits 26:22 + U32 DqSlewRateCompOffset : 5; // Bits 31:27 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_STRUCT; + +typedef union { + struct { + U32 RefPi : 4; // Bits 3:0 + U32 DllMask : 2; // Bits 5:4 + U32 DllWeakLock : 1; // Bits 6:6 + U32 SdllSegmentDisable : 3; // Bits 9:7 + U32 RxBiasCtl : 3; // Bits 12:10 + U32 OdtDelay : 4; // Bits 16:13 + U32 OdtDuration : 3; // Bits 19:17 + U32 SenseAmpDelay : 4; // Bits 23:20 + U32 SenseAmpDuration : 3; // Bits 26:24 + U32 BurstEndODTDelay : 3; // Bits 29:27 + U32 LpDdrLongOdtEn : 1; // Bits 30:30 + U32 Rsvd1 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA8CH0_CR_DDRCRDATACONTROL1_STRUCT; + +typedef union { + struct { + U32 RxStaggerCtl : 5; // Bits 4:0 + U32 ForceBiasOn : 1; // Bits 5:5 + U32 ForceRxOn : 1; // Bits 6:6 + U32 LeakerComp : 2; // Bits 8:7 + U32 RxDqsAmpOffset : 4; // Bits 12:9 + U32 RxClkStgNum : 5; // Bits 17:13 + U32 WlLongDelEn : 1; // Bits 18:18 + U32 Spare : 13; // Bits 31:19 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA8CH0_CR_DDRCRDATACONTROL2_STRUCT; + +typedef union { + struct { + U32 VssHiOrVrefCtl : 24; // Bits 23:0 + U32 OutputCode : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA8CH0_CR_DDRCRVSSHIORVREFCONTROL_STRUCT; + +typedef union { + struct { + U32 RcvEnOffset : 6; // Bits 5:0 + U32 RxDqsOffset : 6; // Bits 11:6 + U32 TxDqOffset : 6; // Bits 17:12 + U32 TxDqsOffset : 6; // Bits 23:18 + U32 VrefOffset : 7; // Bits 30:24 + U32 Spare : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA8CH0_CR_DDRCRDATAOFFSETTRAIN_STRUCT; + +typedef union { + struct { + U32 RxTrainingMode : 1; // Bits 0:0 + U32 WLTrainingMode : 1; // Bits 1:1 + U32 RLTrainingMode : 1; // Bits 2:2 + U32 SenseampTrainingMode : 1; // Bits 3:3 + U32 TxOn : 1; // Bits 4:4 + U32 RfOn : 1; // Bits 5:5 + U32 RxPiOn : 1; // Bits 6:6 + U32 TxPiOn : 1; // Bits 7:7 + U32 InternalClocksOn : 1; // Bits 8:8 + U32 RepeaterClocksOn : 1; // Bits 9:9 + U32 TxDisable : 1; // Bits 10:10 + U32 RxDisable : 1; // Bits 11:11 + U32 TxLong : 1; // Bits 12:12 + U32 RxDqsCtle : 2; // Bits 14:13 + U32 RxReadPointer : 3; // Bits 17:15 + U32 DriverSegmentEnable : 1; // Bits 18:18 + U32 DataVccddqHi : 1; // Bits 19:19 + U32 ReadRFRd : 1; // Bits 20:20 + U32 ReadRFWr : 1; // Bits 21:21 + U32 ReadRFRank : 2; // Bits 23:22 + U32 ForceOdtOn : 1; // Bits 24:24 + U32 OdtSampOff : 1; // Bits 25:25 + U32 DisableOdtStatic : 1; // Bits 26:26 + U32 DdrCRForceODTOn : 1; // Bits 27:27 + U32 LPDDR_Mode : 1; // Bits 28:28 + U32 EnReadPreamble : 1; // Bits 29:29 + U32 OdtSampExtendEn : 1; // Bits 30:30 + U32 EarlyRleakEn : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA8CH0_CR_DDRCRDATACONTROL0_STRUCT; + +typedef union { + struct { + U32 CAVrefCtl : 7; // Bits 6:0 + U32 Ch1VrefCtl : 7; // Bits 13:7 + U32 Ch0VrefCtl : 7; // Bits 20:14 + U32 EnDimmVrefCA : 1; // Bits 21:21 + U32 EnDimmVrefCh1 : 1; // Bits 22:22 + U32 EnDimmVrefCh0 : 1; // Bits 23:23 + U32 HiZTimerCtrl : 2; // Bits 25:24 + U32 VccddqHiQnnnH : 1; // Bits 26:26 + U32 Rsvd : 2; // Bits 28:27 + U32 caSlowBW : 1; // Bits 29:29 + U32 ch0SlowBW : 1; // Bits 30:30 + U32 ch1SlowBW : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA8CH0_CR_DDRCRVREFADJUST1_STRUCT; + +typedef union { + struct { + U32 RxRcvEnPi : 9; // Bits 8:0 + U32 RxDqsPPi : 6; // Bits 14:9 + U32 RxEq : 5; // Bits 19:15 + U32 RxDqsNPi : 6; // Bits 25:20 + U32 RxVref : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA8CH1_CR_RXTRAINRANK0_STRUCT; + +typedef union { + struct { + U32 RxRcvEnPi : 9; // Bits 8:0 + U32 RxDqsPPi : 6; // Bits 14:9 + U32 RxEq : 5; // Bits 19:15 + U32 RxDqsNPi : 6; // Bits 25:20 + U32 RxVref : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA8CH1_CR_RXTRAINRANK1_STRUCT; + +typedef union { + struct { + U32 RxRcvEnPi : 9; // Bits 8:0 + U32 RxDqsPPi : 6; // Bits 14:9 + U32 RxEq : 5; // Bits 19:15 + U32 RxDqsNPi : 6; // Bits 25:20 + U32 RxVref : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA8CH1_CR_RXTRAINRANK2_STRUCT; + +typedef union { + struct { + U32 RxRcvEnPi : 9; // Bits 8:0 + U32 RxDqsPPi : 6; // Bits 14:9 + U32 RxEq : 5; // Bits 19:15 + U32 RxDqsNPi : 6; // Bits 25:20 + U32 RxVref : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA8CH1_CR_RXTRAINRANK3_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA8CH1_CR_RXPERBITRANK0_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA8CH1_CR_RXPERBITRANK1_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA8CH1_CR_RXPERBITRANK2_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA8CH1_CR_RXPERBITRANK3_STRUCT; + +typedef union { + struct { + U32 TxDqDelay : 9; // Bits 8:0 + U32 TxDqsDelay : 9; // Bits 17:9 + U32 Spare0 : 2; // Bits 19:18 + U32 TxEqualization : 6; // Bits 25:20 + U32 Spare1 : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA8CH1_CR_TXTRAINRANK0_STRUCT; + +typedef union { + struct { + U32 TxDqDelay : 9; // Bits 8:0 + U32 TxDqsDelay : 9; // Bits 17:9 + U32 Spare0 : 2; // Bits 19:18 + U32 TxEqualization : 6; // Bits 25:20 + U32 Spare1 : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA8CH1_CR_TXTRAINRANK1_STRUCT; + +typedef union { + struct { + U32 TxDqDelay : 9; // Bits 8:0 + U32 TxDqsDelay : 9; // Bits 17:9 + U32 Spare0 : 2; // Bits 19:18 + U32 TxEqualization : 6; // Bits 25:20 + U32 Spare1 : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA8CH1_CR_TXTRAINRANK2_STRUCT; + +typedef union { + struct { + U32 TxDqDelay : 9; // Bits 8:0 + U32 TxDqsDelay : 9; // Bits 17:9 + U32 Spare0 : 2; // Bits 19:18 + U32 TxEqualization : 6; // Bits 25:20 + U32 Spare1 : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA8CH1_CR_TXTRAINRANK3_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA8CH1_CR_TXPERBITRANK0_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA8CH1_CR_TXPERBITRANK1_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA8CH1_CR_TXPERBITRANK2_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA8CH1_CR_TXPERBITRANK3_STRUCT; + +typedef union { + struct { + U32 RcompDrvUp : 6; // Bits 5:0 + U32 Spare0 : 3; // Bits 8:6 + U32 RcompDrvDown : 6; // Bits 14:9 + U32 VTComp : 5; // Bits 19:15 + U32 TcoComp : 6; // Bits 25:20 + U32 SlewRateComp : 5; // Bits 30:26 + U32 Spare2 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA8CH1_CR_RCOMPDATA0_STRUCT; + +typedef union { + struct { + U32 RcompOdtUp : 6; // Bits 5:0 + U32 Spare0 : 3; // Bits 8:6 + U32 RcompOdtDown : 6; // Bits 14:9 + U32 Spare1 : 1; // Bits 15:15 + U32 PanicDrvDn : 6; // Bits 21:16 + U32 PanicDrvUp : 6; // Bits 27:22 + U32 LevelShifterComp : 3; // Bits 30:28 + U32 Spare2 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA8CH1_CR_RCOMPDATA1_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA8CH1_CR_TXXTALK_STRUCT; + +typedef union { + struct { + U32 Lane0 : 4; // Bits 3:0 + U32 Lane1 : 4; // Bits 7:4 + U32 Lane2 : 4; // Bits 11:8 + U32 Lane3 : 4; // Bits 15:12 + U32 Lane4 : 4; // Bits 19:16 + U32 Lane5 : 4; // Bits 23:20 + U32 Lane6 : 4; // Bits 27:24 + U32 Lane7 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA8CH1_CR_RXOFFSETVDQ_STRUCT; + +typedef union { + struct { + U32 Spare : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA8CH1_CR_DDRDATARESERVED_STRUCT; + +typedef union { + struct { + U32 DataTrainFeedback : 9; // Bits 8:0 + U32 Spare : 23; // Bits 31:9 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA8CH1_CR_DATATRAINFEEDBACK_STRUCT; + +typedef union { + struct { + U32 RunTest : 1; // Bits 0:0 + U32 Load : 1; // Bits 1:1 + U32 ModeHVM : 1; // Bits 2:2 + U32 ModeDV : 1; // Bits 3:3 + U32 ModeADC : 1; // Bits 4:4 + U32 LoadCount : 10; // Bits 14:5 + U32 CountStatus : 10; // Bits 24:15 + U32 Spare : 7; // Bits 31:25 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA8CH1_CR_DLLPITESTANDADC_STRUCT; + +typedef union { + struct { + U32 DqDrvUpCompOffset : 6; // Bits 5:0 + U32 DqDrvDownCompOffset : 6; // Bits 11:6 + U32 DqOdtUpCompOffset : 5; // Bits 16:12 + U32 DqOdtDownCompOffset : 5; // Bits 21:17 + U32 DqTcoCompOffset : 5; // Bits 26:22 + U32 DqSlewRateCompOffset : 5; // Bits 31:27 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_STRUCT; + +typedef union { + struct { + U32 RefPi : 4; // Bits 3:0 + U32 DllMask : 2; // Bits 5:4 + U32 DllWeakLock : 1; // Bits 6:6 + U32 SdllSegmentDisable : 3; // Bits 9:7 + U32 RxBiasCtl : 3; // Bits 12:10 + U32 OdtDelay : 4; // Bits 16:13 + U32 OdtDuration : 3; // Bits 19:17 + U32 SenseAmpDelay : 4; // Bits 23:20 + U32 SenseAmpDuration : 3; // Bits 26:24 + U32 BurstEndODTDelay : 3; // Bits 29:27 + U32 LpDdrLongOdtEn : 1; // Bits 30:30 + U32 Rsvd1 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA8CH1_CR_DDRCRDATACONTROL1_STRUCT; + +typedef union { + struct { + U32 RxStaggerCtl : 5; // Bits 4:0 + U32 ForceBiasOn : 1; // Bits 5:5 + U32 ForceRxOn : 1; // Bits 6:6 + U32 LeakerComp : 2; // Bits 8:7 + U32 RxDqsAmpOffset : 4; // Bits 12:9 + U32 RxClkStgNum : 5; // Bits 17:13 + U32 WlLongDelEn : 1; // Bits 18:18 + U32 Spare : 13; // Bits 31:19 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA8CH1_CR_DDRCRDATACONTROL2_STRUCT; + +typedef union { + struct { + U32 VssHiOrVrefCtl : 24; // Bits 23:0 + U32 OutputCode : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA8CH1_CR_DDRCRVSSHIORVREFCONTROL_STRUCT; + +typedef union { + struct { + U32 RcvEnOffset : 6; // Bits 5:0 + U32 RxDqsOffset : 6; // Bits 11:6 + U32 TxDqOffset : 6; // Bits 17:12 + U32 TxDqsOffset : 6; // Bits 23:18 + U32 VrefOffset : 7; // Bits 30:24 + U32 Spare : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA8CH1_CR_DDRCRDATAOFFSETTRAIN_STRUCT; + +typedef union { + struct { + U32 RxTrainingMode : 1; // Bits 0:0 + U32 WLTrainingMode : 1; // Bits 1:1 + U32 RLTrainingMode : 1; // Bits 2:2 + U32 SenseampTrainingMode : 1; // Bits 3:3 + U32 TxOn : 1; // Bits 4:4 + U32 RfOn : 1; // Bits 5:5 + U32 RxPiOn : 1; // Bits 6:6 + U32 TxPiOn : 1; // Bits 7:7 + U32 InternalClocksOn : 1; // Bits 8:8 + U32 RepeaterClocksOn : 1; // Bits 9:9 + U32 TxDisable : 1; // Bits 10:10 + U32 RxDisable : 1; // Bits 11:11 + U32 TxLong : 1; // Bits 12:12 + U32 RxDqsCtle : 2; // Bits 14:13 + U32 RxReadPointer : 3; // Bits 17:15 + U32 DriverSegmentEnable : 1; // Bits 18:18 + U32 DataVccddqHi : 1; // Bits 19:19 + U32 ReadRFRd : 1; // Bits 20:20 + U32 ReadRFWr : 1; // Bits 21:21 + U32 ReadRFRank : 2; // Bits 23:22 + U32 ForceOdtOn : 1; // Bits 24:24 + U32 OdtSampOff : 1; // Bits 25:25 + U32 DisableOdtStatic : 1; // Bits 26:26 + U32 DdrCRForceODTOn : 1; // Bits 27:27 + U32 LPDDR_Mode : 1; // Bits 28:28 + U32 EnReadPreamble : 1; // Bits 29:29 + U32 OdtSampExtendEn : 1; // Bits 30:30 + U32 EarlyRleakEn : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA8CH1_CR_DDRCRDATACONTROL0_STRUCT; + +typedef union { + struct { + U32 CAVrefCtl : 7; // Bits 6:0 + U32 Ch1VrefCtl : 7; // Bits 13:7 + U32 Ch0VrefCtl : 7; // Bits 20:14 + U32 EnDimmVrefCA : 1; // Bits 21:21 + U32 EnDimmVrefCh1 : 1; // Bits 22:22 + U32 EnDimmVrefCh0 : 1; // Bits 23:23 + U32 HiZTimerCtrl : 2; // Bits 25:24 + U32 VccddqHiQnnnH : 1; // Bits 26:26 + U32 Rsvd : 2; // Bits 28:27 + U32 caSlowBW : 1; // Bits 29:29 + U32 ch0SlowBW : 1; // Bits 30:30 + U32 ch1SlowBW : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRDATA8CH1_CR_DDRCRVREFADJUST1_STRUCT; + +#define DDRDATA_CR_RXTRAINRANK0_REG (0x00003600) + #define DDRDATA_CR_RXTRAINRANK0_RxRcvEnPi_OFF ( 0) + #define DDRDATA_CR_RXTRAINRANK0_RxRcvEnPi_WID ( 9) + #define DDRDATA_CR_RXTRAINRANK0_RxRcvEnPi_MSK (0x000001FF) + #define DDRDATA_CR_RXTRAINRANK0_RxRcvEnPi_MAX (0x000001FF) + #define DDRDATA_CR_RXTRAINRANK0_RxDqsPPi_OFF ( 9) + #define DDRDATA_CR_RXTRAINRANK0_RxDqsPPi_WID ( 6) + #define DDRDATA_CR_RXTRAINRANK0_RxDqsPPi_MSK (0x00007E00) + #define DDRDATA_CR_RXTRAINRANK0_RxDqsPPi_MAX (0x0000003F) + #define DDRDATA_CR_RXTRAINRANK0_RxEq_OFF (15) + #define DDRDATA_CR_RXTRAINRANK0_RxEq_WID ( 5) + #define DDRDATA_CR_RXTRAINRANK0_RxEq_MSK (0x000F8000) + #define DDRDATA_CR_RXTRAINRANK0_RxEq_MAX (0x0000001F) + #define DDRDATA_CR_RXTRAINRANK0_RxDqsNPi_OFF (20) + #define DDRDATA_CR_RXTRAINRANK0_RxDqsNPi_WID ( 6) + #define DDRDATA_CR_RXTRAINRANK0_RxDqsNPi_MSK (0x03F00000) + #define DDRDATA_CR_RXTRAINRANK0_RxDqsNPi_MAX (0x0000003F) + #define DDRDATA_CR_RXTRAINRANK0_RxVref_OFF (26) + #define DDRDATA_CR_RXTRAINRANK0_RxVref_WID ( 6) + #define DDRDATA_CR_RXTRAINRANK0_RxVref_MSK (0xFC000000) + #define DDRDATA_CR_RXTRAINRANK0_RxVref_MAX (0x0000003F) + +#define DDRDATA_CR_RXTRAINRANK1_REG (0x00003604) + #define DDRDATA_CR_RXTRAINRANK1_RxRcvEnPi_OFF ( 0) + #define DDRDATA_CR_RXTRAINRANK1_RxRcvEnPi_WID ( 9) + #define DDRDATA_CR_RXTRAINRANK1_RxRcvEnPi_MSK (0x000001FF) + #define DDRDATA_CR_RXTRAINRANK1_RxRcvEnPi_MAX (0x000001FF) + #define DDRDATA_CR_RXTRAINRANK1_RxDqsPPi_OFF ( 9) + #define DDRDATA_CR_RXTRAINRANK1_RxDqsPPi_WID ( 6) + #define DDRDATA_CR_RXTRAINRANK1_RxDqsPPi_MSK (0x00007E00) + #define DDRDATA_CR_RXTRAINRANK1_RxDqsPPi_MAX (0x0000003F) + #define DDRDATA_CR_RXTRAINRANK1_RxEq_OFF (15) + #define DDRDATA_CR_RXTRAINRANK1_RxEq_WID ( 5) + #define DDRDATA_CR_RXTRAINRANK1_RxEq_MSK (0x000F8000) + #define DDRDATA_CR_RXTRAINRANK1_RxEq_MAX (0x0000001F) + #define DDRDATA_CR_RXTRAINRANK1_RxDqsNPi_OFF (20) + #define DDRDATA_CR_RXTRAINRANK1_RxDqsNPi_WID ( 6) + #define DDRDATA_CR_RXTRAINRANK1_RxDqsNPi_MSK (0x03F00000) + #define DDRDATA_CR_RXTRAINRANK1_RxDqsNPi_MAX (0x0000003F) + #define DDRDATA_CR_RXTRAINRANK1_RxVref_OFF (26) + #define DDRDATA_CR_RXTRAINRANK1_RxVref_WID ( 6) + #define DDRDATA_CR_RXTRAINRANK1_RxVref_MSK (0xFC000000) + #define DDRDATA_CR_RXTRAINRANK1_RxVref_MAX (0x0000003F) + +#define DDRDATA_CR_RXTRAINRANK2_REG (0x00003608) + #define DDRDATA_CR_RXTRAINRANK2_RxRcvEnPi_OFF ( 0) + #define DDRDATA_CR_RXTRAINRANK2_RxRcvEnPi_WID ( 9) + #define DDRDATA_CR_RXTRAINRANK2_RxRcvEnPi_MSK (0x000001FF) + #define DDRDATA_CR_RXTRAINRANK2_RxRcvEnPi_MAX (0x000001FF) + #define DDRDATA_CR_RXTRAINRANK2_RxDqsPPi_OFF ( 9) + #define DDRDATA_CR_RXTRAINRANK2_RxDqsPPi_WID ( 6) + #define DDRDATA_CR_RXTRAINRANK2_RxDqsPPi_MSK (0x00007E00) + #define DDRDATA_CR_RXTRAINRANK2_RxDqsPPi_MAX (0x0000003F) + #define DDRDATA_CR_RXTRAINRANK2_RxEq_OFF (15) + #define DDRDATA_CR_RXTRAINRANK2_RxEq_WID ( 5) + #define DDRDATA_CR_RXTRAINRANK2_RxEq_MSK (0x000F8000) + #define DDRDATA_CR_RXTRAINRANK2_RxEq_MAX (0x0000001F) + #define DDRDATA_CR_RXTRAINRANK2_RxDqsNPi_OFF (20) + #define DDRDATA_CR_RXTRAINRANK2_RxDqsNPi_WID ( 6) + #define DDRDATA_CR_RXTRAINRANK2_RxDqsNPi_MSK (0x03F00000) + #define DDRDATA_CR_RXTRAINRANK2_RxDqsNPi_MAX (0x0000003F) + #define DDRDATA_CR_RXTRAINRANK2_RxVref_OFF (26) + #define DDRDATA_CR_RXTRAINRANK2_RxVref_WID ( 6) + #define DDRDATA_CR_RXTRAINRANK2_RxVref_MSK (0xFC000000) + #define DDRDATA_CR_RXTRAINRANK2_RxVref_MAX (0x0000003F) + +#define DDRDATA_CR_RXTRAINRANK3_REG (0x0000360C) + #define DDRDATA_CR_RXTRAINRANK3_RxRcvEnPi_OFF ( 0) + #define DDRDATA_CR_RXTRAINRANK3_RxRcvEnPi_WID ( 9) + #define DDRDATA_CR_RXTRAINRANK3_RxRcvEnPi_MSK (0x000001FF) + #define DDRDATA_CR_RXTRAINRANK3_RxRcvEnPi_MAX (0x000001FF) + #define DDRDATA_CR_RXTRAINRANK3_RxDqsPPi_OFF ( 9) + #define DDRDATA_CR_RXTRAINRANK3_RxDqsPPi_WID ( 6) + #define DDRDATA_CR_RXTRAINRANK3_RxDqsPPi_MSK (0x00007E00) + #define DDRDATA_CR_RXTRAINRANK3_RxDqsPPi_MAX (0x0000003F) + #define DDRDATA_CR_RXTRAINRANK3_RxEq_OFF (15) + #define DDRDATA_CR_RXTRAINRANK3_RxEq_WID ( 5) + #define DDRDATA_CR_RXTRAINRANK3_RxEq_MSK (0x000F8000) + #define DDRDATA_CR_RXTRAINRANK3_RxEq_MAX (0x0000001F) + #define DDRDATA_CR_RXTRAINRANK3_RxDqsNPi_OFF (20) + #define DDRDATA_CR_RXTRAINRANK3_RxDqsNPi_WID ( 6) + #define DDRDATA_CR_RXTRAINRANK3_RxDqsNPi_MSK (0x03F00000) + #define DDRDATA_CR_RXTRAINRANK3_RxDqsNPi_MAX (0x0000003F) + #define DDRDATA_CR_RXTRAINRANK3_RxVref_OFF (26) + #define DDRDATA_CR_RXTRAINRANK3_RxVref_WID ( 6) + #define DDRDATA_CR_RXTRAINRANK3_RxVref_MSK (0xFC000000) + #define DDRDATA_CR_RXTRAINRANK3_RxVref_MAX (0x0000003F) + +#define DDRDATA_CR_RXPERBITRANK0_REG (0x00003610) + #define DDRDATA_CR_RXPERBITRANK0_Lane0_OFF ( 0) + #define DDRDATA_CR_RXPERBITRANK0_Lane0_WID ( 4) + #define DDRDATA_CR_RXPERBITRANK0_Lane0_MSK (0x0000000F) + #define DDRDATA_CR_RXPERBITRANK0_Lane0_MAX (0x0000000F) + #define DDRDATA_CR_RXPERBITRANK0_Lane1_OFF ( 4) + #define DDRDATA_CR_RXPERBITRANK0_Lane1_WID ( 4) + #define DDRDATA_CR_RXPERBITRANK0_Lane1_MSK (0x000000F0) + #define DDRDATA_CR_RXPERBITRANK0_Lane1_MAX (0x0000000F) + #define DDRDATA_CR_RXPERBITRANK0_Lane2_OFF ( 8) + #define DDRDATA_CR_RXPERBITRANK0_Lane2_WID ( 4) + #define DDRDATA_CR_RXPERBITRANK0_Lane2_MSK (0x00000F00) + #define DDRDATA_CR_RXPERBITRANK0_Lane2_MAX (0x0000000F) + #define DDRDATA_CR_RXPERBITRANK0_Lane3_OFF (12) + #define DDRDATA_CR_RXPERBITRANK0_Lane3_WID ( 4) + #define DDRDATA_CR_RXPERBITRANK0_Lane3_MSK (0x0000F000) + #define DDRDATA_CR_RXPERBITRANK0_Lane3_MAX (0x0000000F) + #define DDRDATA_CR_RXPERBITRANK0_Lane4_OFF (16) + #define DDRDATA_CR_RXPERBITRANK0_Lane4_WID ( 4) + #define DDRDATA_CR_RXPERBITRANK0_Lane4_MSK (0x000F0000) + #define DDRDATA_CR_RXPERBITRANK0_Lane4_MAX (0x0000000F) + #define DDRDATA_CR_RXPERBITRANK0_Lane5_OFF (20) + #define DDRDATA_CR_RXPERBITRANK0_Lane5_WID ( 4) + #define DDRDATA_CR_RXPERBITRANK0_Lane5_MSK (0x00F00000) + #define DDRDATA_CR_RXPERBITRANK0_Lane5_MAX (0x0000000F) + #define DDRDATA_CR_RXPERBITRANK0_Lane6_OFF (24) + #define DDRDATA_CR_RXPERBITRANK0_Lane6_WID ( 4) + #define DDRDATA_CR_RXPERBITRANK0_Lane6_MSK (0x0F000000) + #define DDRDATA_CR_RXPERBITRANK0_Lane6_MAX (0x0000000F) + #define DDRDATA_CR_RXPERBITRANK0_Lane7_OFF (28) + #define DDRDATA_CR_RXPERBITRANK0_Lane7_WID ( 4) + #define DDRDATA_CR_RXPERBITRANK0_Lane7_MSK (0xF0000000) + #define DDRDATA_CR_RXPERBITRANK0_Lane7_MAX (0x0000000F) + +#define DDRDATA_CR_RXPERBITRANK1_REG (0x00003614) + #define DDRDATA_CR_RXPERBITRANK1_Lane0_OFF ( 0) + #define DDRDATA_CR_RXPERBITRANK1_Lane0_WID ( 4) + #define DDRDATA_CR_RXPERBITRANK1_Lane0_MSK (0x0000000F) + #define DDRDATA_CR_RXPERBITRANK1_Lane0_MAX (0x0000000F) + #define DDRDATA_CR_RXPERBITRANK1_Lane1_OFF ( 4) + #define DDRDATA_CR_RXPERBITRANK1_Lane1_WID ( 4) + #define DDRDATA_CR_RXPERBITRANK1_Lane1_MSK (0x000000F0) + #define DDRDATA_CR_RXPERBITRANK1_Lane1_MAX (0x0000000F) + #define DDRDATA_CR_RXPERBITRANK1_Lane2_OFF ( 8) + #define DDRDATA_CR_RXPERBITRANK1_Lane2_WID ( 4) + #define DDRDATA_CR_RXPERBITRANK1_Lane2_MSK (0x00000F00) + #define DDRDATA_CR_RXPERBITRANK1_Lane2_MAX (0x0000000F) + #define DDRDATA_CR_RXPERBITRANK1_Lane3_OFF (12) + #define DDRDATA_CR_RXPERBITRANK1_Lane3_WID ( 4) + #define DDRDATA_CR_RXPERBITRANK1_Lane3_MSK (0x0000F000) + #define DDRDATA_CR_RXPERBITRANK1_Lane3_MAX (0x0000000F) + #define DDRDATA_CR_RXPERBITRANK1_Lane4_OFF (16) + #define DDRDATA_CR_RXPERBITRANK1_Lane4_WID ( 4) + #define DDRDATA_CR_RXPERBITRANK1_Lane4_MSK (0x000F0000) + #define DDRDATA_CR_RXPERBITRANK1_Lane4_MAX (0x0000000F) + #define DDRDATA_CR_RXPERBITRANK1_Lane5_OFF (20) + #define DDRDATA_CR_RXPERBITRANK1_Lane5_WID ( 4) + #define DDRDATA_CR_RXPERBITRANK1_Lane5_MSK (0x00F00000) + #define DDRDATA_CR_RXPERBITRANK1_Lane5_MAX (0x0000000F) + #define DDRDATA_CR_RXPERBITRANK1_Lane6_OFF (24) + #define DDRDATA_CR_RXPERBITRANK1_Lane6_WID ( 4) + #define DDRDATA_CR_RXPERBITRANK1_Lane6_MSK (0x0F000000) + #define DDRDATA_CR_RXPERBITRANK1_Lane6_MAX (0x0000000F) + #define DDRDATA_CR_RXPERBITRANK1_Lane7_OFF (28) + #define DDRDATA_CR_RXPERBITRANK1_Lane7_WID ( 4) + #define DDRDATA_CR_RXPERBITRANK1_Lane7_MSK (0xF0000000) + #define DDRDATA_CR_RXPERBITRANK1_Lane7_MAX (0x0000000F) + +#define DDRDATA_CR_RXPERBITRANK2_REG (0x00003618) + #define DDRDATA_CR_RXPERBITRANK2_Lane0_OFF ( 0) + #define DDRDATA_CR_RXPERBITRANK2_Lane0_WID ( 4) + #define DDRDATA_CR_RXPERBITRANK2_Lane0_MSK (0x0000000F) + #define DDRDATA_CR_RXPERBITRANK2_Lane0_MAX (0x0000000F) + #define DDRDATA_CR_RXPERBITRANK2_Lane1_OFF ( 4) + #define DDRDATA_CR_RXPERBITRANK2_Lane1_WID ( 4) + #define DDRDATA_CR_RXPERBITRANK2_Lane1_MSK (0x000000F0) + #define DDRDATA_CR_RXPERBITRANK2_Lane1_MAX (0x0000000F) + #define DDRDATA_CR_RXPERBITRANK2_Lane2_OFF ( 8) + #define DDRDATA_CR_RXPERBITRANK2_Lane2_WID ( 4) + #define DDRDATA_CR_RXPERBITRANK2_Lane2_MSK (0x00000F00) + #define DDRDATA_CR_RXPERBITRANK2_Lane2_MAX (0x0000000F) + #define DDRDATA_CR_RXPERBITRANK2_Lane3_OFF (12) + #define DDRDATA_CR_RXPERBITRANK2_Lane3_WID ( 4) + #define DDRDATA_CR_RXPERBITRANK2_Lane3_MSK (0x0000F000) + #define DDRDATA_CR_RXPERBITRANK2_Lane3_MAX (0x0000000F) + #define DDRDATA_CR_RXPERBITRANK2_Lane4_OFF (16) + #define DDRDATA_CR_RXPERBITRANK2_Lane4_WID ( 4) + #define DDRDATA_CR_RXPERBITRANK2_Lane4_MSK (0x000F0000) + #define DDRDATA_CR_RXPERBITRANK2_Lane4_MAX (0x0000000F) + #define DDRDATA_CR_RXPERBITRANK2_Lane5_OFF (20) + #define DDRDATA_CR_RXPERBITRANK2_Lane5_WID ( 4) + #define DDRDATA_CR_RXPERBITRANK2_Lane5_MSK (0x00F00000) + #define DDRDATA_CR_RXPERBITRANK2_Lane5_MAX (0x0000000F) + #define DDRDATA_CR_RXPERBITRANK2_Lane6_OFF (24) + #define DDRDATA_CR_RXPERBITRANK2_Lane6_WID ( 4) + #define DDRDATA_CR_RXPERBITRANK2_Lane6_MSK (0x0F000000) + #define DDRDATA_CR_RXPERBITRANK2_Lane6_MAX (0x0000000F) + #define DDRDATA_CR_RXPERBITRANK2_Lane7_OFF (28) + #define DDRDATA_CR_RXPERBITRANK2_Lane7_WID ( 4) + #define DDRDATA_CR_RXPERBITRANK2_Lane7_MSK (0xF0000000) + #define DDRDATA_CR_RXPERBITRANK2_Lane7_MAX (0x0000000F) + +#define DDRDATA_CR_RXPERBITRANK3_REG (0x0000361C) + #define DDRDATA_CR_RXPERBITRANK3_Lane0_OFF ( 0) + #define DDRDATA_CR_RXPERBITRANK3_Lane0_WID ( 4) + #define DDRDATA_CR_RXPERBITRANK3_Lane0_MSK (0x0000000F) + #define DDRDATA_CR_RXPERBITRANK3_Lane0_MAX (0x0000000F) + #define DDRDATA_CR_RXPERBITRANK3_Lane1_OFF ( 4) + #define DDRDATA_CR_RXPERBITRANK3_Lane1_WID ( 4) + #define DDRDATA_CR_RXPERBITRANK3_Lane1_MSK (0x000000F0) + #define DDRDATA_CR_RXPERBITRANK3_Lane1_MAX (0x0000000F) + #define DDRDATA_CR_RXPERBITRANK3_Lane2_OFF ( 8) + #define DDRDATA_CR_RXPERBITRANK3_Lane2_WID ( 4) + #define DDRDATA_CR_RXPERBITRANK3_Lane2_MSK (0x00000F00) + #define DDRDATA_CR_RXPERBITRANK3_Lane2_MAX (0x0000000F) + #define DDRDATA_CR_RXPERBITRANK3_Lane3_OFF (12) + #define DDRDATA_CR_RXPERBITRANK3_Lane3_WID ( 4) + #define DDRDATA_CR_RXPERBITRANK3_Lane3_MSK (0x0000F000) + #define DDRDATA_CR_RXPERBITRANK3_Lane3_MAX (0x0000000F) + #define DDRDATA_CR_RXPERBITRANK3_Lane4_OFF (16) + #define DDRDATA_CR_RXPERBITRANK3_Lane4_WID ( 4) + #define DDRDATA_CR_RXPERBITRANK3_Lane4_MSK (0x000F0000) + #define DDRDATA_CR_RXPERBITRANK3_Lane4_MAX (0x0000000F) + #define DDRDATA_CR_RXPERBITRANK3_Lane5_OFF (20) + #define DDRDATA_CR_RXPERBITRANK3_Lane5_WID ( 4) + #define DDRDATA_CR_RXPERBITRANK3_Lane5_MSK (0x00F00000) + #define DDRDATA_CR_RXPERBITRANK3_Lane5_MAX (0x0000000F) + #define DDRDATA_CR_RXPERBITRANK3_Lane6_OFF (24) + #define DDRDATA_CR_RXPERBITRANK3_Lane6_WID ( 4) + #define DDRDATA_CR_RXPERBITRANK3_Lane6_MSK (0x0F000000) + #define DDRDATA_CR_RXPERBITRANK3_Lane6_MAX (0x0000000F) + #define DDRDATA_CR_RXPERBITRANK3_Lane7_OFF (28) + #define DDRDATA_CR_RXPERBITRANK3_Lane7_WID ( 4) + #define DDRDATA_CR_RXPERBITRANK3_Lane7_MSK (0xF0000000) + #define DDRDATA_CR_RXPERBITRANK3_Lane7_MAX (0x0000000F) + +#define DDRDATA_CR_TXTRAINRANK0_REG (0x00003620) + #define DDRDATA_CR_TXTRAINRANK0_TxDqDelay_OFF ( 0) + #define DDRDATA_CR_TXTRAINRANK0_TxDqDelay_WID ( 9) + #define DDRDATA_CR_TXTRAINRANK0_TxDqDelay_MSK (0x000001FF) + #define DDRDATA_CR_TXTRAINRANK0_TxDqDelay_MAX (0x000001FF) + #define DDRDATA_CR_TXTRAINRANK0_TxDqsDelay_OFF ( 9) + #define DDRDATA_CR_TXTRAINRANK0_TxDqsDelay_WID ( 9) + #define DDRDATA_CR_TXTRAINRANK0_TxDqsDelay_MSK (0x0003FE00) + #define DDRDATA_CR_TXTRAINRANK0_TxDqsDelay_MAX (0x000001FF) + #define DDRDATA_CR_TXTRAINRANK0_Spare0_OFF (18) + #define DDRDATA_CR_TXTRAINRANK0_Spare0_WID ( 2) + #define DDRDATA_CR_TXTRAINRANK0_Spare0_MSK (0x000C0000) + #define DDRDATA_CR_TXTRAINRANK0_Spare0_MAX (0x00000003) + #define DDRDATA_CR_TXTRAINRANK0_TxEqualization_OFF (20) + #define DDRDATA_CR_TXTRAINRANK0_TxEqualization_WID ( 6) + #define DDRDATA_CR_TXTRAINRANK0_TxEqualization_MSK (0x03F00000) + #define DDRDATA_CR_TXTRAINRANK0_TxEqualization_MAX (0x0000003F) + #define DDRDATA_CR_TXTRAINRANK0_Spare1_OFF (26) + #define DDRDATA_CR_TXTRAINRANK0_Spare1_WID ( 6) + #define DDRDATA_CR_TXTRAINRANK0_Spare1_MSK (0xFC000000) + #define DDRDATA_CR_TXTRAINRANK0_Spare1_MAX (0x0000003F) + +#define DDRDATA_CR_TXTRAINRANK1_REG (0x00003624) + #define DDRDATA_CR_TXTRAINRANK1_TxDqDelay_OFF ( 0) + #define DDRDATA_CR_TXTRAINRANK1_TxDqDelay_WID ( 9) + #define DDRDATA_CR_TXTRAINRANK1_TxDqDelay_MSK (0x000001FF) + #define DDRDATA_CR_TXTRAINRANK1_TxDqDelay_MAX (0x000001FF) + #define DDRDATA_CR_TXTRAINRANK1_TxDqsDelay_OFF ( 9) + #define DDRDATA_CR_TXTRAINRANK1_TxDqsDelay_WID ( 9) + #define DDRDATA_CR_TXTRAINRANK1_TxDqsDelay_MSK (0x0003FE00) + #define DDRDATA_CR_TXTRAINRANK1_TxDqsDelay_MAX (0x000001FF) + #define DDRDATA_CR_TXTRAINRANK1_Spare0_OFF (18) + #define DDRDATA_CR_TXTRAINRANK1_Spare0_WID ( 2) + #define DDRDATA_CR_TXTRAINRANK1_Spare0_MSK (0x000C0000) + #define DDRDATA_CR_TXTRAINRANK1_Spare0_MAX (0x00000003) + #define DDRDATA_CR_TXTRAINRANK1_TxEqualization_OFF (20) + #define DDRDATA_CR_TXTRAINRANK1_TxEqualization_WID ( 6) + #define DDRDATA_CR_TXTRAINRANK1_TxEqualization_MSK (0x03F00000) + #define DDRDATA_CR_TXTRAINRANK1_TxEqualization_MAX (0x0000003F) + #define DDRDATA_CR_TXTRAINRANK1_Spare1_OFF (26) + #define DDRDATA_CR_TXTRAINRANK1_Spare1_WID ( 6) + #define DDRDATA_CR_TXTRAINRANK1_Spare1_MSK (0xFC000000) + #define DDRDATA_CR_TXTRAINRANK1_Spare1_MAX (0x0000003F) + +#define DDRDATA_CR_TXTRAINRANK2_REG (0x00003628) + #define DDRDATA_CR_TXTRAINRANK2_TxDqDelay_OFF ( 0) + #define DDRDATA_CR_TXTRAINRANK2_TxDqDelay_WID ( 9) + #define DDRDATA_CR_TXTRAINRANK2_TxDqDelay_MSK (0x000001FF) + #define DDRDATA_CR_TXTRAINRANK2_TxDqDelay_MAX (0x000001FF) + #define DDRDATA_CR_TXTRAINRANK2_TxDqsDelay_OFF ( 9) + #define DDRDATA_CR_TXTRAINRANK2_TxDqsDelay_WID ( 9) + #define DDRDATA_CR_TXTRAINRANK2_TxDqsDelay_MSK (0x0003FE00) + #define DDRDATA_CR_TXTRAINRANK2_TxDqsDelay_MAX (0x000001FF) + #define DDRDATA_CR_TXTRAINRANK2_Spare0_OFF (18) + #define DDRDATA_CR_TXTRAINRANK2_Spare0_WID ( 2) + #define DDRDATA_CR_TXTRAINRANK2_Spare0_MSK (0x000C0000) + #define DDRDATA_CR_TXTRAINRANK2_Spare0_MAX (0x00000003) + #define DDRDATA_CR_TXTRAINRANK2_TxEqualization_OFF (20) + #define DDRDATA_CR_TXTRAINRANK2_TxEqualization_WID ( 6) + #define DDRDATA_CR_TXTRAINRANK2_TxEqualization_MSK (0x03F00000) + #define DDRDATA_CR_TXTRAINRANK2_TxEqualization_MAX (0x0000003F) + #define DDRDATA_CR_TXTRAINRANK2_Spare1_OFF (26) + #define DDRDATA_CR_TXTRAINRANK2_Spare1_WID ( 6) + #define DDRDATA_CR_TXTRAINRANK2_Spare1_MSK (0xFC000000) + #define DDRDATA_CR_TXTRAINRANK2_Spare1_MAX (0x0000003F) + +#define DDRDATA_CR_TXTRAINRANK3_REG (0x0000362C) + #define DDRDATA_CR_TXTRAINRANK3_TxDqDelay_OFF ( 0) + #define DDRDATA_CR_TXTRAINRANK3_TxDqDelay_WID ( 9) + #define DDRDATA_CR_TXTRAINRANK3_TxDqDelay_MSK (0x000001FF) + #define DDRDATA_CR_TXTRAINRANK3_TxDqDelay_MAX (0x000001FF) + #define DDRDATA_CR_TXTRAINRANK3_TxDqsDelay_OFF ( 9) + #define DDRDATA_CR_TXTRAINRANK3_TxDqsDelay_WID ( 9) + #define DDRDATA_CR_TXTRAINRANK3_TxDqsDelay_MSK (0x0003FE00) + #define DDRDATA_CR_TXTRAINRANK3_TxDqsDelay_MAX (0x000001FF) + #define DDRDATA_CR_TXTRAINRANK3_Spare0_OFF (18) + #define DDRDATA_CR_TXTRAINRANK3_Spare0_WID ( 2) + #define DDRDATA_CR_TXTRAINRANK3_Spare0_MSK (0x000C0000) + #define DDRDATA_CR_TXTRAINRANK3_Spare0_MAX (0x00000003) + #define DDRDATA_CR_TXTRAINRANK3_TxEqualization_OFF (20) + #define DDRDATA_CR_TXTRAINRANK3_TxEqualization_WID ( 6) + #define DDRDATA_CR_TXTRAINRANK3_TxEqualization_MSK (0x03F00000) + #define DDRDATA_CR_TXTRAINRANK3_TxEqualization_MAX (0x0000003F) + #define DDRDATA_CR_TXTRAINRANK3_Spare1_OFF (26) + #define DDRDATA_CR_TXTRAINRANK3_Spare1_WID ( 6) + #define DDRDATA_CR_TXTRAINRANK3_Spare1_MSK (0xFC000000) + #define DDRDATA_CR_TXTRAINRANK3_Spare1_MAX (0x0000003F) + +#define DDRDATA_CR_TXPERBITRANK0_REG (0x00003630) + #define DDRDATA_CR_TXPERBITRANK0_Lane0_OFF ( 0) + #define DDRDATA_CR_TXPERBITRANK0_Lane0_WID ( 4) + #define DDRDATA_CR_TXPERBITRANK0_Lane0_MSK (0x0000000F) + #define DDRDATA_CR_TXPERBITRANK0_Lane0_MAX (0x0000000F) + #define DDRDATA_CR_TXPERBITRANK0_Lane1_OFF ( 4) + #define DDRDATA_CR_TXPERBITRANK0_Lane1_WID ( 4) + #define DDRDATA_CR_TXPERBITRANK0_Lane1_MSK (0x000000F0) + #define DDRDATA_CR_TXPERBITRANK0_Lane1_MAX (0x0000000F) + #define DDRDATA_CR_TXPERBITRANK0_Lane2_OFF ( 8) + #define DDRDATA_CR_TXPERBITRANK0_Lane2_WID ( 4) + #define DDRDATA_CR_TXPERBITRANK0_Lane2_MSK (0x00000F00) + #define DDRDATA_CR_TXPERBITRANK0_Lane2_MAX (0x0000000F) + #define DDRDATA_CR_TXPERBITRANK0_Lane3_OFF (12) + #define DDRDATA_CR_TXPERBITRANK0_Lane3_WID ( 4) + #define DDRDATA_CR_TXPERBITRANK0_Lane3_MSK (0x0000F000) + #define DDRDATA_CR_TXPERBITRANK0_Lane3_MAX (0x0000000F) + #define DDRDATA_CR_TXPERBITRANK0_Lane4_OFF (16) + #define DDRDATA_CR_TXPERBITRANK0_Lane4_WID ( 4) + #define DDRDATA_CR_TXPERBITRANK0_Lane4_MSK (0x000F0000) + #define DDRDATA_CR_TXPERBITRANK0_Lane4_MAX (0x0000000F) + #define DDRDATA_CR_TXPERBITRANK0_Lane5_OFF (20) + #define DDRDATA_CR_TXPERBITRANK0_Lane5_WID ( 4) + #define DDRDATA_CR_TXPERBITRANK0_Lane5_MSK (0x00F00000) + #define DDRDATA_CR_TXPERBITRANK0_Lane5_MAX (0x0000000F) + #define DDRDATA_CR_TXPERBITRANK0_Lane6_OFF (24) + #define DDRDATA_CR_TXPERBITRANK0_Lane6_WID ( 4) + #define DDRDATA_CR_TXPERBITRANK0_Lane6_MSK (0x0F000000) + #define DDRDATA_CR_TXPERBITRANK0_Lane6_MAX (0x0000000F) + #define DDRDATA_CR_TXPERBITRANK0_Lane7_OFF (28) + #define DDRDATA_CR_TXPERBITRANK0_Lane7_WID ( 4) + #define DDRDATA_CR_TXPERBITRANK0_Lane7_MSK (0xF0000000) + #define DDRDATA_CR_TXPERBITRANK0_Lane7_MAX (0x0000000F) + +#define DDRDATA_CR_TXPERBITRANK1_REG (0x00003634) + #define DDRDATA_CR_TXPERBITRANK1_Lane0_OFF ( 0) + #define DDRDATA_CR_TXPERBITRANK1_Lane0_WID ( 4) + #define DDRDATA_CR_TXPERBITRANK1_Lane0_MSK (0x0000000F) + #define DDRDATA_CR_TXPERBITRANK1_Lane0_MAX (0x0000000F) + #define DDRDATA_CR_TXPERBITRANK1_Lane1_OFF ( 4) + #define DDRDATA_CR_TXPERBITRANK1_Lane1_WID ( 4) + #define DDRDATA_CR_TXPERBITRANK1_Lane1_MSK (0x000000F0) + #define DDRDATA_CR_TXPERBITRANK1_Lane1_MAX (0x0000000F) + #define DDRDATA_CR_TXPERBITRANK1_Lane2_OFF ( 8) + #define DDRDATA_CR_TXPERBITRANK1_Lane2_WID ( 4) + #define DDRDATA_CR_TXPERBITRANK1_Lane2_MSK (0x00000F00) + #define DDRDATA_CR_TXPERBITRANK1_Lane2_MAX (0x0000000F) + #define DDRDATA_CR_TXPERBITRANK1_Lane3_OFF (12) + #define DDRDATA_CR_TXPERBITRANK1_Lane3_WID ( 4) + #define DDRDATA_CR_TXPERBITRANK1_Lane3_MSK (0x0000F000) + #define DDRDATA_CR_TXPERBITRANK1_Lane3_MAX (0x0000000F) + #define DDRDATA_CR_TXPERBITRANK1_Lane4_OFF (16) + #define DDRDATA_CR_TXPERBITRANK1_Lane4_WID ( 4) + #define DDRDATA_CR_TXPERBITRANK1_Lane4_MSK (0x000F0000) + #define DDRDATA_CR_TXPERBITRANK1_Lane4_MAX (0x0000000F) + #define DDRDATA_CR_TXPERBITRANK1_Lane5_OFF (20) + #define DDRDATA_CR_TXPERBITRANK1_Lane5_WID ( 4) + #define DDRDATA_CR_TXPERBITRANK1_Lane5_MSK (0x00F00000) + #define DDRDATA_CR_TXPERBITRANK1_Lane5_MAX (0x0000000F) + #define DDRDATA_CR_TXPERBITRANK1_Lane6_OFF (24) + #define DDRDATA_CR_TXPERBITRANK1_Lane6_WID ( 4) + #define DDRDATA_CR_TXPERBITRANK1_Lane6_MSK (0x0F000000) + #define DDRDATA_CR_TXPERBITRANK1_Lane6_MAX (0x0000000F) + #define DDRDATA_CR_TXPERBITRANK1_Lane7_OFF (28) + #define DDRDATA_CR_TXPERBITRANK1_Lane7_WID ( 4) + #define DDRDATA_CR_TXPERBITRANK1_Lane7_MSK (0xF0000000) + #define DDRDATA_CR_TXPERBITRANK1_Lane7_MAX (0x0000000F) + +#define DDRDATA_CR_TXPERBITRANK2_REG (0x00003638) + #define DDRDATA_CR_TXPERBITRANK2_Lane0_OFF ( 0) + #define DDRDATA_CR_TXPERBITRANK2_Lane0_WID ( 4) + #define DDRDATA_CR_TXPERBITRANK2_Lane0_MSK (0x0000000F) + #define DDRDATA_CR_TXPERBITRANK2_Lane0_MAX (0x0000000F) + #define DDRDATA_CR_TXPERBITRANK2_Lane1_OFF ( 4) + #define DDRDATA_CR_TXPERBITRANK2_Lane1_WID ( 4) + #define DDRDATA_CR_TXPERBITRANK2_Lane1_MSK (0x000000F0) + #define DDRDATA_CR_TXPERBITRANK2_Lane1_MAX (0x0000000F) + #define DDRDATA_CR_TXPERBITRANK2_Lane2_OFF ( 8) + #define DDRDATA_CR_TXPERBITRANK2_Lane2_WID ( 4) + #define DDRDATA_CR_TXPERBITRANK2_Lane2_MSK (0x00000F00) + #define DDRDATA_CR_TXPERBITRANK2_Lane2_MAX (0x0000000F) + #define DDRDATA_CR_TXPERBITRANK2_Lane3_OFF (12) + #define DDRDATA_CR_TXPERBITRANK2_Lane3_WID ( 4) + #define DDRDATA_CR_TXPERBITRANK2_Lane3_MSK (0x0000F000) + #define DDRDATA_CR_TXPERBITRANK2_Lane3_MAX (0x0000000F) + #define DDRDATA_CR_TXPERBITRANK2_Lane4_OFF (16) + #define DDRDATA_CR_TXPERBITRANK2_Lane4_WID ( 4) + #define DDRDATA_CR_TXPERBITRANK2_Lane4_MSK (0x000F0000) + #define DDRDATA_CR_TXPERBITRANK2_Lane4_MAX (0x0000000F) + #define DDRDATA_CR_TXPERBITRANK2_Lane5_OFF (20) + #define DDRDATA_CR_TXPERBITRANK2_Lane5_WID ( 4) + #define DDRDATA_CR_TXPERBITRANK2_Lane5_MSK (0x00F00000) + #define DDRDATA_CR_TXPERBITRANK2_Lane5_MAX (0x0000000F) + #define DDRDATA_CR_TXPERBITRANK2_Lane6_OFF (24) + #define DDRDATA_CR_TXPERBITRANK2_Lane6_WID ( 4) + #define DDRDATA_CR_TXPERBITRANK2_Lane6_MSK (0x0F000000) + #define DDRDATA_CR_TXPERBITRANK2_Lane6_MAX (0x0000000F) + #define DDRDATA_CR_TXPERBITRANK2_Lane7_OFF (28) + #define DDRDATA_CR_TXPERBITRANK2_Lane7_WID ( 4) + #define DDRDATA_CR_TXPERBITRANK2_Lane7_MSK (0xF0000000) + #define DDRDATA_CR_TXPERBITRANK2_Lane7_MAX (0x0000000F) + +#define DDRDATA_CR_TXPERBITRANK3_REG (0x0000363C) + #define DDRDATA_CR_TXPERBITRANK3_Lane0_OFF ( 0) + #define DDRDATA_CR_TXPERBITRANK3_Lane0_WID ( 4) + #define DDRDATA_CR_TXPERBITRANK3_Lane0_MSK (0x0000000F) + #define DDRDATA_CR_TXPERBITRANK3_Lane0_MAX (0x0000000F) + #define DDRDATA_CR_TXPERBITRANK3_Lane1_OFF ( 4) + #define DDRDATA_CR_TXPERBITRANK3_Lane1_WID ( 4) + #define DDRDATA_CR_TXPERBITRANK3_Lane1_MSK (0x000000F0) + #define DDRDATA_CR_TXPERBITRANK3_Lane1_MAX (0x0000000F) + #define DDRDATA_CR_TXPERBITRANK3_Lane2_OFF ( 8) + #define DDRDATA_CR_TXPERBITRANK3_Lane2_WID ( 4) + #define DDRDATA_CR_TXPERBITRANK3_Lane2_MSK (0x00000F00) + #define DDRDATA_CR_TXPERBITRANK3_Lane2_MAX (0x0000000F) + #define DDRDATA_CR_TXPERBITRANK3_Lane3_OFF (12) + #define DDRDATA_CR_TXPERBITRANK3_Lane3_WID ( 4) + #define DDRDATA_CR_TXPERBITRANK3_Lane3_MSK (0x0000F000) + #define DDRDATA_CR_TXPERBITRANK3_Lane3_MAX (0x0000000F) + #define DDRDATA_CR_TXPERBITRANK3_Lane4_OFF (16) + #define DDRDATA_CR_TXPERBITRANK3_Lane4_WID ( 4) + #define DDRDATA_CR_TXPERBITRANK3_Lane4_MSK (0x000F0000) + #define DDRDATA_CR_TXPERBITRANK3_Lane4_MAX (0x0000000F) + #define DDRDATA_CR_TXPERBITRANK3_Lane5_OFF (20) + #define DDRDATA_CR_TXPERBITRANK3_Lane5_WID ( 4) + #define DDRDATA_CR_TXPERBITRANK3_Lane5_MSK (0x00F00000) + #define DDRDATA_CR_TXPERBITRANK3_Lane5_MAX (0x0000000F) + #define DDRDATA_CR_TXPERBITRANK3_Lane6_OFF (24) + #define DDRDATA_CR_TXPERBITRANK3_Lane6_WID ( 4) + #define DDRDATA_CR_TXPERBITRANK3_Lane6_MSK (0x0F000000) + #define DDRDATA_CR_TXPERBITRANK3_Lane6_MAX (0x0000000F) + #define DDRDATA_CR_TXPERBITRANK3_Lane7_OFF (28) + #define DDRDATA_CR_TXPERBITRANK3_Lane7_WID ( 4) + #define DDRDATA_CR_TXPERBITRANK3_Lane7_MSK (0xF0000000) + #define DDRDATA_CR_TXPERBITRANK3_Lane7_MAX (0x0000000F) + +#define DDRDATA_CR_RCOMPDATA0_REG (0x00003640) + #define DDRDATA_CR_RCOMPDATA0_RcompDrvUp_OFF ( 0) + #define DDRDATA_CR_RCOMPDATA0_RcompDrvUp_WID ( 6) + #define DDRDATA_CR_RCOMPDATA0_RcompDrvUp_MSK (0x0000003F) + #define DDRDATA_CR_RCOMPDATA0_RcompDrvUp_MAX (0x0000003F) + #define DDRDATA_CR_RCOMPDATA0_Spare0_OFF ( 6) + #define DDRDATA_CR_RCOMPDATA0_Spare0_WID ( 3) + #define DDRDATA_CR_RCOMPDATA0_Spare0_MSK (0x000001C0) + #define DDRDATA_CR_RCOMPDATA0_Spare0_MAX (0x00000007) + #define DDRDATA_CR_RCOMPDATA0_RcompDrvDown_OFF ( 9) + #define DDRDATA_CR_RCOMPDATA0_RcompDrvDown_WID ( 6) + #define DDRDATA_CR_RCOMPDATA0_RcompDrvDown_MSK (0x00007E00) + #define DDRDATA_CR_RCOMPDATA0_RcompDrvDown_MAX (0x0000003F) + #define DDRDATA_CR_RCOMPDATA0_VTComp_OFF (15) + #define DDRDATA_CR_RCOMPDATA0_VTComp_WID ( 5) + #define DDRDATA_CR_RCOMPDATA0_VTComp_MSK (0x000F8000) + #define DDRDATA_CR_RCOMPDATA0_VTComp_MAX (0x0000001F) + #define DDRDATA_CR_RCOMPDATA0_TcoComp_OFF (20) + #define DDRDATA_CR_RCOMPDATA0_TcoComp_WID ( 6) + #define DDRDATA_CR_RCOMPDATA0_TcoComp_MSK (0x03F00000) + #define DDRDATA_CR_RCOMPDATA0_TcoComp_MAX (0x0000003F) + #define DDRDATA_CR_RCOMPDATA0_SlewRateComp_OFF (26) + #define DDRDATA_CR_RCOMPDATA0_SlewRateComp_WID ( 5) + #define DDRDATA_CR_RCOMPDATA0_SlewRateComp_MSK (0x7C000000) + #define DDRDATA_CR_RCOMPDATA0_SlewRateComp_MAX (0x0000001F) + #define DDRDATA_CR_RCOMPDATA0_Spare2_OFF (31) + #define DDRDATA_CR_RCOMPDATA0_Spare2_WID ( 1) + #define DDRDATA_CR_RCOMPDATA0_Spare2_MSK (0x80000000) + #define DDRDATA_CR_RCOMPDATA0_Spare2_MAX (0x00000001) + +#define DDRDATA_CR_RCOMPDATA1_REG (0x00003644) + #define DDRDATA_CR_RCOMPDATA1_RcompOdtUp_OFF ( 0) + #define DDRDATA_CR_RCOMPDATA1_RcompOdtUp_WID ( 6) + #define DDRDATA_CR_RCOMPDATA1_RcompOdtUp_MSK (0x0000003F) + #define DDRDATA_CR_RCOMPDATA1_RcompOdtUp_MAX (0x0000003F) + #define DDRDATA_CR_RCOMPDATA1_Spare0_OFF ( 6) + #define DDRDATA_CR_RCOMPDATA1_Spare0_WID ( 3) + #define DDRDATA_CR_RCOMPDATA1_Spare0_MSK (0x000001C0) + #define DDRDATA_CR_RCOMPDATA1_Spare0_MAX (0x00000007) + #define DDRDATA_CR_RCOMPDATA1_RcompOdtDown_OFF ( 9) + #define DDRDATA_CR_RCOMPDATA1_RcompOdtDown_WID ( 6) + #define DDRDATA_CR_RCOMPDATA1_RcompOdtDown_MSK (0x00007E00) + #define DDRDATA_CR_RCOMPDATA1_RcompOdtDown_MAX (0x0000003F) + #define DDRDATA_CR_RCOMPDATA1_Spare1_OFF (15) + #define DDRDATA_CR_RCOMPDATA1_Spare1_WID ( 1) + #define DDRDATA_CR_RCOMPDATA1_Spare1_MSK (0x00008000) + #define DDRDATA_CR_RCOMPDATA1_Spare1_MAX (0x00000001) + #define DDRDATA_CR_RCOMPDATA1_PanicDrvDn_OFF (16) + #define DDRDATA_CR_RCOMPDATA1_PanicDrvDn_WID ( 6) + #define DDRDATA_CR_RCOMPDATA1_PanicDrvDn_MSK (0x003F0000) + #define DDRDATA_CR_RCOMPDATA1_PanicDrvDn_MAX (0x0000003F) + #define DDRDATA_CR_RCOMPDATA1_PanicDrvUp_OFF (22) + #define DDRDATA_CR_RCOMPDATA1_PanicDrvUp_WID ( 6) + #define DDRDATA_CR_RCOMPDATA1_PanicDrvUp_MSK (0x0FC00000) + #define DDRDATA_CR_RCOMPDATA1_PanicDrvUp_MAX (0x0000003F) + #define DDRDATA_CR_RCOMPDATA1_LevelShifterComp_OFF (28) + #define DDRDATA_CR_RCOMPDATA1_LevelShifterComp_WID ( 3) + #define DDRDATA_CR_RCOMPDATA1_LevelShifterComp_MSK (0x70000000) + #define DDRDATA_CR_RCOMPDATA1_LevelShifterComp_MAX (0x00000007) + #define DDRDATA_CR_RCOMPDATA1_Spare2_OFF (31) + #define DDRDATA_CR_RCOMPDATA1_Spare2_WID ( 1) + #define DDRDATA_CR_RCOMPDATA1_Spare2_MSK (0x80000000) + #define DDRDATA_CR_RCOMPDATA1_Spare2_MAX (0x00000001) + +#define DDRDATA_CR_TXXTALK_REG (0x00003648) + #define DDRDATA_CR_TXXTALK_Lane0_OFF ( 0) + #define DDRDATA_CR_TXXTALK_Lane0_WID ( 4) + #define DDRDATA_CR_TXXTALK_Lane0_MSK (0x0000000F) + #define DDRDATA_CR_TXXTALK_Lane0_MAX (0x0000000F) + #define DDRDATA_CR_TXXTALK_Lane1_OFF ( 4) + #define DDRDATA_CR_TXXTALK_Lane1_WID ( 4) + #define DDRDATA_CR_TXXTALK_Lane1_MSK (0x000000F0) + #define DDRDATA_CR_TXXTALK_Lane1_MAX (0x0000000F) + #define DDRDATA_CR_TXXTALK_Lane2_OFF ( 8) + #define DDRDATA_CR_TXXTALK_Lane2_WID ( 4) + #define DDRDATA_CR_TXXTALK_Lane2_MSK (0x00000F00) + #define DDRDATA_CR_TXXTALK_Lane2_MAX (0x0000000F) + #define DDRDATA_CR_TXXTALK_Lane3_OFF (12) + #define DDRDATA_CR_TXXTALK_Lane3_WID ( 4) + #define DDRDATA_CR_TXXTALK_Lane3_MSK (0x0000F000) + #define DDRDATA_CR_TXXTALK_Lane3_MAX (0x0000000F) + #define DDRDATA_CR_TXXTALK_Lane4_OFF (16) + #define DDRDATA_CR_TXXTALK_Lane4_WID ( 4) + #define DDRDATA_CR_TXXTALK_Lane4_MSK (0x000F0000) + #define DDRDATA_CR_TXXTALK_Lane4_MAX (0x0000000F) + #define DDRDATA_CR_TXXTALK_Lane5_OFF (20) + #define DDRDATA_CR_TXXTALK_Lane5_WID ( 4) + #define DDRDATA_CR_TXXTALK_Lane5_MSK (0x00F00000) + #define DDRDATA_CR_TXXTALK_Lane5_MAX (0x0000000F) + #define DDRDATA_CR_TXXTALK_Lane6_OFF (24) + #define DDRDATA_CR_TXXTALK_Lane6_WID ( 4) + #define DDRDATA_CR_TXXTALK_Lane6_MSK (0x0F000000) + #define DDRDATA_CR_TXXTALK_Lane6_MAX (0x0000000F) + #define DDRDATA_CR_TXXTALK_Lane7_OFF (28) + #define DDRDATA_CR_TXXTALK_Lane7_WID ( 4) + #define DDRDATA_CR_TXXTALK_Lane7_MSK (0xF0000000) + #define DDRDATA_CR_TXXTALK_Lane7_MAX (0x0000000F) + +#define DDRDATA_CR_RXOFFSETVDQ_REG (0x0000364C) + #define DDRDATA_CR_RXOFFSETVDQ_Lane0_OFF ( 0) + #define DDRDATA_CR_RXOFFSETVDQ_Lane0_WID ( 4) + #define DDRDATA_CR_RXOFFSETVDQ_Lane0_MSK (0x0000000F) + #define DDRDATA_CR_RXOFFSETVDQ_Lane0_MAX (0x0000000F) + #define DDRDATA_CR_RXOFFSETVDQ_Lane1_OFF ( 4) + #define DDRDATA_CR_RXOFFSETVDQ_Lane1_WID ( 4) + #define DDRDATA_CR_RXOFFSETVDQ_Lane1_MSK (0x000000F0) + #define DDRDATA_CR_RXOFFSETVDQ_Lane1_MAX (0x0000000F) + #define DDRDATA_CR_RXOFFSETVDQ_Lane2_OFF ( 8) + #define DDRDATA_CR_RXOFFSETVDQ_Lane2_WID ( 4) + #define DDRDATA_CR_RXOFFSETVDQ_Lane2_MSK (0x00000F00) + #define DDRDATA_CR_RXOFFSETVDQ_Lane2_MAX (0x0000000F) + #define DDRDATA_CR_RXOFFSETVDQ_Lane3_OFF (12) + #define DDRDATA_CR_RXOFFSETVDQ_Lane3_WID ( 4) + #define DDRDATA_CR_RXOFFSETVDQ_Lane3_MSK (0x0000F000) + #define DDRDATA_CR_RXOFFSETVDQ_Lane3_MAX (0x0000000F) + #define DDRDATA_CR_RXOFFSETVDQ_Lane4_OFF (16) + #define DDRDATA_CR_RXOFFSETVDQ_Lane4_WID ( 4) + #define DDRDATA_CR_RXOFFSETVDQ_Lane4_MSK (0x000F0000) + #define DDRDATA_CR_RXOFFSETVDQ_Lane4_MAX (0x0000000F) + #define DDRDATA_CR_RXOFFSETVDQ_Lane5_OFF (20) + #define DDRDATA_CR_RXOFFSETVDQ_Lane5_WID ( 4) + #define DDRDATA_CR_RXOFFSETVDQ_Lane5_MSK (0x00F00000) + #define DDRDATA_CR_RXOFFSETVDQ_Lane5_MAX (0x0000000F) + #define DDRDATA_CR_RXOFFSETVDQ_Lane6_OFF (24) + #define DDRDATA_CR_RXOFFSETVDQ_Lane6_WID ( 4) + #define DDRDATA_CR_RXOFFSETVDQ_Lane6_MSK (0x0F000000) + #define DDRDATA_CR_RXOFFSETVDQ_Lane6_MAX (0x0000000F) + #define DDRDATA_CR_RXOFFSETVDQ_Lane7_OFF (28) + #define DDRDATA_CR_RXOFFSETVDQ_Lane7_WID ( 4) + #define DDRDATA_CR_RXOFFSETVDQ_Lane7_MSK (0xF0000000) + #define DDRDATA_CR_RXOFFSETVDQ_Lane7_MAX (0x0000000F) + +#define DDRDATA_CR_DDRDATARESERVED_REG (0x00003650) + #define DDRDATA_CR_DDRDATARESERVED_Spare_OFF ( 0) + #define DDRDATA_CR_DDRDATARESERVED_Spare_WID (32) + #define DDRDATA_CR_DDRDATARESERVED_Spare_MSK (0xFFFFFFFF) + #define DDRDATA_CR_DDRDATARESERVED_Spare_MAX (0xFFFFFFFF) + +#define DDRDATA_CR_DATATRAINFEEDBACK_REG (0x00003654) + #define DDRDATA_CR_DATATRAINFEEDBACK_DataTrainFeedback_OFF ( 0) + #define DDRDATA_CR_DATATRAINFEEDBACK_DataTrainFeedback_WID ( 9) + #define DDRDATA_CR_DATATRAINFEEDBACK_DataTrainFeedback_MSK (0x000001FF) + #define DDRDATA_CR_DATATRAINFEEDBACK_DataTrainFeedback_MAX (0x000001FF) + #define DDRDATA_CR_DATATRAINFEEDBACK_Spare_OFF ( 9) + #define DDRDATA_CR_DATATRAINFEEDBACK_Spare_WID (23) + #define DDRDATA_CR_DATATRAINFEEDBACK_Spare_MSK (0xFFFFFE00) + #define DDRDATA_CR_DATATRAINFEEDBACK_Spare_MAX (0x007FFFFF) + +#define DDRDATA_CR_DLLPITESTANDADC_REG (0x00003658) + #define DDRDATA_CR_DLLPITESTANDADC_RunTest_OFF ( 0) + #define DDRDATA_CR_DLLPITESTANDADC_RunTest_WID ( 1) + #define DDRDATA_CR_DLLPITESTANDADC_RunTest_MSK (0x00000001) + #define DDRDATA_CR_DLLPITESTANDADC_RunTest_MAX (0x00000001) + #define DDRDATA_CR_DLLPITESTANDADC_RunTest_DEF (0x00000000) + #define DDRDATA_CR_DLLPITESTANDADC_Load_OFF ( 1) + #define DDRDATA_CR_DLLPITESTANDADC_Load_WID ( 1) + #define DDRDATA_CR_DLLPITESTANDADC_Load_MSK (0x00000002) + #define DDRDATA_CR_DLLPITESTANDADC_Load_MAX (0x00000001) + #define DDRDATA_CR_DLLPITESTANDADC_Load_DEF (0x00000000) + #define DDRDATA_CR_DLLPITESTANDADC_ModeHVM_OFF ( 2) + #define DDRDATA_CR_DLLPITESTANDADC_ModeHVM_WID ( 1) + #define DDRDATA_CR_DLLPITESTANDADC_ModeHVM_MSK (0x00000004) + #define DDRDATA_CR_DLLPITESTANDADC_ModeHVM_MAX (0x00000001) + #define DDRDATA_CR_DLLPITESTANDADC_ModeHVM_DEF (0x00000000) + #define DDRDATA_CR_DLLPITESTANDADC_ModeDV_OFF ( 3) + #define DDRDATA_CR_DLLPITESTANDADC_ModeDV_WID ( 1) + #define DDRDATA_CR_DLLPITESTANDADC_ModeDV_MSK (0x00000008) + #define DDRDATA_CR_DLLPITESTANDADC_ModeDV_MAX (0x00000001) + #define DDRDATA_CR_DLLPITESTANDADC_ModeDV_DEF (0x00000000) + #define DDRDATA_CR_DLLPITESTANDADC_ModeADC_OFF ( 4) + #define DDRDATA_CR_DLLPITESTANDADC_ModeADC_WID ( 1) + #define DDRDATA_CR_DLLPITESTANDADC_ModeADC_MSK (0x00000010) + #define DDRDATA_CR_DLLPITESTANDADC_ModeADC_MAX (0x00000001) + #define DDRDATA_CR_DLLPITESTANDADC_ModeADC_DEF (0x00000000) + #define DDRDATA_CR_DLLPITESTANDADC_LoadCount_OFF ( 5) + #define DDRDATA_CR_DLLPITESTANDADC_LoadCount_WID (10) + #define DDRDATA_CR_DLLPITESTANDADC_LoadCount_MSK (0x00007FE0) + #define DDRDATA_CR_DLLPITESTANDADC_LoadCount_MAX (0x000003FF) + #define DDRDATA_CR_DLLPITESTANDADC_CountStatus_OFF (15) + #define DDRDATA_CR_DLLPITESTANDADC_CountStatus_WID (10) + #define DDRDATA_CR_DLLPITESTANDADC_CountStatus_MSK (0x01FF8000) + #define DDRDATA_CR_DLLPITESTANDADC_CountStatus_MAX (0x000003FF) + #define DDRDATA_CR_DLLPITESTANDADC_CountStatus_DEF (0x00000000) + #define DDRDATA_CR_DLLPITESTANDADC_Spare_OFF (25) + #define DDRDATA_CR_DLLPITESTANDADC_Spare_WID ( 7) + #define DDRDATA_CR_DLLPITESTANDADC_Spare_MSK (0xFE000000) + #define DDRDATA_CR_DLLPITESTANDADC_Spare_MAX (0x0000007F) + +#define DDRDATA_CR_DDRCRDATAOFFSETCOMP_REG (0x0000365C) + #define DDRDATA_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_OFF ( 0) + #define DDRDATA_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_WID ( 6) + #define DDRDATA_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MSK (0x0000003F) + #define DDRDATA_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MAX (0x0000003F) + #define DDRDATA_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_DEF (0x00000000) + #define DDRDATA_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_OFF ( 6) + #define DDRDATA_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_WID ( 6) + #define DDRDATA_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MSK (0x00000FC0) + #define DDRDATA_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MAX (0x0000003F) + #define DDRDATA_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_DEF (0x00000000) + #define DDRDATA_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_OFF (12) + #define DDRDATA_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_WID ( 5) + #define DDRDATA_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MSK (0x0001F000) + #define DDRDATA_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MAX (0x0000001F) + #define DDRDATA_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_DEF (0x00000000) + #define DDRDATA_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_OFF (17) + #define DDRDATA_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_WID ( 5) + #define DDRDATA_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MSK (0x003E0000) + #define DDRDATA_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MAX (0x0000001F) + #define DDRDATA_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_DEF (0x00000000) + #define DDRDATA_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_OFF (22) + #define DDRDATA_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_WID ( 5) + #define DDRDATA_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_MSK (0x07C00000) + #define DDRDATA_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_MAX (0x0000001F) + #define DDRDATA_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_DEF (0x00000000) + #define DDRDATA_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_OFF (27) + #define DDRDATA_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_WID ( 5) + #define DDRDATA_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MSK (0xF8000000) + #define DDRDATA_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MAX (0x0000001F) + #define DDRDATA_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_DEF (0x00000000) + +#define DDRDATA_CR_DDRCRDATACONTROL1_REG (0x00003660) + #define DDRDATA_CR_DDRCRDATACONTROL1_RefPi_OFF ( 0) + #define DDRDATA_CR_DDRCRDATACONTROL1_RefPi_WID ( 4) + #define DDRDATA_CR_DDRCRDATACONTROL1_RefPi_MSK (0x0000000F) + #define DDRDATA_CR_DDRCRDATACONTROL1_RefPi_MAX (0x0000000F) + #define DDRDATA_CR_DDRCRDATACONTROL1_RefPi_DEF (0x00000000) + #define DDRDATA_CR_DDRCRDATACONTROL1_DllMask_OFF ( 4) + #define DDRDATA_CR_DDRCRDATACONTROL1_DllMask_WID ( 2) + #define DDRDATA_CR_DDRCRDATACONTROL1_DllMask_MSK (0x00000030) + #define DDRDATA_CR_DDRCRDATACONTROL1_DllMask_MAX (0x00000003) + #define DDRDATA_CR_DDRCRDATACONTROL1_DllMask_DEF (0x00000000) + #define DDRDATA_CR_DDRCRDATACONTROL1_DllWeakLock_OFF ( 6) + #define DDRDATA_CR_DDRCRDATACONTROL1_DllWeakLock_WID ( 1) + #define DDRDATA_CR_DDRCRDATACONTROL1_DllWeakLock_MSK (0x00000040) + #define DDRDATA_CR_DDRCRDATACONTROL1_DllWeakLock_MAX (0x00000001) + #define DDRDATA_CR_DDRCRDATACONTROL1_DllWeakLock_DEF (0x00000000) + #define DDRDATA_CR_DDRCRDATACONTROL1_SdllSegmentDisable_OFF ( 7) + #define DDRDATA_CR_DDRCRDATACONTROL1_SdllSegmentDisable_WID ( 3) + #define DDRDATA_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MSK (0x00000380) + #define DDRDATA_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MAX (0x00000007) + #define DDRDATA_CR_DDRCRDATACONTROL1_SdllSegmentDisable_DEF (0x00000000) + #define DDRDATA_CR_DDRCRDATACONTROL1_RxBiasCtl_OFF (10) + #define DDRDATA_CR_DDRCRDATACONTROL1_RxBiasCtl_WID ( 3) + #define DDRDATA_CR_DDRCRDATACONTROL1_RxBiasCtl_MSK (0x00001C00) + #define DDRDATA_CR_DDRCRDATACONTROL1_RxBiasCtl_MAX (0x00000007) + #define DDRDATA_CR_DDRCRDATACONTROL1_RxBiasCtl_DEF (0x00000000) + #define DDRDATA_CR_DDRCRDATACONTROL1_OdtDelay_OFF (13) + #define DDRDATA_CR_DDRCRDATACONTROL1_OdtDelay_WID ( 4) + #define DDRDATA_CR_DDRCRDATACONTROL1_OdtDelay_MSK (0x0001E000) + #define DDRDATA_CR_DDRCRDATACONTROL1_OdtDelay_MAX (0x0000000F) + #define DDRDATA_CR_DDRCRDATACONTROL1_OdtDelay_DEF (0x00000000) + #define DDRDATA_CR_DDRCRDATACONTROL1_OdtDuration_OFF (17) + #define DDRDATA_CR_DDRCRDATACONTROL1_OdtDuration_WID ( 3) + #define DDRDATA_CR_DDRCRDATACONTROL1_OdtDuration_MSK (0x000E0000) + #define DDRDATA_CR_DDRCRDATACONTROL1_OdtDuration_MAX (0x00000007) + #define DDRDATA_CR_DDRCRDATACONTROL1_OdtDuration_DEF (0x00000000) + #define DDRDATA_CR_DDRCRDATACONTROL1_SenseAmpDelay_OFF (20) + #define DDRDATA_CR_DDRCRDATACONTROL1_SenseAmpDelay_WID ( 4) + #define DDRDATA_CR_DDRCRDATACONTROL1_SenseAmpDelay_MSK (0x00F00000) + #define DDRDATA_CR_DDRCRDATACONTROL1_SenseAmpDelay_MAX (0x0000000F) + #define DDRDATA_CR_DDRCRDATACONTROL1_SenseAmpDelay_DEF (0x00000000) + #define DDRDATA_CR_DDRCRDATACONTROL1_SenseAmpDuration_OFF (24) + #define DDRDATA_CR_DDRCRDATACONTROL1_SenseAmpDuration_WID ( 3) + #define DDRDATA_CR_DDRCRDATACONTROL1_SenseAmpDuration_MSK (0x07000000) + #define DDRDATA_CR_DDRCRDATACONTROL1_SenseAmpDuration_MAX (0x00000007) + #define DDRDATA_CR_DDRCRDATACONTROL1_SenseAmpDuration_DEF (0x00000000) + #define DDRDATA_CR_DDRCRDATACONTROL1_BurstEndODTDelay_OFF (27) + #define DDRDATA_CR_DDRCRDATACONTROL1_BurstEndODTDelay_WID ( 3) + #define DDRDATA_CR_DDRCRDATACONTROL1_BurstEndODTDelay_MSK (0x38000000) + #define DDRDATA_CR_DDRCRDATACONTROL1_BurstEndODTDelay_MAX (0x00000007) + #define DDRDATA_CR_DDRCRDATACONTROL1_BurstEndODTDelay_DEF (0x00000000) + #define DDRDATA_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_OFF (30) + #define DDRDATA_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_WID ( 1) + #define DDRDATA_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_MSK (0x40000000) + #define DDRDATA_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_MAX (0x00000001) + #define DDRDATA_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_DEF (0x00000000) + #define DDRDATA_CR_DDRCRDATACONTROL1_Rsvd1_OFF (31) + #define DDRDATA_CR_DDRCRDATACONTROL1_Rsvd1_WID ( 1) + #define DDRDATA_CR_DDRCRDATACONTROL1_Rsvd1_MSK (0x80000000) + #define DDRDATA_CR_DDRCRDATACONTROL1_Rsvd1_MAX (0x00000001) + #define DDRDATA_CR_DDRCRDATACONTROL1_Rsvd1_DEF (0x00000000) + +#define DDRDATA_CR_DDRCRDATACONTROL2_REG (0x00003664) + #define DDRDATA_CR_DDRCRDATACONTROL2_RxStaggerCtl_OFF ( 0) + #define DDRDATA_CR_DDRCRDATACONTROL2_RxStaggerCtl_WID ( 5) + #define DDRDATA_CR_DDRCRDATACONTROL2_RxStaggerCtl_MSK (0x0000001F) + #define DDRDATA_CR_DDRCRDATACONTROL2_RxStaggerCtl_MAX (0x0000001F) + #define DDRDATA_CR_DDRCRDATACONTROL2_RxStaggerCtl_DEF (0x00000000) + #define DDRDATA_CR_DDRCRDATACONTROL2_ForceBiasOn_OFF ( 5) + #define DDRDATA_CR_DDRCRDATACONTROL2_ForceBiasOn_WID ( 1) + #define DDRDATA_CR_DDRCRDATACONTROL2_ForceBiasOn_MSK (0x00000020) + #define DDRDATA_CR_DDRCRDATACONTROL2_ForceBiasOn_MAX (0x00000001) + #define DDRDATA_CR_DDRCRDATACONTROL2_ForceBiasOn_DEF (0x00000000) + #define DDRDATA_CR_DDRCRDATACONTROL2_ForceRxOn_OFF ( 6) + #define DDRDATA_CR_DDRCRDATACONTROL2_ForceRxOn_WID ( 1) + #define DDRDATA_CR_DDRCRDATACONTROL2_ForceRxOn_MSK (0x00000040) + #define DDRDATA_CR_DDRCRDATACONTROL2_ForceRxOn_MAX (0x00000001) + #define DDRDATA_CR_DDRCRDATACONTROL2_ForceRxOn_DEF (0x00000000) + #define DDRDATA_CR_DDRCRDATACONTROL2_LeakerComp_OFF ( 7) + #define DDRDATA_CR_DDRCRDATACONTROL2_LeakerComp_WID ( 2) + #define DDRDATA_CR_DDRCRDATACONTROL2_LeakerComp_MSK (0x00000180) + #define DDRDATA_CR_DDRCRDATACONTROL2_LeakerComp_MAX (0x00000003) + #define DDRDATA_CR_DDRCRDATACONTROL2_LeakerComp_DEF (0x00000000) + #define DDRDATA_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_OFF ( 9) + #define DDRDATA_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_WID ( 4) + #define DDRDATA_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_MSK (0x00001E00) + #define DDRDATA_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_MAX (0x0000000F) + #define DDRDATA_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_DEF (0x00000008) + #define DDRDATA_CR_DDRCRDATACONTROL2_RxClkStgNum_OFF (13) + #define DDRDATA_CR_DDRCRDATACONTROL2_RxClkStgNum_WID ( 5) + #define DDRDATA_CR_DDRCRDATACONTROL2_RxClkStgNum_MSK (0x0003E000) + #define DDRDATA_CR_DDRCRDATACONTROL2_RxClkStgNum_MAX (0x0000001F) + #define DDRDATA_CR_DDRCRDATACONTROL2_RxClkStgNum_DEF (0x00000011) + #define DDRDATA_CR_DDRCRDATACONTROL2_WlLongDelEn_OFF (18) + #define DDRDATA_CR_DDRCRDATACONTROL2_WlLongDelEn_WID ( 1) + #define DDRDATA_CR_DDRCRDATACONTROL2_WlLongDelEn_MSK (0x00040000) + #define DDRDATA_CR_DDRCRDATACONTROL2_WlLongDelEn_MAX (0x00000001) + #define DDRDATA_CR_DDRCRDATACONTROL2_WlLongDelEn_DEF (0x00000000) + #define DDRDATA_CR_DDRCRDATACONTROL2_Spare_OFF (19) + #define DDRDATA_CR_DDRCRDATACONTROL2_Spare_WID (13) + #define DDRDATA_CR_DDRCRDATACONTROL2_Spare_MSK (0xFFF80000) + #define DDRDATA_CR_DDRCRDATACONTROL2_Spare_MAX (0x00001FFF) + #define DDRDATA_CR_DDRCRDATACONTROL2_Spare_DEF (0x00000000) + +#define DDRDATA_CR_DDRCRVREFCONTROL_REG (0x00003668) + #define DDRDATA_CR_DDRCRVREFCONTROL_VrefCtl_OFF ( 0) + #define DDRDATA_CR_DDRCRVREFCONTROL_VrefCtl_WID (24) + #define DDRDATA_CR_DDRCRVREFCONTROL_VrefCtl_MSK (0x00FFFFFF) + #define DDRDATA_CR_DDRCRVREFCONTROL_VrefCtl_MAX (0x00FFFFFF) + #define DDRDATA_CR_DDRCRVREFCONTROL_VrefCtl_DEF (0x000E453A) + #define DDRDATA_CR_DDRCRVREFCONTROL_OutputCode_OFF (24) + #define DDRDATA_CR_DDRCRVREFCONTROL_OutputCode_WID ( 8) + #define DDRDATA_CR_DDRCRVREFCONTROL_OutputCode_MSK (0xFF000000) + #define DDRDATA_CR_DDRCRVREFCONTROL_OutputCode_MAX (0x000000FF) + #define DDRDATA_CR_DDRCRVREFCONTROL_OutputCode_DEF (0x00000000) + +#define DDRDATA_CR_DDRCRVSSHICONTROL_REG (0x0000366C) + #define DDRDATA_CR_DDRCRVSSHICONTROL_VssHiCtl_OFF ( 0) + #define DDRDATA_CR_DDRCRVSSHICONTROL_VssHiCtl_WID (24) + #define DDRDATA_CR_DDRCRVSSHICONTROL_VssHiCtl_MSK (0x00FFFFFF) + #define DDRDATA_CR_DDRCRVSSHICONTROL_VssHiCtl_MAX (0x00FFFFFF) + #define DDRDATA_CR_DDRCRVSSHICONTROL_VssHiCtl_DEF (0x004D8238) + #define DDRDATA_CR_DDRCRVSSHICONTROL_OutputCode_OFF (24) + #define DDRDATA_CR_DDRCRVSSHICONTROL_OutputCode_WID ( 8) + #define DDRDATA_CR_DDRCRVSSHICONTROL_OutputCode_MSK (0xFF000000) + #define DDRDATA_CR_DDRCRVSSHICONTROL_OutputCode_MAX (0x000000FF) + #define DDRDATA_CR_DDRCRVSSHICONTROL_OutputCode_DEF (0x00000000) + +#define DDRDATA_CR_DDRCRVSSHIORVREFCONTROL_REG (0x0000366C) + #define DDRDATA_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_OFF ( 0) + #define DDRDATA_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_WID (24) + #define DDRDATA_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_MSK (0x00FFFFFF) + #define DDRDATA_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_MAX (0x00FFFFFF) + #define DDRDATA_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_DEF (0x00000000) + #define DDRDATA_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_OFF (24) + #define DDRDATA_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_WID ( 8) + #define DDRDATA_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_MSK (0xFF000000) + #define DDRDATA_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_MAX (0x000000FF) + #define DDRDATA_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_DEF (0x00000000) + +#define DDRDATA_CR_DDRCRDATAOFFSETTRAIN_REG (0x00003670) + #define DDRDATA_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_OFF ( 0) + #define DDRDATA_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_WID ( 6) + #define DDRDATA_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MSK (0x0000003F) + #define DDRDATA_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MAX (0x0000003F) + #define DDRDATA_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_DEF (0x00000000) + #define DDRDATA_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_OFF ( 6) + #define DDRDATA_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_WID ( 6) + #define DDRDATA_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MSK (0x00000FC0) + #define DDRDATA_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MAX (0x0000003F) + #define DDRDATA_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_DEF (0x00000000) + #define DDRDATA_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_OFF (12) + #define DDRDATA_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_WID ( 6) + #define DDRDATA_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MSK (0x0003F000) + #define DDRDATA_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MAX (0x0000003F) + #define DDRDATA_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_DEF (0x00000000) + #define DDRDATA_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_OFF (18) + #define DDRDATA_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_WID ( 6) + #define DDRDATA_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MSK (0x00FC0000) + #define DDRDATA_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MAX (0x0000003F) + #define DDRDATA_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_DEF (0x00000000) + #define DDRDATA_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_OFF (24) + #define DDRDATA_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_WID ( 7) + #define DDRDATA_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MSK (0x7F000000) + #define DDRDATA_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MAX (0x0000007F) + #define DDRDATA_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_DEF (0x00000000) + #define DDRDATA_CR_DDRCRDATAOFFSETTRAIN_Spare_OFF (31) + #define DDRDATA_CR_DDRCRDATAOFFSETTRAIN_Spare_WID ( 1) + #define DDRDATA_CR_DDRCRDATAOFFSETTRAIN_Spare_MSK (0x80000000) + #define DDRDATA_CR_DDRCRDATAOFFSETTRAIN_Spare_MAX (0x00000001) + #define DDRDATA_CR_DDRCRDATAOFFSETTRAIN_Spare_DEF (0x00000000) + +#define DDRDATA_CR_DDRCRDATACONTROL0_REG (0x00003674) + #define DDRDATA_CR_DDRCRDATACONTROL0_RxTrainingMode_OFF ( 0) + #define DDRDATA_CR_DDRCRDATACONTROL0_RxTrainingMode_WID ( 1) + #define DDRDATA_CR_DDRCRDATACONTROL0_RxTrainingMode_MSK (0x00000001) + #define DDRDATA_CR_DDRCRDATACONTROL0_RxTrainingMode_MAX (0x00000001) + #define DDRDATA_CR_DDRCRDATACONTROL0_RxTrainingMode_DEF (0x00000000) + #define DDRDATA_CR_DDRCRDATACONTROL0_WLTrainingMode_OFF ( 1) + #define DDRDATA_CR_DDRCRDATACONTROL0_WLTrainingMode_WID ( 1) + #define DDRDATA_CR_DDRCRDATACONTROL0_WLTrainingMode_MSK (0x00000002) + #define DDRDATA_CR_DDRCRDATACONTROL0_WLTrainingMode_MAX (0x00000001) + #define DDRDATA_CR_DDRCRDATACONTROL0_WLTrainingMode_DEF (0x00000000) + #define DDRDATA_CR_DDRCRDATACONTROL0_RLTrainingMode_OFF ( 2) + #define DDRDATA_CR_DDRCRDATACONTROL0_RLTrainingMode_WID ( 1) + #define DDRDATA_CR_DDRCRDATACONTROL0_RLTrainingMode_MSK (0x00000004) + #define DDRDATA_CR_DDRCRDATACONTROL0_RLTrainingMode_MAX (0x00000001) + #define DDRDATA_CR_DDRCRDATACONTROL0_RLTrainingMode_DEF (0x00000000) + #define DDRDATA_CR_DDRCRDATACONTROL0_SenseampTrainingMode_OFF ( 3) + #define DDRDATA_CR_DDRCRDATACONTROL0_SenseampTrainingMode_WID ( 1) + #define DDRDATA_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MSK (0x00000008) + #define DDRDATA_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MAX (0x00000001) + #define DDRDATA_CR_DDRCRDATACONTROL0_SenseampTrainingMode_DEF (0x00000000) + #define DDRDATA_CR_DDRCRDATACONTROL0_TxOn_OFF ( 4) + #define DDRDATA_CR_DDRCRDATACONTROL0_TxOn_WID ( 1) + #define DDRDATA_CR_DDRCRDATACONTROL0_TxOn_MSK (0x00000010) + #define DDRDATA_CR_DDRCRDATACONTROL0_TxOn_MAX (0x00000001) + #define DDRDATA_CR_DDRCRDATACONTROL0_TxOn_DEF (0x00000000) + #define DDRDATA_CR_DDRCRDATACONTROL0_RfOn_OFF ( 5) + #define DDRDATA_CR_DDRCRDATACONTROL0_RfOn_WID ( 1) + #define DDRDATA_CR_DDRCRDATACONTROL0_RfOn_MSK (0x00000020) + #define DDRDATA_CR_DDRCRDATACONTROL0_RfOn_MAX (0x00000001) + #define DDRDATA_CR_DDRCRDATACONTROL0_RfOn_DEF (0x00000000) + #define DDRDATA_CR_DDRCRDATACONTROL0_RxPiOn_OFF ( 6) + #define DDRDATA_CR_DDRCRDATACONTROL0_RxPiOn_WID ( 1) + #define DDRDATA_CR_DDRCRDATACONTROL0_RxPiOn_MSK (0x00000040) + #define DDRDATA_CR_DDRCRDATACONTROL0_RxPiOn_MAX (0x00000001) + #define DDRDATA_CR_DDRCRDATACONTROL0_RxPiOn_DEF (0x00000000) + #define DDRDATA_CR_DDRCRDATACONTROL0_TxPiOn_OFF ( 7) + #define DDRDATA_CR_DDRCRDATACONTROL0_TxPiOn_WID ( 1) + #define DDRDATA_CR_DDRCRDATACONTROL0_TxPiOn_MSK (0x00000080) + #define DDRDATA_CR_DDRCRDATACONTROL0_TxPiOn_MAX (0x00000001) + #define DDRDATA_CR_DDRCRDATACONTROL0_TxPiOn_DEF (0x00000000) + #define DDRDATA_CR_DDRCRDATACONTROL0_InternalClocksOn_OFF ( 8) + #define DDRDATA_CR_DDRCRDATACONTROL0_InternalClocksOn_WID ( 1) + #define DDRDATA_CR_DDRCRDATACONTROL0_InternalClocksOn_MSK (0x00000100) + #define DDRDATA_CR_DDRCRDATACONTROL0_InternalClocksOn_MAX (0x00000001) + #define DDRDATA_CR_DDRCRDATACONTROL0_InternalClocksOn_DEF (0x00000000) + #define DDRDATA_CR_DDRCRDATACONTROL0_RepeaterClocksOn_OFF ( 9) + #define DDRDATA_CR_DDRCRDATACONTROL0_RepeaterClocksOn_WID ( 1) + #define DDRDATA_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MSK (0x00000200) + #define DDRDATA_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MAX (0x00000001) + #define DDRDATA_CR_DDRCRDATACONTROL0_RepeaterClocksOn_DEF (0x00000000) + #define DDRDATA_CR_DDRCRDATACONTROL0_TxDisable_OFF (10) + #define DDRDATA_CR_DDRCRDATACONTROL0_TxDisable_WID ( 1) + #define DDRDATA_CR_DDRCRDATACONTROL0_TxDisable_MSK (0x00000400) + #define DDRDATA_CR_DDRCRDATACONTROL0_TxDisable_MAX (0x00000001) + #define DDRDATA_CR_DDRCRDATACONTROL0_TxDisable_DEF (0x00000000) + #define DDRDATA_CR_DDRCRDATACONTROL0_RxDisable_OFF (11) + #define DDRDATA_CR_DDRCRDATACONTROL0_RxDisable_WID ( 1) + #define DDRDATA_CR_DDRCRDATACONTROL0_RxDisable_MSK (0x00000800) + #define DDRDATA_CR_DDRCRDATACONTROL0_RxDisable_MAX (0x00000001) + #define DDRDATA_CR_DDRCRDATACONTROL0_RxDisable_DEF (0x00000000) + #define DDRDATA_CR_DDRCRDATACONTROL0_TxLong_OFF (12) + #define DDRDATA_CR_DDRCRDATACONTROL0_TxLong_WID ( 1) + #define DDRDATA_CR_DDRCRDATACONTROL0_TxLong_MSK (0x00001000) + #define DDRDATA_CR_DDRCRDATACONTROL0_TxLong_MAX (0x00000001) + #define DDRDATA_CR_DDRCRDATACONTROL0_TxLong_DEF (0x00000000) + #define DDRDATA_CR_DDRCRDATACONTROL0_RxDqsCtle_OFF (13) + #define DDRDATA_CR_DDRCRDATACONTROL0_RxDqsCtle_WID ( 2) + #define DDRDATA_CR_DDRCRDATACONTROL0_RxDqsCtle_MSK (0x00006000) + #define DDRDATA_CR_DDRCRDATACONTROL0_RxDqsCtle_MAX (0x00000003) + #define DDRDATA_CR_DDRCRDATACONTROL0_RxDqsCtle_DEF (0x00000000) + #define DDRDATA_CR_DDRCRDATACONTROL0_RxReadPointer_OFF (15) + #define DDRDATA_CR_DDRCRDATACONTROL0_RxReadPointer_WID ( 3) + #define DDRDATA_CR_DDRCRDATACONTROL0_RxReadPointer_MSK (0x00038000) + #define DDRDATA_CR_DDRCRDATACONTROL0_RxReadPointer_MAX (0x00000007) + #define DDRDATA_CR_DDRCRDATACONTROL0_RxReadPointer_DEF (0x00000000) + #define DDRDATA_CR_DDRCRDATACONTROL0_DriverSegmentEnable_OFF (18) + #define DDRDATA_CR_DDRCRDATACONTROL0_DriverSegmentEnable_WID ( 1) + #define DDRDATA_CR_DDRCRDATACONTROL0_DriverSegmentEnable_MSK (0x00040000) + #define DDRDATA_CR_DDRCRDATACONTROL0_DriverSegmentEnable_MAX (0x00000001) + #define DDRDATA_CR_DDRCRDATACONTROL0_DriverSegmentEnable_DEF (0x00000000) + #define DDRDATA_CR_DDRCRDATACONTROL0_DataVccddqHi_OFF (19) + #define DDRDATA_CR_DDRCRDATACONTROL0_DataVccddqHi_WID ( 1) + #define DDRDATA_CR_DDRCRDATACONTROL0_DataVccddqHi_MSK (0x00080000) + #define DDRDATA_CR_DDRCRDATACONTROL0_DataVccddqHi_MAX (0x00000001) + #define DDRDATA_CR_DDRCRDATACONTROL0_DataVccddqHi_DEF (0x00000000) + #define DDRDATA_CR_DDRCRDATACONTROL0_ReadRFRd_OFF (20) + #define DDRDATA_CR_DDRCRDATACONTROL0_ReadRFRd_WID ( 1) + #define DDRDATA_CR_DDRCRDATACONTROL0_ReadRFRd_MSK (0x00100000) + #define DDRDATA_CR_DDRCRDATACONTROL0_ReadRFRd_MAX (0x00000001) + #define DDRDATA_CR_DDRCRDATACONTROL0_ReadRFRd_DEF (0x00000000) + #define DDRDATA_CR_DDRCRDATACONTROL0_ReadRFWr_OFF (21) + #define DDRDATA_CR_DDRCRDATACONTROL0_ReadRFWr_WID ( 1) + #define DDRDATA_CR_DDRCRDATACONTROL0_ReadRFWr_MSK (0x00200000) + #define DDRDATA_CR_DDRCRDATACONTROL0_ReadRFWr_MAX (0x00000001) + #define DDRDATA_CR_DDRCRDATACONTROL0_ReadRFWr_DEF (0x00000000) + #define DDRDATA_CR_DDRCRDATACONTROL0_ReadRFRank_OFF (22) + #define DDRDATA_CR_DDRCRDATACONTROL0_ReadRFRank_WID ( 2) + #define DDRDATA_CR_DDRCRDATACONTROL0_ReadRFRank_MSK (0x00C00000) + #define DDRDATA_CR_DDRCRDATACONTROL0_ReadRFRank_MAX (0x00000003) + #define DDRDATA_CR_DDRCRDATACONTROL0_ReadRFRank_DEF (0x00000000) + #define DDRDATA_CR_DDRCRDATACONTROL0_ForceOdtOn_OFF (24) + #define DDRDATA_CR_DDRCRDATACONTROL0_ForceOdtOn_WID ( 1) + #define DDRDATA_CR_DDRCRDATACONTROL0_ForceOdtOn_MSK (0x01000000) + #define DDRDATA_CR_DDRCRDATACONTROL0_ForceOdtOn_MAX (0x00000001) + #define DDRDATA_CR_DDRCRDATACONTROL0_ForceOdtOn_DEF (0x00000000) + #define DDRDATA_CR_DDRCRDATACONTROL0_OdtSampOff_OFF (25) + #define DDRDATA_CR_DDRCRDATACONTROL0_OdtSampOff_WID ( 1) + #define DDRDATA_CR_DDRCRDATACONTROL0_OdtSampOff_MSK (0x02000000) + #define DDRDATA_CR_DDRCRDATACONTROL0_OdtSampOff_MAX (0x00000001) + #define DDRDATA_CR_DDRCRDATACONTROL0_OdtSampOff_DEF (0x00000000) + #define DDRDATA_CR_DDRCRDATACONTROL0_DisableOdtStatic_OFF (26) + #define DDRDATA_CR_DDRCRDATACONTROL0_DisableOdtStatic_WID ( 1) + #define DDRDATA_CR_DDRCRDATACONTROL0_DisableOdtStatic_MSK (0x04000000) + #define DDRDATA_CR_DDRCRDATACONTROL0_DisableOdtStatic_MAX (0x00000001) + #define DDRDATA_CR_DDRCRDATACONTROL0_DisableOdtStatic_DEF (0x00000000) + #define DDRDATA_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_OFF (27) + #define DDRDATA_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_WID ( 1) + #define DDRDATA_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MSK (0x08000000) + #define DDRDATA_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MAX (0x00000001) + #define DDRDATA_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_DEF (0x00000000) + #define DDRDATA_CR_DDRCRDATACONTROL0_LPDDR_Mode_OFF (28) + #define DDRDATA_CR_DDRCRDATACONTROL0_LPDDR_Mode_WID ( 1) + #define DDRDATA_CR_DDRCRDATACONTROL0_LPDDR_Mode_MSK (0x10000000) + #define DDRDATA_CR_DDRCRDATACONTROL0_LPDDR_Mode_MAX (0x00000001) + #define DDRDATA_CR_DDRCRDATACONTROL0_LPDDR_Mode_DEF (0x00000000) + #define DDRDATA_CR_DDRCRDATACONTROL0_EnReadPreamble_OFF (29) + #define DDRDATA_CR_DDRCRDATACONTROL0_EnReadPreamble_WID ( 1) + #define DDRDATA_CR_DDRCRDATACONTROL0_EnReadPreamble_MSK (0x20000000) + #define DDRDATA_CR_DDRCRDATACONTROL0_EnReadPreamble_MAX (0x00000001) + #define DDRDATA_CR_DDRCRDATACONTROL0_EnReadPreamble_DEF (0x00000000) + #define DDRDATA_CR_DDRCRDATACONTROL0_OdtSampExtendEn_OFF (30) + #define DDRDATA_CR_DDRCRDATACONTROL0_OdtSampExtendEn_WID ( 1) + #define DDRDATA_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MSK (0x40000000) + #define DDRDATA_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MAX (0x00000001) + #define DDRDATA_CR_DDRCRDATACONTROL0_OdtSampExtendEn_DEF (0x00000000) + #define DDRDATA_CR_DDRCRDATACONTROL0_EarlyRleakEn_OFF (31) + #define DDRDATA_CR_DDRCRDATACONTROL0_EarlyRleakEn_WID ( 1) + #define DDRDATA_CR_DDRCRDATACONTROL0_EarlyRleakEn_MSK (0x80000000) + #define DDRDATA_CR_DDRCRDATACONTROL0_EarlyRleakEn_MAX (0x00000001) + #define DDRDATA_CR_DDRCRDATACONTROL0_EarlyRleakEn_DEF (0x00000000) + +#define DDRDATA_CR_DDRCRVREFADJUST1_REG (0x00003678) + #define DDRDATA_CR_DDRCRVREFADJUST1_CAVrefCtl_OFF ( 0) + #define DDRDATA_CR_DDRCRVREFADJUST1_CAVrefCtl_WID ( 7) + #define DDRDATA_CR_DDRCRVREFADJUST1_CAVrefCtl_MSK (0x0000007F) + #define DDRDATA_CR_DDRCRVREFADJUST1_CAVrefCtl_MAX (0x0000007F) + #define DDRDATA_CR_DDRCRVREFADJUST1_CAVrefCtl_DEF (0x00000000) + #define DDRDATA_CR_DDRCRVREFADJUST1_Ch1VrefCtl_OFF ( 7) + #define DDRDATA_CR_DDRCRVREFADJUST1_Ch1VrefCtl_WID ( 7) + #define DDRDATA_CR_DDRCRVREFADJUST1_Ch1VrefCtl_MSK (0x00003F80) + #define DDRDATA_CR_DDRCRVREFADJUST1_Ch1VrefCtl_MAX (0x0000007F) + #define DDRDATA_CR_DDRCRVREFADJUST1_Ch1VrefCtl_DEF (0x00000000) + #define DDRDATA_CR_DDRCRVREFADJUST1_Ch0VrefCtl_OFF (14) + #define DDRDATA_CR_DDRCRVREFADJUST1_Ch0VrefCtl_WID ( 7) + #define DDRDATA_CR_DDRCRVREFADJUST1_Ch0VrefCtl_MSK (0x001FC000) + #define DDRDATA_CR_DDRCRVREFADJUST1_Ch0VrefCtl_MAX (0x0000007F) + #define DDRDATA_CR_DDRCRVREFADJUST1_Ch0VrefCtl_DEF (0x00000000) + #define DDRDATA_CR_DDRCRVREFADJUST1_EnDimmVrefCA_OFF (21) + #define DDRDATA_CR_DDRCRVREFADJUST1_EnDimmVrefCA_WID ( 1) + #define DDRDATA_CR_DDRCRVREFADJUST1_EnDimmVrefCA_MSK (0x00200000) + #define DDRDATA_CR_DDRCRVREFADJUST1_EnDimmVrefCA_MAX (0x00000001) + #define DDRDATA_CR_DDRCRVREFADJUST1_EnDimmVrefCA_DEF (0x00000000) + #define DDRDATA_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_OFF (22) + #define DDRDATA_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_WID ( 1) + #define DDRDATA_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_MSK (0x00400000) + #define DDRDATA_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_MAX (0x00000001) + #define DDRDATA_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_DEF (0x00000000) + #define DDRDATA_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_OFF (23) + #define DDRDATA_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_WID ( 1) + #define DDRDATA_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_MSK (0x00800000) + #define DDRDATA_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_MAX (0x00000001) + #define DDRDATA_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_DEF (0x00000000) + #define DDRDATA_CR_DDRCRVREFADJUST1_HiZTimerCtrl_OFF (24) + #define DDRDATA_CR_DDRCRVREFADJUST1_HiZTimerCtrl_WID ( 2) + #define DDRDATA_CR_DDRCRVREFADJUST1_HiZTimerCtrl_MSK (0x03000000) + #define DDRDATA_CR_DDRCRVREFADJUST1_HiZTimerCtrl_MAX (0x00000003) + #define DDRDATA_CR_DDRCRVREFADJUST1_HiZTimerCtrl_DEF (0x00000000) + #define DDRDATA_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_OFF (26) + #define DDRDATA_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_WID ( 1) + #define DDRDATA_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_MSK (0x04000000) + #define DDRDATA_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_MAX (0x00000001) + #define DDRDATA_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_DEF (0x00000000) + #define DDRDATA_CR_DDRCRVREFADJUST1_Rsvd_OFF (27) + #define DDRDATA_CR_DDRCRVREFADJUST1_Rsvd_WID ( 2) + #define DDRDATA_CR_DDRCRVREFADJUST1_Rsvd_MSK (0x18000000) + #define DDRDATA_CR_DDRCRVREFADJUST1_Rsvd_MAX (0x00000003) + #define DDRDATA_CR_DDRCRVREFADJUST1_Rsvd_DEF (0x00000000) + #define DDRDATA_CR_DDRCRVREFADJUST1_caSlowBW_OFF (29) + #define DDRDATA_CR_DDRCRVREFADJUST1_caSlowBW_WID ( 1) + #define DDRDATA_CR_DDRCRVREFADJUST1_caSlowBW_MSK (0x20000000) + #define DDRDATA_CR_DDRCRVREFADJUST1_caSlowBW_MAX (0x00000001) + #define DDRDATA_CR_DDRCRVREFADJUST1_caSlowBW_DEF (0x00000000) + #define DDRDATA_CR_DDRCRVREFADJUST1_ch0SlowBW_OFF (30) + #define DDRDATA_CR_DDRCRVREFADJUST1_ch0SlowBW_WID ( 1) + #define DDRDATA_CR_DDRCRVREFADJUST1_ch0SlowBW_MSK (0x40000000) + #define DDRDATA_CR_DDRCRVREFADJUST1_ch0SlowBW_MAX (0x00000001) + #define DDRDATA_CR_DDRCRVREFADJUST1_ch0SlowBW_DEF (0x00000000) + #define DDRDATA_CR_DDRCRVREFADJUST1_ch1SlowBW_OFF (31) + #define DDRDATA_CR_DDRCRVREFADJUST1_ch1SlowBW_WID ( 1) + #define DDRDATA_CR_DDRCRVREFADJUST1_ch1SlowBW_MSK (0x80000000) + #define DDRDATA_CR_DDRCRVREFADJUST1_ch1SlowBW_MAX (0x00000001) + #define DDRDATA_CR_DDRCRVREFADJUST1_ch1SlowBW_DEF (0x00000000) + +#define DDRDATACH0_CR_RXTRAINRANK0_REG (0x00003000) + #define DDRDATACH0_CR_RXTRAINRANK0_RxRcvEnPi_OFF ( 0) + #define DDRDATACH0_CR_RXTRAINRANK0_RxRcvEnPi_WID ( 9) + #define DDRDATACH0_CR_RXTRAINRANK0_RxRcvEnPi_MSK (0x000001FF) + #define DDRDATACH0_CR_RXTRAINRANK0_RxRcvEnPi_MAX (0x000001FF) + #define DDRDATACH0_CR_RXTRAINRANK0_RxDqsPPi_OFF ( 9) + #define DDRDATACH0_CR_RXTRAINRANK0_RxDqsPPi_WID ( 6) + #define DDRDATACH0_CR_RXTRAINRANK0_RxDqsPPi_MSK (0x00007E00) + #define DDRDATACH0_CR_RXTRAINRANK0_RxDqsPPi_MAX (0x0000003F) + #define DDRDATACH0_CR_RXTRAINRANK0_RxEq_OFF (15) + #define DDRDATACH0_CR_RXTRAINRANK0_RxEq_WID ( 5) + #define DDRDATACH0_CR_RXTRAINRANK0_RxEq_MSK (0x000F8000) + #define DDRDATACH0_CR_RXTRAINRANK0_RxEq_MAX (0x0000001F) + #define DDRDATACH0_CR_RXTRAINRANK0_RxDqsNPi_OFF (20) + #define DDRDATACH0_CR_RXTRAINRANK0_RxDqsNPi_WID ( 6) + #define DDRDATACH0_CR_RXTRAINRANK0_RxDqsNPi_MSK (0x03F00000) + #define DDRDATACH0_CR_RXTRAINRANK0_RxDqsNPi_MAX (0x0000003F) + #define DDRDATACH0_CR_RXTRAINRANK0_RxVref_OFF (26) + #define DDRDATACH0_CR_RXTRAINRANK0_RxVref_WID ( 6) + #define DDRDATACH0_CR_RXTRAINRANK0_RxVref_MSK (0xFC000000) + #define DDRDATACH0_CR_RXTRAINRANK0_RxVref_MAX (0x0000003F) + +#define DDRDATACH0_CR_RXTRAINRANK1_REG (0x00003004) + #define DDRDATACH0_CR_RXTRAINRANK1_RxRcvEnPi_OFF ( 0) + #define DDRDATACH0_CR_RXTRAINRANK1_RxRcvEnPi_WID ( 9) + #define DDRDATACH0_CR_RXTRAINRANK1_RxRcvEnPi_MSK (0x000001FF) + #define DDRDATACH0_CR_RXTRAINRANK1_RxRcvEnPi_MAX (0x000001FF) + #define DDRDATACH0_CR_RXTRAINRANK1_RxDqsPPi_OFF ( 9) + #define DDRDATACH0_CR_RXTRAINRANK1_RxDqsPPi_WID ( 6) + #define DDRDATACH0_CR_RXTRAINRANK1_RxDqsPPi_MSK (0x00007E00) + #define DDRDATACH0_CR_RXTRAINRANK1_RxDqsPPi_MAX (0x0000003F) + #define DDRDATACH0_CR_RXTRAINRANK1_RxEq_OFF (15) + #define DDRDATACH0_CR_RXTRAINRANK1_RxEq_WID ( 5) + #define DDRDATACH0_CR_RXTRAINRANK1_RxEq_MSK (0x000F8000) + #define DDRDATACH0_CR_RXTRAINRANK1_RxEq_MAX (0x0000001F) + #define DDRDATACH0_CR_RXTRAINRANK1_RxDqsNPi_OFF (20) + #define DDRDATACH0_CR_RXTRAINRANK1_RxDqsNPi_WID ( 6) + #define DDRDATACH0_CR_RXTRAINRANK1_RxDqsNPi_MSK (0x03F00000) + #define DDRDATACH0_CR_RXTRAINRANK1_RxDqsNPi_MAX (0x0000003F) + #define DDRDATACH0_CR_RXTRAINRANK1_RxVref_OFF (26) + #define DDRDATACH0_CR_RXTRAINRANK1_RxVref_WID ( 6) + #define DDRDATACH0_CR_RXTRAINRANK1_RxVref_MSK (0xFC000000) + #define DDRDATACH0_CR_RXTRAINRANK1_RxVref_MAX (0x0000003F) + +#define DDRDATACH0_CR_RXTRAINRANK2_REG (0x00003008) + #define DDRDATACH0_CR_RXTRAINRANK2_RxRcvEnPi_OFF ( 0) + #define DDRDATACH0_CR_RXTRAINRANK2_RxRcvEnPi_WID ( 9) + #define DDRDATACH0_CR_RXTRAINRANK2_RxRcvEnPi_MSK (0x000001FF) + #define DDRDATACH0_CR_RXTRAINRANK2_RxRcvEnPi_MAX (0x000001FF) + #define DDRDATACH0_CR_RXTRAINRANK2_RxDqsPPi_OFF ( 9) + #define DDRDATACH0_CR_RXTRAINRANK2_RxDqsPPi_WID ( 6) + #define DDRDATACH0_CR_RXTRAINRANK2_RxDqsPPi_MSK (0x00007E00) + #define DDRDATACH0_CR_RXTRAINRANK2_RxDqsPPi_MAX (0x0000003F) + #define DDRDATACH0_CR_RXTRAINRANK2_RxEq_OFF (15) + #define DDRDATACH0_CR_RXTRAINRANK2_RxEq_WID ( 5) + #define DDRDATACH0_CR_RXTRAINRANK2_RxEq_MSK (0x000F8000) + #define DDRDATACH0_CR_RXTRAINRANK2_RxEq_MAX (0x0000001F) + #define DDRDATACH0_CR_RXTRAINRANK2_RxDqsNPi_OFF (20) + #define DDRDATACH0_CR_RXTRAINRANK2_RxDqsNPi_WID ( 6) + #define DDRDATACH0_CR_RXTRAINRANK2_RxDqsNPi_MSK (0x03F00000) + #define DDRDATACH0_CR_RXTRAINRANK2_RxDqsNPi_MAX (0x0000003F) + #define DDRDATACH0_CR_RXTRAINRANK2_RxVref_OFF (26) + #define DDRDATACH0_CR_RXTRAINRANK2_RxVref_WID ( 6) + #define DDRDATACH0_CR_RXTRAINRANK2_RxVref_MSK (0xFC000000) + #define DDRDATACH0_CR_RXTRAINRANK2_RxVref_MAX (0x0000003F) + +#define DDRDATACH0_CR_RXTRAINRANK3_REG (0x0000300C) + #define DDRDATACH0_CR_RXTRAINRANK3_RxRcvEnPi_OFF ( 0) + #define DDRDATACH0_CR_RXTRAINRANK3_RxRcvEnPi_WID ( 9) + #define DDRDATACH0_CR_RXTRAINRANK3_RxRcvEnPi_MSK (0x000001FF) + #define DDRDATACH0_CR_RXTRAINRANK3_RxRcvEnPi_MAX (0x000001FF) + #define DDRDATACH0_CR_RXTRAINRANK3_RxDqsPPi_OFF ( 9) + #define DDRDATACH0_CR_RXTRAINRANK3_RxDqsPPi_WID ( 6) + #define DDRDATACH0_CR_RXTRAINRANK3_RxDqsPPi_MSK (0x00007E00) + #define DDRDATACH0_CR_RXTRAINRANK3_RxDqsPPi_MAX (0x0000003F) + #define DDRDATACH0_CR_RXTRAINRANK3_RxEq_OFF (15) + #define DDRDATACH0_CR_RXTRAINRANK3_RxEq_WID ( 5) + #define DDRDATACH0_CR_RXTRAINRANK3_RxEq_MSK (0x000F8000) + #define DDRDATACH0_CR_RXTRAINRANK3_RxEq_MAX (0x0000001F) + #define DDRDATACH0_CR_RXTRAINRANK3_RxDqsNPi_OFF (20) + #define DDRDATACH0_CR_RXTRAINRANK3_RxDqsNPi_WID ( 6) + #define DDRDATACH0_CR_RXTRAINRANK3_RxDqsNPi_MSK (0x03F00000) + #define DDRDATACH0_CR_RXTRAINRANK3_RxDqsNPi_MAX (0x0000003F) + #define DDRDATACH0_CR_RXTRAINRANK3_RxVref_OFF (26) + #define DDRDATACH0_CR_RXTRAINRANK3_RxVref_WID ( 6) + #define DDRDATACH0_CR_RXTRAINRANK3_RxVref_MSK (0xFC000000) + #define DDRDATACH0_CR_RXTRAINRANK3_RxVref_MAX (0x0000003F) + +#define DDRDATACH0_CR_RXPERBITRANK0_REG (0x00003010) + #define DDRDATACH0_CR_RXPERBITRANK0_Lane0_OFF ( 0) + #define DDRDATACH0_CR_RXPERBITRANK0_Lane0_WID ( 4) + #define DDRDATACH0_CR_RXPERBITRANK0_Lane0_MSK (0x0000000F) + #define DDRDATACH0_CR_RXPERBITRANK0_Lane0_MAX (0x0000000F) + #define DDRDATACH0_CR_RXPERBITRANK0_Lane1_OFF ( 4) + #define DDRDATACH0_CR_RXPERBITRANK0_Lane1_WID ( 4) + #define DDRDATACH0_CR_RXPERBITRANK0_Lane1_MSK (0x000000F0) + #define DDRDATACH0_CR_RXPERBITRANK0_Lane1_MAX (0x0000000F) + #define DDRDATACH0_CR_RXPERBITRANK0_Lane2_OFF ( 8) + #define DDRDATACH0_CR_RXPERBITRANK0_Lane2_WID ( 4) + #define DDRDATACH0_CR_RXPERBITRANK0_Lane2_MSK (0x00000F00) + #define DDRDATACH0_CR_RXPERBITRANK0_Lane2_MAX (0x0000000F) + #define DDRDATACH0_CR_RXPERBITRANK0_Lane3_OFF (12) + #define DDRDATACH0_CR_RXPERBITRANK0_Lane3_WID ( 4) + #define DDRDATACH0_CR_RXPERBITRANK0_Lane3_MSK (0x0000F000) + #define DDRDATACH0_CR_RXPERBITRANK0_Lane3_MAX (0x0000000F) + #define DDRDATACH0_CR_RXPERBITRANK0_Lane4_OFF (16) + #define DDRDATACH0_CR_RXPERBITRANK0_Lane4_WID ( 4) + #define DDRDATACH0_CR_RXPERBITRANK0_Lane4_MSK (0x000F0000) + #define DDRDATACH0_CR_RXPERBITRANK0_Lane4_MAX (0x0000000F) + #define DDRDATACH0_CR_RXPERBITRANK0_Lane5_OFF (20) + #define DDRDATACH0_CR_RXPERBITRANK0_Lane5_WID ( 4) + #define DDRDATACH0_CR_RXPERBITRANK0_Lane5_MSK (0x00F00000) + #define DDRDATACH0_CR_RXPERBITRANK0_Lane5_MAX (0x0000000F) + #define DDRDATACH0_CR_RXPERBITRANK0_Lane6_OFF (24) + #define DDRDATACH0_CR_RXPERBITRANK0_Lane6_WID ( 4) + #define DDRDATACH0_CR_RXPERBITRANK0_Lane6_MSK (0x0F000000) + #define DDRDATACH0_CR_RXPERBITRANK0_Lane6_MAX (0x0000000F) + #define DDRDATACH0_CR_RXPERBITRANK0_Lane7_OFF (28) + #define DDRDATACH0_CR_RXPERBITRANK0_Lane7_WID ( 4) + #define DDRDATACH0_CR_RXPERBITRANK0_Lane7_MSK (0xF0000000) + #define DDRDATACH0_CR_RXPERBITRANK0_Lane7_MAX (0x0000000F) + +#define DDRDATACH0_CR_RXPERBITRANK1_REG (0x00003014) + #define DDRDATACH0_CR_RXPERBITRANK1_Lane0_OFF ( 0) + #define DDRDATACH0_CR_RXPERBITRANK1_Lane0_WID ( 4) + #define DDRDATACH0_CR_RXPERBITRANK1_Lane0_MSK (0x0000000F) + #define DDRDATACH0_CR_RXPERBITRANK1_Lane0_MAX (0x0000000F) + #define DDRDATACH0_CR_RXPERBITRANK1_Lane1_OFF ( 4) + #define DDRDATACH0_CR_RXPERBITRANK1_Lane1_WID ( 4) + #define DDRDATACH0_CR_RXPERBITRANK1_Lane1_MSK (0x000000F0) + #define DDRDATACH0_CR_RXPERBITRANK1_Lane1_MAX (0x0000000F) + #define DDRDATACH0_CR_RXPERBITRANK1_Lane2_OFF ( 8) + #define DDRDATACH0_CR_RXPERBITRANK1_Lane2_WID ( 4) + #define DDRDATACH0_CR_RXPERBITRANK1_Lane2_MSK (0x00000F00) + #define DDRDATACH0_CR_RXPERBITRANK1_Lane2_MAX (0x0000000F) + #define DDRDATACH0_CR_RXPERBITRANK1_Lane3_OFF (12) + #define DDRDATACH0_CR_RXPERBITRANK1_Lane3_WID ( 4) + #define DDRDATACH0_CR_RXPERBITRANK1_Lane3_MSK (0x0000F000) + #define DDRDATACH0_CR_RXPERBITRANK1_Lane3_MAX (0x0000000F) + #define DDRDATACH0_CR_RXPERBITRANK1_Lane4_OFF (16) + #define DDRDATACH0_CR_RXPERBITRANK1_Lane4_WID ( 4) + #define DDRDATACH0_CR_RXPERBITRANK1_Lane4_MSK (0x000F0000) + #define DDRDATACH0_CR_RXPERBITRANK1_Lane4_MAX (0x0000000F) + #define DDRDATACH0_CR_RXPERBITRANK1_Lane5_OFF (20) + #define DDRDATACH0_CR_RXPERBITRANK1_Lane5_WID ( 4) + #define DDRDATACH0_CR_RXPERBITRANK1_Lane5_MSK (0x00F00000) + #define DDRDATACH0_CR_RXPERBITRANK1_Lane5_MAX (0x0000000F) + #define DDRDATACH0_CR_RXPERBITRANK1_Lane6_OFF (24) + #define DDRDATACH0_CR_RXPERBITRANK1_Lane6_WID ( 4) + #define DDRDATACH0_CR_RXPERBITRANK1_Lane6_MSK (0x0F000000) + #define DDRDATACH0_CR_RXPERBITRANK1_Lane6_MAX (0x0000000F) + #define DDRDATACH0_CR_RXPERBITRANK1_Lane7_OFF (28) + #define DDRDATACH0_CR_RXPERBITRANK1_Lane7_WID ( 4) + #define DDRDATACH0_CR_RXPERBITRANK1_Lane7_MSK (0xF0000000) + #define DDRDATACH0_CR_RXPERBITRANK1_Lane7_MAX (0x0000000F) + +#define DDRDATACH0_CR_RXPERBITRANK2_REG (0x00003018) + #define DDRDATACH0_CR_RXPERBITRANK2_Lane0_OFF ( 0) + #define DDRDATACH0_CR_RXPERBITRANK2_Lane0_WID ( 4) + #define DDRDATACH0_CR_RXPERBITRANK2_Lane0_MSK (0x0000000F) + #define DDRDATACH0_CR_RXPERBITRANK2_Lane0_MAX (0x0000000F) + #define DDRDATACH0_CR_RXPERBITRANK2_Lane1_OFF ( 4) + #define DDRDATACH0_CR_RXPERBITRANK2_Lane1_WID ( 4) + #define DDRDATACH0_CR_RXPERBITRANK2_Lane1_MSK (0x000000F0) + #define DDRDATACH0_CR_RXPERBITRANK2_Lane1_MAX (0x0000000F) + #define DDRDATACH0_CR_RXPERBITRANK2_Lane2_OFF ( 8) + #define DDRDATACH0_CR_RXPERBITRANK2_Lane2_WID ( 4) + #define DDRDATACH0_CR_RXPERBITRANK2_Lane2_MSK (0x00000F00) + #define DDRDATACH0_CR_RXPERBITRANK2_Lane2_MAX (0x0000000F) + #define DDRDATACH0_CR_RXPERBITRANK2_Lane3_OFF (12) + #define DDRDATACH0_CR_RXPERBITRANK2_Lane3_WID ( 4) + #define DDRDATACH0_CR_RXPERBITRANK2_Lane3_MSK (0x0000F000) + #define DDRDATACH0_CR_RXPERBITRANK2_Lane3_MAX (0x0000000F) + #define DDRDATACH0_CR_RXPERBITRANK2_Lane4_OFF (16) + #define DDRDATACH0_CR_RXPERBITRANK2_Lane4_WID ( 4) + #define DDRDATACH0_CR_RXPERBITRANK2_Lane4_MSK (0x000F0000) + #define DDRDATACH0_CR_RXPERBITRANK2_Lane4_MAX (0x0000000F) + #define DDRDATACH0_CR_RXPERBITRANK2_Lane5_OFF (20) + #define DDRDATACH0_CR_RXPERBITRANK2_Lane5_WID ( 4) + #define DDRDATACH0_CR_RXPERBITRANK2_Lane5_MSK (0x00F00000) + #define DDRDATACH0_CR_RXPERBITRANK2_Lane5_MAX (0x0000000F) + #define DDRDATACH0_CR_RXPERBITRANK2_Lane6_OFF (24) + #define DDRDATACH0_CR_RXPERBITRANK2_Lane6_WID ( 4) + #define DDRDATACH0_CR_RXPERBITRANK2_Lane6_MSK (0x0F000000) + #define DDRDATACH0_CR_RXPERBITRANK2_Lane6_MAX (0x0000000F) + #define DDRDATACH0_CR_RXPERBITRANK2_Lane7_OFF (28) + #define DDRDATACH0_CR_RXPERBITRANK2_Lane7_WID ( 4) + #define DDRDATACH0_CR_RXPERBITRANK2_Lane7_MSK (0xF0000000) + #define DDRDATACH0_CR_RXPERBITRANK2_Lane7_MAX (0x0000000F) + +#define DDRDATACH0_CR_RXPERBITRANK3_REG (0x0000301C) + #define DDRDATACH0_CR_RXPERBITRANK3_Lane0_OFF ( 0) + #define DDRDATACH0_CR_RXPERBITRANK3_Lane0_WID ( 4) + #define DDRDATACH0_CR_RXPERBITRANK3_Lane0_MSK (0x0000000F) + #define DDRDATACH0_CR_RXPERBITRANK3_Lane0_MAX (0x0000000F) + #define DDRDATACH0_CR_RXPERBITRANK3_Lane1_OFF ( 4) + #define DDRDATACH0_CR_RXPERBITRANK3_Lane1_WID ( 4) + #define DDRDATACH0_CR_RXPERBITRANK3_Lane1_MSK (0x000000F0) + #define DDRDATACH0_CR_RXPERBITRANK3_Lane1_MAX (0x0000000F) + #define DDRDATACH0_CR_RXPERBITRANK3_Lane2_OFF ( 8) + #define DDRDATACH0_CR_RXPERBITRANK3_Lane2_WID ( 4) + #define DDRDATACH0_CR_RXPERBITRANK3_Lane2_MSK (0x00000F00) + #define DDRDATACH0_CR_RXPERBITRANK3_Lane2_MAX (0x0000000F) + #define DDRDATACH0_CR_RXPERBITRANK3_Lane3_OFF (12) + #define DDRDATACH0_CR_RXPERBITRANK3_Lane3_WID ( 4) + #define DDRDATACH0_CR_RXPERBITRANK3_Lane3_MSK (0x0000F000) + #define DDRDATACH0_CR_RXPERBITRANK3_Lane3_MAX (0x0000000F) + #define DDRDATACH0_CR_RXPERBITRANK3_Lane4_OFF (16) + #define DDRDATACH0_CR_RXPERBITRANK3_Lane4_WID ( 4) + #define DDRDATACH0_CR_RXPERBITRANK3_Lane4_MSK (0x000F0000) + #define DDRDATACH0_CR_RXPERBITRANK3_Lane4_MAX (0x0000000F) + #define DDRDATACH0_CR_RXPERBITRANK3_Lane5_OFF (20) + #define DDRDATACH0_CR_RXPERBITRANK3_Lane5_WID ( 4) + #define DDRDATACH0_CR_RXPERBITRANK3_Lane5_MSK (0x00F00000) + #define DDRDATACH0_CR_RXPERBITRANK3_Lane5_MAX (0x0000000F) + #define DDRDATACH0_CR_RXPERBITRANK3_Lane6_OFF (24) + #define DDRDATACH0_CR_RXPERBITRANK3_Lane6_WID ( 4) + #define DDRDATACH0_CR_RXPERBITRANK3_Lane6_MSK (0x0F000000) + #define DDRDATACH0_CR_RXPERBITRANK3_Lane6_MAX (0x0000000F) + #define DDRDATACH0_CR_RXPERBITRANK3_Lane7_OFF (28) + #define DDRDATACH0_CR_RXPERBITRANK3_Lane7_WID ( 4) + #define DDRDATACH0_CR_RXPERBITRANK3_Lane7_MSK (0xF0000000) + #define DDRDATACH0_CR_RXPERBITRANK3_Lane7_MAX (0x0000000F) + +#define DDRDATACH0_CR_TXTRAINRANK0_REG (0x00003020) + #define DDRDATACH0_CR_TXTRAINRANK0_TxDqDelay_OFF ( 0) + #define DDRDATACH0_CR_TXTRAINRANK0_TxDqDelay_WID ( 9) + #define DDRDATACH0_CR_TXTRAINRANK0_TxDqDelay_MSK (0x000001FF) + #define DDRDATACH0_CR_TXTRAINRANK0_TxDqDelay_MAX (0x000001FF) + #define DDRDATACH0_CR_TXTRAINRANK0_TxDqsDelay_OFF ( 9) + #define DDRDATACH0_CR_TXTRAINRANK0_TxDqsDelay_WID ( 9) + #define DDRDATACH0_CR_TXTRAINRANK0_TxDqsDelay_MSK (0x0003FE00) + #define DDRDATACH0_CR_TXTRAINRANK0_TxDqsDelay_MAX (0x000001FF) + #define DDRDATACH0_CR_TXTRAINRANK0_Spare0_OFF (18) + #define DDRDATACH0_CR_TXTRAINRANK0_Spare0_WID ( 2) + #define DDRDATACH0_CR_TXTRAINRANK0_Spare0_MSK (0x000C0000) + #define DDRDATACH0_CR_TXTRAINRANK0_Spare0_MAX (0x00000003) + #define DDRDATACH0_CR_TXTRAINRANK0_TxEqualization_OFF (20) + #define DDRDATACH0_CR_TXTRAINRANK0_TxEqualization_WID ( 6) + #define DDRDATACH0_CR_TXTRAINRANK0_TxEqualization_MSK (0x03F00000) + #define DDRDATACH0_CR_TXTRAINRANK0_TxEqualization_MAX (0x0000003F) + #define DDRDATACH0_CR_TXTRAINRANK0_Spare1_OFF (26) + #define DDRDATACH0_CR_TXTRAINRANK0_Spare1_WID ( 6) + #define DDRDATACH0_CR_TXTRAINRANK0_Spare1_MSK (0xFC000000) + #define DDRDATACH0_CR_TXTRAINRANK0_Spare1_MAX (0x0000003F) + +#define DDRDATACH0_CR_TXTRAINRANK1_REG (0x00003024) + #define DDRDATACH0_CR_TXTRAINRANK1_TxDqDelay_OFF ( 0) + #define DDRDATACH0_CR_TXTRAINRANK1_TxDqDelay_WID ( 9) + #define DDRDATACH0_CR_TXTRAINRANK1_TxDqDelay_MSK (0x000001FF) + #define DDRDATACH0_CR_TXTRAINRANK1_TxDqDelay_MAX (0x000001FF) + #define DDRDATACH0_CR_TXTRAINRANK1_TxDqsDelay_OFF ( 9) + #define DDRDATACH0_CR_TXTRAINRANK1_TxDqsDelay_WID ( 9) + #define DDRDATACH0_CR_TXTRAINRANK1_TxDqsDelay_MSK (0x0003FE00) + #define DDRDATACH0_CR_TXTRAINRANK1_TxDqsDelay_MAX (0x000001FF) + #define DDRDATACH0_CR_TXTRAINRANK1_Spare0_OFF (18) + #define DDRDATACH0_CR_TXTRAINRANK1_Spare0_WID ( 2) + #define DDRDATACH0_CR_TXTRAINRANK1_Spare0_MSK (0x000C0000) + #define DDRDATACH0_CR_TXTRAINRANK1_Spare0_MAX (0x00000003) + #define DDRDATACH0_CR_TXTRAINRANK1_TxEqualization_OFF (20) + #define DDRDATACH0_CR_TXTRAINRANK1_TxEqualization_WID ( 6) + #define DDRDATACH0_CR_TXTRAINRANK1_TxEqualization_MSK (0x03F00000) + #define DDRDATACH0_CR_TXTRAINRANK1_TxEqualization_MAX (0x0000003F) + #define DDRDATACH0_CR_TXTRAINRANK1_Spare1_OFF (26) + #define DDRDATACH0_CR_TXTRAINRANK1_Spare1_WID ( 6) + #define DDRDATACH0_CR_TXTRAINRANK1_Spare1_MSK (0xFC000000) + #define DDRDATACH0_CR_TXTRAINRANK1_Spare1_MAX (0x0000003F) + +#define DDRDATACH0_CR_TXTRAINRANK2_REG (0x00003028) + #define DDRDATACH0_CR_TXTRAINRANK2_TxDqDelay_OFF ( 0) + #define DDRDATACH0_CR_TXTRAINRANK2_TxDqDelay_WID ( 9) + #define DDRDATACH0_CR_TXTRAINRANK2_TxDqDelay_MSK (0x000001FF) + #define DDRDATACH0_CR_TXTRAINRANK2_TxDqDelay_MAX (0x000001FF) + #define DDRDATACH0_CR_TXTRAINRANK2_TxDqsDelay_OFF ( 9) + #define DDRDATACH0_CR_TXTRAINRANK2_TxDqsDelay_WID ( 9) + #define DDRDATACH0_CR_TXTRAINRANK2_TxDqsDelay_MSK (0x0003FE00) + #define DDRDATACH0_CR_TXTRAINRANK2_TxDqsDelay_MAX (0x000001FF) + #define DDRDATACH0_CR_TXTRAINRANK2_Spare0_OFF (18) + #define DDRDATACH0_CR_TXTRAINRANK2_Spare0_WID ( 2) + #define DDRDATACH0_CR_TXTRAINRANK2_Spare0_MSK (0x000C0000) + #define DDRDATACH0_CR_TXTRAINRANK2_Spare0_MAX (0x00000003) + #define DDRDATACH0_CR_TXTRAINRANK2_TxEqualization_OFF (20) + #define DDRDATACH0_CR_TXTRAINRANK2_TxEqualization_WID ( 6) + #define DDRDATACH0_CR_TXTRAINRANK2_TxEqualization_MSK (0x03F00000) + #define DDRDATACH0_CR_TXTRAINRANK2_TxEqualization_MAX (0x0000003F) + #define DDRDATACH0_CR_TXTRAINRANK2_Spare1_OFF (26) + #define DDRDATACH0_CR_TXTRAINRANK2_Spare1_WID ( 6) + #define DDRDATACH0_CR_TXTRAINRANK2_Spare1_MSK (0xFC000000) + #define DDRDATACH0_CR_TXTRAINRANK2_Spare1_MAX (0x0000003F) + +#define DDRDATACH0_CR_TXTRAINRANK3_REG (0x0000302C) + #define DDRDATACH0_CR_TXTRAINRANK3_TxDqDelay_OFF ( 0) + #define DDRDATACH0_CR_TXTRAINRANK3_TxDqDelay_WID ( 9) + #define DDRDATACH0_CR_TXTRAINRANK3_TxDqDelay_MSK (0x000001FF) + #define DDRDATACH0_CR_TXTRAINRANK3_TxDqDelay_MAX (0x000001FF) + #define DDRDATACH0_CR_TXTRAINRANK3_TxDqsDelay_OFF ( 9) + #define DDRDATACH0_CR_TXTRAINRANK3_TxDqsDelay_WID ( 9) + #define DDRDATACH0_CR_TXTRAINRANK3_TxDqsDelay_MSK (0x0003FE00) + #define DDRDATACH0_CR_TXTRAINRANK3_TxDqsDelay_MAX (0x000001FF) + #define DDRDATACH0_CR_TXTRAINRANK3_Spare0_OFF (18) + #define DDRDATACH0_CR_TXTRAINRANK3_Spare0_WID ( 2) + #define DDRDATACH0_CR_TXTRAINRANK3_Spare0_MSK (0x000C0000) + #define DDRDATACH0_CR_TXTRAINRANK3_Spare0_MAX (0x00000003) + #define DDRDATACH0_CR_TXTRAINRANK3_TxEqualization_OFF (20) + #define DDRDATACH0_CR_TXTRAINRANK3_TxEqualization_WID ( 6) + #define DDRDATACH0_CR_TXTRAINRANK3_TxEqualization_MSK (0x03F00000) + #define DDRDATACH0_CR_TXTRAINRANK3_TxEqualization_MAX (0x0000003F) + #define DDRDATACH0_CR_TXTRAINRANK3_Spare1_OFF (26) + #define DDRDATACH0_CR_TXTRAINRANK3_Spare1_WID ( 6) + #define DDRDATACH0_CR_TXTRAINRANK3_Spare1_MSK (0xFC000000) + #define DDRDATACH0_CR_TXTRAINRANK3_Spare1_MAX (0x0000003F) + +#define DDRDATACH0_CR_TXPERBITRANK0_REG (0x00003030) + #define DDRDATACH0_CR_TXPERBITRANK0_Lane0_OFF ( 0) + #define DDRDATACH0_CR_TXPERBITRANK0_Lane0_WID ( 4) + #define DDRDATACH0_CR_TXPERBITRANK0_Lane0_MSK (0x0000000F) + #define DDRDATACH0_CR_TXPERBITRANK0_Lane0_MAX (0x0000000F) + #define DDRDATACH0_CR_TXPERBITRANK0_Lane1_OFF ( 4) + #define DDRDATACH0_CR_TXPERBITRANK0_Lane1_WID ( 4) + #define DDRDATACH0_CR_TXPERBITRANK0_Lane1_MSK (0x000000F0) + #define DDRDATACH0_CR_TXPERBITRANK0_Lane1_MAX (0x0000000F) + #define DDRDATACH0_CR_TXPERBITRANK0_Lane2_OFF ( 8) + #define DDRDATACH0_CR_TXPERBITRANK0_Lane2_WID ( 4) + #define DDRDATACH0_CR_TXPERBITRANK0_Lane2_MSK (0x00000F00) + #define DDRDATACH0_CR_TXPERBITRANK0_Lane2_MAX (0x0000000F) + #define DDRDATACH0_CR_TXPERBITRANK0_Lane3_OFF (12) + #define DDRDATACH0_CR_TXPERBITRANK0_Lane3_WID ( 4) + #define DDRDATACH0_CR_TXPERBITRANK0_Lane3_MSK (0x0000F000) + #define DDRDATACH0_CR_TXPERBITRANK0_Lane3_MAX (0x0000000F) + #define DDRDATACH0_CR_TXPERBITRANK0_Lane4_OFF (16) + #define DDRDATACH0_CR_TXPERBITRANK0_Lane4_WID ( 4) + #define DDRDATACH0_CR_TXPERBITRANK0_Lane4_MSK (0x000F0000) + #define DDRDATACH0_CR_TXPERBITRANK0_Lane4_MAX (0x0000000F) + #define DDRDATACH0_CR_TXPERBITRANK0_Lane5_OFF (20) + #define DDRDATACH0_CR_TXPERBITRANK0_Lane5_WID ( 4) + #define DDRDATACH0_CR_TXPERBITRANK0_Lane5_MSK (0x00F00000) + #define DDRDATACH0_CR_TXPERBITRANK0_Lane5_MAX (0x0000000F) + #define DDRDATACH0_CR_TXPERBITRANK0_Lane6_OFF (24) + #define DDRDATACH0_CR_TXPERBITRANK0_Lane6_WID ( 4) + #define DDRDATACH0_CR_TXPERBITRANK0_Lane6_MSK (0x0F000000) + #define DDRDATACH0_CR_TXPERBITRANK0_Lane6_MAX (0x0000000F) + #define DDRDATACH0_CR_TXPERBITRANK0_Lane7_OFF (28) + #define DDRDATACH0_CR_TXPERBITRANK0_Lane7_WID ( 4) + #define DDRDATACH0_CR_TXPERBITRANK0_Lane7_MSK (0xF0000000) + #define DDRDATACH0_CR_TXPERBITRANK0_Lane7_MAX (0x0000000F) + +#define DDRDATACH0_CR_TXPERBITRANK1_REG (0x00003034) + #define DDRDATACH0_CR_TXPERBITRANK1_Lane0_OFF ( 0) + #define DDRDATACH0_CR_TXPERBITRANK1_Lane0_WID ( 4) + #define DDRDATACH0_CR_TXPERBITRANK1_Lane0_MSK (0x0000000F) + #define DDRDATACH0_CR_TXPERBITRANK1_Lane0_MAX (0x0000000F) + #define DDRDATACH0_CR_TXPERBITRANK1_Lane1_OFF ( 4) + #define DDRDATACH0_CR_TXPERBITRANK1_Lane1_WID ( 4) + #define DDRDATACH0_CR_TXPERBITRANK1_Lane1_MSK (0x000000F0) + #define DDRDATACH0_CR_TXPERBITRANK1_Lane1_MAX (0x0000000F) + #define DDRDATACH0_CR_TXPERBITRANK1_Lane2_OFF ( 8) + #define DDRDATACH0_CR_TXPERBITRANK1_Lane2_WID ( 4) + #define DDRDATACH0_CR_TXPERBITRANK1_Lane2_MSK (0x00000F00) + #define DDRDATACH0_CR_TXPERBITRANK1_Lane2_MAX (0x0000000F) + #define DDRDATACH0_CR_TXPERBITRANK1_Lane3_OFF (12) + #define DDRDATACH0_CR_TXPERBITRANK1_Lane3_WID ( 4) + #define DDRDATACH0_CR_TXPERBITRANK1_Lane3_MSK (0x0000F000) + #define DDRDATACH0_CR_TXPERBITRANK1_Lane3_MAX (0x0000000F) + #define DDRDATACH0_CR_TXPERBITRANK1_Lane4_OFF (16) + #define DDRDATACH0_CR_TXPERBITRANK1_Lane4_WID ( 4) + #define DDRDATACH0_CR_TXPERBITRANK1_Lane4_MSK (0x000F0000) + #define DDRDATACH0_CR_TXPERBITRANK1_Lane4_MAX (0x0000000F) + #define DDRDATACH0_CR_TXPERBITRANK1_Lane5_OFF (20) + #define DDRDATACH0_CR_TXPERBITRANK1_Lane5_WID ( 4) + #define DDRDATACH0_CR_TXPERBITRANK1_Lane5_MSK (0x00F00000) + #define DDRDATACH0_CR_TXPERBITRANK1_Lane5_MAX (0x0000000F) + #define DDRDATACH0_CR_TXPERBITRANK1_Lane6_OFF (24) + #define DDRDATACH0_CR_TXPERBITRANK1_Lane6_WID ( 4) + #define DDRDATACH0_CR_TXPERBITRANK1_Lane6_MSK (0x0F000000) + #define DDRDATACH0_CR_TXPERBITRANK1_Lane6_MAX (0x0000000F) + #define DDRDATACH0_CR_TXPERBITRANK1_Lane7_OFF (28) + #define DDRDATACH0_CR_TXPERBITRANK1_Lane7_WID ( 4) + #define DDRDATACH0_CR_TXPERBITRANK1_Lane7_MSK (0xF0000000) + #define DDRDATACH0_CR_TXPERBITRANK1_Lane7_MAX (0x0000000F) + +#define DDRDATACH0_CR_TXPERBITRANK2_REG (0x00003038) + #define DDRDATACH0_CR_TXPERBITRANK2_Lane0_OFF ( 0) + #define DDRDATACH0_CR_TXPERBITRANK2_Lane0_WID ( 4) + #define DDRDATACH0_CR_TXPERBITRANK2_Lane0_MSK (0x0000000F) + #define DDRDATACH0_CR_TXPERBITRANK2_Lane0_MAX (0x0000000F) + #define DDRDATACH0_CR_TXPERBITRANK2_Lane1_OFF ( 4) + #define DDRDATACH0_CR_TXPERBITRANK2_Lane1_WID ( 4) + #define DDRDATACH0_CR_TXPERBITRANK2_Lane1_MSK (0x000000F0) + #define DDRDATACH0_CR_TXPERBITRANK2_Lane1_MAX (0x0000000F) + #define DDRDATACH0_CR_TXPERBITRANK2_Lane2_OFF ( 8) + #define DDRDATACH0_CR_TXPERBITRANK2_Lane2_WID ( 4) + #define DDRDATACH0_CR_TXPERBITRANK2_Lane2_MSK (0x00000F00) + #define DDRDATACH0_CR_TXPERBITRANK2_Lane2_MAX (0x0000000F) + #define DDRDATACH0_CR_TXPERBITRANK2_Lane3_OFF (12) + #define DDRDATACH0_CR_TXPERBITRANK2_Lane3_WID ( 4) + #define DDRDATACH0_CR_TXPERBITRANK2_Lane3_MSK (0x0000F000) + #define DDRDATACH0_CR_TXPERBITRANK2_Lane3_MAX (0x0000000F) + #define DDRDATACH0_CR_TXPERBITRANK2_Lane4_OFF (16) + #define DDRDATACH0_CR_TXPERBITRANK2_Lane4_WID ( 4) + #define DDRDATACH0_CR_TXPERBITRANK2_Lane4_MSK (0x000F0000) + #define DDRDATACH0_CR_TXPERBITRANK2_Lane4_MAX (0x0000000F) + #define DDRDATACH0_CR_TXPERBITRANK2_Lane5_OFF (20) + #define DDRDATACH0_CR_TXPERBITRANK2_Lane5_WID ( 4) + #define DDRDATACH0_CR_TXPERBITRANK2_Lane5_MSK (0x00F00000) + #define DDRDATACH0_CR_TXPERBITRANK2_Lane5_MAX (0x0000000F) + #define DDRDATACH0_CR_TXPERBITRANK2_Lane6_OFF (24) + #define DDRDATACH0_CR_TXPERBITRANK2_Lane6_WID ( 4) + #define DDRDATACH0_CR_TXPERBITRANK2_Lane6_MSK (0x0F000000) + #define DDRDATACH0_CR_TXPERBITRANK2_Lane6_MAX (0x0000000F) + #define DDRDATACH0_CR_TXPERBITRANK2_Lane7_OFF (28) + #define DDRDATACH0_CR_TXPERBITRANK2_Lane7_WID ( 4) + #define DDRDATACH0_CR_TXPERBITRANK2_Lane7_MSK (0xF0000000) + #define DDRDATACH0_CR_TXPERBITRANK2_Lane7_MAX (0x0000000F) + +#define DDRDATACH0_CR_TXPERBITRANK3_REG (0x0000303C) + #define DDRDATACH0_CR_TXPERBITRANK3_Lane0_OFF ( 0) + #define DDRDATACH0_CR_TXPERBITRANK3_Lane0_WID ( 4) + #define DDRDATACH0_CR_TXPERBITRANK3_Lane0_MSK (0x0000000F) + #define DDRDATACH0_CR_TXPERBITRANK3_Lane0_MAX (0x0000000F) + #define DDRDATACH0_CR_TXPERBITRANK3_Lane1_OFF ( 4) + #define DDRDATACH0_CR_TXPERBITRANK3_Lane1_WID ( 4) + #define DDRDATACH0_CR_TXPERBITRANK3_Lane1_MSK (0x000000F0) + #define DDRDATACH0_CR_TXPERBITRANK3_Lane1_MAX (0x0000000F) + #define DDRDATACH0_CR_TXPERBITRANK3_Lane2_OFF ( 8) + #define DDRDATACH0_CR_TXPERBITRANK3_Lane2_WID ( 4) + #define DDRDATACH0_CR_TXPERBITRANK3_Lane2_MSK (0x00000F00) + #define DDRDATACH0_CR_TXPERBITRANK3_Lane2_MAX (0x0000000F) + #define DDRDATACH0_CR_TXPERBITRANK3_Lane3_OFF (12) + #define DDRDATACH0_CR_TXPERBITRANK3_Lane3_WID ( 4) + #define DDRDATACH0_CR_TXPERBITRANK3_Lane3_MSK (0x0000F000) + #define DDRDATACH0_CR_TXPERBITRANK3_Lane3_MAX (0x0000000F) + #define DDRDATACH0_CR_TXPERBITRANK3_Lane4_OFF (16) + #define DDRDATACH0_CR_TXPERBITRANK3_Lane4_WID ( 4) + #define DDRDATACH0_CR_TXPERBITRANK3_Lane4_MSK (0x000F0000) + #define DDRDATACH0_CR_TXPERBITRANK3_Lane4_MAX (0x0000000F) + #define DDRDATACH0_CR_TXPERBITRANK3_Lane5_OFF (20) + #define DDRDATACH0_CR_TXPERBITRANK3_Lane5_WID ( 4) + #define DDRDATACH0_CR_TXPERBITRANK3_Lane5_MSK (0x00F00000) + #define DDRDATACH0_CR_TXPERBITRANK3_Lane5_MAX (0x0000000F) + #define DDRDATACH0_CR_TXPERBITRANK3_Lane6_OFF (24) + #define DDRDATACH0_CR_TXPERBITRANK3_Lane6_WID ( 4) + #define DDRDATACH0_CR_TXPERBITRANK3_Lane6_MSK (0x0F000000) + #define DDRDATACH0_CR_TXPERBITRANK3_Lane6_MAX (0x0000000F) + #define DDRDATACH0_CR_TXPERBITRANK3_Lane7_OFF (28) + #define DDRDATACH0_CR_TXPERBITRANK3_Lane7_WID ( 4) + #define DDRDATACH0_CR_TXPERBITRANK3_Lane7_MSK (0xF0000000) + #define DDRDATACH0_CR_TXPERBITRANK3_Lane7_MAX (0x0000000F) + +#define DDRDATACH0_CR_RCOMPDATA0_REG (0x00003040) + #define DDRDATACH0_CR_RCOMPDATA0_RcompDrvUp_OFF ( 0) + #define DDRDATACH0_CR_RCOMPDATA0_RcompDrvUp_WID ( 6) + #define DDRDATACH0_CR_RCOMPDATA0_RcompDrvUp_MSK (0x0000003F) + #define DDRDATACH0_CR_RCOMPDATA0_RcompDrvUp_MAX (0x0000003F) + #define DDRDATACH0_CR_RCOMPDATA0_Spare0_OFF ( 6) + #define DDRDATACH0_CR_RCOMPDATA0_Spare0_WID ( 3) + #define DDRDATACH0_CR_RCOMPDATA0_Spare0_MSK (0x000001C0) + #define DDRDATACH0_CR_RCOMPDATA0_Spare0_MAX (0x00000007) + #define DDRDATACH0_CR_RCOMPDATA0_RcompDrvDown_OFF ( 9) + #define DDRDATACH0_CR_RCOMPDATA0_RcompDrvDown_WID ( 6) + #define DDRDATACH0_CR_RCOMPDATA0_RcompDrvDown_MSK (0x00007E00) + #define DDRDATACH0_CR_RCOMPDATA0_RcompDrvDown_MAX (0x0000003F) + #define DDRDATACH0_CR_RCOMPDATA0_VTComp_OFF (15) + #define DDRDATACH0_CR_RCOMPDATA0_VTComp_WID ( 5) + #define DDRDATACH0_CR_RCOMPDATA0_VTComp_MSK (0x000F8000) + #define DDRDATACH0_CR_RCOMPDATA0_VTComp_MAX (0x0000001F) + #define DDRDATACH0_CR_RCOMPDATA0_TcoComp_OFF (20) + #define DDRDATACH0_CR_RCOMPDATA0_TcoComp_WID ( 6) + #define DDRDATACH0_CR_RCOMPDATA0_TcoComp_MSK (0x03F00000) + #define DDRDATACH0_CR_RCOMPDATA0_TcoComp_MAX (0x0000003F) + #define DDRDATACH0_CR_RCOMPDATA0_SlewRateComp_OFF (26) + #define DDRDATACH0_CR_RCOMPDATA0_SlewRateComp_WID ( 5) + #define DDRDATACH0_CR_RCOMPDATA0_SlewRateComp_MSK (0x7C000000) + #define DDRDATACH0_CR_RCOMPDATA0_SlewRateComp_MAX (0x0000001F) + #define DDRDATACH0_CR_RCOMPDATA0_Spare2_OFF (31) + #define DDRDATACH0_CR_RCOMPDATA0_Spare2_WID ( 1) + #define DDRDATACH0_CR_RCOMPDATA0_Spare2_MSK (0x80000000) + #define DDRDATACH0_CR_RCOMPDATA0_Spare2_MAX (0x00000001) + +#define DDRDATACH0_CR_RCOMPDATA1_REG (0x00003044) + #define DDRDATACH0_CR_RCOMPDATA1_RcompOdtUp_OFF ( 0) + #define DDRDATACH0_CR_RCOMPDATA1_RcompOdtUp_WID ( 6) + #define DDRDATACH0_CR_RCOMPDATA1_RcompOdtUp_MSK (0x0000003F) + #define DDRDATACH0_CR_RCOMPDATA1_RcompOdtUp_MAX (0x0000003F) + #define DDRDATACH0_CR_RCOMPDATA1_Spare0_OFF ( 6) + #define DDRDATACH0_CR_RCOMPDATA1_Spare0_WID ( 3) + #define DDRDATACH0_CR_RCOMPDATA1_Spare0_MSK (0x000001C0) + #define DDRDATACH0_CR_RCOMPDATA1_Spare0_MAX (0x00000007) + #define DDRDATACH0_CR_RCOMPDATA1_RcompOdtDown_OFF ( 9) + #define DDRDATACH0_CR_RCOMPDATA1_RcompOdtDown_WID ( 6) + #define DDRDATACH0_CR_RCOMPDATA1_RcompOdtDown_MSK (0x00007E00) + #define DDRDATACH0_CR_RCOMPDATA1_RcompOdtDown_MAX (0x0000003F) + #define DDRDATACH0_CR_RCOMPDATA1_Spare1_OFF (15) + #define DDRDATACH0_CR_RCOMPDATA1_Spare1_WID ( 1) + #define DDRDATACH0_CR_RCOMPDATA1_Spare1_MSK (0x00008000) + #define DDRDATACH0_CR_RCOMPDATA1_Spare1_MAX (0x00000001) + #define DDRDATACH0_CR_RCOMPDATA1_PanicDrvDn_OFF (16) + #define DDRDATACH0_CR_RCOMPDATA1_PanicDrvDn_WID ( 6) + #define DDRDATACH0_CR_RCOMPDATA1_PanicDrvDn_MSK (0x003F0000) + #define DDRDATACH0_CR_RCOMPDATA1_PanicDrvDn_MAX (0x0000003F) + #define DDRDATACH0_CR_RCOMPDATA1_PanicDrvUp_OFF (22) + #define DDRDATACH0_CR_RCOMPDATA1_PanicDrvUp_WID ( 6) + #define DDRDATACH0_CR_RCOMPDATA1_PanicDrvUp_MSK (0x0FC00000) + #define DDRDATACH0_CR_RCOMPDATA1_PanicDrvUp_MAX (0x0000003F) + #define DDRDATACH0_CR_RCOMPDATA1_LevelShifterComp_OFF (28) + #define DDRDATACH0_CR_RCOMPDATA1_LevelShifterComp_WID ( 3) + #define DDRDATACH0_CR_RCOMPDATA1_LevelShifterComp_MSK (0x70000000) + #define DDRDATACH0_CR_RCOMPDATA1_LevelShifterComp_MAX (0x00000007) + #define DDRDATACH0_CR_RCOMPDATA1_Spare2_OFF (31) + #define DDRDATACH0_CR_RCOMPDATA1_Spare2_WID ( 1) + #define DDRDATACH0_CR_RCOMPDATA1_Spare2_MSK (0x80000000) + #define DDRDATACH0_CR_RCOMPDATA1_Spare2_MAX (0x00000001) + +#define DDRDATACH0_CR_TXXTALK_REG (0x00003048) + #define DDRDATACH0_CR_TXXTALK_Lane0_OFF ( 0) + #define DDRDATACH0_CR_TXXTALK_Lane0_WID ( 4) + #define DDRDATACH0_CR_TXXTALK_Lane0_MSK (0x0000000F) + #define DDRDATACH0_CR_TXXTALK_Lane0_MAX (0x0000000F) + #define DDRDATACH0_CR_TXXTALK_Lane1_OFF ( 4) + #define DDRDATACH0_CR_TXXTALK_Lane1_WID ( 4) + #define DDRDATACH0_CR_TXXTALK_Lane1_MSK (0x000000F0) + #define DDRDATACH0_CR_TXXTALK_Lane1_MAX (0x0000000F) + #define DDRDATACH0_CR_TXXTALK_Lane2_OFF ( 8) + #define DDRDATACH0_CR_TXXTALK_Lane2_WID ( 4) + #define DDRDATACH0_CR_TXXTALK_Lane2_MSK (0x00000F00) + #define DDRDATACH0_CR_TXXTALK_Lane2_MAX (0x0000000F) + #define DDRDATACH0_CR_TXXTALK_Lane3_OFF (12) + #define DDRDATACH0_CR_TXXTALK_Lane3_WID ( 4) + #define DDRDATACH0_CR_TXXTALK_Lane3_MSK (0x0000F000) + #define DDRDATACH0_CR_TXXTALK_Lane3_MAX (0x0000000F) + #define DDRDATACH0_CR_TXXTALK_Lane4_OFF (16) + #define DDRDATACH0_CR_TXXTALK_Lane4_WID ( 4) + #define DDRDATACH0_CR_TXXTALK_Lane4_MSK (0x000F0000) + #define DDRDATACH0_CR_TXXTALK_Lane4_MAX (0x0000000F) + #define DDRDATACH0_CR_TXXTALK_Lane5_OFF (20) + #define DDRDATACH0_CR_TXXTALK_Lane5_WID ( 4) + #define DDRDATACH0_CR_TXXTALK_Lane5_MSK (0x00F00000) + #define DDRDATACH0_CR_TXXTALK_Lane5_MAX (0x0000000F) + #define DDRDATACH0_CR_TXXTALK_Lane6_OFF (24) + #define DDRDATACH0_CR_TXXTALK_Lane6_WID ( 4) + #define DDRDATACH0_CR_TXXTALK_Lane6_MSK (0x0F000000) + #define DDRDATACH0_CR_TXXTALK_Lane6_MAX (0x0000000F) + #define DDRDATACH0_CR_TXXTALK_Lane7_OFF (28) + #define DDRDATACH0_CR_TXXTALK_Lane7_WID ( 4) + #define DDRDATACH0_CR_TXXTALK_Lane7_MSK (0xF0000000) + #define DDRDATACH0_CR_TXXTALK_Lane7_MAX (0x0000000F) + +#define DDRDATACH0_CR_RXOFFSETVDQ_REG (0x0000304C) + #define DDRDATACH0_CR_RXOFFSETVDQ_Lane0_OFF ( 0) + #define DDRDATACH0_CR_RXOFFSETVDQ_Lane0_WID ( 4) + #define DDRDATACH0_CR_RXOFFSETVDQ_Lane0_MSK (0x0000000F) + #define DDRDATACH0_CR_RXOFFSETVDQ_Lane0_MAX (0x0000000F) + #define DDRDATACH0_CR_RXOFFSETVDQ_Lane1_OFF ( 4) + #define DDRDATACH0_CR_RXOFFSETVDQ_Lane1_WID ( 4) + #define DDRDATACH0_CR_RXOFFSETVDQ_Lane1_MSK (0x000000F0) + #define DDRDATACH0_CR_RXOFFSETVDQ_Lane1_MAX (0x0000000F) + #define DDRDATACH0_CR_RXOFFSETVDQ_Lane2_OFF ( 8) + #define DDRDATACH0_CR_RXOFFSETVDQ_Lane2_WID ( 4) + #define DDRDATACH0_CR_RXOFFSETVDQ_Lane2_MSK (0x00000F00) + #define DDRDATACH0_CR_RXOFFSETVDQ_Lane2_MAX (0x0000000F) + #define DDRDATACH0_CR_RXOFFSETVDQ_Lane3_OFF (12) + #define DDRDATACH0_CR_RXOFFSETVDQ_Lane3_WID ( 4) + #define DDRDATACH0_CR_RXOFFSETVDQ_Lane3_MSK (0x0000F000) + #define DDRDATACH0_CR_RXOFFSETVDQ_Lane3_MAX (0x0000000F) + #define DDRDATACH0_CR_RXOFFSETVDQ_Lane4_OFF (16) + #define DDRDATACH0_CR_RXOFFSETVDQ_Lane4_WID ( 4) + #define DDRDATACH0_CR_RXOFFSETVDQ_Lane4_MSK (0x000F0000) + #define DDRDATACH0_CR_RXOFFSETVDQ_Lane4_MAX (0x0000000F) + #define DDRDATACH0_CR_RXOFFSETVDQ_Lane5_OFF (20) + #define DDRDATACH0_CR_RXOFFSETVDQ_Lane5_WID ( 4) + #define DDRDATACH0_CR_RXOFFSETVDQ_Lane5_MSK (0x00F00000) + #define DDRDATACH0_CR_RXOFFSETVDQ_Lane5_MAX (0x0000000F) + #define DDRDATACH0_CR_RXOFFSETVDQ_Lane6_OFF (24) + #define DDRDATACH0_CR_RXOFFSETVDQ_Lane6_WID ( 4) + #define DDRDATACH0_CR_RXOFFSETVDQ_Lane6_MSK (0x0F000000) + #define DDRDATACH0_CR_RXOFFSETVDQ_Lane6_MAX (0x0000000F) + #define DDRDATACH0_CR_RXOFFSETVDQ_Lane7_OFF (28) + #define DDRDATACH0_CR_RXOFFSETVDQ_Lane7_WID ( 4) + #define DDRDATACH0_CR_RXOFFSETVDQ_Lane7_MSK (0xF0000000) + #define DDRDATACH0_CR_RXOFFSETVDQ_Lane7_MAX (0x0000000F) + +#define DDRDATACH0_CR_DDRDATARESERVED_REG (0x00003050) + #define DDRDATACH0_CR_DDRDATARESERVED_Spare_OFF ( 0) + #define DDRDATACH0_CR_DDRDATARESERVED_Spare_WID (32) + #define DDRDATACH0_CR_DDRDATARESERVED_Spare_MSK (0xFFFFFFFF) + #define DDRDATACH0_CR_DDRDATARESERVED_Spare_MAX (0xFFFFFFFF) + +#define DDRDATACH0_CR_DATATRAINFEEDBACK_REG (0x00003054) + #define DDRDATACH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_OFF ( 0) + #define DDRDATACH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_WID ( 9) + #define DDRDATACH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_MSK (0x000001FF) + #define DDRDATACH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_MAX (0x000001FF) + #define DDRDATACH0_CR_DATATRAINFEEDBACK_Spare_OFF ( 9) + #define DDRDATACH0_CR_DATATRAINFEEDBACK_Spare_WID (23) + #define DDRDATACH0_CR_DATATRAINFEEDBACK_Spare_MSK (0xFFFFFE00) + #define DDRDATACH0_CR_DATATRAINFEEDBACK_Spare_MAX (0x007FFFFF) + +#define DDRDATACH0_CR_DLLPITESTANDADC_REG (0x00003058) + #define DDRDATACH0_CR_DLLPITESTANDADC_RunTest_OFF ( 0) + #define DDRDATACH0_CR_DLLPITESTANDADC_RunTest_WID ( 1) + #define DDRDATACH0_CR_DLLPITESTANDADC_RunTest_MSK (0x00000001) + #define DDRDATACH0_CR_DLLPITESTANDADC_RunTest_MAX (0x00000001) + #define DDRDATACH0_CR_DLLPITESTANDADC_RunTest_DEF (0x00000000) + #define DDRDATACH0_CR_DLLPITESTANDADC_Load_OFF ( 1) + #define DDRDATACH0_CR_DLLPITESTANDADC_Load_WID ( 1) + #define DDRDATACH0_CR_DLLPITESTANDADC_Load_MSK (0x00000002) + #define DDRDATACH0_CR_DLLPITESTANDADC_Load_MAX (0x00000001) + #define DDRDATACH0_CR_DLLPITESTANDADC_Load_DEF (0x00000000) + #define DDRDATACH0_CR_DLLPITESTANDADC_ModeHVM_OFF ( 2) + #define DDRDATACH0_CR_DLLPITESTANDADC_ModeHVM_WID ( 1) + #define DDRDATACH0_CR_DLLPITESTANDADC_ModeHVM_MSK (0x00000004) + #define DDRDATACH0_CR_DLLPITESTANDADC_ModeHVM_MAX (0x00000001) + #define DDRDATACH0_CR_DLLPITESTANDADC_ModeHVM_DEF (0x00000000) + #define DDRDATACH0_CR_DLLPITESTANDADC_ModeDV_OFF ( 3) + #define DDRDATACH0_CR_DLLPITESTANDADC_ModeDV_WID ( 1) + #define DDRDATACH0_CR_DLLPITESTANDADC_ModeDV_MSK (0x00000008) + #define DDRDATACH0_CR_DLLPITESTANDADC_ModeDV_MAX (0x00000001) + #define DDRDATACH0_CR_DLLPITESTANDADC_ModeDV_DEF (0x00000000) + #define DDRDATACH0_CR_DLLPITESTANDADC_ModeADC_OFF ( 4) + #define DDRDATACH0_CR_DLLPITESTANDADC_ModeADC_WID ( 1) + #define DDRDATACH0_CR_DLLPITESTANDADC_ModeADC_MSK (0x00000010) + #define DDRDATACH0_CR_DLLPITESTANDADC_ModeADC_MAX (0x00000001) + #define DDRDATACH0_CR_DLLPITESTANDADC_ModeADC_DEF (0x00000000) + #define DDRDATACH0_CR_DLLPITESTANDADC_LoadCount_OFF ( 5) + #define DDRDATACH0_CR_DLLPITESTANDADC_LoadCount_WID (10) + #define DDRDATACH0_CR_DLLPITESTANDADC_LoadCount_MSK (0x00007FE0) + #define DDRDATACH0_CR_DLLPITESTANDADC_LoadCount_MAX (0x000003FF) + #define DDRDATACH0_CR_DLLPITESTANDADC_CountStatus_OFF (15) + #define DDRDATACH0_CR_DLLPITESTANDADC_CountStatus_WID (10) + #define DDRDATACH0_CR_DLLPITESTANDADC_CountStatus_MSK (0x01FF8000) + #define DDRDATACH0_CR_DLLPITESTANDADC_CountStatus_MAX (0x000003FF) + #define DDRDATACH0_CR_DLLPITESTANDADC_CountStatus_DEF (0x00000000) + #define DDRDATACH0_CR_DLLPITESTANDADC_Spare_OFF (25) + #define DDRDATACH0_CR_DLLPITESTANDADC_Spare_WID ( 7) + #define DDRDATACH0_CR_DLLPITESTANDADC_Spare_MSK (0xFE000000) + #define DDRDATACH0_CR_DLLPITESTANDADC_Spare_MAX (0x0000007F) + +#define DDRDATACH0_CR_DDRCRDATAOFFSETCOMP_REG (0x0000305C) + #define DDRDATACH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_OFF ( 0) + #define DDRDATACH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_WID ( 6) + #define DDRDATACH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MSK (0x0000003F) + #define DDRDATACH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MAX (0x0000003F) + #define DDRDATACH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_DEF (0x00000000) + #define DDRDATACH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_OFF ( 6) + #define DDRDATACH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_WID ( 6) + #define DDRDATACH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MSK (0x00000FC0) + #define DDRDATACH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MAX (0x0000003F) + #define DDRDATACH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_DEF (0x00000000) + #define DDRDATACH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_OFF (12) + #define DDRDATACH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_WID ( 5) + #define DDRDATACH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MSK (0x0001F000) + #define DDRDATACH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MAX (0x0000001F) + #define DDRDATACH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_DEF (0x00000000) + #define DDRDATACH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_OFF (17) + #define DDRDATACH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_WID ( 5) + #define DDRDATACH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MSK (0x003E0000) + #define DDRDATACH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MAX (0x0000001F) + #define DDRDATACH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_DEF (0x00000000) + #define DDRDATACH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_OFF (22) + #define DDRDATACH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_WID ( 5) + #define DDRDATACH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_MSK (0x07C00000) + #define DDRDATACH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_MAX (0x0000001F) + #define DDRDATACH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_DEF (0x00000000) + #define DDRDATACH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_OFF (27) + #define DDRDATACH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_WID ( 5) + #define DDRDATACH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MSK (0xF8000000) + #define DDRDATACH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MAX (0x0000001F) + #define DDRDATACH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_DEF (0x00000000) + +#define DDRDATACH0_CR_DDRCRDATACONTROL1_REG (0x00003060) + #define DDRDATACH0_CR_DDRCRDATACONTROL1_RefPi_OFF ( 0) + #define DDRDATACH0_CR_DDRCRDATACONTROL1_RefPi_WID ( 4) + #define DDRDATACH0_CR_DDRCRDATACONTROL1_RefPi_MSK (0x0000000F) + #define DDRDATACH0_CR_DDRCRDATACONTROL1_RefPi_MAX (0x0000000F) + #define DDRDATACH0_CR_DDRCRDATACONTROL1_RefPi_DEF (0x00000000) + #define DDRDATACH0_CR_DDRCRDATACONTROL1_DllMask_OFF ( 4) + #define DDRDATACH0_CR_DDRCRDATACONTROL1_DllMask_WID ( 2) + #define DDRDATACH0_CR_DDRCRDATACONTROL1_DllMask_MSK (0x00000030) + #define DDRDATACH0_CR_DDRCRDATACONTROL1_DllMask_MAX (0x00000003) + #define DDRDATACH0_CR_DDRCRDATACONTROL1_DllMask_DEF (0x00000000) + #define DDRDATACH0_CR_DDRCRDATACONTROL1_DllWeakLock_OFF ( 6) + #define DDRDATACH0_CR_DDRCRDATACONTROL1_DllWeakLock_WID ( 1) + #define DDRDATACH0_CR_DDRCRDATACONTROL1_DllWeakLock_MSK (0x00000040) + #define DDRDATACH0_CR_DDRCRDATACONTROL1_DllWeakLock_MAX (0x00000001) + #define DDRDATACH0_CR_DDRCRDATACONTROL1_DllWeakLock_DEF (0x00000000) + #define DDRDATACH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_OFF ( 7) + #define DDRDATACH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_WID ( 3) + #define DDRDATACH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MSK (0x00000380) + #define DDRDATACH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MAX (0x00000007) + #define DDRDATACH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_DEF (0x00000000) + #define DDRDATACH0_CR_DDRCRDATACONTROL1_RxBiasCtl_OFF (10) + #define DDRDATACH0_CR_DDRCRDATACONTROL1_RxBiasCtl_WID ( 3) + #define DDRDATACH0_CR_DDRCRDATACONTROL1_RxBiasCtl_MSK (0x00001C00) + #define DDRDATACH0_CR_DDRCRDATACONTROL1_RxBiasCtl_MAX (0x00000007) + #define DDRDATACH0_CR_DDRCRDATACONTROL1_RxBiasCtl_DEF (0x00000000) + #define DDRDATACH0_CR_DDRCRDATACONTROL1_OdtDelay_OFF (13) + #define DDRDATACH0_CR_DDRCRDATACONTROL1_OdtDelay_WID ( 4) + #define DDRDATACH0_CR_DDRCRDATACONTROL1_OdtDelay_MSK (0x0001E000) + #define DDRDATACH0_CR_DDRCRDATACONTROL1_OdtDelay_MAX (0x0000000F) + #define DDRDATACH0_CR_DDRCRDATACONTROL1_OdtDelay_DEF (0x00000000) + #define DDRDATACH0_CR_DDRCRDATACONTROL1_OdtDuration_OFF (17) + #define DDRDATACH0_CR_DDRCRDATACONTROL1_OdtDuration_WID ( 3) + #define DDRDATACH0_CR_DDRCRDATACONTROL1_OdtDuration_MSK (0x000E0000) + #define DDRDATACH0_CR_DDRCRDATACONTROL1_OdtDuration_MAX (0x00000007) + #define DDRDATACH0_CR_DDRCRDATACONTROL1_OdtDuration_DEF (0x00000000) + #define DDRDATACH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_OFF (20) + #define DDRDATACH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_WID ( 4) + #define DDRDATACH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_MSK (0x00F00000) + #define DDRDATACH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_MAX (0x0000000F) + #define DDRDATACH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_DEF (0x00000000) + #define DDRDATACH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_OFF (24) + #define DDRDATACH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_WID ( 3) + #define DDRDATACH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_MSK (0x07000000) + #define DDRDATACH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_MAX (0x00000007) + #define DDRDATACH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_DEF (0x00000000) + #define DDRDATACH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_OFF (27) + #define DDRDATACH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_WID ( 3) + #define DDRDATACH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_MSK (0x38000000) + #define DDRDATACH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_MAX (0x00000007) + #define DDRDATACH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_DEF (0x00000000) + #define DDRDATACH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_OFF (30) + #define DDRDATACH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_WID ( 1) + #define DDRDATACH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_MSK (0x40000000) + #define DDRDATACH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_MAX (0x00000001) + #define DDRDATACH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_DEF (0x00000000) + #define DDRDATACH0_CR_DDRCRDATACONTROL1_Rsvd1_OFF (31) + #define DDRDATACH0_CR_DDRCRDATACONTROL1_Rsvd1_WID ( 1) + #define DDRDATACH0_CR_DDRCRDATACONTROL1_Rsvd1_MSK (0x80000000) + #define DDRDATACH0_CR_DDRCRDATACONTROL1_Rsvd1_MAX (0x00000001) + #define DDRDATACH0_CR_DDRCRDATACONTROL1_Rsvd1_DEF (0x00000000) + +#define DDRDATACH0_CR_DDRCRDATACONTROL2_REG (0x00003064) + #define DDRDATACH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_OFF ( 0) + #define DDRDATACH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_WID ( 5) + #define DDRDATACH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_MSK (0x0000001F) + #define DDRDATACH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_MAX (0x0000001F) + #define DDRDATACH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_DEF (0x00000000) + #define DDRDATACH0_CR_DDRCRDATACONTROL2_ForceBiasOn_OFF ( 5) + #define DDRDATACH0_CR_DDRCRDATACONTROL2_ForceBiasOn_WID ( 1) + #define DDRDATACH0_CR_DDRCRDATACONTROL2_ForceBiasOn_MSK (0x00000020) + #define DDRDATACH0_CR_DDRCRDATACONTROL2_ForceBiasOn_MAX (0x00000001) + #define DDRDATACH0_CR_DDRCRDATACONTROL2_ForceBiasOn_DEF (0x00000000) + #define DDRDATACH0_CR_DDRCRDATACONTROL2_ForceRxOn_OFF ( 6) + #define DDRDATACH0_CR_DDRCRDATACONTROL2_ForceRxOn_WID ( 1) + #define DDRDATACH0_CR_DDRCRDATACONTROL2_ForceRxOn_MSK (0x00000040) + #define DDRDATACH0_CR_DDRCRDATACONTROL2_ForceRxOn_MAX (0x00000001) + #define DDRDATACH0_CR_DDRCRDATACONTROL2_ForceRxOn_DEF (0x00000000) + #define DDRDATACH0_CR_DDRCRDATACONTROL2_LeakerComp_OFF ( 7) + #define DDRDATACH0_CR_DDRCRDATACONTROL2_LeakerComp_WID ( 2) + #define DDRDATACH0_CR_DDRCRDATACONTROL2_LeakerComp_MSK (0x00000180) + #define DDRDATACH0_CR_DDRCRDATACONTROL2_LeakerComp_MAX (0x00000003) + #define DDRDATACH0_CR_DDRCRDATACONTROL2_LeakerComp_DEF (0x00000000) + #define DDRDATACH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_OFF ( 9) + #define DDRDATACH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_WID ( 4) + #define DDRDATACH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_MSK (0x00001E00) + #define DDRDATACH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_MAX (0x0000000F) + #define DDRDATACH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_DEF (0x00000008) + #define DDRDATACH0_CR_DDRCRDATACONTROL2_RxClkStgNum_OFF (13) + #define DDRDATACH0_CR_DDRCRDATACONTROL2_RxClkStgNum_WID ( 5) + #define DDRDATACH0_CR_DDRCRDATACONTROL2_RxClkStgNum_MSK (0x0003E000) + #define DDRDATACH0_CR_DDRCRDATACONTROL2_RxClkStgNum_MAX (0x0000001F) + #define DDRDATACH0_CR_DDRCRDATACONTROL2_RxClkStgNum_DEF (0x00000011) + #define DDRDATACH0_CR_DDRCRDATACONTROL2_WlLongDelEn_OFF (18) + #define DDRDATACH0_CR_DDRCRDATACONTROL2_WlLongDelEn_WID ( 1) + #define DDRDATACH0_CR_DDRCRDATACONTROL2_WlLongDelEn_MSK (0x00040000) + #define DDRDATACH0_CR_DDRCRDATACONTROL2_WlLongDelEn_MAX (0x00000001) + #define DDRDATACH0_CR_DDRCRDATACONTROL2_WlLongDelEn_DEF (0x00000000) + #define DDRDATACH0_CR_DDRCRDATACONTROL2_Spare_OFF (19) + #define DDRDATACH0_CR_DDRCRDATACONTROL2_Spare_WID (13) + #define DDRDATACH0_CR_DDRCRDATACONTROL2_Spare_MSK (0xFFF80000) + #define DDRDATACH0_CR_DDRCRDATACONTROL2_Spare_MAX (0x00001FFF) + #define DDRDATACH0_CR_DDRCRDATACONTROL2_Spare_DEF (0x00000000) + +#define DDRDATACH0_CR_DDRCRVSSHIORVREFCONTROL_REG (0x0000306C) + #define DDRDATACH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_OFF ( 0) + #define DDRDATACH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_WID (24) + #define DDRDATACH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_MSK (0x00FFFFFF) + #define DDRDATACH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_MAX (0x00FFFFFF) + #define DDRDATACH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_DEF (0x00000000) + #define DDRDATACH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_OFF (24) + #define DDRDATACH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_WID ( 8) + #define DDRDATACH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_MSK (0xFF000000) + #define DDRDATACH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_MAX (0x000000FF) + #define DDRDATACH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_DEF (0x00000000) + +#define DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN_REG (0x00003070) + #define DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_OFF ( 0) + #define DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_WID ( 6) + #define DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MSK (0x0000003F) + #define DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MAX (0x0000003F) + #define DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_DEF (0x00000000) + #define DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_OFF ( 6) + #define DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_WID ( 6) + #define DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MSK (0x00000FC0) + #define DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MAX (0x0000003F) + #define DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_DEF (0x00000000) + #define DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_OFF (12) + #define DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_WID ( 6) + #define DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MSK (0x0003F000) + #define DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MAX (0x0000003F) + #define DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_DEF (0x00000000) + #define DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_OFF (18) + #define DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_WID ( 6) + #define DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MSK (0x00FC0000) + #define DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MAX (0x0000003F) + #define DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_DEF (0x00000000) + #define DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_OFF (24) + #define DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_WID ( 7) + #define DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MSK (0x7F000000) + #define DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MAX (0x0000007F) + #define DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_DEF (0x00000000) + #define DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN_Spare_OFF (31) + #define DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN_Spare_WID ( 1) + #define DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN_Spare_MSK (0x80000000) + #define DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN_Spare_MAX (0x00000001) + #define DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN_Spare_DEF (0x00000000) + +#define DDRDATACH0_CR_DDRCRDATACONTROL0_REG (0x00003074) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_RxTrainingMode_OFF ( 0) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_RxTrainingMode_WID ( 1) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_RxTrainingMode_MSK (0x00000001) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_RxTrainingMode_MAX (0x00000001) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_RxTrainingMode_DEF (0x00000000) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_WLTrainingMode_OFF ( 1) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_WLTrainingMode_WID ( 1) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_WLTrainingMode_MSK (0x00000002) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_WLTrainingMode_MAX (0x00000001) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_WLTrainingMode_DEF (0x00000000) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_RLTrainingMode_OFF ( 2) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_RLTrainingMode_WID ( 1) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_RLTrainingMode_MSK (0x00000004) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_RLTrainingMode_MAX (0x00000001) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_RLTrainingMode_DEF (0x00000000) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_OFF ( 3) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_WID ( 1) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MSK (0x00000008) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MAX (0x00000001) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_DEF (0x00000000) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_TxOn_OFF ( 4) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_TxOn_WID ( 1) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_TxOn_MSK (0x00000010) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_TxOn_MAX (0x00000001) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_TxOn_DEF (0x00000000) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_RfOn_OFF ( 5) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_RfOn_WID ( 1) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_RfOn_MSK (0x00000020) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_RfOn_MAX (0x00000001) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_RfOn_DEF (0x00000000) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_RxPiOn_OFF ( 6) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_RxPiOn_WID ( 1) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_RxPiOn_MSK (0x00000040) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_RxPiOn_MAX (0x00000001) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_RxPiOn_DEF (0x00000000) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_TxPiOn_OFF ( 7) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_TxPiOn_WID ( 1) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_TxPiOn_MSK (0x00000080) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_TxPiOn_MAX (0x00000001) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_TxPiOn_DEF (0x00000000) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_InternalClocksOn_OFF ( 8) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_InternalClocksOn_WID ( 1) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_InternalClocksOn_MSK (0x00000100) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_InternalClocksOn_MAX (0x00000001) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_InternalClocksOn_DEF (0x00000000) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_OFF ( 9) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_WID ( 1) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MSK (0x00000200) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MAX (0x00000001) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_DEF (0x00000000) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_TxDisable_OFF (10) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_TxDisable_WID ( 1) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_TxDisable_MSK (0x00000400) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_TxDisable_MAX (0x00000001) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_TxDisable_DEF (0x00000000) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_RxDisable_OFF (11) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_RxDisable_WID ( 1) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_RxDisable_MSK (0x00000800) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_RxDisable_MAX (0x00000001) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_RxDisable_DEF (0x00000000) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_TxLong_OFF (12) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_TxLong_WID ( 1) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_TxLong_MSK (0x00001000) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_TxLong_MAX (0x00000001) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_TxLong_DEF (0x00000000) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_RxDqsCtle_OFF (13) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_RxDqsCtle_WID ( 2) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_RxDqsCtle_MSK (0x00006000) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_RxDqsCtle_MAX (0x00000003) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_RxDqsCtle_DEF (0x00000000) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_RxReadPointer_OFF (15) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_RxReadPointer_WID ( 3) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_RxReadPointer_MSK (0x00038000) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_RxReadPointer_MAX (0x00000007) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_RxReadPointer_DEF (0x00000000) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_OFF (18) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_WID ( 1) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_MSK (0x00040000) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_MAX (0x00000001) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_DEF (0x00000000) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_DataVccddqHi_OFF (19) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_DataVccddqHi_WID ( 1) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_DataVccddqHi_MSK (0x00080000) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_DataVccddqHi_MAX (0x00000001) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_DataVccddqHi_DEF (0x00000000) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_ReadRFRd_OFF (20) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_ReadRFRd_WID ( 1) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_ReadRFRd_MSK (0x00100000) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_ReadRFRd_MAX (0x00000001) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_ReadRFRd_DEF (0x00000000) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_ReadRFWr_OFF (21) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_ReadRFWr_WID ( 1) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_ReadRFWr_MSK (0x00200000) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_ReadRFWr_MAX (0x00000001) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_ReadRFWr_DEF (0x00000000) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_ReadRFRank_OFF (22) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_ReadRFRank_WID ( 2) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_ReadRFRank_MSK (0x00C00000) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_ReadRFRank_MAX (0x00000003) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_ReadRFRank_DEF (0x00000000) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_ForceOdtOn_OFF (24) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_ForceOdtOn_WID ( 1) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_ForceOdtOn_MSK (0x01000000) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_ForceOdtOn_MAX (0x00000001) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_ForceOdtOn_DEF (0x00000000) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_OdtSampOff_OFF (25) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_OdtSampOff_WID ( 1) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_OdtSampOff_MSK (0x02000000) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_OdtSampOff_MAX (0x00000001) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_OdtSampOff_DEF (0x00000000) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_OFF (26) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_WID ( 1) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_MSK (0x04000000) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_MAX (0x00000001) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_DEF (0x00000000) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_OFF (27) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_WID ( 1) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MSK (0x08000000) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MAX (0x00000001) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_DEF (0x00000000) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_OFF (28) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_WID ( 1) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_MSK (0x10000000) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_MAX (0x00000001) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_DEF (0x00000000) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_EnReadPreamble_OFF (29) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_EnReadPreamble_WID ( 1) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_EnReadPreamble_MSK (0x20000000) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_EnReadPreamble_MAX (0x00000001) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_EnReadPreamble_DEF (0x00000000) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_OFF (30) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_WID ( 1) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MSK (0x40000000) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MAX (0x00000001) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_DEF (0x00000000) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_OFF (31) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_WID ( 1) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_MSK (0x80000000) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_MAX (0x00000001) + #define DDRDATACH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_DEF (0x00000000) + +#define DDRDATACH0_CR_DDRCRVREFADJUST1_REG (0x00003078) + #define DDRDATACH0_CR_DDRCRVREFADJUST1_CAVrefCtl_OFF ( 0) + #define DDRDATACH0_CR_DDRCRVREFADJUST1_CAVrefCtl_WID ( 7) + #define DDRDATACH0_CR_DDRCRVREFADJUST1_CAVrefCtl_MSK (0x0000007F) + #define DDRDATACH0_CR_DDRCRVREFADJUST1_CAVrefCtl_MAX (0x0000007F) + #define DDRDATACH0_CR_DDRCRVREFADJUST1_CAVrefCtl_DEF (0x00000000) + #define DDRDATACH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_OFF ( 7) + #define DDRDATACH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_WID ( 7) + #define DDRDATACH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_MSK (0x00003F80) + #define DDRDATACH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_MAX (0x0000007F) + #define DDRDATACH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_DEF (0x00000000) + #define DDRDATACH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_OFF (14) + #define DDRDATACH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_WID ( 7) + #define DDRDATACH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_MSK (0x001FC000) + #define DDRDATACH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_MAX (0x0000007F) + #define DDRDATACH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_DEF (0x00000000) + #define DDRDATACH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_OFF (21) + #define DDRDATACH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_WID ( 1) + #define DDRDATACH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_MSK (0x00200000) + #define DDRDATACH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_MAX (0x00000001) + #define DDRDATACH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_DEF (0x00000000) + #define DDRDATACH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_OFF (22) + #define DDRDATACH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_WID ( 1) + #define DDRDATACH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_MSK (0x00400000) + #define DDRDATACH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_MAX (0x00000001) + #define DDRDATACH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_DEF (0x00000000) + #define DDRDATACH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_OFF (23) + #define DDRDATACH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_WID ( 1) + #define DDRDATACH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_MSK (0x00800000) + #define DDRDATACH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_MAX (0x00000001) + #define DDRDATACH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_DEF (0x00000000) + #define DDRDATACH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_OFF (24) + #define DDRDATACH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_WID ( 2) + #define DDRDATACH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_MSK (0x03000000) + #define DDRDATACH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_MAX (0x00000003) + #define DDRDATACH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_DEF (0x00000000) + #define DDRDATACH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_OFF (26) + #define DDRDATACH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_WID ( 1) + #define DDRDATACH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_MSK (0x04000000) + #define DDRDATACH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_MAX (0x00000001) + #define DDRDATACH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_DEF (0x00000000) + #define DDRDATACH0_CR_DDRCRVREFADJUST1_Rsvd_OFF (27) + #define DDRDATACH0_CR_DDRCRVREFADJUST1_Rsvd_WID ( 2) + #define DDRDATACH0_CR_DDRCRVREFADJUST1_Rsvd_MSK (0x18000000) + #define DDRDATACH0_CR_DDRCRVREFADJUST1_Rsvd_MAX (0x00000003) + #define DDRDATACH0_CR_DDRCRVREFADJUST1_Rsvd_DEF (0x00000000) + #define DDRDATACH0_CR_DDRCRVREFADJUST1_caSlowBW_OFF (29) + #define DDRDATACH0_CR_DDRCRVREFADJUST1_caSlowBW_WID ( 1) + #define DDRDATACH0_CR_DDRCRVREFADJUST1_caSlowBW_MSK (0x20000000) + #define DDRDATACH0_CR_DDRCRVREFADJUST1_caSlowBW_MAX (0x00000001) + #define DDRDATACH0_CR_DDRCRVREFADJUST1_caSlowBW_DEF (0x00000000) + #define DDRDATACH0_CR_DDRCRVREFADJUST1_ch0SlowBW_OFF (30) + #define DDRDATACH0_CR_DDRCRVREFADJUST1_ch0SlowBW_WID ( 1) + #define DDRDATACH0_CR_DDRCRVREFADJUST1_ch0SlowBW_MSK (0x40000000) + #define DDRDATACH0_CR_DDRCRVREFADJUST1_ch0SlowBW_MAX (0x00000001) + #define DDRDATACH0_CR_DDRCRVREFADJUST1_ch0SlowBW_DEF (0x00000000) + #define DDRDATACH0_CR_DDRCRVREFADJUST1_ch1SlowBW_OFF (31) + #define DDRDATACH0_CR_DDRCRVREFADJUST1_ch1SlowBW_WID ( 1) + #define DDRDATACH0_CR_DDRCRVREFADJUST1_ch1SlowBW_MSK (0x80000000) + #define DDRDATACH0_CR_DDRCRVREFADJUST1_ch1SlowBW_MAX (0x00000001) + #define DDRDATACH0_CR_DDRCRVREFADJUST1_ch1SlowBW_DEF (0x00000000) + +#define DDRDATACH1_CR_RXTRAINRANK0_REG (0x00003100) + #define DDRDATACH1_CR_RXTRAINRANK0_RxRcvEnPi_OFF ( 0) + #define DDRDATACH1_CR_RXTRAINRANK0_RxRcvEnPi_WID ( 9) + #define DDRDATACH1_CR_RXTRAINRANK0_RxRcvEnPi_MSK (0x000001FF) + #define DDRDATACH1_CR_RXTRAINRANK0_RxRcvEnPi_MAX (0x000001FF) + #define DDRDATACH1_CR_RXTRAINRANK0_RxDqsPPi_OFF ( 9) + #define DDRDATACH1_CR_RXTRAINRANK0_RxDqsPPi_WID ( 6) + #define DDRDATACH1_CR_RXTRAINRANK0_RxDqsPPi_MSK (0x00007E00) + #define DDRDATACH1_CR_RXTRAINRANK0_RxDqsPPi_MAX (0x0000003F) + #define DDRDATACH1_CR_RXTRAINRANK0_RxEq_OFF (15) + #define DDRDATACH1_CR_RXTRAINRANK0_RxEq_WID ( 5) + #define DDRDATACH1_CR_RXTRAINRANK0_RxEq_MSK (0x000F8000) + #define DDRDATACH1_CR_RXTRAINRANK0_RxEq_MAX (0x0000001F) + #define DDRDATACH1_CR_RXTRAINRANK0_RxDqsNPi_OFF (20) + #define DDRDATACH1_CR_RXTRAINRANK0_RxDqsNPi_WID ( 6) + #define DDRDATACH1_CR_RXTRAINRANK0_RxDqsNPi_MSK (0x03F00000) + #define DDRDATACH1_CR_RXTRAINRANK0_RxDqsNPi_MAX (0x0000003F) + #define DDRDATACH1_CR_RXTRAINRANK0_RxVref_OFF (26) + #define DDRDATACH1_CR_RXTRAINRANK0_RxVref_WID ( 6) + #define DDRDATACH1_CR_RXTRAINRANK0_RxVref_MSK (0xFC000000) + #define DDRDATACH1_CR_RXTRAINRANK0_RxVref_MAX (0x0000003F) + +#define DDRDATACH1_CR_RXTRAINRANK1_REG (0x00003104) + #define DDRDATACH1_CR_RXTRAINRANK1_RxRcvEnPi_OFF ( 0) + #define DDRDATACH1_CR_RXTRAINRANK1_RxRcvEnPi_WID ( 9) + #define DDRDATACH1_CR_RXTRAINRANK1_RxRcvEnPi_MSK (0x000001FF) + #define DDRDATACH1_CR_RXTRAINRANK1_RxRcvEnPi_MAX (0x000001FF) + #define DDRDATACH1_CR_RXTRAINRANK1_RxDqsPPi_OFF ( 9) + #define DDRDATACH1_CR_RXTRAINRANK1_RxDqsPPi_WID ( 6) + #define DDRDATACH1_CR_RXTRAINRANK1_RxDqsPPi_MSK (0x00007E00) + #define DDRDATACH1_CR_RXTRAINRANK1_RxDqsPPi_MAX (0x0000003F) + #define DDRDATACH1_CR_RXTRAINRANK1_RxEq_OFF (15) + #define DDRDATACH1_CR_RXTRAINRANK1_RxEq_WID ( 5) + #define DDRDATACH1_CR_RXTRAINRANK1_RxEq_MSK (0x000F8000) + #define DDRDATACH1_CR_RXTRAINRANK1_RxEq_MAX (0x0000001F) + #define DDRDATACH1_CR_RXTRAINRANK1_RxDqsNPi_OFF (20) + #define DDRDATACH1_CR_RXTRAINRANK1_RxDqsNPi_WID ( 6) + #define DDRDATACH1_CR_RXTRAINRANK1_RxDqsNPi_MSK (0x03F00000) + #define DDRDATACH1_CR_RXTRAINRANK1_RxDqsNPi_MAX (0x0000003F) + #define DDRDATACH1_CR_RXTRAINRANK1_RxVref_OFF (26) + #define DDRDATACH1_CR_RXTRAINRANK1_RxVref_WID ( 6) + #define DDRDATACH1_CR_RXTRAINRANK1_RxVref_MSK (0xFC000000) + #define DDRDATACH1_CR_RXTRAINRANK1_RxVref_MAX (0x0000003F) + +#define DDRDATACH1_CR_RXTRAINRANK2_REG (0x00003108) + #define DDRDATACH1_CR_RXTRAINRANK2_RxRcvEnPi_OFF ( 0) + #define DDRDATACH1_CR_RXTRAINRANK2_RxRcvEnPi_WID ( 9) + #define DDRDATACH1_CR_RXTRAINRANK2_RxRcvEnPi_MSK (0x000001FF) + #define DDRDATACH1_CR_RXTRAINRANK2_RxRcvEnPi_MAX (0x000001FF) + #define DDRDATACH1_CR_RXTRAINRANK2_RxDqsPPi_OFF ( 9) + #define DDRDATACH1_CR_RXTRAINRANK2_RxDqsPPi_WID ( 6) + #define DDRDATACH1_CR_RXTRAINRANK2_RxDqsPPi_MSK (0x00007E00) + #define DDRDATACH1_CR_RXTRAINRANK2_RxDqsPPi_MAX (0x0000003F) + #define DDRDATACH1_CR_RXTRAINRANK2_RxEq_OFF (15) + #define DDRDATACH1_CR_RXTRAINRANK2_RxEq_WID ( 5) + #define DDRDATACH1_CR_RXTRAINRANK2_RxEq_MSK (0x000F8000) + #define DDRDATACH1_CR_RXTRAINRANK2_RxEq_MAX (0x0000001F) + #define DDRDATACH1_CR_RXTRAINRANK2_RxDqsNPi_OFF (20) + #define DDRDATACH1_CR_RXTRAINRANK2_RxDqsNPi_WID ( 6) + #define DDRDATACH1_CR_RXTRAINRANK2_RxDqsNPi_MSK (0x03F00000) + #define DDRDATACH1_CR_RXTRAINRANK2_RxDqsNPi_MAX (0x0000003F) + #define DDRDATACH1_CR_RXTRAINRANK2_RxVref_OFF (26) + #define DDRDATACH1_CR_RXTRAINRANK2_RxVref_WID ( 6) + #define DDRDATACH1_CR_RXTRAINRANK2_RxVref_MSK (0xFC000000) + #define DDRDATACH1_CR_RXTRAINRANK2_RxVref_MAX (0x0000003F) + +#define DDRDATACH1_CR_RXTRAINRANK3_REG (0x0000310C) + #define DDRDATACH1_CR_RXTRAINRANK3_RxRcvEnPi_OFF ( 0) + #define DDRDATACH1_CR_RXTRAINRANK3_RxRcvEnPi_WID ( 9) + #define DDRDATACH1_CR_RXTRAINRANK3_RxRcvEnPi_MSK (0x000001FF) + #define DDRDATACH1_CR_RXTRAINRANK3_RxRcvEnPi_MAX (0x000001FF) + #define DDRDATACH1_CR_RXTRAINRANK3_RxDqsPPi_OFF ( 9) + #define DDRDATACH1_CR_RXTRAINRANK3_RxDqsPPi_WID ( 6) + #define DDRDATACH1_CR_RXTRAINRANK3_RxDqsPPi_MSK (0x00007E00) + #define DDRDATACH1_CR_RXTRAINRANK3_RxDqsPPi_MAX (0x0000003F) + #define DDRDATACH1_CR_RXTRAINRANK3_RxEq_OFF (15) + #define DDRDATACH1_CR_RXTRAINRANK3_RxEq_WID ( 5) + #define DDRDATACH1_CR_RXTRAINRANK3_RxEq_MSK (0x000F8000) + #define DDRDATACH1_CR_RXTRAINRANK3_RxEq_MAX (0x0000001F) + #define DDRDATACH1_CR_RXTRAINRANK3_RxDqsNPi_OFF (20) + #define DDRDATACH1_CR_RXTRAINRANK3_RxDqsNPi_WID ( 6) + #define DDRDATACH1_CR_RXTRAINRANK3_RxDqsNPi_MSK (0x03F00000) + #define DDRDATACH1_CR_RXTRAINRANK3_RxDqsNPi_MAX (0x0000003F) + #define DDRDATACH1_CR_RXTRAINRANK3_RxVref_OFF (26) + #define DDRDATACH1_CR_RXTRAINRANK3_RxVref_WID ( 6) + #define DDRDATACH1_CR_RXTRAINRANK3_RxVref_MSK (0xFC000000) + #define DDRDATACH1_CR_RXTRAINRANK3_RxVref_MAX (0x0000003F) + +#define DDRDATACH1_CR_RXPERBITRANK0_REG (0x00003110) + #define DDRDATACH1_CR_RXPERBITRANK0_Lane0_OFF ( 0) + #define DDRDATACH1_CR_RXPERBITRANK0_Lane0_WID ( 4) + #define DDRDATACH1_CR_RXPERBITRANK0_Lane0_MSK (0x0000000F) + #define DDRDATACH1_CR_RXPERBITRANK0_Lane0_MAX (0x0000000F) + #define DDRDATACH1_CR_RXPERBITRANK0_Lane1_OFF ( 4) + #define DDRDATACH1_CR_RXPERBITRANK0_Lane1_WID ( 4) + #define DDRDATACH1_CR_RXPERBITRANK0_Lane1_MSK (0x000000F0) + #define DDRDATACH1_CR_RXPERBITRANK0_Lane1_MAX (0x0000000F) + #define DDRDATACH1_CR_RXPERBITRANK0_Lane2_OFF ( 8) + #define DDRDATACH1_CR_RXPERBITRANK0_Lane2_WID ( 4) + #define DDRDATACH1_CR_RXPERBITRANK0_Lane2_MSK (0x00000F00) + #define DDRDATACH1_CR_RXPERBITRANK0_Lane2_MAX (0x0000000F) + #define DDRDATACH1_CR_RXPERBITRANK0_Lane3_OFF (12) + #define DDRDATACH1_CR_RXPERBITRANK0_Lane3_WID ( 4) + #define DDRDATACH1_CR_RXPERBITRANK0_Lane3_MSK (0x0000F000) + #define DDRDATACH1_CR_RXPERBITRANK0_Lane3_MAX (0x0000000F) + #define DDRDATACH1_CR_RXPERBITRANK0_Lane4_OFF (16) + #define DDRDATACH1_CR_RXPERBITRANK0_Lane4_WID ( 4) + #define DDRDATACH1_CR_RXPERBITRANK0_Lane4_MSK (0x000F0000) + #define DDRDATACH1_CR_RXPERBITRANK0_Lane4_MAX (0x0000000F) + #define DDRDATACH1_CR_RXPERBITRANK0_Lane5_OFF (20) + #define DDRDATACH1_CR_RXPERBITRANK0_Lane5_WID ( 4) + #define DDRDATACH1_CR_RXPERBITRANK0_Lane5_MSK (0x00F00000) + #define DDRDATACH1_CR_RXPERBITRANK0_Lane5_MAX (0x0000000F) + #define DDRDATACH1_CR_RXPERBITRANK0_Lane6_OFF (24) + #define DDRDATACH1_CR_RXPERBITRANK0_Lane6_WID ( 4) + #define DDRDATACH1_CR_RXPERBITRANK0_Lane6_MSK (0x0F000000) + #define DDRDATACH1_CR_RXPERBITRANK0_Lane6_MAX (0x0000000F) + #define DDRDATACH1_CR_RXPERBITRANK0_Lane7_OFF (28) + #define DDRDATACH1_CR_RXPERBITRANK0_Lane7_WID ( 4) + #define DDRDATACH1_CR_RXPERBITRANK0_Lane7_MSK (0xF0000000) + #define DDRDATACH1_CR_RXPERBITRANK0_Lane7_MAX (0x0000000F) + +#define DDRDATACH1_CR_RXPERBITRANK1_REG (0x00003114) + #define DDRDATACH1_CR_RXPERBITRANK1_Lane0_OFF ( 0) + #define DDRDATACH1_CR_RXPERBITRANK1_Lane0_WID ( 4) + #define DDRDATACH1_CR_RXPERBITRANK1_Lane0_MSK (0x0000000F) + #define DDRDATACH1_CR_RXPERBITRANK1_Lane0_MAX (0x0000000F) + #define DDRDATACH1_CR_RXPERBITRANK1_Lane1_OFF ( 4) + #define DDRDATACH1_CR_RXPERBITRANK1_Lane1_WID ( 4) + #define DDRDATACH1_CR_RXPERBITRANK1_Lane1_MSK (0x000000F0) + #define DDRDATACH1_CR_RXPERBITRANK1_Lane1_MAX (0x0000000F) + #define DDRDATACH1_CR_RXPERBITRANK1_Lane2_OFF ( 8) + #define DDRDATACH1_CR_RXPERBITRANK1_Lane2_WID ( 4) + #define DDRDATACH1_CR_RXPERBITRANK1_Lane2_MSK (0x00000F00) + #define DDRDATACH1_CR_RXPERBITRANK1_Lane2_MAX (0x0000000F) + #define DDRDATACH1_CR_RXPERBITRANK1_Lane3_OFF (12) + #define DDRDATACH1_CR_RXPERBITRANK1_Lane3_WID ( 4) + #define DDRDATACH1_CR_RXPERBITRANK1_Lane3_MSK (0x0000F000) + #define DDRDATACH1_CR_RXPERBITRANK1_Lane3_MAX (0x0000000F) + #define DDRDATACH1_CR_RXPERBITRANK1_Lane4_OFF (16) + #define DDRDATACH1_CR_RXPERBITRANK1_Lane4_WID ( 4) + #define DDRDATACH1_CR_RXPERBITRANK1_Lane4_MSK (0x000F0000) + #define DDRDATACH1_CR_RXPERBITRANK1_Lane4_MAX (0x0000000F) + #define DDRDATACH1_CR_RXPERBITRANK1_Lane5_OFF (20) + #define DDRDATACH1_CR_RXPERBITRANK1_Lane5_WID ( 4) + #define DDRDATACH1_CR_RXPERBITRANK1_Lane5_MSK (0x00F00000) + #define DDRDATACH1_CR_RXPERBITRANK1_Lane5_MAX (0x0000000F) + #define DDRDATACH1_CR_RXPERBITRANK1_Lane6_OFF (24) + #define DDRDATACH1_CR_RXPERBITRANK1_Lane6_WID ( 4) + #define DDRDATACH1_CR_RXPERBITRANK1_Lane6_MSK (0x0F000000) + #define DDRDATACH1_CR_RXPERBITRANK1_Lane6_MAX (0x0000000F) + #define DDRDATACH1_CR_RXPERBITRANK1_Lane7_OFF (28) + #define DDRDATACH1_CR_RXPERBITRANK1_Lane7_WID ( 4) + #define DDRDATACH1_CR_RXPERBITRANK1_Lane7_MSK (0xF0000000) + #define DDRDATACH1_CR_RXPERBITRANK1_Lane7_MAX (0x0000000F) + +#define DDRDATACH1_CR_RXPERBITRANK2_REG (0x00003118) + #define DDRDATACH1_CR_RXPERBITRANK2_Lane0_OFF ( 0) + #define DDRDATACH1_CR_RXPERBITRANK2_Lane0_WID ( 4) + #define DDRDATACH1_CR_RXPERBITRANK2_Lane0_MSK (0x0000000F) + #define DDRDATACH1_CR_RXPERBITRANK2_Lane0_MAX (0x0000000F) + #define DDRDATACH1_CR_RXPERBITRANK2_Lane1_OFF ( 4) + #define DDRDATACH1_CR_RXPERBITRANK2_Lane1_WID ( 4) + #define DDRDATACH1_CR_RXPERBITRANK2_Lane1_MSK (0x000000F0) + #define DDRDATACH1_CR_RXPERBITRANK2_Lane1_MAX (0x0000000F) + #define DDRDATACH1_CR_RXPERBITRANK2_Lane2_OFF ( 8) + #define DDRDATACH1_CR_RXPERBITRANK2_Lane2_WID ( 4) + #define DDRDATACH1_CR_RXPERBITRANK2_Lane2_MSK (0x00000F00) + #define DDRDATACH1_CR_RXPERBITRANK2_Lane2_MAX (0x0000000F) + #define DDRDATACH1_CR_RXPERBITRANK2_Lane3_OFF (12) + #define DDRDATACH1_CR_RXPERBITRANK2_Lane3_WID ( 4) + #define DDRDATACH1_CR_RXPERBITRANK2_Lane3_MSK (0x0000F000) + #define DDRDATACH1_CR_RXPERBITRANK2_Lane3_MAX (0x0000000F) + #define DDRDATACH1_CR_RXPERBITRANK2_Lane4_OFF (16) + #define DDRDATACH1_CR_RXPERBITRANK2_Lane4_WID ( 4) + #define DDRDATACH1_CR_RXPERBITRANK2_Lane4_MSK (0x000F0000) + #define DDRDATACH1_CR_RXPERBITRANK2_Lane4_MAX (0x0000000F) + #define DDRDATACH1_CR_RXPERBITRANK2_Lane5_OFF (20) + #define DDRDATACH1_CR_RXPERBITRANK2_Lane5_WID ( 4) + #define DDRDATACH1_CR_RXPERBITRANK2_Lane5_MSK (0x00F00000) + #define DDRDATACH1_CR_RXPERBITRANK2_Lane5_MAX (0x0000000F) + #define DDRDATACH1_CR_RXPERBITRANK2_Lane6_OFF (24) + #define DDRDATACH1_CR_RXPERBITRANK2_Lane6_WID ( 4) + #define DDRDATACH1_CR_RXPERBITRANK2_Lane6_MSK (0x0F000000) + #define DDRDATACH1_CR_RXPERBITRANK2_Lane6_MAX (0x0000000F) + #define DDRDATACH1_CR_RXPERBITRANK2_Lane7_OFF (28) + #define DDRDATACH1_CR_RXPERBITRANK2_Lane7_WID ( 4) + #define DDRDATACH1_CR_RXPERBITRANK2_Lane7_MSK (0xF0000000) + #define DDRDATACH1_CR_RXPERBITRANK2_Lane7_MAX (0x0000000F) + +#define DDRDATACH1_CR_RXPERBITRANK3_REG (0x0000311C) + #define DDRDATACH1_CR_RXPERBITRANK3_Lane0_OFF ( 0) + #define DDRDATACH1_CR_RXPERBITRANK3_Lane0_WID ( 4) + #define DDRDATACH1_CR_RXPERBITRANK3_Lane0_MSK (0x0000000F) + #define DDRDATACH1_CR_RXPERBITRANK3_Lane0_MAX (0x0000000F) + #define DDRDATACH1_CR_RXPERBITRANK3_Lane1_OFF ( 4) + #define DDRDATACH1_CR_RXPERBITRANK3_Lane1_WID ( 4) + #define DDRDATACH1_CR_RXPERBITRANK3_Lane1_MSK (0x000000F0) + #define DDRDATACH1_CR_RXPERBITRANK3_Lane1_MAX (0x0000000F) + #define DDRDATACH1_CR_RXPERBITRANK3_Lane2_OFF ( 8) + #define DDRDATACH1_CR_RXPERBITRANK3_Lane2_WID ( 4) + #define DDRDATACH1_CR_RXPERBITRANK3_Lane2_MSK (0x00000F00) + #define DDRDATACH1_CR_RXPERBITRANK3_Lane2_MAX (0x0000000F) + #define DDRDATACH1_CR_RXPERBITRANK3_Lane3_OFF (12) + #define DDRDATACH1_CR_RXPERBITRANK3_Lane3_WID ( 4) + #define DDRDATACH1_CR_RXPERBITRANK3_Lane3_MSK (0x0000F000) + #define DDRDATACH1_CR_RXPERBITRANK3_Lane3_MAX (0x0000000F) + #define DDRDATACH1_CR_RXPERBITRANK3_Lane4_OFF (16) + #define DDRDATACH1_CR_RXPERBITRANK3_Lane4_WID ( 4) + #define DDRDATACH1_CR_RXPERBITRANK3_Lane4_MSK (0x000F0000) + #define DDRDATACH1_CR_RXPERBITRANK3_Lane4_MAX (0x0000000F) + #define DDRDATACH1_CR_RXPERBITRANK3_Lane5_OFF (20) + #define DDRDATACH1_CR_RXPERBITRANK3_Lane5_WID ( 4) + #define DDRDATACH1_CR_RXPERBITRANK3_Lane5_MSK (0x00F00000) + #define DDRDATACH1_CR_RXPERBITRANK3_Lane5_MAX (0x0000000F) + #define DDRDATACH1_CR_RXPERBITRANK3_Lane6_OFF (24) + #define DDRDATACH1_CR_RXPERBITRANK3_Lane6_WID ( 4) + #define DDRDATACH1_CR_RXPERBITRANK3_Lane6_MSK (0x0F000000) + #define DDRDATACH1_CR_RXPERBITRANK3_Lane6_MAX (0x0000000F) + #define DDRDATACH1_CR_RXPERBITRANK3_Lane7_OFF (28) + #define DDRDATACH1_CR_RXPERBITRANK3_Lane7_WID ( 4) + #define DDRDATACH1_CR_RXPERBITRANK3_Lane7_MSK (0xF0000000) + #define DDRDATACH1_CR_RXPERBITRANK3_Lane7_MAX (0x0000000F) + +#define DDRDATACH1_CR_TXTRAINRANK0_REG (0x00003120) + #define DDRDATACH1_CR_TXTRAINRANK0_TxDqDelay_OFF ( 0) + #define DDRDATACH1_CR_TXTRAINRANK0_TxDqDelay_WID ( 9) + #define DDRDATACH1_CR_TXTRAINRANK0_TxDqDelay_MSK (0x000001FF) + #define DDRDATACH1_CR_TXTRAINRANK0_TxDqDelay_MAX (0x000001FF) + #define DDRDATACH1_CR_TXTRAINRANK0_TxDqsDelay_OFF ( 9) + #define DDRDATACH1_CR_TXTRAINRANK0_TxDqsDelay_WID ( 9) + #define DDRDATACH1_CR_TXTRAINRANK0_TxDqsDelay_MSK (0x0003FE00) + #define DDRDATACH1_CR_TXTRAINRANK0_TxDqsDelay_MAX (0x000001FF) + #define DDRDATACH1_CR_TXTRAINRANK0_Spare0_OFF (18) + #define DDRDATACH1_CR_TXTRAINRANK0_Spare0_WID ( 2) + #define DDRDATACH1_CR_TXTRAINRANK0_Spare0_MSK (0x000C0000) + #define DDRDATACH1_CR_TXTRAINRANK0_Spare0_MAX (0x00000003) + #define DDRDATACH1_CR_TXTRAINRANK0_TxEqualization_OFF (20) + #define DDRDATACH1_CR_TXTRAINRANK0_TxEqualization_WID ( 6) + #define DDRDATACH1_CR_TXTRAINRANK0_TxEqualization_MSK (0x03F00000) + #define DDRDATACH1_CR_TXTRAINRANK0_TxEqualization_MAX (0x0000003F) + #define DDRDATACH1_CR_TXTRAINRANK0_Spare1_OFF (26) + #define DDRDATACH1_CR_TXTRAINRANK0_Spare1_WID ( 6) + #define DDRDATACH1_CR_TXTRAINRANK0_Spare1_MSK (0xFC000000) + #define DDRDATACH1_CR_TXTRAINRANK0_Spare1_MAX (0x0000003F) + +#define DDRDATACH1_CR_TXTRAINRANK1_REG (0x00003124) + #define DDRDATACH1_CR_TXTRAINRANK1_TxDqDelay_OFF ( 0) + #define DDRDATACH1_CR_TXTRAINRANK1_TxDqDelay_WID ( 9) + #define DDRDATACH1_CR_TXTRAINRANK1_TxDqDelay_MSK (0x000001FF) + #define DDRDATACH1_CR_TXTRAINRANK1_TxDqDelay_MAX (0x000001FF) + #define DDRDATACH1_CR_TXTRAINRANK1_TxDqsDelay_OFF ( 9) + #define DDRDATACH1_CR_TXTRAINRANK1_TxDqsDelay_WID ( 9) + #define DDRDATACH1_CR_TXTRAINRANK1_TxDqsDelay_MSK (0x0003FE00) + #define DDRDATACH1_CR_TXTRAINRANK1_TxDqsDelay_MAX (0x000001FF) + #define DDRDATACH1_CR_TXTRAINRANK1_Spare0_OFF (18) + #define DDRDATACH1_CR_TXTRAINRANK1_Spare0_WID ( 2) + #define DDRDATACH1_CR_TXTRAINRANK1_Spare0_MSK (0x000C0000) + #define DDRDATACH1_CR_TXTRAINRANK1_Spare0_MAX (0x00000003) + #define DDRDATACH1_CR_TXTRAINRANK1_TxEqualization_OFF (20) + #define DDRDATACH1_CR_TXTRAINRANK1_TxEqualization_WID ( 6) + #define DDRDATACH1_CR_TXTRAINRANK1_TxEqualization_MSK (0x03F00000) + #define DDRDATACH1_CR_TXTRAINRANK1_TxEqualization_MAX (0x0000003F) + #define DDRDATACH1_CR_TXTRAINRANK1_Spare1_OFF (26) + #define DDRDATACH1_CR_TXTRAINRANK1_Spare1_WID ( 6) + #define DDRDATACH1_CR_TXTRAINRANK1_Spare1_MSK (0xFC000000) + #define DDRDATACH1_CR_TXTRAINRANK1_Spare1_MAX (0x0000003F) + +#define DDRDATACH1_CR_TXTRAINRANK2_REG (0x00003128) + #define DDRDATACH1_CR_TXTRAINRANK2_TxDqDelay_OFF ( 0) + #define DDRDATACH1_CR_TXTRAINRANK2_TxDqDelay_WID ( 9) + #define DDRDATACH1_CR_TXTRAINRANK2_TxDqDelay_MSK (0x000001FF) + #define DDRDATACH1_CR_TXTRAINRANK2_TxDqDelay_MAX (0x000001FF) + #define DDRDATACH1_CR_TXTRAINRANK2_TxDqsDelay_OFF ( 9) + #define DDRDATACH1_CR_TXTRAINRANK2_TxDqsDelay_WID ( 9) + #define DDRDATACH1_CR_TXTRAINRANK2_TxDqsDelay_MSK (0x0003FE00) + #define DDRDATACH1_CR_TXTRAINRANK2_TxDqsDelay_MAX (0x000001FF) + #define DDRDATACH1_CR_TXTRAINRANK2_Spare0_OFF (18) + #define DDRDATACH1_CR_TXTRAINRANK2_Spare0_WID ( 2) + #define DDRDATACH1_CR_TXTRAINRANK2_Spare0_MSK (0x000C0000) + #define DDRDATACH1_CR_TXTRAINRANK2_Spare0_MAX (0x00000003) + #define DDRDATACH1_CR_TXTRAINRANK2_TxEqualization_OFF (20) + #define DDRDATACH1_CR_TXTRAINRANK2_TxEqualization_WID ( 6) + #define DDRDATACH1_CR_TXTRAINRANK2_TxEqualization_MSK (0x03F00000) + #define DDRDATACH1_CR_TXTRAINRANK2_TxEqualization_MAX (0x0000003F) + #define DDRDATACH1_CR_TXTRAINRANK2_Spare1_OFF (26) + #define DDRDATACH1_CR_TXTRAINRANK2_Spare1_WID ( 6) + #define DDRDATACH1_CR_TXTRAINRANK2_Spare1_MSK (0xFC000000) + #define DDRDATACH1_CR_TXTRAINRANK2_Spare1_MAX (0x0000003F) + +#define DDRDATACH1_CR_TXTRAINRANK3_REG (0x0000312C) + #define DDRDATACH1_CR_TXTRAINRANK3_TxDqDelay_OFF ( 0) + #define DDRDATACH1_CR_TXTRAINRANK3_TxDqDelay_WID ( 9) + #define DDRDATACH1_CR_TXTRAINRANK3_TxDqDelay_MSK (0x000001FF) + #define DDRDATACH1_CR_TXTRAINRANK3_TxDqDelay_MAX (0x000001FF) + #define DDRDATACH1_CR_TXTRAINRANK3_TxDqsDelay_OFF ( 9) + #define DDRDATACH1_CR_TXTRAINRANK3_TxDqsDelay_WID ( 9) + #define DDRDATACH1_CR_TXTRAINRANK3_TxDqsDelay_MSK (0x0003FE00) + #define DDRDATACH1_CR_TXTRAINRANK3_TxDqsDelay_MAX (0x000001FF) + #define DDRDATACH1_CR_TXTRAINRANK3_Spare0_OFF (18) + #define DDRDATACH1_CR_TXTRAINRANK3_Spare0_WID ( 2) + #define DDRDATACH1_CR_TXTRAINRANK3_Spare0_MSK (0x000C0000) + #define DDRDATACH1_CR_TXTRAINRANK3_Spare0_MAX (0x00000003) + #define DDRDATACH1_CR_TXTRAINRANK3_TxEqualization_OFF (20) + #define DDRDATACH1_CR_TXTRAINRANK3_TxEqualization_WID ( 6) + #define DDRDATACH1_CR_TXTRAINRANK3_TxEqualization_MSK (0x03F00000) + #define DDRDATACH1_CR_TXTRAINRANK3_TxEqualization_MAX (0x0000003F) + #define DDRDATACH1_CR_TXTRAINRANK3_Spare1_OFF (26) + #define DDRDATACH1_CR_TXTRAINRANK3_Spare1_WID ( 6) + #define DDRDATACH1_CR_TXTRAINRANK3_Spare1_MSK (0xFC000000) + #define DDRDATACH1_CR_TXTRAINRANK3_Spare1_MAX (0x0000003F) + +#define DDRDATACH1_CR_TXPERBITRANK0_REG (0x00003130) + #define DDRDATACH1_CR_TXPERBITRANK0_Lane0_OFF ( 0) + #define DDRDATACH1_CR_TXPERBITRANK0_Lane0_WID ( 4) + #define DDRDATACH1_CR_TXPERBITRANK0_Lane0_MSK (0x0000000F) + #define DDRDATACH1_CR_TXPERBITRANK0_Lane0_MAX (0x0000000F) + #define DDRDATACH1_CR_TXPERBITRANK0_Lane1_OFF ( 4) + #define DDRDATACH1_CR_TXPERBITRANK0_Lane1_WID ( 4) + #define DDRDATACH1_CR_TXPERBITRANK0_Lane1_MSK (0x000000F0) + #define DDRDATACH1_CR_TXPERBITRANK0_Lane1_MAX (0x0000000F) + #define DDRDATACH1_CR_TXPERBITRANK0_Lane2_OFF ( 8) + #define DDRDATACH1_CR_TXPERBITRANK0_Lane2_WID ( 4) + #define DDRDATACH1_CR_TXPERBITRANK0_Lane2_MSK (0x00000F00) + #define DDRDATACH1_CR_TXPERBITRANK0_Lane2_MAX (0x0000000F) + #define DDRDATACH1_CR_TXPERBITRANK0_Lane3_OFF (12) + #define DDRDATACH1_CR_TXPERBITRANK0_Lane3_WID ( 4) + #define DDRDATACH1_CR_TXPERBITRANK0_Lane3_MSK (0x0000F000) + #define DDRDATACH1_CR_TXPERBITRANK0_Lane3_MAX (0x0000000F) + #define DDRDATACH1_CR_TXPERBITRANK0_Lane4_OFF (16) + #define DDRDATACH1_CR_TXPERBITRANK0_Lane4_WID ( 4) + #define DDRDATACH1_CR_TXPERBITRANK0_Lane4_MSK (0x000F0000) + #define DDRDATACH1_CR_TXPERBITRANK0_Lane4_MAX (0x0000000F) + #define DDRDATACH1_CR_TXPERBITRANK0_Lane5_OFF (20) + #define DDRDATACH1_CR_TXPERBITRANK0_Lane5_WID ( 4) + #define DDRDATACH1_CR_TXPERBITRANK0_Lane5_MSK (0x00F00000) + #define DDRDATACH1_CR_TXPERBITRANK0_Lane5_MAX (0x0000000F) + #define DDRDATACH1_CR_TXPERBITRANK0_Lane6_OFF (24) + #define DDRDATACH1_CR_TXPERBITRANK0_Lane6_WID ( 4) + #define DDRDATACH1_CR_TXPERBITRANK0_Lane6_MSK (0x0F000000) + #define DDRDATACH1_CR_TXPERBITRANK0_Lane6_MAX (0x0000000F) + #define DDRDATACH1_CR_TXPERBITRANK0_Lane7_OFF (28) + #define DDRDATACH1_CR_TXPERBITRANK0_Lane7_WID ( 4) + #define DDRDATACH1_CR_TXPERBITRANK0_Lane7_MSK (0xF0000000) + #define DDRDATACH1_CR_TXPERBITRANK0_Lane7_MAX (0x0000000F) + +#define DDRDATACH1_CR_TXPERBITRANK1_REG (0x00003134) + #define DDRDATACH1_CR_TXPERBITRANK1_Lane0_OFF ( 0) + #define DDRDATACH1_CR_TXPERBITRANK1_Lane0_WID ( 4) + #define DDRDATACH1_CR_TXPERBITRANK1_Lane0_MSK (0x0000000F) + #define DDRDATACH1_CR_TXPERBITRANK1_Lane0_MAX (0x0000000F) + #define DDRDATACH1_CR_TXPERBITRANK1_Lane1_OFF ( 4) + #define DDRDATACH1_CR_TXPERBITRANK1_Lane1_WID ( 4) + #define DDRDATACH1_CR_TXPERBITRANK1_Lane1_MSK (0x000000F0) + #define DDRDATACH1_CR_TXPERBITRANK1_Lane1_MAX (0x0000000F) + #define DDRDATACH1_CR_TXPERBITRANK1_Lane2_OFF ( 8) + #define DDRDATACH1_CR_TXPERBITRANK1_Lane2_WID ( 4) + #define DDRDATACH1_CR_TXPERBITRANK1_Lane2_MSK (0x00000F00) + #define DDRDATACH1_CR_TXPERBITRANK1_Lane2_MAX (0x0000000F) + #define DDRDATACH1_CR_TXPERBITRANK1_Lane3_OFF (12) + #define DDRDATACH1_CR_TXPERBITRANK1_Lane3_WID ( 4) + #define DDRDATACH1_CR_TXPERBITRANK1_Lane3_MSK (0x0000F000) + #define DDRDATACH1_CR_TXPERBITRANK1_Lane3_MAX (0x0000000F) + #define DDRDATACH1_CR_TXPERBITRANK1_Lane4_OFF (16) + #define DDRDATACH1_CR_TXPERBITRANK1_Lane4_WID ( 4) + #define DDRDATACH1_CR_TXPERBITRANK1_Lane4_MSK (0x000F0000) + #define DDRDATACH1_CR_TXPERBITRANK1_Lane4_MAX (0x0000000F) + #define DDRDATACH1_CR_TXPERBITRANK1_Lane5_OFF (20) + #define DDRDATACH1_CR_TXPERBITRANK1_Lane5_WID ( 4) + #define DDRDATACH1_CR_TXPERBITRANK1_Lane5_MSK (0x00F00000) + #define DDRDATACH1_CR_TXPERBITRANK1_Lane5_MAX (0x0000000F) + #define DDRDATACH1_CR_TXPERBITRANK1_Lane6_OFF (24) + #define DDRDATACH1_CR_TXPERBITRANK1_Lane6_WID ( 4) + #define DDRDATACH1_CR_TXPERBITRANK1_Lane6_MSK (0x0F000000) + #define DDRDATACH1_CR_TXPERBITRANK1_Lane6_MAX (0x0000000F) + #define DDRDATACH1_CR_TXPERBITRANK1_Lane7_OFF (28) + #define DDRDATACH1_CR_TXPERBITRANK1_Lane7_WID ( 4) + #define DDRDATACH1_CR_TXPERBITRANK1_Lane7_MSK (0xF0000000) + #define DDRDATACH1_CR_TXPERBITRANK1_Lane7_MAX (0x0000000F) + +#define DDRDATACH1_CR_TXPERBITRANK2_REG (0x00003138) + #define DDRDATACH1_CR_TXPERBITRANK2_Lane0_OFF ( 0) + #define DDRDATACH1_CR_TXPERBITRANK2_Lane0_WID ( 4) + #define DDRDATACH1_CR_TXPERBITRANK2_Lane0_MSK (0x0000000F) + #define DDRDATACH1_CR_TXPERBITRANK2_Lane0_MAX (0x0000000F) + #define DDRDATACH1_CR_TXPERBITRANK2_Lane1_OFF ( 4) + #define DDRDATACH1_CR_TXPERBITRANK2_Lane1_WID ( 4) + #define DDRDATACH1_CR_TXPERBITRANK2_Lane1_MSK (0x000000F0) + #define DDRDATACH1_CR_TXPERBITRANK2_Lane1_MAX (0x0000000F) + #define DDRDATACH1_CR_TXPERBITRANK2_Lane2_OFF ( 8) + #define DDRDATACH1_CR_TXPERBITRANK2_Lane2_WID ( 4) + #define DDRDATACH1_CR_TXPERBITRANK2_Lane2_MSK (0x00000F00) + #define DDRDATACH1_CR_TXPERBITRANK2_Lane2_MAX (0x0000000F) + #define DDRDATACH1_CR_TXPERBITRANK2_Lane3_OFF (12) + #define DDRDATACH1_CR_TXPERBITRANK2_Lane3_WID ( 4) + #define DDRDATACH1_CR_TXPERBITRANK2_Lane3_MSK (0x0000F000) + #define DDRDATACH1_CR_TXPERBITRANK2_Lane3_MAX (0x0000000F) + #define DDRDATACH1_CR_TXPERBITRANK2_Lane4_OFF (16) + #define DDRDATACH1_CR_TXPERBITRANK2_Lane4_WID ( 4) + #define DDRDATACH1_CR_TXPERBITRANK2_Lane4_MSK (0x000F0000) + #define DDRDATACH1_CR_TXPERBITRANK2_Lane4_MAX (0x0000000F) + #define DDRDATACH1_CR_TXPERBITRANK2_Lane5_OFF (20) + #define DDRDATACH1_CR_TXPERBITRANK2_Lane5_WID ( 4) + #define DDRDATACH1_CR_TXPERBITRANK2_Lane5_MSK (0x00F00000) + #define DDRDATACH1_CR_TXPERBITRANK2_Lane5_MAX (0x0000000F) + #define DDRDATACH1_CR_TXPERBITRANK2_Lane6_OFF (24) + #define DDRDATACH1_CR_TXPERBITRANK2_Lane6_WID ( 4) + #define DDRDATACH1_CR_TXPERBITRANK2_Lane6_MSK (0x0F000000) + #define DDRDATACH1_CR_TXPERBITRANK2_Lane6_MAX (0x0000000F) + #define DDRDATACH1_CR_TXPERBITRANK2_Lane7_OFF (28) + #define DDRDATACH1_CR_TXPERBITRANK2_Lane7_WID ( 4) + #define DDRDATACH1_CR_TXPERBITRANK2_Lane7_MSK (0xF0000000) + #define DDRDATACH1_CR_TXPERBITRANK2_Lane7_MAX (0x0000000F) + +#define DDRDATACH1_CR_TXPERBITRANK3_REG (0x0000313C) + #define DDRDATACH1_CR_TXPERBITRANK3_Lane0_OFF ( 0) + #define DDRDATACH1_CR_TXPERBITRANK3_Lane0_WID ( 4) + #define DDRDATACH1_CR_TXPERBITRANK3_Lane0_MSK (0x0000000F) + #define DDRDATACH1_CR_TXPERBITRANK3_Lane0_MAX (0x0000000F) + #define DDRDATACH1_CR_TXPERBITRANK3_Lane1_OFF ( 4) + #define DDRDATACH1_CR_TXPERBITRANK3_Lane1_WID ( 4) + #define DDRDATACH1_CR_TXPERBITRANK3_Lane1_MSK (0x000000F0) + #define DDRDATACH1_CR_TXPERBITRANK3_Lane1_MAX (0x0000000F) + #define DDRDATACH1_CR_TXPERBITRANK3_Lane2_OFF ( 8) + #define DDRDATACH1_CR_TXPERBITRANK3_Lane2_WID ( 4) + #define DDRDATACH1_CR_TXPERBITRANK3_Lane2_MSK (0x00000F00) + #define DDRDATACH1_CR_TXPERBITRANK3_Lane2_MAX (0x0000000F) + #define DDRDATACH1_CR_TXPERBITRANK3_Lane3_OFF (12) + #define DDRDATACH1_CR_TXPERBITRANK3_Lane3_WID ( 4) + #define DDRDATACH1_CR_TXPERBITRANK3_Lane3_MSK (0x0000F000) + #define DDRDATACH1_CR_TXPERBITRANK3_Lane3_MAX (0x0000000F) + #define DDRDATACH1_CR_TXPERBITRANK3_Lane4_OFF (16) + #define DDRDATACH1_CR_TXPERBITRANK3_Lane4_WID ( 4) + #define DDRDATACH1_CR_TXPERBITRANK3_Lane4_MSK (0x000F0000) + #define DDRDATACH1_CR_TXPERBITRANK3_Lane4_MAX (0x0000000F) + #define DDRDATACH1_CR_TXPERBITRANK3_Lane5_OFF (20) + #define DDRDATACH1_CR_TXPERBITRANK3_Lane5_WID ( 4) + #define DDRDATACH1_CR_TXPERBITRANK3_Lane5_MSK (0x00F00000) + #define DDRDATACH1_CR_TXPERBITRANK3_Lane5_MAX (0x0000000F) + #define DDRDATACH1_CR_TXPERBITRANK3_Lane6_OFF (24) + #define DDRDATACH1_CR_TXPERBITRANK3_Lane6_WID ( 4) + #define DDRDATACH1_CR_TXPERBITRANK3_Lane6_MSK (0x0F000000) + #define DDRDATACH1_CR_TXPERBITRANK3_Lane6_MAX (0x0000000F) + #define DDRDATACH1_CR_TXPERBITRANK3_Lane7_OFF (28) + #define DDRDATACH1_CR_TXPERBITRANK3_Lane7_WID ( 4) + #define DDRDATACH1_CR_TXPERBITRANK3_Lane7_MSK (0xF0000000) + #define DDRDATACH1_CR_TXPERBITRANK3_Lane7_MAX (0x0000000F) + +#define DDRDATACH1_CR_RCOMPDATA0_REG (0x00003140) + #define DDRDATACH1_CR_RCOMPDATA0_RcompDrvUp_OFF ( 0) + #define DDRDATACH1_CR_RCOMPDATA0_RcompDrvUp_WID ( 6) + #define DDRDATACH1_CR_RCOMPDATA0_RcompDrvUp_MSK (0x0000003F) + #define DDRDATACH1_CR_RCOMPDATA0_RcompDrvUp_MAX (0x0000003F) + #define DDRDATACH1_CR_RCOMPDATA0_Spare0_OFF ( 6) + #define DDRDATACH1_CR_RCOMPDATA0_Spare0_WID ( 3) + #define DDRDATACH1_CR_RCOMPDATA0_Spare0_MSK (0x000001C0) + #define DDRDATACH1_CR_RCOMPDATA0_Spare0_MAX (0x00000007) + #define DDRDATACH1_CR_RCOMPDATA0_RcompDrvDown_OFF ( 9) + #define DDRDATACH1_CR_RCOMPDATA0_RcompDrvDown_WID ( 6) + #define DDRDATACH1_CR_RCOMPDATA0_RcompDrvDown_MSK (0x00007E00) + #define DDRDATACH1_CR_RCOMPDATA0_RcompDrvDown_MAX (0x0000003F) + #define DDRDATACH1_CR_RCOMPDATA0_VTComp_OFF (15) + #define DDRDATACH1_CR_RCOMPDATA0_VTComp_WID ( 5) + #define DDRDATACH1_CR_RCOMPDATA0_VTComp_MSK (0x000F8000) + #define DDRDATACH1_CR_RCOMPDATA0_VTComp_MAX (0x0000001F) + #define DDRDATACH1_CR_RCOMPDATA0_TcoComp_OFF (20) + #define DDRDATACH1_CR_RCOMPDATA0_TcoComp_WID ( 6) + #define DDRDATACH1_CR_RCOMPDATA0_TcoComp_MSK (0x03F00000) + #define DDRDATACH1_CR_RCOMPDATA0_TcoComp_MAX (0x0000003F) + #define DDRDATACH1_CR_RCOMPDATA0_SlewRateComp_OFF (26) + #define DDRDATACH1_CR_RCOMPDATA0_SlewRateComp_WID ( 5) + #define DDRDATACH1_CR_RCOMPDATA0_SlewRateComp_MSK (0x7C000000) + #define DDRDATACH1_CR_RCOMPDATA0_SlewRateComp_MAX (0x0000001F) + #define DDRDATACH1_CR_RCOMPDATA0_Spare2_OFF (31) + #define DDRDATACH1_CR_RCOMPDATA0_Spare2_WID ( 1) + #define DDRDATACH1_CR_RCOMPDATA0_Spare2_MSK (0x80000000) + #define DDRDATACH1_CR_RCOMPDATA0_Spare2_MAX (0x00000001) + +#define DDRDATACH1_CR_RCOMPDATA1_REG (0x00003144) + #define DDRDATACH1_CR_RCOMPDATA1_RcompOdtUp_OFF ( 0) + #define DDRDATACH1_CR_RCOMPDATA1_RcompOdtUp_WID ( 6) + #define DDRDATACH1_CR_RCOMPDATA1_RcompOdtUp_MSK (0x0000003F) + #define DDRDATACH1_CR_RCOMPDATA1_RcompOdtUp_MAX (0x0000003F) + #define DDRDATACH1_CR_RCOMPDATA1_Spare0_OFF ( 6) + #define DDRDATACH1_CR_RCOMPDATA1_Spare0_WID ( 3) + #define DDRDATACH1_CR_RCOMPDATA1_Spare0_MSK (0x000001C0) + #define DDRDATACH1_CR_RCOMPDATA1_Spare0_MAX (0x00000007) + #define DDRDATACH1_CR_RCOMPDATA1_RcompOdtDown_OFF ( 9) + #define DDRDATACH1_CR_RCOMPDATA1_RcompOdtDown_WID ( 6) + #define DDRDATACH1_CR_RCOMPDATA1_RcompOdtDown_MSK (0x00007E00) + #define DDRDATACH1_CR_RCOMPDATA1_RcompOdtDown_MAX (0x0000003F) + #define DDRDATACH1_CR_RCOMPDATA1_Spare1_OFF (15) + #define DDRDATACH1_CR_RCOMPDATA1_Spare1_WID ( 1) + #define DDRDATACH1_CR_RCOMPDATA1_Spare1_MSK (0x00008000) + #define DDRDATACH1_CR_RCOMPDATA1_Spare1_MAX (0x00000001) + #define DDRDATACH1_CR_RCOMPDATA1_PanicDrvDn_OFF (16) + #define DDRDATACH1_CR_RCOMPDATA1_PanicDrvDn_WID ( 6) + #define DDRDATACH1_CR_RCOMPDATA1_PanicDrvDn_MSK (0x003F0000) + #define DDRDATACH1_CR_RCOMPDATA1_PanicDrvDn_MAX (0x0000003F) + #define DDRDATACH1_CR_RCOMPDATA1_PanicDrvUp_OFF (22) + #define DDRDATACH1_CR_RCOMPDATA1_PanicDrvUp_WID ( 6) + #define DDRDATACH1_CR_RCOMPDATA1_PanicDrvUp_MSK (0x0FC00000) + #define DDRDATACH1_CR_RCOMPDATA1_PanicDrvUp_MAX (0x0000003F) + #define DDRDATACH1_CR_RCOMPDATA1_LevelShifterComp_OFF (28) + #define DDRDATACH1_CR_RCOMPDATA1_LevelShifterComp_WID ( 3) + #define DDRDATACH1_CR_RCOMPDATA1_LevelShifterComp_MSK (0x70000000) + #define DDRDATACH1_CR_RCOMPDATA1_LevelShifterComp_MAX (0x00000007) + #define DDRDATACH1_CR_RCOMPDATA1_Spare2_OFF (31) + #define DDRDATACH1_CR_RCOMPDATA1_Spare2_WID ( 1) + #define DDRDATACH1_CR_RCOMPDATA1_Spare2_MSK (0x80000000) + #define DDRDATACH1_CR_RCOMPDATA1_Spare2_MAX (0x00000001) + +#define DDRDATACH1_CR_TXXTALK_REG (0x00003148) + #define DDRDATACH1_CR_TXXTALK_Lane0_OFF ( 0) + #define DDRDATACH1_CR_TXXTALK_Lane0_WID ( 4) + #define DDRDATACH1_CR_TXXTALK_Lane0_MSK (0x0000000F) + #define DDRDATACH1_CR_TXXTALK_Lane0_MAX (0x0000000F) + #define DDRDATACH1_CR_TXXTALK_Lane1_OFF ( 4) + #define DDRDATACH1_CR_TXXTALK_Lane1_WID ( 4) + #define DDRDATACH1_CR_TXXTALK_Lane1_MSK (0x000000F0) + #define DDRDATACH1_CR_TXXTALK_Lane1_MAX (0x0000000F) + #define DDRDATACH1_CR_TXXTALK_Lane2_OFF ( 8) + #define DDRDATACH1_CR_TXXTALK_Lane2_WID ( 4) + #define DDRDATACH1_CR_TXXTALK_Lane2_MSK (0x00000F00) + #define DDRDATACH1_CR_TXXTALK_Lane2_MAX (0x0000000F) + #define DDRDATACH1_CR_TXXTALK_Lane3_OFF (12) + #define DDRDATACH1_CR_TXXTALK_Lane3_WID ( 4) + #define DDRDATACH1_CR_TXXTALK_Lane3_MSK (0x0000F000) + #define DDRDATACH1_CR_TXXTALK_Lane3_MAX (0x0000000F) + #define DDRDATACH1_CR_TXXTALK_Lane4_OFF (16) + #define DDRDATACH1_CR_TXXTALK_Lane4_WID ( 4) + #define DDRDATACH1_CR_TXXTALK_Lane4_MSK (0x000F0000) + #define DDRDATACH1_CR_TXXTALK_Lane4_MAX (0x0000000F) + #define DDRDATACH1_CR_TXXTALK_Lane5_OFF (20) + #define DDRDATACH1_CR_TXXTALK_Lane5_WID ( 4) + #define DDRDATACH1_CR_TXXTALK_Lane5_MSK (0x00F00000) + #define DDRDATACH1_CR_TXXTALK_Lane5_MAX (0x0000000F) + #define DDRDATACH1_CR_TXXTALK_Lane6_OFF (24) + #define DDRDATACH1_CR_TXXTALK_Lane6_WID ( 4) + #define DDRDATACH1_CR_TXXTALK_Lane6_MSK (0x0F000000) + #define DDRDATACH1_CR_TXXTALK_Lane6_MAX (0x0000000F) + #define DDRDATACH1_CR_TXXTALK_Lane7_OFF (28) + #define DDRDATACH1_CR_TXXTALK_Lane7_WID ( 4) + #define DDRDATACH1_CR_TXXTALK_Lane7_MSK (0xF0000000) + #define DDRDATACH1_CR_TXXTALK_Lane7_MAX (0x0000000F) + +#define DDRDATACH1_CR_RXOFFSETVDQ_REG (0x0000314C) + #define DDRDATACH1_CR_RXOFFSETVDQ_Lane0_OFF ( 0) + #define DDRDATACH1_CR_RXOFFSETVDQ_Lane0_WID ( 4) + #define DDRDATACH1_CR_RXOFFSETVDQ_Lane0_MSK (0x0000000F) + #define DDRDATACH1_CR_RXOFFSETVDQ_Lane0_MAX (0x0000000F) + #define DDRDATACH1_CR_RXOFFSETVDQ_Lane1_OFF ( 4) + #define DDRDATACH1_CR_RXOFFSETVDQ_Lane1_WID ( 4) + #define DDRDATACH1_CR_RXOFFSETVDQ_Lane1_MSK (0x000000F0) + #define DDRDATACH1_CR_RXOFFSETVDQ_Lane1_MAX (0x0000000F) + #define DDRDATACH1_CR_RXOFFSETVDQ_Lane2_OFF ( 8) + #define DDRDATACH1_CR_RXOFFSETVDQ_Lane2_WID ( 4) + #define DDRDATACH1_CR_RXOFFSETVDQ_Lane2_MSK (0x00000F00) + #define DDRDATACH1_CR_RXOFFSETVDQ_Lane2_MAX (0x0000000F) + #define DDRDATACH1_CR_RXOFFSETVDQ_Lane3_OFF (12) + #define DDRDATACH1_CR_RXOFFSETVDQ_Lane3_WID ( 4) + #define DDRDATACH1_CR_RXOFFSETVDQ_Lane3_MSK (0x0000F000) + #define DDRDATACH1_CR_RXOFFSETVDQ_Lane3_MAX (0x0000000F) + #define DDRDATACH1_CR_RXOFFSETVDQ_Lane4_OFF (16) + #define DDRDATACH1_CR_RXOFFSETVDQ_Lane4_WID ( 4) + #define DDRDATACH1_CR_RXOFFSETVDQ_Lane4_MSK (0x000F0000) + #define DDRDATACH1_CR_RXOFFSETVDQ_Lane4_MAX (0x0000000F) + #define DDRDATACH1_CR_RXOFFSETVDQ_Lane5_OFF (20) + #define DDRDATACH1_CR_RXOFFSETVDQ_Lane5_WID ( 4) + #define DDRDATACH1_CR_RXOFFSETVDQ_Lane5_MSK (0x00F00000) + #define DDRDATACH1_CR_RXOFFSETVDQ_Lane5_MAX (0x0000000F) + #define DDRDATACH1_CR_RXOFFSETVDQ_Lane6_OFF (24) + #define DDRDATACH1_CR_RXOFFSETVDQ_Lane6_WID ( 4) + #define DDRDATACH1_CR_RXOFFSETVDQ_Lane6_MSK (0x0F000000) + #define DDRDATACH1_CR_RXOFFSETVDQ_Lane6_MAX (0x0000000F) + #define DDRDATACH1_CR_RXOFFSETVDQ_Lane7_OFF (28) + #define DDRDATACH1_CR_RXOFFSETVDQ_Lane7_WID ( 4) + #define DDRDATACH1_CR_RXOFFSETVDQ_Lane7_MSK (0xF0000000) + #define DDRDATACH1_CR_RXOFFSETVDQ_Lane7_MAX (0x0000000F) + +#define DDRDATACH1_CR_DDRDATARESERVED_REG (0x00003150) + #define DDRDATACH1_CR_DDRDATARESERVED_Spare_OFF ( 0) + #define DDRDATACH1_CR_DDRDATARESERVED_Spare_WID (32) + #define DDRDATACH1_CR_DDRDATARESERVED_Spare_MSK (0xFFFFFFFF) + #define DDRDATACH1_CR_DDRDATARESERVED_Spare_MAX (0xFFFFFFFF) + +#define DDRDATACH1_CR_DATATRAINFEEDBACK_REG (0x00003154) + #define DDRDATACH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_OFF ( 0) + #define DDRDATACH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_WID ( 9) + #define DDRDATACH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_MSK (0x000001FF) + #define DDRDATACH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_MAX (0x000001FF) + #define DDRDATACH1_CR_DATATRAINFEEDBACK_Spare_OFF ( 9) + #define DDRDATACH1_CR_DATATRAINFEEDBACK_Spare_WID (23) + #define DDRDATACH1_CR_DATATRAINFEEDBACK_Spare_MSK (0xFFFFFE00) + #define DDRDATACH1_CR_DATATRAINFEEDBACK_Spare_MAX (0x007FFFFF) + +#define DDRDATACH1_CR_DLLPITESTANDADC_REG (0x00003158) + #define DDRDATACH1_CR_DLLPITESTANDADC_RunTest_OFF ( 0) + #define DDRDATACH1_CR_DLLPITESTANDADC_RunTest_WID ( 1) + #define DDRDATACH1_CR_DLLPITESTANDADC_RunTest_MSK (0x00000001) + #define DDRDATACH1_CR_DLLPITESTANDADC_RunTest_MAX (0x00000001) + #define DDRDATACH1_CR_DLLPITESTANDADC_RunTest_DEF (0x00000000) + #define DDRDATACH1_CR_DLLPITESTANDADC_Load_OFF ( 1) + #define DDRDATACH1_CR_DLLPITESTANDADC_Load_WID ( 1) + #define DDRDATACH1_CR_DLLPITESTANDADC_Load_MSK (0x00000002) + #define DDRDATACH1_CR_DLLPITESTANDADC_Load_MAX (0x00000001) + #define DDRDATACH1_CR_DLLPITESTANDADC_Load_DEF (0x00000000) + #define DDRDATACH1_CR_DLLPITESTANDADC_ModeHVM_OFF ( 2) + #define DDRDATACH1_CR_DLLPITESTANDADC_ModeHVM_WID ( 1) + #define DDRDATACH1_CR_DLLPITESTANDADC_ModeHVM_MSK (0x00000004) + #define DDRDATACH1_CR_DLLPITESTANDADC_ModeHVM_MAX (0x00000001) + #define DDRDATACH1_CR_DLLPITESTANDADC_ModeHVM_DEF (0x00000000) + #define DDRDATACH1_CR_DLLPITESTANDADC_ModeDV_OFF ( 3) + #define DDRDATACH1_CR_DLLPITESTANDADC_ModeDV_WID ( 1) + #define DDRDATACH1_CR_DLLPITESTANDADC_ModeDV_MSK (0x00000008) + #define DDRDATACH1_CR_DLLPITESTANDADC_ModeDV_MAX (0x00000001) + #define DDRDATACH1_CR_DLLPITESTANDADC_ModeDV_DEF (0x00000000) + #define DDRDATACH1_CR_DLLPITESTANDADC_ModeADC_OFF ( 4) + #define DDRDATACH1_CR_DLLPITESTANDADC_ModeADC_WID ( 1) + #define DDRDATACH1_CR_DLLPITESTANDADC_ModeADC_MSK (0x00000010) + #define DDRDATACH1_CR_DLLPITESTANDADC_ModeADC_MAX (0x00000001) + #define DDRDATACH1_CR_DLLPITESTANDADC_ModeADC_DEF (0x00000000) + #define DDRDATACH1_CR_DLLPITESTANDADC_LoadCount_OFF ( 5) + #define DDRDATACH1_CR_DLLPITESTANDADC_LoadCount_WID (10) + #define DDRDATACH1_CR_DLLPITESTANDADC_LoadCount_MSK (0x00007FE0) + #define DDRDATACH1_CR_DLLPITESTANDADC_LoadCount_MAX (0x000003FF) + #define DDRDATACH1_CR_DLLPITESTANDADC_CountStatus_OFF (15) + #define DDRDATACH1_CR_DLLPITESTANDADC_CountStatus_WID (10) + #define DDRDATACH1_CR_DLLPITESTANDADC_CountStatus_MSK (0x01FF8000) + #define DDRDATACH1_CR_DLLPITESTANDADC_CountStatus_MAX (0x000003FF) + #define DDRDATACH1_CR_DLLPITESTANDADC_CountStatus_DEF (0x00000000) + #define DDRDATACH1_CR_DLLPITESTANDADC_Spare_OFF (25) + #define DDRDATACH1_CR_DLLPITESTANDADC_Spare_WID ( 7) + #define DDRDATACH1_CR_DLLPITESTANDADC_Spare_MSK (0xFE000000) + #define DDRDATACH1_CR_DLLPITESTANDADC_Spare_MAX (0x0000007F) + +#define DDRDATACH1_CR_DDRCRDATAOFFSETCOMP_REG (0x0000315C) + #define DDRDATACH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_OFF ( 0) + #define DDRDATACH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_WID ( 6) + #define DDRDATACH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MSK (0x0000003F) + #define DDRDATACH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MAX (0x0000003F) + #define DDRDATACH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_DEF (0x00000000) + #define DDRDATACH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_OFF ( 6) + #define DDRDATACH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_WID ( 6) + #define DDRDATACH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MSK (0x00000FC0) + #define DDRDATACH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MAX (0x0000003F) + #define DDRDATACH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_DEF (0x00000000) + #define DDRDATACH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_OFF (12) + #define DDRDATACH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_WID ( 5) + #define DDRDATACH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MSK (0x0001F000) + #define DDRDATACH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MAX (0x0000001F) + #define DDRDATACH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_DEF (0x00000000) + #define DDRDATACH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_OFF (17) + #define DDRDATACH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_WID ( 5) + #define DDRDATACH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MSK (0x003E0000) + #define DDRDATACH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MAX (0x0000001F) + #define DDRDATACH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_DEF (0x00000000) + #define DDRDATACH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_OFF (22) + #define DDRDATACH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_WID ( 5) + #define DDRDATACH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_MSK (0x07C00000) + #define DDRDATACH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_MAX (0x0000001F) + #define DDRDATACH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_DEF (0x00000000) + #define DDRDATACH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_OFF (27) + #define DDRDATACH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_WID ( 5) + #define DDRDATACH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MSK (0xF8000000) + #define DDRDATACH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MAX (0x0000001F) + #define DDRDATACH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_DEF (0x00000000) + +#define DDRDATACH1_CR_DDRCRDATACONTROL1_REG (0x00003160) + #define DDRDATACH1_CR_DDRCRDATACONTROL1_RefPi_OFF ( 0) + #define DDRDATACH1_CR_DDRCRDATACONTROL1_RefPi_WID ( 4) + #define DDRDATACH1_CR_DDRCRDATACONTROL1_RefPi_MSK (0x0000000F) + #define DDRDATACH1_CR_DDRCRDATACONTROL1_RefPi_MAX (0x0000000F) + #define DDRDATACH1_CR_DDRCRDATACONTROL1_RefPi_DEF (0x00000000) + #define DDRDATACH1_CR_DDRCRDATACONTROL1_DllMask_OFF ( 4) + #define DDRDATACH1_CR_DDRCRDATACONTROL1_DllMask_WID ( 2) + #define DDRDATACH1_CR_DDRCRDATACONTROL1_DllMask_MSK (0x00000030) + #define DDRDATACH1_CR_DDRCRDATACONTROL1_DllMask_MAX (0x00000003) + #define DDRDATACH1_CR_DDRCRDATACONTROL1_DllMask_DEF (0x00000000) + #define DDRDATACH1_CR_DDRCRDATACONTROL1_DllWeakLock_OFF ( 6) + #define DDRDATACH1_CR_DDRCRDATACONTROL1_DllWeakLock_WID ( 1) + #define DDRDATACH1_CR_DDRCRDATACONTROL1_DllWeakLock_MSK (0x00000040) + #define DDRDATACH1_CR_DDRCRDATACONTROL1_DllWeakLock_MAX (0x00000001) + #define DDRDATACH1_CR_DDRCRDATACONTROL1_DllWeakLock_DEF (0x00000000) + #define DDRDATACH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_OFF ( 7) + #define DDRDATACH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_WID ( 3) + #define DDRDATACH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MSK (0x00000380) + #define DDRDATACH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MAX (0x00000007) + #define DDRDATACH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_DEF (0x00000000) + #define DDRDATACH1_CR_DDRCRDATACONTROL1_RxBiasCtl_OFF (10) + #define DDRDATACH1_CR_DDRCRDATACONTROL1_RxBiasCtl_WID ( 3) + #define DDRDATACH1_CR_DDRCRDATACONTROL1_RxBiasCtl_MSK (0x00001C00) + #define DDRDATACH1_CR_DDRCRDATACONTROL1_RxBiasCtl_MAX (0x00000007) + #define DDRDATACH1_CR_DDRCRDATACONTROL1_RxBiasCtl_DEF (0x00000000) + #define DDRDATACH1_CR_DDRCRDATACONTROL1_OdtDelay_OFF (13) + #define DDRDATACH1_CR_DDRCRDATACONTROL1_OdtDelay_WID ( 4) + #define DDRDATACH1_CR_DDRCRDATACONTROL1_OdtDelay_MSK (0x0001E000) + #define DDRDATACH1_CR_DDRCRDATACONTROL1_OdtDelay_MAX (0x0000000F) + #define DDRDATACH1_CR_DDRCRDATACONTROL1_OdtDelay_DEF (0x00000000) + #define DDRDATACH1_CR_DDRCRDATACONTROL1_OdtDuration_OFF (17) + #define DDRDATACH1_CR_DDRCRDATACONTROL1_OdtDuration_WID ( 3) + #define DDRDATACH1_CR_DDRCRDATACONTROL1_OdtDuration_MSK (0x000E0000) + #define DDRDATACH1_CR_DDRCRDATACONTROL1_OdtDuration_MAX (0x00000007) + #define DDRDATACH1_CR_DDRCRDATACONTROL1_OdtDuration_DEF (0x00000000) + #define DDRDATACH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_OFF (20) + #define DDRDATACH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_WID ( 4) + #define DDRDATACH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_MSK (0x00F00000) + #define DDRDATACH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_MAX (0x0000000F) + #define DDRDATACH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_DEF (0x00000000) + #define DDRDATACH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_OFF (24) + #define DDRDATACH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_WID ( 3) + #define DDRDATACH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_MSK (0x07000000) + #define DDRDATACH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_MAX (0x00000007) + #define DDRDATACH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_DEF (0x00000000) + #define DDRDATACH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_OFF (27) + #define DDRDATACH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_WID ( 3) + #define DDRDATACH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_MSK (0x38000000) + #define DDRDATACH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_MAX (0x00000007) + #define DDRDATACH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_DEF (0x00000000) + #define DDRDATACH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_OFF (30) + #define DDRDATACH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_WID ( 1) + #define DDRDATACH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_MSK (0x40000000) + #define DDRDATACH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_MAX (0x00000001) + #define DDRDATACH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_DEF (0x00000000) + #define DDRDATACH1_CR_DDRCRDATACONTROL1_Rsvd1_OFF (31) + #define DDRDATACH1_CR_DDRCRDATACONTROL1_Rsvd1_WID ( 1) + #define DDRDATACH1_CR_DDRCRDATACONTROL1_Rsvd1_MSK (0x80000000) + #define DDRDATACH1_CR_DDRCRDATACONTROL1_Rsvd1_MAX (0x00000001) + #define DDRDATACH1_CR_DDRCRDATACONTROL1_Rsvd1_DEF (0x00000000) + +#define DDRDATACH1_CR_DDRCRDATACONTROL2_REG (0x00003164) + #define DDRDATACH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_OFF ( 0) + #define DDRDATACH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_WID ( 5) + #define DDRDATACH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_MSK (0x0000001F) + #define DDRDATACH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_MAX (0x0000001F) + #define DDRDATACH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_DEF (0x00000000) + #define DDRDATACH1_CR_DDRCRDATACONTROL2_ForceBiasOn_OFF ( 5) + #define DDRDATACH1_CR_DDRCRDATACONTROL2_ForceBiasOn_WID ( 1) + #define DDRDATACH1_CR_DDRCRDATACONTROL2_ForceBiasOn_MSK (0x00000020) + #define DDRDATACH1_CR_DDRCRDATACONTROL2_ForceBiasOn_MAX (0x00000001) + #define DDRDATACH1_CR_DDRCRDATACONTROL2_ForceBiasOn_DEF (0x00000000) + #define DDRDATACH1_CR_DDRCRDATACONTROL2_ForceRxOn_OFF ( 6) + #define DDRDATACH1_CR_DDRCRDATACONTROL2_ForceRxOn_WID ( 1) + #define DDRDATACH1_CR_DDRCRDATACONTROL2_ForceRxOn_MSK (0x00000040) + #define DDRDATACH1_CR_DDRCRDATACONTROL2_ForceRxOn_MAX (0x00000001) + #define DDRDATACH1_CR_DDRCRDATACONTROL2_ForceRxOn_DEF (0x00000000) + #define DDRDATACH1_CR_DDRCRDATACONTROL2_LeakerComp_OFF ( 7) + #define DDRDATACH1_CR_DDRCRDATACONTROL2_LeakerComp_WID ( 2) + #define DDRDATACH1_CR_DDRCRDATACONTROL2_LeakerComp_MSK (0x00000180) + #define DDRDATACH1_CR_DDRCRDATACONTROL2_LeakerComp_MAX (0x00000003) + #define DDRDATACH1_CR_DDRCRDATACONTROL2_LeakerComp_DEF (0x00000000) + #define DDRDATACH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_OFF ( 9) + #define DDRDATACH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_WID ( 4) + #define DDRDATACH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_MSK (0x00001E00) + #define DDRDATACH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_MAX (0x0000000F) + #define DDRDATACH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_DEF (0x00000008) + #define DDRDATACH1_CR_DDRCRDATACONTROL2_RxClkStgNum_OFF (13) + #define DDRDATACH1_CR_DDRCRDATACONTROL2_RxClkStgNum_WID ( 5) + #define DDRDATACH1_CR_DDRCRDATACONTROL2_RxClkStgNum_MSK (0x0003E000) + #define DDRDATACH1_CR_DDRCRDATACONTROL2_RxClkStgNum_MAX (0x0000001F) + #define DDRDATACH1_CR_DDRCRDATACONTROL2_RxClkStgNum_DEF (0x00000011) + #define DDRDATACH1_CR_DDRCRDATACONTROL2_WlLongDelEn_OFF (18) + #define DDRDATACH1_CR_DDRCRDATACONTROL2_WlLongDelEn_WID ( 1) + #define DDRDATACH1_CR_DDRCRDATACONTROL2_WlLongDelEn_MSK (0x00040000) + #define DDRDATACH1_CR_DDRCRDATACONTROL2_WlLongDelEn_MAX (0x00000001) + #define DDRDATACH1_CR_DDRCRDATACONTROL2_WlLongDelEn_DEF (0x00000000) + #define DDRDATACH1_CR_DDRCRDATACONTROL2_Spare_OFF (19) + #define DDRDATACH1_CR_DDRCRDATACONTROL2_Spare_WID (13) + #define DDRDATACH1_CR_DDRCRDATACONTROL2_Spare_MSK (0xFFF80000) + #define DDRDATACH1_CR_DDRCRDATACONTROL2_Spare_MAX (0x00001FFF) + #define DDRDATACH1_CR_DDRCRDATACONTROL2_Spare_DEF (0x00000000) + +#define DDRDATACH1_CR_DDRCRVSSHIORVREFCONTROL_REG (0x0000316C) + #define DDRDATACH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_OFF ( 0) + #define DDRDATACH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_WID (24) + #define DDRDATACH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_MSK (0x00FFFFFF) + #define DDRDATACH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_MAX (0x00FFFFFF) + #define DDRDATACH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_DEF (0x00000000) + #define DDRDATACH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_OFF (24) + #define DDRDATACH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_WID ( 8) + #define DDRDATACH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_MSK (0xFF000000) + #define DDRDATACH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_MAX (0x000000FF) + #define DDRDATACH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_DEF (0x00000000) + +#define DDRDATACH1_CR_DDRCRDATAOFFSETTRAIN_REG (0x00003170) + #define DDRDATACH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_OFF ( 0) + #define DDRDATACH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_WID ( 6) + #define DDRDATACH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MSK (0x0000003F) + #define DDRDATACH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MAX (0x0000003F) + #define DDRDATACH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_DEF (0x00000000) + #define DDRDATACH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_OFF ( 6) + #define DDRDATACH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_WID ( 6) + #define DDRDATACH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MSK (0x00000FC0) + #define DDRDATACH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MAX (0x0000003F) + #define DDRDATACH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_DEF (0x00000000) + #define DDRDATACH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_OFF (12) + #define DDRDATACH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_WID ( 6) + #define DDRDATACH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MSK (0x0003F000) + #define DDRDATACH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MAX (0x0000003F) + #define DDRDATACH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_DEF (0x00000000) + #define DDRDATACH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_OFF (18) + #define DDRDATACH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_WID ( 6) + #define DDRDATACH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MSK (0x00FC0000) + #define DDRDATACH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MAX (0x0000003F) + #define DDRDATACH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_DEF (0x00000000) + #define DDRDATACH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_OFF (24) + #define DDRDATACH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_WID ( 7) + #define DDRDATACH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MSK (0x7F000000) + #define DDRDATACH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MAX (0x0000007F) + #define DDRDATACH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_DEF (0x00000000) + #define DDRDATACH1_CR_DDRCRDATAOFFSETTRAIN_Spare_OFF (31) + #define DDRDATACH1_CR_DDRCRDATAOFFSETTRAIN_Spare_WID ( 1) + #define DDRDATACH1_CR_DDRCRDATAOFFSETTRAIN_Spare_MSK (0x80000000) + #define DDRDATACH1_CR_DDRCRDATAOFFSETTRAIN_Spare_MAX (0x00000001) + #define DDRDATACH1_CR_DDRCRDATAOFFSETTRAIN_Spare_DEF (0x00000000) + +#define DDRDATACH1_CR_DDRCRDATACONTROL0_REG (0x00003174) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_RxTrainingMode_OFF ( 0) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_RxTrainingMode_WID ( 1) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_RxTrainingMode_MSK (0x00000001) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_RxTrainingMode_MAX (0x00000001) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_RxTrainingMode_DEF (0x00000000) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_WLTrainingMode_OFF ( 1) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_WLTrainingMode_WID ( 1) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_WLTrainingMode_MSK (0x00000002) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_WLTrainingMode_MAX (0x00000001) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_WLTrainingMode_DEF (0x00000000) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_RLTrainingMode_OFF ( 2) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_RLTrainingMode_WID ( 1) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_RLTrainingMode_MSK (0x00000004) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_RLTrainingMode_MAX (0x00000001) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_RLTrainingMode_DEF (0x00000000) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_OFF ( 3) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_WID ( 1) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MSK (0x00000008) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MAX (0x00000001) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_DEF (0x00000000) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_TxOn_OFF ( 4) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_TxOn_WID ( 1) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_TxOn_MSK (0x00000010) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_TxOn_MAX (0x00000001) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_TxOn_DEF (0x00000000) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_RfOn_OFF ( 5) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_RfOn_WID ( 1) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_RfOn_MSK (0x00000020) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_RfOn_MAX (0x00000001) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_RfOn_DEF (0x00000000) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_RxPiOn_OFF ( 6) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_RxPiOn_WID ( 1) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_RxPiOn_MSK (0x00000040) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_RxPiOn_MAX (0x00000001) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_RxPiOn_DEF (0x00000000) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_TxPiOn_OFF ( 7) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_TxPiOn_WID ( 1) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_TxPiOn_MSK (0x00000080) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_TxPiOn_MAX (0x00000001) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_TxPiOn_DEF (0x00000000) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_InternalClocksOn_OFF ( 8) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_InternalClocksOn_WID ( 1) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_InternalClocksOn_MSK (0x00000100) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_InternalClocksOn_MAX (0x00000001) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_InternalClocksOn_DEF (0x00000000) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_OFF ( 9) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_WID ( 1) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MSK (0x00000200) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MAX (0x00000001) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_DEF (0x00000000) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_TxDisable_OFF (10) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_TxDisable_WID ( 1) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_TxDisable_MSK (0x00000400) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_TxDisable_MAX (0x00000001) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_TxDisable_DEF (0x00000000) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_RxDisable_OFF (11) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_RxDisable_WID ( 1) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_RxDisable_MSK (0x00000800) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_RxDisable_MAX (0x00000001) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_RxDisable_DEF (0x00000000) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_TxLong_OFF (12) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_TxLong_WID ( 1) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_TxLong_MSK (0x00001000) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_TxLong_MAX (0x00000001) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_TxLong_DEF (0x00000000) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_RxDqsCtle_OFF (13) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_RxDqsCtle_WID ( 2) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_RxDqsCtle_MSK (0x00006000) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_RxDqsCtle_MAX (0x00000003) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_RxDqsCtle_DEF (0x00000000) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_RxReadPointer_OFF (15) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_RxReadPointer_WID ( 3) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_RxReadPointer_MSK (0x00038000) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_RxReadPointer_MAX (0x00000007) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_RxReadPointer_DEF (0x00000000) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_OFF (18) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_WID ( 1) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_MSK (0x00040000) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_MAX (0x00000001) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_DEF (0x00000000) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_DataVccddqHi_OFF (19) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_DataVccddqHi_WID ( 1) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_DataVccddqHi_MSK (0x00080000) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_DataVccddqHi_MAX (0x00000001) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_DataVccddqHi_DEF (0x00000000) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_ReadRFRd_OFF (20) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_ReadRFRd_WID ( 1) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_ReadRFRd_MSK (0x00100000) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_ReadRFRd_MAX (0x00000001) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_ReadRFRd_DEF (0x00000000) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_ReadRFWr_OFF (21) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_ReadRFWr_WID ( 1) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_ReadRFWr_MSK (0x00200000) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_ReadRFWr_MAX (0x00000001) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_ReadRFWr_DEF (0x00000000) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_ReadRFRank_OFF (22) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_ReadRFRank_WID ( 2) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_ReadRFRank_MSK (0x00C00000) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_ReadRFRank_MAX (0x00000003) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_ReadRFRank_DEF (0x00000000) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_ForceOdtOn_OFF (24) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_ForceOdtOn_WID ( 1) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_ForceOdtOn_MSK (0x01000000) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_ForceOdtOn_MAX (0x00000001) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_ForceOdtOn_DEF (0x00000000) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_OdtSampOff_OFF (25) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_OdtSampOff_WID ( 1) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_OdtSampOff_MSK (0x02000000) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_OdtSampOff_MAX (0x00000001) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_OdtSampOff_DEF (0x00000000) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_OFF (26) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_WID ( 1) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_MSK (0x04000000) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_MAX (0x00000001) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_DEF (0x00000000) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_OFF (27) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_WID ( 1) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MSK (0x08000000) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MAX (0x00000001) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_DEF (0x00000000) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_OFF (28) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_WID ( 1) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_MSK (0x10000000) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_MAX (0x00000001) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_DEF (0x00000000) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_EnReadPreamble_OFF (29) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_EnReadPreamble_WID ( 1) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_EnReadPreamble_MSK (0x20000000) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_EnReadPreamble_MAX (0x00000001) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_EnReadPreamble_DEF (0x00000000) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_OFF (30) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_WID ( 1) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MSK (0x40000000) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MAX (0x00000001) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_DEF (0x00000000) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_OFF (31) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_WID ( 1) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_MSK (0x80000000) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_MAX (0x00000001) + #define DDRDATACH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_DEF (0x00000000) + +#define DDRDATACH1_CR_DDRCRVREFADJUST1_REG (0x00003178) + #define DDRDATACH1_CR_DDRCRVREFADJUST1_CAVrefCtl_OFF ( 0) + #define DDRDATACH1_CR_DDRCRVREFADJUST1_CAVrefCtl_WID ( 7) + #define DDRDATACH1_CR_DDRCRVREFADJUST1_CAVrefCtl_MSK (0x0000007F) + #define DDRDATACH1_CR_DDRCRVREFADJUST1_CAVrefCtl_MAX (0x0000007F) + #define DDRDATACH1_CR_DDRCRVREFADJUST1_CAVrefCtl_DEF (0x00000000) + #define DDRDATACH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_OFF ( 7) + #define DDRDATACH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_WID ( 7) + #define DDRDATACH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_MSK (0x00003F80) + #define DDRDATACH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_MAX (0x0000007F) + #define DDRDATACH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_DEF (0x00000000) + #define DDRDATACH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_OFF (14) + #define DDRDATACH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_WID ( 7) + #define DDRDATACH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_MSK (0x001FC000) + #define DDRDATACH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_MAX (0x0000007F) + #define DDRDATACH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_DEF (0x00000000) + #define DDRDATACH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_OFF (21) + #define DDRDATACH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_WID ( 1) + #define DDRDATACH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_MSK (0x00200000) + #define DDRDATACH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_MAX (0x00000001) + #define DDRDATACH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_DEF (0x00000000) + #define DDRDATACH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_OFF (22) + #define DDRDATACH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_WID ( 1) + #define DDRDATACH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_MSK (0x00400000) + #define DDRDATACH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_MAX (0x00000001) + #define DDRDATACH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_DEF (0x00000000) + #define DDRDATACH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_OFF (23) + #define DDRDATACH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_WID ( 1) + #define DDRDATACH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_MSK (0x00800000) + #define DDRDATACH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_MAX (0x00000001) + #define DDRDATACH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_DEF (0x00000000) + #define DDRDATACH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_OFF (24) + #define DDRDATACH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_WID ( 2) + #define DDRDATACH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_MSK (0x03000000) + #define DDRDATACH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_MAX (0x00000003) + #define DDRDATACH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_DEF (0x00000000) + #define DDRDATACH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_OFF (26) + #define DDRDATACH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_WID ( 1) + #define DDRDATACH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_MSK (0x04000000) + #define DDRDATACH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_MAX (0x00000001) + #define DDRDATACH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_DEF (0x00000000) + #define DDRDATACH1_CR_DDRCRVREFADJUST1_Rsvd_OFF (27) + #define DDRDATACH1_CR_DDRCRVREFADJUST1_Rsvd_WID ( 2) + #define DDRDATACH1_CR_DDRCRVREFADJUST1_Rsvd_MSK (0x18000000) + #define DDRDATACH1_CR_DDRCRVREFADJUST1_Rsvd_MAX (0x00000003) + #define DDRDATACH1_CR_DDRCRVREFADJUST1_Rsvd_DEF (0x00000000) + #define DDRDATACH1_CR_DDRCRVREFADJUST1_caSlowBW_OFF (29) + #define DDRDATACH1_CR_DDRCRVREFADJUST1_caSlowBW_WID ( 1) + #define DDRDATACH1_CR_DDRCRVREFADJUST1_caSlowBW_MSK (0x20000000) + #define DDRDATACH1_CR_DDRCRVREFADJUST1_caSlowBW_MAX (0x00000001) + #define DDRDATACH1_CR_DDRCRVREFADJUST1_caSlowBW_DEF (0x00000000) + #define DDRDATACH1_CR_DDRCRVREFADJUST1_ch0SlowBW_OFF (30) + #define DDRDATACH1_CR_DDRCRVREFADJUST1_ch0SlowBW_WID ( 1) + #define DDRDATACH1_CR_DDRCRVREFADJUST1_ch0SlowBW_MSK (0x40000000) + #define DDRDATACH1_CR_DDRCRVREFADJUST1_ch0SlowBW_MAX (0x00000001) + #define DDRDATACH1_CR_DDRCRVREFADJUST1_ch0SlowBW_DEF (0x00000000) + #define DDRDATACH1_CR_DDRCRVREFADJUST1_ch1SlowBW_OFF (31) + #define DDRDATACH1_CR_DDRCRVREFADJUST1_ch1SlowBW_WID ( 1) + #define DDRDATACH1_CR_DDRCRVREFADJUST1_ch1SlowBW_MSK (0x80000000) + #define DDRDATACH1_CR_DDRCRVREFADJUST1_ch1SlowBW_MAX (0x00000001) + #define DDRDATACH1_CR_DDRCRVREFADJUST1_ch1SlowBW_DEF (0x00000000) + +#define DDRDATA0CH0_CR_RXTRAINRANK0_REG (0x00000000) + #define DDRDATA0CH0_CR_RXTRAINRANK0_RxRcvEnPi_OFF ( 0) + #define DDRDATA0CH0_CR_RXTRAINRANK0_RxRcvEnPi_WID ( 9) + #define DDRDATA0CH0_CR_RXTRAINRANK0_RxRcvEnPi_MSK (0x000001FF) + #define DDRDATA0CH0_CR_RXTRAINRANK0_RxRcvEnPi_MAX (0x000001FF) + #define DDRDATA0CH0_CR_RXTRAINRANK0_RxDqsPPi_OFF ( 9) + #define DDRDATA0CH0_CR_RXTRAINRANK0_RxDqsPPi_WID ( 6) + #define DDRDATA0CH0_CR_RXTRAINRANK0_RxDqsPPi_MSK (0x00007E00) + #define DDRDATA0CH0_CR_RXTRAINRANK0_RxDqsPPi_MAX (0x0000003F) + #define DDRDATA0CH0_CR_RXTRAINRANK0_RxEq_OFF (15) + #define DDRDATA0CH0_CR_RXTRAINRANK0_RxEq_WID ( 5) + #define DDRDATA0CH0_CR_RXTRAINRANK0_RxEq_MSK (0x000F8000) + #define DDRDATA0CH0_CR_RXTRAINRANK0_RxEq_MAX (0x0000001F) + #define DDRDATA0CH0_CR_RXTRAINRANK0_RxDqsNPi_OFF (20) + #define DDRDATA0CH0_CR_RXTRAINRANK0_RxDqsNPi_WID ( 6) + #define DDRDATA0CH0_CR_RXTRAINRANK0_RxDqsNPi_MSK (0x03F00000) + #define DDRDATA0CH0_CR_RXTRAINRANK0_RxDqsNPi_MAX (0x0000003F) + #define DDRDATA0CH0_CR_RXTRAINRANK0_RxVref_OFF (26) + #define DDRDATA0CH0_CR_RXTRAINRANK0_RxVref_WID ( 6) + #define DDRDATA0CH0_CR_RXTRAINRANK0_RxVref_MSK (0xFC000000) + #define DDRDATA0CH0_CR_RXTRAINRANK0_RxVref_MAX (0x0000003F) + +#define DDRDATA0CH0_CR_RXTRAINRANK1_REG (0x00000004) + #define DDRDATA0CH0_CR_RXTRAINRANK1_RxRcvEnPi_OFF ( 0) + #define DDRDATA0CH0_CR_RXTRAINRANK1_RxRcvEnPi_WID ( 9) + #define DDRDATA0CH0_CR_RXTRAINRANK1_RxRcvEnPi_MSK (0x000001FF) + #define DDRDATA0CH0_CR_RXTRAINRANK1_RxRcvEnPi_MAX (0x000001FF) + #define DDRDATA0CH0_CR_RXTRAINRANK1_RxDqsPPi_OFF ( 9) + #define DDRDATA0CH0_CR_RXTRAINRANK1_RxDqsPPi_WID ( 6) + #define DDRDATA0CH0_CR_RXTRAINRANK1_RxDqsPPi_MSK (0x00007E00) + #define DDRDATA0CH0_CR_RXTRAINRANK1_RxDqsPPi_MAX (0x0000003F) + #define DDRDATA0CH0_CR_RXTRAINRANK1_RxEq_OFF (15) + #define DDRDATA0CH0_CR_RXTRAINRANK1_RxEq_WID ( 5) + #define DDRDATA0CH0_CR_RXTRAINRANK1_RxEq_MSK (0x000F8000) + #define DDRDATA0CH0_CR_RXTRAINRANK1_RxEq_MAX (0x0000001F) + #define DDRDATA0CH0_CR_RXTRAINRANK1_RxDqsNPi_OFF (20) + #define DDRDATA0CH0_CR_RXTRAINRANK1_RxDqsNPi_WID ( 6) + #define DDRDATA0CH0_CR_RXTRAINRANK1_RxDqsNPi_MSK (0x03F00000) + #define DDRDATA0CH0_CR_RXTRAINRANK1_RxDqsNPi_MAX (0x0000003F) + #define DDRDATA0CH0_CR_RXTRAINRANK1_RxVref_OFF (26) + #define DDRDATA0CH0_CR_RXTRAINRANK1_RxVref_WID ( 6) + #define DDRDATA0CH0_CR_RXTRAINRANK1_RxVref_MSK (0xFC000000) + #define DDRDATA0CH0_CR_RXTRAINRANK1_RxVref_MAX (0x0000003F) + +#define DDRDATA0CH0_CR_RXTRAINRANK2_REG (0x00000008) + #define DDRDATA0CH0_CR_RXTRAINRANK2_RxRcvEnPi_OFF ( 0) + #define DDRDATA0CH0_CR_RXTRAINRANK2_RxRcvEnPi_WID ( 9) + #define DDRDATA0CH0_CR_RXTRAINRANK2_RxRcvEnPi_MSK (0x000001FF) + #define DDRDATA0CH0_CR_RXTRAINRANK2_RxRcvEnPi_MAX (0x000001FF) + #define DDRDATA0CH0_CR_RXTRAINRANK2_RxDqsPPi_OFF ( 9) + #define DDRDATA0CH0_CR_RXTRAINRANK2_RxDqsPPi_WID ( 6) + #define DDRDATA0CH0_CR_RXTRAINRANK2_RxDqsPPi_MSK (0x00007E00) + #define DDRDATA0CH0_CR_RXTRAINRANK2_RxDqsPPi_MAX (0x0000003F) + #define DDRDATA0CH0_CR_RXTRAINRANK2_RxEq_OFF (15) + #define DDRDATA0CH0_CR_RXTRAINRANK2_RxEq_WID ( 5) + #define DDRDATA0CH0_CR_RXTRAINRANK2_RxEq_MSK (0x000F8000) + #define DDRDATA0CH0_CR_RXTRAINRANK2_RxEq_MAX (0x0000001F) + #define DDRDATA0CH0_CR_RXTRAINRANK2_RxDqsNPi_OFF (20) + #define DDRDATA0CH0_CR_RXTRAINRANK2_RxDqsNPi_WID ( 6) + #define DDRDATA0CH0_CR_RXTRAINRANK2_RxDqsNPi_MSK (0x03F00000) + #define DDRDATA0CH0_CR_RXTRAINRANK2_RxDqsNPi_MAX (0x0000003F) + #define DDRDATA0CH0_CR_RXTRAINRANK2_RxVref_OFF (26) + #define DDRDATA0CH0_CR_RXTRAINRANK2_RxVref_WID ( 6) + #define DDRDATA0CH0_CR_RXTRAINRANK2_RxVref_MSK (0xFC000000) + #define DDRDATA0CH0_CR_RXTRAINRANK2_RxVref_MAX (0x0000003F) + +#define DDRDATA0CH0_CR_RXTRAINRANK3_REG (0x0000000C) + #define DDRDATA0CH0_CR_RXTRAINRANK3_RxRcvEnPi_OFF ( 0) + #define DDRDATA0CH0_CR_RXTRAINRANK3_RxRcvEnPi_WID ( 9) + #define DDRDATA0CH0_CR_RXTRAINRANK3_RxRcvEnPi_MSK (0x000001FF) + #define DDRDATA0CH0_CR_RXTRAINRANK3_RxRcvEnPi_MAX (0x000001FF) + #define DDRDATA0CH0_CR_RXTRAINRANK3_RxDqsPPi_OFF ( 9) + #define DDRDATA0CH0_CR_RXTRAINRANK3_RxDqsPPi_WID ( 6) + #define DDRDATA0CH0_CR_RXTRAINRANK3_RxDqsPPi_MSK (0x00007E00) + #define DDRDATA0CH0_CR_RXTRAINRANK3_RxDqsPPi_MAX (0x0000003F) + #define DDRDATA0CH0_CR_RXTRAINRANK3_RxEq_OFF (15) + #define DDRDATA0CH0_CR_RXTRAINRANK3_RxEq_WID ( 5) + #define DDRDATA0CH0_CR_RXTRAINRANK3_RxEq_MSK (0x000F8000) + #define DDRDATA0CH0_CR_RXTRAINRANK3_RxEq_MAX (0x0000001F) + #define DDRDATA0CH0_CR_RXTRAINRANK3_RxDqsNPi_OFF (20) + #define DDRDATA0CH0_CR_RXTRAINRANK3_RxDqsNPi_WID ( 6) + #define DDRDATA0CH0_CR_RXTRAINRANK3_RxDqsNPi_MSK (0x03F00000) + #define DDRDATA0CH0_CR_RXTRAINRANK3_RxDqsNPi_MAX (0x0000003F) + #define DDRDATA0CH0_CR_RXTRAINRANK3_RxVref_OFF (26) + #define DDRDATA0CH0_CR_RXTRAINRANK3_RxVref_WID ( 6) + #define DDRDATA0CH0_CR_RXTRAINRANK3_RxVref_MSK (0xFC000000) + #define DDRDATA0CH0_CR_RXTRAINRANK3_RxVref_MAX (0x0000003F) + +#define DDRDATA0CH0_CR_RXPERBITRANK0_REG (0x00000010) + #define DDRDATA0CH0_CR_RXPERBITRANK0_Lane0_OFF ( 0) + #define DDRDATA0CH0_CR_RXPERBITRANK0_Lane0_WID ( 4) + #define DDRDATA0CH0_CR_RXPERBITRANK0_Lane0_MSK (0x0000000F) + #define DDRDATA0CH0_CR_RXPERBITRANK0_Lane0_MAX (0x0000000F) + #define DDRDATA0CH0_CR_RXPERBITRANK0_Lane1_OFF ( 4) + #define DDRDATA0CH0_CR_RXPERBITRANK0_Lane1_WID ( 4) + #define DDRDATA0CH0_CR_RXPERBITRANK0_Lane1_MSK (0x000000F0) + #define DDRDATA0CH0_CR_RXPERBITRANK0_Lane1_MAX (0x0000000F) + #define DDRDATA0CH0_CR_RXPERBITRANK0_Lane2_OFF ( 8) + #define DDRDATA0CH0_CR_RXPERBITRANK0_Lane2_WID ( 4) + #define DDRDATA0CH0_CR_RXPERBITRANK0_Lane2_MSK (0x00000F00) + #define DDRDATA0CH0_CR_RXPERBITRANK0_Lane2_MAX (0x0000000F) + #define DDRDATA0CH0_CR_RXPERBITRANK0_Lane3_OFF (12) + #define DDRDATA0CH0_CR_RXPERBITRANK0_Lane3_WID ( 4) + #define DDRDATA0CH0_CR_RXPERBITRANK0_Lane3_MSK (0x0000F000) + #define DDRDATA0CH0_CR_RXPERBITRANK0_Lane3_MAX (0x0000000F) + #define DDRDATA0CH0_CR_RXPERBITRANK0_Lane4_OFF (16) + #define DDRDATA0CH0_CR_RXPERBITRANK0_Lane4_WID ( 4) + #define DDRDATA0CH0_CR_RXPERBITRANK0_Lane4_MSK (0x000F0000) + #define DDRDATA0CH0_CR_RXPERBITRANK0_Lane4_MAX (0x0000000F) + #define DDRDATA0CH0_CR_RXPERBITRANK0_Lane5_OFF (20) + #define DDRDATA0CH0_CR_RXPERBITRANK0_Lane5_WID ( 4) + #define DDRDATA0CH0_CR_RXPERBITRANK0_Lane5_MSK (0x00F00000) + #define DDRDATA0CH0_CR_RXPERBITRANK0_Lane5_MAX (0x0000000F) + #define DDRDATA0CH0_CR_RXPERBITRANK0_Lane6_OFF (24) + #define DDRDATA0CH0_CR_RXPERBITRANK0_Lane6_WID ( 4) + #define DDRDATA0CH0_CR_RXPERBITRANK0_Lane6_MSK (0x0F000000) + #define DDRDATA0CH0_CR_RXPERBITRANK0_Lane6_MAX (0x0000000F) + #define DDRDATA0CH0_CR_RXPERBITRANK0_Lane7_OFF (28) + #define DDRDATA0CH0_CR_RXPERBITRANK0_Lane7_WID ( 4) + #define DDRDATA0CH0_CR_RXPERBITRANK0_Lane7_MSK (0xF0000000) + #define DDRDATA0CH0_CR_RXPERBITRANK0_Lane7_MAX (0x0000000F) + +#define DDRDATA0CH0_CR_RXPERBITRANK1_REG (0x00000014) + #define DDRDATA0CH0_CR_RXPERBITRANK1_Lane0_OFF ( 0) + #define DDRDATA0CH0_CR_RXPERBITRANK1_Lane0_WID ( 4) + #define DDRDATA0CH0_CR_RXPERBITRANK1_Lane0_MSK (0x0000000F) + #define DDRDATA0CH0_CR_RXPERBITRANK1_Lane0_MAX (0x0000000F) + #define DDRDATA0CH0_CR_RXPERBITRANK1_Lane1_OFF ( 4) + #define DDRDATA0CH0_CR_RXPERBITRANK1_Lane1_WID ( 4) + #define DDRDATA0CH0_CR_RXPERBITRANK1_Lane1_MSK (0x000000F0) + #define DDRDATA0CH0_CR_RXPERBITRANK1_Lane1_MAX (0x0000000F) + #define DDRDATA0CH0_CR_RXPERBITRANK1_Lane2_OFF ( 8) + #define DDRDATA0CH0_CR_RXPERBITRANK1_Lane2_WID ( 4) + #define DDRDATA0CH0_CR_RXPERBITRANK1_Lane2_MSK (0x00000F00) + #define DDRDATA0CH0_CR_RXPERBITRANK1_Lane2_MAX (0x0000000F) + #define DDRDATA0CH0_CR_RXPERBITRANK1_Lane3_OFF (12) + #define DDRDATA0CH0_CR_RXPERBITRANK1_Lane3_WID ( 4) + #define DDRDATA0CH0_CR_RXPERBITRANK1_Lane3_MSK (0x0000F000) + #define DDRDATA0CH0_CR_RXPERBITRANK1_Lane3_MAX (0x0000000F) + #define DDRDATA0CH0_CR_RXPERBITRANK1_Lane4_OFF (16) + #define DDRDATA0CH0_CR_RXPERBITRANK1_Lane4_WID ( 4) + #define DDRDATA0CH0_CR_RXPERBITRANK1_Lane4_MSK (0x000F0000) + #define DDRDATA0CH0_CR_RXPERBITRANK1_Lane4_MAX (0x0000000F) + #define DDRDATA0CH0_CR_RXPERBITRANK1_Lane5_OFF (20) + #define DDRDATA0CH0_CR_RXPERBITRANK1_Lane5_WID ( 4) + #define DDRDATA0CH0_CR_RXPERBITRANK1_Lane5_MSK (0x00F00000) + #define DDRDATA0CH0_CR_RXPERBITRANK1_Lane5_MAX (0x0000000F) + #define DDRDATA0CH0_CR_RXPERBITRANK1_Lane6_OFF (24) + #define DDRDATA0CH0_CR_RXPERBITRANK1_Lane6_WID ( 4) + #define DDRDATA0CH0_CR_RXPERBITRANK1_Lane6_MSK (0x0F000000) + #define DDRDATA0CH0_CR_RXPERBITRANK1_Lane6_MAX (0x0000000F) + #define DDRDATA0CH0_CR_RXPERBITRANK1_Lane7_OFF (28) + #define DDRDATA0CH0_CR_RXPERBITRANK1_Lane7_WID ( 4) + #define DDRDATA0CH0_CR_RXPERBITRANK1_Lane7_MSK (0xF0000000) + #define DDRDATA0CH0_CR_RXPERBITRANK1_Lane7_MAX (0x0000000F) + +#define DDRDATA0CH0_CR_RXPERBITRANK2_REG (0x00000018) + #define DDRDATA0CH0_CR_RXPERBITRANK2_Lane0_OFF ( 0) + #define DDRDATA0CH0_CR_RXPERBITRANK2_Lane0_WID ( 4) + #define DDRDATA0CH0_CR_RXPERBITRANK2_Lane0_MSK (0x0000000F) + #define DDRDATA0CH0_CR_RXPERBITRANK2_Lane0_MAX (0x0000000F) + #define DDRDATA0CH0_CR_RXPERBITRANK2_Lane1_OFF ( 4) + #define DDRDATA0CH0_CR_RXPERBITRANK2_Lane1_WID ( 4) + #define DDRDATA0CH0_CR_RXPERBITRANK2_Lane1_MSK (0x000000F0) + #define DDRDATA0CH0_CR_RXPERBITRANK2_Lane1_MAX (0x0000000F) + #define DDRDATA0CH0_CR_RXPERBITRANK2_Lane2_OFF ( 8) + #define DDRDATA0CH0_CR_RXPERBITRANK2_Lane2_WID ( 4) + #define DDRDATA0CH0_CR_RXPERBITRANK2_Lane2_MSK (0x00000F00) + #define DDRDATA0CH0_CR_RXPERBITRANK2_Lane2_MAX (0x0000000F) + #define DDRDATA0CH0_CR_RXPERBITRANK2_Lane3_OFF (12) + #define DDRDATA0CH0_CR_RXPERBITRANK2_Lane3_WID ( 4) + #define DDRDATA0CH0_CR_RXPERBITRANK2_Lane3_MSK (0x0000F000) + #define DDRDATA0CH0_CR_RXPERBITRANK2_Lane3_MAX (0x0000000F) + #define DDRDATA0CH0_CR_RXPERBITRANK2_Lane4_OFF (16) + #define DDRDATA0CH0_CR_RXPERBITRANK2_Lane4_WID ( 4) + #define DDRDATA0CH0_CR_RXPERBITRANK2_Lane4_MSK (0x000F0000) + #define DDRDATA0CH0_CR_RXPERBITRANK2_Lane4_MAX (0x0000000F) + #define DDRDATA0CH0_CR_RXPERBITRANK2_Lane5_OFF (20) + #define DDRDATA0CH0_CR_RXPERBITRANK2_Lane5_WID ( 4) + #define DDRDATA0CH0_CR_RXPERBITRANK2_Lane5_MSK (0x00F00000) + #define DDRDATA0CH0_CR_RXPERBITRANK2_Lane5_MAX (0x0000000F) + #define DDRDATA0CH0_CR_RXPERBITRANK2_Lane6_OFF (24) + #define DDRDATA0CH0_CR_RXPERBITRANK2_Lane6_WID ( 4) + #define DDRDATA0CH0_CR_RXPERBITRANK2_Lane6_MSK (0x0F000000) + #define DDRDATA0CH0_CR_RXPERBITRANK2_Lane6_MAX (0x0000000F) + #define DDRDATA0CH0_CR_RXPERBITRANK2_Lane7_OFF (28) + #define DDRDATA0CH0_CR_RXPERBITRANK2_Lane7_WID ( 4) + #define DDRDATA0CH0_CR_RXPERBITRANK2_Lane7_MSK (0xF0000000) + #define DDRDATA0CH0_CR_RXPERBITRANK2_Lane7_MAX (0x0000000F) + +#define DDRDATA0CH0_CR_RXPERBITRANK3_REG (0x0000001C) + #define DDRDATA0CH0_CR_RXPERBITRANK3_Lane0_OFF ( 0) + #define DDRDATA0CH0_CR_RXPERBITRANK3_Lane0_WID ( 4) + #define DDRDATA0CH0_CR_RXPERBITRANK3_Lane0_MSK (0x0000000F) + #define DDRDATA0CH0_CR_RXPERBITRANK3_Lane0_MAX (0x0000000F) + #define DDRDATA0CH0_CR_RXPERBITRANK3_Lane1_OFF ( 4) + #define DDRDATA0CH0_CR_RXPERBITRANK3_Lane1_WID ( 4) + #define DDRDATA0CH0_CR_RXPERBITRANK3_Lane1_MSK (0x000000F0) + #define DDRDATA0CH0_CR_RXPERBITRANK3_Lane1_MAX (0x0000000F) + #define DDRDATA0CH0_CR_RXPERBITRANK3_Lane2_OFF ( 8) + #define DDRDATA0CH0_CR_RXPERBITRANK3_Lane2_WID ( 4) + #define DDRDATA0CH0_CR_RXPERBITRANK3_Lane2_MSK (0x00000F00) + #define DDRDATA0CH0_CR_RXPERBITRANK3_Lane2_MAX (0x0000000F) + #define DDRDATA0CH0_CR_RXPERBITRANK3_Lane3_OFF (12) + #define DDRDATA0CH0_CR_RXPERBITRANK3_Lane3_WID ( 4) + #define DDRDATA0CH0_CR_RXPERBITRANK3_Lane3_MSK (0x0000F000) + #define DDRDATA0CH0_CR_RXPERBITRANK3_Lane3_MAX (0x0000000F) + #define DDRDATA0CH0_CR_RXPERBITRANK3_Lane4_OFF (16) + #define DDRDATA0CH0_CR_RXPERBITRANK3_Lane4_WID ( 4) + #define DDRDATA0CH0_CR_RXPERBITRANK3_Lane4_MSK (0x000F0000) + #define DDRDATA0CH0_CR_RXPERBITRANK3_Lane4_MAX (0x0000000F) + #define DDRDATA0CH0_CR_RXPERBITRANK3_Lane5_OFF (20) + #define DDRDATA0CH0_CR_RXPERBITRANK3_Lane5_WID ( 4) + #define DDRDATA0CH0_CR_RXPERBITRANK3_Lane5_MSK (0x00F00000) + #define DDRDATA0CH0_CR_RXPERBITRANK3_Lane5_MAX (0x0000000F) + #define DDRDATA0CH0_CR_RXPERBITRANK3_Lane6_OFF (24) + #define DDRDATA0CH0_CR_RXPERBITRANK3_Lane6_WID ( 4) + #define DDRDATA0CH0_CR_RXPERBITRANK3_Lane6_MSK (0x0F000000) + #define DDRDATA0CH0_CR_RXPERBITRANK3_Lane6_MAX (0x0000000F) + #define DDRDATA0CH0_CR_RXPERBITRANK3_Lane7_OFF (28) + #define DDRDATA0CH0_CR_RXPERBITRANK3_Lane7_WID ( 4) + #define DDRDATA0CH0_CR_RXPERBITRANK3_Lane7_MSK (0xF0000000) + #define DDRDATA0CH0_CR_RXPERBITRANK3_Lane7_MAX (0x0000000F) + +#define DDRDATA0CH0_CR_TXTRAINRANK0_REG (0x00000020) + #define DDRDATA0CH0_CR_TXTRAINRANK0_TxDqDelay_OFF ( 0) + #define DDRDATA0CH0_CR_TXTRAINRANK0_TxDqDelay_WID ( 9) + #define DDRDATA0CH0_CR_TXTRAINRANK0_TxDqDelay_MSK (0x000001FF) + #define DDRDATA0CH0_CR_TXTRAINRANK0_TxDqDelay_MAX (0x000001FF) + #define DDRDATA0CH0_CR_TXTRAINRANK0_TxDqsDelay_OFF ( 9) + #define DDRDATA0CH0_CR_TXTRAINRANK0_TxDqsDelay_WID ( 9) + #define DDRDATA0CH0_CR_TXTRAINRANK0_TxDqsDelay_MSK (0x0003FE00) + #define DDRDATA0CH0_CR_TXTRAINRANK0_TxDqsDelay_MAX (0x000001FF) + #define DDRDATA0CH0_CR_TXTRAINRANK0_Spare0_OFF (18) + #define DDRDATA0CH0_CR_TXTRAINRANK0_Spare0_WID ( 2) + #define DDRDATA0CH0_CR_TXTRAINRANK0_Spare0_MSK (0x000C0000) + #define DDRDATA0CH0_CR_TXTRAINRANK0_Spare0_MAX (0x00000003) + #define DDRDATA0CH0_CR_TXTRAINRANK0_TxEqualization_OFF (20) + #define DDRDATA0CH0_CR_TXTRAINRANK0_TxEqualization_WID ( 6) + #define DDRDATA0CH0_CR_TXTRAINRANK0_TxEqualization_MSK (0x03F00000) + #define DDRDATA0CH0_CR_TXTRAINRANK0_TxEqualization_MAX (0x0000003F) + #define DDRDATA0CH0_CR_TXTRAINRANK0_Spare1_OFF (26) + #define DDRDATA0CH0_CR_TXTRAINRANK0_Spare1_WID ( 6) + #define DDRDATA0CH0_CR_TXTRAINRANK0_Spare1_MSK (0xFC000000) + #define DDRDATA0CH0_CR_TXTRAINRANK0_Spare1_MAX (0x0000003F) + +#define DDRDATA0CH0_CR_TXTRAINRANK1_REG (0x00000024) + #define DDRDATA0CH0_CR_TXTRAINRANK1_TxDqDelay_OFF ( 0) + #define DDRDATA0CH0_CR_TXTRAINRANK1_TxDqDelay_WID ( 9) + #define DDRDATA0CH0_CR_TXTRAINRANK1_TxDqDelay_MSK (0x000001FF) + #define DDRDATA0CH0_CR_TXTRAINRANK1_TxDqDelay_MAX (0x000001FF) + #define DDRDATA0CH0_CR_TXTRAINRANK1_TxDqsDelay_OFF ( 9) + #define DDRDATA0CH0_CR_TXTRAINRANK1_TxDqsDelay_WID ( 9) + #define DDRDATA0CH0_CR_TXTRAINRANK1_TxDqsDelay_MSK (0x0003FE00) + #define DDRDATA0CH0_CR_TXTRAINRANK1_TxDqsDelay_MAX (0x000001FF) + #define DDRDATA0CH0_CR_TXTRAINRANK1_Spare0_OFF (18) + #define DDRDATA0CH0_CR_TXTRAINRANK1_Spare0_WID ( 2) + #define DDRDATA0CH0_CR_TXTRAINRANK1_Spare0_MSK (0x000C0000) + #define DDRDATA0CH0_CR_TXTRAINRANK1_Spare0_MAX (0x00000003) + #define DDRDATA0CH0_CR_TXTRAINRANK1_TxEqualization_OFF (20) + #define DDRDATA0CH0_CR_TXTRAINRANK1_TxEqualization_WID ( 6) + #define DDRDATA0CH0_CR_TXTRAINRANK1_TxEqualization_MSK (0x03F00000) + #define DDRDATA0CH0_CR_TXTRAINRANK1_TxEqualization_MAX (0x0000003F) + #define DDRDATA0CH0_CR_TXTRAINRANK1_Spare1_OFF (26) + #define DDRDATA0CH0_CR_TXTRAINRANK1_Spare1_WID ( 6) + #define DDRDATA0CH0_CR_TXTRAINRANK1_Spare1_MSK (0xFC000000) + #define DDRDATA0CH0_CR_TXTRAINRANK1_Spare1_MAX (0x0000003F) + +#define DDRDATA0CH0_CR_TXTRAINRANK2_REG (0x00000028) + #define DDRDATA0CH0_CR_TXTRAINRANK2_TxDqDelay_OFF ( 0) + #define DDRDATA0CH0_CR_TXTRAINRANK2_TxDqDelay_WID ( 9) + #define DDRDATA0CH0_CR_TXTRAINRANK2_TxDqDelay_MSK (0x000001FF) + #define DDRDATA0CH0_CR_TXTRAINRANK2_TxDqDelay_MAX (0x000001FF) + #define DDRDATA0CH0_CR_TXTRAINRANK2_TxDqsDelay_OFF ( 9) + #define DDRDATA0CH0_CR_TXTRAINRANK2_TxDqsDelay_WID ( 9) + #define DDRDATA0CH0_CR_TXTRAINRANK2_TxDqsDelay_MSK (0x0003FE00) + #define DDRDATA0CH0_CR_TXTRAINRANK2_TxDqsDelay_MAX (0x000001FF) + #define DDRDATA0CH0_CR_TXTRAINRANK2_Spare0_OFF (18) + #define DDRDATA0CH0_CR_TXTRAINRANK2_Spare0_WID ( 2) + #define DDRDATA0CH0_CR_TXTRAINRANK2_Spare0_MSK (0x000C0000) + #define DDRDATA0CH0_CR_TXTRAINRANK2_Spare0_MAX (0x00000003) + #define DDRDATA0CH0_CR_TXTRAINRANK2_TxEqualization_OFF (20) + #define DDRDATA0CH0_CR_TXTRAINRANK2_TxEqualization_WID ( 6) + #define DDRDATA0CH0_CR_TXTRAINRANK2_TxEqualization_MSK (0x03F00000) + #define DDRDATA0CH0_CR_TXTRAINRANK2_TxEqualization_MAX (0x0000003F) + #define DDRDATA0CH0_CR_TXTRAINRANK2_Spare1_OFF (26) + #define DDRDATA0CH0_CR_TXTRAINRANK2_Spare1_WID ( 6) + #define DDRDATA0CH0_CR_TXTRAINRANK2_Spare1_MSK (0xFC000000) + #define DDRDATA0CH0_CR_TXTRAINRANK2_Spare1_MAX (0x0000003F) + +#define DDRDATA0CH0_CR_TXTRAINRANK3_REG (0x0000002C) + #define DDRDATA0CH0_CR_TXTRAINRANK3_TxDqDelay_OFF ( 0) + #define DDRDATA0CH0_CR_TXTRAINRANK3_TxDqDelay_WID ( 9) + #define DDRDATA0CH0_CR_TXTRAINRANK3_TxDqDelay_MSK (0x000001FF) + #define DDRDATA0CH0_CR_TXTRAINRANK3_TxDqDelay_MAX (0x000001FF) + #define DDRDATA0CH0_CR_TXTRAINRANK3_TxDqsDelay_OFF ( 9) + #define DDRDATA0CH0_CR_TXTRAINRANK3_TxDqsDelay_WID ( 9) + #define DDRDATA0CH0_CR_TXTRAINRANK3_TxDqsDelay_MSK (0x0003FE00) + #define DDRDATA0CH0_CR_TXTRAINRANK3_TxDqsDelay_MAX (0x000001FF) + #define DDRDATA0CH0_CR_TXTRAINRANK3_Spare0_OFF (18) + #define DDRDATA0CH0_CR_TXTRAINRANK3_Spare0_WID ( 2) + #define DDRDATA0CH0_CR_TXTRAINRANK3_Spare0_MSK (0x000C0000) + #define DDRDATA0CH0_CR_TXTRAINRANK3_Spare0_MAX (0x00000003) + #define DDRDATA0CH0_CR_TXTRAINRANK3_TxEqualization_OFF (20) + #define DDRDATA0CH0_CR_TXTRAINRANK3_TxEqualization_WID ( 6) + #define DDRDATA0CH0_CR_TXTRAINRANK3_TxEqualization_MSK (0x03F00000) + #define DDRDATA0CH0_CR_TXTRAINRANK3_TxEqualization_MAX (0x0000003F) + #define DDRDATA0CH0_CR_TXTRAINRANK3_Spare1_OFF (26) + #define DDRDATA0CH0_CR_TXTRAINRANK3_Spare1_WID ( 6) + #define DDRDATA0CH0_CR_TXTRAINRANK3_Spare1_MSK (0xFC000000) + #define DDRDATA0CH0_CR_TXTRAINRANK3_Spare1_MAX (0x0000003F) + +#define DDRDATA0CH0_CR_TXPERBITRANK0_REG (0x00000030) + #define DDRDATA0CH0_CR_TXPERBITRANK0_Lane0_OFF ( 0) + #define DDRDATA0CH0_CR_TXPERBITRANK0_Lane0_WID ( 4) + #define DDRDATA0CH0_CR_TXPERBITRANK0_Lane0_MSK (0x0000000F) + #define DDRDATA0CH0_CR_TXPERBITRANK0_Lane0_MAX (0x0000000F) + #define DDRDATA0CH0_CR_TXPERBITRANK0_Lane1_OFF ( 4) + #define DDRDATA0CH0_CR_TXPERBITRANK0_Lane1_WID ( 4) + #define DDRDATA0CH0_CR_TXPERBITRANK0_Lane1_MSK (0x000000F0) + #define DDRDATA0CH0_CR_TXPERBITRANK0_Lane1_MAX (0x0000000F) + #define DDRDATA0CH0_CR_TXPERBITRANK0_Lane2_OFF ( 8) + #define DDRDATA0CH0_CR_TXPERBITRANK0_Lane2_WID ( 4) + #define DDRDATA0CH0_CR_TXPERBITRANK0_Lane2_MSK (0x00000F00) + #define DDRDATA0CH0_CR_TXPERBITRANK0_Lane2_MAX (0x0000000F) + #define DDRDATA0CH0_CR_TXPERBITRANK0_Lane3_OFF (12) + #define DDRDATA0CH0_CR_TXPERBITRANK0_Lane3_WID ( 4) + #define DDRDATA0CH0_CR_TXPERBITRANK0_Lane3_MSK (0x0000F000) + #define DDRDATA0CH0_CR_TXPERBITRANK0_Lane3_MAX (0x0000000F) + #define DDRDATA0CH0_CR_TXPERBITRANK0_Lane4_OFF (16) + #define DDRDATA0CH0_CR_TXPERBITRANK0_Lane4_WID ( 4) + #define DDRDATA0CH0_CR_TXPERBITRANK0_Lane4_MSK (0x000F0000) + #define DDRDATA0CH0_CR_TXPERBITRANK0_Lane4_MAX (0x0000000F) + #define DDRDATA0CH0_CR_TXPERBITRANK0_Lane5_OFF (20) + #define DDRDATA0CH0_CR_TXPERBITRANK0_Lane5_WID ( 4) + #define DDRDATA0CH0_CR_TXPERBITRANK0_Lane5_MSK (0x00F00000) + #define DDRDATA0CH0_CR_TXPERBITRANK0_Lane5_MAX (0x0000000F) + #define DDRDATA0CH0_CR_TXPERBITRANK0_Lane6_OFF (24) + #define DDRDATA0CH0_CR_TXPERBITRANK0_Lane6_WID ( 4) + #define DDRDATA0CH0_CR_TXPERBITRANK0_Lane6_MSK (0x0F000000) + #define DDRDATA0CH0_CR_TXPERBITRANK0_Lane6_MAX (0x0000000F) + #define DDRDATA0CH0_CR_TXPERBITRANK0_Lane7_OFF (28) + #define DDRDATA0CH0_CR_TXPERBITRANK0_Lane7_WID ( 4) + #define DDRDATA0CH0_CR_TXPERBITRANK0_Lane7_MSK (0xF0000000) + #define DDRDATA0CH0_CR_TXPERBITRANK0_Lane7_MAX (0x0000000F) + +#define DDRDATA0CH0_CR_TXPERBITRANK1_REG (0x00000034) + #define DDRDATA0CH0_CR_TXPERBITRANK1_Lane0_OFF ( 0) + #define DDRDATA0CH0_CR_TXPERBITRANK1_Lane0_WID ( 4) + #define DDRDATA0CH0_CR_TXPERBITRANK1_Lane0_MSK (0x0000000F) + #define DDRDATA0CH0_CR_TXPERBITRANK1_Lane0_MAX (0x0000000F) + #define DDRDATA0CH0_CR_TXPERBITRANK1_Lane1_OFF ( 4) + #define DDRDATA0CH0_CR_TXPERBITRANK1_Lane1_WID ( 4) + #define DDRDATA0CH0_CR_TXPERBITRANK1_Lane1_MSK (0x000000F0) + #define DDRDATA0CH0_CR_TXPERBITRANK1_Lane1_MAX (0x0000000F) + #define DDRDATA0CH0_CR_TXPERBITRANK1_Lane2_OFF ( 8) + #define DDRDATA0CH0_CR_TXPERBITRANK1_Lane2_WID ( 4) + #define DDRDATA0CH0_CR_TXPERBITRANK1_Lane2_MSK (0x00000F00) + #define DDRDATA0CH0_CR_TXPERBITRANK1_Lane2_MAX (0x0000000F) + #define DDRDATA0CH0_CR_TXPERBITRANK1_Lane3_OFF (12) + #define DDRDATA0CH0_CR_TXPERBITRANK1_Lane3_WID ( 4) + #define DDRDATA0CH0_CR_TXPERBITRANK1_Lane3_MSK (0x0000F000) + #define DDRDATA0CH0_CR_TXPERBITRANK1_Lane3_MAX (0x0000000F) + #define DDRDATA0CH0_CR_TXPERBITRANK1_Lane4_OFF (16) + #define DDRDATA0CH0_CR_TXPERBITRANK1_Lane4_WID ( 4) + #define DDRDATA0CH0_CR_TXPERBITRANK1_Lane4_MSK (0x000F0000) + #define DDRDATA0CH0_CR_TXPERBITRANK1_Lane4_MAX (0x0000000F) + #define DDRDATA0CH0_CR_TXPERBITRANK1_Lane5_OFF (20) + #define DDRDATA0CH0_CR_TXPERBITRANK1_Lane5_WID ( 4) + #define DDRDATA0CH0_CR_TXPERBITRANK1_Lane5_MSK (0x00F00000) + #define DDRDATA0CH0_CR_TXPERBITRANK1_Lane5_MAX (0x0000000F) + #define DDRDATA0CH0_CR_TXPERBITRANK1_Lane6_OFF (24) + #define DDRDATA0CH0_CR_TXPERBITRANK1_Lane6_WID ( 4) + #define DDRDATA0CH0_CR_TXPERBITRANK1_Lane6_MSK (0x0F000000) + #define DDRDATA0CH0_CR_TXPERBITRANK1_Lane6_MAX (0x0000000F) + #define DDRDATA0CH0_CR_TXPERBITRANK1_Lane7_OFF (28) + #define DDRDATA0CH0_CR_TXPERBITRANK1_Lane7_WID ( 4) + #define DDRDATA0CH0_CR_TXPERBITRANK1_Lane7_MSK (0xF0000000) + #define DDRDATA0CH0_CR_TXPERBITRANK1_Lane7_MAX (0x0000000F) + +#define DDRDATA0CH0_CR_TXPERBITRANK2_REG (0x00000038) + #define DDRDATA0CH0_CR_TXPERBITRANK2_Lane0_OFF ( 0) + #define DDRDATA0CH0_CR_TXPERBITRANK2_Lane0_WID ( 4) + #define DDRDATA0CH0_CR_TXPERBITRANK2_Lane0_MSK (0x0000000F) + #define DDRDATA0CH0_CR_TXPERBITRANK2_Lane0_MAX (0x0000000F) + #define DDRDATA0CH0_CR_TXPERBITRANK2_Lane1_OFF ( 4) + #define DDRDATA0CH0_CR_TXPERBITRANK2_Lane1_WID ( 4) + #define DDRDATA0CH0_CR_TXPERBITRANK2_Lane1_MSK (0x000000F0) + #define DDRDATA0CH0_CR_TXPERBITRANK2_Lane1_MAX (0x0000000F) + #define DDRDATA0CH0_CR_TXPERBITRANK2_Lane2_OFF ( 8) + #define DDRDATA0CH0_CR_TXPERBITRANK2_Lane2_WID ( 4) + #define DDRDATA0CH0_CR_TXPERBITRANK2_Lane2_MSK (0x00000F00) + #define DDRDATA0CH0_CR_TXPERBITRANK2_Lane2_MAX (0x0000000F) + #define DDRDATA0CH0_CR_TXPERBITRANK2_Lane3_OFF (12) + #define DDRDATA0CH0_CR_TXPERBITRANK2_Lane3_WID ( 4) + #define DDRDATA0CH0_CR_TXPERBITRANK2_Lane3_MSK (0x0000F000) + #define DDRDATA0CH0_CR_TXPERBITRANK2_Lane3_MAX (0x0000000F) + #define DDRDATA0CH0_CR_TXPERBITRANK2_Lane4_OFF (16) + #define DDRDATA0CH0_CR_TXPERBITRANK2_Lane4_WID ( 4) + #define DDRDATA0CH0_CR_TXPERBITRANK2_Lane4_MSK (0x000F0000) + #define DDRDATA0CH0_CR_TXPERBITRANK2_Lane4_MAX (0x0000000F) + #define DDRDATA0CH0_CR_TXPERBITRANK2_Lane5_OFF (20) + #define DDRDATA0CH0_CR_TXPERBITRANK2_Lane5_WID ( 4) + #define DDRDATA0CH0_CR_TXPERBITRANK2_Lane5_MSK (0x00F00000) + #define DDRDATA0CH0_CR_TXPERBITRANK2_Lane5_MAX (0x0000000F) + #define DDRDATA0CH0_CR_TXPERBITRANK2_Lane6_OFF (24) + #define DDRDATA0CH0_CR_TXPERBITRANK2_Lane6_WID ( 4) + #define DDRDATA0CH0_CR_TXPERBITRANK2_Lane6_MSK (0x0F000000) + #define DDRDATA0CH0_CR_TXPERBITRANK2_Lane6_MAX (0x0000000F) + #define DDRDATA0CH0_CR_TXPERBITRANK2_Lane7_OFF (28) + #define DDRDATA0CH0_CR_TXPERBITRANK2_Lane7_WID ( 4) + #define DDRDATA0CH0_CR_TXPERBITRANK2_Lane7_MSK (0xF0000000) + #define DDRDATA0CH0_CR_TXPERBITRANK2_Lane7_MAX (0x0000000F) + +#define DDRDATA0CH0_CR_TXPERBITRANK3_REG (0x0000003C) + #define DDRDATA0CH0_CR_TXPERBITRANK3_Lane0_OFF ( 0) + #define DDRDATA0CH0_CR_TXPERBITRANK3_Lane0_WID ( 4) + #define DDRDATA0CH0_CR_TXPERBITRANK3_Lane0_MSK (0x0000000F) + #define DDRDATA0CH0_CR_TXPERBITRANK3_Lane0_MAX (0x0000000F) + #define DDRDATA0CH0_CR_TXPERBITRANK3_Lane1_OFF ( 4) + #define DDRDATA0CH0_CR_TXPERBITRANK3_Lane1_WID ( 4) + #define DDRDATA0CH0_CR_TXPERBITRANK3_Lane1_MSK (0x000000F0) + #define DDRDATA0CH0_CR_TXPERBITRANK3_Lane1_MAX (0x0000000F) + #define DDRDATA0CH0_CR_TXPERBITRANK3_Lane2_OFF ( 8) + #define DDRDATA0CH0_CR_TXPERBITRANK3_Lane2_WID ( 4) + #define DDRDATA0CH0_CR_TXPERBITRANK3_Lane2_MSK (0x00000F00) + #define DDRDATA0CH0_CR_TXPERBITRANK3_Lane2_MAX (0x0000000F) + #define DDRDATA0CH0_CR_TXPERBITRANK3_Lane3_OFF (12) + #define DDRDATA0CH0_CR_TXPERBITRANK3_Lane3_WID ( 4) + #define DDRDATA0CH0_CR_TXPERBITRANK3_Lane3_MSK (0x0000F000) + #define DDRDATA0CH0_CR_TXPERBITRANK3_Lane3_MAX (0x0000000F) + #define DDRDATA0CH0_CR_TXPERBITRANK3_Lane4_OFF (16) + #define DDRDATA0CH0_CR_TXPERBITRANK3_Lane4_WID ( 4) + #define DDRDATA0CH0_CR_TXPERBITRANK3_Lane4_MSK (0x000F0000) + #define DDRDATA0CH0_CR_TXPERBITRANK3_Lane4_MAX (0x0000000F) + #define DDRDATA0CH0_CR_TXPERBITRANK3_Lane5_OFF (20) + #define DDRDATA0CH0_CR_TXPERBITRANK3_Lane5_WID ( 4) + #define DDRDATA0CH0_CR_TXPERBITRANK3_Lane5_MSK (0x00F00000) + #define DDRDATA0CH0_CR_TXPERBITRANK3_Lane5_MAX (0x0000000F) + #define DDRDATA0CH0_CR_TXPERBITRANK3_Lane6_OFF (24) + #define DDRDATA0CH0_CR_TXPERBITRANK3_Lane6_WID ( 4) + #define DDRDATA0CH0_CR_TXPERBITRANK3_Lane6_MSK (0x0F000000) + #define DDRDATA0CH0_CR_TXPERBITRANK3_Lane6_MAX (0x0000000F) + #define DDRDATA0CH0_CR_TXPERBITRANK3_Lane7_OFF (28) + #define DDRDATA0CH0_CR_TXPERBITRANK3_Lane7_WID ( 4) + #define DDRDATA0CH0_CR_TXPERBITRANK3_Lane7_MSK (0xF0000000) + #define DDRDATA0CH0_CR_TXPERBITRANK3_Lane7_MAX (0x0000000F) + +#define DDRDATA0CH0_CR_RCOMPDATA0_REG (0x00000040) + #define DDRDATA0CH0_CR_RCOMPDATA0_RcompDrvUp_OFF ( 0) + #define DDRDATA0CH0_CR_RCOMPDATA0_RcompDrvUp_WID ( 6) + #define DDRDATA0CH0_CR_RCOMPDATA0_RcompDrvUp_MSK (0x0000003F) + #define DDRDATA0CH0_CR_RCOMPDATA0_RcompDrvUp_MAX (0x0000003F) + #define DDRDATA0CH0_CR_RCOMPDATA0_Spare0_OFF ( 6) + #define DDRDATA0CH0_CR_RCOMPDATA0_Spare0_WID ( 3) + #define DDRDATA0CH0_CR_RCOMPDATA0_Spare0_MSK (0x000001C0) + #define DDRDATA0CH0_CR_RCOMPDATA0_Spare0_MAX (0x00000007) + #define DDRDATA0CH0_CR_RCOMPDATA0_RcompDrvDown_OFF ( 9) + #define DDRDATA0CH0_CR_RCOMPDATA0_RcompDrvDown_WID ( 6) + #define DDRDATA0CH0_CR_RCOMPDATA0_RcompDrvDown_MSK (0x00007E00) + #define DDRDATA0CH0_CR_RCOMPDATA0_RcompDrvDown_MAX (0x0000003F) + #define DDRDATA0CH0_CR_RCOMPDATA0_VTComp_OFF (15) + #define DDRDATA0CH0_CR_RCOMPDATA0_VTComp_WID ( 5) + #define DDRDATA0CH0_CR_RCOMPDATA0_VTComp_MSK (0x000F8000) + #define DDRDATA0CH0_CR_RCOMPDATA0_VTComp_MAX (0x0000001F) + #define DDRDATA0CH0_CR_RCOMPDATA0_TcoComp_OFF (20) + #define DDRDATA0CH0_CR_RCOMPDATA0_TcoComp_WID ( 6) + #define DDRDATA0CH0_CR_RCOMPDATA0_TcoComp_MSK (0x03F00000) + #define DDRDATA0CH0_CR_RCOMPDATA0_TcoComp_MAX (0x0000003F) + #define DDRDATA0CH0_CR_RCOMPDATA0_SlewRateComp_OFF (26) + #define DDRDATA0CH0_CR_RCOMPDATA0_SlewRateComp_WID ( 5) + #define DDRDATA0CH0_CR_RCOMPDATA0_SlewRateComp_MSK (0x7C000000) + #define DDRDATA0CH0_CR_RCOMPDATA0_SlewRateComp_MAX (0x0000001F) + #define DDRDATA0CH0_CR_RCOMPDATA0_Spare2_OFF (31) + #define DDRDATA0CH0_CR_RCOMPDATA0_Spare2_WID ( 1) + #define DDRDATA0CH0_CR_RCOMPDATA0_Spare2_MSK (0x80000000) + #define DDRDATA0CH0_CR_RCOMPDATA0_Spare2_MAX (0x00000001) + +#define DDRDATA0CH0_CR_RCOMPDATA1_REG (0x00000044) + #define DDRDATA0CH0_CR_RCOMPDATA1_RcompOdtUp_OFF ( 0) + #define DDRDATA0CH0_CR_RCOMPDATA1_RcompOdtUp_WID ( 6) + #define DDRDATA0CH0_CR_RCOMPDATA1_RcompOdtUp_MSK (0x0000003F) + #define DDRDATA0CH0_CR_RCOMPDATA1_RcompOdtUp_MAX (0x0000003F) + #define DDRDATA0CH0_CR_RCOMPDATA1_Spare0_OFF ( 6) + #define DDRDATA0CH0_CR_RCOMPDATA1_Spare0_WID ( 3) + #define DDRDATA0CH0_CR_RCOMPDATA1_Spare0_MSK (0x000001C0) + #define DDRDATA0CH0_CR_RCOMPDATA1_Spare0_MAX (0x00000007) + #define DDRDATA0CH0_CR_RCOMPDATA1_RcompOdtDown_OFF ( 9) + #define DDRDATA0CH0_CR_RCOMPDATA1_RcompOdtDown_WID ( 6) + #define DDRDATA0CH0_CR_RCOMPDATA1_RcompOdtDown_MSK (0x00007E00) + #define DDRDATA0CH0_CR_RCOMPDATA1_RcompOdtDown_MAX (0x0000003F) + #define DDRDATA0CH0_CR_RCOMPDATA1_Spare1_OFF (15) + #define DDRDATA0CH0_CR_RCOMPDATA1_Spare1_WID ( 1) + #define DDRDATA0CH0_CR_RCOMPDATA1_Spare1_MSK (0x00008000) + #define DDRDATA0CH0_CR_RCOMPDATA1_Spare1_MAX (0x00000001) + #define DDRDATA0CH0_CR_RCOMPDATA1_PanicDrvDn_OFF (16) + #define DDRDATA0CH0_CR_RCOMPDATA1_PanicDrvDn_WID ( 6) + #define DDRDATA0CH0_CR_RCOMPDATA1_PanicDrvDn_MSK (0x003F0000) + #define DDRDATA0CH0_CR_RCOMPDATA1_PanicDrvDn_MAX (0x0000003F) + #define DDRDATA0CH0_CR_RCOMPDATA1_PanicDrvUp_OFF (22) + #define DDRDATA0CH0_CR_RCOMPDATA1_PanicDrvUp_WID ( 6) + #define DDRDATA0CH0_CR_RCOMPDATA1_PanicDrvUp_MSK (0x0FC00000) + #define DDRDATA0CH0_CR_RCOMPDATA1_PanicDrvUp_MAX (0x0000003F) + #define DDRDATA0CH0_CR_RCOMPDATA1_LevelShifterComp_OFF (28) + #define DDRDATA0CH0_CR_RCOMPDATA1_LevelShifterComp_WID ( 3) + #define DDRDATA0CH0_CR_RCOMPDATA1_LevelShifterComp_MSK (0x70000000) + #define DDRDATA0CH0_CR_RCOMPDATA1_LevelShifterComp_MAX (0x00000007) + #define DDRDATA0CH0_CR_RCOMPDATA1_Spare2_OFF (31) + #define DDRDATA0CH0_CR_RCOMPDATA1_Spare2_WID ( 1) + #define DDRDATA0CH0_CR_RCOMPDATA1_Spare2_MSK (0x80000000) + #define DDRDATA0CH0_CR_RCOMPDATA1_Spare2_MAX (0x00000001) + +#define DDRDATA0CH0_CR_TXXTALK_REG (0x00000048) + #define DDRDATA0CH0_CR_TXXTALK_Lane0_OFF ( 0) + #define DDRDATA0CH0_CR_TXXTALK_Lane0_WID ( 4) + #define DDRDATA0CH0_CR_TXXTALK_Lane0_MSK (0x0000000F) + #define DDRDATA0CH0_CR_TXXTALK_Lane0_MAX (0x0000000F) + #define DDRDATA0CH0_CR_TXXTALK_Lane1_OFF ( 4) + #define DDRDATA0CH0_CR_TXXTALK_Lane1_WID ( 4) + #define DDRDATA0CH0_CR_TXXTALK_Lane1_MSK (0x000000F0) + #define DDRDATA0CH0_CR_TXXTALK_Lane1_MAX (0x0000000F) + #define DDRDATA0CH0_CR_TXXTALK_Lane2_OFF ( 8) + #define DDRDATA0CH0_CR_TXXTALK_Lane2_WID ( 4) + #define DDRDATA0CH0_CR_TXXTALK_Lane2_MSK (0x00000F00) + #define DDRDATA0CH0_CR_TXXTALK_Lane2_MAX (0x0000000F) + #define DDRDATA0CH0_CR_TXXTALK_Lane3_OFF (12) + #define DDRDATA0CH0_CR_TXXTALK_Lane3_WID ( 4) + #define DDRDATA0CH0_CR_TXXTALK_Lane3_MSK (0x0000F000) + #define DDRDATA0CH0_CR_TXXTALK_Lane3_MAX (0x0000000F) + #define DDRDATA0CH0_CR_TXXTALK_Lane4_OFF (16) + #define DDRDATA0CH0_CR_TXXTALK_Lane4_WID ( 4) + #define DDRDATA0CH0_CR_TXXTALK_Lane4_MSK (0x000F0000) + #define DDRDATA0CH0_CR_TXXTALK_Lane4_MAX (0x0000000F) + #define DDRDATA0CH0_CR_TXXTALK_Lane5_OFF (20) + #define DDRDATA0CH0_CR_TXXTALK_Lane5_WID ( 4) + #define DDRDATA0CH0_CR_TXXTALK_Lane5_MSK (0x00F00000) + #define DDRDATA0CH0_CR_TXXTALK_Lane5_MAX (0x0000000F) + #define DDRDATA0CH0_CR_TXXTALK_Lane6_OFF (24) + #define DDRDATA0CH0_CR_TXXTALK_Lane6_WID ( 4) + #define DDRDATA0CH0_CR_TXXTALK_Lane6_MSK (0x0F000000) + #define DDRDATA0CH0_CR_TXXTALK_Lane6_MAX (0x0000000F) + #define DDRDATA0CH0_CR_TXXTALK_Lane7_OFF (28) + #define DDRDATA0CH0_CR_TXXTALK_Lane7_WID ( 4) + #define DDRDATA0CH0_CR_TXXTALK_Lane7_MSK (0xF0000000) + #define DDRDATA0CH0_CR_TXXTALK_Lane7_MAX (0x0000000F) + +#define DDRDATA0CH0_CR_RXOFFSETVDQ_REG (0x0000004C) + #define DDRDATA0CH0_CR_RXOFFSETVDQ_Lane0_OFF ( 0) + #define DDRDATA0CH0_CR_RXOFFSETVDQ_Lane0_WID ( 4) + #define DDRDATA0CH0_CR_RXOFFSETVDQ_Lane0_MSK (0x0000000F) + #define DDRDATA0CH0_CR_RXOFFSETVDQ_Lane0_MAX (0x0000000F) + #define DDRDATA0CH0_CR_RXOFFSETVDQ_Lane1_OFF ( 4) + #define DDRDATA0CH0_CR_RXOFFSETVDQ_Lane1_WID ( 4) + #define DDRDATA0CH0_CR_RXOFFSETVDQ_Lane1_MSK (0x000000F0) + #define DDRDATA0CH0_CR_RXOFFSETVDQ_Lane1_MAX (0x0000000F) + #define DDRDATA0CH0_CR_RXOFFSETVDQ_Lane2_OFF ( 8) + #define DDRDATA0CH0_CR_RXOFFSETVDQ_Lane2_WID ( 4) + #define DDRDATA0CH0_CR_RXOFFSETVDQ_Lane2_MSK (0x00000F00) + #define DDRDATA0CH0_CR_RXOFFSETVDQ_Lane2_MAX (0x0000000F) + #define DDRDATA0CH0_CR_RXOFFSETVDQ_Lane3_OFF (12) + #define DDRDATA0CH0_CR_RXOFFSETVDQ_Lane3_WID ( 4) + #define DDRDATA0CH0_CR_RXOFFSETVDQ_Lane3_MSK (0x0000F000) + #define DDRDATA0CH0_CR_RXOFFSETVDQ_Lane3_MAX (0x0000000F) + #define DDRDATA0CH0_CR_RXOFFSETVDQ_Lane4_OFF (16) + #define DDRDATA0CH0_CR_RXOFFSETVDQ_Lane4_WID ( 4) + #define DDRDATA0CH0_CR_RXOFFSETVDQ_Lane4_MSK (0x000F0000) + #define DDRDATA0CH0_CR_RXOFFSETVDQ_Lane4_MAX (0x0000000F) + #define DDRDATA0CH0_CR_RXOFFSETVDQ_Lane5_OFF (20) + #define DDRDATA0CH0_CR_RXOFFSETVDQ_Lane5_WID ( 4) + #define DDRDATA0CH0_CR_RXOFFSETVDQ_Lane5_MSK (0x00F00000) + #define DDRDATA0CH0_CR_RXOFFSETVDQ_Lane5_MAX (0x0000000F) + #define DDRDATA0CH0_CR_RXOFFSETVDQ_Lane6_OFF (24) + #define DDRDATA0CH0_CR_RXOFFSETVDQ_Lane6_WID ( 4) + #define DDRDATA0CH0_CR_RXOFFSETVDQ_Lane6_MSK (0x0F000000) + #define DDRDATA0CH0_CR_RXOFFSETVDQ_Lane6_MAX (0x0000000F) + #define DDRDATA0CH0_CR_RXOFFSETVDQ_Lane7_OFF (28) + #define DDRDATA0CH0_CR_RXOFFSETVDQ_Lane7_WID ( 4) + #define DDRDATA0CH0_CR_RXOFFSETVDQ_Lane7_MSK (0xF0000000) + #define DDRDATA0CH0_CR_RXOFFSETVDQ_Lane7_MAX (0x0000000F) + +#define DDRDATA0CH0_CR_DDRDATARESERVED_REG (0x00000050) + #define DDRDATA0CH0_CR_DDRDATARESERVED_Spare_OFF ( 0) + #define DDRDATA0CH0_CR_DDRDATARESERVED_Spare_WID (32) + #define DDRDATA0CH0_CR_DDRDATARESERVED_Spare_MSK (0xFFFFFFFF) + #define DDRDATA0CH0_CR_DDRDATARESERVED_Spare_MAX (0xFFFFFFFF) + +#define DDRDATA0CH0_CR_DATATRAINFEEDBACK_REG (0x00000054) + #define DDRDATA0CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_OFF ( 0) + #define DDRDATA0CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_WID ( 9) + #define DDRDATA0CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_MSK (0x000001FF) + #define DDRDATA0CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_MAX (0x000001FF) + #define DDRDATA0CH0_CR_DATATRAINFEEDBACK_Spare_OFF ( 9) + #define DDRDATA0CH0_CR_DATATRAINFEEDBACK_Spare_WID (23) + #define DDRDATA0CH0_CR_DATATRAINFEEDBACK_Spare_MSK (0xFFFFFE00) + #define DDRDATA0CH0_CR_DATATRAINFEEDBACK_Spare_MAX (0x007FFFFF) + +#define DDRDATA0CH0_CR_DLLPITESTANDADC_REG (0x00000058) + #define DDRDATA0CH0_CR_DLLPITESTANDADC_RunTest_OFF ( 0) + #define DDRDATA0CH0_CR_DLLPITESTANDADC_RunTest_WID ( 1) + #define DDRDATA0CH0_CR_DLLPITESTANDADC_RunTest_MSK (0x00000001) + #define DDRDATA0CH0_CR_DLLPITESTANDADC_RunTest_MAX (0x00000001) + #define DDRDATA0CH0_CR_DLLPITESTANDADC_RunTest_DEF (0x00000000) + #define DDRDATA0CH0_CR_DLLPITESTANDADC_Load_OFF ( 1) + #define DDRDATA0CH0_CR_DLLPITESTANDADC_Load_WID ( 1) + #define DDRDATA0CH0_CR_DLLPITESTANDADC_Load_MSK (0x00000002) + #define DDRDATA0CH0_CR_DLLPITESTANDADC_Load_MAX (0x00000001) + #define DDRDATA0CH0_CR_DLLPITESTANDADC_Load_DEF (0x00000000) + #define DDRDATA0CH0_CR_DLLPITESTANDADC_ModeHVM_OFF ( 2) + #define DDRDATA0CH0_CR_DLLPITESTANDADC_ModeHVM_WID ( 1) + #define DDRDATA0CH0_CR_DLLPITESTANDADC_ModeHVM_MSK (0x00000004) + #define DDRDATA0CH0_CR_DLLPITESTANDADC_ModeHVM_MAX (0x00000001) + #define DDRDATA0CH0_CR_DLLPITESTANDADC_ModeHVM_DEF (0x00000000) + #define DDRDATA0CH0_CR_DLLPITESTANDADC_ModeDV_OFF ( 3) + #define DDRDATA0CH0_CR_DLLPITESTANDADC_ModeDV_WID ( 1) + #define DDRDATA0CH0_CR_DLLPITESTANDADC_ModeDV_MSK (0x00000008) + #define DDRDATA0CH0_CR_DLLPITESTANDADC_ModeDV_MAX (0x00000001) + #define DDRDATA0CH0_CR_DLLPITESTANDADC_ModeDV_DEF (0x00000000) + #define DDRDATA0CH0_CR_DLLPITESTANDADC_ModeADC_OFF ( 4) + #define DDRDATA0CH0_CR_DLLPITESTANDADC_ModeADC_WID ( 1) + #define DDRDATA0CH0_CR_DLLPITESTANDADC_ModeADC_MSK (0x00000010) + #define DDRDATA0CH0_CR_DLLPITESTANDADC_ModeADC_MAX (0x00000001) + #define DDRDATA0CH0_CR_DLLPITESTANDADC_ModeADC_DEF (0x00000000) + #define DDRDATA0CH0_CR_DLLPITESTANDADC_LoadCount_OFF ( 5) + #define DDRDATA0CH0_CR_DLLPITESTANDADC_LoadCount_WID (10) + #define DDRDATA0CH0_CR_DLLPITESTANDADC_LoadCount_MSK (0x00007FE0) + #define DDRDATA0CH0_CR_DLLPITESTANDADC_LoadCount_MAX (0x000003FF) + #define DDRDATA0CH0_CR_DLLPITESTANDADC_CountStatus_OFF (15) + #define DDRDATA0CH0_CR_DLLPITESTANDADC_CountStatus_WID (10) + #define DDRDATA0CH0_CR_DLLPITESTANDADC_CountStatus_MSK (0x01FF8000) + #define DDRDATA0CH0_CR_DLLPITESTANDADC_CountStatus_MAX (0x000003FF) + #define DDRDATA0CH0_CR_DLLPITESTANDADC_CountStatus_DEF (0x00000000) + #define DDRDATA0CH0_CR_DLLPITESTANDADC_Spare_OFF (25) + #define DDRDATA0CH0_CR_DLLPITESTANDADC_Spare_WID ( 7) + #define DDRDATA0CH0_CR_DLLPITESTANDADC_Spare_MSK (0xFE000000) + #define DDRDATA0CH0_CR_DLLPITESTANDADC_Spare_MAX (0x0000007F) + +#define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_REG (0x0000005C) + #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_OFF ( 0) + #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_WID ( 6) + #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MSK (0x0000003F) + #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MAX (0x0000003F) + #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_DEF (0x00000000) + #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_OFF ( 6) + #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_WID ( 6) + #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MSK (0x00000FC0) + #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MAX (0x0000003F) + #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_DEF (0x00000000) + #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_OFF (12) + #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_WID ( 5) + #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MSK (0x0001F000) + #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MAX (0x0000001F) + #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_DEF (0x00000000) + #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_OFF (17) + #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_WID ( 5) + #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MSK (0x003E0000) + #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MAX (0x0000001F) + #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_DEF (0x00000000) + #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_OFF (22) + #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_WID ( 5) + #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_MSK (0x07C00000) + #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_MAX (0x0000001F) + #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_DEF (0x00000000) + #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_OFF (27) + #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_WID ( 5) + #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MSK (0xF8000000) + #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MAX (0x0000001F) + #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_DEF (0x00000000) + +#define DDRDATA0CH0_CR_DDRCRDATACONTROL1_REG (0x00000060) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_RefPi_OFF ( 0) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_RefPi_WID ( 4) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_RefPi_MSK (0x0000000F) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_RefPi_MAX (0x0000000F) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_RefPi_DEF (0x00000000) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_DllMask_OFF ( 4) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_DllMask_WID ( 2) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_DllMask_MSK (0x00000030) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_DllMask_MAX (0x00000003) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_DllMask_DEF (0x00000000) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_DllWeakLock_OFF ( 6) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_DllWeakLock_WID ( 1) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_DllWeakLock_MSK (0x00000040) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_DllWeakLock_MAX (0x00000001) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_DllWeakLock_DEF (0x00000000) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_OFF ( 7) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_WID ( 3) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MSK (0x00000380) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MAX (0x00000007) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_DEF (0x00000000) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_OFF (10) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_WID ( 3) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_MSK (0x00001C00) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_MAX (0x00000007) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_DEF (0x00000000) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_OdtDelay_OFF (13) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_OdtDelay_WID ( 4) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_OdtDelay_MSK (0x0001E000) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_OdtDelay_MAX (0x0000000F) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_OdtDelay_DEF (0x00000000) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_OdtDuration_OFF (17) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_OdtDuration_WID ( 3) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_OdtDuration_MSK (0x000E0000) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_OdtDuration_MAX (0x00000007) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_OdtDuration_DEF (0x00000000) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_OFF (20) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_WID ( 4) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_MSK (0x00F00000) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_MAX (0x0000000F) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_DEF (0x00000000) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_OFF (24) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_WID ( 3) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_MSK (0x07000000) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_MAX (0x00000007) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_DEF (0x00000000) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_OFF (27) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_WID ( 3) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_MSK (0x38000000) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_MAX (0x00000007) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_DEF (0x00000000) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_OFF (30) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_WID ( 1) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_MSK (0x40000000) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_MAX (0x00000001) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_DEF (0x00000000) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_Rsvd1_OFF (31) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_Rsvd1_WID ( 1) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_Rsvd1_MSK (0x80000000) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_Rsvd1_MAX (0x00000001) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_Rsvd1_DEF (0x00000000) + +#define DDRDATA0CH0_CR_DDRCRDATACONTROL2_REG (0x00000064) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_OFF ( 0) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_WID ( 5) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_MSK (0x0000001F) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_MAX (0x0000001F) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_DEF (0x00000000) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_OFF ( 5) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_WID ( 1) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_MSK (0x00000020) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_MAX (0x00000001) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_DEF (0x00000000) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_ForceRxOn_OFF ( 6) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_ForceRxOn_WID ( 1) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_ForceRxOn_MSK (0x00000040) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_ForceRxOn_MAX (0x00000001) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_ForceRxOn_DEF (0x00000000) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_LeakerComp_OFF ( 7) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_LeakerComp_WID ( 2) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_LeakerComp_MSK (0x00000180) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_LeakerComp_MAX (0x00000003) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_LeakerComp_DEF (0x00000000) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_OFF ( 9) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_WID ( 4) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_MSK (0x00001E00) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_MAX (0x0000000F) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_DEF (0x00000008) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_OFF (13) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_WID ( 5) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_MSK (0x0003E000) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_MAX (0x0000001F) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_DEF (0x00000011) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_OFF (18) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_WID ( 1) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_MSK (0x00040000) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_MAX (0x00000001) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_DEF (0x00000000) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_Spare_OFF (19) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_Spare_WID (13) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_Spare_MSK (0xFFF80000) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_Spare_MAX (0x00001FFF) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_Spare_DEF (0x00000000) + +#define DDRDATA0CH0_CR_DDRCRVSSHIORVREFCONTROL_REG (0x0000006C) + #define DDRDATA0CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_OFF ( 0) + #define DDRDATA0CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_WID (24) + #define DDRDATA0CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_MSK (0x00FFFFFF) + #define DDRDATA0CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_MAX (0x00FFFFFF) + #define DDRDATA0CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_DEF (0x00000000) + #define DDRDATA0CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_OFF (24) + #define DDRDATA0CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_WID ( 8) + #define DDRDATA0CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_MSK (0xFF000000) + #define DDRDATA0CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_MAX (0x000000FF) + #define DDRDATA0CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_DEF (0x00000000) + +#define DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_REG (0x00000070) + #define DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_OFF ( 0) + #define DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_WID ( 6) + #define DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MSK (0x0000003F) + #define DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MAX (0x0000003F) + #define DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_DEF (0x00000000) + #define DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_OFF ( 6) + #define DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_WID ( 6) + #define DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MSK (0x00000FC0) + #define DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MAX (0x0000003F) + #define DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_DEF (0x00000000) + #define DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_OFF (12) + #define DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_WID ( 6) + #define DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MSK (0x0003F000) + #define DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MAX (0x0000003F) + #define DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_DEF (0x00000000) + #define DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_OFF (18) + #define DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_WID ( 6) + #define DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MSK (0x00FC0000) + #define DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MAX (0x0000003F) + #define DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_DEF (0x00000000) + #define DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_OFF (24) + #define DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_WID ( 7) + #define DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MSK (0x7F000000) + #define DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MAX (0x0000007F) + #define DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_DEF (0x00000000) + #define DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_OFF (31) + #define DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_WID ( 1) + #define DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_MSK (0x80000000) + #define DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_MAX (0x00000001) + #define DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_DEF (0x00000000) + +#define DDRDATA0CH0_CR_DDRCRDATACONTROL0_REG (0x00000074) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_OFF ( 0) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_WID ( 1) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_MSK (0x00000001) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_MAX (0x00000001) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_DEF (0x00000000) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_OFF ( 1) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_WID ( 1) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_MSK (0x00000002) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_MAX (0x00000001) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_DEF (0x00000000) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_OFF ( 2) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_WID ( 1) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_MSK (0x00000004) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_MAX (0x00000001) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_DEF (0x00000000) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_OFF ( 3) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_WID ( 1) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MSK (0x00000008) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MAX (0x00000001) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_DEF (0x00000000) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_TxOn_OFF ( 4) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_TxOn_WID ( 1) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_TxOn_MSK (0x00000010) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_TxOn_MAX (0x00000001) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_TxOn_DEF (0x00000000) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RfOn_OFF ( 5) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RfOn_WID ( 1) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RfOn_MSK (0x00000020) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RfOn_MAX (0x00000001) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RfOn_DEF (0x00000000) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RxPiOn_OFF ( 6) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RxPiOn_WID ( 1) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RxPiOn_MSK (0x00000040) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RxPiOn_MAX (0x00000001) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RxPiOn_DEF (0x00000000) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_TxPiOn_OFF ( 7) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_TxPiOn_WID ( 1) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_TxPiOn_MSK (0x00000080) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_TxPiOn_MAX (0x00000001) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_TxPiOn_DEF (0x00000000) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_OFF ( 8) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_WID ( 1) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_MSK (0x00000100) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_MAX (0x00000001) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_DEF (0x00000000) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_OFF ( 9) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_WID ( 1) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MSK (0x00000200) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MAX (0x00000001) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_DEF (0x00000000) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_TxDisable_OFF (10) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_TxDisable_WID ( 1) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_TxDisable_MSK (0x00000400) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_TxDisable_MAX (0x00000001) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_TxDisable_DEF (0x00000000) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RxDisable_OFF (11) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RxDisable_WID ( 1) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RxDisable_MSK (0x00000800) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RxDisable_MAX (0x00000001) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RxDisable_DEF (0x00000000) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_TxLong_OFF (12) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_TxLong_WID ( 1) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_TxLong_MSK (0x00001000) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_TxLong_MAX (0x00000001) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_TxLong_DEF (0x00000000) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_OFF (13) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_WID ( 2) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_MSK (0x00006000) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_MAX (0x00000003) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_DEF (0x00000000) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RxReadPointer_OFF (15) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RxReadPointer_WID ( 3) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RxReadPointer_MSK (0x00038000) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RxReadPointer_MAX (0x00000007) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RxReadPointer_DEF (0x00000000) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_OFF (18) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_WID ( 1) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_MSK (0x00040000) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_MAX (0x00000001) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_DEF (0x00000000) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_OFF (19) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_WID ( 1) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_MSK (0x00080000) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_MAX (0x00000001) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_DEF (0x00000000) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_ReadRFRd_OFF (20) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_ReadRFRd_WID ( 1) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_ReadRFRd_MSK (0x00100000) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_ReadRFRd_MAX (0x00000001) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_ReadRFRd_DEF (0x00000000) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_ReadRFWr_OFF (21) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_ReadRFWr_WID ( 1) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_ReadRFWr_MSK (0x00200000) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_ReadRFWr_MAX (0x00000001) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_ReadRFWr_DEF (0x00000000) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_ReadRFRank_OFF (22) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_ReadRFRank_WID ( 2) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_ReadRFRank_MSK (0x00C00000) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_ReadRFRank_MAX (0x00000003) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_ReadRFRank_DEF (0x00000000) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_OFF (24) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_WID ( 1) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_MSK (0x01000000) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_MAX (0x00000001) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_DEF (0x00000000) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_OdtSampOff_OFF (25) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_OdtSampOff_WID ( 1) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_OdtSampOff_MSK (0x02000000) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_OdtSampOff_MAX (0x00000001) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_OdtSampOff_DEF (0x00000000) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_OFF (26) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_WID ( 1) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_MSK (0x04000000) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_MAX (0x00000001) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_DEF (0x00000000) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_OFF (27) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_WID ( 1) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MSK (0x08000000) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MAX (0x00000001) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_DEF (0x00000000) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_OFF (28) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_WID ( 1) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_MSK (0x10000000) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_MAX (0x00000001) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_DEF (0x00000000) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_OFF (29) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_WID ( 1) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_MSK (0x20000000) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_MAX (0x00000001) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_DEF (0x00000000) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_OFF (30) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_WID ( 1) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MSK (0x40000000) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MAX (0x00000001) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_DEF (0x00000000) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_OFF (31) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_WID ( 1) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_MSK (0x80000000) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_MAX (0x00000001) + #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_DEF (0x00000000) + +#define DDRDATA0CH0_CR_DDRCRVREFADJUST1_REG (0x00000078) + #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_OFF ( 0) + #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_WID ( 7) + #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_MSK (0x0000007F) + #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_MAX (0x0000007F) + #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_DEF (0x00000000) + #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_OFF ( 7) + #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_WID ( 7) + #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_MSK (0x00003F80) + #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_MAX (0x0000007F) + #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_DEF (0x00000000) + #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_OFF (14) + #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_WID ( 7) + #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_MSK (0x001FC000) + #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_MAX (0x0000007F) + #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_DEF (0x00000000) + #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_OFF (21) + #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_WID ( 1) + #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_MSK (0x00200000) + #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_MAX (0x00000001) + #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_DEF (0x00000000) + #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_OFF (22) + #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_WID ( 1) + #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_MSK (0x00400000) + #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_MAX (0x00000001) + #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_DEF (0x00000000) + #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_OFF (23) + #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_WID ( 1) + #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_MSK (0x00800000) + #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_MAX (0x00000001) + #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_DEF (0x00000000) + #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_OFF (24) + #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_WID ( 2) + #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_MSK (0x03000000) + #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_MAX (0x00000003) + #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_DEF (0x00000000) + #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_OFF (26) + #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_WID ( 1) + #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_MSK (0x04000000) + #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_MAX (0x00000001) + #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_DEF (0x00000000) + #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_Rsvd_OFF (27) + #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_Rsvd_WID ( 2) + #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_Rsvd_MSK (0x18000000) + #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_Rsvd_MAX (0x00000003) + #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_Rsvd_DEF (0x00000000) + #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_caSlowBW_OFF (29) + #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_caSlowBW_WID ( 1) + #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_caSlowBW_MSK (0x20000000) + #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_caSlowBW_MAX (0x00000001) + #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_caSlowBW_DEF (0x00000000) + #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_OFF (30) + #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_WID ( 1) + #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_MSK (0x40000000) + #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_MAX (0x00000001) + #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_DEF (0x00000000) + #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_OFF (31) + #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_WID ( 1) + #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_MSK (0x80000000) + #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_MAX (0x00000001) + #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_DEF (0x00000000) + +#define DDRDATA0CH1_CR_RXTRAINRANK0_REG (0x00000100) + #define DDRDATA0CH1_CR_RXTRAINRANK0_RxRcvEnPi_OFF ( 0) + #define DDRDATA0CH1_CR_RXTRAINRANK0_RxRcvEnPi_WID ( 9) + #define DDRDATA0CH1_CR_RXTRAINRANK0_RxRcvEnPi_MSK (0x000001FF) + #define DDRDATA0CH1_CR_RXTRAINRANK0_RxRcvEnPi_MAX (0x000001FF) + #define DDRDATA0CH1_CR_RXTRAINRANK0_RxDqsPPi_OFF ( 9) + #define DDRDATA0CH1_CR_RXTRAINRANK0_RxDqsPPi_WID ( 6) + #define DDRDATA0CH1_CR_RXTRAINRANK0_RxDqsPPi_MSK (0x00007E00) + #define DDRDATA0CH1_CR_RXTRAINRANK0_RxDqsPPi_MAX (0x0000003F) + #define DDRDATA0CH1_CR_RXTRAINRANK0_RxEq_OFF (15) + #define DDRDATA0CH1_CR_RXTRAINRANK0_RxEq_WID ( 5) + #define DDRDATA0CH1_CR_RXTRAINRANK0_RxEq_MSK (0x000F8000) + #define DDRDATA0CH1_CR_RXTRAINRANK0_RxEq_MAX (0x0000001F) + #define DDRDATA0CH1_CR_RXTRAINRANK0_RxDqsNPi_OFF (20) + #define DDRDATA0CH1_CR_RXTRAINRANK0_RxDqsNPi_WID ( 6) + #define DDRDATA0CH1_CR_RXTRAINRANK0_RxDqsNPi_MSK (0x03F00000) + #define DDRDATA0CH1_CR_RXTRAINRANK0_RxDqsNPi_MAX (0x0000003F) + #define DDRDATA0CH1_CR_RXTRAINRANK0_RxVref_OFF (26) + #define DDRDATA0CH1_CR_RXTRAINRANK0_RxVref_WID ( 6) + #define DDRDATA0CH1_CR_RXTRAINRANK0_RxVref_MSK (0xFC000000) + #define DDRDATA0CH1_CR_RXTRAINRANK0_RxVref_MAX (0x0000003F) + +#define DDRDATA0CH1_CR_RXTRAINRANK1_REG (0x00000104) + #define DDRDATA0CH1_CR_RXTRAINRANK1_RxRcvEnPi_OFF ( 0) + #define DDRDATA0CH1_CR_RXTRAINRANK1_RxRcvEnPi_WID ( 9) + #define DDRDATA0CH1_CR_RXTRAINRANK1_RxRcvEnPi_MSK (0x000001FF) + #define DDRDATA0CH1_CR_RXTRAINRANK1_RxRcvEnPi_MAX (0x000001FF) + #define DDRDATA0CH1_CR_RXTRAINRANK1_RxDqsPPi_OFF ( 9) + #define DDRDATA0CH1_CR_RXTRAINRANK1_RxDqsPPi_WID ( 6) + #define DDRDATA0CH1_CR_RXTRAINRANK1_RxDqsPPi_MSK (0x00007E00) + #define DDRDATA0CH1_CR_RXTRAINRANK1_RxDqsPPi_MAX (0x0000003F) + #define DDRDATA0CH1_CR_RXTRAINRANK1_RxEq_OFF (15) + #define DDRDATA0CH1_CR_RXTRAINRANK1_RxEq_WID ( 5) + #define DDRDATA0CH1_CR_RXTRAINRANK1_RxEq_MSK (0x000F8000) + #define DDRDATA0CH1_CR_RXTRAINRANK1_RxEq_MAX (0x0000001F) + #define DDRDATA0CH1_CR_RXTRAINRANK1_RxDqsNPi_OFF (20) + #define DDRDATA0CH1_CR_RXTRAINRANK1_RxDqsNPi_WID ( 6) + #define DDRDATA0CH1_CR_RXTRAINRANK1_RxDqsNPi_MSK (0x03F00000) + #define DDRDATA0CH1_CR_RXTRAINRANK1_RxDqsNPi_MAX (0x0000003F) + #define DDRDATA0CH1_CR_RXTRAINRANK1_RxVref_OFF (26) + #define DDRDATA0CH1_CR_RXTRAINRANK1_RxVref_WID ( 6) + #define DDRDATA0CH1_CR_RXTRAINRANK1_RxVref_MSK (0xFC000000) + #define DDRDATA0CH1_CR_RXTRAINRANK1_RxVref_MAX (0x0000003F) + +#define DDRDATA0CH1_CR_RXTRAINRANK2_REG (0x00000108) + #define DDRDATA0CH1_CR_RXTRAINRANK2_RxRcvEnPi_OFF ( 0) + #define DDRDATA0CH1_CR_RXTRAINRANK2_RxRcvEnPi_WID ( 9) + #define DDRDATA0CH1_CR_RXTRAINRANK2_RxRcvEnPi_MSK (0x000001FF) + #define DDRDATA0CH1_CR_RXTRAINRANK2_RxRcvEnPi_MAX (0x000001FF) + #define DDRDATA0CH1_CR_RXTRAINRANK2_RxDqsPPi_OFF ( 9) + #define DDRDATA0CH1_CR_RXTRAINRANK2_RxDqsPPi_WID ( 6) + #define DDRDATA0CH1_CR_RXTRAINRANK2_RxDqsPPi_MSK (0x00007E00) + #define DDRDATA0CH1_CR_RXTRAINRANK2_RxDqsPPi_MAX (0x0000003F) + #define DDRDATA0CH1_CR_RXTRAINRANK2_RxEq_OFF (15) + #define DDRDATA0CH1_CR_RXTRAINRANK2_RxEq_WID ( 5) + #define DDRDATA0CH1_CR_RXTRAINRANK2_RxEq_MSK (0x000F8000) + #define DDRDATA0CH1_CR_RXTRAINRANK2_RxEq_MAX (0x0000001F) + #define DDRDATA0CH1_CR_RXTRAINRANK2_RxDqsNPi_OFF (20) + #define DDRDATA0CH1_CR_RXTRAINRANK2_RxDqsNPi_WID ( 6) + #define DDRDATA0CH1_CR_RXTRAINRANK2_RxDqsNPi_MSK (0x03F00000) + #define DDRDATA0CH1_CR_RXTRAINRANK2_RxDqsNPi_MAX (0x0000003F) + #define DDRDATA0CH1_CR_RXTRAINRANK2_RxVref_OFF (26) + #define DDRDATA0CH1_CR_RXTRAINRANK2_RxVref_WID ( 6) + #define DDRDATA0CH1_CR_RXTRAINRANK2_RxVref_MSK (0xFC000000) + #define DDRDATA0CH1_CR_RXTRAINRANK2_RxVref_MAX (0x0000003F) + +#define DDRDATA0CH1_CR_RXTRAINRANK3_REG (0x0000010C) + #define DDRDATA0CH1_CR_RXTRAINRANK3_RxRcvEnPi_OFF ( 0) + #define DDRDATA0CH1_CR_RXTRAINRANK3_RxRcvEnPi_WID ( 9) + #define DDRDATA0CH1_CR_RXTRAINRANK3_RxRcvEnPi_MSK (0x000001FF) + #define DDRDATA0CH1_CR_RXTRAINRANK3_RxRcvEnPi_MAX (0x000001FF) + #define DDRDATA0CH1_CR_RXTRAINRANK3_RxDqsPPi_OFF ( 9) + #define DDRDATA0CH1_CR_RXTRAINRANK3_RxDqsPPi_WID ( 6) + #define DDRDATA0CH1_CR_RXTRAINRANK3_RxDqsPPi_MSK (0x00007E00) + #define DDRDATA0CH1_CR_RXTRAINRANK3_RxDqsPPi_MAX (0x0000003F) + #define DDRDATA0CH1_CR_RXTRAINRANK3_RxEq_OFF (15) + #define DDRDATA0CH1_CR_RXTRAINRANK3_RxEq_WID ( 5) + #define DDRDATA0CH1_CR_RXTRAINRANK3_RxEq_MSK (0x000F8000) + #define DDRDATA0CH1_CR_RXTRAINRANK3_RxEq_MAX (0x0000001F) + #define DDRDATA0CH1_CR_RXTRAINRANK3_RxDqsNPi_OFF (20) + #define DDRDATA0CH1_CR_RXTRAINRANK3_RxDqsNPi_WID ( 6) + #define DDRDATA0CH1_CR_RXTRAINRANK3_RxDqsNPi_MSK (0x03F00000) + #define DDRDATA0CH1_CR_RXTRAINRANK3_RxDqsNPi_MAX (0x0000003F) + #define DDRDATA0CH1_CR_RXTRAINRANK3_RxVref_OFF (26) + #define DDRDATA0CH1_CR_RXTRAINRANK3_RxVref_WID ( 6) + #define DDRDATA0CH1_CR_RXTRAINRANK3_RxVref_MSK (0xFC000000) + #define DDRDATA0CH1_CR_RXTRAINRANK3_RxVref_MAX (0x0000003F) + +#define DDRDATA0CH1_CR_RXPERBITRANK0_REG (0x00000110) + #define DDRDATA0CH1_CR_RXPERBITRANK0_Lane0_OFF ( 0) + #define DDRDATA0CH1_CR_RXPERBITRANK0_Lane0_WID ( 4) + #define DDRDATA0CH1_CR_RXPERBITRANK0_Lane0_MSK (0x0000000F) + #define DDRDATA0CH1_CR_RXPERBITRANK0_Lane0_MAX (0x0000000F) + #define DDRDATA0CH1_CR_RXPERBITRANK0_Lane1_OFF ( 4) + #define DDRDATA0CH1_CR_RXPERBITRANK0_Lane1_WID ( 4) + #define DDRDATA0CH1_CR_RXPERBITRANK0_Lane1_MSK (0x000000F0) + #define DDRDATA0CH1_CR_RXPERBITRANK0_Lane1_MAX (0x0000000F) + #define DDRDATA0CH1_CR_RXPERBITRANK0_Lane2_OFF ( 8) + #define DDRDATA0CH1_CR_RXPERBITRANK0_Lane2_WID ( 4) + #define DDRDATA0CH1_CR_RXPERBITRANK0_Lane2_MSK (0x00000F00) + #define DDRDATA0CH1_CR_RXPERBITRANK0_Lane2_MAX (0x0000000F) + #define DDRDATA0CH1_CR_RXPERBITRANK0_Lane3_OFF (12) + #define DDRDATA0CH1_CR_RXPERBITRANK0_Lane3_WID ( 4) + #define DDRDATA0CH1_CR_RXPERBITRANK0_Lane3_MSK (0x0000F000) + #define DDRDATA0CH1_CR_RXPERBITRANK0_Lane3_MAX (0x0000000F) + #define DDRDATA0CH1_CR_RXPERBITRANK0_Lane4_OFF (16) + #define DDRDATA0CH1_CR_RXPERBITRANK0_Lane4_WID ( 4) + #define DDRDATA0CH1_CR_RXPERBITRANK0_Lane4_MSK (0x000F0000) + #define DDRDATA0CH1_CR_RXPERBITRANK0_Lane4_MAX (0x0000000F) + #define DDRDATA0CH1_CR_RXPERBITRANK0_Lane5_OFF (20) + #define DDRDATA0CH1_CR_RXPERBITRANK0_Lane5_WID ( 4) + #define DDRDATA0CH1_CR_RXPERBITRANK0_Lane5_MSK (0x00F00000) + #define DDRDATA0CH1_CR_RXPERBITRANK0_Lane5_MAX (0x0000000F) + #define DDRDATA0CH1_CR_RXPERBITRANK0_Lane6_OFF (24) + #define DDRDATA0CH1_CR_RXPERBITRANK0_Lane6_WID ( 4) + #define DDRDATA0CH1_CR_RXPERBITRANK0_Lane6_MSK (0x0F000000) + #define DDRDATA0CH1_CR_RXPERBITRANK0_Lane6_MAX (0x0000000F) + #define DDRDATA0CH1_CR_RXPERBITRANK0_Lane7_OFF (28) + #define DDRDATA0CH1_CR_RXPERBITRANK0_Lane7_WID ( 4) + #define DDRDATA0CH1_CR_RXPERBITRANK0_Lane7_MSK (0xF0000000) + #define DDRDATA0CH1_CR_RXPERBITRANK0_Lane7_MAX (0x0000000F) + +#define DDRDATA0CH1_CR_RXPERBITRANK1_REG (0x00000114) + #define DDRDATA0CH1_CR_RXPERBITRANK1_Lane0_OFF ( 0) + #define DDRDATA0CH1_CR_RXPERBITRANK1_Lane0_WID ( 4) + #define DDRDATA0CH1_CR_RXPERBITRANK1_Lane0_MSK (0x0000000F) + #define DDRDATA0CH1_CR_RXPERBITRANK1_Lane0_MAX (0x0000000F) + #define DDRDATA0CH1_CR_RXPERBITRANK1_Lane1_OFF ( 4) + #define DDRDATA0CH1_CR_RXPERBITRANK1_Lane1_WID ( 4) + #define DDRDATA0CH1_CR_RXPERBITRANK1_Lane1_MSK (0x000000F0) + #define DDRDATA0CH1_CR_RXPERBITRANK1_Lane1_MAX (0x0000000F) + #define DDRDATA0CH1_CR_RXPERBITRANK1_Lane2_OFF ( 8) + #define DDRDATA0CH1_CR_RXPERBITRANK1_Lane2_WID ( 4) + #define DDRDATA0CH1_CR_RXPERBITRANK1_Lane2_MSK (0x00000F00) + #define DDRDATA0CH1_CR_RXPERBITRANK1_Lane2_MAX (0x0000000F) + #define DDRDATA0CH1_CR_RXPERBITRANK1_Lane3_OFF (12) + #define DDRDATA0CH1_CR_RXPERBITRANK1_Lane3_WID ( 4) + #define DDRDATA0CH1_CR_RXPERBITRANK1_Lane3_MSK (0x0000F000) + #define DDRDATA0CH1_CR_RXPERBITRANK1_Lane3_MAX (0x0000000F) + #define DDRDATA0CH1_CR_RXPERBITRANK1_Lane4_OFF (16) + #define DDRDATA0CH1_CR_RXPERBITRANK1_Lane4_WID ( 4) + #define DDRDATA0CH1_CR_RXPERBITRANK1_Lane4_MSK (0x000F0000) + #define DDRDATA0CH1_CR_RXPERBITRANK1_Lane4_MAX (0x0000000F) + #define DDRDATA0CH1_CR_RXPERBITRANK1_Lane5_OFF (20) + #define DDRDATA0CH1_CR_RXPERBITRANK1_Lane5_WID ( 4) + #define DDRDATA0CH1_CR_RXPERBITRANK1_Lane5_MSK (0x00F00000) + #define DDRDATA0CH1_CR_RXPERBITRANK1_Lane5_MAX (0x0000000F) + #define DDRDATA0CH1_CR_RXPERBITRANK1_Lane6_OFF (24) + #define DDRDATA0CH1_CR_RXPERBITRANK1_Lane6_WID ( 4) + #define DDRDATA0CH1_CR_RXPERBITRANK1_Lane6_MSK (0x0F000000) + #define DDRDATA0CH1_CR_RXPERBITRANK1_Lane6_MAX (0x0000000F) + #define DDRDATA0CH1_CR_RXPERBITRANK1_Lane7_OFF (28) + #define DDRDATA0CH1_CR_RXPERBITRANK1_Lane7_WID ( 4) + #define DDRDATA0CH1_CR_RXPERBITRANK1_Lane7_MSK (0xF0000000) + #define DDRDATA0CH1_CR_RXPERBITRANK1_Lane7_MAX (0x0000000F) + +#define DDRDATA0CH1_CR_RXPERBITRANK2_REG (0x00000118) + #define DDRDATA0CH1_CR_RXPERBITRANK2_Lane0_OFF ( 0) + #define DDRDATA0CH1_CR_RXPERBITRANK2_Lane0_WID ( 4) + #define DDRDATA0CH1_CR_RXPERBITRANK2_Lane0_MSK (0x0000000F) + #define DDRDATA0CH1_CR_RXPERBITRANK2_Lane0_MAX (0x0000000F) + #define DDRDATA0CH1_CR_RXPERBITRANK2_Lane1_OFF ( 4) + #define DDRDATA0CH1_CR_RXPERBITRANK2_Lane1_WID ( 4) + #define DDRDATA0CH1_CR_RXPERBITRANK2_Lane1_MSK (0x000000F0) + #define DDRDATA0CH1_CR_RXPERBITRANK2_Lane1_MAX (0x0000000F) + #define DDRDATA0CH1_CR_RXPERBITRANK2_Lane2_OFF ( 8) + #define DDRDATA0CH1_CR_RXPERBITRANK2_Lane2_WID ( 4) + #define DDRDATA0CH1_CR_RXPERBITRANK2_Lane2_MSK (0x00000F00) + #define DDRDATA0CH1_CR_RXPERBITRANK2_Lane2_MAX (0x0000000F) + #define DDRDATA0CH1_CR_RXPERBITRANK2_Lane3_OFF (12) + #define DDRDATA0CH1_CR_RXPERBITRANK2_Lane3_WID ( 4) + #define DDRDATA0CH1_CR_RXPERBITRANK2_Lane3_MSK (0x0000F000) + #define DDRDATA0CH1_CR_RXPERBITRANK2_Lane3_MAX (0x0000000F) + #define DDRDATA0CH1_CR_RXPERBITRANK2_Lane4_OFF (16) + #define DDRDATA0CH1_CR_RXPERBITRANK2_Lane4_WID ( 4) + #define DDRDATA0CH1_CR_RXPERBITRANK2_Lane4_MSK (0x000F0000) + #define DDRDATA0CH1_CR_RXPERBITRANK2_Lane4_MAX (0x0000000F) + #define DDRDATA0CH1_CR_RXPERBITRANK2_Lane5_OFF (20) + #define DDRDATA0CH1_CR_RXPERBITRANK2_Lane5_WID ( 4) + #define DDRDATA0CH1_CR_RXPERBITRANK2_Lane5_MSK (0x00F00000) + #define DDRDATA0CH1_CR_RXPERBITRANK2_Lane5_MAX (0x0000000F) + #define DDRDATA0CH1_CR_RXPERBITRANK2_Lane6_OFF (24) + #define DDRDATA0CH1_CR_RXPERBITRANK2_Lane6_WID ( 4) + #define DDRDATA0CH1_CR_RXPERBITRANK2_Lane6_MSK (0x0F000000) + #define DDRDATA0CH1_CR_RXPERBITRANK2_Lane6_MAX (0x0000000F) + #define DDRDATA0CH1_CR_RXPERBITRANK2_Lane7_OFF (28) + #define DDRDATA0CH1_CR_RXPERBITRANK2_Lane7_WID ( 4) + #define DDRDATA0CH1_CR_RXPERBITRANK2_Lane7_MSK (0xF0000000) + #define DDRDATA0CH1_CR_RXPERBITRANK2_Lane7_MAX (0x0000000F) + +#define DDRDATA0CH1_CR_RXPERBITRANK3_REG (0x0000011C) + #define DDRDATA0CH1_CR_RXPERBITRANK3_Lane0_OFF ( 0) + #define DDRDATA0CH1_CR_RXPERBITRANK3_Lane0_WID ( 4) + #define DDRDATA0CH1_CR_RXPERBITRANK3_Lane0_MSK (0x0000000F) + #define DDRDATA0CH1_CR_RXPERBITRANK3_Lane0_MAX (0x0000000F) + #define DDRDATA0CH1_CR_RXPERBITRANK3_Lane1_OFF ( 4) + #define DDRDATA0CH1_CR_RXPERBITRANK3_Lane1_WID ( 4) + #define DDRDATA0CH1_CR_RXPERBITRANK3_Lane1_MSK (0x000000F0) + #define DDRDATA0CH1_CR_RXPERBITRANK3_Lane1_MAX (0x0000000F) + #define DDRDATA0CH1_CR_RXPERBITRANK3_Lane2_OFF ( 8) + #define DDRDATA0CH1_CR_RXPERBITRANK3_Lane2_WID ( 4) + #define DDRDATA0CH1_CR_RXPERBITRANK3_Lane2_MSK (0x00000F00) + #define DDRDATA0CH1_CR_RXPERBITRANK3_Lane2_MAX (0x0000000F) + #define DDRDATA0CH1_CR_RXPERBITRANK3_Lane3_OFF (12) + #define DDRDATA0CH1_CR_RXPERBITRANK3_Lane3_WID ( 4) + #define DDRDATA0CH1_CR_RXPERBITRANK3_Lane3_MSK (0x0000F000) + #define DDRDATA0CH1_CR_RXPERBITRANK3_Lane3_MAX (0x0000000F) + #define DDRDATA0CH1_CR_RXPERBITRANK3_Lane4_OFF (16) + #define DDRDATA0CH1_CR_RXPERBITRANK3_Lane4_WID ( 4) + #define DDRDATA0CH1_CR_RXPERBITRANK3_Lane4_MSK (0x000F0000) + #define DDRDATA0CH1_CR_RXPERBITRANK3_Lane4_MAX (0x0000000F) + #define DDRDATA0CH1_CR_RXPERBITRANK3_Lane5_OFF (20) + #define DDRDATA0CH1_CR_RXPERBITRANK3_Lane5_WID ( 4) + #define DDRDATA0CH1_CR_RXPERBITRANK3_Lane5_MSK (0x00F00000) + #define DDRDATA0CH1_CR_RXPERBITRANK3_Lane5_MAX (0x0000000F) + #define DDRDATA0CH1_CR_RXPERBITRANK3_Lane6_OFF (24) + #define DDRDATA0CH1_CR_RXPERBITRANK3_Lane6_WID ( 4) + #define DDRDATA0CH1_CR_RXPERBITRANK3_Lane6_MSK (0x0F000000) + #define DDRDATA0CH1_CR_RXPERBITRANK3_Lane6_MAX (0x0000000F) + #define DDRDATA0CH1_CR_RXPERBITRANK3_Lane7_OFF (28) + #define DDRDATA0CH1_CR_RXPERBITRANK3_Lane7_WID ( 4) + #define DDRDATA0CH1_CR_RXPERBITRANK3_Lane7_MSK (0xF0000000) + #define DDRDATA0CH1_CR_RXPERBITRANK3_Lane7_MAX (0x0000000F) + +#define DDRDATA0CH1_CR_TXTRAINRANK0_REG (0x00000120) + #define DDRDATA0CH1_CR_TXTRAINRANK0_TxDqDelay_OFF ( 0) + #define DDRDATA0CH1_CR_TXTRAINRANK0_TxDqDelay_WID ( 9) + #define DDRDATA0CH1_CR_TXTRAINRANK0_TxDqDelay_MSK (0x000001FF) + #define DDRDATA0CH1_CR_TXTRAINRANK0_TxDqDelay_MAX (0x000001FF) + #define DDRDATA0CH1_CR_TXTRAINRANK0_TxDqsDelay_OFF ( 9) + #define DDRDATA0CH1_CR_TXTRAINRANK0_TxDqsDelay_WID ( 9) + #define DDRDATA0CH1_CR_TXTRAINRANK0_TxDqsDelay_MSK (0x0003FE00) + #define DDRDATA0CH1_CR_TXTRAINRANK0_TxDqsDelay_MAX (0x000001FF) + #define DDRDATA0CH1_CR_TXTRAINRANK0_Spare0_OFF (18) + #define DDRDATA0CH1_CR_TXTRAINRANK0_Spare0_WID ( 2) + #define DDRDATA0CH1_CR_TXTRAINRANK0_Spare0_MSK (0x000C0000) + #define DDRDATA0CH1_CR_TXTRAINRANK0_Spare0_MAX (0x00000003) + #define DDRDATA0CH1_CR_TXTRAINRANK0_TxEqualization_OFF (20) + #define DDRDATA0CH1_CR_TXTRAINRANK0_TxEqualization_WID ( 6) + #define DDRDATA0CH1_CR_TXTRAINRANK0_TxEqualization_MSK (0x03F00000) + #define DDRDATA0CH1_CR_TXTRAINRANK0_TxEqualization_MAX (0x0000003F) + #define DDRDATA0CH1_CR_TXTRAINRANK0_Spare1_OFF (26) + #define DDRDATA0CH1_CR_TXTRAINRANK0_Spare1_WID ( 6) + #define DDRDATA0CH1_CR_TXTRAINRANK0_Spare1_MSK (0xFC000000) + #define DDRDATA0CH1_CR_TXTRAINRANK0_Spare1_MAX (0x0000003F) + +#define DDRDATA0CH1_CR_TXTRAINRANK1_REG (0x00000124) + #define DDRDATA0CH1_CR_TXTRAINRANK1_TxDqDelay_OFF ( 0) + #define DDRDATA0CH1_CR_TXTRAINRANK1_TxDqDelay_WID ( 9) + #define DDRDATA0CH1_CR_TXTRAINRANK1_TxDqDelay_MSK (0x000001FF) + #define DDRDATA0CH1_CR_TXTRAINRANK1_TxDqDelay_MAX (0x000001FF) + #define DDRDATA0CH1_CR_TXTRAINRANK1_TxDqsDelay_OFF ( 9) + #define DDRDATA0CH1_CR_TXTRAINRANK1_TxDqsDelay_WID ( 9) + #define DDRDATA0CH1_CR_TXTRAINRANK1_TxDqsDelay_MSK (0x0003FE00) + #define DDRDATA0CH1_CR_TXTRAINRANK1_TxDqsDelay_MAX (0x000001FF) + #define DDRDATA0CH1_CR_TXTRAINRANK1_Spare0_OFF (18) + #define DDRDATA0CH1_CR_TXTRAINRANK1_Spare0_WID ( 2) + #define DDRDATA0CH1_CR_TXTRAINRANK1_Spare0_MSK (0x000C0000) + #define DDRDATA0CH1_CR_TXTRAINRANK1_Spare0_MAX (0x00000003) + #define DDRDATA0CH1_CR_TXTRAINRANK1_TxEqualization_OFF (20) + #define DDRDATA0CH1_CR_TXTRAINRANK1_TxEqualization_WID ( 6) + #define DDRDATA0CH1_CR_TXTRAINRANK1_TxEqualization_MSK (0x03F00000) + #define DDRDATA0CH1_CR_TXTRAINRANK1_TxEqualization_MAX (0x0000003F) + #define DDRDATA0CH1_CR_TXTRAINRANK1_Spare1_OFF (26) + #define DDRDATA0CH1_CR_TXTRAINRANK1_Spare1_WID ( 6) + #define DDRDATA0CH1_CR_TXTRAINRANK1_Spare1_MSK (0xFC000000) + #define DDRDATA0CH1_CR_TXTRAINRANK1_Spare1_MAX (0x0000003F) + +#define DDRDATA0CH1_CR_TXTRAINRANK2_REG (0x00000128) + #define DDRDATA0CH1_CR_TXTRAINRANK2_TxDqDelay_OFF ( 0) + #define DDRDATA0CH1_CR_TXTRAINRANK2_TxDqDelay_WID ( 9) + #define DDRDATA0CH1_CR_TXTRAINRANK2_TxDqDelay_MSK (0x000001FF) + #define DDRDATA0CH1_CR_TXTRAINRANK2_TxDqDelay_MAX (0x000001FF) + #define DDRDATA0CH1_CR_TXTRAINRANK2_TxDqsDelay_OFF ( 9) + #define DDRDATA0CH1_CR_TXTRAINRANK2_TxDqsDelay_WID ( 9) + #define DDRDATA0CH1_CR_TXTRAINRANK2_TxDqsDelay_MSK (0x0003FE00) + #define DDRDATA0CH1_CR_TXTRAINRANK2_TxDqsDelay_MAX (0x000001FF) + #define DDRDATA0CH1_CR_TXTRAINRANK2_Spare0_OFF (18) + #define DDRDATA0CH1_CR_TXTRAINRANK2_Spare0_WID ( 2) + #define DDRDATA0CH1_CR_TXTRAINRANK2_Spare0_MSK (0x000C0000) + #define DDRDATA0CH1_CR_TXTRAINRANK2_Spare0_MAX (0x00000003) + #define DDRDATA0CH1_CR_TXTRAINRANK2_TxEqualization_OFF (20) + #define DDRDATA0CH1_CR_TXTRAINRANK2_TxEqualization_WID ( 6) + #define DDRDATA0CH1_CR_TXTRAINRANK2_TxEqualization_MSK (0x03F00000) + #define DDRDATA0CH1_CR_TXTRAINRANK2_TxEqualization_MAX (0x0000003F) + #define DDRDATA0CH1_CR_TXTRAINRANK2_Spare1_OFF (26) + #define DDRDATA0CH1_CR_TXTRAINRANK2_Spare1_WID ( 6) + #define DDRDATA0CH1_CR_TXTRAINRANK2_Spare1_MSK (0xFC000000) + #define DDRDATA0CH1_CR_TXTRAINRANK2_Spare1_MAX (0x0000003F) + +#define DDRDATA0CH1_CR_TXTRAINRANK3_REG (0x0000012C) + #define DDRDATA0CH1_CR_TXTRAINRANK3_TxDqDelay_OFF ( 0) + #define DDRDATA0CH1_CR_TXTRAINRANK3_TxDqDelay_WID ( 9) + #define DDRDATA0CH1_CR_TXTRAINRANK3_TxDqDelay_MSK (0x000001FF) + #define DDRDATA0CH1_CR_TXTRAINRANK3_TxDqDelay_MAX (0x000001FF) + #define DDRDATA0CH1_CR_TXTRAINRANK3_TxDqsDelay_OFF ( 9) + #define DDRDATA0CH1_CR_TXTRAINRANK3_TxDqsDelay_WID ( 9) + #define DDRDATA0CH1_CR_TXTRAINRANK3_TxDqsDelay_MSK (0x0003FE00) + #define DDRDATA0CH1_CR_TXTRAINRANK3_TxDqsDelay_MAX (0x000001FF) + #define DDRDATA0CH1_CR_TXTRAINRANK3_Spare0_OFF (18) + #define DDRDATA0CH1_CR_TXTRAINRANK3_Spare0_WID ( 2) + #define DDRDATA0CH1_CR_TXTRAINRANK3_Spare0_MSK (0x000C0000) + #define DDRDATA0CH1_CR_TXTRAINRANK3_Spare0_MAX (0x00000003) + #define DDRDATA0CH1_CR_TXTRAINRANK3_TxEqualization_OFF (20) + #define DDRDATA0CH1_CR_TXTRAINRANK3_TxEqualization_WID ( 6) + #define DDRDATA0CH1_CR_TXTRAINRANK3_TxEqualization_MSK (0x03F00000) + #define DDRDATA0CH1_CR_TXTRAINRANK3_TxEqualization_MAX (0x0000003F) + #define DDRDATA0CH1_CR_TXTRAINRANK3_Spare1_OFF (26) + #define DDRDATA0CH1_CR_TXTRAINRANK3_Spare1_WID ( 6) + #define DDRDATA0CH1_CR_TXTRAINRANK3_Spare1_MSK (0xFC000000) + #define DDRDATA0CH1_CR_TXTRAINRANK3_Spare1_MAX (0x0000003F) + +#define DDRDATA0CH1_CR_TXPERBITRANK0_REG (0x00000130) + #define DDRDATA0CH1_CR_TXPERBITRANK0_Lane0_OFF ( 0) + #define DDRDATA0CH1_CR_TXPERBITRANK0_Lane0_WID ( 4) + #define DDRDATA0CH1_CR_TXPERBITRANK0_Lane0_MSK (0x0000000F) + #define DDRDATA0CH1_CR_TXPERBITRANK0_Lane0_MAX (0x0000000F) + #define DDRDATA0CH1_CR_TXPERBITRANK0_Lane1_OFF ( 4) + #define DDRDATA0CH1_CR_TXPERBITRANK0_Lane1_WID ( 4) + #define DDRDATA0CH1_CR_TXPERBITRANK0_Lane1_MSK (0x000000F0) + #define DDRDATA0CH1_CR_TXPERBITRANK0_Lane1_MAX (0x0000000F) + #define DDRDATA0CH1_CR_TXPERBITRANK0_Lane2_OFF ( 8) + #define DDRDATA0CH1_CR_TXPERBITRANK0_Lane2_WID ( 4) + #define DDRDATA0CH1_CR_TXPERBITRANK0_Lane2_MSK (0x00000F00) + #define DDRDATA0CH1_CR_TXPERBITRANK0_Lane2_MAX (0x0000000F) + #define DDRDATA0CH1_CR_TXPERBITRANK0_Lane3_OFF (12) + #define DDRDATA0CH1_CR_TXPERBITRANK0_Lane3_WID ( 4) + #define DDRDATA0CH1_CR_TXPERBITRANK0_Lane3_MSK (0x0000F000) + #define DDRDATA0CH1_CR_TXPERBITRANK0_Lane3_MAX (0x0000000F) + #define DDRDATA0CH1_CR_TXPERBITRANK0_Lane4_OFF (16) + #define DDRDATA0CH1_CR_TXPERBITRANK0_Lane4_WID ( 4) + #define DDRDATA0CH1_CR_TXPERBITRANK0_Lane4_MSK (0x000F0000) + #define DDRDATA0CH1_CR_TXPERBITRANK0_Lane4_MAX (0x0000000F) + #define DDRDATA0CH1_CR_TXPERBITRANK0_Lane5_OFF (20) + #define DDRDATA0CH1_CR_TXPERBITRANK0_Lane5_WID ( 4) + #define DDRDATA0CH1_CR_TXPERBITRANK0_Lane5_MSK (0x00F00000) + #define DDRDATA0CH1_CR_TXPERBITRANK0_Lane5_MAX (0x0000000F) + #define DDRDATA0CH1_CR_TXPERBITRANK0_Lane6_OFF (24) + #define DDRDATA0CH1_CR_TXPERBITRANK0_Lane6_WID ( 4) + #define DDRDATA0CH1_CR_TXPERBITRANK0_Lane6_MSK (0x0F000000) + #define DDRDATA0CH1_CR_TXPERBITRANK0_Lane6_MAX (0x0000000F) + #define DDRDATA0CH1_CR_TXPERBITRANK0_Lane7_OFF (28) + #define DDRDATA0CH1_CR_TXPERBITRANK0_Lane7_WID ( 4) + #define DDRDATA0CH1_CR_TXPERBITRANK0_Lane7_MSK (0xF0000000) + #define DDRDATA0CH1_CR_TXPERBITRANK0_Lane7_MAX (0x0000000F) + +#define DDRDATA0CH1_CR_TXPERBITRANK1_REG (0x00000134) + #define DDRDATA0CH1_CR_TXPERBITRANK1_Lane0_OFF ( 0) + #define DDRDATA0CH1_CR_TXPERBITRANK1_Lane0_WID ( 4) + #define DDRDATA0CH1_CR_TXPERBITRANK1_Lane0_MSK (0x0000000F) + #define DDRDATA0CH1_CR_TXPERBITRANK1_Lane0_MAX (0x0000000F) + #define DDRDATA0CH1_CR_TXPERBITRANK1_Lane1_OFF ( 4) + #define DDRDATA0CH1_CR_TXPERBITRANK1_Lane1_WID ( 4) + #define DDRDATA0CH1_CR_TXPERBITRANK1_Lane1_MSK (0x000000F0) + #define DDRDATA0CH1_CR_TXPERBITRANK1_Lane1_MAX (0x0000000F) + #define DDRDATA0CH1_CR_TXPERBITRANK1_Lane2_OFF ( 8) + #define DDRDATA0CH1_CR_TXPERBITRANK1_Lane2_WID ( 4) + #define DDRDATA0CH1_CR_TXPERBITRANK1_Lane2_MSK (0x00000F00) + #define DDRDATA0CH1_CR_TXPERBITRANK1_Lane2_MAX (0x0000000F) + #define DDRDATA0CH1_CR_TXPERBITRANK1_Lane3_OFF (12) + #define DDRDATA0CH1_CR_TXPERBITRANK1_Lane3_WID ( 4) + #define DDRDATA0CH1_CR_TXPERBITRANK1_Lane3_MSK (0x0000F000) + #define DDRDATA0CH1_CR_TXPERBITRANK1_Lane3_MAX (0x0000000F) + #define DDRDATA0CH1_CR_TXPERBITRANK1_Lane4_OFF (16) + #define DDRDATA0CH1_CR_TXPERBITRANK1_Lane4_WID ( 4) + #define DDRDATA0CH1_CR_TXPERBITRANK1_Lane4_MSK (0x000F0000) + #define DDRDATA0CH1_CR_TXPERBITRANK1_Lane4_MAX (0x0000000F) + #define DDRDATA0CH1_CR_TXPERBITRANK1_Lane5_OFF (20) + #define DDRDATA0CH1_CR_TXPERBITRANK1_Lane5_WID ( 4) + #define DDRDATA0CH1_CR_TXPERBITRANK1_Lane5_MSK (0x00F00000) + #define DDRDATA0CH1_CR_TXPERBITRANK1_Lane5_MAX (0x0000000F) + #define DDRDATA0CH1_CR_TXPERBITRANK1_Lane6_OFF (24) + #define DDRDATA0CH1_CR_TXPERBITRANK1_Lane6_WID ( 4) + #define DDRDATA0CH1_CR_TXPERBITRANK1_Lane6_MSK (0x0F000000) + #define DDRDATA0CH1_CR_TXPERBITRANK1_Lane6_MAX (0x0000000F) + #define DDRDATA0CH1_CR_TXPERBITRANK1_Lane7_OFF (28) + #define DDRDATA0CH1_CR_TXPERBITRANK1_Lane7_WID ( 4) + #define DDRDATA0CH1_CR_TXPERBITRANK1_Lane7_MSK (0xF0000000) + #define DDRDATA0CH1_CR_TXPERBITRANK1_Lane7_MAX (0x0000000F) + +#define DDRDATA0CH1_CR_TXPERBITRANK2_REG (0x00000138) + #define DDRDATA0CH1_CR_TXPERBITRANK2_Lane0_OFF ( 0) + #define DDRDATA0CH1_CR_TXPERBITRANK2_Lane0_WID ( 4) + #define DDRDATA0CH1_CR_TXPERBITRANK2_Lane0_MSK (0x0000000F) + #define DDRDATA0CH1_CR_TXPERBITRANK2_Lane0_MAX (0x0000000F) + #define DDRDATA0CH1_CR_TXPERBITRANK2_Lane1_OFF ( 4) + #define DDRDATA0CH1_CR_TXPERBITRANK2_Lane1_WID ( 4) + #define DDRDATA0CH1_CR_TXPERBITRANK2_Lane1_MSK (0x000000F0) + #define DDRDATA0CH1_CR_TXPERBITRANK2_Lane1_MAX (0x0000000F) + #define DDRDATA0CH1_CR_TXPERBITRANK2_Lane2_OFF ( 8) + #define DDRDATA0CH1_CR_TXPERBITRANK2_Lane2_WID ( 4) + #define DDRDATA0CH1_CR_TXPERBITRANK2_Lane2_MSK (0x00000F00) + #define DDRDATA0CH1_CR_TXPERBITRANK2_Lane2_MAX (0x0000000F) + #define DDRDATA0CH1_CR_TXPERBITRANK2_Lane3_OFF (12) + #define DDRDATA0CH1_CR_TXPERBITRANK2_Lane3_WID ( 4) + #define DDRDATA0CH1_CR_TXPERBITRANK2_Lane3_MSK (0x0000F000) + #define DDRDATA0CH1_CR_TXPERBITRANK2_Lane3_MAX (0x0000000F) + #define DDRDATA0CH1_CR_TXPERBITRANK2_Lane4_OFF (16) + #define DDRDATA0CH1_CR_TXPERBITRANK2_Lane4_WID ( 4) + #define DDRDATA0CH1_CR_TXPERBITRANK2_Lane4_MSK (0x000F0000) + #define DDRDATA0CH1_CR_TXPERBITRANK2_Lane4_MAX (0x0000000F) + #define DDRDATA0CH1_CR_TXPERBITRANK2_Lane5_OFF (20) + #define DDRDATA0CH1_CR_TXPERBITRANK2_Lane5_WID ( 4) + #define DDRDATA0CH1_CR_TXPERBITRANK2_Lane5_MSK (0x00F00000) + #define DDRDATA0CH1_CR_TXPERBITRANK2_Lane5_MAX (0x0000000F) + #define DDRDATA0CH1_CR_TXPERBITRANK2_Lane6_OFF (24) + #define DDRDATA0CH1_CR_TXPERBITRANK2_Lane6_WID ( 4) + #define DDRDATA0CH1_CR_TXPERBITRANK2_Lane6_MSK (0x0F000000) + #define DDRDATA0CH1_CR_TXPERBITRANK2_Lane6_MAX (0x0000000F) + #define DDRDATA0CH1_CR_TXPERBITRANK2_Lane7_OFF (28) + #define DDRDATA0CH1_CR_TXPERBITRANK2_Lane7_WID ( 4) + #define DDRDATA0CH1_CR_TXPERBITRANK2_Lane7_MSK (0xF0000000) + #define DDRDATA0CH1_CR_TXPERBITRANK2_Lane7_MAX (0x0000000F) + +#define DDRDATA0CH1_CR_TXPERBITRANK3_REG (0x0000013C) + #define DDRDATA0CH1_CR_TXPERBITRANK3_Lane0_OFF ( 0) + #define DDRDATA0CH1_CR_TXPERBITRANK3_Lane0_WID ( 4) + #define DDRDATA0CH1_CR_TXPERBITRANK3_Lane0_MSK (0x0000000F) + #define DDRDATA0CH1_CR_TXPERBITRANK3_Lane0_MAX (0x0000000F) + #define DDRDATA0CH1_CR_TXPERBITRANK3_Lane1_OFF ( 4) + #define DDRDATA0CH1_CR_TXPERBITRANK3_Lane1_WID ( 4) + #define DDRDATA0CH1_CR_TXPERBITRANK3_Lane1_MSK (0x000000F0) + #define DDRDATA0CH1_CR_TXPERBITRANK3_Lane1_MAX (0x0000000F) + #define DDRDATA0CH1_CR_TXPERBITRANK3_Lane2_OFF ( 8) + #define DDRDATA0CH1_CR_TXPERBITRANK3_Lane2_WID ( 4) + #define DDRDATA0CH1_CR_TXPERBITRANK3_Lane2_MSK (0x00000F00) + #define DDRDATA0CH1_CR_TXPERBITRANK3_Lane2_MAX (0x0000000F) + #define DDRDATA0CH1_CR_TXPERBITRANK3_Lane3_OFF (12) + #define DDRDATA0CH1_CR_TXPERBITRANK3_Lane3_WID ( 4) + #define DDRDATA0CH1_CR_TXPERBITRANK3_Lane3_MSK (0x0000F000) + #define DDRDATA0CH1_CR_TXPERBITRANK3_Lane3_MAX (0x0000000F) + #define DDRDATA0CH1_CR_TXPERBITRANK3_Lane4_OFF (16) + #define DDRDATA0CH1_CR_TXPERBITRANK3_Lane4_WID ( 4) + #define DDRDATA0CH1_CR_TXPERBITRANK3_Lane4_MSK (0x000F0000) + #define DDRDATA0CH1_CR_TXPERBITRANK3_Lane4_MAX (0x0000000F) + #define DDRDATA0CH1_CR_TXPERBITRANK3_Lane5_OFF (20) + #define DDRDATA0CH1_CR_TXPERBITRANK3_Lane5_WID ( 4) + #define DDRDATA0CH1_CR_TXPERBITRANK3_Lane5_MSK (0x00F00000) + #define DDRDATA0CH1_CR_TXPERBITRANK3_Lane5_MAX (0x0000000F) + #define DDRDATA0CH1_CR_TXPERBITRANK3_Lane6_OFF (24) + #define DDRDATA0CH1_CR_TXPERBITRANK3_Lane6_WID ( 4) + #define DDRDATA0CH1_CR_TXPERBITRANK3_Lane6_MSK (0x0F000000) + #define DDRDATA0CH1_CR_TXPERBITRANK3_Lane6_MAX (0x0000000F) + #define DDRDATA0CH1_CR_TXPERBITRANK3_Lane7_OFF (28) + #define DDRDATA0CH1_CR_TXPERBITRANK3_Lane7_WID ( 4) + #define DDRDATA0CH1_CR_TXPERBITRANK3_Lane7_MSK (0xF0000000) + #define DDRDATA0CH1_CR_TXPERBITRANK3_Lane7_MAX (0x0000000F) + +#define DDRDATA0CH1_CR_RCOMPDATA0_REG (0x00000140) + #define DDRDATA0CH1_CR_RCOMPDATA0_RcompDrvUp_OFF ( 0) + #define DDRDATA0CH1_CR_RCOMPDATA0_RcompDrvUp_WID ( 6) + #define DDRDATA0CH1_CR_RCOMPDATA0_RcompDrvUp_MSK (0x0000003F) + #define DDRDATA0CH1_CR_RCOMPDATA0_RcompDrvUp_MAX (0x0000003F) + #define DDRDATA0CH1_CR_RCOMPDATA0_Spare0_OFF ( 6) + #define DDRDATA0CH1_CR_RCOMPDATA0_Spare0_WID ( 3) + #define DDRDATA0CH1_CR_RCOMPDATA0_Spare0_MSK (0x000001C0) + #define DDRDATA0CH1_CR_RCOMPDATA0_Spare0_MAX (0x00000007) + #define DDRDATA0CH1_CR_RCOMPDATA0_RcompDrvDown_OFF ( 9) + #define DDRDATA0CH1_CR_RCOMPDATA0_RcompDrvDown_WID ( 6) + #define DDRDATA0CH1_CR_RCOMPDATA0_RcompDrvDown_MSK (0x00007E00) + #define DDRDATA0CH1_CR_RCOMPDATA0_RcompDrvDown_MAX (0x0000003F) + #define DDRDATA0CH1_CR_RCOMPDATA0_VTComp_OFF (15) + #define DDRDATA0CH1_CR_RCOMPDATA0_VTComp_WID ( 5) + #define DDRDATA0CH1_CR_RCOMPDATA0_VTComp_MSK (0x000F8000) + #define DDRDATA0CH1_CR_RCOMPDATA0_VTComp_MAX (0x0000001F) + #define DDRDATA0CH1_CR_RCOMPDATA0_TcoComp_OFF (20) + #define DDRDATA0CH1_CR_RCOMPDATA0_TcoComp_WID ( 6) + #define DDRDATA0CH1_CR_RCOMPDATA0_TcoComp_MSK (0x03F00000) + #define DDRDATA0CH1_CR_RCOMPDATA0_TcoComp_MAX (0x0000003F) + #define DDRDATA0CH1_CR_RCOMPDATA0_SlewRateComp_OFF (26) + #define DDRDATA0CH1_CR_RCOMPDATA0_SlewRateComp_WID ( 5) + #define DDRDATA0CH1_CR_RCOMPDATA0_SlewRateComp_MSK (0x7C000000) + #define DDRDATA0CH1_CR_RCOMPDATA0_SlewRateComp_MAX (0x0000001F) + #define DDRDATA0CH1_CR_RCOMPDATA0_Spare2_OFF (31) + #define DDRDATA0CH1_CR_RCOMPDATA0_Spare2_WID ( 1) + #define DDRDATA0CH1_CR_RCOMPDATA0_Spare2_MSK (0x80000000) + #define DDRDATA0CH1_CR_RCOMPDATA0_Spare2_MAX (0x00000001) + +#define DDRDATA0CH1_CR_RCOMPDATA1_REG (0x00000144) + #define DDRDATA0CH1_CR_RCOMPDATA1_RcompOdtUp_OFF ( 0) + #define DDRDATA0CH1_CR_RCOMPDATA1_RcompOdtUp_WID ( 6) + #define DDRDATA0CH1_CR_RCOMPDATA1_RcompOdtUp_MSK (0x0000003F) + #define DDRDATA0CH1_CR_RCOMPDATA1_RcompOdtUp_MAX (0x0000003F) + #define DDRDATA0CH1_CR_RCOMPDATA1_Spare0_OFF ( 6) + #define DDRDATA0CH1_CR_RCOMPDATA1_Spare0_WID ( 3) + #define DDRDATA0CH1_CR_RCOMPDATA1_Spare0_MSK (0x000001C0) + #define DDRDATA0CH1_CR_RCOMPDATA1_Spare0_MAX (0x00000007) + #define DDRDATA0CH1_CR_RCOMPDATA1_RcompOdtDown_OFF ( 9) + #define DDRDATA0CH1_CR_RCOMPDATA1_RcompOdtDown_WID ( 6) + #define DDRDATA0CH1_CR_RCOMPDATA1_RcompOdtDown_MSK (0x00007E00) + #define DDRDATA0CH1_CR_RCOMPDATA1_RcompOdtDown_MAX (0x0000003F) + #define DDRDATA0CH1_CR_RCOMPDATA1_Spare1_OFF (15) + #define DDRDATA0CH1_CR_RCOMPDATA1_Spare1_WID ( 1) + #define DDRDATA0CH1_CR_RCOMPDATA1_Spare1_MSK (0x00008000) + #define DDRDATA0CH1_CR_RCOMPDATA1_Spare1_MAX (0x00000001) + #define DDRDATA0CH1_CR_RCOMPDATA1_PanicDrvDn_OFF (16) + #define DDRDATA0CH1_CR_RCOMPDATA1_PanicDrvDn_WID ( 6) + #define DDRDATA0CH1_CR_RCOMPDATA1_PanicDrvDn_MSK (0x003F0000) + #define DDRDATA0CH1_CR_RCOMPDATA1_PanicDrvDn_MAX (0x0000003F) + #define DDRDATA0CH1_CR_RCOMPDATA1_PanicDrvUp_OFF (22) + #define DDRDATA0CH1_CR_RCOMPDATA1_PanicDrvUp_WID ( 6) + #define DDRDATA0CH1_CR_RCOMPDATA1_PanicDrvUp_MSK (0x0FC00000) + #define DDRDATA0CH1_CR_RCOMPDATA1_PanicDrvUp_MAX (0x0000003F) + #define DDRDATA0CH1_CR_RCOMPDATA1_LevelShifterComp_OFF (28) + #define DDRDATA0CH1_CR_RCOMPDATA1_LevelShifterComp_WID ( 3) + #define DDRDATA0CH1_CR_RCOMPDATA1_LevelShifterComp_MSK (0x70000000) + #define DDRDATA0CH1_CR_RCOMPDATA1_LevelShifterComp_MAX (0x00000007) + #define DDRDATA0CH1_CR_RCOMPDATA1_Spare2_OFF (31) + #define DDRDATA0CH1_CR_RCOMPDATA1_Spare2_WID ( 1) + #define DDRDATA0CH1_CR_RCOMPDATA1_Spare2_MSK (0x80000000) + #define DDRDATA0CH1_CR_RCOMPDATA1_Spare2_MAX (0x00000001) + +#define DDRDATA0CH1_CR_TXXTALK_REG (0x00000148) + #define DDRDATA0CH1_CR_TXXTALK_Lane0_OFF ( 0) + #define DDRDATA0CH1_CR_TXXTALK_Lane0_WID ( 4) + #define DDRDATA0CH1_CR_TXXTALK_Lane0_MSK (0x0000000F) + #define DDRDATA0CH1_CR_TXXTALK_Lane0_MAX (0x0000000F) + #define DDRDATA0CH1_CR_TXXTALK_Lane1_OFF ( 4) + #define DDRDATA0CH1_CR_TXXTALK_Lane1_WID ( 4) + #define DDRDATA0CH1_CR_TXXTALK_Lane1_MSK (0x000000F0) + #define DDRDATA0CH1_CR_TXXTALK_Lane1_MAX (0x0000000F) + #define DDRDATA0CH1_CR_TXXTALK_Lane2_OFF ( 8) + #define DDRDATA0CH1_CR_TXXTALK_Lane2_WID ( 4) + #define DDRDATA0CH1_CR_TXXTALK_Lane2_MSK (0x00000F00) + #define DDRDATA0CH1_CR_TXXTALK_Lane2_MAX (0x0000000F) + #define DDRDATA0CH1_CR_TXXTALK_Lane3_OFF (12) + #define DDRDATA0CH1_CR_TXXTALK_Lane3_WID ( 4) + #define DDRDATA0CH1_CR_TXXTALK_Lane3_MSK (0x0000F000) + #define DDRDATA0CH1_CR_TXXTALK_Lane3_MAX (0x0000000F) + #define DDRDATA0CH1_CR_TXXTALK_Lane4_OFF (16) + #define DDRDATA0CH1_CR_TXXTALK_Lane4_WID ( 4) + #define DDRDATA0CH1_CR_TXXTALK_Lane4_MSK (0x000F0000) + #define DDRDATA0CH1_CR_TXXTALK_Lane4_MAX (0x0000000F) + #define DDRDATA0CH1_CR_TXXTALK_Lane5_OFF (20) + #define DDRDATA0CH1_CR_TXXTALK_Lane5_WID ( 4) + #define DDRDATA0CH1_CR_TXXTALK_Lane5_MSK (0x00F00000) + #define DDRDATA0CH1_CR_TXXTALK_Lane5_MAX (0x0000000F) + #define DDRDATA0CH1_CR_TXXTALK_Lane6_OFF (24) + #define DDRDATA0CH1_CR_TXXTALK_Lane6_WID ( 4) + #define DDRDATA0CH1_CR_TXXTALK_Lane6_MSK (0x0F000000) + #define DDRDATA0CH1_CR_TXXTALK_Lane6_MAX (0x0000000F) + #define DDRDATA0CH1_CR_TXXTALK_Lane7_OFF (28) + #define DDRDATA0CH1_CR_TXXTALK_Lane7_WID ( 4) + #define DDRDATA0CH1_CR_TXXTALK_Lane7_MSK (0xF0000000) + #define DDRDATA0CH1_CR_TXXTALK_Lane7_MAX (0x0000000F) + +#define DDRDATA0CH1_CR_RXOFFSETVDQ_REG (0x0000014C) + #define DDRDATA0CH1_CR_RXOFFSETVDQ_Lane0_OFF ( 0) + #define DDRDATA0CH1_CR_RXOFFSETVDQ_Lane0_WID ( 4) + #define DDRDATA0CH1_CR_RXOFFSETVDQ_Lane0_MSK (0x0000000F) + #define DDRDATA0CH1_CR_RXOFFSETVDQ_Lane0_MAX (0x0000000F) + #define DDRDATA0CH1_CR_RXOFFSETVDQ_Lane1_OFF ( 4) + #define DDRDATA0CH1_CR_RXOFFSETVDQ_Lane1_WID ( 4) + #define DDRDATA0CH1_CR_RXOFFSETVDQ_Lane1_MSK (0x000000F0) + #define DDRDATA0CH1_CR_RXOFFSETVDQ_Lane1_MAX (0x0000000F) + #define DDRDATA0CH1_CR_RXOFFSETVDQ_Lane2_OFF ( 8) + #define DDRDATA0CH1_CR_RXOFFSETVDQ_Lane2_WID ( 4) + #define DDRDATA0CH1_CR_RXOFFSETVDQ_Lane2_MSK (0x00000F00) + #define DDRDATA0CH1_CR_RXOFFSETVDQ_Lane2_MAX (0x0000000F) + #define DDRDATA0CH1_CR_RXOFFSETVDQ_Lane3_OFF (12) + #define DDRDATA0CH1_CR_RXOFFSETVDQ_Lane3_WID ( 4) + #define DDRDATA0CH1_CR_RXOFFSETVDQ_Lane3_MSK (0x0000F000) + #define DDRDATA0CH1_CR_RXOFFSETVDQ_Lane3_MAX (0x0000000F) + #define DDRDATA0CH1_CR_RXOFFSETVDQ_Lane4_OFF (16) + #define DDRDATA0CH1_CR_RXOFFSETVDQ_Lane4_WID ( 4) + #define DDRDATA0CH1_CR_RXOFFSETVDQ_Lane4_MSK (0x000F0000) + #define DDRDATA0CH1_CR_RXOFFSETVDQ_Lane4_MAX (0x0000000F) + #define DDRDATA0CH1_CR_RXOFFSETVDQ_Lane5_OFF (20) + #define DDRDATA0CH1_CR_RXOFFSETVDQ_Lane5_WID ( 4) + #define DDRDATA0CH1_CR_RXOFFSETVDQ_Lane5_MSK (0x00F00000) + #define DDRDATA0CH1_CR_RXOFFSETVDQ_Lane5_MAX (0x0000000F) + #define DDRDATA0CH1_CR_RXOFFSETVDQ_Lane6_OFF (24) + #define DDRDATA0CH1_CR_RXOFFSETVDQ_Lane6_WID ( 4) + #define DDRDATA0CH1_CR_RXOFFSETVDQ_Lane6_MSK (0x0F000000) + #define DDRDATA0CH1_CR_RXOFFSETVDQ_Lane6_MAX (0x0000000F) + #define DDRDATA0CH1_CR_RXOFFSETVDQ_Lane7_OFF (28) + #define DDRDATA0CH1_CR_RXOFFSETVDQ_Lane7_WID ( 4) + #define DDRDATA0CH1_CR_RXOFFSETVDQ_Lane7_MSK (0xF0000000) + #define DDRDATA0CH1_CR_RXOFFSETVDQ_Lane7_MAX (0x0000000F) + +#define DDRDATA0CH1_CR_DDRDATARESERVED_REG (0x00000150) + #define DDRDATA0CH1_CR_DDRDATARESERVED_Spare_OFF ( 0) + #define DDRDATA0CH1_CR_DDRDATARESERVED_Spare_WID (32) + #define DDRDATA0CH1_CR_DDRDATARESERVED_Spare_MSK (0xFFFFFFFF) + #define DDRDATA0CH1_CR_DDRDATARESERVED_Spare_MAX (0xFFFFFFFF) + +#define DDRDATA0CH1_CR_DATATRAINFEEDBACK_REG (0x00000154) + #define DDRDATA0CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_OFF ( 0) + #define DDRDATA0CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_WID ( 9) + #define DDRDATA0CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_MSK (0x000001FF) + #define DDRDATA0CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_MAX (0x000001FF) + #define DDRDATA0CH1_CR_DATATRAINFEEDBACK_Spare_OFF ( 9) + #define DDRDATA0CH1_CR_DATATRAINFEEDBACK_Spare_WID (23) + #define DDRDATA0CH1_CR_DATATRAINFEEDBACK_Spare_MSK (0xFFFFFE00) + #define DDRDATA0CH1_CR_DATATRAINFEEDBACK_Spare_MAX (0x007FFFFF) + +#define DDRDATA0CH1_CR_DLLPITESTANDADC_REG (0x00000158) + #define DDRDATA0CH1_CR_DLLPITESTANDADC_RunTest_OFF ( 0) + #define DDRDATA0CH1_CR_DLLPITESTANDADC_RunTest_WID ( 1) + #define DDRDATA0CH1_CR_DLLPITESTANDADC_RunTest_MSK (0x00000001) + #define DDRDATA0CH1_CR_DLLPITESTANDADC_RunTest_MAX (0x00000001) + #define DDRDATA0CH1_CR_DLLPITESTANDADC_RunTest_DEF (0x00000000) + #define DDRDATA0CH1_CR_DLLPITESTANDADC_Load_OFF ( 1) + #define DDRDATA0CH1_CR_DLLPITESTANDADC_Load_WID ( 1) + #define DDRDATA0CH1_CR_DLLPITESTANDADC_Load_MSK (0x00000002) + #define DDRDATA0CH1_CR_DLLPITESTANDADC_Load_MAX (0x00000001) + #define DDRDATA0CH1_CR_DLLPITESTANDADC_Load_DEF (0x00000000) + #define DDRDATA0CH1_CR_DLLPITESTANDADC_ModeHVM_OFF ( 2) + #define DDRDATA0CH1_CR_DLLPITESTANDADC_ModeHVM_WID ( 1) + #define DDRDATA0CH1_CR_DLLPITESTANDADC_ModeHVM_MSK (0x00000004) + #define DDRDATA0CH1_CR_DLLPITESTANDADC_ModeHVM_MAX (0x00000001) + #define DDRDATA0CH1_CR_DLLPITESTANDADC_ModeHVM_DEF (0x00000000) + #define DDRDATA0CH1_CR_DLLPITESTANDADC_ModeDV_OFF ( 3) + #define DDRDATA0CH1_CR_DLLPITESTANDADC_ModeDV_WID ( 1) + #define DDRDATA0CH1_CR_DLLPITESTANDADC_ModeDV_MSK (0x00000008) + #define DDRDATA0CH1_CR_DLLPITESTANDADC_ModeDV_MAX (0x00000001) + #define DDRDATA0CH1_CR_DLLPITESTANDADC_ModeDV_DEF (0x00000000) + #define DDRDATA0CH1_CR_DLLPITESTANDADC_ModeADC_OFF ( 4) + #define DDRDATA0CH1_CR_DLLPITESTANDADC_ModeADC_WID ( 1) + #define DDRDATA0CH1_CR_DLLPITESTANDADC_ModeADC_MSK (0x00000010) + #define DDRDATA0CH1_CR_DLLPITESTANDADC_ModeADC_MAX (0x00000001) + #define DDRDATA0CH1_CR_DLLPITESTANDADC_ModeADC_DEF (0x00000000) + #define DDRDATA0CH1_CR_DLLPITESTANDADC_LoadCount_OFF ( 5) + #define DDRDATA0CH1_CR_DLLPITESTANDADC_LoadCount_WID (10) + #define DDRDATA0CH1_CR_DLLPITESTANDADC_LoadCount_MSK (0x00007FE0) + #define DDRDATA0CH1_CR_DLLPITESTANDADC_LoadCount_MAX (0x000003FF) + #define DDRDATA0CH1_CR_DLLPITESTANDADC_CountStatus_OFF (15) + #define DDRDATA0CH1_CR_DLLPITESTANDADC_CountStatus_WID (10) + #define DDRDATA0CH1_CR_DLLPITESTANDADC_CountStatus_MSK (0x01FF8000) + #define DDRDATA0CH1_CR_DLLPITESTANDADC_CountStatus_MAX (0x000003FF) + #define DDRDATA0CH1_CR_DLLPITESTANDADC_CountStatus_DEF (0x00000000) + #define DDRDATA0CH1_CR_DLLPITESTANDADC_Spare_OFF (25) + #define DDRDATA0CH1_CR_DLLPITESTANDADC_Spare_WID ( 7) + #define DDRDATA0CH1_CR_DLLPITESTANDADC_Spare_MSK (0xFE000000) + #define DDRDATA0CH1_CR_DLLPITESTANDADC_Spare_MAX (0x0000007F) + +#define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_REG (0x0000015C) + #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_OFF ( 0) + #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_WID ( 6) + #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MSK (0x0000003F) + #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MAX (0x0000003F) + #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_DEF (0x00000000) + #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_OFF ( 6) + #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_WID ( 6) + #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MSK (0x00000FC0) + #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MAX (0x0000003F) + #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_DEF (0x00000000) + #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_OFF (12) + #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_WID ( 5) + #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MSK (0x0001F000) + #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MAX (0x0000001F) + #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_DEF (0x00000000) + #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_OFF (17) + #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_WID ( 5) + #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MSK (0x003E0000) + #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MAX (0x0000001F) + #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_DEF (0x00000000) + #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_OFF (22) + #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_WID ( 5) + #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_MSK (0x07C00000) + #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_MAX (0x0000001F) + #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_DEF (0x00000000) + #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_OFF (27) + #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_WID ( 5) + #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MSK (0xF8000000) + #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MAX (0x0000001F) + #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_DEF (0x00000000) + +#define DDRDATA0CH1_CR_DDRCRDATACONTROL1_REG (0x00000160) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_RefPi_OFF ( 0) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_RefPi_WID ( 4) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_RefPi_MSK (0x0000000F) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_RefPi_MAX (0x0000000F) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_RefPi_DEF (0x00000000) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_DllMask_OFF ( 4) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_DllMask_WID ( 2) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_DllMask_MSK (0x00000030) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_DllMask_MAX (0x00000003) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_DllMask_DEF (0x00000000) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_DllWeakLock_OFF ( 6) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_DllWeakLock_WID ( 1) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_DllWeakLock_MSK (0x00000040) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_DllWeakLock_MAX (0x00000001) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_DllWeakLock_DEF (0x00000000) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_OFF ( 7) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_WID ( 3) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MSK (0x00000380) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MAX (0x00000007) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_DEF (0x00000000) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_OFF (10) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_WID ( 3) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_MSK (0x00001C00) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_MAX (0x00000007) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_DEF (0x00000000) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_OdtDelay_OFF (13) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_OdtDelay_WID ( 4) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_OdtDelay_MSK (0x0001E000) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_OdtDelay_MAX (0x0000000F) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_OdtDelay_DEF (0x00000000) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_OdtDuration_OFF (17) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_OdtDuration_WID ( 3) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_OdtDuration_MSK (0x000E0000) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_OdtDuration_MAX (0x00000007) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_OdtDuration_DEF (0x00000000) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_OFF (20) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_WID ( 4) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_MSK (0x00F00000) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_MAX (0x0000000F) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_DEF (0x00000000) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_OFF (24) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_WID ( 3) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_MSK (0x07000000) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_MAX (0x00000007) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_DEF (0x00000000) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_OFF (27) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_WID ( 3) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_MSK (0x38000000) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_MAX (0x00000007) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_DEF (0x00000000) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_OFF (30) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_WID ( 1) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_MSK (0x40000000) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_MAX (0x00000001) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_DEF (0x00000000) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_Rsvd1_OFF (31) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_Rsvd1_WID ( 1) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_Rsvd1_MSK (0x80000000) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_Rsvd1_MAX (0x00000001) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_Rsvd1_DEF (0x00000000) + +#define DDRDATA0CH1_CR_DDRCRDATACONTROL2_REG (0x00000164) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_OFF ( 0) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_WID ( 5) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_MSK (0x0000001F) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_MAX (0x0000001F) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_DEF (0x00000000) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_OFF ( 5) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_WID ( 1) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_MSK (0x00000020) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_MAX (0x00000001) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_DEF (0x00000000) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_ForceRxOn_OFF ( 6) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_ForceRxOn_WID ( 1) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_ForceRxOn_MSK (0x00000040) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_ForceRxOn_MAX (0x00000001) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_ForceRxOn_DEF (0x00000000) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_LeakerComp_OFF ( 7) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_LeakerComp_WID ( 2) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_LeakerComp_MSK (0x00000180) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_LeakerComp_MAX (0x00000003) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_LeakerComp_DEF (0x00000000) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_OFF ( 9) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_WID ( 4) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_MSK (0x00001E00) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_MAX (0x0000000F) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_DEF (0x00000008) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_OFF (13) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_WID ( 5) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_MSK (0x0003E000) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_MAX (0x0000001F) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_DEF (0x00000011) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_OFF (18) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_WID ( 1) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_MSK (0x00040000) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_MAX (0x00000001) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_DEF (0x00000000) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_Spare_OFF (19) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_Spare_WID (13) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_Spare_MSK (0xFFF80000) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_Spare_MAX (0x00001FFF) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_Spare_DEF (0x00000000) + +#define DDRDATA0CH1_CR_DDRCRVSSHIORVREFCONTROL_REG (0x0000016C) + #define DDRDATA0CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_OFF ( 0) + #define DDRDATA0CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_WID (24) + #define DDRDATA0CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_MSK (0x00FFFFFF) + #define DDRDATA0CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_MAX (0x00FFFFFF) + #define DDRDATA0CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_DEF (0x00000000) + #define DDRDATA0CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_OFF (24) + #define DDRDATA0CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_WID ( 8) + #define DDRDATA0CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_MSK (0xFF000000) + #define DDRDATA0CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_MAX (0x000000FF) + #define DDRDATA0CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_DEF (0x00000000) + +#define DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_REG (0x00000170) + #define DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_OFF ( 0) + #define DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_WID ( 6) + #define DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MSK (0x0000003F) + #define DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MAX (0x0000003F) + #define DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_DEF (0x00000000) + #define DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_OFF ( 6) + #define DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_WID ( 6) + #define DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MSK (0x00000FC0) + #define DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MAX (0x0000003F) + #define DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_DEF (0x00000000) + #define DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_OFF (12) + #define DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_WID ( 6) + #define DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MSK (0x0003F000) + #define DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MAX (0x0000003F) + #define DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_DEF (0x00000000) + #define DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_OFF (18) + #define DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_WID ( 6) + #define DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MSK (0x00FC0000) + #define DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MAX (0x0000003F) + #define DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_DEF (0x00000000) + #define DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_OFF (24) + #define DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_WID ( 7) + #define DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MSK (0x7F000000) + #define DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MAX (0x0000007F) + #define DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_DEF (0x00000000) + #define DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_OFF (31) + #define DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_WID ( 1) + #define DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_MSK (0x80000000) + #define DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_MAX (0x00000001) + #define DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_DEF (0x00000000) + +#define DDRDATA0CH1_CR_DDRCRDATACONTROL0_REG (0x00000174) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_OFF ( 0) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_WID ( 1) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_MSK (0x00000001) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_MAX (0x00000001) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_DEF (0x00000000) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_OFF ( 1) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_WID ( 1) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_MSK (0x00000002) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_MAX (0x00000001) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_DEF (0x00000000) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_OFF ( 2) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_WID ( 1) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_MSK (0x00000004) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_MAX (0x00000001) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_DEF (0x00000000) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_OFF ( 3) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_WID ( 1) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MSK (0x00000008) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MAX (0x00000001) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_DEF (0x00000000) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_TxOn_OFF ( 4) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_TxOn_WID ( 1) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_TxOn_MSK (0x00000010) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_TxOn_MAX (0x00000001) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_TxOn_DEF (0x00000000) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RfOn_OFF ( 5) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RfOn_WID ( 1) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RfOn_MSK (0x00000020) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RfOn_MAX (0x00000001) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RfOn_DEF (0x00000000) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RxPiOn_OFF ( 6) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RxPiOn_WID ( 1) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RxPiOn_MSK (0x00000040) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RxPiOn_MAX (0x00000001) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RxPiOn_DEF (0x00000000) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_TxPiOn_OFF ( 7) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_TxPiOn_WID ( 1) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_TxPiOn_MSK (0x00000080) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_TxPiOn_MAX (0x00000001) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_TxPiOn_DEF (0x00000000) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_OFF ( 8) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_WID ( 1) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_MSK (0x00000100) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_MAX (0x00000001) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_DEF (0x00000000) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_OFF ( 9) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_WID ( 1) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MSK (0x00000200) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MAX (0x00000001) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_DEF (0x00000000) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_TxDisable_OFF (10) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_TxDisable_WID ( 1) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_TxDisable_MSK (0x00000400) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_TxDisable_MAX (0x00000001) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_TxDisable_DEF (0x00000000) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RxDisable_OFF (11) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RxDisable_WID ( 1) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RxDisable_MSK (0x00000800) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RxDisable_MAX (0x00000001) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RxDisable_DEF (0x00000000) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_TxLong_OFF (12) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_TxLong_WID ( 1) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_TxLong_MSK (0x00001000) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_TxLong_MAX (0x00000001) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_TxLong_DEF (0x00000000) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_OFF (13) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_WID ( 2) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_MSK (0x00006000) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_MAX (0x00000003) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_DEF (0x00000000) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RxReadPointer_OFF (15) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RxReadPointer_WID ( 3) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RxReadPointer_MSK (0x00038000) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RxReadPointer_MAX (0x00000007) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RxReadPointer_DEF (0x00000000) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_OFF (18) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_WID ( 1) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_MSK (0x00040000) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_MAX (0x00000001) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_DEF (0x00000000) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_OFF (19) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_WID ( 1) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_MSK (0x00080000) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_MAX (0x00000001) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_DEF (0x00000000) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_ReadRFRd_OFF (20) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_ReadRFRd_WID ( 1) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_ReadRFRd_MSK (0x00100000) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_ReadRFRd_MAX (0x00000001) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_ReadRFRd_DEF (0x00000000) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_ReadRFWr_OFF (21) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_ReadRFWr_WID ( 1) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_ReadRFWr_MSK (0x00200000) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_ReadRFWr_MAX (0x00000001) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_ReadRFWr_DEF (0x00000000) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_ReadRFRank_OFF (22) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_ReadRFRank_WID ( 2) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_ReadRFRank_MSK (0x00C00000) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_ReadRFRank_MAX (0x00000003) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_ReadRFRank_DEF (0x00000000) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_OFF (24) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_WID ( 1) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_MSK (0x01000000) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_MAX (0x00000001) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_DEF (0x00000000) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_OdtSampOff_OFF (25) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_OdtSampOff_WID ( 1) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_OdtSampOff_MSK (0x02000000) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_OdtSampOff_MAX (0x00000001) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_OdtSampOff_DEF (0x00000000) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_OFF (26) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_WID ( 1) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_MSK (0x04000000) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_MAX (0x00000001) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_DEF (0x00000000) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_OFF (27) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_WID ( 1) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MSK (0x08000000) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MAX (0x00000001) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_DEF (0x00000000) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_OFF (28) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_WID ( 1) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_MSK (0x10000000) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_MAX (0x00000001) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_DEF (0x00000000) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_OFF (29) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_WID ( 1) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_MSK (0x20000000) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_MAX (0x00000001) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_DEF (0x00000000) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_OFF (30) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_WID ( 1) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MSK (0x40000000) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MAX (0x00000001) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_DEF (0x00000000) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_OFF (31) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_WID ( 1) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_MSK (0x80000000) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_MAX (0x00000001) + #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_DEF (0x00000000) + +#define DDRDATA0CH1_CR_DDRCRVREFADJUST1_REG (0x00000178) + #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_OFF ( 0) + #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_WID ( 7) + #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_MSK (0x0000007F) + #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_MAX (0x0000007F) + #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_DEF (0x00000000) + #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_OFF ( 7) + #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_WID ( 7) + #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_MSK (0x00003F80) + #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_MAX (0x0000007F) + #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_DEF (0x00000000) + #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_OFF (14) + #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_WID ( 7) + #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_MSK (0x001FC000) + #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_MAX (0x0000007F) + #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_DEF (0x00000000) + #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_OFF (21) + #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_WID ( 1) + #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_MSK (0x00200000) + #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_MAX (0x00000001) + #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_DEF (0x00000000) + #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_OFF (22) + #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_WID ( 1) + #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_MSK (0x00400000) + #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_MAX (0x00000001) + #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_DEF (0x00000000) + #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_OFF (23) + #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_WID ( 1) + #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_MSK (0x00800000) + #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_MAX (0x00000001) + #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_DEF (0x00000000) + #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_OFF (24) + #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_WID ( 2) + #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_MSK (0x03000000) + #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_MAX (0x00000003) + #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_DEF (0x00000000) + #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_OFF (26) + #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_WID ( 1) + #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_MSK (0x04000000) + #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_MAX (0x00000001) + #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_DEF (0x00000000) + #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_Rsvd_OFF (27) + #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_Rsvd_WID ( 2) + #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_Rsvd_MSK (0x18000000) + #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_Rsvd_MAX (0x00000003) + #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_Rsvd_DEF (0x00000000) + #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_caSlowBW_OFF (29) + #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_caSlowBW_WID ( 1) + #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_caSlowBW_MSK (0x20000000) + #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_caSlowBW_MAX (0x00000001) + #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_caSlowBW_DEF (0x00000000) + #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_OFF (30) + #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_WID ( 1) + #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_MSK (0x40000000) + #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_MAX (0x00000001) + #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_DEF (0x00000000) + #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_OFF (31) + #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_WID ( 1) + #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_MSK (0x80000000) + #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_MAX (0x00000001) + #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_DEF (0x00000000) + +#define DDRDATA1CH0_CR_RXTRAINRANK0_REG (0x00000200) + #define DDRDATA1CH0_CR_RXTRAINRANK0_RxRcvEnPi_OFF ( 0) + #define DDRDATA1CH0_CR_RXTRAINRANK0_RxRcvEnPi_WID ( 9) + #define DDRDATA1CH0_CR_RXTRAINRANK0_RxRcvEnPi_MSK (0x000001FF) + #define DDRDATA1CH0_CR_RXTRAINRANK0_RxRcvEnPi_MAX (0x000001FF) + #define DDRDATA1CH0_CR_RXTRAINRANK0_RxDqsPPi_OFF ( 9) + #define DDRDATA1CH0_CR_RXTRAINRANK0_RxDqsPPi_WID ( 6) + #define DDRDATA1CH0_CR_RXTRAINRANK0_RxDqsPPi_MSK (0x00007E00) + #define DDRDATA1CH0_CR_RXTRAINRANK0_RxDqsPPi_MAX (0x0000003F) + #define DDRDATA1CH0_CR_RXTRAINRANK0_RxEq_OFF (15) + #define DDRDATA1CH0_CR_RXTRAINRANK0_RxEq_WID ( 5) + #define DDRDATA1CH0_CR_RXTRAINRANK0_RxEq_MSK (0x000F8000) + #define DDRDATA1CH0_CR_RXTRAINRANK0_RxEq_MAX (0x0000001F) + #define DDRDATA1CH0_CR_RXTRAINRANK0_RxDqsNPi_OFF (20) + #define DDRDATA1CH0_CR_RXTRAINRANK0_RxDqsNPi_WID ( 6) + #define DDRDATA1CH0_CR_RXTRAINRANK0_RxDqsNPi_MSK (0x03F00000) + #define DDRDATA1CH0_CR_RXTRAINRANK0_RxDqsNPi_MAX (0x0000003F) + #define DDRDATA1CH0_CR_RXTRAINRANK0_RxVref_OFF (26) + #define DDRDATA1CH0_CR_RXTRAINRANK0_RxVref_WID ( 6) + #define DDRDATA1CH0_CR_RXTRAINRANK0_RxVref_MSK (0xFC000000) + #define DDRDATA1CH0_CR_RXTRAINRANK0_RxVref_MAX (0x0000003F) + +#define DDRDATA1CH0_CR_RXTRAINRANK1_REG (0x00000204) + #define DDRDATA1CH0_CR_RXTRAINRANK1_RxRcvEnPi_OFF ( 0) + #define DDRDATA1CH0_CR_RXTRAINRANK1_RxRcvEnPi_WID ( 9) + #define DDRDATA1CH0_CR_RXTRAINRANK1_RxRcvEnPi_MSK (0x000001FF) + #define DDRDATA1CH0_CR_RXTRAINRANK1_RxRcvEnPi_MAX (0x000001FF) + #define DDRDATA1CH0_CR_RXTRAINRANK1_RxDqsPPi_OFF ( 9) + #define DDRDATA1CH0_CR_RXTRAINRANK1_RxDqsPPi_WID ( 6) + #define DDRDATA1CH0_CR_RXTRAINRANK1_RxDqsPPi_MSK (0x00007E00) + #define DDRDATA1CH0_CR_RXTRAINRANK1_RxDqsPPi_MAX (0x0000003F) + #define DDRDATA1CH0_CR_RXTRAINRANK1_RxEq_OFF (15) + #define DDRDATA1CH0_CR_RXTRAINRANK1_RxEq_WID ( 5) + #define DDRDATA1CH0_CR_RXTRAINRANK1_RxEq_MSK (0x000F8000) + #define DDRDATA1CH0_CR_RXTRAINRANK1_RxEq_MAX (0x0000001F) + #define DDRDATA1CH0_CR_RXTRAINRANK1_RxDqsNPi_OFF (20) + #define DDRDATA1CH0_CR_RXTRAINRANK1_RxDqsNPi_WID ( 6) + #define DDRDATA1CH0_CR_RXTRAINRANK1_RxDqsNPi_MSK (0x03F00000) + #define DDRDATA1CH0_CR_RXTRAINRANK1_RxDqsNPi_MAX (0x0000003F) + #define DDRDATA1CH0_CR_RXTRAINRANK1_RxVref_OFF (26) + #define DDRDATA1CH0_CR_RXTRAINRANK1_RxVref_WID ( 6) + #define DDRDATA1CH0_CR_RXTRAINRANK1_RxVref_MSK (0xFC000000) + #define DDRDATA1CH0_CR_RXTRAINRANK1_RxVref_MAX (0x0000003F) + +#define DDRDATA1CH0_CR_RXTRAINRANK2_REG (0x00000208) + #define DDRDATA1CH0_CR_RXTRAINRANK2_RxRcvEnPi_OFF ( 0) + #define DDRDATA1CH0_CR_RXTRAINRANK2_RxRcvEnPi_WID ( 9) + #define DDRDATA1CH0_CR_RXTRAINRANK2_RxRcvEnPi_MSK (0x000001FF) + #define DDRDATA1CH0_CR_RXTRAINRANK2_RxRcvEnPi_MAX (0x000001FF) + #define DDRDATA1CH0_CR_RXTRAINRANK2_RxDqsPPi_OFF ( 9) + #define DDRDATA1CH0_CR_RXTRAINRANK2_RxDqsPPi_WID ( 6) + #define DDRDATA1CH0_CR_RXTRAINRANK2_RxDqsPPi_MSK (0x00007E00) + #define DDRDATA1CH0_CR_RXTRAINRANK2_RxDqsPPi_MAX (0x0000003F) + #define DDRDATA1CH0_CR_RXTRAINRANK2_RxEq_OFF (15) + #define DDRDATA1CH0_CR_RXTRAINRANK2_RxEq_WID ( 5) + #define DDRDATA1CH0_CR_RXTRAINRANK2_RxEq_MSK (0x000F8000) + #define DDRDATA1CH0_CR_RXTRAINRANK2_RxEq_MAX (0x0000001F) + #define DDRDATA1CH0_CR_RXTRAINRANK2_RxDqsNPi_OFF (20) + #define DDRDATA1CH0_CR_RXTRAINRANK2_RxDqsNPi_WID ( 6) + #define DDRDATA1CH0_CR_RXTRAINRANK2_RxDqsNPi_MSK (0x03F00000) + #define DDRDATA1CH0_CR_RXTRAINRANK2_RxDqsNPi_MAX (0x0000003F) + #define DDRDATA1CH0_CR_RXTRAINRANK2_RxVref_OFF (26) + #define DDRDATA1CH0_CR_RXTRAINRANK2_RxVref_WID ( 6) + #define DDRDATA1CH0_CR_RXTRAINRANK2_RxVref_MSK (0xFC000000) + #define DDRDATA1CH0_CR_RXTRAINRANK2_RxVref_MAX (0x0000003F) + +#define DDRDATA1CH0_CR_RXTRAINRANK3_REG (0x0000020C) + #define DDRDATA1CH0_CR_RXTRAINRANK3_RxRcvEnPi_OFF ( 0) + #define DDRDATA1CH0_CR_RXTRAINRANK3_RxRcvEnPi_WID ( 9) + #define DDRDATA1CH0_CR_RXTRAINRANK3_RxRcvEnPi_MSK (0x000001FF) + #define DDRDATA1CH0_CR_RXTRAINRANK3_RxRcvEnPi_MAX (0x000001FF) + #define DDRDATA1CH0_CR_RXTRAINRANK3_RxDqsPPi_OFF ( 9) + #define DDRDATA1CH0_CR_RXTRAINRANK3_RxDqsPPi_WID ( 6) + #define DDRDATA1CH0_CR_RXTRAINRANK3_RxDqsPPi_MSK (0x00007E00) + #define DDRDATA1CH0_CR_RXTRAINRANK3_RxDqsPPi_MAX (0x0000003F) + #define DDRDATA1CH0_CR_RXTRAINRANK3_RxEq_OFF (15) + #define DDRDATA1CH0_CR_RXTRAINRANK3_RxEq_WID ( 5) + #define DDRDATA1CH0_CR_RXTRAINRANK3_RxEq_MSK (0x000F8000) + #define DDRDATA1CH0_CR_RXTRAINRANK3_RxEq_MAX (0x0000001F) + #define DDRDATA1CH0_CR_RXTRAINRANK3_RxDqsNPi_OFF (20) + #define DDRDATA1CH0_CR_RXTRAINRANK3_RxDqsNPi_WID ( 6) + #define DDRDATA1CH0_CR_RXTRAINRANK3_RxDqsNPi_MSK (0x03F00000) + #define DDRDATA1CH0_CR_RXTRAINRANK3_RxDqsNPi_MAX (0x0000003F) + #define DDRDATA1CH0_CR_RXTRAINRANK3_RxVref_OFF (26) + #define DDRDATA1CH0_CR_RXTRAINRANK3_RxVref_WID ( 6) + #define DDRDATA1CH0_CR_RXTRAINRANK3_RxVref_MSK (0xFC000000) + #define DDRDATA1CH0_CR_RXTRAINRANK3_RxVref_MAX (0x0000003F) + +#define DDRDATA1CH0_CR_RXPERBITRANK0_REG (0x00000210) + #define DDRDATA1CH0_CR_RXPERBITRANK0_Lane0_OFF ( 0) + #define DDRDATA1CH0_CR_RXPERBITRANK0_Lane0_WID ( 4) + #define DDRDATA1CH0_CR_RXPERBITRANK0_Lane0_MSK (0x0000000F) + #define DDRDATA1CH0_CR_RXPERBITRANK0_Lane0_MAX (0x0000000F) + #define DDRDATA1CH0_CR_RXPERBITRANK0_Lane1_OFF ( 4) + #define DDRDATA1CH0_CR_RXPERBITRANK0_Lane1_WID ( 4) + #define DDRDATA1CH0_CR_RXPERBITRANK0_Lane1_MSK (0x000000F0) + #define DDRDATA1CH0_CR_RXPERBITRANK0_Lane1_MAX (0x0000000F) + #define DDRDATA1CH0_CR_RXPERBITRANK0_Lane2_OFF ( 8) + #define DDRDATA1CH0_CR_RXPERBITRANK0_Lane2_WID ( 4) + #define DDRDATA1CH0_CR_RXPERBITRANK0_Lane2_MSK (0x00000F00) + #define DDRDATA1CH0_CR_RXPERBITRANK0_Lane2_MAX (0x0000000F) + #define DDRDATA1CH0_CR_RXPERBITRANK0_Lane3_OFF (12) + #define DDRDATA1CH0_CR_RXPERBITRANK0_Lane3_WID ( 4) + #define DDRDATA1CH0_CR_RXPERBITRANK0_Lane3_MSK (0x0000F000) + #define DDRDATA1CH0_CR_RXPERBITRANK0_Lane3_MAX (0x0000000F) + #define DDRDATA1CH0_CR_RXPERBITRANK0_Lane4_OFF (16) + #define DDRDATA1CH0_CR_RXPERBITRANK0_Lane4_WID ( 4) + #define DDRDATA1CH0_CR_RXPERBITRANK0_Lane4_MSK (0x000F0000) + #define DDRDATA1CH0_CR_RXPERBITRANK0_Lane4_MAX (0x0000000F) + #define DDRDATA1CH0_CR_RXPERBITRANK0_Lane5_OFF (20) + #define DDRDATA1CH0_CR_RXPERBITRANK0_Lane5_WID ( 4) + #define DDRDATA1CH0_CR_RXPERBITRANK0_Lane5_MSK (0x00F00000) + #define DDRDATA1CH0_CR_RXPERBITRANK0_Lane5_MAX (0x0000000F) + #define DDRDATA1CH0_CR_RXPERBITRANK0_Lane6_OFF (24) + #define DDRDATA1CH0_CR_RXPERBITRANK0_Lane6_WID ( 4) + #define DDRDATA1CH0_CR_RXPERBITRANK0_Lane6_MSK (0x0F000000) + #define DDRDATA1CH0_CR_RXPERBITRANK0_Lane6_MAX (0x0000000F) + #define DDRDATA1CH0_CR_RXPERBITRANK0_Lane7_OFF (28) + #define DDRDATA1CH0_CR_RXPERBITRANK0_Lane7_WID ( 4) + #define DDRDATA1CH0_CR_RXPERBITRANK0_Lane7_MSK (0xF0000000) + #define DDRDATA1CH0_CR_RXPERBITRANK0_Lane7_MAX (0x0000000F) + +#define DDRDATA1CH0_CR_RXPERBITRANK1_REG (0x00000214) + #define DDRDATA1CH0_CR_RXPERBITRANK1_Lane0_OFF ( 0) + #define DDRDATA1CH0_CR_RXPERBITRANK1_Lane0_WID ( 4) + #define DDRDATA1CH0_CR_RXPERBITRANK1_Lane0_MSK (0x0000000F) + #define DDRDATA1CH0_CR_RXPERBITRANK1_Lane0_MAX (0x0000000F) + #define DDRDATA1CH0_CR_RXPERBITRANK1_Lane1_OFF ( 4) + #define DDRDATA1CH0_CR_RXPERBITRANK1_Lane1_WID ( 4) + #define DDRDATA1CH0_CR_RXPERBITRANK1_Lane1_MSK (0x000000F0) + #define DDRDATA1CH0_CR_RXPERBITRANK1_Lane1_MAX (0x0000000F) + #define DDRDATA1CH0_CR_RXPERBITRANK1_Lane2_OFF ( 8) + #define DDRDATA1CH0_CR_RXPERBITRANK1_Lane2_WID ( 4) + #define DDRDATA1CH0_CR_RXPERBITRANK1_Lane2_MSK (0x00000F00) + #define DDRDATA1CH0_CR_RXPERBITRANK1_Lane2_MAX (0x0000000F) + #define DDRDATA1CH0_CR_RXPERBITRANK1_Lane3_OFF (12) + #define DDRDATA1CH0_CR_RXPERBITRANK1_Lane3_WID ( 4) + #define DDRDATA1CH0_CR_RXPERBITRANK1_Lane3_MSK (0x0000F000) + #define DDRDATA1CH0_CR_RXPERBITRANK1_Lane3_MAX (0x0000000F) + #define DDRDATA1CH0_CR_RXPERBITRANK1_Lane4_OFF (16) + #define DDRDATA1CH0_CR_RXPERBITRANK1_Lane4_WID ( 4) + #define DDRDATA1CH0_CR_RXPERBITRANK1_Lane4_MSK (0x000F0000) + #define DDRDATA1CH0_CR_RXPERBITRANK1_Lane4_MAX (0x0000000F) + #define DDRDATA1CH0_CR_RXPERBITRANK1_Lane5_OFF (20) + #define DDRDATA1CH0_CR_RXPERBITRANK1_Lane5_WID ( 4) + #define DDRDATA1CH0_CR_RXPERBITRANK1_Lane5_MSK (0x00F00000) + #define DDRDATA1CH0_CR_RXPERBITRANK1_Lane5_MAX (0x0000000F) + #define DDRDATA1CH0_CR_RXPERBITRANK1_Lane6_OFF (24) + #define DDRDATA1CH0_CR_RXPERBITRANK1_Lane6_WID ( 4) + #define DDRDATA1CH0_CR_RXPERBITRANK1_Lane6_MSK (0x0F000000) + #define DDRDATA1CH0_CR_RXPERBITRANK1_Lane6_MAX (0x0000000F) + #define DDRDATA1CH0_CR_RXPERBITRANK1_Lane7_OFF (28) + #define DDRDATA1CH0_CR_RXPERBITRANK1_Lane7_WID ( 4) + #define DDRDATA1CH0_CR_RXPERBITRANK1_Lane7_MSK (0xF0000000) + #define DDRDATA1CH0_CR_RXPERBITRANK1_Lane7_MAX (0x0000000F) + +#define DDRDATA1CH0_CR_RXPERBITRANK2_REG (0x00000218) + #define DDRDATA1CH0_CR_RXPERBITRANK2_Lane0_OFF ( 0) + #define DDRDATA1CH0_CR_RXPERBITRANK2_Lane0_WID ( 4) + #define DDRDATA1CH0_CR_RXPERBITRANK2_Lane0_MSK (0x0000000F) + #define DDRDATA1CH0_CR_RXPERBITRANK2_Lane0_MAX (0x0000000F) + #define DDRDATA1CH0_CR_RXPERBITRANK2_Lane1_OFF ( 4) + #define DDRDATA1CH0_CR_RXPERBITRANK2_Lane1_WID ( 4) + #define DDRDATA1CH0_CR_RXPERBITRANK2_Lane1_MSK (0x000000F0) + #define DDRDATA1CH0_CR_RXPERBITRANK2_Lane1_MAX (0x0000000F) + #define DDRDATA1CH0_CR_RXPERBITRANK2_Lane2_OFF ( 8) + #define DDRDATA1CH0_CR_RXPERBITRANK2_Lane2_WID ( 4) + #define DDRDATA1CH0_CR_RXPERBITRANK2_Lane2_MSK (0x00000F00) + #define DDRDATA1CH0_CR_RXPERBITRANK2_Lane2_MAX (0x0000000F) + #define DDRDATA1CH0_CR_RXPERBITRANK2_Lane3_OFF (12) + #define DDRDATA1CH0_CR_RXPERBITRANK2_Lane3_WID ( 4) + #define DDRDATA1CH0_CR_RXPERBITRANK2_Lane3_MSK (0x0000F000) + #define DDRDATA1CH0_CR_RXPERBITRANK2_Lane3_MAX (0x0000000F) + #define DDRDATA1CH0_CR_RXPERBITRANK2_Lane4_OFF (16) + #define DDRDATA1CH0_CR_RXPERBITRANK2_Lane4_WID ( 4) + #define DDRDATA1CH0_CR_RXPERBITRANK2_Lane4_MSK (0x000F0000) + #define DDRDATA1CH0_CR_RXPERBITRANK2_Lane4_MAX (0x0000000F) + #define DDRDATA1CH0_CR_RXPERBITRANK2_Lane5_OFF (20) + #define DDRDATA1CH0_CR_RXPERBITRANK2_Lane5_WID ( 4) + #define DDRDATA1CH0_CR_RXPERBITRANK2_Lane5_MSK (0x00F00000) + #define DDRDATA1CH0_CR_RXPERBITRANK2_Lane5_MAX (0x0000000F) + #define DDRDATA1CH0_CR_RXPERBITRANK2_Lane6_OFF (24) + #define DDRDATA1CH0_CR_RXPERBITRANK2_Lane6_WID ( 4) + #define DDRDATA1CH0_CR_RXPERBITRANK2_Lane6_MSK (0x0F000000) + #define DDRDATA1CH0_CR_RXPERBITRANK2_Lane6_MAX (0x0000000F) + #define DDRDATA1CH0_CR_RXPERBITRANK2_Lane7_OFF (28) + #define DDRDATA1CH0_CR_RXPERBITRANK2_Lane7_WID ( 4) + #define DDRDATA1CH0_CR_RXPERBITRANK2_Lane7_MSK (0xF0000000) + #define DDRDATA1CH0_CR_RXPERBITRANK2_Lane7_MAX (0x0000000F) + +#define DDRDATA1CH0_CR_RXPERBITRANK3_REG (0x0000021C) + #define DDRDATA1CH0_CR_RXPERBITRANK3_Lane0_OFF ( 0) + #define DDRDATA1CH0_CR_RXPERBITRANK3_Lane0_WID ( 4) + #define DDRDATA1CH0_CR_RXPERBITRANK3_Lane0_MSK (0x0000000F) + #define DDRDATA1CH0_CR_RXPERBITRANK3_Lane0_MAX (0x0000000F) + #define DDRDATA1CH0_CR_RXPERBITRANK3_Lane1_OFF ( 4) + #define DDRDATA1CH0_CR_RXPERBITRANK3_Lane1_WID ( 4) + #define DDRDATA1CH0_CR_RXPERBITRANK3_Lane1_MSK (0x000000F0) + #define DDRDATA1CH0_CR_RXPERBITRANK3_Lane1_MAX (0x0000000F) + #define DDRDATA1CH0_CR_RXPERBITRANK3_Lane2_OFF ( 8) + #define DDRDATA1CH0_CR_RXPERBITRANK3_Lane2_WID ( 4) + #define DDRDATA1CH0_CR_RXPERBITRANK3_Lane2_MSK (0x00000F00) + #define DDRDATA1CH0_CR_RXPERBITRANK3_Lane2_MAX (0x0000000F) + #define DDRDATA1CH0_CR_RXPERBITRANK3_Lane3_OFF (12) + #define DDRDATA1CH0_CR_RXPERBITRANK3_Lane3_WID ( 4) + #define DDRDATA1CH0_CR_RXPERBITRANK3_Lane3_MSK (0x0000F000) + #define DDRDATA1CH0_CR_RXPERBITRANK3_Lane3_MAX (0x0000000F) + #define DDRDATA1CH0_CR_RXPERBITRANK3_Lane4_OFF (16) + #define DDRDATA1CH0_CR_RXPERBITRANK3_Lane4_WID ( 4) + #define DDRDATA1CH0_CR_RXPERBITRANK3_Lane4_MSK (0x000F0000) + #define DDRDATA1CH0_CR_RXPERBITRANK3_Lane4_MAX (0x0000000F) + #define DDRDATA1CH0_CR_RXPERBITRANK3_Lane5_OFF (20) + #define DDRDATA1CH0_CR_RXPERBITRANK3_Lane5_WID ( 4) + #define DDRDATA1CH0_CR_RXPERBITRANK3_Lane5_MSK (0x00F00000) + #define DDRDATA1CH0_CR_RXPERBITRANK3_Lane5_MAX (0x0000000F) + #define DDRDATA1CH0_CR_RXPERBITRANK3_Lane6_OFF (24) + #define DDRDATA1CH0_CR_RXPERBITRANK3_Lane6_WID ( 4) + #define DDRDATA1CH0_CR_RXPERBITRANK3_Lane6_MSK (0x0F000000) + #define DDRDATA1CH0_CR_RXPERBITRANK3_Lane6_MAX (0x0000000F) + #define DDRDATA1CH0_CR_RXPERBITRANK3_Lane7_OFF (28) + #define DDRDATA1CH0_CR_RXPERBITRANK3_Lane7_WID ( 4) + #define DDRDATA1CH0_CR_RXPERBITRANK3_Lane7_MSK (0xF0000000) + #define DDRDATA1CH0_CR_RXPERBITRANK3_Lane7_MAX (0x0000000F) + +#define DDRDATA1CH0_CR_TXTRAINRANK0_REG (0x00000220) + #define DDRDATA1CH0_CR_TXTRAINRANK0_TxDqDelay_OFF ( 0) + #define DDRDATA1CH0_CR_TXTRAINRANK0_TxDqDelay_WID ( 9) + #define DDRDATA1CH0_CR_TXTRAINRANK0_TxDqDelay_MSK (0x000001FF) + #define DDRDATA1CH0_CR_TXTRAINRANK0_TxDqDelay_MAX (0x000001FF) + #define DDRDATA1CH0_CR_TXTRAINRANK0_TxDqsDelay_OFF ( 9) + #define DDRDATA1CH0_CR_TXTRAINRANK0_TxDqsDelay_WID ( 9) + #define DDRDATA1CH0_CR_TXTRAINRANK0_TxDqsDelay_MSK (0x0003FE00) + #define DDRDATA1CH0_CR_TXTRAINRANK0_TxDqsDelay_MAX (0x000001FF) + #define DDRDATA1CH0_CR_TXTRAINRANK0_Spare0_OFF (18) + #define DDRDATA1CH0_CR_TXTRAINRANK0_Spare0_WID ( 2) + #define DDRDATA1CH0_CR_TXTRAINRANK0_Spare0_MSK (0x000C0000) + #define DDRDATA1CH0_CR_TXTRAINRANK0_Spare0_MAX (0x00000003) + #define DDRDATA1CH0_CR_TXTRAINRANK0_TxEqualization_OFF (20) + #define DDRDATA1CH0_CR_TXTRAINRANK0_TxEqualization_WID ( 6) + #define DDRDATA1CH0_CR_TXTRAINRANK0_TxEqualization_MSK (0x03F00000) + #define DDRDATA1CH0_CR_TXTRAINRANK0_TxEqualization_MAX (0x0000003F) + #define DDRDATA1CH0_CR_TXTRAINRANK0_Spare1_OFF (26) + #define DDRDATA1CH0_CR_TXTRAINRANK0_Spare1_WID ( 6) + #define DDRDATA1CH0_CR_TXTRAINRANK0_Spare1_MSK (0xFC000000) + #define DDRDATA1CH0_CR_TXTRAINRANK0_Spare1_MAX (0x0000003F) + +#define DDRDATA1CH0_CR_TXTRAINRANK1_REG (0x00000224) + #define DDRDATA1CH0_CR_TXTRAINRANK1_TxDqDelay_OFF ( 0) + #define DDRDATA1CH0_CR_TXTRAINRANK1_TxDqDelay_WID ( 9) + #define DDRDATA1CH0_CR_TXTRAINRANK1_TxDqDelay_MSK (0x000001FF) + #define DDRDATA1CH0_CR_TXTRAINRANK1_TxDqDelay_MAX (0x000001FF) + #define DDRDATA1CH0_CR_TXTRAINRANK1_TxDqsDelay_OFF ( 9) + #define DDRDATA1CH0_CR_TXTRAINRANK1_TxDqsDelay_WID ( 9) + #define DDRDATA1CH0_CR_TXTRAINRANK1_TxDqsDelay_MSK (0x0003FE00) + #define DDRDATA1CH0_CR_TXTRAINRANK1_TxDqsDelay_MAX (0x000001FF) + #define DDRDATA1CH0_CR_TXTRAINRANK1_Spare0_OFF (18) + #define DDRDATA1CH0_CR_TXTRAINRANK1_Spare0_WID ( 2) + #define DDRDATA1CH0_CR_TXTRAINRANK1_Spare0_MSK (0x000C0000) + #define DDRDATA1CH0_CR_TXTRAINRANK1_Spare0_MAX (0x00000003) + #define DDRDATA1CH0_CR_TXTRAINRANK1_TxEqualization_OFF (20) + #define DDRDATA1CH0_CR_TXTRAINRANK1_TxEqualization_WID ( 6) + #define DDRDATA1CH0_CR_TXTRAINRANK1_TxEqualization_MSK (0x03F00000) + #define DDRDATA1CH0_CR_TXTRAINRANK1_TxEqualization_MAX (0x0000003F) + #define DDRDATA1CH0_CR_TXTRAINRANK1_Spare1_OFF (26) + #define DDRDATA1CH0_CR_TXTRAINRANK1_Spare1_WID ( 6) + #define DDRDATA1CH0_CR_TXTRAINRANK1_Spare1_MSK (0xFC000000) + #define DDRDATA1CH0_CR_TXTRAINRANK1_Spare1_MAX (0x0000003F) + +#define DDRDATA1CH0_CR_TXTRAINRANK2_REG (0x00000228) + #define DDRDATA1CH0_CR_TXTRAINRANK2_TxDqDelay_OFF ( 0) + #define DDRDATA1CH0_CR_TXTRAINRANK2_TxDqDelay_WID ( 9) + #define DDRDATA1CH0_CR_TXTRAINRANK2_TxDqDelay_MSK (0x000001FF) + #define DDRDATA1CH0_CR_TXTRAINRANK2_TxDqDelay_MAX (0x000001FF) + #define DDRDATA1CH0_CR_TXTRAINRANK2_TxDqsDelay_OFF ( 9) + #define DDRDATA1CH0_CR_TXTRAINRANK2_TxDqsDelay_WID ( 9) + #define DDRDATA1CH0_CR_TXTRAINRANK2_TxDqsDelay_MSK (0x0003FE00) + #define DDRDATA1CH0_CR_TXTRAINRANK2_TxDqsDelay_MAX (0x000001FF) + #define DDRDATA1CH0_CR_TXTRAINRANK2_Spare0_OFF (18) + #define DDRDATA1CH0_CR_TXTRAINRANK2_Spare0_WID ( 2) + #define DDRDATA1CH0_CR_TXTRAINRANK2_Spare0_MSK (0x000C0000) + #define DDRDATA1CH0_CR_TXTRAINRANK2_Spare0_MAX (0x00000003) + #define DDRDATA1CH0_CR_TXTRAINRANK2_TxEqualization_OFF (20) + #define DDRDATA1CH0_CR_TXTRAINRANK2_TxEqualization_WID ( 6) + #define DDRDATA1CH0_CR_TXTRAINRANK2_TxEqualization_MSK (0x03F00000) + #define DDRDATA1CH0_CR_TXTRAINRANK2_TxEqualization_MAX (0x0000003F) + #define DDRDATA1CH0_CR_TXTRAINRANK2_Spare1_OFF (26) + #define DDRDATA1CH0_CR_TXTRAINRANK2_Spare1_WID ( 6) + #define DDRDATA1CH0_CR_TXTRAINRANK2_Spare1_MSK (0xFC000000) + #define DDRDATA1CH0_CR_TXTRAINRANK2_Spare1_MAX (0x0000003F) + +#define DDRDATA1CH0_CR_TXTRAINRANK3_REG (0x0000022C) + #define DDRDATA1CH0_CR_TXTRAINRANK3_TxDqDelay_OFF ( 0) + #define DDRDATA1CH0_CR_TXTRAINRANK3_TxDqDelay_WID ( 9) + #define DDRDATA1CH0_CR_TXTRAINRANK3_TxDqDelay_MSK (0x000001FF) + #define DDRDATA1CH0_CR_TXTRAINRANK3_TxDqDelay_MAX (0x000001FF) + #define DDRDATA1CH0_CR_TXTRAINRANK3_TxDqsDelay_OFF ( 9) + #define DDRDATA1CH0_CR_TXTRAINRANK3_TxDqsDelay_WID ( 9) + #define DDRDATA1CH0_CR_TXTRAINRANK3_TxDqsDelay_MSK (0x0003FE00) + #define DDRDATA1CH0_CR_TXTRAINRANK3_TxDqsDelay_MAX (0x000001FF) + #define DDRDATA1CH0_CR_TXTRAINRANK3_Spare0_OFF (18) + #define DDRDATA1CH0_CR_TXTRAINRANK3_Spare0_WID ( 2) + #define DDRDATA1CH0_CR_TXTRAINRANK3_Spare0_MSK (0x000C0000) + #define DDRDATA1CH0_CR_TXTRAINRANK3_Spare0_MAX (0x00000003) + #define DDRDATA1CH0_CR_TXTRAINRANK3_TxEqualization_OFF (20) + #define DDRDATA1CH0_CR_TXTRAINRANK3_TxEqualization_WID ( 6) + #define DDRDATA1CH0_CR_TXTRAINRANK3_TxEqualization_MSK (0x03F00000) + #define DDRDATA1CH0_CR_TXTRAINRANK3_TxEqualization_MAX (0x0000003F) + #define DDRDATA1CH0_CR_TXTRAINRANK3_Spare1_OFF (26) + #define DDRDATA1CH0_CR_TXTRAINRANK3_Spare1_WID ( 6) + #define DDRDATA1CH0_CR_TXTRAINRANK3_Spare1_MSK (0xFC000000) + #define DDRDATA1CH0_CR_TXTRAINRANK3_Spare1_MAX (0x0000003F) + +#define DDRDATA1CH0_CR_TXPERBITRANK0_REG (0x00000230) + #define DDRDATA1CH0_CR_TXPERBITRANK0_Lane0_OFF ( 0) + #define DDRDATA1CH0_CR_TXPERBITRANK0_Lane0_WID ( 4) + #define DDRDATA1CH0_CR_TXPERBITRANK0_Lane0_MSK (0x0000000F) + #define DDRDATA1CH0_CR_TXPERBITRANK0_Lane0_MAX (0x0000000F) + #define DDRDATA1CH0_CR_TXPERBITRANK0_Lane1_OFF ( 4) + #define DDRDATA1CH0_CR_TXPERBITRANK0_Lane1_WID ( 4) + #define DDRDATA1CH0_CR_TXPERBITRANK0_Lane1_MSK (0x000000F0) + #define DDRDATA1CH0_CR_TXPERBITRANK0_Lane1_MAX (0x0000000F) + #define DDRDATA1CH0_CR_TXPERBITRANK0_Lane2_OFF ( 8) + #define DDRDATA1CH0_CR_TXPERBITRANK0_Lane2_WID ( 4) + #define DDRDATA1CH0_CR_TXPERBITRANK0_Lane2_MSK (0x00000F00) + #define DDRDATA1CH0_CR_TXPERBITRANK0_Lane2_MAX (0x0000000F) + #define DDRDATA1CH0_CR_TXPERBITRANK0_Lane3_OFF (12) + #define DDRDATA1CH0_CR_TXPERBITRANK0_Lane3_WID ( 4) + #define DDRDATA1CH0_CR_TXPERBITRANK0_Lane3_MSK (0x0000F000) + #define DDRDATA1CH0_CR_TXPERBITRANK0_Lane3_MAX (0x0000000F) + #define DDRDATA1CH0_CR_TXPERBITRANK0_Lane4_OFF (16) + #define DDRDATA1CH0_CR_TXPERBITRANK0_Lane4_WID ( 4) + #define DDRDATA1CH0_CR_TXPERBITRANK0_Lane4_MSK (0x000F0000) + #define DDRDATA1CH0_CR_TXPERBITRANK0_Lane4_MAX (0x0000000F) + #define DDRDATA1CH0_CR_TXPERBITRANK0_Lane5_OFF (20) + #define DDRDATA1CH0_CR_TXPERBITRANK0_Lane5_WID ( 4) + #define DDRDATA1CH0_CR_TXPERBITRANK0_Lane5_MSK (0x00F00000) + #define DDRDATA1CH0_CR_TXPERBITRANK0_Lane5_MAX (0x0000000F) + #define DDRDATA1CH0_CR_TXPERBITRANK0_Lane6_OFF (24) + #define DDRDATA1CH0_CR_TXPERBITRANK0_Lane6_WID ( 4) + #define DDRDATA1CH0_CR_TXPERBITRANK0_Lane6_MSK (0x0F000000) + #define DDRDATA1CH0_CR_TXPERBITRANK0_Lane6_MAX (0x0000000F) + #define DDRDATA1CH0_CR_TXPERBITRANK0_Lane7_OFF (28) + #define DDRDATA1CH0_CR_TXPERBITRANK0_Lane7_WID ( 4) + #define DDRDATA1CH0_CR_TXPERBITRANK0_Lane7_MSK (0xF0000000) + #define DDRDATA1CH0_CR_TXPERBITRANK0_Lane7_MAX (0x0000000F) + +#define DDRDATA1CH0_CR_TXPERBITRANK1_REG (0x00000234) + #define DDRDATA1CH0_CR_TXPERBITRANK1_Lane0_OFF ( 0) + #define DDRDATA1CH0_CR_TXPERBITRANK1_Lane0_WID ( 4) + #define DDRDATA1CH0_CR_TXPERBITRANK1_Lane0_MSK (0x0000000F) + #define DDRDATA1CH0_CR_TXPERBITRANK1_Lane0_MAX (0x0000000F) + #define DDRDATA1CH0_CR_TXPERBITRANK1_Lane1_OFF ( 4) + #define DDRDATA1CH0_CR_TXPERBITRANK1_Lane1_WID ( 4) + #define DDRDATA1CH0_CR_TXPERBITRANK1_Lane1_MSK (0x000000F0) + #define DDRDATA1CH0_CR_TXPERBITRANK1_Lane1_MAX (0x0000000F) + #define DDRDATA1CH0_CR_TXPERBITRANK1_Lane2_OFF ( 8) + #define DDRDATA1CH0_CR_TXPERBITRANK1_Lane2_WID ( 4) + #define DDRDATA1CH0_CR_TXPERBITRANK1_Lane2_MSK (0x00000F00) + #define DDRDATA1CH0_CR_TXPERBITRANK1_Lane2_MAX (0x0000000F) + #define DDRDATA1CH0_CR_TXPERBITRANK1_Lane3_OFF (12) + #define DDRDATA1CH0_CR_TXPERBITRANK1_Lane3_WID ( 4) + #define DDRDATA1CH0_CR_TXPERBITRANK1_Lane3_MSK (0x0000F000) + #define DDRDATA1CH0_CR_TXPERBITRANK1_Lane3_MAX (0x0000000F) + #define DDRDATA1CH0_CR_TXPERBITRANK1_Lane4_OFF (16) + #define DDRDATA1CH0_CR_TXPERBITRANK1_Lane4_WID ( 4) + #define DDRDATA1CH0_CR_TXPERBITRANK1_Lane4_MSK (0x000F0000) + #define DDRDATA1CH0_CR_TXPERBITRANK1_Lane4_MAX (0x0000000F) + #define DDRDATA1CH0_CR_TXPERBITRANK1_Lane5_OFF (20) + #define DDRDATA1CH0_CR_TXPERBITRANK1_Lane5_WID ( 4) + #define DDRDATA1CH0_CR_TXPERBITRANK1_Lane5_MSK (0x00F00000) + #define DDRDATA1CH0_CR_TXPERBITRANK1_Lane5_MAX (0x0000000F) + #define DDRDATA1CH0_CR_TXPERBITRANK1_Lane6_OFF (24) + #define DDRDATA1CH0_CR_TXPERBITRANK1_Lane6_WID ( 4) + #define DDRDATA1CH0_CR_TXPERBITRANK1_Lane6_MSK (0x0F000000) + #define DDRDATA1CH0_CR_TXPERBITRANK1_Lane6_MAX (0x0000000F) + #define DDRDATA1CH0_CR_TXPERBITRANK1_Lane7_OFF (28) + #define DDRDATA1CH0_CR_TXPERBITRANK1_Lane7_WID ( 4) + #define DDRDATA1CH0_CR_TXPERBITRANK1_Lane7_MSK (0xF0000000) + #define DDRDATA1CH0_CR_TXPERBITRANK1_Lane7_MAX (0x0000000F) + +#define DDRDATA1CH0_CR_TXPERBITRANK2_REG (0x00000238) + #define DDRDATA1CH0_CR_TXPERBITRANK2_Lane0_OFF ( 0) + #define DDRDATA1CH0_CR_TXPERBITRANK2_Lane0_WID ( 4) + #define DDRDATA1CH0_CR_TXPERBITRANK2_Lane0_MSK (0x0000000F) + #define DDRDATA1CH0_CR_TXPERBITRANK2_Lane0_MAX (0x0000000F) + #define DDRDATA1CH0_CR_TXPERBITRANK2_Lane1_OFF ( 4) + #define DDRDATA1CH0_CR_TXPERBITRANK2_Lane1_WID ( 4) + #define DDRDATA1CH0_CR_TXPERBITRANK2_Lane1_MSK (0x000000F0) + #define DDRDATA1CH0_CR_TXPERBITRANK2_Lane1_MAX (0x0000000F) + #define DDRDATA1CH0_CR_TXPERBITRANK2_Lane2_OFF ( 8) + #define DDRDATA1CH0_CR_TXPERBITRANK2_Lane2_WID ( 4) + #define DDRDATA1CH0_CR_TXPERBITRANK2_Lane2_MSK (0x00000F00) + #define DDRDATA1CH0_CR_TXPERBITRANK2_Lane2_MAX (0x0000000F) + #define DDRDATA1CH0_CR_TXPERBITRANK2_Lane3_OFF (12) + #define DDRDATA1CH0_CR_TXPERBITRANK2_Lane3_WID ( 4) + #define DDRDATA1CH0_CR_TXPERBITRANK2_Lane3_MSK (0x0000F000) + #define DDRDATA1CH0_CR_TXPERBITRANK2_Lane3_MAX (0x0000000F) + #define DDRDATA1CH0_CR_TXPERBITRANK2_Lane4_OFF (16) + #define DDRDATA1CH0_CR_TXPERBITRANK2_Lane4_WID ( 4) + #define DDRDATA1CH0_CR_TXPERBITRANK2_Lane4_MSK (0x000F0000) + #define DDRDATA1CH0_CR_TXPERBITRANK2_Lane4_MAX (0x0000000F) + #define DDRDATA1CH0_CR_TXPERBITRANK2_Lane5_OFF (20) + #define DDRDATA1CH0_CR_TXPERBITRANK2_Lane5_WID ( 4) + #define DDRDATA1CH0_CR_TXPERBITRANK2_Lane5_MSK (0x00F00000) + #define DDRDATA1CH0_CR_TXPERBITRANK2_Lane5_MAX (0x0000000F) + #define DDRDATA1CH0_CR_TXPERBITRANK2_Lane6_OFF (24) + #define DDRDATA1CH0_CR_TXPERBITRANK2_Lane6_WID ( 4) + #define DDRDATA1CH0_CR_TXPERBITRANK2_Lane6_MSK (0x0F000000) + #define DDRDATA1CH0_CR_TXPERBITRANK2_Lane6_MAX (0x0000000F) + #define DDRDATA1CH0_CR_TXPERBITRANK2_Lane7_OFF (28) + #define DDRDATA1CH0_CR_TXPERBITRANK2_Lane7_WID ( 4) + #define DDRDATA1CH0_CR_TXPERBITRANK2_Lane7_MSK (0xF0000000) + #define DDRDATA1CH0_CR_TXPERBITRANK2_Lane7_MAX (0x0000000F) + +#define DDRDATA1CH0_CR_TXPERBITRANK3_REG (0x0000023C) + #define DDRDATA1CH0_CR_TXPERBITRANK3_Lane0_OFF ( 0) + #define DDRDATA1CH0_CR_TXPERBITRANK3_Lane0_WID ( 4) + #define DDRDATA1CH0_CR_TXPERBITRANK3_Lane0_MSK (0x0000000F) + #define DDRDATA1CH0_CR_TXPERBITRANK3_Lane0_MAX (0x0000000F) + #define DDRDATA1CH0_CR_TXPERBITRANK3_Lane1_OFF ( 4) + #define DDRDATA1CH0_CR_TXPERBITRANK3_Lane1_WID ( 4) + #define DDRDATA1CH0_CR_TXPERBITRANK3_Lane1_MSK (0x000000F0) + #define DDRDATA1CH0_CR_TXPERBITRANK3_Lane1_MAX (0x0000000F) + #define DDRDATA1CH0_CR_TXPERBITRANK3_Lane2_OFF ( 8) + #define DDRDATA1CH0_CR_TXPERBITRANK3_Lane2_WID ( 4) + #define DDRDATA1CH0_CR_TXPERBITRANK3_Lane2_MSK (0x00000F00) + #define DDRDATA1CH0_CR_TXPERBITRANK3_Lane2_MAX (0x0000000F) + #define DDRDATA1CH0_CR_TXPERBITRANK3_Lane3_OFF (12) + #define DDRDATA1CH0_CR_TXPERBITRANK3_Lane3_WID ( 4) + #define DDRDATA1CH0_CR_TXPERBITRANK3_Lane3_MSK (0x0000F000) + #define DDRDATA1CH0_CR_TXPERBITRANK3_Lane3_MAX (0x0000000F) + #define DDRDATA1CH0_CR_TXPERBITRANK3_Lane4_OFF (16) + #define DDRDATA1CH0_CR_TXPERBITRANK3_Lane4_WID ( 4) + #define DDRDATA1CH0_CR_TXPERBITRANK3_Lane4_MSK (0x000F0000) + #define DDRDATA1CH0_CR_TXPERBITRANK3_Lane4_MAX (0x0000000F) + #define DDRDATA1CH0_CR_TXPERBITRANK3_Lane5_OFF (20) + #define DDRDATA1CH0_CR_TXPERBITRANK3_Lane5_WID ( 4) + #define DDRDATA1CH0_CR_TXPERBITRANK3_Lane5_MSK (0x00F00000) + #define DDRDATA1CH0_CR_TXPERBITRANK3_Lane5_MAX (0x0000000F) + #define DDRDATA1CH0_CR_TXPERBITRANK3_Lane6_OFF (24) + #define DDRDATA1CH0_CR_TXPERBITRANK3_Lane6_WID ( 4) + #define DDRDATA1CH0_CR_TXPERBITRANK3_Lane6_MSK (0x0F000000) + #define DDRDATA1CH0_CR_TXPERBITRANK3_Lane6_MAX (0x0000000F) + #define DDRDATA1CH0_CR_TXPERBITRANK3_Lane7_OFF (28) + #define DDRDATA1CH0_CR_TXPERBITRANK3_Lane7_WID ( 4) + #define DDRDATA1CH0_CR_TXPERBITRANK3_Lane7_MSK (0xF0000000) + #define DDRDATA1CH0_CR_TXPERBITRANK3_Lane7_MAX (0x0000000F) + +#define DDRDATA1CH0_CR_RCOMPDATA0_REG (0x00000240) + #define DDRDATA1CH0_CR_RCOMPDATA0_RcompDrvUp_OFF ( 0) + #define DDRDATA1CH0_CR_RCOMPDATA0_RcompDrvUp_WID ( 6) + #define DDRDATA1CH0_CR_RCOMPDATA0_RcompDrvUp_MSK (0x0000003F) + #define DDRDATA1CH0_CR_RCOMPDATA0_RcompDrvUp_MAX (0x0000003F) + #define DDRDATA1CH0_CR_RCOMPDATA0_Spare0_OFF ( 6) + #define DDRDATA1CH0_CR_RCOMPDATA0_Spare0_WID ( 3) + #define DDRDATA1CH0_CR_RCOMPDATA0_Spare0_MSK (0x000001C0) + #define DDRDATA1CH0_CR_RCOMPDATA0_Spare0_MAX (0x00000007) + #define DDRDATA1CH0_CR_RCOMPDATA0_RcompDrvDown_OFF ( 9) + #define DDRDATA1CH0_CR_RCOMPDATA0_RcompDrvDown_WID ( 6) + #define DDRDATA1CH0_CR_RCOMPDATA0_RcompDrvDown_MSK (0x00007E00) + #define DDRDATA1CH0_CR_RCOMPDATA0_RcompDrvDown_MAX (0x0000003F) + #define DDRDATA1CH0_CR_RCOMPDATA0_VTComp_OFF (15) + #define DDRDATA1CH0_CR_RCOMPDATA0_VTComp_WID ( 5) + #define DDRDATA1CH0_CR_RCOMPDATA0_VTComp_MSK (0x000F8000) + #define DDRDATA1CH0_CR_RCOMPDATA0_VTComp_MAX (0x0000001F) + #define DDRDATA1CH0_CR_RCOMPDATA0_TcoComp_OFF (20) + #define DDRDATA1CH0_CR_RCOMPDATA0_TcoComp_WID ( 6) + #define DDRDATA1CH0_CR_RCOMPDATA0_TcoComp_MSK (0x03F00000) + #define DDRDATA1CH0_CR_RCOMPDATA0_TcoComp_MAX (0x0000003F) + #define DDRDATA1CH0_CR_RCOMPDATA0_SlewRateComp_OFF (26) + #define DDRDATA1CH0_CR_RCOMPDATA0_SlewRateComp_WID ( 5) + #define DDRDATA1CH0_CR_RCOMPDATA0_SlewRateComp_MSK (0x7C000000) + #define DDRDATA1CH0_CR_RCOMPDATA0_SlewRateComp_MAX (0x0000001F) + #define DDRDATA1CH0_CR_RCOMPDATA0_Spare2_OFF (31) + #define DDRDATA1CH0_CR_RCOMPDATA0_Spare2_WID ( 1) + #define DDRDATA1CH0_CR_RCOMPDATA0_Spare2_MSK (0x80000000) + #define DDRDATA1CH0_CR_RCOMPDATA0_Spare2_MAX (0x00000001) + +#define DDRDATA1CH0_CR_RCOMPDATA1_REG (0x00000244) + #define DDRDATA1CH0_CR_RCOMPDATA1_RcompOdtUp_OFF ( 0) + #define DDRDATA1CH0_CR_RCOMPDATA1_RcompOdtUp_WID ( 6) + #define DDRDATA1CH0_CR_RCOMPDATA1_RcompOdtUp_MSK (0x0000003F) + #define DDRDATA1CH0_CR_RCOMPDATA1_RcompOdtUp_MAX (0x0000003F) + #define DDRDATA1CH0_CR_RCOMPDATA1_Spare0_OFF ( 6) + #define DDRDATA1CH0_CR_RCOMPDATA1_Spare0_WID ( 3) + #define DDRDATA1CH0_CR_RCOMPDATA1_Spare0_MSK (0x000001C0) + #define DDRDATA1CH0_CR_RCOMPDATA1_Spare0_MAX (0x00000007) + #define DDRDATA1CH0_CR_RCOMPDATA1_RcompOdtDown_OFF ( 9) + #define DDRDATA1CH0_CR_RCOMPDATA1_RcompOdtDown_WID ( 6) + #define DDRDATA1CH0_CR_RCOMPDATA1_RcompOdtDown_MSK (0x00007E00) + #define DDRDATA1CH0_CR_RCOMPDATA1_RcompOdtDown_MAX (0x0000003F) + #define DDRDATA1CH0_CR_RCOMPDATA1_Spare1_OFF (15) + #define DDRDATA1CH0_CR_RCOMPDATA1_Spare1_WID ( 1) + #define DDRDATA1CH0_CR_RCOMPDATA1_Spare1_MSK (0x00008000) + #define DDRDATA1CH0_CR_RCOMPDATA1_Spare1_MAX (0x00000001) + #define DDRDATA1CH0_CR_RCOMPDATA1_PanicDrvDn_OFF (16) + #define DDRDATA1CH0_CR_RCOMPDATA1_PanicDrvDn_WID ( 6) + #define DDRDATA1CH0_CR_RCOMPDATA1_PanicDrvDn_MSK (0x003F0000) + #define DDRDATA1CH0_CR_RCOMPDATA1_PanicDrvDn_MAX (0x0000003F) + #define DDRDATA1CH0_CR_RCOMPDATA1_PanicDrvUp_OFF (22) + #define DDRDATA1CH0_CR_RCOMPDATA1_PanicDrvUp_WID ( 6) + #define DDRDATA1CH0_CR_RCOMPDATA1_PanicDrvUp_MSK (0x0FC00000) + #define DDRDATA1CH0_CR_RCOMPDATA1_PanicDrvUp_MAX (0x0000003F) + #define DDRDATA1CH0_CR_RCOMPDATA1_LevelShifterComp_OFF (28) + #define DDRDATA1CH0_CR_RCOMPDATA1_LevelShifterComp_WID ( 3) + #define DDRDATA1CH0_CR_RCOMPDATA1_LevelShifterComp_MSK (0x70000000) + #define DDRDATA1CH0_CR_RCOMPDATA1_LevelShifterComp_MAX (0x00000007) + #define DDRDATA1CH0_CR_RCOMPDATA1_Spare2_OFF (31) + #define DDRDATA1CH0_CR_RCOMPDATA1_Spare2_WID ( 1) + #define DDRDATA1CH0_CR_RCOMPDATA1_Spare2_MSK (0x80000000) + #define DDRDATA1CH0_CR_RCOMPDATA1_Spare2_MAX (0x00000001) + +#define DDRDATA1CH0_CR_TXXTALK_REG (0x00000248) + #define DDRDATA1CH0_CR_TXXTALK_Lane0_OFF ( 0) + #define DDRDATA1CH0_CR_TXXTALK_Lane0_WID ( 4) + #define DDRDATA1CH0_CR_TXXTALK_Lane0_MSK (0x0000000F) + #define DDRDATA1CH0_CR_TXXTALK_Lane0_MAX (0x0000000F) + #define DDRDATA1CH0_CR_TXXTALK_Lane1_OFF ( 4) + #define DDRDATA1CH0_CR_TXXTALK_Lane1_WID ( 4) + #define DDRDATA1CH0_CR_TXXTALK_Lane1_MSK (0x000000F0) + #define DDRDATA1CH0_CR_TXXTALK_Lane1_MAX (0x0000000F) + #define DDRDATA1CH0_CR_TXXTALK_Lane2_OFF ( 8) + #define DDRDATA1CH0_CR_TXXTALK_Lane2_WID ( 4) + #define DDRDATA1CH0_CR_TXXTALK_Lane2_MSK (0x00000F00) + #define DDRDATA1CH0_CR_TXXTALK_Lane2_MAX (0x0000000F) + #define DDRDATA1CH0_CR_TXXTALK_Lane3_OFF (12) + #define DDRDATA1CH0_CR_TXXTALK_Lane3_WID ( 4) + #define DDRDATA1CH0_CR_TXXTALK_Lane3_MSK (0x0000F000) + #define DDRDATA1CH0_CR_TXXTALK_Lane3_MAX (0x0000000F) + #define DDRDATA1CH0_CR_TXXTALK_Lane4_OFF (16) + #define DDRDATA1CH0_CR_TXXTALK_Lane4_WID ( 4) + #define DDRDATA1CH0_CR_TXXTALK_Lane4_MSK (0x000F0000) + #define DDRDATA1CH0_CR_TXXTALK_Lane4_MAX (0x0000000F) + #define DDRDATA1CH0_CR_TXXTALK_Lane5_OFF (20) + #define DDRDATA1CH0_CR_TXXTALK_Lane5_WID ( 4) + #define DDRDATA1CH0_CR_TXXTALK_Lane5_MSK (0x00F00000) + #define DDRDATA1CH0_CR_TXXTALK_Lane5_MAX (0x0000000F) + #define DDRDATA1CH0_CR_TXXTALK_Lane6_OFF (24) + #define DDRDATA1CH0_CR_TXXTALK_Lane6_WID ( 4) + #define DDRDATA1CH0_CR_TXXTALK_Lane6_MSK (0x0F000000) + #define DDRDATA1CH0_CR_TXXTALK_Lane6_MAX (0x0000000F) + #define DDRDATA1CH0_CR_TXXTALK_Lane7_OFF (28) + #define DDRDATA1CH0_CR_TXXTALK_Lane7_WID ( 4) + #define DDRDATA1CH0_CR_TXXTALK_Lane7_MSK (0xF0000000) + #define DDRDATA1CH0_CR_TXXTALK_Lane7_MAX (0x0000000F) + +#define DDRDATA1CH0_CR_RXOFFSETVDQ_REG (0x0000024C) + #define DDRDATA1CH0_CR_RXOFFSETVDQ_Lane0_OFF ( 0) + #define DDRDATA1CH0_CR_RXOFFSETVDQ_Lane0_WID ( 4) + #define DDRDATA1CH0_CR_RXOFFSETVDQ_Lane0_MSK (0x0000000F) + #define DDRDATA1CH0_CR_RXOFFSETVDQ_Lane0_MAX (0x0000000F) + #define DDRDATA1CH0_CR_RXOFFSETVDQ_Lane1_OFF ( 4) + #define DDRDATA1CH0_CR_RXOFFSETVDQ_Lane1_WID ( 4) + #define DDRDATA1CH0_CR_RXOFFSETVDQ_Lane1_MSK (0x000000F0) + #define DDRDATA1CH0_CR_RXOFFSETVDQ_Lane1_MAX (0x0000000F) + #define DDRDATA1CH0_CR_RXOFFSETVDQ_Lane2_OFF ( 8) + #define DDRDATA1CH0_CR_RXOFFSETVDQ_Lane2_WID ( 4) + #define DDRDATA1CH0_CR_RXOFFSETVDQ_Lane2_MSK (0x00000F00) + #define DDRDATA1CH0_CR_RXOFFSETVDQ_Lane2_MAX (0x0000000F) + #define DDRDATA1CH0_CR_RXOFFSETVDQ_Lane3_OFF (12) + #define DDRDATA1CH0_CR_RXOFFSETVDQ_Lane3_WID ( 4) + #define DDRDATA1CH0_CR_RXOFFSETVDQ_Lane3_MSK (0x0000F000) + #define DDRDATA1CH0_CR_RXOFFSETVDQ_Lane3_MAX (0x0000000F) + #define DDRDATA1CH0_CR_RXOFFSETVDQ_Lane4_OFF (16) + #define DDRDATA1CH0_CR_RXOFFSETVDQ_Lane4_WID ( 4) + #define DDRDATA1CH0_CR_RXOFFSETVDQ_Lane4_MSK (0x000F0000) + #define DDRDATA1CH0_CR_RXOFFSETVDQ_Lane4_MAX (0x0000000F) + #define DDRDATA1CH0_CR_RXOFFSETVDQ_Lane5_OFF (20) + #define DDRDATA1CH0_CR_RXOFFSETVDQ_Lane5_WID ( 4) + #define DDRDATA1CH0_CR_RXOFFSETVDQ_Lane5_MSK (0x00F00000) + #define DDRDATA1CH0_CR_RXOFFSETVDQ_Lane5_MAX (0x0000000F) + #define DDRDATA1CH0_CR_RXOFFSETVDQ_Lane6_OFF (24) + #define DDRDATA1CH0_CR_RXOFFSETVDQ_Lane6_WID ( 4) + #define DDRDATA1CH0_CR_RXOFFSETVDQ_Lane6_MSK (0x0F000000) + #define DDRDATA1CH0_CR_RXOFFSETVDQ_Lane6_MAX (0x0000000F) + #define DDRDATA1CH0_CR_RXOFFSETVDQ_Lane7_OFF (28) + #define DDRDATA1CH0_CR_RXOFFSETVDQ_Lane7_WID ( 4) + #define DDRDATA1CH0_CR_RXOFFSETVDQ_Lane7_MSK (0xF0000000) + #define DDRDATA1CH0_CR_RXOFFSETVDQ_Lane7_MAX (0x0000000F) + +#define DDRDATA1CH0_CR_DDRDATARESERVED_REG (0x00000250) + #define DDRDATA1CH0_CR_DDRDATARESERVED_Spare_OFF ( 0) + #define DDRDATA1CH0_CR_DDRDATARESERVED_Spare_WID (32) + #define DDRDATA1CH0_CR_DDRDATARESERVED_Spare_MSK (0xFFFFFFFF) + #define DDRDATA1CH0_CR_DDRDATARESERVED_Spare_MAX (0xFFFFFFFF) + +#define DDRDATA1CH0_CR_DATATRAINFEEDBACK_REG (0x00000254) + #define DDRDATA1CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_OFF ( 0) + #define DDRDATA1CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_WID ( 9) + #define DDRDATA1CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_MSK (0x000001FF) + #define DDRDATA1CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_MAX (0x000001FF) + #define DDRDATA1CH0_CR_DATATRAINFEEDBACK_Spare_OFF ( 9) + #define DDRDATA1CH0_CR_DATATRAINFEEDBACK_Spare_WID (23) + #define DDRDATA1CH0_CR_DATATRAINFEEDBACK_Spare_MSK (0xFFFFFE00) + #define DDRDATA1CH0_CR_DATATRAINFEEDBACK_Spare_MAX (0x007FFFFF) + +#define DDRDATA1CH0_CR_DLLPITESTANDADC_REG (0x00000258) + #define DDRDATA1CH0_CR_DLLPITESTANDADC_RunTest_OFF ( 0) + #define DDRDATA1CH0_CR_DLLPITESTANDADC_RunTest_WID ( 1) + #define DDRDATA1CH0_CR_DLLPITESTANDADC_RunTest_MSK (0x00000001) + #define DDRDATA1CH0_CR_DLLPITESTANDADC_RunTest_MAX (0x00000001) + #define DDRDATA1CH0_CR_DLLPITESTANDADC_RunTest_DEF (0x00000000) + #define DDRDATA1CH0_CR_DLLPITESTANDADC_Load_OFF ( 1) + #define DDRDATA1CH0_CR_DLLPITESTANDADC_Load_WID ( 1) + #define DDRDATA1CH0_CR_DLLPITESTANDADC_Load_MSK (0x00000002) + #define DDRDATA1CH0_CR_DLLPITESTANDADC_Load_MAX (0x00000001) + #define DDRDATA1CH0_CR_DLLPITESTANDADC_Load_DEF (0x00000000) + #define DDRDATA1CH0_CR_DLLPITESTANDADC_ModeHVM_OFF ( 2) + #define DDRDATA1CH0_CR_DLLPITESTANDADC_ModeHVM_WID ( 1) + #define DDRDATA1CH0_CR_DLLPITESTANDADC_ModeHVM_MSK (0x00000004) + #define DDRDATA1CH0_CR_DLLPITESTANDADC_ModeHVM_MAX (0x00000001) + #define DDRDATA1CH0_CR_DLLPITESTANDADC_ModeHVM_DEF (0x00000000) + #define DDRDATA1CH0_CR_DLLPITESTANDADC_ModeDV_OFF ( 3) + #define DDRDATA1CH0_CR_DLLPITESTANDADC_ModeDV_WID ( 1) + #define DDRDATA1CH0_CR_DLLPITESTANDADC_ModeDV_MSK (0x00000008) + #define DDRDATA1CH0_CR_DLLPITESTANDADC_ModeDV_MAX (0x00000001) + #define DDRDATA1CH0_CR_DLLPITESTANDADC_ModeDV_DEF (0x00000000) + #define DDRDATA1CH0_CR_DLLPITESTANDADC_ModeADC_OFF ( 4) + #define DDRDATA1CH0_CR_DLLPITESTANDADC_ModeADC_WID ( 1) + #define DDRDATA1CH0_CR_DLLPITESTANDADC_ModeADC_MSK (0x00000010) + #define DDRDATA1CH0_CR_DLLPITESTANDADC_ModeADC_MAX (0x00000001) + #define DDRDATA1CH0_CR_DLLPITESTANDADC_ModeADC_DEF (0x00000000) + #define DDRDATA1CH0_CR_DLLPITESTANDADC_LoadCount_OFF ( 5) + #define DDRDATA1CH0_CR_DLLPITESTANDADC_LoadCount_WID (10) + #define DDRDATA1CH0_CR_DLLPITESTANDADC_LoadCount_MSK (0x00007FE0) + #define DDRDATA1CH0_CR_DLLPITESTANDADC_LoadCount_MAX (0x000003FF) + #define DDRDATA1CH0_CR_DLLPITESTANDADC_CountStatus_OFF (15) + #define DDRDATA1CH0_CR_DLLPITESTANDADC_CountStatus_WID (10) + #define DDRDATA1CH0_CR_DLLPITESTANDADC_CountStatus_MSK (0x01FF8000) + #define DDRDATA1CH0_CR_DLLPITESTANDADC_CountStatus_MAX (0x000003FF) + #define DDRDATA1CH0_CR_DLLPITESTANDADC_CountStatus_DEF (0x00000000) + #define DDRDATA1CH0_CR_DLLPITESTANDADC_Spare_OFF (25) + #define DDRDATA1CH0_CR_DLLPITESTANDADC_Spare_WID ( 7) + #define DDRDATA1CH0_CR_DLLPITESTANDADC_Spare_MSK (0xFE000000) + #define DDRDATA1CH0_CR_DLLPITESTANDADC_Spare_MAX (0x0000007F) + +#define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_REG (0x0000025C) + #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_OFF ( 0) + #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_WID ( 6) + #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MSK (0x0000003F) + #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MAX (0x0000003F) + #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_DEF (0x00000000) + #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_OFF ( 6) + #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_WID ( 6) + #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MSK (0x00000FC0) + #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MAX (0x0000003F) + #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_DEF (0x00000000) + #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_OFF (12) + #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_WID ( 5) + #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MSK (0x0001F000) + #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MAX (0x0000001F) + #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_DEF (0x00000000) + #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_OFF (17) + #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_WID ( 5) + #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MSK (0x003E0000) + #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MAX (0x0000001F) + #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_DEF (0x00000000) + #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_OFF (22) + #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_WID ( 5) + #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_MSK (0x07C00000) + #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_MAX (0x0000001F) + #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_DEF (0x00000000) + #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_OFF (27) + #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_WID ( 5) + #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MSK (0xF8000000) + #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MAX (0x0000001F) + #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_DEF (0x00000000) + +#define DDRDATA1CH0_CR_DDRCRDATACONTROL1_REG (0x00000260) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_RefPi_OFF ( 0) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_RefPi_WID ( 4) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_RefPi_MSK (0x0000000F) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_RefPi_MAX (0x0000000F) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_RefPi_DEF (0x00000000) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_DllMask_OFF ( 4) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_DllMask_WID ( 2) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_DllMask_MSK (0x00000030) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_DllMask_MAX (0x00000003) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_DllMask_DEF (0x00000000) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_DllWeakLock_OFF ( 6) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_DllWeakLock_WID ( 1) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_DllWeakLock_MSK (0x00000040) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_DllWeakLock_MAX (0x00000001) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_DllWeakLock_DEF (0x00000000) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_OFF ( 7) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_WID ( 3) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MSK (0x00000380) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MAX (0x00000007) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_DEF (0x00000000) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_OFF (10) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_WID ( 3) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_MSK (0x00001C00) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_MAX (0x00000007) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_DEF (0x00000000) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_OdtDelay_OFF (13) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_OdtDelay_WID ( 4) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_OdtDelay_MSK (0x0001E000) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_OdtDelay_MAX (0x0000000F) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_OdtDelay_DEF (0x00000000) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_OdtDuration_OFF (17) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_OdtDuration_WID ( 3) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_OdtDuration_MSK (0x000E0000) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_OdtDuration_MAX (0x00000007) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_OdtDuration_DEF (0x00000000) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_OFF (20) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_WID ( 4) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_MSK (0x00F00000) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_MAX (0x0000000F) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_DEF (0x00000000) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_OFF (24) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_WID ( 3) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_MSK (0x07000000) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_MAX (0x00000007) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_DEF (0x00000000) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_OFF (27) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_WID ( 3) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_MSK (0x38000000) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_MAX (0x00000007) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_DEF (0x00000000) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_OFF (30) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_WID ( 1) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_MSK (0x40000000) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_MAX (0x00000001) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_DEF (0x00000000) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_Rsvd1_OFF (31) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_Rsvd1_WID ( 1) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_Rsvd1_MSK (0x80000000) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_Rsvd1_MAX (0x00000001) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_Rsvd1_DEF (0x00000000) + +#define DDRDATA1CH0_CR_DDRCRDATACONTROL2_REG (0x00000264) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_OFF ( 0) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_WID ( 5) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_MSK (0x0000001F) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_MAX (0x0000001F) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_DEF (0x00000000) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_OFF ( 5) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_WID ( 1) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_MSK (0x00000020) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_MAX (0x00000001) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_DEF (0x00000000) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_ForceRxOn_OFF ( 6) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_ForceRxOn_WID ( 1) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_ForceRxOn_MSK (0x00000040) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_ForceRxOn_MAX (0x00000001) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_ForceRxOn_DEF (0x00000000) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_LeakerComp_OFF ( 7) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_LeakerComp_WID ( 2) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_LeakerComp_MSK (0x00000180) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_LeakerComp_MAX (0x00000003) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_LeakerComp_DEF (0x00000000) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_OFF ( 9) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_WID ( 4) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_MSK (0x00001E00) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_MAX (0x0000000F) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_DEF (0x00000008) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_OFF (13) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_WID ( 5) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_MSK (0x0003E000) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_MAX (0x0000001F) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_DEF (0x00000011) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_OFF (18) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_WID ( 1) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_MSK (0x00040000) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_MAX (0x00000001) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_DEF (0x00000000) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_Spare_OFF (19) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_Spare_WID (13) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_Spare_MSK (0xFFF80000) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_Spare_MAX (0x00001FFF) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_Spare_DEF (0x00000000) + +#define DDRDATA1CH0_CR_DDRCRVSSHIORVREFCONTROL_REG (0x0000026C) + #define DDRDATA1CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_OFF ( 0) + #define DDRDATA1CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_WID (24) + #define DDRDATA1CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_MSK (0x00FFFFFF) + #define DDRDATA1CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_MAX (0x00FFFFFF) + #define DDRDATA1CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_DEF (0x00000000) + #define DDRDATA1CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_OFF (24) + #define DDRDATA1CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_WID ( 8) + #define DDRDATA1CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_MSK (0xFF000000) + #define DDRDATA1CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_MAX (0x000000FF) + #define DDRDATA1CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_DEF (0x00000000) + +#define DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_REG (0x00000270) + #define DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_OFF ( 0) + #define DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_WID ( 6) + #define DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MSK (0x0000003F) + #define DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MAX (0x0000003F) + #define DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_DEF (0x00000000) + #define DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_OFF ( 6) + #define DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_WID ( 6) + #define DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MSK (0x00000FC0) + #define DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MAX (0x0000003F) + #define DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_DEF (0x00000000) + #define DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_OFF (12) + #define DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_WID ( 6) + #define DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MSK (0x0003F000) + #define DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MAX (0x0000003F) + #define DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_DEF (0x00000000) + #define DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_OFF (18) + #define DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_WID ( 6) + #define DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MSK (0x00FC0000) + #define DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MAX (0x0000003F) + #define DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_DEF (0x00000000) + #define DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_OFF (24) + #define DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_WID ( 7) + #define DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MSK (0x7F000000) + #define DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MAX (0x0000007F) + #define DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_DEF (0x00000000) + #define DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_OFF (31) + #define DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_WID ( 1) + #define DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_MSK (0x80000000) + #define DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_MAX (0x00000001) + #define DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_DEF (0x00000000) + +#define DDRDATA1CH0_CR_DDRCRDATACONTROL0_REG (0x00000274) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_OFF ( 0) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_WID ( 1) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_MSK (0x00000001) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_MAX (0x00000001) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_DEF (0x00000000) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_OFF ( 1) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_WID ( 1) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_MSK (0x00000002) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_MAX (0x00000001) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_DEF (0x00000000) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_OFF ( 2) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_WID ( 1) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_MSK (0x00000004) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_MAX (0x00000001) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_DEF (0x00000000) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_OFF ( 3) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_WID ( 1) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MSK (0x00000008) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MAX (0x00000001) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_DEF (0x00000000) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_TxOn_OFF ( 4) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_TxOn_WID ( 1) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_TxOn_MSK (0x00000010) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_TxOn_MAX (0x00000001) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_TxOn_DEF (0x00000000) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RfOn_OFF ( 5) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RfOn_WID ( 1) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RfOn_MSK (0x00000020) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RfOn_MAX (0x00000001) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RfOn_DEF (0x00000000) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RxPiOn_OFF ( 6) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RxPiOn_WID ( 1) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RxPiOn_MSK (0x00000040) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RxPiOn_MAX (0x00000001) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RxPiOn_DEF (0x00000000) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_TxPiOn_OFF ( 7) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_TxPiOn_WID ( 1) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_TxPiOn_MSK (0x00000080) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_TxPiOn_MAX (0x00000001) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_TxPiOn_DEF (0x00000000) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_OFF ( 8) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_WID ( 1) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_MSK (0x00000100) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_MAX (0x00000001) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_DEF (0x00000000) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_OFF ( 9) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_WID ( 1) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MSK (0x00000200) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MAX (0x00000001) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_DEF (0x00000000) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_TxDisable_OFF (10) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_TxDisable_WID ( 1) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_TxDisable_MSK (0x00000400) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_TxDisable_MAX (0x00000001) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_TxDisable_DEF (0x00000000) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RxDisable_OFF (11) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RxDisable_WID ( 1) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RxDisable_MSK (0x00000800) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RxDisable_MAX (0x00000001) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RxDisable_DEF (0x00000000) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_TxLong_OFF (12) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_TxLong_WID ( 1) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_TxLong_MSK (0x00001000) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_TxLong_MAX (0x00000001) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_TxLong_DEF (0x00000000) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_OFF (13) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_WID ( 2) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_MSK (0x00006000) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_MAX (0x00000003) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_DEF (0x00000000) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RxReadPointer_OFF (15) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RxReadPointer_WID ( 3) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RxReadPointer_MSK (0x00038000) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RxReadPointer_MAX (0x00000007) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RxReadPointer_DEF (0x00000000) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_OFF (18) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_WID ( 1) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_MSK (0x00040000) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_MAX (0x00000001) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_DEF (0x00000000) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_OFF (19) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_WID ( 1) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_MSK (0x00080000) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_MAX (0x00000001) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_DEF (0x00000000) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_ReadRFRd_OFF (20) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_ReadRFRd_WID ( 1) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_ReadRFRd_MSK (0x00100000) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_ReadRFRd_MAX (0x00000001) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_ReadRFRd_DEF (0x00000000) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_ReadRFWr_OFF (21) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_ReadRFWr_WID ( 1) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_ReadRFWr_MSK (0x00200000) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_ReadRFWr_MAX (0x00000001) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_ReadRFWr_DEF (0x00000000) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_ReadRFRank_OFF (22) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_ReadRFRank_WID ( 2) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_ReadRFRank_MSK (0x00C00000) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_ReadRFRank_MAX (0x00000003) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_ReadRFRank_DEF (0x00000000) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_OFF (24) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_WID ( 1) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_MSK (0x01000000) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_MAX (0x00000001) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_DEF (0x00000000) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_OdtSampOff_OFF (25) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_OdtSampOff_WID ( 1) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_OdtSampOff_MSK (0x02000000) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_OdtSampOff_MAX (0x00000001) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_OdtSampOff_DEF (0x00000000) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_OFF (26) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_WID ( 1) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_MSK (0x04000000) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_MAX (0x00000001) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_DEF (0x00000000) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_OFF (27) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_WID ( 1) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MSK (0x08000000) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MAX (0x00000001) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_DEF (0x00000000) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_OFF (28) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_WID ( 1) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_MSK (0x10000000) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_MAX (0x00000001) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_DEF (0x00000000) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_OFF (29) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_WID ( 1) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_MSK (0x20000000) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_MAX (0x00000001) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_DEF (0x00000000) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_OFF (30) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_WID ( 1) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MSK (0x40000000) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MAX (0x00000001) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_DEF (0x00000000) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_OFF (31) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_WID ( 1) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_MSK (0x80000000) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_MAX (0x00000001) + #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_DEF (0x00000000) + +#define DDRDATA1CH0_CR_DDRCRVREFADJUST1_REG (0x00000278) + #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_OFF ( 0) + #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_WID ( 7) + #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_MSK (0x0000007F) + #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_MAX (0x0000007F) + #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_DEF (0x00000000) + #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_OFF ( 7) + #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_WID ( 7) + #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_MSK (0x00003F80) + #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_MAX (0x0000007F) + #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_DEF (0x00000000) + #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_OFF (14) + #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_WID ( 7) + #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_MSK (0x001FC000) + #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_MAX (0x0000007F) + #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_DEF (0x00000000) + #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_OFF (21) + #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_WID ( 1) + #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_MSK (0x00200000) + #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_MAX (0x00000001) + #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_DEF (0x00000000) + #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_OFF (22) + #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_WID ( 1) + #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_MSK (0x00400000) + #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_MAX (0x00000001) + #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_DEF (0x00000000) + #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_OFF (23) + #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_WID ( 1) + #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_MSK (0x00800000) + #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_MAX (0x00000001) + #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_DEF (0x00000000) + #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_OFF (24) + #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_WID ( 2) + #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_MSK (0x03000000) + #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_MAX (0x00000003) + #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_DEF (0x00000000) + #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_OFF (26) + #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_WID ( 1) + #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_MSK (0x04000000) + #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_MAX (0x00000001) + #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_DEF (0x00000000) + #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_Rsvd_OFF (27) + #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_Rsvd_WID ( 2) + #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_Rsvd_MSK (0x18000000) + #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_Rsvd_MAX (0x00000003) + #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_Rsvd_DEF (0x00000000) + #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_caSlowBW_OFF (29) + #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_caSlowBW_WID ( 1) + #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_caSlowBW_MSK (0x20000000) + #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_caSlowBW_MAX (0x00000001) + #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_caSlowBW_DEF (0x00000000) + #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_OFF (30) + #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_WID ( 1) + #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_MSK (0x40000000) + #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_MAX (0x00000001) + #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_DEF (0x00000000) + #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_OFF (31) + #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_WID ( 1) + #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_MSK (0x80000000) + #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_MAX (0x00000001) + #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_DEF (0x00000000) + +#define DDRDATA1CH1_CR_RXTRAINRANK0_REG (0x00000300) + #define DDRDATA1CH1_CR_RXTRAINRANK0_RxRcvEnPi_OFF ( 0) + #define DDRDATA1CH1_CR_RXTRAINRANK0_RxRcvEnPi_WID ( 9) + #define DDRDATA1CH1_CR_RXTRAINRANK0_RxRcvEnPi_MSK (0x000001FF) + #define DDRDATA1CH1_CR_RXTRAINRANK0_RxRcvEnPi_MAX (0x000001FF) + #define DDRDATA1CH1_CR_RXTRAINRANK0_RxDqsPPi_OFF ( 9) + #define DDRDATA1CH1_CR_RXTRAINRANK0_RxDqsPPi_WID ( 6) + #define DDRDATA1CH1_CR_RXTRAINRANK0_RxDqsPPi_MSK (0x00007E00) + #define DDRDATA1CH1_CR_RXTRAINRANK0_RxDqsPPi_MAX (0x0000003F) + #define DDRDATA1CH1_CR_RXTRAINRANK0_RxEq_OFF (15) + #define DDRDATA1CH1_CR_RXTRAINRANK0_RxEq_WID ( 5) + #define DDRDATA1CH1_CR_RXTRAINRANK0_RxEq_MSK (0x000F8000) + #define DDRDATA1CH1_CR_RXTRAINRANK0_RxEq_MAX (0x0000001F) + #define DDRDATA1CH1_CR_RXTRAINRANK0_RxDqsNPi_OFF (20) + #define DDRDATA1CH1_CR_RXTRAINRANK0_RxDqsNPi_WID ( 6) + #define DDRDATA1CH1_CR_RXTRAINRANK0_RxDqsNPi_MSK (0x03F00000) + #define DDRDATA1CH1_CR_RXTRAINRANK0_RxDqsNPi_MAX (0x0000003F) + #define DDRDATA1CH1_CR_RXTRAINRANK0_RxVref_OFF (26) + #define DDRDATA1CH1_CR_RXTRAINRANK0_RxVref_WID ( 6) + #define DDRDATA1CH1_CR_RXTRAINRANK0_RxVref_MSK (0xFC000000) + #define DDRDATA1CH1_CR_RXTRAINRANK0_RxVref_MAX (0x0000003F) + +#define DDRDATA1CH1_CR_RXTRAINRANK1_REG (0x00000304) + #define DDRDATA1CH1_CR_RXTRAINRANK1_RxRcvEnPi_OFF ( 0) + #define DDRDATA1CH1_CR_RXTRAINRANK1_RxRcvEnPi_WID ( 9) + #define DDRDATA1CH1_CR_RXTRAINRANK1_RxRcvEnPi_MSK (0x000001FF) + #define DDRDATA1CH1_CR_RXTRAINRANK1_RxRcvEnPi_MAX (0x000001FF) + #define DDRDATA1CH1_CR_RXTRAINRANK1_RxDqsPPi_OFF ( 9) + #define DDRDATA1CH1_CR_RXTRAINRANK1_RxDqsPPi_WID ( 6) + #define DDRDATA1CH1_CR_RXTRAINRANK1_RxDqsPPi_MSK (0x00007E00) + #define DDRDATA1CH1_CR_RXTRAINRANK1_RxDqsPPi_MAX (0x0000003F) + #define DDRDATA1CH1_CR_RXTRAINRANK1_RxEq_OFF (15) + #define DDRDATA1CH1_CR_RXTRAINRANK1_RxEq_WID ( 5) + #define DDRDATA1CH1_CR_RXTRAINRANK1_RxEq_MSK (0x000F8000) + #define DDRDATA1CH1_CR_RXTRAINRANK1_RxEq_MAX (0x0000001F) + #define DDRDATA1CH1_CR_RXTRAINRANK1_RxDqsNPi_OFF (20) + #define DDRDATA1CH1_CR_RXTRAINRANK1_RxDqsNPi_WID ( 6) + #define DDRDATA1CH1_CR_RXTRAINRANK1_RxDqsNPi_MSK (0x03F00000) + #define DDRDATA1CH1_CR_RXTRAINRANK1_RxDqsNPi_MAX (0x0000003F) + #define DDRDATA1CH1_CR_RXTRAINRANK1_RxVref_OFF (26) + #define DDRDATA1CH1_CR_RXTRAINRANK1_RxVref_WID ( 6) + #define DDRDATA1CH1_CR_RXTRAINRANK1_RxVref_MSK (0xFC000000) + #define DDRDATA1CH1_CR_RXTRAINRANK1_RxVref_MAX (0x0000003F) + +#define DDRDATA1CH1_CR_RXTRAINRANK2_REG (0x00000308) + #define DDRDATA1CH1_CR_RXTRAINRANK2_RxRcvEnPi_OFF ( 0) + #define DDRDATA1CH1_CR_RXTRAINRANK2_RxRcvEnPi_WID ( 9) + #define DDRDATA1CH1_CR_RXTRAINRANK2_RxRcvEnPi_MSK (0x000001FF) + #define DDRDATA1CH1_CR_RXTRAINRANK2_RxRcvEnPi_MAX (0x000001FF) + #define DDRDATA1CH1_CR_RXTRAINRANK2_RxDqsPPi_OFF ( 9) + #define DDRDATA1CH1_CR_RXTRAINRANK2_RxDqsPPi_WID ( 6) + #define DDRDATA1CH1_CR_RXTRAINRANK2_RxDqsPPi_MSK (0x00007E00) + #define DDRDATA1CH1_CR_RXTRAINRANK2_RxDqsPPi_MAX (0x0000003F) + #define DDRDATA1CH1_CR_RXTRAINRANK2_RxEq_OFF (15) + #define DDRDATA1CH1_CR_RXTRAINRANK2_RxEq_WID ( 5) + #define DDRDATA1CH1_CR_RXTRAINRANK2_RxEq_MSK (0x000F8000) + #define DDRDATA1CH1_CR_RXTRAINRANK2_RxEq_MAX (0x0000001F) + #define DDRDATA1CH1_CR_RXTRAINRANK2_RxDqsNPi_OFF (20) + #define DDRDATA1CH1_CR_RXTRAINRANK2_RxDqsNPi_WID ( 6) + #define DDRDATA1CH1_CR_RXTRAINRANK2_RxDqsNPi_MSK (0x03F00000) + #define DDRDATA1CH1_CR_RXTRAINRANK2_RxDqsNPi_MAX (0x0000003F) + #define DDRDATA1CH1_CR_RXTRAINRANK2_RxVref_OFF (26) + #define DDRDATA1CH1_CR_RXTRAINRANK2_RxVref_WID ( 6) + #define DDRDATA1CH1_CR_RXTRAINRANK2_RxVref_MSK (0xFC000000) + #define DDRDATA1CH1_CR_RXTRAINRANK2_RxVref_MAX (0x0000003F) + +#define DDRDATA1CH1_CR_RXTRAINRANK3_REG (0x0000030C) + #define DDRDATA1CH1_CR_RXTRAINRANK3_RxRcvEnPi_OFF ( 0) + #define DDRDATA1CH1_CR_RXTRAINRANK3_RxRcvEnPi_WID ( 9) + #define DDRDATA1CH1_CR_RXTRAINRANK3_RxRcvEnPi_MSK (0x000001FF) + #define DDRDATA1CH1_CR_RXTRAINRANK3_RxRcvEnPi_MAX (0x000001FF) + #define DDRDATA1CH1_CR_RXTRAINRANK3_RxDqsPPi_OFF ( 9) + #define DDRDATA1CH1_CR_RXTRAINRANK3_RxDqsPPi_WID ( 6) + #define DDRDATA1CH1_CR_RXTRAINRANK3_RxDqsPPi_MSK (0x00007E00) + #define DDRDATA1CH1_CR_RXTRAINRANK3_RxDqsPPi_MAX (0x0000003F) + #define DDRDATA1CH1_CR_RXTRAINRANK3_RxEq_OFF (15) + #define DDRDATA1CH1_CR_RXTRAINRANK3_RxEq_WID ( 5) + #define DDRDATA1CH1_CR_RXTRAINRANK3_RxEq_MSK (0x000F8000) + #define DDRDATA1CH1_CR_RXTRAINRANK3_RxEq_MAX (0x0000001F) + #define DDRDATA1CH1_CR_RXTRAINRANK3_RxDqsNPi_OFF (20) + #define DDRDATA1CH1_CR_RXTRAINRANK3_RxDqsNPi_WID ( 6) + #define DDRDATA1CH1_CR_RXTRAINRANK3_RxDqsNPi_MSK (0x03F00000) + #define DDRDATA1CH1_CR_RXTRAINRANK3_RxDqsNPi_MAX (0x0000003F) + #define DDRDATA1CH1_CR_RXTRAINRANK3_RxVref_OFF (26) + #define DDRDATA1CH1_CR_RXTRAINRANK3_RxVref_WID ( 6) + #define DDRDATA1CH1_CR_RXTRAINRANK3_RxVref_MSK (0xFC000000) + #define DDRDATA1CH1_CR_RXTRAINRANK3_RxVref_MAX (0x0000003F) + +#define DDRDATA1CH1_CR_RXPERBITRANK0_REG (0x00000310) + #define DDRDATA1CH1_CR_RXPERBITRANK0_Lane0_OFF ( 0) + #define DDRDATA1CH1_CR_RXPERBITRANK0_Lane0_WID ( 4) + #define DDRDATA1CH1_CR_RXPERBITRANK0_Lane0_MSK (0x0000000F) + #define DDRDATA1CH1_CR_RXPERBITRANK0_Lane0_MAX (0x0000000F) + #define DDRDATA1CH1_CR_RXPERBITRANK0_Lane1_OFF ( 4) + #define DDRDATA1CH1_CR_RXPERBITRANK0_Lane1_WID ( 4) + #define DDRDATA1CH1_CR_RXPERBITRANK0_Lane1_MSK (0x000000F0) + #define DDRDATA1CH1_CR_RXPERBITRANK0_Lane1_MAX (0x0000000F) + #define DDRDATA1CH1_CR_RXPERBITRANK0_Lane2_OFF ( 8) + #define DDRDATA1CH1_CR_RXPERBITRANK0_Lane2_WID ( 4) + #define DDRDATA1CH1_CR_RXPERBITRANK0_Lane2_MSK (0x00000F00) + #define DDRDATA1CH1_CR_RXPERBITRANK0_Lane2_MAX (0x0000000F) + #define DDRDATA1CH1_CR_RXPERBITRANK0_Lane3_OFF (12) + #define DDRDATA1CH1_CR_RXPERBITRANK0_Lane3_WID ( 4) + #define DDRDATA1CH1_CR_RXPERBITRANK0_Lane3_MSK (0x0000F000) + #define DDRDATA1CH1_CR_RXPERBITRANK0_Lane3_MAX (0x0000000F) + #define DDRDATA1CH1_CR_RXPERBITRANK0_Lane4_OFF (16) + #define DDRDATA1CH1_CR_RXPERBITRANK0_Lane4_WID ( 4) + #define DDRDATA1CH1_CR_RXPERBITRANK0_Lane4_MSK (0x000F0000) + #define DDRDATA1CH1_CR_RXPERBITRANK0_Lane4_MAX (0x0000000F) + #define DDRDATA1CH1_CR_RXPERBITRANK0_Lane5_OFF (20) + #define DDRDATA1CH1_CR_RXPERBITRANK0_Lane5_WID ( 4) + #define DDRDATA1CH1_CR_RXPERBITRANK0_Lane5_MSK (0x00F00000) + #define DDRDATA1CH1_CR_RXPERBITRANK0_Lane5_MAX (0x0000000F) + #define DDRDATA1CH1_CR_RXPERBITRANK0_Lane6_OFF (24) + #define DDRDATA1CH1_CR_RXPERBITRANK0_Lane6_WID ( 4) + #define DDRDATA1CH1_CR_RXPERBITRANK0_Lane6_MSK (0x0F000000) + #define DDRDATA1CH1_CR_RXPERBITRANK0_Lane6_MAX (0x0000000F) + #define DDRDATA1CH1_CR_RXPERBITRANK0_Lane7_OFF (28) + #define DDRDATA1CH1_CR_RXPERBITRANK0_Lane7_WID ( 4) + #define DDRDATA1CH1_CR_RXPERBITRANK0_Lane7_MSK (0xF0000000) + #define DDRDATA1CH1_CR_RXPERBITRANK0_Lane7_MAX (0x0000000F) + +#define DDRDATA1CH1_CR_RXPERBITRANK1_REG (0x00000314) + #define DDRDATA1CH1_CR_RXPERBITRANK1_Lane0_OFF ( 0) + #define DDRDATA1CH1_CR_RXPERBITRANK1_Lane0_WID ( 4) + #define DDRDATA1CH1_CR_RXPERBITRANK1_Lane0_MSK (0x0000000F) + #define DDRDATA1CH1_CR_RXPERBITRANK1_Lane0_MAX (0x0000000F) + #define DDRDATA1CH1_CR_RXPERBITRANK1_Lane1_OFF ( 4) + #define DDRDATA1CH1_CR_RXPERBITRANK1_Lane1_WID ( 4) + #define DDRDATA1CH1_CR_RXPERBITRANK1_Lane1_MSK (0x000000F0) + #define DDRDATA1CH1_CR_RXPERBITRANK1_Lane1_MAX (0x0000000F) + #define DDRDATA1CH1_CR_RXPERBITRANK1_Lane2_OFF ( 8) + #define DDRDATA1CH1_CR_RXPERBITRANK1_Lane2_WID ( 4) + #define DDRDATA1CH1_CR_RXPERBITRANK1_Lane2_MSK (0x00000F00) + #define DDRDATA1CH1_CR_RXPERBITRANK1_Lane2_MAX (0x0000000F) + #define DDRDATA1CH1_CR_RXPERBITRANK1_Lane3_OFF (12) + #define DDRDATA1CH1_CR_RXPERBITRANK1_Lane3_WID ( 4) + #define DDRDATA1CH1_CR_RXPERBITRANK1_Lane3_MSK (0x0000F000) + #define DDRDATA1CH1_CR_RXPERBITRANK1_Lane3_MAX (0x0000000F) + #define DDRDATA1CH1_CR_RXPERBITRANK1_Lane4_OFF (16) + #define DDRDATA1CH1_CR_RXPERBITRANK1_Lane4_WID ( 4) + #define DDRDATA1CH1_CR_RXPERBITRANK1_Lane4_MSK (0x000F0000) + #define DDRDATA1CH1_CR_RXPERBITRANK1_Lane4_MAX (0x0000000F) + #define DDRDATA1CH1_CR_RXPERBITRANK1_Lane5_OFF (20) + #define DDRDATA1CH1_CR_RXPERBITRANK1_Lane5_WID ( 4) + #define DDRDATA1CH1_CR_RXPERBITRANK1_Lane5_MSK (0x00F00000) + #define DDRDATA1CH1_CR_RXPERBITRANK1_Lane5_MAX (0x0000000F) + #define DDRDATA1CH1_CR_RXPERBITRANK1_Lane6_OFF (24) + #define DDRDATA1CH1_CR_RXPERBITRANK1_Lane6_WID ( 4) + #define DDRDATA1CH1_CR_RXPERBITRANK1_Lane6_MSK (0x0F000000) + #define DDRDATA1CH1_CR_RXPERBITRANK1_Lane6_MAX (0x0000000F) + #define DDRDATA1CH1_CR_RXPERBITRANK1_Lane7_OFF (28) + #define DDRDATA1CH1_CR_RXPERBITRANK1_Lane7_WID ( 4) + #define DDRDATA1CH1_CR_RXPERBITRANK1_Lane7_MSK (0xF0000000) + #define DDRDATA1CH1_CR_RXPERBITRANK1_Lane7_MAX (0x0000000F) + +#define DDRDATA1CH1_CR_RXPERBITRANK2_REG (0x00000318) + #define DDRDATA1CH1_CR_RXPERBITRANK2_Lane0_OFF ( 0) + #define DDRDATA1CH1_CR_RXPERBITRANK2_Lane0_WID ( 4) + #define DDRDATA1CH1_CR_RXPERBITRANK2_Lane0_MSK (0x0000000F) + #define DDRDATA1CH1_CR_RXPERBITRANK2_Lane0_MAX (0x0000000F) + #define DDRDATA1CH1_CR_RXPERBITRANK2_Lane1_OFF ( 4) + #define DDRDATA1CH1_CR_RXPERBITRANK2_Lane1_WID ( 4) + #define DDRDATA1CH1_CR_RXPERBITRANK2_Lane1_MSK (0x000000F0) + #define DDRDATA1CH1_CR_RXPERBITRANK2_Lane1_MAX (0x0000000F) + #define DDRDATA1CH1_CR_RXPERBITRANK2_Lane2_OFF ( 8) + #define DDRDATA1CH1_CR_RXPERBITRANK2_Lane2_WID ( 4) + #define DDRDATA1CH1_CR_RXPERBITRANK2_Lane2_MSK (0x00000F00) + #define DDRDATA1CH1_CR_RXPERBITRANK2_Lane2_MAX (0x0000000F) + #define DDRDATA1CH1_CR_RXPERBITRANK2_Lane3_OFF (12) + #define DDRDATA1CH1_CR_RXPERBITRANK2_Lane3_WID ( 4) + #define DDRDATA1CH1_CR_RXPERBITRANK2_Lane3_MSK (0x0000F000) + #define DDRDATA1CH1_CR_RXPERBITRANK2_Lane3_MAX (0x0000000F) + #define DDRDATA1CH1_CR_RXPERBITRANK2_Lane4_OFF (16) + #define DDRDATA1CH1_CR_RXPERBITRANK2_Lane4_WID ( 4) + #define DDRDATA1CH1_CR_RXPERBITRANK2_Lane4_MSK (0x000F0000) + #define DDRDATA1CH1_CR_RXPERBITRANK2_Lane4_MAX (0x0000000F) + #define DDRDATA1CH1_CR_RXPERBITRANK2_Lane5_OFF (20) + #define DDRDATA1CH1_CR_RXPERBITRANK2_Lane5_WID ( 4) + #define DDRDATA1CH1_CR_RXPERBITRANK2_Lane5_MSK (0x00F00000) + #define DDRDATA1CH1_CR_RXPERBITRANK2_Lane5_MAX (0x0000000F) + #define DDRDATA1CH1_CR_RXPERBITRANK2_Lane6_OFF (24) + #define DDRDATA1CH1_CR_RXPERBITRANK2_Lane6_WID ( 4) + #define DDRDATA1CH1_CR_RXPERBITRANK2_Lane6_MSK (0x0F000000) + #define DDRDATA1CH1_CR_RXPERBITRANK2_Lane6_MAX (0x0000000F) + #define DDRDATA1CH1_CR_RXPERBITRANK2_Lane7_OFF (28) + #define DDRDATA1CH1_CR_RXPERBITRANK2_Lane7_WID ( 4) + #define DDRDATA1CH1_CR_RXPERBITRANK2_Lane7_MSK (0xF0000000) + #define DDRDATA1CH1_CR_RXPERBITRANK2_Lane7_MAX (0x0000000F) + +#define DDRDATA1CH1_CR_RXPERBITRANK3_REG (0x0000031C) + #define DDRDATA1CH1_CR_RXPERBITRANK3_Lane0_OFF ( 0) + #define DDRDATA1CH1_CR_RXPERBITRANK3_Lane0_WID ( 4) + #define DDRDATA1CH1_CR_RXPERBITRANK3_Lane0_MSK (0x0000000F) + #define DDRDATA1CH1_CR_RXPERBITRANK3_Lane0_MAX (0x0000000F) + #define DDRDATA1CH1_CR_RXPERBITRANK3_Lane1_OFF ( 4) + #define DDRDATA1CH1_CR_RXPERBITRANK3_Lane1_WID ( 4) + #define DDRDATA1CH1_CR_RXPERBITRANK3_Lane1_MSK (0x000000F0) + #define DDRDATA1CH1_CR_RXPERBITRANK3_Lane1_MAX (0x0000000F) + #define DDRDATA1CH1_CR_RXPERBITRANK3_Lane2_OFF ( 8) + #define DDRDATA1CH1_CR_RXPERBITRANK3_Lane2_WID ( 4) + #define DDRDATA1CH1_CR_RXPERBITRANK3_Lane2_MSK (0x00000F00) + #define DDRDATA1CH1_CR_RXPERBITRANK3_Lane2_MAX (0x0000000F) + #define DDRDATA1CH1_CR_RXPERBITRANK3_Lane3_OFF (12) + #define DDRDATA1CH1_CR_RXPERBITRANK3_Lane3_WID ( 4) + #define DDRDATA1CH1_CR_RXPERBITRANK3_Lane3_MSK (0x0000F000) + #define DDRDATA1CH1_CR_RXPERBITRANK3_Lane3_MAX (0x0000000F) + #define DDRDATA1CH1_CR_RXPERBITRANK3_Lane4_OFF (16) + #define DDRDATA1CH1_CR_RXPERBITRANK3_Lane4_WID ( 4) + #define DDRDATA1CH1_CR_RXPERBITRANK3_Lane4_MSK (0x000F0000) + #define DDRDATA1CH1_CR_RXPERBITRANK3_Lane4_MAX (0x0000000F) + #define DDRDATA1CH1_CR_RXPERBITRANK3_Lane5_OFF (20) + #define DDRDATA1CH1_CR_RXPERBITRANK3_Lane5_WID ( 4) + #define DDRDATA1CH1_CR_RXPERBITRANK3_Lane5_MSK (0x00F00000) + #define DDRDATA1CH1_CR_RXPERBITRANK3_Lane5_MAX (0x0000000F) + #define DDRDATA1CH1_CR_RXPERBITRANK3_Lane6_OFF (24) + #define DDRDATA1CH1_CR_RXPERBITRANK3_Lane6_WID ( 4) + #define DDRDATA1CH1_CR_RXPERBITRANK3_Lane6_MSK (0x0F000000) + #define DDRDATA1CH1_CR_RXPERBITRANK3_Lane6_MAX (0x0000000F) + #define DDRDATA1CH1_CR_RXPERBITRANK3_Lane7_OFF (28) + #define DDRDATA1CH1_CR_RXPERBITRANK3_Lane7_WID ( 4) + #define DDRDATA1CH1_CR_RXPERBITRANK3_Lane7_MSK (0xF0000000) + #define DDRDATA1CH1_CR_RXPERBITRANK3_Lane7_MAX (0x0000000F) + +#define DDRDATA1CH1_CR_TXTRAINRANK0_REG (0x00000320) + #define DDRDATA1CH1_CR_TXTRAINRANK0_TxDqDelay_OFF ( 0) + #define DDRDATA1CH1_CR_TXTRAINRANK0_TxDqDelay_WID ( 9) + #define DDRDATA1CH1_CR_TXTRAINRANK0_TxDqDelay_MSK (0x000001FF) + #define DDRDATA1CH1_CR_TXTRAINRANK0_TxDqDelay_MAX (0x000001FF) + #define DDRDATA1CH1_CR_TXTRAINRANK0_TxDqsDelay_OFF ( 9) + #define DDRDATA1CH1_CR_TXTRAINRANK0_TxDqsDelay_WID ( 9) + #define DDRDATA1CH1_CR_TXTRAINRANK0_TxDqsDelay_MSK (0x0003FE00) + #define DDRDATA1CH1_CR_TXTRAINRANK0_TxDqsDelay_MAX (0x000001FF) + #define DDRDATA1CH1_CR_TXTRAINRANK0_Spare0_OFF (18) + #define DDRDATA1CH1_CR_TXTRAINRANK0_Spare0_WID ( 2) + #define DDRDATA1CH1_CR_TXTRAINRANK0_Spare0_MSK (0x000C0000) + #define DDRDATA1CH1_CR_TXTRAINRANK0_Spare0_MAX (0x00000003) + #define DDRDATA1CH1_CR_TXTRAINRANK0_TxEqualization_OFF (20) + #define DDRDATA1CH1_CR_TXTRAINRANK0_TxEqualization_WID ( 6) + #define DDRDATA1CH1_CR_TXTRAINRANK0_TxEqualization_MSK (0x03F00000) + #define DDRDATA1CH1_CR_TXTRAINRANK0_TxEqualization_MAX (0x0000003F) + #define DDRDATA1CH1_CR_TXTRAINRANK0_Spare1_OFF (26) + #define DDRDATA1CH1_CR_TXTRAINRANK0_Spare1_WID ( 6) + #define DDRDATA1CH1_CR_TXTRAINRANK0_Spare1_MSK (0xFC000000) + #define DDRDATA1CH1_CR_TXTRAINRANK0_Spare1_MAX (0x0000003F) + +#define DDRDATA1CH1_CR_TXTRAINRANK1_REG (0x00000324) + #define DDRDATA1CH1_CR_TXTRAINRANK1_TxDqDelay_OFF ( 0) + #define DDRDATA1CH1_CR_TXTRAINRANK1_TxDqDelay_WID ( 9) + #define DDRDATA1CH1_CR_TXTRAINRANK1_TxDqDelay_MSK (0x000001FF) + #define DDRDATA1CH1_CR_TXTRAINRANK1_TxDqDelay_MAX (0x000001FF) + #define DDRDATA1CH1_CR_TXTRAINRANK1_TxDqsDelay_OFF ( 9) + #define DDRDATA1CH1_CR_TXTRAINRANK1_TxDqsDelay_WID ( 9) + #define DDRDATA1CH1_CR_TXTRAINRANK1_TxDqsDelay_MSK (0x0003FE00) + #define DDRDATA1CH1_CR_TXTRAINRANK1_TxDqsDelay_MAX (0x000001FF) + #define DDRDATA1CH1_CR_TXTRAINRANK1_Spare0_OFF (18) + #define DDRDATA1CH1_CR_TXTRAINRANK1_Spare0_WID ( 2) + #define DDRDATA1CH1_CR_TXTRAINRANK1_Spare0_MSK (0x000C0000) + #define DDRDATA1CH1_CR_TXTRAINRANK1_Spare0_MAX (0x00000003) + #define DDRDATA1CH1_CR_TXTRAINRANK1_TxEqualization_OFF (20) + #define DDRDATA1CH1_CR_TXTRAINRANK1_TxEqualization_WID ( 6) + #define DDRDATA1CH1_CR_TXTRAINRANK1_TxEqualization_MSK (0x03F00000) + #define DDRDATA1CH1_CR_TXTRAINRANK1_TxEqualization_MAX (0x0000003F) + #define DDRDATA1CH1_CR_TXTRAINRANK1_Spare1_OFF (26) + #define DDRDATA1CH1_CR_TXTRAINRANK1_Spare1_WID ( 6) + #define DDRDATA1CH1_CR_TXTRAINRANK1_Spare1_MSK (0xFC000000) + #define DDRDATA1CH1_CR_TXTRAINRANK1_Spare1_MAX (0x0000003F) + +#define DDRDATA1CH1_CR_TXTRAINRANK2_REG (0x00000328) + #define DDRDATA1CH1_CR_TXTRAINRANK2_TxDqDelay_OFF ( 0) + #define DDRDATA1CH1_CR_TXTRAINRANK2_TxDqDelay_WID ( 9) + #define DDRDATA1CH1_CR_TXTRAINRANK2_TxDqDelay_MSK (0x000001FF) + #define DDRDATA1CH1_CR_TXTRAINRANK2_TxDqDelay_MAX (0x000001FF) + #define DDRDATA1CH1_CR_TXTRAINRANK2_TxDqsDelay_OFF ( 9) + #define DDRDATA1CH1_CR_TXTRAINRANK2_TxDqsDelay_WID ( 9) + #define DDRDATA1CH1_CR_TXTRAINRANK2_TxDqsDelay_MSK (0x0003FE00) + #define DDRDATA1CH1_CR_TXTRAINRANK2_TxDqsDelay_MAX (0x000001FF) + #define DDRDATA1CH1_CR_TXTRAINRANK2_Spare0_OFF (18) + #define DDRDATA1CH1_CR_TXTRAINRANK2_Spare0_WID ( 2) + #define DDRDATA1CH1_CR_TXTRAINRANK2_Spare0_MSK (0x000C0000) + #define DDRDATA1CH1_CR_TXTRAINRANK2_Spare0_MAX (0x00000003) + #define DDRDATA1CH1_CR_TXTRAINRANK2_TxEqualization_OFF (20) + #define DDRDATA1CH1_CR_TXTRAINRANK2_TxEqualization_WID ( 6) + #define DDRDATA1CH1_CR_TXTRAINRANK2_TxEqualization_MSK (0x03F00000) + #define DDRDATA1CH1_CR_TXTRAINRANK2_TxEqualization_MAX (0x0000003F) + #define DDRDATA1CH1_CR_TXTRAINRANK2_Spare1_OFF (26) + #define DDRDATA1CH1_CR_TXTRAINRANK2_Spare1_WID ( 6) + #define DDRDATA1CH1_CR_TXTRAINRANK2_Spare1_MSK (0xFC000000) + #define DDRDATA1CH1_CR_TXTRAINRANK2_Spare1_MAX (0x0000003F) + +#define DDRDATA1CH1_CR_TXTRAINRANK3_REG (0x0000032C) + #define DDRDATA1CH1_CR_TXTRAINRANK3_TxDqDelay_OFF ( 0) + #define DDRDATA1CH1_CR_TXTRAINRANK3_TxDqDelay_WID ( 9) + #define DDRDATA1CH1_CR_TXTRAINRANK3_TxDqDelay_MSK (0x000001FF) + #define DDRDATA1CH1_CR_TXTRAINRANK3_TxDqDelay_MAX (0x000001FF) + #define DDRDATA1CH1_CR_TXTRAINRANK3_TxDqsDelay_OFF ( 9) + #define DDRDATA1CH1_CR_TXTRAINRANK3_TxDqsDelay_WID ( 9) + #define DDRDATA1CH1_CR_TXTRAINRANK3_TxDqsDelay_MSK (0x0003FE00) + #define DDRDATA1CH1_CR_TXTRAINRANK3_TxDqsDelay_MAX (0x000001FF) + #define DDRDATA1CH1_CR_TXTRAINRANK3_Spare0_OFF (18) + #define DDRDATA1CH1_CR_TXTRAINRANK3_Spare0_WID ( 2) + #define DDRDATA1CH1_CR_TXTRAINRANK3_Spare0_MSK (0x000C0000) + #define DDRDATA1CH1_CR_TXTRAINRANK3_Spare0_MAX (0x00000003) + #define DDRDATA1CH1_CR_TXTRAINRANK3_TxEqualization_OFF (20) + #define DDRDATA1CH1_CR_TXTRAINRANK3_TxEqualization_WID ( 6) + #define DDRDATA1CH1_CR_TXTRAINRANK3_TxEqualization_MSK (0x03F00000) + #define DDRDATA1CH1_CR_TXTRAINRANK3_TxEqualization_MAX (0x0000003F) + #define DDRDATA1CH1_CR_TXTRAINRANK3_Spare1_OFF (26) + #define DDRDATA1CH1_CR_TXTRAINRANK3_Spare1_WID ( 6) + #define DDRDATA1CH1_CR_TXTRAINRANK3_Spare1_MSK (0xFC000000) + #define DDRDATA1CH1_CR_TXTRAINRANK3_Spare1_MAX (0x0000003F) + +#define DDRDATA1CH1_CR_TXPERBITRANK0_REG (0x00000330) + #define DDRDATA1CH1_CR_TXPERBITRANK0_Lane0_OFF ( 0) + #define DDRDATA1CH1_CR_TXPERBITRANK0_Lane0_WID ( 4) + #define DDRDATA1CH1_CR_TXPERBITRANK0_Lane0_MSK (0x0000000F) + #define DDRDATA1CH1_CR_TXPERBITRANK0_Lane0_MAX (0x0000000F) + #define DDRDATA1CH1_CR_TXPERBITRANK0_Lane1_OFF ( 4) + #define DDRDATA1CH1_CR_TXPERBITRANK0_Lane1_WID ( 4) + #define DDRDATA1CH1_CR_TXPERBITRANK0_Lane1_MSK (0x000000F0) + #define DDRDATA1CH1_CR_TXPERBITRANK0_Lane1_MAX (0x0000000F) + #define DDRDATA1CH1_CR_TXPERBITRANK0_Lane2_OFF ( 8) + #define DDRDATA1CH1_CR_TXPERBITRANK0_Lane2_WID ( 4) + #define DDRDATA1CH1_CR_TXPERBITRANK0_Lane2_MSK (0x00000F00) + #define DDRDATA1CH1_CR_TXPERBITRANK0_Lane2_MAX (0x0000000F) + #define DDRDATA1CH1_CR_TXPERBITRANK0_Lane3_OFF (12) + #define DDRDATA1CH1_CR_TXPERBITRANK0_Lane3_WID ( 4) + #define DDRDATA1CH1_CR_TXPERBITRANK0_Lane3_MSK (0x0000F000) + #define DDRDATA1CH1_CR_TXPERBITRANK0_Lane3_MAX (0x0000000F) + #define DDRDATA1CH1_CR_TXPERBITRANK0_Lane4_OFF (16) + #define DDRDATA1CH1_CR_TXPERBITRANK0_Lane4_WID ( 4) + #define DDRDATA1CH1_CR_TXPERBITRANK0_Lane4_MSK (0x000F0000) + #define DDRDATA1CH1_CR_TXPERBITRANK0_Lane4_MAX (0x0000000F) + #define DDRDATA1CH1_CR_TXPERBITRANK0_Lane5_OFF (20) + #define DDRDATA1CH1_CR_TXPERBITRANK0_Lane5_WID ( 4) + #define DDRDATA1CH1_CR_TXPERBITRANK0_Lane5_MSK (0x00F00000) + #define DDRDATA1CH1_CR_TXPERBITRANK0_Lane5_MAX (0x0000000F) + #define DDRDATA1CH1_CR_TXPERBITRANK0_Lane6_OFF (24) + #define DDRDATA1CH1_CR_TXPERBITRANK0_Lane6_WID ( 4) + #define DDRDATA1CH1_CR_TXPERBITRANK0_Lane6_MSK (0x0F000000) + #define DDRDATA1CH1_CR_TXPERBITRANK0_Lane6_MAX (0x0000000F) + #define DDRDATA1CH1_CR_TXPERBITRANK0_Lane7_OFF (28) + #define DDRDATA1CH1_CR_TXPERBITRANK0_Lane7_WID ( 4) + #define DDRDATA1CH1_CR_TXPERBITRANK0_Lane7_MSK (0xF0000000) + #define DDRDATA1CH1_CR_TXPERBITRANK0_Lane7_MAX (0x0000000F) + +#define DDRDATA1CH1_CR_TXPERBITRANK1_REG (0x00000334) + #define DDRDATA1CH1_CR_TXPERBITRANK1_Lane0_OFF ( 0) + #define DDRDATA1CH1_CR_TXPERBITRANK1_Lane0_WID ( 4) + #define DDRDATA1CH1_CR_TXPERBITRANK1_Lane0_MSK (0x0000000F) + #define DDRDATA1CH1_CR_TXPERBITRANK1_Lane0_MAX (0x0000000F) + #define DDRDATA1CH1_CR_TXPERBITRANK1_Lane1_OFF ( 4) + #define DDRDATA1CH1_CR_TXPERBITRANK1_Lane1_WID ( 4) + #define DDRDATA1CH1_CR_TXPERBITRANK1_Lane1_MSK (0x000000F0) + #define DDRDATA1CH1_CR_TXPERBITRANK1_Lane1_MAX (0x0000000F) + #define DDRDATA1CH1_CR_TXPERBITRANK1_Lane2_OFF ( 8) + #define DDRDATA1CH1_CR_TXPERBITRANK1_Lane2_WID ( 4) + #define DDRDATA1CH1_CR_TXPERBITRANK1_Lane2_MSK (0x00000F00) + #define DDRDATA1CH1_CR_TXPERBITRANK1_Lane2_MAX (0x0000000F) + #define DDRDATA1CH1_CR_TXPERBITRANK1_Lane3_OFF (12) + #define DDRDATA1CH1_CR_TXPERBITRANK1_Lane3_WID ( 4) + #define DDRDATA1CH1_CR_TXPERBITRANK1_Lane3_MSK (0x0000F000) + #define DDRDATA1CH1_CR_TXPERBITRANK1_Lane3_MAX (0x0000000F) + #define DDRDATA1CH1_CR_TXPERBITRANK1_Lane4_OFF (16) + #define DDRDATA1CH1_CR_TXPERBITRANK1_Lane4_WID ( 4) + #define DDRDATA1CH1_CR_TXPERBITRANK1_Lane4_MSK (0x000F0000) + #define DDRDATA1CH1_CR_TXPERBITRANK1_Lane4_MAX (0x0000000F) + #define DDRDATA1CH1_CR_TXPERBITRANK1_Lane5_OFF (20) + #define DDRDATA1CH1_CR_TXPERBITRANK1_Lane5_WID ( 4) + #define DDRDATA1CH1_CR_TXPERBITRANK1_Lane5_MSK (0x00F00000) + #define DDRDATA1CH1_CR_TXPERBITRANK1_Lane5_MAX (0x0000000F) + #define DDRDATA1CH1_CR_TXPERBITRANK1_Lane6_OFF (24) + #define DDRDATA1CH1_CR_TXPERBITRANK1_Lane6_WID ( 4) + #define DDRDATA1CH1_CR_TXPERBITRANK1_Lane6_MSK (0x0F000000) + #define DDRDATA1CH1_CR_TXPERBITRANK1_Lane6_MAX (0x0000000F) + #define DDRDATA1CH1_CR_TXPERBITRANK1_Lane7_OFF (28) + #define DDRDATA1CH1_CR_TXPERBITRANK1_Lane7_WID ( 4) + #define DDRDATA1CH1_CR_TXPERBITRANK1_Lane7_MSK (0xF0000000) + #define DDRDATA1CH1_CR_TXPERBITRANK1_Lane7_MAX (0x0000000F) + +#define DDRDATA1CH1_CR_TXPERBITRANK2_REG (0x00000338) + #define DDRDATA1CH1_CR_TXPERBITRANK2_Lane0_OFF ( 0) + #define DDRDATA1CH1_CR_TXPERBITRANK2_Lane0_WID ( 4) + #define DDRDATA1CH1_CR_TXPERBITRANK2_Lane0_MSK (0x0000000F) + #define DDRDATA1CH1_CR_TXPERBITRANK2_Lane0_MAX (0x0000000F) + #define DDRDATA1CH1_CR_TXPERBITRANK2_Lane1_OFF ( 4) + #define DDRDATA1CH1_CR_TXPERBITRANK2_Lane1_WID ( 4) + #define DDRDATA1CH1_CR_TXPERBITRANK2_Lane1_MSK (0x000000F0) + #define DDRDATA1CH1_CR_TXPERBITRANK2_Lane1_MAX (0x0000000F) + #define DDRDATA1CH1_CR_TXPERBITRANK2_Lane2_OFF ( 8) + #define DDRDATA1CH1_CR_TXPERBITRANK2_Lane2_WID ( 4) + #define DDRDATA1CH1_CR_TXPERBITRANK2_Lane2_MSK (0x00000F00) + #define DDRDATA1CH1_CR_TXPERBITRANK2_Lane2_MAX (0x0000000F) + #define DDRDATA1CH1_CR_TXPERBITRANK2_Lane3_OFF (12) + #define DDRDATA1CH1_CR_TXPERBITRANK2_Lane3_WID ( 4) + #define DDRDATA1CH1_CR_TXPERBITRANK2_Lane3_MSK (0x0000F000) + #define DDRDATA1CH1_CR_TXPERBITRANK2_Lane3_MAX (0x0000000F) + #define DDRDATA1CH1_CR_TXPERBITRANK2_Lane4_OFF (16) + #define DDRDATA1CH1_CR_TXPERBITRANK2_Lane4_WID ( 4) + #define DDRDATA1CH1_CR_TXPERBITRANK2_Lane4_MSK (0x000F0000) + #define DDRDATA1CH1_CR_TXPERBITRANK2_Lane4_MAX (0x0000000F) + #define DDRDATA1CH1_CR_TXPERBITRANK2_Lane5_OFF (20) + #define DDRDATA1CH1_CR_TXPERBITRANK2_Lane5_WID ( 4) + #define DDRDATA1CH1_CR_TXPERBITRANK2_Lane5_MSK (0x00F00000) + #define DDRDATA1CH1_CR_TXPERBITRANK2_Lane5_MAX (0x0000000F) + #define DDRDATA1CH1_CR_TXPERBITRANK2_Lane6_OFF (24) + #define DDRDATA1CH1_CR_TXPERBITRANK2_Lane6_WID ( 4) + #define DDRDATA1CH1_CR_TXPERBITRANK2_Lane6_MSK (0x0F000000) + #define DDRDATA1CH1_CR_TXPERBITRANK2_Lane6_MAX (0x0000000F) + #define DDRDATA1CH1_CR_TXPERBITRANK2_Lane7_OFF (28) + #define DDRDATA1CH1_CR_TXPERBITRANK2_Lane7_WID ( 4) + #define DDRDATA1CH1_CR_TXPERBITRANK2_Lane7_MSK (0xF0000000) + #define DDRDATA1CH1_CR_TXPERBITRANK2_Lane7_MAX (0x0000000F) + +#define DDRDATA1CH1_CR_TXPERBITRANK3_REG (0x0000033C) + #define DDRDATA1CH1_CR_TXPERBITRANK3_Lane0_OFF ( 0) + #define DDRDATA1CH1_CR_TXPERBITRANK3_Lane0_WID ( 4) + #define DDRDATA1CH1_CR_TXPERBITRANK3_Lane0_MSK (0x0000000F) + #define DDRDATA1CH1_CR_TXPERBITRANK3_Lane0_MAX (0x0000000F) + #define DDRDATA1CH1_CR_TXPERBITRANK3_Lane1_OFF ( 4) + #define DDRDATA1CH1_CR_TXPERBITRANK3_Lane1_WID ( 4) + #define DDRDATA1CH1_CR_TXPERBITRANK3_Lane1_MSK (0x000000F0) + #define DDRDATA1CH1_CR_TXPERBITRANK3_Lane1_MAX (0x0000000F) + #define DDRDATA1CH1_CR_TXPERBITRANK3_Lane2_OFF ( 8) + #define DDRDATA1CH1_CR_TXPERBITRANK3_Lane2_WID ( 4) + #define DDRDATA1CH1_CR_TXPERBITRANK3_Lane2_MSK (0x00000F00) + #define DDRDATA1CH1_CR_TXPERBITRANK3_Lane2_MAX (0x0000000F) + #define DDRDATA1CH1_CR_TXPERBITRANK3_Lane3_OFF (12) + #define DDRDATA1CH1_CR_TXPERBITRANK3_Lane3_WID ( 4) + #define DDRDATA1CH1_CR_TXPERBITRANK3_Lane3_MSK (0x0000F000) + #define DDRDATA1CH1_CR_TXPERBITRANK3_Lane3_MAX (0x0000000F) + #define DDRDATA1CH1_CR_TXPERBITRANK3_Lane4_OFF (16) + #define DDRDATA1CH1_CR_TXPERBITRANK3_Lane4_WID ( 4) + #define DDRDATA1CH1_CR_TXPERBITRANK3_Lane4_MSK (0x000F0000) + #define DDRDATA1CH1_CR_TXPERBITRANK3_Lane4_MAX (0x0000000F) + #define DDRDATA1CH1_CR_TXPERBITRANK3_Lane5_OFF (20) + #define DDRDATA1CH1_CR_TXPERBITRANK3_Lane5_WID ( 4) + #define DDRDATA1CH1_CR_TXPERBITRANK3_Lane5_MSK (0x00F00000) + #define DDRDATA1CH1_CR_TXPERBITRANK3_Lane5_MAX (0x0000000F) + #define DDRDATA1CH1_CR_TXPERBITRANK3_Lane6_OFF (24) + #define DDRDATA1CH1_CR_TXPERBITRANK3_Lane6_WID ( 4) + #define DDRDATA1CH1_CR_TXPERBITRANK3_Lane6_MSK (0x0F000000) + #define DDRDATA1CH1_CR_TXPERBITRANK3_Lane6_MAX (0x0000000F) + #define DDRDATA1CH1_CR_TXPERBITRANK3_Lane7_OFF (28) + #define DDRDATA1CH1_CR_TXPERBITRANK3_Lane7_WID ( 4) + #define DDRDATA1CH1_CR_TXPERBITRANK3_Lane7_MSK (0xF0000000) + #define DDRDATA1CH1_CR_TXPERBITRANK3_Lane7_MAX (0x0000000F) + +#define DDRDATA1CH1_CR_RCOMPDATA0_REG (0x00000340) + #define DDRDATA1CH1_CR_RCOMPDATA0_RcompDrvUp_OFF ( 0) + #define DDRDATA1CH1_CR_RCOMPDATA0_RcompDrvUp_WID ( 6) + #define DDRDATA1CH1_CR_RCOMPDATA0_RcompDrvUp_MSK (0x0000003F) + #define DDRDATA1CH1_CR_RCOMPDATA0_RcompDrvUp_MAX (0x0000003F) + #define DDRDATA1CH1_CR_RCOMPDATA0_Spare0_OFF ( 6) + #define DDRDATA1CH1_CR_RCOMPDATA0_Spare0_WID ( 3) + #define DDRDATA1CH1_CR_RCOMPDATA0_Spare0_MSK (0x000001C0) + #define DDRDATA1CH1_CR_RCOMPDATA0_Spare0_MAX (0x00000007) + #define DDRDATA1CH1_CR_RCOMPDATA0_RcompDrvDown_OFF ( 9) + #define DDRDATA1CH1_CR_RCOMPDATA0_RcompDrvDown_WID ( 6) + #define DDRDATA1CH1_CR_RCOMPDATA0_RcompDrvDown_MSK (0x00007E00) + #define DDRDATA1CH1_CR_RCOMPDATA0_RcompDrvDown_MAX (0x0000003F) + #define DDRDATA1CH1_CR_RCOMPDATA0_VTComp_OFF (15) + #define DDRDATA1CH1_CR_RCOMPDATA0_VTComp_WID ( 5) + #define DDRDATA1CH1_CR_RCOMPDATA0_VTComp_MSK (0x000F8000) + #define DDRDATA1CH1_CR_RCOMPDATA0_VTComp_MAX (0x0000001F) + #define DDRDATA1CH1_CR_RCOMPDATA0_TcoComp_OFF (20) + #define DDRDATA1CH1_CR_RCOMPDATA0_TcoComp_WID ( 6) + #define DDRDATA1CH1_CR_RCOMPDATA0_TcoComp_MSK (0x03F00000) + #define DDRDATA1CH1_CR_RCOMPDATA0_TcoComp_MAX (0x0000003F) + #define DDRDATA1CH1_CR_RCOMPDATA0_SlewRateComp_OFF (26) + #define DDRDATA1CH1_CR_RCOMPDATA0_SlewRateComp_WID ( 5) + #define DDRDATA1CH1_CR_RCOMPDATA0_SlewRateComp_MSK (0x7C000000) + #define DDRDATA1CH1_CR_RCOMPDATA0_SlewRateComp_MAX (0x0000001F) + #define DDRDATA1CH1_CR_RCOMPDATA0_Spare2_OFF (31) + #define DDRDATA1CH1_CR_RCOMPDATA0_Spare2_WID ( 1) + #define DDRDATA1CH1_CR_RCOMPDATA0_Spare2_MSK (0x80000000) + #define DDRDATA1CH1_CR_RCOMPDATA0_Spare2_MAX (0x00000001) + +#define DDRDATA1CH1_CR_RCOMPDATA1_REG (0x00000344) + #define DDRDATA1CH1_CR_RCOMPDATA1_RcompOdtUp_OFF ( 0) + #define DDRDATA1CH1_CR_RCOMPDATA1_RcompOdtUp_WID ( 6) + #define DDRDATA1CH1_CR_RCOMPDATA1_RcompOdtUp_MSK (0x0000003F) + #define DDRDATA1CH1_CR_RCOMPDATA1_RcompOdtUp_MAX (0x0000003F) + #define DDRDATA1CH1_CR_RCOMPDATA1_Spare0_OFF ( 6) + #define DDRDATA1CH1_CR_RCOMPDATA1_Spare0_WID ( 3) + #define DDRDATA1CH1_CR_RCOMPDATA1_Spare0_MSK (0x000001C0) + #define DDRDATA1CH1_CR_RCOMPDATA1_Spare0_MAX (0x00000007) + #define DDRDATA1CH1_CR_RCOMPDATA1_RcompOdtDown_OFF ( 9) + #define DDRDATA1CH1_CR_RCOMPDATA1_RcompOdtDown_WID ( 6) + #define DDRDATA1CH1_CR_RCOMPDATA1_RcompOdtDown_MSK (0x00007E00) + #define DDRDATA1CH1_CR_RCOMPDATA1_RcompOdtDown_MAX (0x0000003F) + #define DDRDATA1CH1_CR_RCOMPDATA1_Spare1_OFF (15) + #define DDRDATA1CH1_CR_RCOMPDATA1_Spare1_WID ( 1) + #define DDRDATA1CH1_CR_RCOMPDATA1_Spare1_MSK (0x00008000) + #define DDRDATA1CH1_CR_RCOMPDATA1_Spare1_MAX (0x00000001) + #define DDRDATA1CH1_CR_RCOMPDATA1_PanicDrvDn_OFF (16) + #define DDRDATA1CH1_CR_RCOMPDATA1_PanicDrvDn_WID ( 6) + #define DDRDATA1CH1_CR_RCOMPDATA1_PanicDrvDn_MSK (0x003F0000) + #define DDRDATA1CH1_CR_RCOMPDATA1_PanicDrvDn_MAX (0x0000003F) + #define DDRDATA1CH1_CR_RCOMPDATA1_PanicDrvUp_OFF (22) + #define DDRDATA1CH1_CR_RCOMPDATA1_PanicDrvUp_WID ( 6) + #define DDRDATA1CH1_CR_RCOMPDATA1_PanicDrvUp_MSK (0x0FC00000) + #define DDRDATA1CH1_CR_RCOMPDATA1_PanicDrvUp_MAX (0x0000003F) + #define DDRDATA1CH1_CR_RCOMPDATA1_LevelShifterComp_OFF (28) + #define DDRDATA1CH1_CR_RCOMPDATA1_LevelShifterComp_WID ( 3) + #define DDRDATA1CH1_CR_RCOMPDATA1_LevelShifterComp_MSK (0x70000000) + #define DDRDATA1CH1_CR_RCOMPDATA1_LevelShifterComp_MAX (0x00000007) + #define DDRDATA1CH1_CR_RCOMPDATA1_Spare2_OFF (31) + #define DDRDATA1CH1_CR_RCOMPDATA1_Spare2_WID ( 1) + #define DDRDATA1CH1_CR_RCOMPDATA1_Spare2_MSK (0x80000000) + #define DDRDATA1CH1_CR_RCOMPDATA1_Spare2_MAX (0x00000001) + +#define DDRDATA1CH1_CR_TXXTALK_REG (0x00000348) + #define DDRDATA1CH1_CR_TXXTALK_Lane0_OFF ( 0) + #define DDRDATA1CH1_CR_TXXTALK_Lane0_WID ( 4) + #define DDRDATA1CH1_CR_TXXTALK_Lane0_MSK (0x0000000F) + #define DDRDATA1CH1_CR_TXXTALK_Lane0_MAX (0x0000000F) + #define DDRDATA1CH1_CR_TXXTALK_Lane1_OFF ( 4) + #define DDRDATA1CH1_CR_TXXTALK_Lane1_WID ( 4) + #define DDRDATA1CH1_CR_TXXTALK_Lane1_MSK (0x000000F0) + #define DDRDATA1CH1_CR_TXXTALK_Lane1_MAX (0x0000000F) + #define DDRDATA1CH1_CR_TXXTALK_Lane2_OFF ( 8) + #define DDRDATA1CH1_CR_TXXTALK_Lane2_WID ( 4) + #define DDRDATA1CH1_CR_TXXTALK_Lane2_MSK (0x00000F00) + #define DDRDATA1CH1_CR_TXXTALK_Lane2_MAX (0x0000000F) + #define DDRDATA1CH1_CR_TXXTALK_Lane3_OFF (12) + #define DDRDATA1CH1_CR_TXXTALK_Lane3_WID ( 4) + #define DDRDATA1CH1_CR_TXXTALK_Lane3_MSK (0x0000F000) + #define DDRDATA1CH1_CR_TXXTALK_Lane3_MAX (0x0000000F) + #define DDRDATA1CH1_CR_TXXTALK_Lane4_OFF (16) + #define DDRDATA1CH1_CR_TXXTALK_Lane4_WID ( 4) + #define DDRDATA1CH1_CR_TXXTALK_Lane4_MSK (0x000F0000) + #define DDRDATA1CH1_CR_TXXTALK_Lane4_MAX (0x0000000F) + #define DDRDATA1CH1_CR_TXXTALK_Lane5_OFF (20) + #define DDRDATA1CH1_CR_TXXTALK_Lane5_WID ( 4) + #define DDRDATA1CH1_CR_TXXTALK_Lane5_MSK (0x00F00000) + #define DDRDATA1CH1_CR_TXXTALK_Lane5_MAX (0x0000000F) + #define DDRDATA1CH1_CR_TXXTALK_Lane6_OFF (24) + #define DDRDATA1CH1_CR_TXXTALK_Lane6_WID ( 4) + #define DDRDATA1CH1_CR_TXXTALK_Lane6_MSK (0x0F000000) + #define DDRDATA1CH1_CR_TXXTALK_Lane6_MAX (0x0000000F) + #define DDRDATA1CH1_CR_TXXTALK_Lane7_OFF (28) + #define DDRDATA1CH1_CR_TXXTALK_Lane7_WID ( 4) + #define DDRDATA1CH1_CR_TXXTALK_Lane7_MSK (0xF0000000) + #define DDRDATA1CH1_CR_TXXTALK_Lane7_MAX (0x0000000F) + +#define DDRDATA1CH1_CR_RXOFFSETVDQ_REG (0x0000034C) + #define DDRDATA1CH1_CR_RXOFFSETVDQ_Lane0_OFF ( 0) + #define DDRDATA1CH1_CR_RXOFFSETVDQ_Lane0_WID ( 4) + #define DDRDATA1CH1_CR_RXOFFSETVDQ_Lane0_MSK (0x0000000F) + #define DDRDATA1CH1_CR_RXOFFSETVDQ_Lane0_MAX (0x0000000F) + #define DDRDATA1CH1_CR_RXOFFSETVDQ_Lane1_OFF ( 4) + #define DDRDATA1CH1_CR_RXOFFSETVDQ_Lane1_WID ( 4) + #define DDRDATA1CH1_CR_RXOFFSETVDQ_Lane1_MSK (0x000000F0) + #define DDRDATA1CH1_CR_RXOFFSETVDQ_Lane1_MAX (0x0000000F) + #define DDRDATA1CH1_CR_RXOFFSETVDQ_Lane2_OFF ( 8) + #define DDRDATA1CH1_CR_RXOFFSETVDQ_Lane2_WID ( 4) + #define DDRDATA1CH1_CR_RXOFFSETVDQ_Lane2_MSK (0x00000F00) + #define DDRDATA1CH1_CR_RXOFFSETVDQ_Lane2_MAX (0x0000000F) + #define DDRDATA1CH1_CR_RXOFFSETVDQ_Lane3_OFF (12) + #define DDRDATA1CH1_CR_RXOFFSETVDQ_Lane3_WID ( 4) + #define DDRDATA1CH1_CR_RXOFFSETVDQ_Lane3_MSK (0x0000F000) + #define DDRDATA1CH1_CR_RXOFFSETVDQ_Lane3_MAX (0x0000000F) + #define DDRDATA1CH1_CR_RXOFFSETVDQ_Lane4_OFF (16) + #define DDRDATA1CH1_CR_RXOFFSETVDQ_Lane4_WID ( 4) + #define DDRDATA1CH1_CR_RXOFFSETVDQ_Lane4_MSK (0x000F0000) + #define DDRDATA1CH1_CR_RXOFFSETVDQ_Lane4_MAX (0x0000000F) + #define DDRDATA1CH1_CR_RXOFFSETVDQ_Lane5_OFF (20) + #define DDRDATA1CH1_CR_RXOFFSETVDQ_Lane5_WID ( 4) + #define DDRDATA1CH1_CR_RXOFFSETVDQ_Lane5_MSK (0x00F00000) + #define DDRDATA1CH1_CR_RXOFFSETVDQ_Lane5_MAX (0x0000000F) + #define DDRDATA1CH1_CR_RXOFFSETVDQ_Lane6_OFF (24) + #define DDRDATA1CH1_CR_RXOFFSETVDQ_Lane6_WID ( 4) + #define DDRDATA1CH1_CR_RXOFFSETVDQ_Lane6_MSK (0x0F000000) + #define DDRDATA1CH1_CR_RXOFFSETVDQ_Lane6_MAX (0x0000000F) + #define DDRDATA1CH1_CR_RXOFFSETVDQ_Lane7_OFF (28) + #define DDRDATA1CH1_CR_RXOFFSETVDQ_Lane7_WID ( 4) + #define DDRDATA1CH1_CR_RXOFFSETVDQ_Lane7_MSK (0xF0000000) + #define DDRDATA1CH1_CR_RXOFFSETVDQ_Lane7_MAX (0x0000000F) + +#define DDRDATA1CH1_CR_DDRDATARESERVED_REG (0x00000350) + #define DDRDATA1CH1_CR_DDRDATARESERVED_Spare_OFF ( 0) + #define DDRDATA1CH1_CR_DDRDATARESERVED_Spare_WID (32) + #define DDRDATA1CH1_CR_DDRDATARESERVED_Spare_MSK (0xFFFFFFFF) + #define DDRDATA1CH1_CR_DDRDATARESERVED_Spare_MAX (0xFFFFFFFF) + +#define DDRDATA1CH1_CR_DATATRAINFEEDBACK_REG (0x00000354) + #define DDRDATA1CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_OFF ( 0) + #define DDRDATA1CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_WID ( 9) + #define DDRDATA1CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_MSK (0x000001FF) + #define DDRDATA1CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_MAX (0x000001FF) + #define DDRDATA1CH1_CR_DATATRAINFEEDBACK_Spare_OFF ( 9) + #define DDRDATA1CH1_CR_DATATRAINFEEDBACK_Spare_WID (23) + #define DDRDATA1CH1_CR_DATATRAINFEEDBACK_Spare_MSK (0xFFFFFE00) + #define DDRDATA1CH1_CR_DATATRAINFEEDBACK_Spare_MAX (0x007FFFFF) + +#define DDRDATA1CH1_CR_DLLPITESTANDADC_REG (0x00000358) + #define DDRDATA1CH1_CR_DLLPITESTANDADC_RunTest_OFF ( 0) + #define DDRDATA1CH1_CR_DLLPITESTANDADC_RunTest_WID ( 1) + #define DDRDATA1CH1_CR_DLLPITESTANDADC_RunTest_MSK (0x00000001) + #define DDRDATA1CH1_CR_DLLPITESTANDADC_RunTest_MAX (0x00000001) + #define DDRDATA1CH1_CR_DLLPITESTANDADC_RunTest_DEF (0x00000000) + #define DDRDATA1CH1_CR_DLLPITESTANDADC_Load_OFF ( 1) + #define DDRDATA1CH1_CR_DLLPITESTANDADC_Load_WID ( 1) + #define DDRDATA1CH1_CR_DLLPITESTANDADC_Load_MSK (0x00000002) + #define DDRDATA1CH1_CR_DLLPITESTANDADC_Load_MAX (0x00000001) + #define DDRDATA1CH1_CR_DLLPITESTANDADC_Load_DEF (0x00000000) + #define DDRDATA1CH1_CR_DLLPITESTANDADC_ModeHVM_OFF ( 2) + #define DDRDATA1CH1_CR_DLLPITESTANDADC_ModeHVM_WID ( 1) + #define DDRDATA1CH1_CR_DLLPITESTANDADC_ModeHVM_MSK (0x00000004) + #define DDRDATA1CH1_CR_DLLPITESTANDADC_ModeHVM_MAX (0x00000001) + #define DDRDATA1CH1_CR_DLLPITESTANDADC_ModeHVM_DEF (0x00000000) + #define DDRDATA1CH1_CR_DLLPITESTANDADC_ModeDV_OFF ( 3) + #define DDRDATA1CH1_CR_DLLPITESTANDADC_ModeDV_WID ( 1) + #define DDRDATA1CH1_CR_DLLPITESTANDADC_ModeDV_MSK (0x00000008) + #define DDRDATA1CH1_CR_DLLPITESTANDADC_ModeDV_MAX (0x00000001) + #define DDRDATA1CH1_CR_DLLPITESTANDADC_ModeDV_DEF (0x00000000) + #define DDRDATA1CH1_CR_DLLPITESTANDADC_ModeADC_OFF ( 4) + #define DDRDATA1CH1_CR_DLLPITESTANDADC_ModeADC_WID ( 1) + #define DDRDATA1CH1_CR_DLLPITESTANDADC_ModeADC_MSK (0x00000010) + #define DDRDATA1CH1_CR_DLLPITESTANDADC_ModeADC_MAX (0x00000001) + #define DDRDATA1CH1_CR_DLLPITESTANDADC_ModeADC_DEF (0x00000000) + #define DDRDATA1CH1_CR_DLLPITESTANDADC_LoadCount_OFF ( 5) + #define DDRDATA1CH1_CR_DLLPITESTANDADC_LoadCount_WID (10) + #define DDRDATA1CH1_CR_DLLPITESTANDADC_LoadCount_MSK (0x00007FE0) + #define DDRDATA1CH1_CR_DLLPITESTANDADC_LoadCount_MAX (0x000003FF) + #define DDRDATA1CH1_CR_DLLPITESTANDADC_CountStatus_OFF (15) + #define DDRDATA1CH1_CR_DLLPITESTANDADC_CountStatus_WID (10) + #define DDRDATA1CH1_CR_DLLPITESTANDADC_CountStatus_MSK (0x01FF8000) + #define DDRDATA1CH1_CR_DLLPITESTANDADC_CountStatus_MAX (0x000003FF) + #define DDRDATA1CH1_CR_DLLPITESTANDADC_CountStatus_DEF (0x00000000) + #define DDRDATA1CH1_CR_DLLPITESTANDADC_Spare_OFF (25) + #define DDRDATA1CH1_CR_DLLPITESTANDADC_Spare_WID ( 7) + #define DDRDATA1CH1_CR_DLLPITESTANDADC_Spare_MSK (0xFE000000) + #define DDRDATA1CH1_CR_DLLPITESTANDADC_Spare_MAX (0x0000007F) + +#define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_REG (0x0000035C) + #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_OFF ( 0) + #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_WID ( 6) + #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MSK (0x0000003F) + #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MAX (0x0000003F) + #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_DEF (0x00000000) + #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_OFF ( 6) + #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_WID ( 6) + #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MSK (0x00000FC0) + #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MAX (0x0000003F) + #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_DEF (0x00000000) + #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_OFF (12) + #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_WID ( 5) + #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MSK (0x0001F000) + #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MAX (0x0000001F) + #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_DEF (0x00000000) + #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_OFF (17) + #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_WID ( 5) + #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MSK (0x003E0000) + #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MAX (0x0000001F) + #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_DEF (0x00000000) + #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_OFF (22) + #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_WID ( 5) + #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_MSK (0x07C00000) + #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_MAX (0x0000001F) + #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_DEF (0x00000000) + #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_OFF (27) + #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_WID ( 5) + #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MSK (0xF8000000) + #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MAX (0x0000001F) + #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_DEF (0x00000000) + +#define DDRDATA1CH1_CR_DDRCRDATACONTROL1_REG (0x00000360) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_RefPi_OFF ( 0) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_RefPi_WID ( 4) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_RefPi_MSK (0x0000000F) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_RefPi_MAX (0x0000000F) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_RefPi_DEF (0x00000000) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_DllMask_OFF ( 4) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_DllMask_WID ( 2) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_DllMask_MSK (0x00000030) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_DllMask_MAX (0x00000003) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_DllMask_DEF (0x00000000) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_DllWeakLock_OFF ( 6) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_DllWeakLock_WID ( 1) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_DllWeakLock_MSK (0x00000040) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_DllWeakLock_MAX (0x00000001) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_DllWeakLock_DEF (0x00000000) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_OFF ( 7) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_WID ( 3) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MSK (0x00000380) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MAX (0x00000007) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_DEF (0x00000000) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_OFF (10) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_WID ( 3) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_MSK (0x00001C00) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_MAX (0x00000007) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_DEF (0x00000000) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_OdtDelay_OFF (13) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_OdtDelay_WID ( 4) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_OdtDelay_MSK (0x0001E000) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_OdtDelay_MAX (0x0000000F) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_OdtDelay_DEF (0x00000000) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_OdtDuration_OFF (17) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_OdtDuration_WID ( 3) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_OdtDuration_MSK (0x000E0000) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_OdtDuration_MAX (0x00000007) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_OdtDuration_DEF (0x00000000) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_OFF (20) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_WID ( 4) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_MSK (0x00F00000) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_MAX (0x0000000F) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_DEF (0x00000000) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_OFF (24) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_WID ( 3) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_MSK (0x07000000) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_MAX (0x00000007) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_DEF (0x00000000) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_OFF (27) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_WID ( 3) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_MSK (0x38000000) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_MAX (0x00000007) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_DEF (0x00000000) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_OFF (30) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_WID ( 1) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_MSK (0x40000000) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_MAX (0x00000001) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_DEF (0x00000000) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_Rsvd1_OFF (31) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_Rsvd1_WID ( 1) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_Rsvd1_MSK (0x80000000) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_Rsvd1_MAX (0x00000001) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_Rsvd1_DEF (0x00000000) + +#define DDRDATA1CH1_CR_DDRCRDATACONTROL2_REG (0x00000364) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_OFF ( 0) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_WID ( 5) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_MSK (0x0000001F) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_MAX (0x0000001F) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_DEF (0x00000000) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_OFF ( 5) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_WID ( 1) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_MSK (0x00000020) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_MAX (0x00000001) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_DEF (0x00000000) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_ForceRxOn_OFF ( 6) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_ForceRxOn_WID ( 1) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_ForceRxOn_MSK (0x00000040) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_ForceRxOn_MAX (0x00000001) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_ForceRxOn_DEF (0x00000000) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_LeakerComp_OFF ( 7) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_LeakerComp_WID ( 2) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_LeakerComp_MSK (0x00000180) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_LeakerComp_MAX (0x00000003) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_LeakerComp_DEF (0x00000000) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_OFF ( 9) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_WID ( 4) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_MSK (0x00001E00) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_MAX (0x0000000F) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_DEF (0x00000008) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_OFF (13) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_WID ( 5) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_MSK (0x0003E000) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_MAX (0x0000001F) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_DEF (0x00000011) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_OFF (18) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_WID ( 1) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_MSK (0x00040000) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_MAX (0x00000001) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_DEF (0x00000000) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_Spare_OFF (19) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_Spare_WID (13) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_Spare_MSK (0xFFF80000) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_Spare_MAX (0x00001FFF) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_Spare_DEF (0x00000000) + +#define DDRDATA1CH1_CR_DDRCRVSSHIORVREFCONTROL_REG (0x0000036C) + #define DDRDATA1CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_OFF ( 0) + #define DDRDATA1CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_WID (24) + #define DDRDATA1CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_MSK (0x00FFFFFF) + #define DDRDATA1CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_MAX (0x00FFFFFF) + #define DDRDATA1CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_DEF (0x00000000) + #define DDRDATA1CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_OFF (24) + #define DDRDATA1CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_WID ( 8) + #define DDRDATA1CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_MSK (0xFF000000) + #define DDRDATA1CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_MAX (0x000000FF) + #define DDRDATA1CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_DEF (0x00000000) + +#define DDRDATA1CH1_CR_DDRCRDATAOFFSETTRAIN_REG (0x00000370) + #define DDRDATA1CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_OFF ( 0) + #define DDRDATA1CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_WID ( 6) + #define DDRDATA1CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MSK (0x0000003F) + #define DDRDATA1CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MAX (0x0000003F) + #define DDRDATA1CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_DEF (0x00000000) + #define DDRDATA1CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_OFF ( 6) + #define DDRDATA1CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_WID ( 6) + #define DDRDATA1CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MSK (0x00000FC0) + #define DDRDATA1CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MAX (0x0000003F) + #define DDRDATA1CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_DEF (0x00000000) + #define DDRDATA1CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_OFF (12) + #define DDRDATA1CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_WID ( 6) + #define DDRDATA1CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MSK (0x0003F000) + #define DDRDATA1CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MAX (0x0000003F) + #define DDRDATA1CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_DEF (0x00000000) + #define DDRDATA1CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_OFF (18) + #define DDRDATA1CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_WID ( 6) + #define DDRDATA1CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MSK (0x00FC0000) + #define DDRDATA1CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MAX (0x0000003F) + #define DDRDATA1CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_DEF (0x00000000) + #define DDRDATA1CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_OFF (24) + #define DDRDATA1CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_WID ( 7) + #define DDRDATA1CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MSK (0x7F000000) + #define DDRDATA1CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MAX (0x0000007F) + #define DDRDATA1CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_DEF (0x00000000) + #define DDRDATA1CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_OFF (31) + #define DDRDATA1CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_WID ( 1) + #define DDRDATA1CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_MSK (0x80000000) + #define DDRDATA1CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_MAX (0x00000001) + #define DDRDATA1CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_DEF (0x00000000) + +#define DDRDATA1CH1_CR_DDRCRDATACONTROL0_REG (0x00000374) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_OFF ( 0) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_WID ( 1) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_MSK (0x00000001) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_MAX (0x00000001) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_DEF (0x00000000) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_OFF ( 1) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_WID ( 1) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_MSK (0x00000002) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_MAX (0x00000001) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_DEF (0x00000000) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_OFF ( 2) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_WID ( 1) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_MSK (0x00000004) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_MAX (0x00000001) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_DEF (0x00000000) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_OFF ( 3) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_WID ( 1) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MSK (0x00000008) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MAX (0x00000001) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_DEF (0x00000000) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_TxOn_OFF ( 4) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_TxOn_WID ( 1) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_TxOn_MSK (0x00000010) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_TxOn_MAX (0x00000001) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_TxOn_DEF (0x00000000) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RfOn_OFF ( 5) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RfOn_WID ( 1) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RfOn_MSK (0x00000020) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RfOn_MAX (0x00000001) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RfOn_DEF (0x00000000) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RxPiOn_OFF ( 6) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RxPiOn_WID ( 1) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RxPiOn_MSK (0x00000040) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RxPiOn_MAX (0x00000001) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RxPiOn_DEF (0x00000000) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_TxPiOn_OFF ( 7) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_TxPiOn_WID ( 1) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_TxPiOn_MSK (0x00000080) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_TxPiOn_MAX (0x00000001) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_TxPiOn_DEF (0x00000000) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_OFF ( 8) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_WID ( 1) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_MSK (0x00000100) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_MAX (0x00000001) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_DEF (0x00000000) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_OFF ( 9) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_WID ( 1) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MSK (0x00000200) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MAX (0x00000001) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_DEF (0x00000000) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_TxDisable_OFF (10) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_TxDisable_WID ( 1) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_TxDisable_MSK (0x00000400) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_TxDisable_MAX (0x00000001) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_TxDisable_DEF (0x00000000) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RxDisable_OFF (11) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RxDisable_WID ( 1) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RxDisable_MSK (0x00000800) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RxDisable_MAX (0x00000001) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RxDisable_DEF (0x00000000) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_TxLong_OFF (12) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_TxLong_WID ( 1) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_TxLong_MSK (0x00001000) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_TxLong_MAX (0x00000001) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_TxLong_DEF (0x00000000) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_OFF (13) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_WID ( 2) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_MSK (0x00006000) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_MAX (0x00000003) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_DEF (0x00000000) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RxReadPointer_OFF (15) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RxReadPointer_WID ( 3) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RxReadPointer_MSK (0x00038000) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RxReadPointer_MAX (0x00000007) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RxReadPointer_DEF (0x00000000) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_OFF (18) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_WID ( 1) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_MSK (0x00040000) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_MAX (0x00000001) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_DEF (0x00000000) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_OFF (19) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_WID ( 1) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_MSK (0x00080000) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_MAX (0x00000001) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_DEF (0x00000000) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_ReadRFRd_OFF (20) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_ReadRFRd_WID ( 1) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_ReadRFRd_MSK (0x00100000) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_ReadRFRd_MAX (0x00000001) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_ReadRFRd_DEF (0x00000000) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_ReadRFWr_OFF (21) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_ReadRFWr_WID ( 1) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_ReadRFWr_MSK (0x00200000) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_ReadRFWr_MAX (0x00000001) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_ReadRFWr_DEF (0x00000000) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_ReadRFRank_OFF (22) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_ReadRFRank_WID ( 2) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_ReadRFRank_MSK (0x00C00000) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_ReadRFRank_MAX (0x00000003) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_ReadRFRank_DEF (0x00000000) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_OFF (24) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_WID ( 1) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_MSK (0x01000000) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_MAX (0x00000001) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_DEF (0x00000000) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_OdtSampOff_OFF (25) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_OdtSampOff_WID ( 1) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_OdtSampOff_MSK (0x02000000) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_OdtSampOff_MAX (0x00000001) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_OdtSampOff_DEF (0x00000000) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_OFF (26) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_WID ( 1) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_MSK (0x04000000) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_MAX (0x00000001) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_DEF (0x00000000) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_OFF (27) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_WID ( 1) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MSK (0x08000000) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MAX (0x00000001) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_DEF (0x00000000) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_OFF (28) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_WID ( 1) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_MSK (0x10000000) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_MAX (0x00000001) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_DEF (0x00000000) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_OFF (29) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_WID ( 1) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_MSK (0x20000000) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_MAX (0x00000001) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_DEF (0x00000000) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_OFF (30) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_WID ( 1) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MSK (0x40000000) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MAX (0x00000001) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_DEF (0x00000000) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_OFF (31) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_WID ( 1) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_MSK (0x80000000) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_MAX (0x00000001) + #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_DEF (0x00000000) + +#define DDRDATA1CH1_CR_DDRCRVREFADJUST1_REG (0x00000378) + #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_OFF ( 0) + #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_WID ( 7) + #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_MSK (0x0000007F) + #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_MAX (0x0000007F) + #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_DEF (0x00000000) + #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_OFF ( 7) + #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_WID ( 7) + #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_MSK (0x00003F80) + #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_MAX (0x0000007F) + #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_DEF (0x00000000) + #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_OFF (14) + #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_WID ( 7) + #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_MSK (0x001FC000) + #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_MAX (0x0000007F) + #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_DEF (0x00000000) + #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_OFF (21) + #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_WID ( 1) + #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_MSK (0x00200000) + #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_MAX (0x00000001) + #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_DEF (0x00000000) + #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_OFF (22) + #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_WID ( 1) + #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_MSK (0x00400000) + #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_MAX (0x00000001) + #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_DEF (0x00000000) + #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_OFF (23) + #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_WID ( 1) + #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_MSK (0x00800000) + #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_MAX (0x00000001) + #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_DEF (0x00000000) + #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_OFF (24) + #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_WID ( 2) + #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_MSK (0x03000000) + #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_MAX (0x00000003) + #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_DEF (0x00000000) + #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_OFF (26) + #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_WID ( 1) + #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_MSK (0x04000000) + #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_MAX (0x00000001) + #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_DEF (0x00000000) + #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_Rsvd_OFF (27) + #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_Rsvd_WID ( 2) + #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_Rsvd_MSK (0x18000000) + #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_Rsvd_MAX (0x00000003) + #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_Rsvd_DEF (0x00000000) + #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_caSlowBW_OFF (29) + #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_caSlowBW_WID ( 1) + #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_caSlowBW_MSK (0x20000000) + #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_caSlowBW_MAX (0x00000001) + #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_caSlowBW_DEF (0x00000000) + #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_OFF (30) + #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_WID ( 1) + #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_MSK (0x40000000) + #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_MAX (0x00000001) + #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_DEF (0x00000000) + #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_OFF (31) + #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_WID ( 1) + #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_MSK (0x80000000) + #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_MAX (0x00000001) + #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_DEF (0x00000000) + +#define DDRDATA2CH0_CR_RXTRAINRANK0_REG (0x00000400) + #define DDRDATA2CH0_CR_RXTRAINRANK0_RxRcvEnPi_OFF ( 0) + #define DDRDATA2CH0_CR_RXTRAINRANK0_RxRcvEnPi_WID ( 9) + #define DDRDATA2CH0_CR_RXTRAINRANK0_RxRcvEnPi_MSK (0x000001FF) + #define DDRDATA2CH0_CR_RXTRAINRANK0_RxRcvEnPi_MAX (0x000001FF) + #define DDRDATA2CH0_CR_RXTRAINRANK0_RxDqsPPi_OFF ( 9) + #define DDRDATA2CH0_CR_RXTRAINRANK0_RxDqsPPi_WID ( 6) + #define DDRDATA2CH0_CR_RXTRAINRANK0_RxDqsPPi_MSK (0x00007E00) + #define DDRDATA2CH0_CR_RXTRAINRANK0_RxDqsPPi_MAX (0x0000003F) + #define DDRDATA2CH0_CR_RXTRAINRANK0_RxEq_OFF (15) + #define DDRDATA2CH0_CR_RXTRAINRANK0_RxEq_WID ( 5) + #define DDRDATA2CH0_CR_RXTRAINRANK0_RxEq_MSK (0x000F8000) + #define DDRDATA2CH0_CR_RXTRAINRANK0_RxEq_MAX (0x0000001F) + #define DDRDATA2CH0_CR_RXTRAINRANK0_RxDqsNPi_OFF (20) + #define DDRDATA2CH0_CR_RXTRAINRANK0_RxDqsNPi_WID ( 6) + #define DDRDATA2CH0_CR_RXTRAINRANK0_RxDqsNPi_MSK (0x03F00000) + #define DDRDATA2CH0_CR_RXTRAINRANK0_RxDqsNPi_MAX (0x0000003F) + #define DDRDATA2CH0_CR_RXTRAINRANK0_RxVref_OFF (26) + #define DDRDATA2CH0_CR_RXTRAINRANK0_RxVref_WID ( 6) + #define DDRDATA2CH0_CR_RXTRAINRANK0_RxVref_MSK (0xFC000000) + #define DDRDATA2CH0_CR_RXTRAINRANK0_RxVref_MAX (0x0000003F) + +#define DDRDATA2CH0_CR_RXTRAINRANK1_REG (0x00000404) + #define DDRDATA2CH0_CR_RXTRAINRANK1_RxRcvEnPi_OFF ( 0) + #define DDRDATA2CH0_CR_RXTRAINRANK1_RxRcvEnPi_WID ( 9) + #define DDRDATA2CH0_CR_RXTRAINRANK1_RxRcvEnPi_MSK (0x000001FF) + #define DDRDATA2CH0_CR_RXTRAINRANK1_RxRcvEnPi_MAX (0x000001FF) + #define DDRDATA2CH0_CR_RXTRAINRANK1_RxDqsPPi_OFF ( 9) + #define DDRDATA2CH0_CR_RXTRAINRANK1_RxDqsPPi_WID ( 6) + #define DDRDATA2CH0_CR_RXTRAINRANK1_RxDqsPPi_MSK (0x00007E00) + #define DDRDATA2CH0_CR_RXTRAINRANK1_RxDqsPPi_MAX (0x0000003F) + #define DDRDATA2CH0_CR_RXTRAINRANK1_RxEq_OFF (15) + #define DDRDATA2CH0_CR_RXTRAINRANK1_RxEq_WID ( 5) + #define DDRDATA2CH0_CR_RXTRAINRANK1_RxEq_MSK (0x000F8000) + #define DDRDATA2CH0_CR_RXTRAINRANK1_RxEq_MAX (0x0000001F) + #define DDRDATA2CH0_CR_RXTRAINRANK1_RxDqsNPi_OFF (20) + #define DDRDATA2CH0_CR_RXTRAINRANK1_RxDqsNPi_WID ( 6) + #define DDRDATA2CH0_CR_RXTRAINRANK1_RxDqsNPi_MSK (0x03F00000) + #define DDRDATA2CH0_CR_RXTRAINRANK1_RxDqsNPi_MAX (0x0000003F) + #define DDRDATA2CH0_CR_RXTRAINRANK1_RxVref_OFF (26) + #define DDRDATA2CH0_CR_RXTRAINRANK1_RxVref_WID ( 6) + #define DDRDATA2CH0_CR_RXTRAINRANK1_RxVref_MSK (0xFC000000) + #define DDRDATA2CH0_CR_RXTRAINRANK1_RxVref_MAX (0x0000003F) + +#define DDRDATA2CH0_CR_RXTRAINRANK2_REG (0x00000408) + #define DDRDATA2CH0_CR_RXTRAINRANK2_RxRcvEnPi_OFF ( 0) + #define DDRDATA2CH0_CR_RXTRAINRANK2_RxRcvEnPi_WID ( 9) + #define DDRDATA2CH0_CR_RXTRAINRANK2_RxRcvEnPi_MSK (0x000001FF) + #define DDRDATA2CH0_CR_RXTRAINRANK2_RxRcvEnPi_MAX (0x000001FF) + #define DDRDATA2CH0_CR_RXTRAINRANK2_RxDqsPPi_OFF ( 9) + #define DDRDATA2CH0_CR_RXTRAINRANK2_RxDqsPPi_WID ( 6) + #define DDRDATA2CH0_CR_RXTRAINRANK2_RxDqsPPi_MSK (0x00007E00) + #define DDRDATA2CH0_CR_RXTRAINRANK2_RxDqsPPi_MAX (0x0000003F) + #define DDRDATA2CH0_CR_RXTRAINRANK2_RxEq_OFF (15) + #define DDRDATA2CH0_CR_RXTRAINRANK2_RxEq_WID ( 5) + #define DDRDATA2CH0_CR_RXTRAINRANK2_RxEq_MSK (0x000F8000) + #define DDRDATA2CH0_CR_RXTRAINRANK2_RxEq_MAX (0x0000001F) + #define DDRDATA2CH0_CR_RXTRAINRANK2_RxDqsNPi_OFF (20) + #define DDRDATA2CH0_CR_RXTRAINRANK2_RxDqsNPi_WID ( 6) + #define DDRDATA2CH0_CR_RXTRAINRANK2_RxDqsNPi_MSK (0x03F00000) + #define DDRDATA2CH0_CR_RXTRAINRANK2_RxDqsNPi_MAX (0x0000003F) + #define DDRDATA2CH0_CR_RXTRAINRANK2_RxVref_OFF (26) + #define DDRDATA2CH0_CR_RXTRAINRANK2_RxVref_WID ( 6) + #define DDRDATA2CH0_CR_RXTRAINRANK2_RxVref_MSK (0xFC000000) + #define DDRDATA2CH0_CR_RXTRAINRANK2_RxVref_MAX (0x0000003F) + +#define DDRDATA2CH0_CR_RXTRAINRANK3_REG (0x0000040C) + #define DDRDATA2CH0_CR_RXTRAINRANK3_RxRcvEnPi_OFF ( 0) + #define DDRDATA2CH0_CR_RXTRAINRANK3_RxRcvEnPi_WID ( 9) + #define DDRDATA2CH0_CR_RXTRAINRANK3_RxRcvEnPi_MSK (0x000001FF) + #define DDRDATA2CH0_CR_RXTRAINRANK3_RxRcvEnPi_MAX (0x000001FF) + #define DDRDATA2CH0_CR_RXTRAINRANK3_RxDqsPPi_OFF ( 9) + #define DDRDATA2CH0_CR_RXTRAINRANK3_RxDqsPPi_WID ( 6) + #define DDRDATA2CH0_CR_RXTRAINRANK3_RxDqsPPi_MSK (0x00007E00) + #define DDRDATA2CH0_CR_RXTRAINRANK3_RxDqsPPi_MAX (0x0000003F) + #define DDRDATA2CH0_CR_RXTRAINRANK3_RxEq_OFF (15) + #define DDRDATA2CH0_CR_RXTRAINRANK3_RxEq_WID ( 5) + #define DDRDATA2CH0_CR_RXTRAINRANK3_RxEq_MSK (0x000F8000) + #define DDRDATA2CH0_CR_RXTRAINRANK3_RxEq_MAX (0x0000001F) + #define DDRDATA2CH0_CR_RXTRAINRANK3_RxDqsNPi_OFF (20) + #define DDRDATA2CH0_CR_RXTRAINRANK3_RxDqsNPi_WID ( 6) + #define DDRDATA2CH0_CR_RXTRAINRANK3_RxDqsNPi_MSK (0x03F00000) + #define DDRDATA2CH0_CR_RXTRAINRANK3_RxDqsNPi_MAX (0x0000003F) + #define DDRDATA2CH0_CR_RXTRAINRANK3_RxVref_OFF (26) + #define DDRDATA2CH0_CR_RXTRAINRANK3_RxVref_WID ( 6) + #define DDRDATA2CH0_CR_RXTRAINRANK3_RxVref_MSK (0xFC000000) + #define DDRDATA2CH0_CR_RXTRAINRANK3_RxVref_MAX (0x0000003F) + +#define DDRDATA2CH0_CR_RXPERBITRANK0_REG (0x00000410) + #define DDRDATA2CH0_CR_RXPERBITRANK0_Lane0_OFF ( 0) + #define DDRDATA2CH0_CR_RXPERBITRANK0_Lane0_WID ( 4) + #define DDRDATA2CH0_CR_RXPERBITRANK0_Lane0_MSK (0x0000000F) + #define DDRDATA2CH0_CR_RXPERBITRANK0_Lane0_MAX (0x0000000F) + #define DDRDATA2CH0_CR_RXPERBITRANK0_Lane1_OFF ( 4) + #define DDRDATA2CH0_CR_RXPERBITRANK0_Lane1_WID ( 4) + #define DDRDATA2CH0_CR_RXPERBITRANK0_Lane1_MSK (0x000000F0) + #define DDRDATA2CH0_CR_RXPERBITRANK0_Lane1_MAX (0x0000000F) + #define DDRDATA2CH0_CR_RXPERBITRANK0_Lane2_OFF ( 8) + #define DDRDATA2CH0_CR_RXPERBITRANK0_Lane2_WID ( 4) + #define DDRDATA2CH0_CR_RXPERBITRANK0_Lane2_MSK (0x00000F00) + #define DDRDATA2CH0_CR_RXPERBITRANK0_Lane2_MAX (0x0000000F) + #define DDRDATA2CH0_CR_RXPERBITRANK0_Lane3_OFF (12) + #define DDRDATA2CH0_CR_RXPERBITRANK0_Lane3_WID ( 4) + #define DDRDATA2CH0_CR_RXPERBITRANK0_Lane3_MSK (0x0000F000) + #define DDRDATA2CH0_CR_RXPERBITRANK0_Lane3_MAX (0x0000000F) + #define DDRDATA2CH0_CR_RXPERBITRANK0_Lane4_OFF (16) + #define DDRDATA2CH0_CR_RXPERBITRANK0_Lane4_WID ( 4) + #define DDRDATA2CH0_CR_RXPERBITRANK0_Lane4_MSK (0x000F0000) + #define DDRDATA2CH0_CR_RXPERBITRANK0_Lane4_MAX (0x0000000F) + #define DDRDATA2CH0_CR_RXPERBITRANK0_Lane5_OFF (20) + #define DDRDATA2CH0_CR_RXPERBITRANK0_Lane5_WID ( 4) + #define DDRDATA2CH0_CR_RXPERBITRANK0_Lane5_MSK (0x00F00000) + #define DDRDATA2CH0_CR_RXPERBITRANK0_Lane5_MAX (0x0000000F) + #define DDRDATA2CH0_CR_RXPERBITRANK0_Lane6_OFF (24) + #define DDRDATA2CH0_CR_RXPERBITRANK0_Lane6_WID ( 4) + #define DDRDATA2CH0_CR_RXPERBITRANK0_Lane6_MSK (0x0F000000) + #define DDRDATA2CH0_CR_RXPERBITRANK0_Lane6_MAX (0x0000000F) + #define DDRDATA2CH0_CR_RXPERBITRANK0_Lane7_OFF (28) + #define DDRDATA2CH0_CR_RXPERBITRANK0_Lane7_WID ( 4) + #define DDRDATA2CH0_CR_RXPERBITRANK0_Lane7_MSK (0xF0000000) + #define DDRDATA2CH0_CR_RXPERBITRANK0_Lane7_MAX (0x0000000F) + +#define DDRDATA2CH0_CR_RXPERBITRANK1_REG (0x00000414) + #define DDRDATA2CH0_CR_RXPERBITRANK1_Lane0_OFF ( 0) + #define DDRDATA2CH0_CR_RXPERBITRANK1_Lane0_WID ( 4) + #define DDRDATA2CH0_CR_RXPERBITRANK1_Lane0_MSK (0x0000000F) + #define DDRDATA2CH0_CR_RXPERBITRANK1_Lane0_MAX (0x0000000F) + #define DDRDATA2CH0_CR_RXPERBITRANK1_Lane1_OFF ( 4) + #define DDRDATA2CH0_CR_RXPERBITRANK1_Lane1_WID ( 4) + #define DDRDATA2CH0_CR_RXPERBITRANK1_Lane1_MSK (0x000000F0) + #define DDRDATA2CH0_CR_RXPERBITRANK1_Lane1_MAX (0x0000000F) + #define DDRDATA2CH0_CR_RXPERBITRANK1_Lane2_OFF ( 8) + #define DDRDATA2CH0_CR_RXPERBITRANK1_Lane2_WID ( 4) + #define DDRDATA2CH0_CR_RXPERBITRANK1_Lane2_MSK (0x00000F00) + #define DDRDATA2CH0_CR_RXPERBITRANK1_Lane2_MAX (0x0000000F) + #define DDRDATA2CH0_CR_RXPERBITRANK1_Lane3_OFF (12) + #define DDRDATA2CH0_CR_RXPERBITRANK1_Lane3_WID ( 4) + #define DDRDATA2CH0_CR_RXPERBITRANK1_Lane3_MSK (0x0000F000) + #define DDRDATA2CH0_CR_RXPERBITRANK1_Lane3_MAX (0x0000000F) + #define DDRDATA2CH0_CR_RXPERBITRANK1_Lane4_OFF (16) + #define DDRDATA2CH0_CR_RXPERBITRANK1_Lane4_WID ( 4) + #define DDRDATA2CH0_CR_RXPERBITRANK1_Lane4_MSK (0x000F0000) + #define DDRDATA2CH0_CR_RXPERBITRANK1_Lane4_MAX (0x0000000F) + #define DDRDATA2CH0_CR_RXPERBITRANK1_Lane5_OFF (20) + #define DDRDATA2CH0_CR_RXPERBITRANK1_Lane5_WID ( 4) + #define DDRDATA2CH0_CR_RXPERBITRANK1_Lane5_MSK (0x00F00000) + #define DDRDATA2CH0_CR_RXPERBITRANK1_Lane5_MAX (0x0000000F) + #define DDRDATA2CH0_CR_RXPERBITRANK1_Lane6_OFF (24) + #define DDRDATA2CH0_CR_RXPERBITRANK1_Lane6_WID ( 4) + #define DDRDATA2CH0_CR_RXPERBITRANK1_Lane6_MSK (0x0F000000) + #define DDRDATA2CH0_CR_RXPERBITRANK1_Lane6_MAX (0x0000000F) + #define DDRDATA2CH0_CR_RXPERBITRANK1_Lane7_OFF (28) + #define DDRDATA2CH0_CR_RXPERBITRANK1_Lane7_WID ( 4) + #define DDRDATA2CH0_CR_RXPERBITRANK1_Lane7_MSK (0xF0000000) + #define DDRDATA2CH0_CR_RXPERBITRANK1_Lane7_MAX (0x0000000F) + +#define DDRDATA2CH0_CR_RXPERBITRANK2_REG (0x00000418) + #define DDRDATA2CH0_CR_RXPERBITRANK2_Lane0_OFF ( 0) + #define DDRDATA2CH0_CR_RXPERBITRANK2_Lane0_WID ( 4) + #define DDRDATA2CH0_CR_RXPERBITRANK2_Lane0_MSK (0x0000000F) + #define DDRDATA2CH0_CR_RXPERBITRANK2_Lane0_MAX (0x0000000F) + #define DDRDATA2CH0_CR_RXPERBITRANK2_Lane1_OFF ( 4) + #define DDRDATA2CH0_CR_RXPERBITRANK2_Lane1_WID ( 4) + #define DDRDATA2CH0_CR_RXPERBITRANK2_Lane1_MSK (0x000000F0) + #define DDRDATA2CH0_CR_RXPERBITRANK2_Lane1_MAX (0x0000000F) + #define DDRDATA2CH0_CR_RXPERBITRANK2_Lane2_OFF ( 8) + #define DDRDATA2CH0_CR_RXPERBITRANK2_Lane2_WID ( 4) + #define DDRDATA2CH0_CR_RXPERBITRANK2_Lane2_MSK (0x00000F00) + #define DDRDATA2CH0_CR_RXPERBITRANK2_Lane2_MAX (0x0000000F) + #define DDRDATA2CH0_CR_RXPERBITRANK2_Lane3_OFF (12) + #define DDRDATA2CH0_CR_RXPERBITRANK2_Lane3_WID ( 4) + #define DDRDATA2CH0_CR_RXPERBITRANK2_Lane3_MSK (0x0000F000) + #define DDRDATA2CH0_CR_RXPERBITRANK2_Lane3_MAX (0x0000000F) + #define DDRDATA2CH0_CR_RXPERBITRANK2_Lane4_OFF (16) + #define DDRDATA2CH0_CR_RXPERBITRANK2_Lane4_WID ( 4) + #define DDRDATA2CH0_CR_RXPERBITRANK2_Lane4_MSK (0x000F0000) + #define DDRDATA2CH0_CR_RXPERBITRANK2_Lane4_MAX (0x0000000F) + #define DDRDATA2CH0_CR_RXPERBITRANK2_Lane5_OFF (20) + #define DDRDATA2CH0_CR_RXPERBITRANK2_Lane5_WID ( 4) + #define DDRDATA2CH0_CR_RXPERBITRANK2_Lane5_MSK (0x00F00000) + #define DDRDATA2CH0_CR_RXPERBITRANK2_Lane5_MAX (0x0000000F) + #define DDRDATA2CH0_CR_RXPERBITRANK2_Lane6_OFF (24) + #define DDRDATA2CH0_CR_RXPERBITRANK2_Lane6_WID ( 4) + #define DDRDATA2CH0_CR_RXPERBITRANK2_Lane6_MSK (0x0F000000) + #define DDRDATA2CH0_CR_RXPERBITRANK2_Lane6_MAX (0x0000000F) + #define DDRDATA2CH0_CR_RXPERBITRANK2_Lane7_OFF (28) + #define DDRDATA2CH0_CR_RXPERBITRANK2_Lane7_WID ( 4) + #define DDRDATA2CH0_CR_RXPERBITRANK2_Lane7_MSK (0xF0000000) + #define DDRDATA2CH0_CR_RXPERBITRANK2_Lane7_MAX (0x0000000F) + +#define DDRDATA2CH0_CR_RXPERBITRANK3_REG (0x0000041C) + #define DDRDATA2CH0_CR_RXPERBITRANK3_Lane0_OFF ( 0) + #define DDRDATA2CH0_CR_RXPERBITRANK3_Lane0_WID ( 4) + #define DDRDATA2CH0_CR_RXPERBITRANK3_Lane0_MSK (0x0000000F) + #define DDRDATA2CH0_CR_RXPERBITRANK3_Lane0_MAX (0x0000000F) + #define DDRDATA2CH0_CR_RXPERBITRANK3_Lane1_OFF ( 4) + #define DDRDATA2CH0_CR_RXPERBITRANK3_Lane1_WID ( 4) + #define DDRDATA2CH0_CR_RXPERBITRANK3_Lane1_MSK (0x000000F0) + #define DDRDATA2CH0_CR_RXPERBITRANK3_Lane1_MAX (0x0000000F) + #define DDRDATA2CH0_CR_RXPERBITRANK3_Lane2_OFF ( 8) + #define DDRDATA2CH0_CR_RXPERBITRANK3_Lane2_WID ( 4) + #define DDRDATA2CH0_CR_RXPERBITRANK3_Lane2_MSK (0x00000F00) + #define DDRDATA2CH0_CR_RXPERBITRANK3_Lane2_MAX (0x0000000F) + #define DDRDATA2CH0_CR_RXPERBITRANK3_Lane3_OFF (12) + #define DDRDATA2CH0_CR_RXPERBITRANK3_Lane3_WID ( 4) + #define DDRDATA2CH0_CR_RXPERBITRANK3_Lane3_MSK (0x0000F000) + #define DDRDATA2CH0_CR_RXPERBITRANK3_Lane3_MAX (0x0000000F) + #define DDRDATA2CH0_CR_RXPERBITRANK3_Lane4_OFF (16) + #define DDRDATA2CH0_CR_RXPERBITRANK3_Lane4_WID ( 4) + #define DDRDATA2CH0_CR_RXPERBITRANK3_Lane4_MSK (0x000F0000) + #define DDRDATA2CH0_CR_RXPERBITRANK3_Lane4_MAX (0x0000000F) + #define DDRDATA2CH0_CR_RXPERBITRANK3_Lane5_OFF (20) + #define DDRDATA2CH0_CR_RXPERBITRANK3_Lane5_WID ( 4) + #define DDRDATA2CH0_CR_RXPERBITRANK3_Lane5_MSK (0x00F00000) + #define DDRDATA2CH0_CR_RXPERBITRANK3_Lane5_MAX (0x0000000F) + #define DDRDATA2CH0_CR_RXPERBITRANK3_Lane6_OFF (24) + #define DDRDATA2CH0_CR_RXPERBITRANK3_Lane6_WID ( 4) + #define DDRDATA2CH0_CR_RXPERBITRANK3_Lane6_MSK (0x0F000000) + #define DDRDATA2CH0_CR_RXPERBITRANK3_Lane6_MAX (0x0000000F) + #define DDRDATA2CH0_CR_RXPERBITRANK3_Lane7_OFF (28) + #define DDRDATA2CH0_CR_RXPERBITRANK3_Lane7_WID ( 4) + #define DDRDATA2CH0_CR_RXPERBITRANK3_Lane7_MSK (0xF0000000) + #define DDRDATA2CH0_CR_RXPERBITRANK3_Lane7_MAX (0x0000000F) + +#define DDRDATA2CH0_CR_TXTRAINRANK0_REG (0x00000420) + #define DDRDATA2CH0_CR_TXTRAINRANK0_TxDqDelay_OFF ( 0) + #define DDRDATA2CH0_CR_TXTRAINRANK0_TxDqDelay_WID ( 9) + #define DDRDATA2CH0_CR_TXTRAINRANK0_TxDqDelay_MSK (0x000001FF) + #define DDRDATA2CH0_CR_TXTRAINRANK0_TxDqDelay_MAX (0x000001FF) + #define DDRDATA2CH0_CR_TXTRAINRANK0_TxDqsDelay_OFF ( 9) + #define DDRDATA2CH0_CR_TXTRAINRANK0_TxDqsDelay_WID ( 9) + #define DDRDATA2CH0_CR_TXTRAINRANK0_TxDqsDelay_MSK (0x0003FE00) + #define DDRDATA2CH0_CR_TXTRAINRANK0_TxDqsDelay_MAX (0x000001FF) + #define DDRDATA2CH0_CR_TXTRAINRANK0_Spare0_OFF (18) + #define DDRDATA2CH0_CR_TXTRAINRANK0_Spare0_WID ( 2) + #define DDRDATA2CH0_CR_TXTRAINRANK0_Spare0_MSK (0x000C0000) + #define DDRDATA2CH0_CR_TXTRAINRANK0_Spare0_MAX (0x00000003) + #define DDRDATA2CH0_CR_TXTRAINRANK0_TxEqualization_OFF (20) + #define DDRDATA2CH0_CR_TXTRAINRANK0_TxEqualization_WID ( 6) + #define DDRDATA2CH0_CR_TXTRAINRANK0_TxEqualization_MSK (0x03F00000) + #define DDRDATA2CH0_CR_TXTRAINRANK0_TxEqualization_MAX (0x0000003F) + #define DDRDATA2CH0_CR_TXTRAINRANK0_Spare1_OFF (26) + #define DDRDATA2CH0_CR_TXTRAINRANK0_Spare1_WID ( 6) + #define DDRDATA2CH0_CR_TXTRAINRANK0_Spare1_MSK (0xFC000000) + #define DDRDATA2CH0_CR_TXTRAINRANK0_Spare1_MAX (0x0000003F) + +#define DDRDATA2CH0_CR_TXTRAINRANK1_REG (0x00000424) + #define DDRDATA2CH0_CR_TXTRAINRANK1_TxDqDelay_OFF ( 0) + #define DDRDATA2CH0_CR_TXTRAINRANK1_TxDqDelay_WID ( 9) + #define DDRDATA2CH0_CR_TXTRAINRANK1_TxDqDelay_MSK (0x000001FF) + #define DDRDATA2CH0_CR_TXTRAINRANK1_TxDqDelay_MAX (0x000001FF) + #define DDRDATA2CH0_CR_TXTRAINRANK1_TxDqsDelay_OFF ( 9) + #define DDRDATA2CH0_CR_TXTRAINRANK1_TxDqsDelay_WID ( 9) + #define DDRDATA2CH0_CR_TXTRAINRANK1_TxDqsDelay_MSK (0x0003FE00) + #define DDRDATA2CH0_CR_TXTRAINRANK1_TxDqsDelay_MAX (0x000001FF) + #define DDRDATA2CH0_CR_TXTRAINRANK1_Spare0_OFF (18) + #define DDRDATA2CH0_CR_TXTRAINRANK1_Spare0_WID ( 2) + #define DDRDATA2CH0_CR_TXTRAINRANK1_Spare0_MSK (0x000C0000) + #define DDRDATA2CH0_CR_TXTRAINRANK1_Spare0_MAX (0x00000003) + #define DDRDATA2CH0_CR_TXTRAINRANK1_TxEqualization_OFF (20) + #define DDRDATA2CH0_CR_TXTRAINRANK1_TxEqualization_WID ( 6) + #define DDRDATA2CH0_CR_TXTRAINRANK1_TxEqualization_MSK (0x03F00000) + #define DDRDATA2CH0_CR_TXTRAINRANK1_TxEqualization_MAX (0x0000003F) + #define DDRDATA2CH0_CR_TXTRAINRANK1_Spare1_OFF (26) + #define DDRDATA2CH0_CR_TXTRAINRANK1_Spare1_WID ( 6) + #define DDRDATA2CH0_CR_TXTRAINRANK1_Spare1_MSK (0xFC000000) + #define DDRDATA2CH0_CR_TXTRAINRANK1_Spare1_MAX (0x0000003F) + +#define DDRDATA2CH0_CR_TXTRAINRANK2_REG (0x00000428) + #define DDRDATA2CH0_CR_TXTRAINRANK2_TxDqDelay_OFF ( 0) + #define DDRDATA2CH0_CR_TXTRAINRANK2_TxDqDelay_WID ( 9) + #define DDRDATA2CH0_CR_TXTRAINRANK2_TxDqDelay_MSK (0x000001FF) + #define DDRDATA2CH0_CR_TXTRAINRANK2_TxDqDelay_MAX (0x000001FF) + #define DDRDATA2CH0_CR_TXTRAINRANK2_TxDqsDelay_OFF ( 9) + #define DDRDATA2CH0_CR_TXTRAINRANK2_TxDqsDelay_WID ( 9) + #define DDRDATA2CH0_CR_TXTRAINRANK2_TxDqsDelay_MSK (0x0003FE00) + #define DDRDATA2CH0_CR_TXTRAINRANK2_TxDqsDelay_MAX (0x000001FF) + #define DDRDATA2CH0_CR_TXTRAINRANK2_Spare0_OFF (18) + #define DDRDATA2CH0_CR_TXTRAINRANK2_Spare0_WID ( 2) + #define DDRDATA2CH0_CR_TXTRAINRANK2_Spare0_MSK (0x000C0000) + #define DDRDATA2CH0_CR_TXTRAINRANK2_Spare0_MAX (0x00000003) + #define DDRDATA2CH0_CR_TXTRAINRANK2_TxEqualization_OFF (20) + #define DDRDATA2CH0_CR_TXTRAINRANK2_TxEqualization_WID ( 6) + #define DDRDATA2CH0_CR_TXTRAINRANK2_TxEqualization_MSK (0x03F00000) + #define DDRDATA2CH0_CR_TXTRAINRANK2_TxEqualization_MAX (0x0000003F) + #define DDRDATA2CH0_CR_TXTRAINRANK2_Spare1_OFF (26) + #define DDRDATA2CH0_CR_TXTRAINRANK2_Spare1_WID ( 6) + #define DDRDATA2CH0_CR_TXTRAINRANK2_Spare1_MSK (0xFC000000) + #define DDRDATA2CH0_CR_TXTRAINRANK2_Spare1_MAX (0x0000003F) + +#define DDRDATA2CH0_CR_TXTRAINRANK3_REG (0x0000042C) + #define DDRDATA2CH0_CR_TXTRAINRANK3_TxDqDelay_OFF ( 0) + #define DDRDATA2CH0_CR_TXTRAINRANK3_TxDqDelay_WID ( 9) + #define DDRDATA2CH0_CR_TXTRAINRANK3_TxDqDelay_MSK (0x000001FF) + #define DDRDATA2CH0_CR_TXTRAINRANK3_TxDqDelay_MAX (0x000001FF) + #define DDRDATA2CH0_CR_TXTRAINRANK3_TxDqsDelay_OFF ( 9) + #define DDRDATA2CH0_CR_TXTRAINRANK3_TxDqsDelay_WID ( 9) + #define DDRDATA2CH0_CR_TXTRAINRANK3_TxDqsDelay_MSK (0x0003FE00) + #define DDRDATA2CH0_CR_TXTRAINRANK3_TxDqsDelay_MAX (0x000001FF) + #define DDRDATA2CH0_CR_TXTRAINRANK3_Spare0_OFF (18) + #define DDRDATA2CH0_CR_TXTRAINRANK3_Spare0_WID ( 2) + #define DDRDATA2CH0_CR_TXTRAINRANK3_Spare0_MSK (0x000C0000) + #define DDRDATA2CH0_CR_TXTRAINRANK3_Spare0_MAX (0x00000003) + #define DDRDATA2CH0_CR_TXTRAINRANK3_TxEqualization_OFF (20) + #define DDRDATA2CH0_CR_TXTRAINRANK3_TxEqualization_WID ( 6) + #define DDRDATA2CH0_CR_TXTRAINRANK3_TxEqualization_MSK (0x03F00000) + #define DDRDATA2CH0_CR_TXTRAINRANK3_TxEqualization_MAX (0x0000003F) + #define DDRDATA2CH0_CR_TXTRAINRANK3_Spare1_OFF (26) + #define DDRDATA2CH0_CR_TXTRAINRANK3_Spare1_WID ( 6) + #define DDRDATA2CH0_CR_TXTRAINRANK3_Spare1_MSK (0xFC000000) + #define DDRDATA2CH0_CR_TXTRAINRANK3_Spare1_MAX (0x0000003F) + +#define DDRDATA2CH0_CR_TXPERBITRANK0_REG (0x00000430) + #define DDRDATA2CH0_CR_TXPERBITRANK0_Lane0_OFF ( 0) + #define DDRDATA2CH0_CR_TXPERBITRANK0_Lane0_WID ( 4) + #define DDRDATA2CH0_CR_TXPERBITRANK0_Lane0_MSK (0x0000000F) + #define DDRDATA2CH0_CR_TXPERBITRANK0_Lane0_MAX (0x0000000F) + #define DDRDATA2CH0_CR_TXPERBITRANK0_Lane1_OFF ( 4) + #define DDRDATA2CH0_CR_TXPERBITRANK0_Lane1_WID ( 4) + #define DDRDATA2CH0_CR_TXPERBITRANK0_Lane1_MSK (0x000000F0) + #define DDRDATA2CH0_CR_TXPERBITRANK0_Lane1_MAX (0x0000000F) + #define DDRDATA2CH0_CR_TXPERBITRANK0_Lane2_OFF ( 8) + #define DDRDATA2CH0_CR_TXPERBITRANK0_Lane2_WID ( 4) + #define DDRDATA2CH0_CR_TXPERBITRANK0_Lane2_MSK (0x00000F00) + #define DDRDATA2CH0_CR_TXPERBITRANK0_Lane2_MAX (0x0000000F) + #define DDRDATA2CH0_CR_TXPERBITRANK0_Lane3_OFF (12) + #define DDRDATA2CH0_CR_TXPERBITRANK0_Lane3_WID ( 4) + #define DDRDATA2CH0_CR_TXPERBITRANK0_Lane3_MSK (0x0000F000) + #define DDRDATA2CH0_CR_TXPERBITRANK0_Lane3_MAX (0x0000000F) + #define DDRDATA2CH0_CR_TXPERBITRANK0_Lane4_OFF (16) + #define DDRDATA2CH0_CR_TXPERBITRANK0_Lane4_WID ( 4) + #define DDRDATA2CH0_CR_TXPERBITRANK0_Lane4_MSK (0x000F0000) + #define DDRDATA2CH0_CR_TXPERBITRANK0_Lane4_MAX (0x0000000F) + #define DDRDATA2CH0_CR_TXPERBITRANK0_Lane5_OFF (20) + #define DDRDATA2CH0_CR_TXPERBITRANK0_Lane5_WID ( 4) + #define DDRDATA2CH0_CR_TXPERBITRANK0_Lane5_MSK (0x00F00000) + #define DDRDATA2CH0_CR_TXPERBITRANK0_Lane5_MAX (0x0000000F) + #define DDRDATA2CH0_CR_TXPERBITRANK0_Lane6_OFF (24) + #define DDRDATA2CH0_CR_TXPERBITRANK0_Lane6_WID ( 4) + #define DDRDATA2CH0_CR_TXPERBITRANK0_Lane6_MSK (0x0F000000) + #define DDRDATA2CH0_CR_TXPERBITRANK0_Lane6_MAX (0x0000000F) + #define DDRDATA2CH0_CR_TXPERBITRANK0_Lane7_OFF (28) + #define DDRDATA2CH0_CR_TXPERBITRANK0_Lane7_WID ( 4) + #define DDRDATA2CH0_CR_TXPERBITRANK0_Lane7_MSK (0xF0000000) + #define DDRDATA2CH0_CR_TXPERBITRANK0_Lane7_MAX (0x0000000F) + +#define DDRDATA2CH0_CR_TXPERBITRANK1_REG (0x00000434) + #define DDRDATA2CH0_CR_TXPERBITRANK1_Lane0_OFF ( 0) + #define DDRDATA2CH0_CR_TXPERBITRANK1_Lane0_WID ( 4) + #define DDRDATA2CH0_CR_TXPERBITRANK1_Lane0_MSK (0x0000000F) + #define DDRDATA2CH0_CR_TXPERBITRANK1_Lane0_MAX (0x0000000F) + #define DDRDATA2CH0_CR_TXPERBITRANK1_Lane1_OFF ( 4) + #define DDRDATA2CH0_CR_TXPERBITRANK1_Lane1_WID ( 4) + #define DDRDATA2CH0_CR_TXPERBITRANK1_Lane1_MSK (0x000000F0) + #define DDRDATA2CH0_CR_TXPERBITRANK1_Lane1_MAX (0x0000000F) + #define DDRDATA2CH0_CR_TXPERBITRANK1_Lane2_OFF ( 8) + #define DDRDATA2CH0_CR_TXPERBITRANK1_Lane2_WID ( 4) + #define DDRDATA2CH0_CR_TXPERBITRANK1_Lane2_MSK (0x00000F00) + #define DDRDATA2CH0_CR_TXPERBITRANK1_Lane2_MAX (0x0000000F) + #define DDRDATA2CH0_CR_TXPERBITRANK1_Lane3_OFF (12) + #define DDRDATA2CH0_CR_TXPERBITRANK1_Lane3_WID ( 4) + #define DDRDATA2CH0_CR_TXPERBITRANK1_Lane3_MSK (0x0000F000) + #define DDRDATA2CH0_CR_TXPERBITRANK1_Lane3_MAX (0x0000000F) + #define DDRDATA2CH0_CR_TXPERBITRANK1_Lane4_OFF (16) + #define DDRDATA2CH0_CR_TXPERBITRANK1_Lane4_WID ( 4) + #define DDRDATA2CH0_CR_TXPERBITRANK1_Lane4_MSK (0x000F0000) + #define DDRDATA2CH0_CR_TXPERBITRANK1_Lane4_MAX (0x0000000F) + #define DDRDATA2CH0_CR_TXPERBITRANK1_Lane5_OFF (20) + #define DDRDATA2CH0_CR_TXPERBITRANK1_Lane5_WID ( 4) + #define DDRDATA2CH0_CR_TXPERBITRANK1_Lane5_MSK (0x00F00000) + #define DDRDATA2CH0_CR_TXPERBITRANK1_Lane5_MAX (0x0000000F) + #define DDRDATA2CH0_CR_TXPERBITRANK1_Lane6_OFF (24) + #define DDRDATA2CH0_CR_TXPERBITRANK1_Lane6_WID ( 4) + #define DDRDATA2CH0_CR_TXPERBITRANK1_Lane6_MSK (0x0F000000) + #define DDRDATA2CH0_CR_TXPERBITRANK1_Lane6_MAX (0x0000000F) + #define DDRDATA2CH0_CR_TXPERBITRANK1_Lane7_OFF (28) + #define DDRDATA2CH0_CR_TXPERBITRANK1_Lane7_WID ( 4) + #define DDRDATA2CH0_CR_TXPERBITRANK1_Lane7_MSK (0xF0000000) + #define DDRDATA2CH0_CR_TXPERBITRANK1_Lane7_MAX (0x0000000F) + +#define DDRDATA2CH0_CR_TXPERBITRANK2_REG (0x00000438) + #define DDRDATA2CH0_CR_TXPERBITRANK2_Lane0_OFF ( 0) + #define DDRDATA2CH0_CR_TXPERBITRANK2_Lane0_WID ( 4) + #define DDRDATA2CH0_CR_TXPERBITRANK2_Lane0_MSK (0x0000000F) + #define DDRDATA2CH0_CR_TXPERBITRANK2_Lane0_MAX (0x0000000F) + #define DDRDATA2CH0_CR_TXPERBITRANK2_Lane1_OFF ( 4) + #define DDRDATA2CH0_CR_TXPERBITRANK2_Lane1_WID ( 4) + #define DDRDATA2CH0_CR_TXPERBITRANK2_Lane1_MSK (0x000000F0) + #define DDRDATA2CH0_CR_TXPERBITRANK2_Lane1_MAX (0x0000000F) + #define DDRDATA2CH0_CR_TXPERBITRANK2_Lane2_OFF ( 8) + #define DDRDATA2CH0_CR_TXPERBITRANK2_Lane2_WID ( 4) + #define DDRDATA2CH0_CR_TXPERBITRANK2_Lane2_MSK (0x00000F00) + #define DDRDATA2CH0_CR_TXPERBITRANK2_Lane2_MAX (0x0000000F) + #define DDRDATA2CH0_CR_TXPERBITRANK2_Lane3_OFF (12) + #define DDRDATA2CH0_CR_TXPERBITRANK2_Lane3_WID ( 4) + #define DDRDATA2CH0_CR_TXPERBITRANK2_Lane3_MSK (0x0000F000) + #define DDRDATA2CH0_CR_TXPERBITRANK2_Lane3_MAX (0x0000000F) + #define DDRDATA2CH0_CR_TXPERBITRANK2_Lane4_OFF (16) + #define DDRDATA2CH0_CR_TXPERBITRANK2_Lane4_WID ( 4) + #define DDRDATA2CH0_CR_TXPERBITRANK2_Lane4_MSK (0x000F0000) + #define DDRDATA2CH0_CR_TXPERBITRANK2_Lane4_MAX (0x0000000F) + #define DDRDATA2CH0_CR_TXPERBITRANK2_Lane5_OFF (20) + #define DDRDATA2CH0_CR_TXPERBITRANK2_Lane5_WID ( 4) + #define DDRDATA2CH0_CR_TXPERBITRANK2_Lane5_MSK (0x00F00000) + #define DDRDATA2CH0_CR_TXPERBITRANK2_Lane5_MAX (0x0000000F) + #define DDRDATA2CH0_CR_TXPERBITRANK2_Lane6_OFF (24) + #define DDRDATA2CH0_CR_TXPERBITRANK2_Lane6_WID ( 4) + #define DDRDATA2CH0_CR_TXPERBITRANK2_Lane6_MSK (0x0F000000) + #define DDRDATA2CH0_CR_TXPERBITRANK2_Lane6_MAX (0x0000000F) + #define DDRDATA2CH0_CR_TXPERBITRANK2_Lane7_OFF (28) + #define DDRDATA2CH0_CR_TXPERBITRANK2_Lane7_WID ( 4) + #define DDRDATA2CH0_CR_TXPERBITRANK2_Lane7_MSK (0xF0000000) + #define DDRDATA2CH0_CR_TXPERBITRANK2_Lane7_MAX (0x0000000F) + +#define DDRDATA2CH0_CR_TXPERBITRANK3_REG (0x0000043C) + #define DDRDATA2CH0_CR_TXPERBITRANK3_Lane0_OFF ( 0) + #define DDRDATA2CH0_CR_TXPERBITRANK3_Lane0_WID ( 4) + #define DDRDATA2CH0_CR_TXPERBITRANK3_Lane0_MSK (0x0000000F) + #define DDRDATA2CH0_CR_TXPERBITRANK3_Lane0_MAX (0x0000000F) + #define DDRDATA2CH0_CR_TXPERBITRANK3_Lane1_OFF ( 4) + #define DDRDATA2CH0_CR_TXPERBITRANK3_Lane1_WID ( 4) + #define DDRDATA2CH0_CR_TXPERBITRANK3_Lane1_MSK (0x000000F0) + #define DDRDATA2CH0_CR_TXPERBITRANK3_Lane1_MAX (0x0000000F) + #define DDRDATA2CH0_CR_TXPERBITRANK3_Lane2_OFF ( 8) + #define DDRDATA2CH0_CR_TXPERBITRANK3_Lane2_WID ( 4) + #define DDRDATA2CH0_CR_TXPERBITRANK3_Lane2_MSK (0x00000F00) + #define DDRDATA2CH0_CR_TXPERBITRANK3_Lane2_MAX (0x0000000F) + #define DDRDATA2CH0_CR_TXPERBITRANK3_Lane3_OFF (12) + #define DDRDATA2CH0_CR_TXPERBITRANK3_Lane3_WID ( 4) + #define DDRDATA2CH0_CR_TXPERBITRANK3_Lane3_MSK (0x0000F000) + #define DDRDATA2CH0_CR_TXPERBITRANK3_Lane3_MAX (0x0000000F) + #define DDRDATA2CH0_CR_TXPERBITRANK3_Lane4_OFF (16) + #define DDRDATA2CH0_CR_TXPERBITRANK3_Lane4_WID ( 4) + #define DDRDATA2CH0_CR_TXPERBITRANK3_Lane4_MSK (0x000F0000) + #define DDRDATA2CH0_CR_TXPERBITRANK3_Lane4_MAX (0x0000000F) + #define DDRDATA2CH0_CR_TXPERBITRANK3_Lane5_OFF (20) + #define DDRDATA2CH0_CR_TXPERBITRANK3_Lane5_WID ( 4) + #define DDRDATA2CH0_CR_TXPERBITRANK3_Lane5_MSK (0x00F00000) + #define DDRDATA2CH0_CR_TXPERBITRANK3_Lane5_MAX (0x0000000F) + #define DDRDATA2CH0_CR_TXPERBITRANK3_Lane6_OFF (24) + #define DDRDATA2CH0_CR_TXPERBITRANK3_Lane6_WID ( 4) + #define DDRDATA2CH0_CR_TXPERBITRANK3_Lane6_MSK (0x0F000000) + #define DDRDATA2CH0_CR_TXPERBITRANK3_Lane6_MAX (0x0000000F) + #define DDRDATA2CH0_CR_TXPERBITRANK3_Lane7_OFF (28) + #define DDRDATA2CH0_CR_TXPERBITRANK3_Lane7_WID ( 4) + #define DDRDATA2CH0_CR_TXPERBITRANK3_Lane7_MSK (0xF0000000) + #define DDRDATA2CH0_CR_TXPERBITRANK3_Lane7_MAX (0x0000000F) + +#define DDRDATA2CH0_CR_RCOMPDATA0_REG (0x00000440) + #define DDRDATA2CH0_CR_RCOMPDATA0_RcompDrvUp_OFF ( 0) + #define DDRDATA2CH0_CR_RCOMPDATA0_RcompDrvUp_WID ( 6) + #define DDRDATA2CH0_CR_RCOMPDATA0_RcompDrvUp_MSK (0x0000003F) + #define DDRDATA2CH0_CR_RCOMPDATA0_RcompDrvUp_MAX (0x0000003F) + #define DDRDATA2CH0_CR_RCOMPDATA0_Spare0_OFF ( 6) + #define DDRDATA2CH0_CR_RCOMPDATA0_Spare0_WID ( 3) + #define DDRDATA2CH0_CR_RCOMPDATA0_Spare0_MSK (0x000001C0) + #define DDRDATA2CH0_CR_RCOMPDATA0_Spare0_MAX (0x00000007) + #define DDRDATA2CH0_CR_RCOMPDATA0_RcompDrvDown_OFF ( 9) + #define DDRDATA2CH0_CR_RCOMPDATA0_RcompDrvDown_WID ( 6) + #define DDRDATA2CH0_CR_RCOMPDATA0_RcompDrvDown_MSK (0x00007E00) + #define DDRDATA2CH0_CR_RCOMPDATA0_RcompDrvDown_MAX (0x0000003F) + #define DDRDATA2CH0_CR_RCOMPDATA0_VTComp_OFF (15) + #define DDRDATA2CH0_CR_RCOMPDATA0_VTComp_WID ( 5) + #define DDRDATA2CH0_CR_RCOMPDATA0_VTComp_MSK (0x000F8000) + #define DDRDATA2CH0_CR_RCOMPDATA0_VTComp_MAX (0x0000001F) + #define DDRDATA2CH0_CR_RCOMPDATA0_TcoComp_OFF (20) + #define DDRDATA2CH0_CR_RCOMPDATA0_TcoComp_WID ( 6) + #define DDRDATA2CH0_CR_RCOMPDATA0_TcoComp_MSK (0x03F00000) + #define DDRDATA2CH0_CR_RCOMPDATA0_TcoComp_MAX (0x0000003F) + #define DDRDATA2CH0_CR_RCOMPDATA0_SlewRateComp_OFF (26) + #define DDRDATA2CH0_CR_RCOMPDATA0_SlewRateComp_WID ( 5) + #define DDRDATA2CH0_CR_RCOMPDATA0_SlewRateComp_MSK (0x7C000000) + #define DDRDATA2CH0_CR_RCOMPDATA0_SlewRateComp_MAX (0x0000001F) + #define DDRDATA2CH0_CR_RCOMPDATA0_Spare2_OFF (31) + #define DDRDATA2CH0_CR_RCOMPDATA0_Spare2_WID ( 1) + #define DDRDATA2CH0_CR_RCOMPDATA0_Spare2_MSK (0x80000000) + #define DDRDATA2CH0_CR_RCOMPDATA0_Spare2_MAX (0x00000001) + +#define DDRDATA2CH0_CR_RCOMPDATA1_REG (0x00000444) + #define DDRDATA2CH0_CR_RCOMPDATA1_RcompOdtUp_OFF ( 0) + #define DDRDATA2CH0_CR_RCOMPDATA1_RcompOdtUp_WID ( 6) + #define DDRDATA2CH0_CR_RCOMPDATA1_RcompOdtUp_MSK (0x0000003F) + #define DDRDATA2CH0_CR_RCOMPDATA1_RcompOdtUp_MAX (0x0000003F) + #define DDRDATA2CH0_CR_RCOMPDATA1_Spare0_OFF ( 6) + #define DDRDATA2CH0_CR_RCOMPDATA1_Spare0_WID ( 3) + #define DDRDATA2CH0_CR_RCOMPDATA1_Spare0_MSK (0x000001C0) + #define DDRDATA2CH0_CR_RCOMPDATA1_Spare0_MAX (0x00000007) + #define DDRDATA2CH0_CR_RCOMPDATA1_RcompOdtDown_OFF ( 9) + #define DDRDATA2CH0_CR_RCOMPDATA1_RcompOdtDown_WID ( 6) + #define DDRDATA2CH0_CR_RCOMPDATA1_RcompOdtDown_MSK (0x00007E00) + #define DDRDATA2CH0_CR_RCOMPDATA1_RcompOdtDown_MAX (0x0000003F) + #define DDRDATA2CH0_CR_RCOMPDATA1_Spare1_OFF (15) + #define DDRDATA2CH0_CR_RCOMPDATA1_Spare1_WID ( 1) + #define DDRDATA2CH0_CR_RCOMPDATA1_Spare1_MSK (0x00008000) + #define DDRDATA2CH0_CR_RCOMPDATA1_Spare1_MAX (0x00000001) + #define DDRDATA2CH0_CR_RCOMPDATA1_PanicDrvDn_OFF (16) + #define DDRDATA2CH0_CR_RCOMPDATA1_PanicDrvDn_WID ( 6) + #define DDRDATA2CH0_CR_RCOMPDATA1_PanicDrvDn_MSK (0x003F0000) + #define DDRDATA2CH0_CR_RCOMPDATA1_PanicDrvDn_MAX (0x0000003F) + #define DDRDATA2CH0_CR_RCOMPDATA1_PanicDrvUp_OFF (22) + #define DDRDATA2CH0_CR_RCOMPDATA1_PanicDrvUp_WID ( 6) + #define DDRDATA2CH0_CR_RCOMPDATA1_PanicDrvUp_MSK (0x0FC00000) + #define DDRDATA2CH0_CR_RCOMPDATA1_PanicDrvUp_MAX (0x0000003F) + #define DDRDATA2CH0_CR_RCOMPDATA1_LevelShifterComp_OFF (28) + #define DDRDATA2CH0_CR_RCOMPDATA1_LevelShifterComp_WID ( 3) + #define DDRDATA2CH0_CR_RCOMPDATA1_LevelShifterComp_MSK (0x70000000) + #define DDRDATA2CH0_CR_RCOMPDATA1_LevelShifterComp_MAX (0x00000007) + #define DDRDATA2CH0_CR_RCOMPDATA1_Spare2_OFF (31) + #define DDRDATA2CH0_CR_RCOMPDATA1_Spare2_WID ( 1) + #define DDRDATA2CH0_CR_RCOMPDATA1_Spare2_MSK (0x80000000) + #define DDRDATA2CH0_CR_RCOMPDATA1_Spare2_MAX (0x00000001) + +#define DDRDATA2CH0_CR_TXXTALK_REG (0x00000448) + #define DDRDATA2CH0_CR_TXXTALK_Lane0_OFF ( 0) + #define DDRDATA2CH0_CR_TXXTALK_Lane0_WID ( 4) + #define DDRDATA2CH0_CR_TXXTALK_Lane0_MSK (0x0000000F) + #define DDRDATA2CH0_CR_TXXTALK_Lane0_MAX (0x0000000F) + #define DDRDATA2CH0_CR_TXXTALK_Lane1_OFF ( 4) + #define DDRDATA2CH0_CR_TXXTALK_Lane1_WID ( 4) + #define DDRDATA2CH0_CR_TXXTALK_Lane1_MSK (0x000000F0) + #define DDRDATA2CH0_CR_TXXTALK_Lane1_MAX (0x0000000F) + #define DDRDATA2CH0_CR_TXXTALK_Lane2_OFF ( 8) + #define DDRDATA2CH0_CR_TXXTALK_Lane2_WID ( 4) + #define DDRDATA2CH0_CR_TXXTALK_Lane2_MSK (0x00000F00) + #define DDRDATA2CH0_CR_TXXTALK_Lane2_MAX (0x0000000F) + #define DDRDATA2CH0_CR_TXXTALK_Lane3_OFF (12) + #define DDRDATA2CH0_CR_TXXTALK_Lane3_WID ( 4) + #define DDRDATA2CH0_CR_TXXTALK_Lane3_MSK (0x0000F000) + #define DDRDATA2CH0_CR_TXXTALK_Lane3_MAX (0x0000000F) + #define DDRDATA2CH0_CR_TXXTALK_Lane4_OFF (16) + #define DDRDATA2CH0_CR_TXXTALK_Lane4_WID ( 4) + #define DDRDATA2CH0_CR_TXXTALK_Lane4_MSK (0x000F0000) + #define DDRDATA2CH0_CR_TXXTALK_Lane4_MAX (0x0000000F) + #define DDRDATA2CH0_CR_TXXTALK_Lane5_OFF (20) + #define DDRDATA2CH0_CR_TXXTALK_Lane5_WID ( 4) + #define DDRDATA2CH0_CR_TXXTALK_Lane5_MSK (0x00F00000) + #define DDRDATA2CH0_CR_TXXTALK_Lane5_MAX (0x0000000F) + #define DDRDATA2CH0_CR_TXXTALK_Lane6_OFF (24) + #define DDRDATA2CH0_CR_TXXTALK_Lane6_WID ( 4) + #define DDRDATA2CH0_CR_TXXTALK_Lane6_MSK (0x0F000000) + #define DDRDATA2CH0_CR_TXXTALK_Lane6_MAX (0x0000000F) + #define DDRDATA2CH0_CR_TXXTALK_Lane7_OFF (28) + #define DDRDATA2CH0_CR_TXXTALK_Lane7_WID ( 4) + #define DDRDATA2CH0_CR_TXXTALK_Lane7_MSK (0xF0000000) + #define DDRDATA2CH0_CR_TXXTALK_Lane7_MAX (0x0000000F) + +#define DDRDATA2CH0_CR_RXOFFSETVDQ_REG (0x0000044C) + #define DDRDATA2CH0_CR_RXOFFSETVDQ_Lane0_OFF ( 0) + #define DDRDATA2CH0_CR_RXOFFSETVDQ_Lane0_WID ( 4) + #define DDRDATA2CH0_CR_RXOFFSETVDQ_Lane0_MSK (0x0000000F) + #define DDRDATA2CH0_CR_RXOFFSETVDQ_Lane0_MAX (0x0000000F) + #define DDRDATA2CH0_CR_RXOFFSETVDQ_Lane1_OFF ( 4) + #define DDRDATA2CH0_CR_RXOFFSETVDQ_Lane1_WID ( 4) + #define DDRDATA2CH0_CR_RXOFFSETVDQ_Lane1_MSK (0x000000F0) + #define DDRDATA2CH0_CR_RXOFFSETVDQ_Lane1_MAX (0x0000000F) + #define DDRDATA2CH0_CR_RXOFFSETVDQ_Lane2_OFF ( 8) + #define DDRDATA2CH0_CR_RXOFFSETVDQ_Lane2_WID ( 4) + #define DDRDATA2CH0_CR_RXOFFSETVDQ_Lane2_MSK (0x00000F00) + #define DDRDATA2CH0_CR_RXOFFSETVDQ_Lane2_MAX (0x0000000F) + #define DDRDATA2CH0_CR_RXOFFSETVDQ_Lane3_OFF (12) + #define DDRDATA2CH0_CR_RXOFFSETVDQ_Lane3_WID ( 4) + #define DDRDATA2CH0_CR_RXOFFSETVDQ_Lane3_MSK (0x0000F000) + #define DDRDATA2CH0_CR_RXOFFSETVDQ_Lane3_MAX (0x0000000F) + #define DDRDATA2CH0_CR_RXOFFSETVDQ_Lane4_OFF (16) + #define DDRDATA2CH0_CR_RXOFFSETVDQ_Lane4_WID ( 4) + #define DDRDATA2CH0_CR_RXOFFSETVDQ_Lane4_MSK (0x000F0000) + #define DDRDATA2CH0_CR_RXOFFSETVDQ_Lane4_MAX (0x0000000F) + #define DDRDATA2CH0_CR_RXOFFSETVDQ_Lane5_OFF (20) + #define DDRDATA2CH0_CR_RXOFFSETVDQ_Lane5_WID ( 4) + #define DDRDATA2CH0_CR_RXOFFSETVDQ_Lane5_MSK (0x00F00000) + #define DDRDATA2CH0_CR_RXOFFSETVDQ_Lane5_MAX (0x0000000F) + #define DDRDATA2CH0_CR_RXOFFSETVDQ_Lane6_OFF (24) + #define DDRDATA2CH0_CR_RXOFFSETVDQ_Lane6_WID ( 4) + #define DDRDATA2CH0_CR_RXOFFSETVDQ_Lane6_MSK (0x0F000000) + #define DDRDATA2CH0_CR_RXOFFSETVDQ_Lane6_MAX (0x0000000F) + #define DDRDATA2CH0_CR_RXOFFSETVDQ_Lane7_OFF (28) + #define DDRDATA2CH0_CR_RXOFFSETVDQ_Lane7_WID ( 4) + #define DDRDATA2CH0_CR_RXOFFSETVDQ_Lane7_MSK (0xF0000000) + #define DDRDATA2CH0_CR_RXOFFSETVDQ_Lane7_MAX (0x0000000F) + +#define DDRDATA2CH0_CR_DDRDATARESERVED_REG (0x00000450) + #define DDRDATA2CH0_CR_DDRDATARESERVED_Spare_OFF ( 0) + #define DDRDATA2CH0_CR_DDRDATARESERVED_Spare_WID (32) + #define DDRDATA2CH0_CR_DDRDATARESERVED_Spare_MSK (0xFFFFFFFF) + #define DDRDATA2CH0_CR_DDRDATARESERVED_Spare_MAX (0xFFFFFFFF) + +#define DDRDATA2CH0_CR_DATATRAINFEEDBACK_REG (0x00000454) + #define DDRDATA2CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_OFF ( 0) + #define DDRDATA2CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_WID ( 9) + #define DDRDATA2CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_MSK (0x000001FF) + #define DDRDATA2CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_MAX (0x000001FF) + #define DDRDATA2CH0_CR_DATATRAINFEEDBACK_Spare_OFF ( 9) + #define DDRDATA2CH0_CR_DATATRAINFEEDBACK_Spare_WID (23) + #define DDRDATA2CH0_CR_DATATRAINFEEDBACK_Spare_MSK (0xFFFFFE00) + #define DDRDATA2CH0_CR_DATATRAINFEEDBACK_Spare_MAX (0x007FFFFF) + +#define DDRDATA2CH0_CR_DLLPITESTANDADC_REG (0x00000458) + #define DDRDATA2CH0_CR_DLLPITESTANDADC_RunTest_OFF ( 0) + #define DDRDATA2CH0_CR_DLLPITESTANDADC_RunTest_WID ( 1) + #define DDRDATA2CH0_CR_DLLPITESTANDADC_RunTest_MSK (0x00000001) + #define DDRDATA2CH0_CR_DLLPITESTANDADC_RunTest_MAX (0x00000001) + #define DDRDATA2CH0_CR_DLLPITESTANDADC_RunTest_DEF (0x00000000) + #define DDRDATA2CH0_CR_DLLPITESTANDADC_Load_OFF ( 1) + #define DDRDATA2CH0_CR_DLLPITESTANDADC_Load_WID ( 1) + #define DDRDATA2CH0_CR_DLLPITESTANDADC_Load_MSK (0x00000002) + #define DDRDATA2CH0_CR_DLLPITESTANDADC_Load_MAX (0x00000001) + #define DDRDATA2CH0_CR_DLLPITESTANDADC_Load_DEF (0x00000000) + #define DDRDATA2CH0_CR_DLLPITESTANDADC_ModeHVM_OFF ( 2) + #define DDRDATA2CH0_CR_DLLPITESTANDADC_ModeHVM_WID ( 1) + #define DDRDATA2CH0_CR_DLLPITESTANDADC_ModeHVM_MSK (0x00000004) + #define DDRDATA2CH0_CR_DLLPITESTANDADC_ModeHVM_MAX (0x00000001) + #define DDRDATA2CH0_CR_DLLPITESTANDADC_ModeHVM_DEF (0x00000000) + #define DDRDATA2CH0_CR_DLLPITESTANDADC_ModeDV_OFF ( 3) + #define DDRDATA2CH0_CR_DLLPITESTANDADC_ModeDV_WID ( 1) + #define DDRDATA2CH0_CR_DLLPITESTANDADC_ModeDV_MSK (0x00000008) + #define DDRDATA2CH0_CR_DLLPITESTANDADC_ModeDV_MAX (0x00000001) + #define DDRDATA2CH0_CR_DLLPITESTANDADC_ModeDV_DEF (0x00000000) + #define DDRDATA2CH0_CR_DLLPITESTANDADC_ModeADC_OFF ( 4) + #define DDRDATA2CH0_CR_DLLPITESTANDADC_ModeADC_WID ( 1) + #define DDRDATA2CH0_CR_DLLPITESTANDADC_ModeADC_MSK (0x00000010) + #define DDRDATA2CH0_CR_DLLPITESTANDADC_ModeADC_MAX (0x00000001) + #define DDRDATA2CH0_CR_DLLPITESTANDADC_ModeADC_DEF (0x00000000) + #define DDRDATA2CH0_CR_DLLPITESTANDADC_LoadCount_OFF ( 5) + #define DDRDATA2CH0_CR_DLLPITESTANDADC_LoadCount_WID (10) + #define DDRDATA2CH0_CR_DLLPITESTANDADC_LoadCount_MSK (0x00007FE0) + #define DDRDATA2CH0_CR_DLLPITESTANDADC_LoadCount_MAX (0x000003FF) + #define DDRDATA2CH0_CR_DLLPITESTANDADC_CountStatus_OFF (15) + #define DDRDATA2CH0_CR_DLLPITESTANDADC_CountStatus_WID (10) + #define DDRDATA2CH0_CR_DLLPITESTANDADC_CountStatus_MSK (0x01FF8000) + #define DDRDATA2CH0_CR_DLLPITESTANDADC_CountStatus_MAX (0x000003FF) + #define DDRDATA2CH0_CR_DLLPITESTANDADC_CountStatus_DEF (0x00000000) + #define DDRDATA2CH0_CR_DLLPITESTANDADC_Spare_OFF (25) + #define DDRDATA2CH0_CR_DLLPITESTANDADC_Spare_WID ( 7) + #define DDRDATA2CH0_CR_DLLPITESTANDADC_Spare_MSK (0xFE000000) + #define DDRDATA2CH0_CR_DLLPITESTANDADC_Spare_MAX (0x0000007F) + +#define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_REG (0x0000045C) + #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_OFF ( 0) + #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_WID ( 6) + #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MSK (0x0000003F) + #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MAX (0x0000003F) + #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_DEF (0x00000000) + #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_OFF ( 6) + #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_WID ( 6) + #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MSK (0x00000FC0) + #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MAX (0x0000003F) + #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_DEF (0x00000000) + #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_OFF (12) + #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_WID ( 5) + #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MSK (0x0001F000) + #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MAX (0x0000001F) + #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_DEF (0x00000000) + #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_OFF (17) + #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_WID ( 5) + #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MSK (0x003E0000) + #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MAX (0x0000001F) + #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_DEF (0x00000000) + #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_OFF (22) + #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_WID ( 5) + #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_MSK (0x07C00000) + #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_MAX (0x0000001F) + #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_DEF (0x00000000) + #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_OFF (27) + #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_WID ( 5) + #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MSK (0xF8000000) + #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MAX (0x0000001F) + #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_DEF (0x00000000) + +#define DDRDATA2CH0_CR_DDRCRDATACONTROL1_REG (0x00000460) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_RefPi_OFF ( 0) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_RefPi_WID ( 4) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_RefPi_MSK (0x0000000F) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_RefPi_MAX (0x0000000F) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_RefPi_DEF (0x00000000) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_DllMask_OFF ( 4) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_DllMask_WID ( 2) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_DllMask_MSK (0x00000030) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_DllMask_MAX (0x00000003) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_DllMask_DEF (0x00000000) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_DllWeakLock_OFF ( 6) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_DllWeakLock_WID ( 1) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_DllWeakLock_MSK (0x00000040) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_DllWeakLock_MAX (0x00000001) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_DllWeakLock_DEF (0x00000000) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_OFF ( 7) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_WID ( 3) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MSK (0x00000380) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MAX (0x00000007) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_DEF (0x00000000) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_OFF (10) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_WID ( 3) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_MSK (0x00001C00) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_MAX (0x00000007) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_DEF (0x00000000) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_OdtDelay_OFF (13) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_OdtDelay_WID ( 4) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_OdtDelay_MSK (0x0001E000) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_OdtDelay_MAX (0x0000000F) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_OdtDelay_DEF (0x00000000) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_OdtDuration_OFF (17) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_OdtDuration_WID ( 3) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_OdtDuration_MSK (0x000E0000) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_OdtDuration_MAX (0x00000007) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_OdtDuration_DEF (0x00000000) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_OFF (20) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_WID ( 4) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_MSK (0x00F00000) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_MAX (0x0000000F) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_DEF (0x00000000) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_OFF (24) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_WID ( 3) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_MSK (0x07000000) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_MAX (0x00000007) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_DEF (0x00000000) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_OFF (27) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_WID ( 3) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_MSK (0x38000000) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_MAX (0x00000007) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_DEF (0x00000000) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_OFF (30) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_WID ( 1) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_MSK (0x40000000) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_MAX (0x00000001) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_DEF (0x00000000) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_Rsvd1_OFF (31) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_Rsvd1_WID ( 1) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_Rsvd1_MSK (0x80000000) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_Rsvd1_MAX (0x00000001) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_Rsvd1_DEF (0x00000000) + +#define DDRDATA2CH0_CR_DDRCRDATACONTROL2_REG (0x00000464) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_OFF ( 0) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_WID ( 5) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_MSK (0x0000001F) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_MAX (0x0000001F) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_DEF (0x00000000) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_OFF ( 5) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_WID ( 1) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_MSK (0x00000020) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_MAX (0x00000001) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_DEF (0x00000000) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_ForceRxOn_OFF ( 6) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_ForceRxOn_WID ( 1) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_ForceRxOn_MSK (0x00000040) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_ForceRxOn_MAX (0x00000001) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_ForceRxOn_DEF (0x00000000) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_LeakerComp_OFF ( 7) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_LeakerComp_WID ( 2) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_LeakerComp_MSK (0x00000180) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_LeakerComp_MAX (0x00000003) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_LeakerComp_DEF (0x00000000) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_OFF ( 9) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_WID ( 4) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_MSK (0x00001E00) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_MAX (0x0000000F) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_DEF (0x00000008) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_OFF (13) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_WID ( 5) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_MSK (0x0003E000) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_MAX (0x0000001F) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_DEF (0x00000011) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_OFF (18) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_WID ( 1) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_MSK (0x00040000) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_MAX (0x00000001) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_DEF (0x00000000) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_Spare_OFF (19) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_Spare_WID (13) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_Spare_MSK (0xFFF80000) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_Spare_MAX (0x00001FFF) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_Spare_DEF (0x00000000) + +#define DDRDATA2CH0_CR_DDRCRVSSHIORVREFCONTROL_REG (0x0000046C) + #define DDRDATA2CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_OFF ( 0) + #define DDRDATA2CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_WID (24) + #define DDRDATA2CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_MSK (0x00FFFFFF) + #define DDRDATA2CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_MAX (0x00FFFFFF) + #define DDRDATA2CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_DEF (0x00000000) + #define DDRDATA2CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_OFF (24) + #define DDRDATA2CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_WID ( 8) + #define DDRDATA2CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_MSK (0xFF000000) + #define DDRDATA2CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_MAX (0x000000FF) + #define DDRDATA2CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_DEF (0x00000000) + +#define DDRDATA2CH0_CR_DDRCRDATAOFFSETTRAIN_REG (0x00000470) + #define DDRDATA2CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_OFF ( 0) + #define DDRDATA2CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_WID ( 6) + #define DDRDATA2CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MSK (0x0000003F) + #define DDRDATA2CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MAX (0x0000003F) + #define DDRDATA2CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_DEF (0x00000000) + #define DDRDATA2CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_OFF ( 6) + #define DDRDATA2CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_WID ( 6) + #define DDRDATA2CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MSK (0x00000FC0) + #define DDRDATA2CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MAX (0x0000003F) + #define DDRDATA2CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_DEF (0x00000000) + #define DDRDATA2CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_OFF (12) + #define DDRDATA2CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_WID ( 6) + #define DDRDATA2CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MSK (0x0003F000) + #define DDRDATA2CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MAX (0x0000003F) + #define DDRDATA2CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_DEF (0x00000000) + #define DDRDATA2CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_OFF (18) + #define DDRDATA2CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_WID ( 6) + #define DDRDATA2CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MSK (0x00FC0000) + #define DDRDATA2CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MAX (0x0000003F) + #define DDRDATA2CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_DEF (0x00000000) + #define DDRDATA2CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_OFF (24) + #define DDRDATA2CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_WID ( 7) + #define DDRDATA2CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MSK (0x7F000000) + #define DDRDATA2CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MAX (0x0000007F) + #define DDRDATA2CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_DEF (0x00000000) + #define DDRDATA2CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_OFF (31) + #define DDRDATA2CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_WID ( 1) + #define DDRDATA2CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_MSK (0x80000000) + #define DDRDATA2CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_MAX (0x00000001) + #define DDRDATA2CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_DEF (0x00000000) + +#define DDRDATA2CH0_CR_DDRCRDATACONTROL0_REG (0x00000474) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_OFF ( 0) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_WID ( 1) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_MSK (0x00000001) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_MAX (0x00000001) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_DEF (0x00000000) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_OFF ( 1) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_WID ( 1) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_MSK (0x00000002) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_MAX (0x00000001) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_DEF (0x00000000) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_OFF ( 2) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_WID ( 1) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_MSK (0x00000004) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_MAX (0x00000001) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_DEF (0x00000000) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_OFF ( 3) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_WID ( 1) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MSK (0x00000008) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MAX (0x00000001) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_DEF (0x00000000) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_TxOn_OFF ( 4) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_TxOn_WID ( 1) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_TxOn_MSK (0x00000010) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_TxOn_MAX (0x00000001) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_TxOn_DEF (0x00000000) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RfOn_OFF ( 5) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RfOn_WID ( 1) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RfOn_MSK (0x00000020) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RfOn_MAX (0x00000001) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RfOn_DEF (0x00000000) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RxPiOn_OFF ( 6) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RxPiOn_WID ( 1) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RxPiOn_MSK (0x00000040) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RxPiOn_MAX (0x00000001) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RxPiOn_DEF (0x00000000) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_TxPiOn_OFF ( 7) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_TxPiOn_WID ( 1) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_TxPiOn_MSK (0x00000080) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_TxPiOn_MAX (0x00000001) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_TxPiOn_DEF (0x00000000) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_OFF ( 8) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_WID ( 1) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_MSK (0x00000100) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_MAX (0x00000001) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_DEF (0x00000000) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_OFF ( 9) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_WID ( 1) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MSK (0x00000200) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MAX (0x00000001) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_DEF (0x00000000) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_TxDisable_OFF (10) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_TxDisable_WID ( 1) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_TxDisable_MSK (0x00000400) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_TxDisable_MAX (0x00000001) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_TxDisable_DEF (0x00000000) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RxDisable_OFF (11) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RxDisable_WID ( 1) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RxDisable_MSK (0x00000800) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RxDisable_MAX (0x00000001) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RxDisable_DEF (0x00000000) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_TxLong_OFF (12) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_TxLong_WID ( 1) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_TxLong_MSK (0x00001000) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_TxLong_MAX (0x00000001) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_TxLong_DEF (0x00000000) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_OFF (13) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_WID ( 2) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_MSK (0x00006000) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_MAX (0x00000003) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_DEF (0x00000000) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RxReadPointer_OFF (15) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RxReadPointer_WID ( 3) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RxReadPointer_MSK (0x00038000) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RxReadPointer_MAX (0x00000007) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RxReadPointer_DEF (0x00000000) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_OFF (18) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_WID ( 1) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_MSK (0x00040000) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_MAX (0x00000001) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_DEF (0x00000000) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_OFF (19) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_WID ( 1) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_MSK (0x00080000) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_MAX (0x00000001) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_DEF (0x00000000) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_ReadRFRd_OFF (20) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_ReadRFRd_WID ( 1) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_ReadRFRd_MSK (0x00100000) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_ReadRFRd_MAX (0x00000001) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_ReadRFRd_DEF (0x00000000) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_ReadRFWr_OFF (21) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_ReadRFWr_WID ( 1) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_ReadRFWr_MSK (0x00200000) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_ReadRFWr_MAX (0x00000001) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_ReadRFWr_DEF (0x00000000) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_ReadRFRank_OFF (22) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_ReadRFRank_WID ( 2) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_ReadRFRank_MSK (0x00C00000) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_ReadRFRank_MAX (0x00000003) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_ReadRFRank_DEF (0x00000000) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_OFF (24) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_WID ( 1) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_MSK (0x01000000) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_MAX (0x00000001) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_DEF (0x00000000) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_OdtSampOff_OFF (25) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_OdtSampOff_WID ( 1) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_OdtSampOff_MSK (0x02000000) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_OdtSampOff_MAX (0x00000001) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_OdtSampOff_DEF (0x00000000) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_OFF (26) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_WID ( 1) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_MSK (0x04000000) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_MAX (0x00000001) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_DEF (0x00000000) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_OFF (27) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_WID ( 1) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MSK (0x08000000) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MAX (0x00000001) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_DEF (0x00000000) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_OFF (28) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_WID ( 1) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_MSK (0x10000000) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_MAX (0x00000001) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_DEF (0x00000000) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_OFF (29) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_WID ( 1) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_MSK (0x20000000) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_MAX (0x00000001) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_DEF (0x00000000) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_OFF (30) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_WID ( 1) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MSK (0x40000000) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MAX (0x00000001) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_DEF (0x00000000) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_OFF (31) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_WID ( 1) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_MSK (0x80000000) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_MAX (0x00000001) + #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_DEF (0x00000000) + +#define DDRDATA2CH0_CR_DDRCRVREFADJUST1_REG (0x00000478) + #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_OFF ( 0) + #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_WID ( 7) + #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_MSK (0x0000007F) + #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_MAX (0x0000007F) + #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_DEF (0x00000000) + #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_OFF ( 7) + #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_WID ( 7) + #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_MSK (0x00003F80) + #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_MAX (0x0000007F) + #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_DEF (0x00000000) + #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_OFF (14) + #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_WID ( 7) + #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_MSK (0x001FC000) + #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_MAX (0x0000007F) + #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_DEF (0x00000000) + #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_OFF (21) + #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_WID ( 1) + #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_MSK (0x00200000) + #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_MAX (0x00000001) + #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_DEF (0x00000000) + #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_OFF (22) + #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_WID ( 1) + #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_MSK (0x00400000) + #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_MAX (0x00000001) + #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_DEF (0x00000000) + #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_OFF (23) + #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_WID ( 1) + #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_MSK (0x00800000) + #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_MAX (0x00000001) + #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_DEF (0x00000000) + #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_OFF (24) + #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_WID ( 2) + #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_MSK (0x03000000) + #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_MAX (0x00000003) + #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_DEF (0x00000000) + #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_OFF (26) + #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_WID ( 1) + #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_MSK (0x04000000) + #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_MAX (0x00000001) + #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_DEF (0x00000000) + #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_Rsvd_OFF (27) + #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_Rsvd_WID ( 2) + #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_Rsvd_MSK (0x18000000) + #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_Rsvd_MAX (0x00000003) + #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_Rsvd_DEF (0x00000000) + #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_caSlowBW_OFF (29) + #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_caSlowBW_WID ( 1) + #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_caSlowBW_MSK (0x20000000) + #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_caSlowBW_MAX (0x00000001) + #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_caSlowBW_DEF (0x00000000) + #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_OFF (30) + #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_WID ( 1) + #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_MSK (0x40000000) + #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_MAX (0x00000001) + #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_DEF (0x00000000) + #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_OFF (31) + #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_WID ( 1) + #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_MSK (0x80000000) + #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_MAX (0x00000001) + #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_DEF (0x00000000) + +#define DDRDATA2CH1_CR_RXTRAINRANK0_REG (0x00000500) + #define DDRDATA2CH1_CR_RXTRAINRANK0_RxRcvEnPi_OFF ( 0) + #define DDRDATA2CH1_CR_RXTRAINRANK0_RxRcvEnPi_WID ( 9) + #define DDRDATA2CH1_CR_RXTRAINRANK0_RxRcvEnPi_MSK (0x000001FF) + #define DDRDATA2CH1_CR_RXTRAINRANK0_RxRcvEnPi_MAX (0x000001FF) + #define DDRDATA2CH1_CR_RXTRAINRANK0_RxDqsPPi_OFF ( 9) + #define DDRDATA2CH1_CR_RXTRAINRANK0_RxDqsPPi_WID ( 6) + #define DDRDATA2CH1_CR_RXTRAINRANK0_RxDqsPPi_MSK (0x00007E00) + #define DDRDATA2CH1_CR_RXTRAINRANK0_RxDqsPPi_MAX (0x0000003F) + #define DDRDATA2CH1_CR_RXTRAINRANK0_RxEq_OFF (15) + #define DDRDATA2CH1_CR_RXTRAINRANK0_RxEq_WID ( 5) + #define DDRDATA2CH1_CR_RXTRAINRANK0_RxEq_MSK (0x000F8000) + #define DDRDATA2CH1_CR_RXTRAINRANK0_RxEq_MAX (0x0000001F) + #define DDRDATA2CH1_CR_RXTRAINRANK0_RxDqsNPi_OFF (20) + #define DDRDATA2CH1_CR_RXTRAINRANK0_RxDqsNPi_WID ( 6) + #define DDRDATA2CH1_CR_RXTRAINRANK0_RxDqsNPi_MSK (0x03F00000) + #define DDRDATA2CH1_CR_RXTRAINRANK0_RxDqsNPi_MAX (0x0000003F) + #define DDRDATA2CH1_CR_RXTRAINRANK0_RxVref_OFF (26) + #define DDRDATA2CH1_CR_RXTRAINRANK0_RxVref_WID ( 6) + #define DDRDATA2CH1_CR_RXTRAINRANK0_RxVref_MSK (0xFC000000) + #define DDRDATA2CH1_CR_RXTRAINRANK0_RxVref_MAX (0x0000003F) + +#define DDRDATA2CH1_CR_RXTRAINRANK1_REG (0x00000504) + #define DDRDATA2CH1_CR_RXTRAINRANK1_RxRcvEnPi_OFF ( 0) + #define DDRDATA2CH1_CR_RXTRAINRANK1_RxRcvEnPi_WID ( 9) + #define DDRDATA2CH1_CR_RXTRAINRANK1_RxRcvEnPi_MSK (0x000001FF) + #define DDRDATA2CH1_CR_RXTRAINRANK1_RxRcvEnPi_MAX (0x000001FF) + #define DDRDATA2CH1_CR_RXTRAINRANK1_RxDqsPPi_OFF ( 9) + #define DDRDATA2CH1_CR_RXTRAINRANK1_RxDqsPPi_WID ( 6) + #define DDRDATA2CH1_CR_RXTRAINRANK1_RxDqsPPi_MSK (0x00007E00) + #define DDRDATA2CH1_CR_RXTRAINRANK1_RxDqsPPi_MAX (0x0000003F) + #define DDRDATA2CH1_CR_RXTRAINRANK1_RxEq_OFF (15) + #define DDRDATA2CH1_CR_RXTRAINRANK1_RxEq_WID ( 5) + #define DDRDATA2CH1_CR_RXTRAINRANK1_RxEq_MSK (0x000F8000) + #define DDRDATA2CH1_CR_RXTRAINRANK1_RxEq_MAX (0x0000001F) + #define DDRDATA2CH1_CR_RXTRAINRANK1_RxDqsNPi_OFF (20) + #define DDRDATA2CH1_CR_RXTRAINRANK1_RxDqsNPi_WID ( 6) + #define DDRDATA2CH1_CR_RXTRAINRANK1_RxDqsNPi_MSK (0x03F00000) + #define DDRDATA2CH1_CR_RXTRAINRANK1_RxDqsNPi_MAX (0x0000003F) + #define DDRDATA2CH1_CR_RXTRAINRANK1_RxVref_OFF (26) + #define DDRDATA2CH1_CR_RXTRAINRANK1_RxVref_WID ( 6) + #define DDRDATA2CH1_CR_RXTRAINRANK1_RxVref_MSK (0xFC000000) + #define DDRDATA2CH1_CR_RXTRAINRANK1_RxVref_MAX (0x0000003F) + +#define DDRDATA2CH1_CR_RXTRAINRANK2_REG (0x00000508) + #define DDRDATA2CH1_CR_RXTRAINRANK2_RxRcvEnPi_OFF ( 0) + #define DDRDATA2CH1_CR_RXTRAINRANK2_RxRcvEnPi_WID ( 9) + #define DDRDATA2CH1_CR_RXTRAINRANK2_RxRcvEnPi_MSK (0x000001FF) + #define DDRDATA2CH1_CR_RXTRAINRANK2_RxRcvEnPi_MAX (0x000001FF) + #define DDRDATA2CH1_CR_RXTRAINRANK2_RxDqsPPi_OFF ( 9) + #define DDRDATA2CH1_CR_RXTRAINRANK2_RxDqsPPi_WID ( 6) + #define DDRDATA2CH1_CR_RXTRAINRANK2_RxDqsPPi_MSK (0x00007E00) + #define DDRDATA2CH1_CR_RXTRAINRANK2_RxDqsPPi_MAX (0x0000003F) + #define DDRDATA2CH1_CR_RXTRAINRANK2_RxEq_OFF (15) + #define DDRDATA2CH1_CR_RXTRAINRANK2_RxEq_WID ( 5) + #define DDRDATA2CH1_CR_RXTRAINRANK2_RxEq_MSK (0x000F8000) + #define DDRDATA2CH1_CR_RXTRAINRANK2_RxEq_MAX (0x0000001F) + #define DDRDATA2CH1_CR_RXTRAINRANK2_RxDqsNPi_OFF (20) + #define DDRDATA2CH1_CR_RXTRAINRANK2_RxDqsNPi_WID ( 6) + #define DDRDATA2CH1_CR_RXTRAINRANK2_RxDqsNPi_MSK (0x03F00000) + #define DDRDATA2CH1_CR_RXTRAINRANK2_RxDqsNPi_MAX (0x0000003F) + #define DDRDATA2CH1_CR_RXTRAINRANK2_RxVref_OFF (26) + #define DDRDATA2CH1_CR_RXTRAINRANK2_RxVref_WID ( 6) + #define DDRDATA2CH1_CR_RXTRAINRANK2_RxVref_MSK (0xFC000000) + #define DDRDATA2CH1_CR_RXTRAINRANK2_RxVref_MAX (0x0000003F) + +#define DDRDATA2CH1_CR_RXTRAINRANK3_REG (0x0000050C) + #define DDRDATA2CH1_CR_RXTRAINRANK3_RxRcvEnPi_OFF ( 0) + #define DDRDATA2CH1_CR_RXTRAINRANK3_RxRcvEnPi_WID ( 9) + #define DDRDATA2CH1_CR_RXTRAINRANK3_RxRcvEnPi_MSK (0x000001FF) + #define DDRDATA2CH1_CR_RXTRAINRANK3_RxRcvEnPi_MAX (0x000001FF) + #define DDRDATA2CH1_CR_RXTRAINRANK3_RxDqsPPi_OFF ( 9) + #define DDRDATA2CH1_CR_RXTRAINRANK3_RxDqsPPi_WID ( 6) + #define DDRDATA2CH1_CR_RXTRAINRANK3_RxDqsPPi_MSK (0x00007E00) + #define DDRDATA2CH1_CR_RXTRAINRANK3_RxDqsPPi_MAX (0x0000003F) + #define DDRDATA2CH1_CR_RXTRAINRANK3_RxEq_OFF (15) + #define DDRDATA2CH1_CR_RXTRAINRANK3_RxEq_WID ( 5) + #define DDRDATA2CH1_CR_RXTRAINRANK3_RxEq_MSK (0x000F8000) + #define DDRDATA2CH1_CR_RXTRAINRANK3_RxEq_MAX (0x0000001F) + #define DDRDATA2CH1_CR_RXTRAINRANK3_RxDqsNPi_OFF (20) + #define DDRDATA2CH1_CR_RXTRAINRANK3_RxDqsNPi_WID ( 6) + #define DDRDATA2CH1_CR_RXTRAINRANK3_RxDqsNPi_MSK (0x03F00000) + #define DDRDATA2CH1_CR_RXTRAINRANK3_RxDqsNPi_MAX (0x0000003F) + #define DDRDATA2CH1_CR_RXTRAINRANK3_RxVref_OFF (26) + #define DDRDATA2CH1_CR_RXTRAINRANK3_RxVref_WID ( 6) + #define DDRDATA2CH1_CR_RXTRAINRANK3_RxVref_MSK (0xFC000000) + #define DDRDATA2CH1_CR_RXTRAINRANK3_RxVref_MAX (0x0000003F) + +#define DDRDATA2CH1_CR_RXPERBITRANK0_REG (0x00000510) + #define DDRDATA2CH1_CR_RXPERBITRANK0_Lane0_OFF ( 0) + #define DDRDATA2CH1_CR_RXPERBITRANK0_Lane0_WID ( 4) + #define DDRDATA2CH1_CR_RXPERBITRANK0_Lane0_MSK (0x0000000F) + #define DDRDATA2CH1_CR_RXPERBITRANK0_Lane0_MAX (0x0000000F) + #define DDRDATA2CH1_CR_RXPERBITRANK0_Lane1_OFF ( 4) + #define DDRDATA2CH1_CR_RXPERBITRANK0_Lane1_WID ( 4) + #define DDRDATA2CH1_CR_RXPERBITRANK0_Lane1_MSK (0x000000F0) + #define DDRDATA2CH1_CR_RXPERBITRANK0_Lane1_MAX (0x0000000F) + #define DDRDATA2CH1_CR_RXPERBITRANK0_Lane2_OFF ( 8) + #define DDRDATA2CH1_CR_RXPERBITRANK0_Lane2_WID ( 4) + #define DDRDATA2CH1_CR_RXPERBITRANK0_Lane2_MSK (0x00000F00) + #define DDRDATA2CH1_CR_RXPERBITRANK0_Lane2_MAX (0x0000000F) + #define DDRDATA2CH1_CR_RXPERBITRANK0_Lane3_OFF (12) + #define DDRDATA2CH1_CR_RXPERBITRANK0_Lane3_WID ( 4) + #define DDRDATA2CH1_CR_RXPERBITRANK0_Lane3_MSK (0x0000F000) + #define DDRDATA2CH1_CR_RXPERBITRANK0_Lane3_MAX (0x0000000F) + #define DDRDATA2CH1_CR_RXPERBITRANK0_Lane4_OFF (16) + #define DDRDATA2CH1_CR_RXPERBITRANK0_Lane4_WID ( 4) + #define DDRDATA2CH1_CR_RXPERBITRANK0_Lane4_MSK (0x000F0000) + #define DDRDATA2CH1_CR_RXPERBITRANK0_Lane4_MAX (0x0000000F) + #define DDRDATA2CH1_CR_RXPERBITRANK0_Lane5_OFF (20) + #define DDRDATA2CH1_CR_RXPERBITRANK0_Lane5_WID ( 4) + #define DDRDATA2CH1_CR_RXPERBITRANK0_Lane5_MSK (0x00F00000) + #define DDRDATA2CH1_CR_RXPERBITRANK0_Lane5_MAX (0x0000000F) + #define DDRDATA2CH1_CR_RXPERBITRANK0_Lane6_OFF (24) + #define DDRDATA2CH1_CR_RXPERBITRANK0_Lane6_WID ( 4) + #define DDRDATA2CH1_CR_RXPERBITRANK0_Lane6_MSK (0x0F000000) + #define DDRDATA2CH1_CR_RXPERBITRANK0_Lane6_MAX (0x0000000F) + #define DDRDATA2CH1_CR_RXPERBITRANK0_Lane7_OFF (28) + #define DDRDATA2CH1_CR_RXPERBITRANK0_Lane7_WID ( 4) + #define DDRDATA2CH1_CR_RXPERBITRANK0_Lane7_MSK (0xF0000000) + #define DDRDATA2CH1_CR_RXPERBITRANK0_Lane7_MAX (0x0000000F) + +#define DDRDATA2CH1_CR_RXPERBITRANK1_REG (0x00000514) + #define DDRDATA2CH1_CR_RXPERBITRANK1_Lane0_OFF ( 0) + #define DDRDATA2CH1_CR_RXPERBITRANK1_Lane0_WID ( 4) + #define DDRDATA2CH1_CR_RXPERBITRANK1_Lane0_MSK (0x0000000F) + #define DDRDATA2CH1_CR_RXPERBITRANK1_Lane0_MAX (0x0000000F) + #define DDRDATA2CH1_CR_RXPERBITRANK1_Lane1_OFF ( 4) + #define DDRDATA2CH1_CR_RXPERBITRANK1_Lane1_WID ( 4) + #define DDRDATA2CH1_CR_RXPERBITRANK1_Lane1_MSK (0x000000F0) + #define DDRDATA2CH1_CR_RXPERBITRANK1_Lane1_MAX (0x0000000F) + #define DDRDATA2CH1_CR_RXPERBITRANK1_Lane2_OFF ( 8) + #define DDRDATA2CH1_CR_RXPERBITRANK1_Lane2_WID ( 4) + #define DDRDATA2CH1_CR_RXPERBITRANK1_Lane2_MSK (0x00000F00) + #define DDRDATA2CH1_CR_RXPERBITRANK1_Lane2_MAX (0x0000000F) + #define DDRDATA2CH1_CR_RXPERBITRANK1_Lane3_OFF (12) + #define DDRDATA2CH1_CR_RXPERBITRANK1_Lane3_WID ( 4) + #define DDRDATA2CH1_CR_RXPERBITRANK1_Lane3_MSK (0x0000F000) + #define DDRDATA2CH1_CR_RXPERBITRANK1_Lane3_MAX (0x0000000F) + #define DDRDATA2CH1_CR_RXPERBITRANK1_Lane4_OFF (16) + #define DDRDATA2CH1_CR_RXPERBITRANK1_Lane4_WID ( 4) + #define DDRDATA2CH1_CR_RXPERBITRANK1_Lane4_MSK (0x000F0000) + #define DDRDATA2CH1_CR_RXPERBITRANK1_Lane4_MAX (0x0000000F) + #define DDRDATA2CH1_CR_RXPERBITRANK1_Lane5_OFF (20) + #define DDRDATA2CH1_CR_RXPERBITRANK1_Lane5_WID ( 4) + #define DDRDATA2CH1_CR_RXPERBITRANK1_Lane5_MSK (0x00F00000) + #define DDRDATA2CH1_CR_RXPERBITRANK1_Lane5_MAX (0x0000000F) + #define DDRDATA2CH1_CR_RXPERBITRANK1_Lane6_OFF (24) + #define DDRDATA2CH1_CR_RXPERBITRANK1_Lane6_WID ( 4) + #define DDRDATA2CH1_CR_RXPERBITRANK1_Lane6_MSK (0x0F000000) + #define DDRDATA2CH1_CR_RXPERBITRANK1_Lane6_MAX (0x0000000F) + #define DDRDATA2CH1_CR_RXPERBITRANK1_Lane7_OFF (28) + #define DDRDATA2CH1_CR_RXPERBITRANK1_Lane7_WID ( 4) + #define DDRDATA2CH1_CR_RXPERBITRANK1_Lane7_MSK (0xF0000000) + #define DDRDATA2CH1_CR_RXPERBITRANK1_Lane7_MAX (0x0000000F) + +#define DDRDATA2CH1_CR_RXPERBITRANK2_REG (0x00000518) + #define DDRDATA2CH1_CR_RXPERBITRANK2_Lane0_OFF ( 0) + #define DDRDATA2CH1_CR_RXPERBITRANK2_Lane0_WID ( 4) + #define DDRDATA2CH1_CR_RXPERBITRANK2_Lane0_MSK (0x0000000F) + #define DDRDATA2CH1_CR_RXPERBITRANK2_Lane0_MAX (0x0000000F) + #define DDRDATA2CH1_CR_RXPERBITRANK2_Lane1_OFF ( 4) + #define DDRDATA2CH1_CR_RXPERBITRANK2_Lane1_WID ( 4) + #define DDRDATA2CH1_CR_RXPERBITRANK2_Lane1_MSK (0x000000F0) + #define DDRDATA2CH1_CR_RXPERBITRANK2_Lane1_MAX (0x0000000F) + #define DDRDATA2CH1_CR_RXPERBITRANK2_Lane2_OFF ( 8) + #define DDRDATA2CH1_CR_RXPERBITRANK2_Lane2_WID ( 4) + #define DDRDATA2CH1_CR_RXPERBITRANK2_Lane2_MSK (0x00000F00) + #define DDRDATA2CH1_CR_RXPERBITRANK2_Lane2_MAX (0x0000000F) + #define DDRDATA2CH1_CR_RXPERBITRANK2_Lane3_OFF (12) + #define DDRDATA2CH1_CR_RXPERBITRANK2_Lane3_WID ( 4) + #define DDRDATA2CH1_CR_RXPERBITRANK2_Lane3_MSK (0x0000F000) + #define DDRDATA2CH1_CR_RXPERBITRANK2_Lane3_MAX (0x0000000F) + #define DDRDATA2CH1_CR_RXPERBITRANK2_Lane4_OFF (16) + #define DDRDATA2CH1_CR_RXPERBITRANK2_Lane4_WID ( 4) + #define DDRDATA2CH1_CR_RXPERBITRANK2_Lane4_MSK (0x000F0000) + #define DDRDATA2CH1_CR_RXPERBITRANK2_Lane4_MAX (0x0000000F) + #define DDRDATA2CH1_CR_RXPERBITRANK2_Lane5_OFF (20) + #define DDRDATA2CH1_CR_RXPERBITRANK2_Lane5_WID ( 4) + #define DDRDATA2CH1_CR_RXPERBITRANK2_Lane5_MSK (0x00F00000) + #define DDRDATA2CH1_CR_RXPERBITRANK2_Lane5_MAX (0x0000000F) + #define DDRDATA2CH1_CR_RXPERBITRANK2_Lane6_OFF (24) + #define DDRDATA2CH1_CR_RXPERBITRANK2_Lane6_WID ( 4) + #define DDRDATA2CH1_CR_RXPERBITRANK2_Lane6_MSK (0x0F000000) + #define DDRDATA2CH1_CR_RXPERBITRANK2_Lane6_MAX (0x0000000F) + #define DDRDATA2CH1_CR_RXPERBITRANK2_Lane7_OFF (28) + #define DDRDATA2CH1_CR_RXPERBITRANK2_Lane7_WID ( 4) + #define DDRDATA2CH1_CR_RXPERBITRANK2_Lane7_MSK (0xF0000000) + #define DDRDATA2CH1_CR_RXPERBITRANK2_Lane7_MAX (0x0000000F) + +#define DDRDATA2CH1_CR_RXPERBITRANK3_REG (0x0000051C) + #define DDRDATA2CH1_CR_RXPERBITRANK3_Lane0_OFF ( 0) + #define DDRDATA2CH1_CR_RXPERBITRANK3_Lane0_WID ( 4) + #define DDRDATA2CH1_CR_RXPERBITRANK3_Lane0_MSK (0x0000000F) + #define DDRDATA2CH1_CR_RXPERBITRANK3_Lane0_MAX (0x0000000F) + #define DDRDATA2CH1_CR_RXPERBITRANK3_Lane1_OFF ( 4) + #define DDRDATA2CH1_CR_RXPERBITRANK3_Lane1_WID ( 4) + #define DDRDATA2CH1_CR_RXPERBITRANK3_Lane1_MSK (0x000000F0) + #define DDRDATA2CH1_CR_RXPERBITRANK3_Lane1_MAX (0x0000000F) + #define DDRDATA2CH1_CR_RXPERBITRANK3_Lane2_OFF ( 8) + #define DDRDATA2CH1_CR_RXPERBITRANK3_Lane2_WID ( 4) + #define DDRDATA2CH1_CR_RXPERBITRANK3_Lane2_MSK (0x00000F00) + #define DDRDATA2CH1_CR_RXPERBITRANK3_Lane2_MAX (0x0000000F) + #define DDRDATA2CH1_CR_RXPERBITRANK3_Lane3_OFF (12) + #define DDRDATA2CH1_CR_RXPERBITRANK3_Lane3_WID ( 4) + #define DDRDATA2CH1_CR_RXPERBITRANK3_Lane3_MSK (0x0000F000) + #define DDRDATA2CH1_CR_RXPERBITRANK3_Lane3_MAX (0x0000000F) + #define DDRDATA2CH1_CR_RXPERBITRANK3_Lane4_OFF (16) + #define DDRDATA2CH1_CR_RXPERBITRANK3_Lane4_WID ( 4) + #define DDRDATA2CH1_CR_RXPERBITRANK3_Lane4_MSK (0x000F0000) + #define DDRDATA2CH1_CR_RXPERBITRANK3_Lane4_MAX (0x0000000F) + #define DDRDATA2CH1_CR_RXPERBITRANK3_Lane5_OFF (20) + #define DDRDATA2CH1_CR_RXPERBITRANK3_Lane5_WID ( 4) + #define DDRDATA2CH1_CR_RXPERBITRANK3_Lane5_MSK (0x00F00000) + #define DDRDATA2CH1_CR_RXPERBITRANK3_Lane5_MAX (0x0000000F) + #define DDRDATA2CH1_CR_RXPERBITRANK3_Lane6_OFF (24) + #define DDRDATA2CH1_CR_RXPERBITRANK3_Lane6_WID ( 4) + #define DDRDATA2CH1_CR_RXPERBITRANK3_Lane6_MSK (0x0F000000) + #define DDRDATA2CH1_CR_RXPERBITRANK3_Lane6_MAX (0x0000000F) + #define DDRDATA2CH1_CR_RXPERBITRANK3_Lane7_OFF (28) + #define DDRDATA2CH1_CR_RXPERBITRANK3_Lane7_WID ( 4) + #define DDRDATA2CH1_CR_RXPERBITRANK3_Lane7_MSK (0xF0000000) + #define DDRDATA2CH1_CR_RXPERBITRANK3_Lane7_MAX (0x0000000F) + +#define DDRDATA2CH1_CR_TXTRAINRANK0_REG (0x00000520) + #define DDRDATA2CH1_CR_TXTRAINRANK0_TxDqDelay_OFF ( 0) + #define DDRDATA2CH1_CR_TXTRAINRANK0_TxDqDelay_WID ( 9) + #define DDRDATA2CH1_CR_TXTRAINRANK0_TxDqDelay_MSK (0x000001FF) + #define DDRDATA2CH1_CR_TXTRAINRANK0_TxDqDelay_MAX (0x000001FF) + #define DDRDATA2CH1_CR_TXTRAINRANK0_TxDqsDelay_OFF ( 9) + #define DDRDATA2CH1_CR_TXTRAINRANK0_TxDqsDelay_WID ( 9) + #define DDRDATA2CH1_CR_TXTRAINRANK0_TxDqsDelay_MSK (0x0003FE00) + #define DDRDATA2CH1_CR_TXTRAINRANK0_TxDqsDelay_MAX (0x000001FF) + #define DDRDATA2CH1_CR_TXTRAINRANK0_Spare0_OFF (18) + #define DDRDATA2CH1_CR_TXTRAINRANK0_Spare0_WID ( 2) + #define DDRDATA2CH1_CR_TXTRAINRANK0_Spare0_MSK (0x000C0000) + #define DDRDATA2CH1_CR_TXTRAINRANK0_Spare0_MAX (0x00000003) + #define DDRDATA2CH1_CR_TXTRAINRANK0_TxEqualization_OFF (20) + #define DDRDATA2CH1_CR_TXTRAINRANK0_TxEqualization_WID ( 6) + #define DDRDATA2CH1_CR_TXTRAINRANK0_TxEqualization_MSK (0x03F00000) + #define DDRDATA2CH1_CR_TXTRAINRANK0_TxEqualization_MAX (0x0000003F) + #define DDRDATA2CH1_CR_TXTRAINRANK0_Spare1_OFF (26) + #define DDRDATA2CH1_CR_TXTRAINRANK0_Spare1_WID ( 6) + #define DDRDATA2CH1_CR_TXTRAINRANK0_Spare1_MSK (0xFC000000) + #define DDRDATA2CH1_CR_TXTRAINRANK0_Spare1_MAX (0x0000003F) + +#define DDRDATA2CH1_CR_TXTRAINRANK1_REG (0x00000524) + #define DDRDATA2CH1_CR_TXTRAINRANK1_TxDqDelay_OFF ( 0) + #define DDRDATA2CH1_CR_TXTRAINRANK1_TxDqDelay_WID ( 9) + #define DDRDATA2CH1_CR_TXTRAINRANK1_TxDqDelay_MSK (0x000001FF) + #define DDRDATA2CH1_CR_TXTRAINRANK1_TxDqDelay_MAX (0x000001FF) + #define DDRDATA2CH1_CR_TXTRAINRANK1_TxDqsDelay_OFF ( 9) + #define DDRDATA2CH1_CR_TXTRAINRANK1_TxDqsDelay_WID ( 9) + #define DDRDATA2CH1_CR_TXTRAINRANK1_TxDqsDelay_MSK (0x0003FE00) + #define DDRDATA2CH1_CR_TXTRAINRANK1_TxDqsDelay_MAX (0x000001FF) + #define DDRDATA2CH1_CR_TXTRAINRANK1_Spare0_OFF (18) + #define DDRDATA2CH1_CR_TXTRAINRANK1_Spare0_WID ( 2) + #define DDRDATA2CH1_CR_TXTRAINRANK1_Spare0_MSK (0x000C0000) + #define DDRDATA2CH1_CR_TXTRAINRANK1_Spare0_MAX (0x00000003) + #define DDRDATA2CH1_CR_TXTRAINRANK1_TxEqualization_OFF (20) + #define DDRDATA2CH1_CR_TXTRAINRANK1_TxEqualization_WID ( 6) + #define DDRDATA2CH1_CR_TXTRAINRANK1_TxEqualization_MSK (0x03F00000) + #define DDRDATA2CH1_CR_TXTRAINRANK1_TxEqualization_MAX (0x0000003F) + #define DDRDATA2CH1_CR_TXTRAINRANK1_Spare1_OFF (26) + #define DDRDATA2CH1_CR_TXTRAINRANK1_Spare1_WID ( 6) + #define DDRDATA2CH1_CR_TXTRAINRANK1_Spare1_MSK (0xFC000000) + #define DDRDATA2CH1_CR_TXTRAINRANK1_Spare1_MAX (0x0000003F) + +#define DDRDATA2CH1_CR_TXTRAINRANK2_REG (0x00000528) + #define DDRDATA2CH1_CR_TXTRAINRANK2_TxDqDelay_OFF ( 0) + #define DDRDATA2CH1_CR_TXTRAINRANK2_TxDqDelay_WID ( 9) + #define DDRDATA2CH1_CR_TXTRAINRANK2_TxDqDelay_MSK (0x000001FF) + #define DDRDATA2CH1_CR_TXTRAINRANK2_TxDqDelay_MAX (0x000001FF) + #define DDRDATA2CH1_CR_TXTRAINRANK2_TxDqsDelay_OFF ( 9) + #define DDRDATA2CH1_CR_TXTRAINRANK2_TxDqsDelay_WID ( 9) + #define DDRDATA2CH1_CR_TXTRAINRANK2_TxDqsDelay_MSK (0x0003FE00) + #define DDRDATA2CH1_CR_TXTRAINRANK2_TxDqsDelay_MAX (0x000001FF) + #define DDRDATA2CH1_CR_TXTRAINRANK2_Spare0_OFF (18) + #define DDRDATA2CH1_CR_TXTRAINRANK2_Spare0_WID ( 2) + #define DDRDATA2CH1_CR_TXTRAINRANK2_Spare0_MSK (0x000C0000) + #define DDRDATA2CH1_CR_TXTRAINRANK2_Spare0_MAX (0x00000003) + #define DDRDATA2CH1_CR_TXTRAINRANK2_TxEqualization_OFF (20) + #define DDRDATA2CH1_CR_TXTRAINRANK2_TxEqualization_WID ( 6) + #define DDRDATA2CH1_CR_TXTRAINRANK2_TxEqualization_MSK (0x03F00000) + #define DDRDATA2CH1_CR_TXTRAINRANK2_TxEqualization_MAX (0x0000003F) + #define DDRDATA2CH1_CR_TXTRAINRANK2_Spare1_OFF (26) + #define DDRDATA2CH1_CR_TXTRAINRANK2_Spare1_WID ( 6) + #define DDRDATA2CH1_CR_TXTRAINRANK2_Spare1_MSK (0xFC000000) + #define DDRDATA2CH1_CR_TXTRAINRANK2_Spare1_MAX (0x0000003F) + +#define DDRDATA2CH1_CR_TXTRAINRANK3_REG (0x0000052C) + #define DDRDATA2CH1_CR_TXTRAINRANK3_TxDqDelay_OFF ( 0) + #define DDRDATA2CH1_CR_TXTRAINRANK3_TxDqDelay_WID ( 9) + #define DDRDATA2CH1_CR_TXTRAINRANK3_TxDqDelay_MSK (0x000001FF) + #define DDRDATA2CH1_CR_TXTRAINRANK3_TxDqDelay_MAX (0x000001FF) + #define DDRDATA2CH1_CR_TXTRAINRANK3_TxDqsDelay_OFF ( 9) + #define DDRDATA2CH1_CR_TXTRAINRANK3_TxDqsDelay_WID ( 9) + #define DDRDATA2CH1_CR_TXTRAINRANK3_TxDqsDelay_MSK (0x0003FE00) + #define DDRDATA2CH1_CR_TXTRAINRANK3_TxDqsDelay_MAX (0x000001FF) + #define DDRDATA2CH1_CR_TXTRAINRANK3_Spare0_OFF (18) + #define DDRDATA2CH1_CR_TXTRAINRANK3_Spare0_WID ( 2) + #define DDRDATA2CH1_CR_TXTRAINRANK3_Spare0_MSK (0x000C0000) + #define DDRDATA2CH1_CR_TXTRAINRANK3_Spare0_MAX (0x00000003) + #define DDRDATA2CH1_CR_TXTRAINRANK3_TxEqualization_OFF (20) + #define DDRDATA2CH1_CR_TXTRAINRANK3_TxEqualization_WID ( 6) + #define DDRDATA2CH1_CR_TXTRAINRANK3_TxEqualization_MSK (0x03F00000) + #define DDRDATA2CH1_CR_TXTRAINRANK3_TxEqualization_MAX (0x0000003F) + #define DDRDATA2CH1_CR_TXTRAINRANK3_Spare1_OFF (26) + #define DDRDATA2CH1_CR_TXTRAINRANK3_Spare1_WID ( 6) + #define DDRDATA2CH1_CR_TXTRAINRANK3_Spare1_MSK (0xFC000000) + #define DDRDATA2CH1_CR_TXTRAINRANK3_Spare1_MAX (0x0000003F) + +#define DDRDATA2CH1_CR_TXPERBITRANK0_REG (0x00000530) + #define DDRDATA2CH1_CR_TXPERBITRANK0_Lane0_OFF ( 0) + #define DDRDATA2CH1_CR_TXPERBITRANK0_Lane0_WID ( 4) + #define DDRDATA2CH1_CR_TXPERBITRANK0_Lane0_MSK (0x0000000F) + #define DDRDATA2CH1_CR_TXPERBITRANK0_Lane0_MAX (0x0000000F) + #define DDRDATA2CH1_CR_TXPERBITRANK0_Lane1_OFF ( 4) + #define DDRDATA2CH1_CR_TXPERBITRANK0_Lane1_WID ( 4) + #define DDRDATA2CH1_CR_TXPERBITRANK0_Lane1_MSK (0x000000F0) + #define DDRDATA2CH1_CR_TXPERBITRANK0_Lane1_MAX (0x0000000F) + #define DDRDATA2CH1_CR_TXPERBITRANK0_Lane2_OFF ( 8) + #define DDRDATA2CH1_CR_TXPERBITRANK0_Lane2_WID ( 4) + #define DDRDATA2CH1_CR_TXPERBITRANK0_Lane2_MSK (0x00000F00) + #define DDRDATA2CH1_CR_TXPERBITRANK0_Lane2_MAX (0x0000000F) + #define DDRDATA2CH1_CR_TXPERBITRANK0_Lane3_OFF (12) + #define DDRDATA2CH1_CR_TXPERBITRANK0_Lane3_WID ( 4) + #define DDRDATA2CH1_CR_TXPERBITRANK0_Lane3_MSK (0x0000F000) + #define DDRDATA2CH1_CR_TXPERBITRANK0_Lane3_MAX (0x0000000F) + #define DDRDATA2CH1_CR_TXPERBITRANK0_Lane4_OFF (16) + #define DDRDATA2CH1_CR_TXPERBITRANK0_Lane4_WID ( 4) + #define DDRDATA2CH1_CR_TXPERBITRANK0_Lane4_MSK (0x000F0000) + #define DDRDATA2CH1_CR_TXPERBITRANK0_Lane4_MAX (0x0000000F) + #define DDRDATA2CH1_CR_TXPERBITRANK0_Lane5_OFF (20) + #define DDRDATA2CH1_CR_TXPERBITRANK0_Lane5_WID ( 4) + #define DDRDATA2CH1_CR_TXPERBITRANK0_Lane5_MSK (0x00F00000) + #define DDRDATA2CH1_CR_TXPERBITRANK0_Lane5_MAX (0x0000000F) + #define DDRDATA2CH1_CR_TXPERBITRANK0_Lane6_OFF (24) + #define DDRDATA2CH1_CR_TXPERBITRANK0_Lane6_WID ( 4) + #define DDRDATA2CH1_CR_TXPERBITRANK0_Lane6_MSK (0x0F000000) + #define DDRDATA2CH1_CR_TXPERBITRANK0_Lane6_MAX (0x0000000F) + #define DDRDATA2CH1_CR_TXPERBITRANK0_Lane7_OFF (28) + #define DDRDATA2CH1_CR_TXPERBITRANK0_Lane7_WID ( 4) + #define DDRDATA2CH1_CR_TXPERBITRANK0_Lane7_MSK (0xF0000000) + #define DDRDATA2CH1_CR_TXPERBITRANK0_Lane7_MAX (0x0000000F) + +#define DDRDATA2CH1_CR_TXPERBITRANK1_REG (0x00000534) + #define DDRDATA2CH1_CR_TXPERBITRANK1_Lane0_OFF ( 0) + #define DDRDATA2CH1_CR_TXPERBITRANK1_Lane0_WID ( 4) + #define DDRDATA2CH1_CR_TXPERBITRANK1_Lane0_MSK (0x0000000F) + #define DDRDATA2CH1_CR_TXPERBITRANK1_Lane0_MAX (0x0000000F) + #define DDRDATA2CH1_CR_TXPERBITRANK1_Lane1_OFF ( 4) + #define DDRDATA2CH1_CR_TXPERBITRANK1_Lane1_WID ( 4) + #define DDRDATA2CH1_CR_TXPERBITRANK1_Lane1_MSK (0x000000F0) + #define DDRDATA2CH1_CR_TXPERBITRANK1_Lane1_MAX (0x0000000F) + #define DDRDATA2CH1_CR_TXPERBITRANK1_Lane2_OFF ( 8) + #define DDRDATA2CH1_CR_TXPERBITRANK1_Lane2_WID ( 4) + #define DDRDATA2CH1_CR_TXPERBITRANK1_Lane2_MSK (0x00000F00) + #define DDRDATA2CH1_CR_TXPERBITRANK1_Lane2_MAX (0x0000000F) + #define DDRDATA2CH1_CR_TXPERBITRANK1_Lane3_OFF (12) + #define DDRDATA2CH1_CR_TXPERBITRANK1_Lane3_WID ( 4) + #define DDRDATA2CH1_CR_TXPERBITRANK1_Lane3_MSK (0x0000F000) + #define DDRDATA2CH1_CR_TXPERBITRANK1_Lane3_MAX (0x0000000F) + #define DDRDATA2CH1_CR_TXPERBITRANK1_Lane4_OFF (16) + #define DDRDATA2CH1_CR_TXPERBITRANK1_Lane4_WID ( 4) + #define DDRDATA2CH1_CR_TXPERBITRANK1_Lane4_MSK (0x000F0000) + #define DDRDATA2CH1_CR_TXPERBITRANK1_Lane4_MAX (0x0000000F) + #define DDRDATA2CH1_CR_TXPERBITRANK1_Lane5_OFF (20) + #define DDRDATA2CH1_CR_TXPERBITRANK1_Lane5_WID ( 4) + #define DDRDATA2CH1_CR_TXPERBITRANK1_Lane5_MSK (0x00F00000) + #define DDRDATA2CH1_CR_TXPERBITRANK1_Lane5_MAX (0x0000000F) + #define DDRDATA2CH1_CR_TXPERBITRANK1_Lane6_OFF (24) + #define DDRDATA2CH1_CR_TXPERBITRANK1_Lane6_WID ( 4) + #define DDRDATA2CH1_CR_TXPERBITRANK1_Lane6_MSK (0x0F000000) + #define DDRDATA2CH1_CR_TXPERBITRANK1_Lane6_MAX (0x0000000F) + #define DDRDATA2CH1_CR_TXPERBITRANK1_Lane7_OFF (28) + #define DDRDATA2CH1_CR_TXPERBITRANK1_Lane7_WID ( 4) + #define DDRDATA2CH1_CR_TXPERBITRANK1_Lane7_MSK (0xF0000000) + #define DDRDATA2CH1_CR_TXPERBITRANK1_Lane7_MAX (0x0000000F) + +#define DDRDATA2CH1_CR_TXPERBITRANK2_REG (0x00000538) + #define DDRDATA2CH1_CR_TXPERBITRANK2_Lane0_OFF ( 0) + #define DDRDATA2CH1_CR_TXPERBITRANK2_Lane0_WID ( 4) + #define DDRDATA2CH1_CR_TXPERBITRANK2_Lane0_MSK (0x0000000F) + #define DDRDATA2CH1_CR_TXPERBITRANK2_Lane0_MAX (0x0000000F) + #define DDRDATA2CH1_CR_TXPERBITRANK2_Lane1_OFF ( 4) + #define DDRDATA2CH1_CR_TXPERBITRANK2_Lane1_WID ( 4) + #define DDRDATA2CH1_CR_TXPERBITRANK2_Lane1_MSK (0x000000F0) + #define DDRDATA2CH1_CR_TXPERBITRANK2_Lane1_MAX (0x0000000F) + #define DDRDATA2CH1_CR_TXPERBITRANK2_Lane2_OFF ( 8) + #define DDRDATA2CH1_CR_TXPERBITRANK2_Lane2_WID ( 4) + #define DDRDATA2CH1_CR_TXPERBITRANK2_Lane2_MSK (0x00000F00) + #define DDRDATA2CH1_CR_TXPERBITRANK2_Lane2_MAX (0x0000000F) + #define DDRDATA2CH1_CR_TXPERBITRANK2_Lane3_OFF (12) + #define DDRDATA2CH1_CR_TXPERBITRANK2_Lane3_WID ( 4) + #define DDRDATA2CH1_CR_TXPERBITRANK2_Lane3_MSK (0x0000F000) + #define DDRDATA2CH1_CR_TXPERBITRANK2_Lane3_MAX (0x0000000F) + #define DDRDATA2CH1_CR_TXPERBITRANK2_Lane4_OFF (16) + #define DDRDATA2CH1_CR_TXPERBITRANK2_Lane4_WID ( 4) + #define DDRDATA2CH1_CR_TXPERBITRANK2_Lane4_MSK (0x000F0000) + #define DDRDATA2CH1_CR_TXPERBITRANK2_Lane4_MAX (0x0000000F) + #define DDRDATA2CH1_CR_TXPERBITRANK2_Lane5_OFF (20) + #define DDRDATA2CH1_CR_TXPERBITRANK2_Lane5_WID ( 4) + #define DDRDATA2CH1_CR_TXPERBITRANK2_Lane5_MSK (0x00F00000) + #define DDRDATA2CH1_CR_TXPERBITRANK2_Lane5_MAX (0x0000000F) + #define DDRDATA2CH1_CR_TXPERBITRANK2_Lane6_OFF (24) + #define DDRDATA2CH1_CR_TXPERBITRANK2_Lane6_WID ( 4) + #define DDRDATA2CH1_CR_TXPERBITRANK2_Lane6_MSK (0x0F000000) + #define DDRDATA2CH1_CR_TXPERBITRANK2_Lane6_MAX (0x0000000F) + #define DDRDATA2CH1_CR_TXPERBITRANK2_Lane7_OFF (28) + #define DDRDATA2CH1_CR_TXPERBITRANK2_Lane7_WID ( 4) + #define DDRDATA2CH1_CR_TXPERBITRANK2_Lane7_MSK (0xF0000000) + #define DDRDATA2CH1_CR_TXPERBITRANK2_Lane7_MAX (0x0000000F) + +#define DDRDATA2CH1_CR_TXPERBITRANK3_REG (0x0000053C) + #define DDRDATA2CH1_CR_TXPERBITRANK3_Lane0_OFF ( 0) + #define DDRDATA2CH1_CR_TXPERBITRANK3_Lane0_WID ( 4) + #define DDRDATA2CH1_CR_TXPERBITRANK3_Lane0_MSK (0x0000000F) + #define DDRDATA2CH1_CR_TXPERBITRANK3_Lane0_MAX (0x0000000F) + #define DDRDATA2CH1_CR_TXPERBITRANK3_Lane1_OFF ( 4) + #define DDRDATA2CH1_CR_TXPERBITRANK3_Lane1_WID ( 4) + #define DDRDATA2CH1_CR_TXPERBITRANK3_Lane1_MSK (0x000000F0) + #define DDRDATA2CH1_CR_TXPERBITRANK3_Lane1_MAX (0x0000000F) + #define DDRDATA2CH1_CR_TXPERBITRANK3_Lane2_OFF ( 8) + #define DDRDATA2CH1_CR_TXPERBITRANK3_Lane2_WID ( 4) + #define DDRDATA2CH1_CR_TXPERBITRANK3_Lane2_MSK (0x00000F00) + #define DDRDATA2CH1_CR_TXPERBITRANK3_Lane2_MAX (0x0000000F) + #define DDRDATA2CH1_CR_TXPERBITRANK3_Lane3_OFF (12) + #define DDRDATA2CH1_CR_TXPERBITRANK3_Lane3_WID ( 4) + #define DDRDATA2CH1_CR_TXPERBITRANK3_Lane3_MSK (0x0000F000) + #define DDRDATA2CH1_CR_TXPERBITRANK3_Lane3_MAX (0x0000000F) + #define DDRDATA2CH1_CR_TXPERBITRANK3_Lane4_OFF (16) + #define DDRDATA2CH1_CR_TXPERBITRANK3_Lane4_WID ( 4) + #define DDRDATA2CH1_CR_TXPERBITRANK3_Lane4_MSK (0x000F0000) + #define DDRDATA2CH1_CR_TXPERBITRANK3_Lane4_MAX (0x0000000F) + #define DDRDATA2CH1_CR_TXPERBITRANK3_Lane5_OFF (20) + #define DDRDATA2CH1_CR_TXPERBITRANK3_Lane5_WID ( 4) + #define DDRDATA2CH1_CR_TXPERBITRANK3_Lane5_MSK (0x00F00000) + #define DDRDATA2CH1_CR_TXPERBITRANK3_Lane5_MAX (0x0000000F) + #define DDRDATA2CH1_CR_TXPERBITRANK3_Lane6_OFF (24) + #define DDRDATA2CH1_CR_TXPERBITRANK3_Lane6_WID ( 4) + #define DDRDATA2CH1_CR_TXPERBITRANK3_Lane6_MSK (0x0F000000) + #define DDRDATA2CH1_CR_TXPERBITRANK3_Lane6_MAX (0x0000000F) + #define DDRDATA2CH1_CR_TXPERBITRANK3_Lane7_OFF (28) + #define DDRDATA2CH1_CR_TXPERBITRANK3_Lane7_WID ( 4) + #define DDRDATA2CH1_CR_TXPERBITRANK3_Lane7_MSK (0xF0000000) + #define DDRDATA2CH1_CR_TXPERBITRANK3_Lane7_MAX (0x0000000F) + +#define DDRDATA2CH1_CR_RCOMPDATA0_REG (0x00000540) + #define DDRDATA2CH1_CR_RCOMPDATA0_RcompDrvUp_OFF ( 0) + #define DDRDATA2CH1_CR_RCOMPDATA0_RcompDrvUp_WID ( 6) + #define DDRDATA2CH1_CR_RCOMPDATA0_RcompDrvUp_MSK (0x0000003F) + #define DDRDATA2CH1_CR_RCOMPDATA0_RcompDrvUp_MAX (0x0000003F) + #define DDRDATA2CH1_CR_RCOMPDATA0_Spare0_OFF ( 6) + #define DDRDATA2CH1_CR_RCOMPDATA0_Spare0_WID ( 3) + #define DDRDATA2CH1_CR_RCOMPDATA0_Spare0_MSK (0x000001C0) + #define DDRDATA2CH1_CR_RCOMPDATA0_Spare0_MAX (0x00000007) + #define DDRDATA2CH1_CR_RCOMPDATA0_RcompDrvDown_OFF ( 9) + #define DDRDATA2CH1_CR_RCOMPDATA0_RcompDrvDown_WID ( 6) + #define DDRDATA2CH1_CR_RCOMPDATA0_RcompDrvDown_MSK (0x00007E00) + #define DDRDATA2CH1_CR_RCOMPDATA0_RcompDrvDown_MAX (0x0000003F) + #define DDRDATA2CH1_CR_RCOMPDATA0_VTComp_OFF (15) + #define DDRDATA2CH1_CR_RCOMPDATA0_VTComp_WID ( 5) + #define DDRDATA2CH1_CR_RCOMPDATA0_VTComp_MSK (0x000F8000) + #define DDRDATA2CH1_CR_RCOMPDATA0_VTComp_MAX (0x0000001F) + #define DDRDATA2CH1_CR_RCOMPDATA0_TcoComp_OFF (20) + #define DDRDATA2CH1_CR_RCOMPDATA0_TcoComp_WID ( 6) + #define DDRDATA2CH1_CR_RCOMPDATA0_TcoComp_MSK (0x03F00000) + #define DDRDATA2CH1_CR_RCOMPDATA0_TcoComp_MAX (0x0000003F) + #define DDRDATA2CH1_CR_RCOMPDATA0_SlewRateComp_OFF (26) + #define DDRDATA2CH1_CR_RCOMPDATA0_SlewRateComp_WID ( 5) + #define DDRDATA2CH1_CR_RCOMPDATA0_SlewRateComp_MSK (0x7C000000) + #define DDRDATA2CH1_CR_RCOMPDATA0_SlewRateComp_MAX (0x0000001F) + #define DDRDATA2CH1_CR_RCOMPDATA0_Spare2_OFF (31) + #define DDRDATA2CH1_CR_RCOMPDATA0_Spare2_WID ( 1) + #define DDRDATA2CH1_CR_RCOMPDATA0_Spare2_MSK (0x80000000) + #define DDRDATA2CH1_CR_RCOMPDATA0_Spare2_MAX (0x00000001) + +#define DDRDATA2CH1_CR_RCOMPDATA1_REG (0x00000544) + #define DDRDATA2CH1_CR_RCOMPDATA1_RcompOdtUp_OFF ( 0) + #define DDRDATA2CH1_CR_RCOMPDATA1_RcompOdtUp_WID ( 6) + #define DDRDATA2CH1_CR_RCOMPDATA1_RcompOdtUp_MSK (0x0000003F) + #define DDRDATA2CH1_CR_RCOMPDATA1_RcompOdtUp_MAX (0x0000003F) + #define DDRDATA2CH1_CR_RCOMPDATA1_Spare0_OFF ( 6) + #define DDRDATA2CH1_CR_RCOMPDATA1_Spare0_WID ( 3) + #define DDRDATA2CH1_CR_RCOMPDATA1_Spare0_MSK (0x000001C0) + #define DDRDATA2CH1_CR_RCOMPDATA1_Spare0_MAX (0x00000007) + #define DDRDATA2CH1_CR_RCOMPDATA1_RcompOdtDown_OFF ( 9) + #define DDRDATA2CH1_CR_RCOMPDATA1_RcompOdtDown_WID ( 6) + #define DDRDATA2CH1_CR_RCOMPDATA1_RcompOdtDown_MSK (0x00007E00) + #define DDRDATA2CH1_CR_RCOMPDATA1_RcompOdtDown_MAX (0x0000003F) + #define DDRDATA2CH1_CR_RCOMPDATA1_Spare1_OFF (15) + #define DDRDATA2CH1_CR_RCOMPDATA1_Spare1_WID ( 1) + #define DDRDATA2CH1_CR_RCOMPDATA1_Spare1_MSK (0x00008000) + #define DDRDATA2CH1_CR_RCOMPDATA1_Spare1_MAX (0x00000001) + #define DDRDATA2CH1_CR_RCOMPDATA1_PanicDrvDn_OFF (16) + #define DDRDATA2CH1_CR_RCOMPDATA1_PanicDrvDn_WID ( 6) + #define DDRDATA2CH1_CR_RCOMPDATA1_PanicDrvDn_MSK (0x003F0000) + #define DDRDATA2CH1_CR_RCOMPDATA1_PanicDrvDn_MAX (0x0000003F) + #define DDRDATA2CH1_CR_RCOMPDATA1_PanicDrvUp_OFF (22) + #define DDRDATA2CH1_CR_RCOMPDATA1_PanicDrvUp_WID ( 6) + #define DDRDATA2CH1_CR_RCOMPDATA1_PanicDrvUp_MSK (0x0FC00000) + #define DDRDATA2CH1_CR_RCOMPDATA1_PanicDrvUp_MAX (0x0000003F) + #define DDRDATA2CH1_CR_RCOMPDATA1_LevelShifterComp_OFF (28) + #define DDRDATA2CH1_CR_RCOMPDATA1_LevelShifterComp_WID ( 3) + #define DDRDATA2CH1_CR_RCOMPDATA1_LevelShifterComp_MSK (0x70000000) + #define DDRDATA2CH1_CR_RCOMPDATA1_LevelShifterComp_MAX (0x00000007) + #define DDRDATA2CH1_CR_RCOMPDATA1_Spare2_OFF (31) + #define DDRDATA2CH1_CR_RCOMPDATA1_Spare2_WID ( 1) + #define DDRDATA2CH1_CR_RCOMPDATA1_Spare2_MSK (0x80000000) + #define DDRDATA2CH1_CR_RCOMPDATA1_Spare2_MAX (0x00000001) + +#define DDRDATA2CH1_CR_TXXTALK_REG (0x00000548) + #define DDRDATA2CH1_CR_TXXTALK_Lane0_OFF ( 0) + #define DDRDATA2CH1_CR_TXXTALK_Lane0_WID ( 4) + #define DDRDATA2CH1_CR_TXXTALK_Lane0_MSK (0x0000000F) + #define DDRDATA2CH1_CR_TXXTALK_Lane0_MAX (0x0000000F) + #define DDRDATA2CH1_CR_TXXTALK_Lane1_OFF ( 4) + #define DDRDATA2CH1_CR_TXXTALK_Lane1_WID ( 4) + #define DDRDATA2CH1_CR_TXXTALK_Lane1_MSK (0x000000F0) + #define DDRDATA2CH1_CR_TXXTALK_Lane1_MAX (0x0000000F) + #define DDRDATA2CH1_CR_TXXTALK_Lane2_OFF ( 8) + #define DDRDATA2CH1_CR_TXXTALK_Lane2_WID ( 4) + #define DDRDATA2CH1_CR_TXXTALK_Lane2_MSK (0x00000F00) + #define DDRDATA2CH1_CR_TXXTALK_Lane2_MAX (0x0000000F) + #define DDRDATA2CH1_CR_TXXTALK_Lane3_OFF (12) + #define DDRDATA2CH1_CR_TXXTALK_Lane3_WID ( 4) + #define DDRDATA2CH1_CR_TXXTALK_Lane3_MSK (0x0000F000) + #define DDRDATA2CH1_CR_TXXTALK_Lane3_MAX (0x0000000F) + #define DDRDATA2CH1_CR_TXXTALK_Lane4_OFF (16) + #define DDRDATA2CH1_CR_TXXTALK_Lane4_WID ( 4) + #define DDRDATA2CH1_CR_TXXTALK_Lane4_MSK (0x000F0000) + #define DDRDATA2CH1_CR_TXXTALK_Lane4_MAX (0x0000000F) + #define DDRDATA2CH1_CR_TXXTALK_Lane5_OFF (20) + #define DDRDATA2CH1_CR_TXXTALK_Lane5_WID ( 4) + #define DDRDATA2CH1_CR_TXXTALK_Lane5_MSK (0x00F00000) + #define DDRDATA2CH1_CR_TXXTALK_Lane5_MAX (0x0000000F) + #define DDRDATA2CH1_CR_TXXTALK_Lane6_OFF (24) + #define DDRDATA2CH1_CR_TXXTALK_Lane6_WID ( 4) + #define DDRDATA2CH1_CR_TXXTALK_Lane6_MSK (0x0F000000) + #define DDRDATA2CH1_CR_TXXTALK_Lane6_MAX (0x0000000F) + #define DDRDATA2CH1_CR_TXXTALK_Lane7_OFF (28) + #define DDRDATA2CH1_CR_TXXTALK_Lane7_WID ( 4) + #define DDRDATA2CH1_CR_TXXTALK_Lane7_MSK (0xF0000000) + #define DDRDATA2CH1_CR_TXXTALK_Lane7_MAX (0x0000000F) + +#define DDRDATA2CH1_CR_RXOFFSETVDQ_REG (0x0000054C) + #define DDRDATA2CH1_CR_RXOFFSETVDQ_Lane0_OFF ( 0) + #define DDRDATA2CH1_CR_RXOFFSETVDQ_Lane0_WID ( 4) + #define DDRDATA2CH1_CR_RXOFFSETVDQ_Lane0_MSK (0x0000000F) + #define DDRDATA2CH1_CR_RXOFFSETVDQ_Lane0_MAX (0x0000000F) + #define DDRDATA2CH1_CR_RXOFFSETVDQ_Lane1_OFF ( 4) + #define DDRDATA2CH1_CR_RXOFFSETVDQ_Lane1_WID ( 4) + #define DDRDATA2CH1_CR_RXOFFSETVDQ_Lane1_MSK (0x000000F0) + #define DDRDATA2CH1_CR_RXOFFSETVDQ_Lane1_MAX (0x0000000F) + #define DDRDATA2CH1_CR_RXOFFSETVDQ_Lane2_OFF ( 8) + #define DDRDATA2CH1_CR_RXOFFSETVDQ_Lane2_WID ( 4) + #define DDRDATA2CH1_CR_RXOFFSETVDQ_Lane2_MSK (0x00000F00) + #define DDRDATA2CH1_CR_RXOFFSETVDQ_Lane2_MAX (0x0000000F) + #define DDRDATA2CH1_CR_RXOFFSETVDQ_Lane3_OFF (12) + #define DDRDATA2CH1_CR_RXOFFSETVDQ_Lane3_WID ( 4) + #define DDRDATA2CH1_CR_RXOFFSETVDQ_Lane3_MSK (0x0000F000) + #define DDRDATA2CH1_CR_RXOFFSETVDQ_Lane3_MAX (0x0000000F) + #define DDRDATA2CH1_CR_RXOFFSETVDQ_Lane4_OFF (16) + #define DDRDATA2CH1_CR_RXOFFSETVDQ_Lane4_WID ( 4) + #define DDRDATA2CH1_CR_RXOFFSETVDQ_Lane4_MSK (0x000F0000) + #define DDRDATA2CH1_CR_RXOFFSETVDQ_Lane4_MAX (0x0000000F) + #define DDRDATA2CH1_CR_RXOFFSETVDQ_Lane5_OFF (20) + #define DDRDATA2CH1_CR_RXOFFSETVDQ_Lane5_WID ( 4) + #define DDRDATA2CH1_CR_RXOFFSETVDQ_Lane5_MSK (0x00F00000) + #define DDRDATA2CH1_CR_RXOFFSETVDQ_Lane5_MAX (0x0000000F) + #define DDRDATA2CH1_CR_RXOFFSETVDQ_Lane6_OFF (24) + #define DDRDATA2CH1_CR_RXOFFSETVDQ_Lane6_WID ( 4) + #define DDRDATA2CH1_CR_RXOFFSETVDQ_Lane6_MSK (0x0F000000) + #define DDRDATA2CH1_CR_RXOFFSETVDQ_Lane6_MAX (0x0000000F) + #define DDRDATA2CH1_CR_RXOFFSETVDQ_Lane7_OFF (28) + #define DDRDATA2CH1_CR_RXOFFSETVDQ_Lane7_WID ( 4) + #define DDRDATA2CH1_CR_RXOFFSETVDQ_Lane7_MSK (0xF0000000) + #define DDRDATA2CH1_CR_RXOFFSETVDQ_Lane7_MAX (0x0000000F) + +#define DDRDATA2CH1_CR_DDRDATARESERVED_REG (0x00000550) + #define DDRDATA2CH1_CR_DDRDATARESERVED_Spare_OFF ( 0) + #define DDRDATA2CH1_CR_DDRDATARESERVED_Spare_WID (32) + #define DDRDATA2CH1_CR_DDRDATARESERVED_Spare_MSK (0xFFFFFFFF) + #define DDRDATA2CH1_CR_DDRDATARESERVED_Spare_MAX (0xFFFFFFFF) + +#define DDRDATA2CH1_CR_DATATRAINFEEDBACK_REG (0x00000554) + #define DDRDATA2CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_OFF ( 0) + #define DDRDATA2CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_WID ( 9) + #define DDRDATA2CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_MSK (0x000001FF) + #define DDRDATA2CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_MAX (0x000001FF) + #define DDRDATA2CH1_CR_DATATRAINFEEDBACK_Spare_OFF ( 9) + #define DDRDATA2CH1_CR_DATATRAINFEEDBACK_Spare_WID (23) + #define DDRDATA2CH1_CR_DATATRAINFEEDBACK_Spare_MSK (0xFFFFFE00) + #define DDRDATA2CH1_CR_DATATRAINFEEDBACK_Spare_MAX (0x007FFFFF) + +#define DDRDATA2CH1_CR_DLLPITESTANDADC_REG (0x00000558) + #define DDRDATA2CH1_CR_DLLPITESTANDADC_RunTest_OFF ( 0) + #define DDRDATA2CH1_CR_DLLPITESTANDADC_RunTest_WID ( 1) + #define DDRDATA2CH1_CR_DLLPITESTANDADC_RunTest_MSK (0x00000001) + #define DDRDATA2CH1_CR_DLLPITESTANDADC_RunTest_MAX (0x00000001) + #define DDRDATA2CH1_CR_DLLPITESTANDADC_RunTest_DEF (0x00000000) + #define DDRDATA2CH1_CR_DLLPITESTANDADC_Load_OFF ( 1) + #define DDRDATA2CH1_CR_DLLPITESTANDADC_Load_WID ( 1) + #define DDRDATA2CH1_CR_DLLPITESTANDADC_Load_MSK (0x00000002) + #define DDRDATA2CH1_CR_DLLPITESTANDADC_Load_MAX (0x00000001) + #define DDRDATA2CH1_CR_DLLPITESTANDADC_Load_DEF (0x00000000) + #define DDRDATA2CH1_CR_DLLPITESTANDADC_ModeHVM_OFF ( 2) + #define DDRDATA2CH1_CR_DLLPITESTANDADC_ModeHVM_WID ( 1) + #define DDRDATA2CH1_CR_DLLPITESTANDADC_ModeHVM_MSK (0x00000004) + #define DDRDATA2CH1_CR_DLLPITESTANDADC_ModeHVM_MAX (0x00000001) + #define DDRDATA2CH1_CR_DLLPITESTANDADC_ModeHVM_DEF (0x00000000) + #define DDRDATA2CH1_CR_DLLPITESTANDADC_ModeDV_OFF ( 3) + #define DDRDATA2CH1_CR_DLLPITESTANDADC_ModeDV_WID ( 1) + #define DDRDATA2CH1_CR_DLLPITESTANDADC_ModeDV_MSK (0x00000008) + #define DDRDATA2CH1_CR_DLLPITESTANDADC_ModeDV_MAX (0x00000001) + #define DDRDATA2CH1_CR_DLLPITESTANDADC_ModeDV_DEF (0x00000000) + #define DDRDATA2CH1_CR_DLLPITESTANDADC_ModeADC_OFF ( 4) + #define DDRDATA2CH1_CR_DLLPITESTANDADC_ModeADC_WID ( 1) + #define DDRDATA2CH1_CR_DLLPITESTANDADC_ModeADC_MSK (0x00000010) + #define DDRDATA2CH1_CR_DLLPITESTANDADC_ModeADC_MAX (0x00000001) + #define DDRDATA2CH1_CR_DLLPITESTANDADC_ModeADC_DEF (0x00000000) + #define DDRDATA2CH1_CR_DLLPITESTANDADC_LoadCount_OFF ( 5) + #define DDRDATA2CH1_CR_DLLPITESTANDADC_LoadCount_WID (10) + #define DDRDATA2CH1_CR_DLLPITESTANDADC_LoadCount_MSK (0x00007FE0) + #define DDRDATA2CH1_CR_DLLPITESTANDADC_LoadCount_MAX (0x000003FF) + #define DDRDATA2CH1_CR_DLLPITESTANDADC_CountStatus_OFF (15) + #define DDRDATA2CH1_CR_DLLPITESTANDADC_CountStatus_WID (10) + #define DDRDATA2CH1_CR_DLLPITESTANDADC_CountStatus_MSK (0x01FF8000) + #define DDRDATA2CH1_CR_DLLPITESTANDADC_CountStatus_MAX (0x000003FF) + #define DDRDATA2CH1_CR_DLLPITESTANDADC_CountStatus_DEF (0x00000000) + #define DDRDATA2CH1_CR_DLLPITESTANDADC_Spare_OFF (25) + #define DDRDATA2CH1_CR_DLLPITESTANDADC_Spare_WID ( 7) + #define DDRDATA2CH1_CR_DLLPITESTANDADC_Spare_MSK (0xFE000000) + #define DDRDATA2CH1_CR_DLLPITESTANDADC_Spare_MAX (0x0000007F) + +#define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_REG (0x0000055C) + #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_OFF ( 0) + #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_WID ( 6) + #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MSK (0x0000003F) + #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MAX (0x0000003F) + #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_DEF (0x00000000) + #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_OFF ( 6) + #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_WID ( 6) + #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MSK (0x00000FC0) + #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MAX (0x0000003F) + #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_DEF (0x00000000) + #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_OFF (12) + #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_WID ( 5) + #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MSK (0x0001F000) + #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MAX (0x0000001F) + #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_DEF (0x00000000) + #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_OFF (17) + #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_WID ( 5) + #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MSK (0x003E0000) + #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MAX (0x0000001F) + #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_DEF (0x00000000) + #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_OFF (22) + #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_WID ( 5) + #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_MSK (0x07C00000) + #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_MAX (0x0000001F) + #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_DEF (0x00000000) + #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_OFF (27) + #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_WID ( 5) + #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MSK (0xF8000000) + #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MAX (0x0000001F) + #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_DEF (0x00000000) + +#define DDRDATA2CH1_CR_DDRCRDATACONTROL1_REG (0x00000560) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_RefPi_OFF ( 0) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_RefPi_WID ( 4) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_RefPi_MSK (0x0000000F) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_RefPi_MAX (0x0000000F) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_RefPi_DEF (0x00000000) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_DllMask_OFF ( 4) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_DllMask_WID ( 2) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_DllMask_MSK (0x00000030) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_DllMask_MAX (0x00000003) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_DllMask_DEF (0x00000000) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_DllWeakLock_OFF ( 6) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_DllWeakLock_WID ( 1) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_DllWeakLock_MSK (0x00000040) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_DllWeakLock_MAX (0x00000001) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_DllWeakLock_DEF (0x00000000) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_OFF ( 7) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_WID ( 3) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MSK (0x00000380) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MAX (0x00000007) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_DEF (0x00000000) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_OFF (10) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_WID ( 3) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_MSK (0x00001C00) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_MAX (0x00000007) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_DEF (0x00000000) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_OdtDelay_OFF (13) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_OdtDelay_WID ( 4) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_OdtDelay_MSK (0x0001E000) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_OdtDelay_MAX (0x0000000F) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_OdtDelay_DEF (0x00000000) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_OdtDuration_OFF (17) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_OdtDuration_WID ( 3) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_OdtDuration_MSK (0x000E0000) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_OdtDuration_MAX (0x00000007) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_OdtDuration_DEF (0x00000000) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_OFF (20) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_WID ( 4) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_MSK (0x00F00000) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_MAX (0x0000000F) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_DEF (0x00000000) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_OFF (24) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_WID ( 3) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_MSK (0x07000000) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_MAX (0x00000007) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_DEF (0x00000000) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_OFF (27) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_WID ( 3) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_MSK (0x38000000) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_MAX (0x00000007) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_DEF (0x00000000) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_OFF (30) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_WID ( 1) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_MSK (0x40000000) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_MAX (0x00000001) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_DEF (0x00000000) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_Rsvd1_OFF (31) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_Rsvd1_WID ( 1) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_Rsvd1_MSK (0x80000000) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_Rsvd1_MAX (0x00000001) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_Rsvd1_DEF (0x00000000) + +#define DDRDATA2CH1_CR_DDRCRDATACONTROL2_REG (0x00000564) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_OFF ( 0) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_WID ( 5) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_MSK (0x0000001F) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_MAX (0x0000001F) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_DEF (0x00000000) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_OFF ( 5) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_WID ( 1) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_MSK (0x00000020) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_MAX (0x00000001) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_DEF (0x00000000) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_ForceRxOn_OFF ( 6) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_ForceRxOn_WID ( 1) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_ForceRxOn_MSK (0x00000040) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_ForceRxOn_MAX (0x00000001) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_ForceRxOn_DEF (0x00000000) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_LeakerComp_OFF ( 7) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_LeakerComp_WID ( 2) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_LeakerComp_MSK (0x00000180) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_LeakerComp_MAX (0x00000003) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_LeakerComp_DEF (0x00000000) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_OFF ( 9) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_WID ( 4) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_MSK (0x00001E00) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_MAX (0x0000000F) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_DEF (0x00000008) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_OFF (13) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_WID ( 5) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_MSK (0x0003E000) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_MAX (0x0000001F) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_DEF (0x00000011) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_OFF (18) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_WID ( 1) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_MSK (0x00040000) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_MAX (0x00000001) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_DEF (0x00000000) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_Spare_OFF (19) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_Spare_WID (13) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_Spare_MSK (0xFFF80000) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_Spare_MAX (0x00001FFF) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_Spare_DEF (0x00000000) + +#define DDRDATA2CH1_CR_DDRCRVSSHIORVREFCONTROL_REG (0x0000056C) + #define DDRDATA2CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_OFF ( 0) + #define DDRDATA2CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_WID (24) + #define DDRDATA2CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_MSK (0x00FFFFFF) + #define DDRDATA2CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_MAX (0x00FFFFFF) + #define DDRDATA2CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_DEF (0x00000000) + #define DDRDATA2CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_OFF (24) + #define DDRDATA2CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_WID ( 8) + #define DDRDATA2CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_MSK (0xFF000000) + #define DDRDATA2CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_MAX (0x000000FF) + #define DDRDATA2CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_DEF (0x00000000) + +#define DDRDATA2CH1_CR_DDRCRDATAOFFSETTRAIN_REG (0x00000570) + #define DDRDATA2CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_OFF ( 0) + #define DDRDATA2CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_WID ( 6) + #define DDRDATA2CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MSK (0x0000003F) + #define DDRDATA2CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MAX (0x0000003F) + #define DDRDATA2CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_DEF (0x00000000) + #define DDRDATA2CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_OFF ( 6) + #define DDRDATA2CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_WID ( 6) + #define DDRDATA2CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MSK (0x00000FC0) + #define DDRDATA2CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MAX (0x0000003F) + #define DDRDATA2CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_DEF (0x00000000) + #define DDRDATA2CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_OFF (12) + #define DDRDATA2CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_WID ( 6) + #define DDRDATA2CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MSK (0x0003F000) + #define DDRDATA2CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MAX (0x0000003F) + #define DDRDATA2CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_DEF (0x00000000) + #define DDRDATA2CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_OFF (18) + #define DDRDATA2CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_WID ( 6) + #define DDRDATA2CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MSK (0x00FC0000) + #define DDRDATA2CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MAX (0x0000003F) + #define DDRDATA2CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_DEF (0x00000000) + #define DDRDATA2CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_OFF (24) + #define DDRDATA2CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_WID ( 7) + #define DDRDATA2CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MSK (0x7F000000) + #define DDRDATA2CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MAX (0x0000007F) + #define DDRDATA2CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_DEF (0x00000000) + #define DDRDATA2CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_OFF (31) + #define DDRDATA2CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_WID ( 1) + #define DDRDATA2CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_MSK (0x80000000) + #define DDRDATA2CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_MAX (0x00000001) + #define DDRDATA2CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_DEF (0x00000000) + +#define DDRDATA2CH1_CR_DDRCRDATACONTROL0_REG (0x00000574) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_OFF ( 0) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_WID ( 1) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_MSK (0x00000001) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_MAX (0x00000001) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_DEF (0x00000000) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_OFF ( 1) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_WID ( 1) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_MSK (0x00000002) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_MAX (0x00000001) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_DEF (0x00000000) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_OFF ( 2) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_WID ( 1) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_MSK (0x00000004) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_MAX (0x00000001) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_DEF (0x00000000) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_OFF ( 3) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_WID ( 1) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MSK (0x00000008) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MAX (0x00000001) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_DEF (0x00000000) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_TxOn_OFF ( 4) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_TxOn_WID ( 1) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_TxOn_MSK (0x00000010) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_TxOn_MAX (0x00000001) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_TxOn_DEF (0x00000000) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RfOn_OFF ( 5) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RfOn_WID ( 1) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RfOn_MSK (0x00000020) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RfOn_MAX (0x00000001) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RfOn_DEF (0x00000000) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RxPiOn_OFF ( 6) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RxPiOn_WID ( 1) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RxPiOn_MSK (0x00000040) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RxPiOn_MAX (0x00000001) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RxPiOn_DEF (0x00000000) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_TxPiOn_OFF ( 7) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_TxPiOn_WID ( 1) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_TxPiOn_MSK (0x00000080) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_TxPiOn_MAX (0x00000001) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_TxPiOn_DEF (0x00000000) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_OFF ( 8) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_WID ( 1) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_MSK (0x00000100) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_MAX (0x00000001) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_DEF (0x00000000) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_OFF ( 9) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_WID ( 1) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MSK (0x00000200) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MAX (0x00000001) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_DEF (0x00000000) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_TxDisable_OFF (10) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_TxDisable_WID ( 1) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_TxDisable_MSK (0x00000400) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_TxDisable_MAX (0x00000001) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_TxDisable_DEF (0x00000000) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RxDisable_OFF (11) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RxDisable_WID ( 1) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RxDisable_MSK (0x00000800) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RxDisable_MAX (0x00000001) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RxDisable_DEF (0x00000000) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_TxLong_OFF (12) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_TxLong_WID ( 1) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_TxLong_MSK (0x00001000) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_TxLong_MAX (0x00000001) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_TxLong_DEF (0x00000000) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_OFF (13) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_WID ( 2) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_MSK (0x00006000) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_MAX (0x00000003) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_DEF (0x00000000) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RxReadPointer_OFF (15) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RxReadPointer_WID ( 3) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RxReadPointer_MSK (0x00038000) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RxReadPointer_MAX (0x00000007) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RxReadPointer_DEF (0x00000000) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_OFF (18) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_WID ( 1) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_MSK (0x00040000) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_MAX (0x00000001) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_DEF (0x00000000) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_OFF (19) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_WID ( 1) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_MSK (0x00080000) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_MAX (0x00000001) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_DEF (0x00000000) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_ReadRFRd_OFF (20) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_ReadRFRd_WID ( 1) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_ReadRFRd_MSK (0x00100000) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_ReadRFRd_MAX (0x00000001) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_ReadRFRd_DEF (0x00000000) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_ReadRFWr_OFF (21) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_ReadRFWr_WID ( 1) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_ReadRFWr_MSK (0x00200000) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_ReadRFWr_MAX (0x00000001) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_ReadRFWr_DEF (0x00000000) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_ReadRFRank_OFF (22) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_ReadRFRank_WID ( 2) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_ReadRFRank_MSK (0x00C00000) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_ReadRFRank_MAX (0x00000003) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_ReadRFRank_DEF (0x00000000) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_OFF (24) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_WID ( 1) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_MSK (0x01000000) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_MAX (0x00000001) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_DEF (0x00000000) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_OdtSampOff_OFF (25) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_OdtSampOff_WID ( 1) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_OdtSampOff_MSK (0x02000000) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_OdtSampOff_MAX (0x00000001) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_OdtSampOff_DEF (0x00000000) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_OFF (26) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_WID ( 1) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_MSK (0x04000000) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_MAX (0x00000001) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_DEF (0x00000000) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_OFF (27) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_WID ( 1) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MSK (0x08000000) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MAX (0x00000001) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_DEF (0x00000000) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_OFF (28) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_WID ( 1) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_MSK (0x10000000) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_MAX (0x00000001) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_DEF (0x00000000) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_OFF (29) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_WID ( 1) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_MSK (0x20000000) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_MAX (0x00000001) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_DEF (0x00000000) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_OFF (30) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_WID ( 1) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MSK (0x40000000) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MAX (0x00000001) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_DEF (0x00000000) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_OFF (31) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_WID ( 1) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_MSK (0x80000000) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_MAX (0x00000001) + #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_DEF (0x00000000) + +#define DDRDATA2CH1_CR_DDRCRVREFADJUST1_REG (0x00000578) + #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_OFF ( 0) + #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_WID ( 7) + #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_MSK (0x0000007F) + #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_MAX (0x0000007F) + #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_DEF (0x00000000) + #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_OFF ( 7) + #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_WID ( 7) + #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_MSK (0x00003F80) + #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_MAX (0x0000007F) + #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_DEF (0x00000000) + #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_OFF (14) + #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_WID ( 7) + #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_MSK (0x001FC000) + #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_MAX (0x0000007F) + #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_DEF (0x00000000) + #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_OFF (21) + #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_WID ( 1) + #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_MSK (0x00200000) + #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_MAX (0x00000001) + #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_DEF (0x00000000) + #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_OFF (22) + #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_WID ( 1) + #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_MSK (0x00400000) + #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_MAX (0x00000001) + #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_DEF (0x00000000) + #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_OFF (23) + #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_WID ( 1) + #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_MSK (0x00800000) + #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_MAX (0x00000001) + #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_DEF (0x00000000) + #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_OFF (24) + #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_WID ( 2) + #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_MSK (0x03000000) + #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_MAX (0x00000003) + #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_DEF (0x00000000) + #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_OFF (26) + #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_WID ( 1) + #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_MSK (0x04000000) + #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_MAX (0x00000001) + #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_DEF (0x00000000) + #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_Rsvd_OFF (27) + #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_Rsvd_WID ( 2) + #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_Rsvd_MSK (0x18000000) + #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_Rsvd_MAX (0x00000003) + #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_Rsvd_DEF (0x00000000) + #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_caSlowBW_OFF (29) + #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_caSlowBW_WID ( 1) + #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_caSlowBW_MSK (0x20000000) + #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_caSlowBW_MAX (0x00000001) + #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_caSlowBW_DEF (0x00000000) + #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_OFF (30) + #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_WID ( 1) + #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_MSK (0x40000000) + #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_MAX (0x00000001) + #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_DEF (0x00000000) + #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_OFF (31) + #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_WID ( 1) + #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_MSK (0x80000000) + #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_MAX (0x00000001) + #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_DEF (0x00000000) + +#define DDRDATA3CH0_CR_RXTRAINRANK0_REG (0x00000600) + #define DDRDATA3CH0_CR_RXTRAINRANK0_RxRcvEnPi_OFF ( 0) + #define DDRDATA3CH0_CR_RXTRAINRANK0_RxRcvEnPi_WID ( 9) + #define DDRDATA3CH0_CR_RXTRAINRANK0_RxRcvEnPi_MSK (0x000001FF) + #define DDRDATA3CH0_CR_RXTRAINRANK0_RxRcvEnPi_MAX (0x000001FF) + #define DDRDATA3CH0_CR_RXTRAINRANK0_RxDqsPPi_OFF ( 9) + #define DDRDATA3CH0_CR_RXTRAINRANK0_RxDqsPPi_WID ( 6) + #define DDRDATA3CH0_CR_RXTRAINRANK0_RxDqsPPi_MSK (0x00007E00) + #define DDRDATA3CH0_CR_RXTRAINRANK0_RxDqsPPi_MAX (0x0000003F) + #define DDRDATA3CH0_CR_RXTRAINRANK0_RxEq_OFF (15) + #define DDRDATA3CH0_CR_RXTRAINRANK0_RxEq_WID ( 5) + #define DDRDATA3CH0_CR_RXTRAINRANK0_RxEq_MSK (0x000F8000) + #define DDRDATA3CH0_CR_RXTRAINRANK0_RxEq_MAX (0x0000001F) + #define DDRDATA3CH0_CR_RXTRAINRANK0_RxDqsNPi_OFF (20) + #define DDRDATA3CH0_CR_RXTRAINRANK0_RxDqsNPi_WID ( 6) + #define DDRDATA3CH0_CR_RXTRAINRANK0_RxDqsNPi_MSK (0x03F00000) + #define DDRDATA3CH0_CR_RXTRAINRANK0_RxDqsNPi_MAX (0x0000003F) + #define DDRDATA3CH0_CR_RXTRAINRANK0_RxVref_OFF (26) + #define DDRDATA3CH0_CR_RXTRAINRANK0_RxVref_WID ( 6) + #define DDRDATA3CH0_CR_RXTRAINRANK0_RxVref_MSK (0xFC000000) + #define DDRDATA3CH0_CR_RXTRAINRANK0_RxVref_MAX (0x0000003F) + +#define DDRDATA3CH0_CR_RXTRAINRANK1_REG (0x00000604) + #define DDRDATA3CH0_CR_RXTRAINRANK1_RxRcvEnPi_OFF ( 0) + #define DDRDATA3CH0_CR_RXTRAINRANK1_RxRcvEnPi_WID ( 9) + #define DDRDATA3CH0_CR_RXTRAINRANK1_RxRcvEnPi_MSK (0x000001FF) + #define DDRDATA3CH0_CR_RXTRAINRANK1_RxRcvEnPi_MAX (0x000001FF) + #define DDRDATA3CH0_CR_RXTRAINRANK1_RxDqsPPi_OFF ( 9) + #define DDRDATA3CH0_CR_RXTRAINRANK1_RxDqsPPi_WID ( 6) + #define DDRDATA3CH0_CR_RXTRAINRANK1_RxDqsPPi_MSK (0x00007E00) + #define DDRDATA3CH0_CR_RXTRAINRANK1_RxDqsPPi_MAX (0x0000003F) + #define DDRDATA3CH0_CR_RXTRAINRANK1_RxEq_OFF (15) + #define DDRDATA3CH0_CR_RXTRAINRANK1_RxEq_WID ( 5) + #define DDRDATA3CH0_CR_RXTRAINRANK1_RxEq_MSK (0x000F8000) + #define DDRDATA3CH0_CR_RXTRAINRANK1_RxEq_MAX (0x0000001F) + #define DDRDATA3CH0_CR_RXTRAINRANK1_RxDqsNPi_OFF (20) + #define DDRDATA3CH0_CR_RXTRAINRANK1_RxDqsNPi_WID ( 6) + #define DDRDATA3CH0_CR_RXTRAINRANK1_RxDqsNPi_MSK (0x03F00000) + #define DDRDATA3CH0_CR_RXTRAINRANK1_RxDqsNPi_MAX (0x0000003F) + #define DDRDATA3CH0_CR_RXTRAINRANK1_RxVref_OFF (26) + #define DDRDATA3CH0_CR_RXTRAINRANK1_RxVref_WID ( 6) + #define DDRDATA3CH0_CR_RXTRAINRANK1_RxVref_MSK (0xFC000000) + #define DDRDATA3CH0_CR_RXTRAINRANK1_RxVref_MAX (0x0000003F) + +#define DDRDATA3CH0_CR_RXTRAINRANK2_REG (0x00000608) + #define DDRDATA3CH0_CR_RXTRAINRANK2_RxRcvEnPi_OFF ( 0) + #define DDRDATA3CH0_CR_RXTRAINRANK2_RxRcvEnPi_WID ( 9) + #define DDRDATA3CH0_CR_RXTRAINRANK2_RxRcvEnPi_MSK (0x000001FF) + #define DDRDATA3CH0_CR_RXTRAINRANK2_RxRcvEnPi_MAX (0x000001FF) + #define DDRDATA3CH0_CR_RXTRAINRANK2_RxDqsPPi_OFF ( 9) + #define DDRDATA3CH0_CR_RXTRAINRANK2_RxDqsPPi_WID ( 6) + #define DDRDATA3CH0_CR_RXTRAINRANK2_RxDqsPPi_MSK (0x00007E00) + #define DDRDATA3CH0_CR_RXTRAINRANK2_RxDqsPPi_MAX (0x0000003F) + #define DDRDATA3CH0_CR_RXTRAINRANK2_RxEq_OFF (15) + #define DDRDATA3CH0_CR_RXTRAINRANK2_RxEq_WID ( 5) + #define DDRDATA3CH0_CR_RXTRAINRANK2_RxEq_MSK (0x000F8000) + #define DDRDATA3CH0_CR_RXTRAINRANK2_RxEq_MAX (0x0000001F) + #define DDRDATA3CH0_CR_RXTRAINRANK2_RxDqsNPi_OFF (20) + #define DDRDATA3CH0_CR_RXTRAINRANK2_RxDqsNPi_WID ( 6) + #define DDRDATA3CH0_CR_RXTRAINRANK2_RxDqsNPi_MSK (0x03F00000) + #define DDRDATA3CH0_CR_RXTRAINRANK2_RxDqsNPi_MAX (0x0000003F) + #define DDRDATA3CH0_CR_RXTRAINRANK2_RxVref_OFF (26) + #define DDRDATA3CH0_CR_RXTRAINRANK2_RxVref_WID ( 6) + #define DDRDATA3CH0_CR_RXTRAINRANK2_RxVref_MSK (0xFC000000) + #define DDRDATA3CH0_CR_RXTRAINRANK2_RxVref_MAX (0x0000003F) + +#define DDRDATA3CH0_CR_RXTRAINRANK3_REG (0x0000060C) + #define DDRDATA3CH0_CR_RXTRAINRANK3_RxRcvEnPi_OFF ( 0) + #define DDRDATA3CH0_CR_RXTRAINRANK3_RxRcvEnPi_WID ( 9) + #define DDRDATA3CH0_CR_RXTRAINRANK3_RxRcvEnPi_MSK (0x000001FF) + #define DDRDATA3CH0_CR_RXTRAINRANK3_RxRcvEnPi_MAX (0x000001FF) + #define DDRDATA3CH0_CR_RXTRAINRANK3_RxDqsPPi_OFF ( 9) + #define DDRDATA3CH0_CR_RXTRAINRANK3_RxDqsPPi_WID ( 6) + #define DDRDATA3CH0_CR_RXTRAINRANK3_RxDqsPPi_MSK (0x00007E00) + #define DDRDATA3CH0_CR_RXTRAINRANK3_RxDqsPPi_MAX (0x0000003F) + #define DDRDATA3CH0_CR_RXTRAINRANK3_RxEq_OFF (15) + #define DDRDATA3CH0_CR_RXTRAINRANK3_RxEq_WID ( 5) + #define DDRDATA3CH0_CR_RXTRAINRANK3_RxEq_MSK (0x000F8000) + #define DDRDATA3CH0_CR_RXTRAINRANK3_RxEq_MAX (0x0000001F) + #define DDRDATA3CH0_CR_RXTRAINRANK3_RxDqsNPi_OFF (20) + #define DDRDATA3CH0_CR_RXTRAINRANK3_RxDqsNPi_WID ( 6) + #define DDRDATA3CH0_CR_RXTRAINRANK3_RxDqsNPi_MSK (0x03F00000) + #define DDRDATA3CH0_CR_RXTRAINRANK3_RxDqsNPi_MAX (0x0000003F) + #define DDRDATA3CH0_CR_RXTRAINRANK3_RxVref_OFF (26) + #define DDRDATA3CH0_CR_RXTRAINRANK3_RxVref_WID ( 6) + #define DDRDATA3CH0_CR_RXTRAINRANK3_RxVref_MSK (0xFC000000) + #define DDRDATA3CH0_CR_RXTRAINRANK3_RxVref_MAX (0x0000003F) + +#define DDRDATA3CH0_CR_RXPERBITRANK0_REG (0x00000610) + #define DDRDATA3CH0_CR_RXPERBITRANK0_Lane0_OFF ( 0) + #define DDRDATA3CH0_CR_RXPERBITRANK0_Lane0_WID ( 4) + #define DDRDATA3CH0_CR_RXPERBITRANK0_Lane0_MSK (0x0000000F) + #define DDRDATA3CH0_CR_RXPERBITRANK0_Lane0_MAX (0x0000000F) + #define DDRDATA3CH0_CR_RXPERBITRANK0_Lane1_OFF ( 4) + #define DDRDATA3CH0_CR_RXPERBITRANK0_Lane1_WID ( 4) + #define DDRDATA3CH0_CR_RXPERBITRANK0_Lane1_MSK (0x000000F0) + #define DDRDATA3CH0_CR_RXPERBITRANK0_Lane1_MAX (0x0000000F) + #define DDRDATA3CH0_CR_RXPERBITRANK0_Lane2_OFF ( 8) + #define DDRDATA3CH0_CR_RXPERBITRANK0_Lane2_WID ( 4) + #define DDRDATA3CH0_CR_RXPERBITRANK0_Lane2_MSK (0x00000F00) + #define DDRDATA3CH0_CR_RXPERBITRANK0_Lane2_MAX (0x0000000F) + #define DDRDATA3CH0_CR_RXPERBITRANK0_Lane3_OFF (12) + #define DDRDATA3CH0_CR_RXPERBITRANK0_Lane3_WID ( 4) + #define DDRDATA3CH0_CR_RXPERBITRANK0_Lane3_MSK (0x0000F000) + #define DDRDATA3CH0_CR_RXPERBITRANK0_Lane3_MAX (0x0000000F) + #define DDRDATA3CH0_CR_RXPERBITRANK0_Lane4_OFF (16) + #define DDRDATA3CH0_CR_RXPERBITRANK0_Lane4_WID ( 4) + #define DDRDATA3CH0_CR_RXPERBITRANK0_Lane4_MSK (0x000F0000) + #define DDRDATA3CH0_CR_RXPERBITRANK0_Lane4_MAX (0x0000000F) + #define DDRDATA3CH0_CR_RXPERBITRANK0_Lane5_OFF (20) + #define DDRDATA3CH0_CR_RXPERBITRANK0_Lane5_WID ( 4) + #define DDRDATA3CH0_CR_RXPERBITRANK0_Lane5_MSK (0x00F00000) + #define DDRDATA3CH0_CR_RXPERBITRANK0_Lane5_MAX (0x0000000F) + #define DDRDATA3CH0_CR_RXPERBITRANK0_Lane6_OFF (24) + #define DDRDATA3CH0_CR_RXPERBITRANK0_Lane6_WID ( 4) + #define DDRDATA3CH0_CR_RXPERBITRANK0_Lane6_MSK (0x0F000000) + #define DDRDATA3CH0_CR_RXPERBITRANK0_Lane6_MAX (0x0000000F) + #define DDRDATA3CH0_CR_RXPERBITRANK0_Lane7_OFF (28) + #define DDRDATA3CH0_CR_RXPERBITRANK0_Lane7_WID ( 4) + #define DDRDATA3CH0_CR_RXPERBITRANK0_Lane7_MSK (0xF0000000) + #define DDRDATA3CH0_CR_RXPERBITRANK0_Lane7_MAX (0x0000000F) + +#define DDRDATA3CH0_CR_RXPERBITRANK1_REG (0x00000614) + #define DDRDATA3CH0_CR_RXPERBITRANK1_Lane0_OFF ( 0) + #define DDRDATA3CH0_CR_RXPERBITRANK1_Lane0_WID ( 4) + #define DDRDATA3CH0_CR_RXPERBITRANK1_Lane0_MSK (0x0000000F) + #define DDRDATA3CH0_CR_RXPERBITRANK1_Lane0_MAX (0x0000000F) + #define DDRDATA3CH0_CR_RXPERBITRANK1_Lane1_OFF ( 4) + #define DDRDATA3CH0_CR_RXPERBITRANK1_Lane1_WID ( 4) + #define DDRDATA3CH0_CR_RXPERBITRANK1_Lane1_MSK (0x000000F0) + #define DDRDATA3CH0_CR_RXPERBITRANK1_Lane1_MAX (0x0000000F) + #define DDRDATA3CH0_CR_RXPERBITRANK1_Lane2_OFF ( 8) + #define DDRDATA3CH0_CR_RXPERBITRANK1_Lane2_WID ( 4) + #define DDRDATA3CH0_CR_RXPERBITRANK1_Lane2_MSK (0x00000F00) + #define DDRDATA3CH0_CR_RXPERBITRANK1_Lane2_MAX (0x0000000F) + #define DDRDATA3CH0_CR_RXPERBITRANK1_Lane3_OFF (12) + #define DDRDATA3CH0_CR_RXPERBITRANK1_Lane3_WID ( 4) + #define DDRDATA3CH0_CR_RXPERBITRANK1_Lane3_MSK (0x0000F000) + #define DDRDATA3CH0_CR_RXPERBITRANK1_Lane3_MAX (0x0000000F) + #define DDRDATA3CH0_CR_RXPERBITRANK1_Lane4_OFF (16) + #define DDRDATA3CH0_CR_RXPERBITRANK1_Lane4_WID ( 4) + #define DDRDATA3CH0_CR_RXPERBITRANK1_Lane4_MSK (0x000F0000) + #define DDRDATA3CH0_CR_RXPERBITRANK1_Lane4_MAX (0x0000000F) + #define DDRDATA3CH0_CR_RXPERBITRANK1_Lane5_OFF (20) + #define DDRDATA3CH0_CR_RXPERBITRANK1_Lane5_WID ( 4) + #define DDRDATA3CH0_CR_RXPERBITRANK1_Lane5_MSK (0x00F00000) + #define DDRDATA3CH0_CR_RXPERBITRANK1_Lane5_MAX (0x0000000F) + #define DDRDATA3CH0_CR_RXPERBITRANK1_Lane6_OFF (24) + #define DDRDATA3CH0_CR_RXPERBITRANK1_Lane6_WID ( 4) + #define DDRDATA3CH0_CR_RXPERBITRANK1_Lane6_MSK (0x0F000000) + #define DDRDATA3CH0_CR_RXPERBITRANK1_Lane6_MAX (0x0000000F) + #define DDRDATA3CH0_CR_RXPERBITRANK1_Lane7_OFF (28) + #define DDRDATA3CH0_CR_RXPERBITRANK1_Lane7_WID ( 4) + #define DDRDATA3CH0_CR_RXPERBITRANK1_Lane7_MSK (0xF0000000) + #define DDRDATA3CH0_CR_RXPERBITRANK1_Lane7_MAX (0x0000000F) + +#define DDRDATA3CH0_CR_RXPERBITRANK2_REG (0x00000618) + #define DDRDATA3CH0_CR_RXPERBITRANK2_Lane0_OFF ( 0) + #define DDRDATA3CH0_CR_RXPERBITRANK2_Lane0_WID ( 4) + #define DDRDATA3CH0_CR_RXPERBITRANK2_Lane0_MSK (0x0000000F) + #define DDRDATA3CH0_CR_RXPERBITRANK2_Lane0_MAX (0x0000000F) + #define DDRDATA3CH0_CR_RXPERBITRANK2_Lane1_OFF ( 4) + #define DDRDATA3CH0_CR_RXPERBITRANK2_Lane1_WID ( 4) + #define DDRDATA3CH0_CR_RXPERBITRANK2_Lane1_MSK (0x000000F0) + #define DDRDATA3CH0_CR_RXPERBITRANK2_Lane1_MAX (0x0000000F) + #define DDRDATA3CH0_CR_RXPERBITRANK2_Lane2_OFF ( 8) + #define DDRDATA3CH0_CR_RXPERBITRANK2_Lane2_WID ( 4) + #define DDRDATA3CH0_CR_RXPERBITRANK2_Lane2_MSK (0x00000F00) + #define DDRDATA3CH0_CR_RXPERBITRANK2_Lane2_MAX (0x0000000F) + #define DDRDATA3CH0_CR_RXPERBITRANK2_Lane3_OFF (12) + #define DDRDATA3CH0_CR_RXPERBITRANK2_Lane3_WID ( 4) + #define DDRDATA3CH0_CR_RXPERBITRANK2_Lane3_MSK (0x0000F000) + #define DDRDATA3CH0_CR_RXPERBITRANK2_Lane3_MAX (0x0000000F) + #define DDRDATA3CH0_CR_RXPERBITRANK2_Lane4_OFF (16) + #define DDRDATA3CH0_CR_RXPERBITRANK2_Lane4_WID ( 4) + #define DDRDATA3CH0_CR_RXPERBITRANK2_Lane4_MSK (0x000F0000) + #define DDRDATA3CH0_CR_RXPERBITRANK2_Lane4_MAX (0x0000000F) + #define DDRDATA3CH0_CR_RXPERBITRANK2_Lane5_OFF (20) + #define DDRDATA3CH0_CR_RXPERBITRANK2_Lane5_WID ( 4) + #define DDRDATA3CH0_CR_RXPERBITRANK2_Lane5_MSK (0x00F00000) + #define DDRDATA3CH0_CR_RXPERBITRANK2_Lane5_MAX (0x0000000F) + #define DDRDATA3CH0_CR_RXPERBITRANK2_Lane6_OFF (24) + #define DDRDATA3CH0_CR_RXPERBITRANK2_Lane6_WID ( 4) + #define DDRDATA3CH0_CR_RXPERBITRANK2_Lane6_MSK (0x0F000000) + #define DDRDATA3CH0_CR_RXPERBITRANK2_Lane6_MAX (0x0000000F) + #define DDRDATA3CH0_CR_RXPERBITRANK2_Lane7_OFF (28) + #define DDRDATA3CH0_CR_RXPERBITRANK2_Lane7_WID ( 4) + #define DDRDATA3CH0_CR_RXPERBITRANK2_Lane7_MSK (0xF0000000) + #define DDRDATA3CH0_CR_RXPERBITRANK2_Lane7_MAX (0x0000000F) + +#define DDRDATA3CH0_CR_RXPERBITRANK3_REG (0x0000061C) + #define DDRDATA3CH0_CR_RXPERBITRANK3_Lane0_OFF ( 0) + #define DDRDATA3CH0_CR_RXPERBITRANK3_Lane0_WID ( 4) + #define DDRDATA3CH0_CR_RXPERBITRANK3_Lane0_MSK (0x0000000F) + #define DDRDATA3CH0_CR_RXPERBITRANK3_Lane0_MAX (0x0000000F) + #define DDRDATA3CH0_CR_RXPERBITRANK3_Lane1_OFF ( 4) + #define DDRDATA3CH0_CR_RXPERBITRANK3_Lane1_WID ( 4) + #define DDRDATA3CH0_CR_RXPERBITRANK3_Lane1_MSK (0x000000F0) + #define DDRDATA3CH0_CR_RXPERBITRANK3_Lane1_MAX (0x0000000F) + #define DDRDATA3CH0_CR_RXPERBITRANK3_Lane2_OFF ( 8) + #define DDRDATA3CH0_CR_RXPERBITRANK3_Lane2_WID ( 4) + #define DDRDATA3CH0_CR_RXPERBITRANK3_Lane2_MSK (0x00000F00) + #define DDRDATA3CH0_CR_RXPERBITRANK3_Lane2_MAX (0x0000000F) + #define DDRDATA3CH0_CR_RXPERBITRANK3_Lane3_OFF (12) + #define DDRDATA3CH0_CR_RXPERBITRANK3_Lane3_WID ( 4) + #define DDRDATA3CH0_CR_RXPERBITRANK3_Lane3_MSK (0x0000F000) + #define DDRDATA3CH0_CR_RXPERBITRANK3_Lane3_MAX (0x0000000F) + #define DDRDATA3CH0_CR_RXPERBITRANK3_Lane4_OFF (16) + #define DDRDATA3CH0_CR_RXPERBITRANK3_Lane4_WID ( 4) + #define DDRDATA3CH0_CR_RXPERBITRANK3_Lane4_MSK (0x000F0000) + #define DDRDATA3CH0_CR_RXPERBITRANK3_Lane4_MAX (0x0000000F) + #define DDRDATA3CH0_CR_RXPERBITRANK3_Lane5_OFF (20) + #define DDRDATA3CH0_CR_RXPERBITRANK3_Lane5_WID ( 4) + #define DDRDATA3CH0_CR_RXPERBITRANK3_Lane5_MSK (0x00F00000) + #define DDRDATA3CH0_CR_RXPERBITRANK3_Lane5_MAX (0x0000000F) + #define DDRDATA3CH0_CR_RXPERBITRANK3_Lane6_OFF (24) + #define DDRDATA3CH0_CR_RXPERBITRANK3_Lane6_WID ( 4) + #define DDRDATA3CH0_CR_RXPERBITRANK3_Lane6_MSK (0x0F000000) + #define DDRDATA3CH0_CR_RXPERBITRANK3_Lane6_MAX (0x0000000F) + #define DDRDATA3CH0_CR_RXPERBITRANK3_Lane7_OFF (28) + #define DDRDATA3CH0_CR_RXPERBITRANK3_Lane7_WID ( 4) + #define DDRDATA3CH0_CR_RXPERBITRANK3_Lane7_MSK (0xF0000000) + #define DDRDATA3CH0_CR_RXPERBITRANK3_Lane7_MAX (0x0000000F) + +#define DDRDATA3CH0_CR_TXTRAINRANK0_REG (0x00000620) + #define DDRDATA3CH0_CR_TXTRAINRANK0_TxDqDelay_OFF ( 0) + #define DDRDATA3CH0_CR_TXTRAINRANK0_TxDqDelay_WID ( 9) + #define DDRDATA3CH0_CR_TXTRAINRANK0_TxDqDelay_MSK (0x000001FF) + #define DDRDATA3CH0_CR_TXTRAINRANK0_TxDqDelay_MAX (0x000001FF) + #define DDRDATA3CH0_CR_TXTRAINRANK0_TxDqsDelay_OFF ( 9) + #define DDRDATA3CH0_CR_TXTRAINRANK0_TxDqsDelay_WID ( 9) + #define DDRDATA3CH0_CR_TXTRAINRANK0_TxDqsDelay_MSK (0x0003FE00) + #define DDRDATA3CH0_CR_TXTRAINRANK0_TxDqsDelay_MAX (0x000001FF) + #define DDRDATA3CH0_CR_TXTRAINRANK0_Spare0_OFF (18) + #define DDRDATA3CH0_CR_TXTRAINRANK0_Spare0_WID ( 2) + #define DDRDATA3CH0_CR_TXTRAINRANK0_Spare0_MSK (0x000C0000) + #define DDRDATA3CH0_CR_TXTRAINRANK0_Spare0_MAX (0x00000003) + #define DDRDATA3CH0_CR_TXTRAINRANK0_TxEqualization_OFF (20) + #define DDRDATA3CH0_CR_TXTRAINRANK0_TxEqualization_WID ( 6) + #define DDRDATA3CH0_CR_TXTRAINRANK0_TxEqualization_MSK (0x03F00000) + #define DDRDATA3CH0_CR_TXTRAINRANK0_TxEqualization_MAX (0x0000003F) + #define DDRDATA3CH0_CR_TXTRAINRANK0_Spare1_OFF (26) + #define DDRDATA3CH0_CR_TXTRAINRANK0_Spare1_WID ( 6) + #define DDRDATA3CH0_CR_TXTRAINRANK0_Spare1_MSK (0xFC000000) + #define DDRDATA3CH0_CR_TXTRAINRANK0_Spare1_MAX (0x0000003F) + +#define DDRDATA3CH0_CR_TXTRAINRANK1_REG (0x00000624) + #define DDRDATA3CH0_CR_TXTRAINRANK1_TxDqDelay_OFF ( 0) + #define DDRDATA3CH0_CR_TXTRAINRANK1_TxDqDelay_WID ( 9) + #define DDRDATA3CH0_CR_TXTRAINRANK1_TxDqDelay_MSK (0x000001FF) + #define DDRDATA3CH0_CR_TXTRAINRANK1_TxDqDelay_MAX (0x000001FF) + #define DDRDATA3CH0_CR_TXTRAINRANK1_TxDqsDelay_OFF ( 9) + #define DDRDATA3CH0_CR_TXTRAINRANK1_TxDqsDelay_WID ( 9) + #define DDRDATA3CH0_CR_TXTRAINRANK1_TxDqsDelay_MSK (0x0003FE00) + #define DDRDATA3CH0_CR_TXTRAINRANK1_TxDqsDelay_MAX (0x000001FF) + #define DDRDATA3CH0_CR_TXTRAINRANK1_Spare0_OFF (18) + #define DDRDATA3CH0_CR_TXTRAINRANK1_Spare0_WID ( 2) + #define DDRDATA3CH0_CR_TXTRAINRANK1_Spare0_MSK (0x000C0000) + #define DDRDATA3CH0_CR_TXTRAINRANK1_Spare0_MAX (0x00000003) + #define DDRDATA3CH0_CR_TXTRAINRANK1_TxEqualization_OFF (20) + #define DDRDATA3CH0_CR_TXTRAINRANK1_TxEqualization_WID ( 6) + #define DDRDATA3CH0_CR_TXTRAINRANK1_TxEqualization_MSK (0x03F00000) + #define DDRDATA3CH0_CR_TXTRAINRANK1_TxEqualization_MAX (0x0000003F) + #define DDRDATA3CH0_CR_TXTRAINRANK1_Spare1_OFF (26) + #define DDRDATA3CH0_CR_TXTRAINRANK1_Spare1_WID ( 6) + #define DDRDATA3CH0_CR_TXTRAINRANK1_Spare1_MSK (0xFC000000) + #define DDRDATA3CH0_CR_TXTRAINRANK1_Spare1_MAX (0x0000003F) + +#define DDRDATA3CH0_CR_TXTRAINRANK2_REG (0x00000628) + #define DDRDATA3CH0_CR_TXTRAINRANK2_TxDqDelay_OFF ( 0) + #define DDRDATA3CH0_CR_TXTRAINRANK2_TxDqDelay_WID ( 9) + #define DDRDATA3CH0_CR_TXTRAINRANK2_TxDqDelay_MSK (0x000001FF) + #define DDRDATA3CH0_CR_TXTRAINRANK2_TxDqDelay_MAX (0x000001FF) + #define DDRDATA3CH0_CR_TXTRAINRANK2_TxDqsDelay_OFF ( 9) + #define DDRDATA3CH0_CR_TXTRAINRANK2_TxDqsDelay_WID ( 9) + #define DDRDATA3CH0_CR_TXTRAINRANK2_TxDqsDelay_MSK (0x0003FE00) + #define DDRDATA3CH0_CR_TXTRAINRANK2_TxDqsDelay_MAX (0x000001FF) + #define DDRDATA3CH0_CR_TXTRAINRANK2_Spare0_OFF (18) + #define DDRDATA3CH0_CR_TXTRAINRANK2_Spare0_WID ( 2) + #define DDRDATA3CH0_CR_TXTRAINRANK2_Spare0_MSK (0x000C0000) + #define DDRDATA3CH0_CR_TXTRAINRANK2_Spare0_MAX (0x00000003) + #define DDRDATA3CH0_CR_TXTRAINRANK2_TxEqualization_OFF (20) + #define DDRDATA3CH0_CR_TXTRAINRANK2_TxEqualization_WID ( 6) + #define DDRDATA3CH0_CR_TXTRAINRANK2_TxEqualization_MSK (0x03F00000) + #define DDRDATA3CH0_CR_TXTRAINRANK2_TxEqualization_MAX (0x0000003F) + #define DDRDATA3CH0_CR_TXTRAINRANK2_Spare1_OFF (26) + #define DDRDATA3CH0_CR_TXTRAINRANK2_Spare1_WID ( 6) + #define DDRDATA3CH0_CR_TXTRAINRANK2_Spare1_MSK (0xFC000000) + #define DDRDATA3CH0_CR_TXTRAINRANK2_Spare1_MAX (0x0000003F) + +#define DDRDATA3CH0_CR_TXTRAINRANK3_REG (0x0000062C) + #define DDRDATA3CH0_CR_TXTRAINRANK3_TxDqDelay_OFF ( 0) + #define DDRDATA3CH0_CR_TXTRAINRANK3_TxDqDelay_WID ( 9) + #define DDRDATA3CH0_CR_TXTRAINRANK3_TxDqDelay_MSK (0x000001FF) + #define DDRDATA3CH0_CR_TXTRAINRANK3_TxDqDelay_MAX (0x000001FF) + #define DDRDATA3CH0_CR_TXTRAINRANK3_TxDqsDelay_OFF ( 9) + #define DDRDATA3CH0_CR_TXTRAINRANK3_TxDqsDelay_WID ( 9) + #define DDRDATA3CH0_CR_TXTRAINRANK3_TxDqsDelay_MSK (0x0003FE00) + #define DDRDATA3CH0_CR_TXTRAINRANK3_TxDqsDelay_MAX (0x000001FF) + #define DDRDATA3CH0_CR_TXTRAINRANK3_Spare0_OFF (18) + #define DDRDATA3CH0_CR_TXTRAINRANK3_Spare0_WID ( 2) + #define DDRDATA3CH0_CR_TXTRAINRANK3_Spare0_MSK (0x000C0000) + #define DDRDATA3CH0_CR_TXTRAINRANK3_Spare0_MAX (0x00000003) + #define DDRDATA3CH0_CR_TXTRAINRANK3_TxEqualization_OFF (20) + #define DDRDATA3CH0_CR_TXTRAINRANK3_TxEqualization_WID ( 6) + #define DDRDATA3CH0_CR_TXTRAINRANK3_TxEqualization_MSK (0x03F00000) + #define DDRDATA3CH0_CR_TXTRAINRANK3_TxEqualization_MAX (0x0000003F) + #define DDRDATA3CH0_CR_TXTRAINRANK3_Spare1_OFF (26) + #define DDRDATA3CH0_CR_TXTRAINRANK3_Spare1_WID ( 6) + #define DDRDATA3CH0_CR_TXTRAINRANK3_Spare1_MSK (0xFC000000) + #define DDRDATA3CH0_CR_TXTRAINRANK3_Spare1_MAX (0x0000003F) + +#define DDRDATA3CH0_CR_TXPERBITRANK0_REG (0x00000630) + #define DDRDATA3CH0_CR_TXPERBITRANK0_Lane0_OFF ( 0) + #define DDRDATA3CH0_CR_TXPERBITRANK0_Lane0_WID ( 4) + #define DDRDATA3CH0_CR_TXPERBITRANK0_Lane0_MSK (0x0000000F) + #define DDRDATA3CH0_CR_TXPERBITRANK0_Lane0_MAX (0x0000000F) + #define DDRDATA3CH0_CR_TXPERBITRANK0_Lane1_OFF ( 4) + #define DDRDATA3CH0_CR_TXPERBITRANK0_Lane1_WID ( 4) + #define DDRDATA3CH0_CR_TXPERBITRANK0_Lane1_MSK (0x000000F0) + #define DDRDATA3CH0_CR_TXPERBITRANK0_Lane1_MAX (0x0000000F) + #define DDRDATA3CH0_CR_TXPERBITRANK0_Lane2_OFF ( 8) + #define DDRDATA3CH0_CR_TXPERBITRANK0_Lane2_WID ( 4) + #define DDRDATA3CH0_CR_TXPERBITRANK0_Lane2_MSK (0x00000F00) + #define DDRDATA3CH0_CR_TXPERBITRANK0_Lane2_MAX (0x0000000F) + #define DDRDATA3CH0_CR_TXPERBITRANK0_Lane3_OFF (12) + #define DDRDATA3CH0_CR_TXPERBITRANK0_Lane3_WID ( 4) + #define DDRDATA3CH0_CR_TXPERBITRANK0_Lane3_MSK (0x0000F000) + #define DDRDATA3CH0_CR_TXPERBITRANK0_Lane3_MAX (0x0000000F) + #define DDRDATA3CH0_CR_TXPERBITRANK0_Lane4_OFF (16) + #define DDRDATA3CH0_CR_TXPERBITRANK0_Lane4_WID ( 4) + #define DDRDATA3CH0_CR_TXPERBITRANK0_Lane4_MSK (0x000F0000) + #define DDRDATA3CH0_CR_TXPERBITRANK0_Lane4_MAX (0x0000000F) + #define DDRDATA3CH0_CR_TXPERBITRANK0_Lane5_OFF (20) + #define DDRDATA3CH0_CR_TXPERBITRANK0_Lane5_WID ( 4) + #define DDRDATA3CH0_CR_TXPERBITRANK0_Lane5_MSK (0x00F00000) + #define DDRDATA3CH0_CR_TXPERBITRANK0_Lane5_MAX (0x0000000F) + #define DDRDATA3CH0_CR_TXPERBITRANK0_Lane6_OFF (24) + #define DDRDATA3CH0_CR_TXPERBITRANK0_Lane6_WID ( 4) + #define DDRDATA3CH0_CR_TXPERBITRANK0_Lane6_MSK (0x0F000000) + #define DDRDATA3CH0_CR_TXPERBITRANK0_Lane6_MAX (0x0000000F) + #define DDRDATA3CH0_CR_TXPERBITRANK0_Lane7_OFF (28) + #define DDRDATA3CH0_CR_TXPERBITRANK0_Lane7_WID ( 4) + #define DDRDATA3CH0_CR_TXPERBITRANK0_Lane7_MSK (0xF0000000) + #define DDRDATA3CH0_CR_TXPERBITRANK0_Lane7_MAX (0x0000000F) + +#define DDRDATA3CH0_CR_TXPERBITRANK1_REG (0x00000634) + #define DDRDATA3CH0_CR_TXPERBITRANK1_Lane0_OFF ( 0) + #define DDRDATA3CH0_CR_TXPERBITRANK1_Lane0_WID ( 4) + #define DDRDATA3CH0_CR_TXPERBITRANK1_Lane0_MSK (0x0000000F) + #define DDRDATA3CH0_CR_TXPERBITRANK1_Lane0_MAX (0x0000000F) + #define DDRDATA3CH0_CR_TXPERBITRANK1_Lane1_OFF ( 4) + #define DDRDATA3CH0_CR_TXPERBITRANK1_Lane1_WID ( 4) + #define DDRDATA3CH0_CR_TXPERBITRANK1_Lane1_MSK (0x000000F0) + #define DDRDATA3CH0_CR_TXPERBITRANK1_Lane1_MAX (0x0000000F) + #define DDRDATA3CH0_CR_TXPERBITRANK1_Lane2_OFF ( 8) + #define DDRDATA3CH0_CR_TXPERBITRANK1_Lane2_WID ( 4) + #define DDRDATA3CH0_CR_TXPERBITRANK1_Lane2_MSK (0x00000F00) + #define DDRDATA3CH0_CR_TXPERBITRANK1_Lane2_MAX (0x0000000F) + #define DDRDATA3CH0_CR_TXPERBITRANK1_Lane3_OFF (12) + #define DDRDATA3CH0_CR_TXPERBITRANK1_Lane3_WID ( 4) + #define DDRDATA3CH0_CR_TXPERBITRANK1_Lane3_MSK (0x0000F000) + #define DDRDATA3CH0_CR_TXPERBITRANK1_Lane3_MAX (0x0000000F) + #define DDRDATA3CH0_CR_TXPERBITRANK1_Lane4_OFF (16) + #define DDRDATA3CH0_CR_TXPERBITRANK1_Lane4_WID ( 4) + #define DDRDATA3CH0_CR_TXPERBITRANK1_Lane4_MSK (0x000F0000) + #define DDRDATA3CH0_CR_TXPERBITRANK1_Lane4_MAX (0x0000000F) + #define DDRDATA3CH0_CR_TXPERBITRANK1_Lane5_OFF (20) + #define DDRDATA3CH0_CR_TXPERBITRANK1_Lane5_WID ( 4) + #define DDRDATA3CH0_CR_TXPERBITRANK1_Lane5_MSK (0x00F00000) + #define DDRDATA3CH0_CR_TXPERBITRANK1_Lane5_MAX (0x0000000F) + #define DDRDATA3CH0_CR_TXPERBITRANK1_Lane6_OFF (24) + #define DDRDATA3CH0_CR_TXPERBITRANK1_Lane6_WID ( 4) + #define DDRDATA3CH0_CR_TXPERBITRANK1_Lane6_MSK (0x0F000000) + #define DDRDATA3CH0_CR_TXPERBITRANK1_Lane6_MAX (0x0000000F) + #define DDRDATA3CH0_CR_TXPERBITRANK1_Lane7_OFF (28) + #define DDRDATA3CH0_CR_TXPERBITRANK1_Lane7_WID ( 4) + #define DDRDATA3CH0_CR_TXPERBITRANK1_Lane7_MSK (0xF0000000) + #define DDRDATA3CH0_CR_TXPERBITRANK1_Lane7_MAX (0x0000000F) + +#define DDRDATA3CH0_CR_TXPERBITRANK2_REG (0x00000638) + #define DDRDATA3CH0_CR_TXPERBITRANK2_Lane0_OFF ( 0) + #define DDRDATA3CH0_CR_TXPERBITRANK2_Lane0_WID ( 4) + #define DDRDATA3CH0_CR_TXPERBITRANK2_Lane0_MSK (0x0000000F) + #define DDRDATA3CH0_CR_TXPERBITRANK2_Lane0_MAX (0x0000000F) + #define DDRDATA3CH0_CR_TXPERBITRANK2_Lane1_OFF ( 4) + #define DDRDATA3CH0_CR_TXPERBITRANK2_Lane1_WID ( 4) + #define DDRDATA3CH0_CR_TXPERBITRANK2_Lane1_MSK (0x000000F0) + #define DDRDATA3CH0_CR_TXPERBITRANK2_Lane1_MAX (0x0000000F) + #define DDRDATA3CH0_CR_TXPERBITRANK2_Lane2_OFF ( 8) + #define DDRDATA3CH0_CR_TXPERBITRANK2_Lane2_WID ( 4) + #define DDRDATA3CH0_CR_TXPERBITRANK2_Lane2_MSK (0x00000F00) + #define DDRDATA3CH0_CR_TXPERBITRANK2_Lane2_MAX (0x0000000F) + #define DDRDATA3CH0_CR_TXPERBITRANK2_Lane3_OFF (12) + #define DDRDATA3CH0_CR_TXPERBITRANK2_Lane3_WID ( 4) + #define DDRDATA3CH0_CR_TXPERBITRANK2_Lane3_MSK (0x0000F000) + #define DDRDATA3CH0_CR_TXPERBITRANK2_Lane3_MAX (0x0000000F) + #define DDRDATA3CH0_CR_TXPERBITRANK2_Lane4_OFF (16) + #define DDRDATA3CH0_CR_TXPERBITRANK2_Lane4_WID ( 4) + #define DDRDATA3CH0_CR_TXPERBITRANK2_Lane4_MSK (0x000F0000) + #define DDRDATA3CH0_CR_TXPERBITRANK2_Lane4_MAX (0x0000000F) + #define DDRDATA3CH0_CR_TXPERBITRANK2_Lane5_OFF (20) + #define DDRDATA3CH0_CR_TXPERBITRANK2_Lane5_WID ( 4) + #define DDRDATA3CH0_CR_TXPERBITRANK2_Lane5_MSK (0x00F00000) + #define DDRDATA3CH0_CR_TXPERBITRANK2_Lane5_MAX (0x0000000F) + #define DDRDATA3CH0_CR_TXPERBITRANK2_Lane6_OFF (24) + #define DDRDATA3CH0_CR_TXPERBITRANK2_Lane6_WID ( 4) + #define DDRDATA3CH0_CR_TXPERBITRANK2_Lane6_MSK (0x0F000000) + #define DDRDATA3CH0_CR_TXPERBITRANK2_Lane6_MAX (0x0000000F) + #define DDRDATA3CH0_CR_TXPERBITRANK2_Lane7_OFF (28) + #define DDRDATA3CH0_CR_TXPERBITRANK2_Lane7_WID ( 4) + #define DDRDATA3CH0_CR_TXPERBITRANK2_Lane7_MSK (0xF0000000) + #define DDRDATA3CH0_CR_TXPERBITRANK2_Lane7_MAX (0x0000000F) + +#define DDRDATA3CH0_CR_TXPERBITRANK3_REG (0x0000063C) + #define DDRDATA3CH0_CR_TXPERBITRANK3_Lane0_OFF ( 0) + #define DDRDATA3CH0_CR_TXPERBITRANK3_Lane0_WID ( 4) + #define DDRDATA3CH0_CR_TXPERBITRANK3_Lane0_MSK (0x0000000F) + #define DDRDATA3CH0_CR_TXPERBITRANK3_Lane0_MAX (0x0000000F) + #define DDRDATA3CH0_CR_TXPERBITRANK3_Lane1_OFF ( 4) + #define DDRDATA3CH0_CR_TXPERBITRANK3_Lane1_WID ( 4) + #define DDRDATA3CH0_CR_TXPERBITRANK3_Lane1_MSK (0x000000F0) + #define DDRDATA3CH0_CR_TXPERBITRANK3_Lane1_MAX (0x0000000F) + #define DDRDATA3CH0_CR_TXPERBITRANK3_Lane2_OFF ( 8) + #define DDRDATA3CH0_CR_TXPERBITRANK3_Lane2_WID ( 4) + #define DDRDATA3CH0_CR_TXPERBITRANK3_Lane2_MSK (0x00000F00) + #define DDRDATA3CH0_CR_TXPERBITRANK3_Lane2_MAX (0x0000000F) + #define DDRDATA3CH0_CR_TXPERBITRANK3_Lane3_OFF (12) + #define DDRDATA3CH0_CR_TXPERBITRANK3_Lane3_WID ( 4) + #define DDRDATA3CH0_CR_TXPERBITRANK3_Lane3_MSK (0x0000F000) + #define DDRDATA3CH0_CR_TXPERBITRANK3_Lane3_MAX (0x0000000F) + #define DDRDATA3CH0_CR_TXPERBITRANK3_Lane4_OFF (16) + #define DDRDATA3CH0_CR_TXPERBITRANK3_Lane4_WID ( 4) + #define DDRDATA3CH0_CR_TXPERBITRANK3_Lane4_MSK (0x000F0000) + #define DDRDATA3CH0_CR_TXPERBITRANK3_Lane4_MAX (0x0000000F) + #define DDRDATA3CH0_CR_TXPERBITRANK3_Lane5_OFF (20) + #define DDRDATA3CH0_CR_TXPERBITRANK3_Lane5_WID ( 4) + #define DDRDATA3CH0_CR_TXPERBITRANK3_Lane5_MSK (0x00F00000) + #define DDRDATA3CH0_CR_TXPERBITRANK3_Lane5_MAX (0x0000000F) + #define DDRDATA3CH0_CR_TXPERBITRANK3_Lane6_OFF (24) + #define DDRDATA3CH0_CR_TXPERBITRANK3_Lane6_WID ( 4) + #define DDRDATA3CH0_CR_TXPERBITRANK3_Lane6_MSK (0x0F000000) + #define DDRDATA3CH0_CR_TXPERBITRANK3_Lane6_MAX (0x0000000F) + #define DDRDATA3CH0_CR_TXPERBITRANK3_Lane7_OFF (28) + #define DDRDATA3CH0_CR_TXPERBITRANK3_Lane7_WID ( 4) + #define DDRDATA3CH0_CR_TXPERBITRANK3_Lane7_MSK (0xF0000000) + #define DDRDATA3CH0_CR_TXPERBITRANK3_Lane7_MAX (0x0000000F) + +#define DDRDATA3CH0_CR_RCOMPDATA0_REG (0x00000640) + #define DDRDATA3CH0_CR_RCOMPDATA0_RcompDrvUp_OFF ( 0) + #define DDRDATA3CH0_CR_RCOMPDATA0_RcompDrvUp_WID ( 6) + #define DDRDATA3CH0_CR_RCOMPDATA0_RcompDrvUp_MSK (0x0000003F) + #define DDRDATA3CH0_CR_RCOMPDATA0_RcompDrvUp_MAX (0x0000003F) + #define DDRDATA3CH0_CR_RCOMPDATA0_Spare0_OFF ( 6) + #define DDRDATA3CH0_CR_RCOMPDATA0_Spare0_WID ( 3) + #define DDRDATA3CH0_CR_RCOMPDATA0_Spare0_MSK (0x000001C0) + #define DDRDATA3CH0_CR_RCOMPDATA0_Spare0_MAX (0x00000007) + #define DDRDATA3CH0_CR_RCOMPDATA0_RcompDrvDown_OFF ( 9) + #define DDRDATA3CH0_CR_RCOMPDATA0_RcompDrvDown_WID ( 6) + #define DDRDATA3CH0_CR_RCOMPDATA0_RcompDrvDown_MSK (0x00007E00) + #define DDRDATA3CH0_CR_RCOMPDATA0_RcompDrvDown_MAX (0x0000003F) + #define DDRDATA3CH0_CR_RCOMPDATA0_VTComp_OFF (15) + #define DDRDATA3CH0_CR_RCOMPDATA0_VTComp_WID ( 5) + #define DDRDATA3CH0_CR_RCOMPDATA0_VTComp_MSK (0x000F8000) + #define DDRDATA3CH0_CR_RCOMPDATA0_VTComp_MAX (0x0000001F) + #define DDRDATA3CH0_CR_RCOMPDATA0_TcoComp_OFF (20) + #define DDRDATA3CH0_CR_RCOMPDATA0_TcoComp_WID ( 6) + #define DDRDATA3CH0_CR_RCOMPDATA0_TcoComp_MSK (0x03F00000) + #define DDRDATA3CH0_CR_RCOMPDATA0_TcoComp_MAX (0x0000003F) + #define DDRDATA3CH0_CR_RCOMPDATA0_SlewRateComp_OFF (26) + #define DDRDATA3CH0_CR_RCOMPDATA0_SlewRateComp_WID ( 5) + #define DDRDATA3CH0_CR_RCOMPDATA0_SlewRateComp_MSK (0x7C000000) + #define DDRDATA3CH0_CR_RCOMPDATA0_SlewRateComp_MAX (0x0000001F) + #define DDRDATA3CH0_CR_RCOMPDATA0_Spare2_OFF (31) + #define DDRDATA3CH0_CR_RCOMPDATA0_Spare2_WID ( 1) + #define DDRDATA3CH0_CR_RCOMPDATA0_Spare2_MSK (0x80000000) + #define DDRDATA3CH0_CR_RCOMPDATA0_Spare2_MAX (0x00000001) + +#define DDRDATA3CH0_CR_RCOMPDATA1_REG (0x00000644) + #define DDRDATA3CH0_CR_RCOMPDATA1_RcompOdtUp_OFF ( 0) + #define DDRDATA3CH0_CR_RCOMPDATA1_RcompOdtUp_WID ( 6) + #define DDRDATA3CH0_CR_RCOMPDATA1_RcompOdtUp_MSK (0x0000003F) + #define DDRDATA3CH0_CR_RCOMPDATA1_RcompOdtUp_MAX (0x0000003F) + #define DDRDATA3CH0_CR_RCOMPDATA1_Spare0_OFF ( 6) + #define DDRDATA3CH0_CR_RCOMPDATA1_Spare0_WID ( 3) + #define DDRDATA3CH0_CR_RCOMPDATA1_Spare0_MSK (0x000001C0) + #define DDRDATA3CH0_CR_RCOMPDATA1_Spare0_MAX (0x00000007) + #define DDRDATA3CH0_CR_RCOMPDATA1_RcompOdtDown_OFF ( 9) + #define DDRDATA3CH0_CR_RCOMPDATA1_RcompOdtDown_WID ( 6) + #define DDRDATA3CH0_CR_RCOMPDATA1_RcompOdtDown_MSK (0x00007E00) + #define DDRDATA3CH0_CR_RCOMPDATA1_RcompOdtDown_MAX (0x0000003F) + #define DDRDATA3CH0_CR_RCOMPDATA1_Spare1_OFF (15) + #define DDRDATA3CH0_CR_RCOMPDATA1_Spare1_WID ( 1) + #define DDRDATA3CH0_CR_RCOMPDATA1_Spare1_MSK (0x00008000) + #define DDRDATA3CH0_CR_RCOMPDATA1_Spare1_MAX (0x00000001) + #define DDRDATA3CH0_CR_RCOMPDATA1_PanicDrvDn_OFF (16) + #define DDRDATA3CH0_CR_RCOMPDATA1_PanicDrvDn_WID ( 6) + #define DDRDATA3CH0_CR_RCOMPDATA1_PanicDrvDn_MSK (0x003F0000) + #define DDRDATA3CH0_CR_RCOMPDATA1_PanicDrvDn_MAX (0x0000003F) + #define DDRDATA3CH0_CR_RCOMPDATA1_PanicDrvUp_OFF (22) + #define DDRDATA3CH0_CR_RCOMPDATA1_PanicDrvUp_WID ( 6) + #define DDRDATA3CH0_CR_RCOMPDATA1_PanicDrvUp_MSK (0x0FC00000) + #define DDRDATA3CH0_CR_RCOMPDATA1_PanicDrvUp_MAX (0x0000003F) + #define DDRDATA3CH0_CR_RCOMPDATA1_LevelShifterComp_OFF (28) + #define DDRDATA3CH0_CR_RCOMPDATA1_LevelShifterComp_WID ( 3) + #define DDRDATA3CH0_CR_RCOMPDATA1_LevelShifterComp_MSK (0x70000000) + #define DDRDATA3CH0_CR_RCOMPDATA1_LevelShifterComp_MAX (0x00000007) + #define DDRDATA3CH0_CR_RCOMPDATA1_Spare2_OFF (31) + #define DDRDATA3CH0_CR_RCOMPDATA1_Spare2_WID ( 1) + #define DDRDATA3CH0_CR_RCOMPDATA1_Spare2_MSK (0x80000000) + #define DDRDATA3CH0_CR_RCOMPDATA1_Spare2_MAX (0x00000001) + +#define DDRDATA3CH0_CR_TXXTALK_REG (0x00000648) + #define DDRDATA3CH0_CR_TXXTALK_Lane0_OFF ( 0) + #define DDRDATA3CH0_CR_TXXTALK_Lane0_WID ( 4) + #define DDRDATA3CH0_CR_TXXTALK_Lane0_MSK (0x0000000F) + #define DDRDATA3CH0_CR_TXXTALK_Lane0_MAX (0x0000000F) + #define DDRDATA3CH0_CR_TXXTALK_Lane1_OFF ( 4) + #define DDRDATA3CH0_CR_TXXTALK_Lane1_WID ( 4) + #define DDRDATA3CH0_CR_TXXTALK_Lane1_MSK (0x000000F0) + #define DDRDATA3CH0_CR_TXXTALK_Lane1_MAX (0x0000000F) + #define DDRDATA3CH0_CR_TXXTALK_Lane2_OFF ( 8) + #define DDRDATA3CH0_CR_TXXTALK_Lane2_WID ( 4) + #define DDRDATA3CH0_CR_TXXTALK_Lane2_MSK (0x00000F00) + #define DDRDATA3CH0_CR_TXXTALK_Lane2_MAX (0x0000000F) + #define DDRDATA3CH0_CR_TXXTALK_Lane3_OFF (12) + #define DDRDATA3CH0_CR_TXXTALK_Lane3_WID ( 4) + #define DDRDATA3CH0_CR_TXXTALK_Lane3_MSK (0x0000F000) + #define DDRDATA3CH0_CR_TXXTALK_Lane3_MAX (0x0000000F) + #define DDRDATA3CH0_CR_TXXTALK_Lane4_OFF (16) + #define DDRDATA3CH0_CR_TXXTALK_Lane4_WID ( 4) + #define DDRDATA3CH0_CR_TXXTALK_Lane4_MSK (0x000F0000) + #define DDRDATA3CH0_CR_TXXTALK_Lane4_MAX (0x0000000F) + #define DDRDATA3CH0_CR_TXXTALK_Lane5_OFF (20) + #define DDRDATA3CH0_CR_TXXTALK_Lane5_WID ( 4) + #define DDRDATA3CH0_CR_TXXTALK_Lane5_MSK (0x00F00000) + #define DDRDATA3CH0_CR_TXXTALK_Lane5_MAX (0x0000000F) + #define DDRDATA3CH0_CR_TXXTALK_Lane6_OFF (24) + #define DDRDATA3CH0_CR_TXXTALK_Lane6_WID ( 4) + #define DDRDATA3CH0_CR_TXXTALK_Lane6_MSK (0x0F000000) + #define DDRDATA3CH0_CR_TXXTALK_Lane6_MAX (0x0000000F) + #define DDRDATA3CH0_CR_TXXTALK_Lane7_OFF (28) + #define DDRDATA3CH0_CR_TXXTALK_Lane7_WID ( 4) + #define DDRDATA3CH0_CR_TXXTALK_Lane7_MSK (0xF0000000) + #define DDRDATA3CH0_CR_TXXTALK_Lane7_MAX (0x0000000F) + +#define DDRDATA3CH0_CR_RXOFFSETVDQ_REG (0x0000064C) + #define DDRDATA3CH0_CR_RXOFFSETVDQ_Lane0_OFF ( 0) + #define DDRDATA3CH0_CR_RXOFFSETVDQ_Lane0_WID ( 4) + #define DDRDATA3CH0_CR_RXOFFSETVDQ_Lane0_MSK (0x0000000F) + #define DDRDATA3CH0_CR_RXOFFSETVDQ_Lane0_MAX (0x0000000F) + #define DDRDATA3CH0_CR_RXOFFSETVDQ_Lane1_OFF ( 4) + #define DDRDATA3CH0_CR_RXOFFSETVDQ_Lane1_WID ( 4) + #define DDRDATA3CH0_CR_RXOFFSETVDQ_Lane1_MSK (0x000000F0) + #define DDRDATA3CH0_CR_RXOFFSETVDQ_Lane1_MAX (0x0000000F) + #define DDRDATA3CH0_CR_RXOFFSETVDQ_Lane2_OFF ( 8) + #define DDRDATA3CH0_CR_RXOFFSETVDQ_Lane2_WID ( 4) + #define DDRDATA3CH0_CR_RXOFFSETVDQ_Lane2_MSK (0x00000F00) + #define DDRDATA3CH0_CR_RXOFFSETVDQ_Lane2_MAX (0x0000000F) + #define DDRDATA3CH0_CR_RXOFFSETVDQ_Lane3_OFF (12) + #define DDRDATA3CH0_CR_RXOFFSETVDQ_Lane3_WID ( 4) + #define DDRDATA3CH0_CR_RXOFFSETVDQ_Lane3_MSK (0x0000F000) + #define DDRDATA3CH0_CR_RXOFFSETVDQ_Lane3_MAX (0x0000000F) + #define DDRDATA3CH0_CR_RXOFFSETVDQ_Lane4_OFF (16) + #define DDRDATA3CH0_CR_RXOFFSETVDQ_Lane4_WID ( 4) + #define DDRDATA3CH0_CR_RXOFFSETVDQ_Lane4_MSK (0x000F0000) + #define DDRDATA3CH0_CR_RXOFFSETVDQ_Lane4_MAX (0x0000000F) + #define DDRDATA3CH0_CR_RXOFFSETVDQ_Lane5_OFF (20) + #define DDRDATA3CH0_CR_RXOFFSETVDQ_Lane5_WID ( 4) + #define DDRDATA3CH0_CR_RXOFFSETVDQ_Lane5_MSK (0x00F00000) + #define DDRDATA3CH0_CR_RXOFFSETVDQ_Lane5_MAX (0x0000000F) + #define DDRDATA3CH0_CR_RXOFFSETVDQ_Lane6_OFF (24) + #define DDRDATA3CH0_CR_RXOFFSETVDQ_Lane6_WID ( 4) + #define DDRDATA3CH0_CR_RXOFFSETVDQ_Lane6_MSK (0x0F000000) + #define DDRDATA3CH0_CR_RXOFFSETVDQ_Lane6_MAX (0x0000000F) + #define DDRDATA3CH0_CR_RXOFFSETVDQ_Lane7_OFF (28) + #define DDRDATA3CH0_CR_RXOFFSETVDQ_Lane7_WID ( 4) + #define DDRDATA3CH0_CR_RXOFFSETVDQ_Lane7_MSK (0xF0000000) + #define DDRDATA3CH0_CR_RXOFFSETVDQ_Lane7_MAX (0x0000000F) + +#define DDRDATA3CH0_CR_DDRDATARESERVED_REG (0x00000650) + #define DDRDATA3CH0_CR_DDRDATARESERVED_Spare_OFF ( 0) + #define DDRDATA3CH0_CR_DDRDATARESERVED_Spare_WID (32) + #define DDRDATA3CH0_CR_DDRDATARESERVED_Spare_MSK (0xFFFFFFFF) + #define DDRDATA3CH0_CR_DDRDATARESERVED_Spare_MAX (0xFFFFFFFF) + +#define DDRDATA3CH0_CR_DATATRAINFEEDBACK_REG (0x00000654) + #define DDRDATA3CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_OFF ( 0) + #define DDRDATA3CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_WID ( 9) + #define DDRDATA3CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_MSK (0x000001FF) + #define DDRDATA3CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_MAX (0x000001FF) + #define DDRDATA3CH0_CR_DATATRAINFEEDBACK_Spare_OFF ( 9) + #define DDRDATA3CH0_CR_DATATRAINFEEDBACK_Spare_WID (23) + #define DDRDATA3CH0_CR_DATATRAINFEEDBACK_Spare_MSK (0xFFFFFE00) + #define DDRDATA3CH0_CR_DATATRAINFEEDBACK_Spare_MAX (0x007FFFFF) + +#define DDRDATA3CH0_CR_DLLPITESTANDADC_REG (0x00000658) + #define DDRDATA3CH0_CR_DLLPITESTANDADC_RunTest_OFF ( 0) + #define DDRDATA3CH0_CR_DLLPITESTANDADC_RunTest_WID ( 1) + #define DDRDATA3CH0_CR_DLLPITESTANDADC_RunTest_MSK (0x00000001) + #define DDRDATA3CH0_CR_DLLPITESTANDADC_RunTest_MAX (0x00000001) + #define DDRDATA3CH0_CR_DLLPITESTANDADC_RunTest_DEF (0x00000000) + #define DDRDATA3CH0_CR_DLLPITESTANDADC_Load_OFF ( 1) + #define DDRDATA3CH0_CR_DLLPITESTANDADC_Load_WID ( 1) + #define DDRDATA3CH0_CR_DLLPITESTANDADC_Load_MSK (0x00000002) + #define DDRDATA3CH0_CR_DLLPITESTANDADC_Load_MAX (0x00000001) + #define DDRDATA3CH0_CR_DLLPITESTANDADC_Load_DEF (0x00000000) + #define DDRDATA3CH0_CR_DLLPITESTANDADC_ModeHVM_OFF ( 2) + #define DDRDATA3CH0_CR_DLLPITESTANDADC_ModeHVM_WID ( 1) + #define DDRDATA3CH0_CR_DLLPITESTANDADC_ModeHVM_MSK (0x00000004) + #define DDRDATA3CH0_CR_DLLPITESTANDADC_ModeHVM_MAX (0x00000001) + #define DDRDATA3CH0_CR_DLLPITESTANDADC_ModeHVM_DEF (0x00000000) + #define DDRDATA3CH0_CR_DLLPITESTANDADC_ModeDV_OFF ( 3) + #define DDRDATA3CH0_CR_DLLPITESTANDADC_ModeDV_WID ( 1) + #define DDRDATA3CH0_CR_DLLPITESTANDADC_ModeDV_MSK (0x00000008) + #define DDRDATA3CH0_CR_DLLPITESTANDADC_ModeDV_MAX (0x00000001) + #define DDRDATA3CH0_CR_DLLPITESTANDADC_ModeDV_DEF (0x00000000) + #define DDRDATA3CH0_CR_DLLPITESTANDADC_ModeADC_OFF ( 4) + #define DDRDATA3CH0_CR_DLLPITESTANDADC_ModeADC_WID ( 1) + #define DDRDATA3CH0_CR_DLLPITESTANDADC_ModeADC_MSK (0x00000010) + #define DDRDATA3CH0_CR_DLLPITESTANDADC_ModeADC_MAX (0x00000001) + #define DDRDATA3CH0_CR_DLLPITESTANDADC_ModeADC_DEF (0x00000000) + #define DDRDATA3CH0_CR_DLLPITESTANDADC_LoadCount_OFF ( 5) + #define DDRDATA3CH0_CR_DLLPITESTANDADC_LoadCount_WID (10) + #define DDRDATA3CH0_CR_DLLPITESTANDADC_LoadCount_MSK (0x00007FE0) + #define DDRDATA3CH0_CR_DLLPITESTANDADC_LoadCount_MAX (0x000003FF) + #define DDRDATA3CH0_CR_DLLPITESTANDADC_CountStatus_OFF (15) + #define DDRDATA3CH0_CR_DLLPITESTANDADC_CountStatus_WID (10) + #define DDRDATA3CH0_CR_DLLPITESTANDADC_CountStatus_MSK (0x01FF8000) + #define DDRDATA3CH0_CR_DLLPITESTANDADC_CountStatus_MAX (0x000003FF) + #define DDRDATA3CH0_CR_DLLPITESTANDADC_CountStatus_DEF (0x00000000) + #define DDRDATA3CH0_CR_DLLPITESTANDADC_Spare_OFF (25) + #define DDRDATA3CH0_CR_DLLPITESTANDADC_Spare_WID ( 7) + #define DDRDATA3CH0_CR_DLLPITESTANDADC_Spare_MSK (0xFE000000) + #define DDRDATA3CH0_CR_DLLPITESTANDADC_Spare_MAX (0x0000007F) + +#define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_REG (0x0000065C) + #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_OFF ( 0) + #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_WID ( 6) + #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MSK (0x0000003F) + #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MAX (0x0000003F) + #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_DEF (0x00000000) + #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_OFF ( 6) + #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_WID ( 6) + #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MSK (0x00000FC0) + #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MAX (0x0000003F) + #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_DEF (0x00000000) + #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_OFF (12) + #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_WID ( 5) + #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MSK (0x0001F000) + #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MAX (0x0000001F) + #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_DEF (0x00000000) + #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_OFF (17) + #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_WID ( 5) + #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MSK (0x003E0000) + #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MAX (0x0000001F) + #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_DEF (0x00000000) + #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_OFF (22) + #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_WID ( 5) + #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_MSK (0x07C00000) + #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_MAX (0x0000001F) + #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_DEF (0x00000000) + #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_OFF (27) + #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_WID ( 5) + #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MSK (0xF8000000) + #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MAX (0x0000001F) + #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_DEF (0x00000000) + +#define DDRDATA3CH0_CR_DDRCRDATACONTROL1_REG (0x00000660) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_RefPi_OFF ( 0) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_RefPi_WID ( 4) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_RefPi_MSK (0x0000000F) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_RefPi_MAX (0x0000000F) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_RefPi_DEF (0x00000000) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_DllMask_OFF ( 4) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_DllMask_WID ( 2) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_DllMask_MSK (0x00000030) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_DllMask_MAX (0x00000003) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_DllMask_DEF (0x00000000) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_DllWeakLock_OFF ( 6) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_DllWeakLock_WID ( 1) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_DllWeakLock_MSK (0x00000040) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_DllWeakLock_MAX (0x00000001) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_DllWeakLock_DEF (0x00000000) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_OFF ( 7) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_WID ( 3) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MSK (0x00000380) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MAX (0x00000007) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_DEF (0x00000000) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_OFF (10) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_WID ( 3) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_MSK (0x00001C00) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_MAX (0x00000007) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_DEF (0x00000000) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_OdtDelay_OFF (13) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_OdtDelay_WID ( 4) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_OdtDelay_MSK (0x0001E000) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_OdtDelay_MAX (0x0000000F) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_OdtDelay_DEF (0x00000000) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_OdtDuration_OFF (17) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_OdtDuration_WID ( 3) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_OdtDuration_MSK (0x000E0000) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_OdtDuration_MAX (0x00000007) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_OdtDuration_DEF (0x00000000) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_OFF (20) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_WID ( 4) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_MSK (0x00F00000) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_MAX (0x0000000F) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_DEF (0x00000000) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_OFF (24) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_WID ( 3) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_MSK (0x07000000) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_MAX (0x00000007) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_DEF (0x00000000) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_OFF (27) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_WID ( 3) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_MSK (0x38000000) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_MAX (0x00000007) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_DEF (0x00000000) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_OFF (30) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_WID ( 1) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_MSK (0x40000000) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_MAX (0x00000001) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_DEF (0x00000000) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_Rsvd1_OFF (31) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_Rsvd1_WID ( 1) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_Rsvd1_MSK (0x80000000) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_Rsvd1_MAX (0x00000001) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_Rsvd1_DEF (0x00000000) + +#define DDRDATA3CH0_CR_DDRCRDATACONTROL2_REG (0x00000664) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_OFF ( 0) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_WID ( 5) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_MSK (0x0000001F) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_MAX (0x0000001F) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_DEF (0x00000000) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_OFF ( 5) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_WID ( 1) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_MSK (0x00000020) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_MAX (0x00000001) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_DEF (0x00000000) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_ForceRxOn_OFF ( 6) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_ForceRxOn_WID ( 1) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_ForceRxOn_MSK (0x00000040) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_ForceRxOn_MAX (0x00000001) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_ForceRxOn_DEF (0x00000000) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_LeakerComp_OFF ( 7) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_LeakerComp_WID ( 2) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_LeakerComp_MSK (0x00000180) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_LeakerComp_MAX (0x00000003) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_LeakerComp_DEF (0x00000000) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_OFF ( 9) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_WID ( 4) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_MSK (0x00001E00) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_MAX (0x0000000F) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_DEF (0x00000008) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_OFF (13) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_WID ( 5) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_MSK (0x0003E000) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_MAX (0x0000001F) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_DEF (0x00000011) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_OFF (18) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_WID ( 1) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_MSK (0x00040000) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_MAX (0x00000001) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_DEF (0x00000000) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_Spare_OFF (19) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_Spare_WID (13) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_Spare_MSK (0xFFF80000) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_Spare_MAX (0x00001FFF) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_Spare_DEF (0x00000000) + +#define DDRDATA3CH0_CR_DDRCRVSSHIORVREFCONTROL_REG (0x0000066C) + #define DDRDATA3CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_OFF ( 0) + #define DDRDATA3CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_WID (24) + #define DDRDATA3CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_MSK (0x00FFFFFF) + #define DDRDATA3CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_MAX (0x00FFFFFF) + #define DDRDATA3CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_DEF (0x00000000) + #define DDRDATA3CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_OFF (24) + #define DDRDATA3CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_WID ( 8) + #define DDRDATA3CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_MSK (0xFF000000) + #define DDRDATA3CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_MAX (0x000000FF) + #define DDRDATA3CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_DEF (0x00000000) + +#define DDRDATA3CH0_CR_DDRCRDATAOFFSETTRAIN_REG (0x00000670) + #define DDRDATA3CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_OFF ( 0) + #define DDRDATA3CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_WID ( 6) + #define DDRDATA3CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MSK (0x0000003F) + #define DDRDATA3CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MAX (0x0000003F) + #define DDRDATA3CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_DEF (0x00000000) + #define DDRDATA3CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_OFF ( 6) + #define DDRDATA3CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_WID ( 6) + #define DDRDATA3CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MSK (0x00000FC0) + #define DDRDATA3CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MAX (0x0000003F) + #define DDRDATA3CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_DEF (0x00000000) + #define DDRDATA3CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_OFF (12) + #define DDRDATA3CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_WID ( 6) + #define DDRDATA3CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MSK (0x0003F000) + #define DDRDATA3CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MAX (0x0000003F) + #define DDRDATA3CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_DEF (0x00000000) + #define DDRDATA3CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_OFF (18) + #define DDRDATA3CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_WID ( 6) + #define DDRDATA3CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MSK (0x00FC0000) + #define DDRDATA3CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MAX (0x0000003F) + #define DDRDATA3CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_DEF (0x00000000) + #define DDRDATA3CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_OFF (24) + #define DDRDATA3CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_WID ( 7) + #define DDRDATA3CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MSK (0x7F000000) + #define DDRDATA3CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MAX (0x0000007F) + #define DDRDATA3CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_DEF (0x00000000) + #define DDRDATA3CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_OFF (31) + #define DDRDATA3CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_WID ( 1) + #define DDRDATA3CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_MSK (0x80000000) + #define DDRDATA3CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_MAX (0x00000001) + #define DDRDATA3CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_DEF (0x00000000) + +#define DDRDATA3CH0_CR_DDRCRDATACONTROL0_REG (0x00000674) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_OFF ( 0) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_WID ( 1) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_MSK (0x00000001) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_MAX (0x00000001) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_DEF (0x00000000) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_OFF ( 1) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_WID ( 1) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_MSK (0x00000002) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_MAX (0x00000001) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_DEF (0x00000000) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_OFF ( 2) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_WID ( 1) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_MSK (0x00000004) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_MAX (0x00000001) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_DEF (0x00000000) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_OFF ( 3) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_WID ( 1) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MSK (0x00000008) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MAX (0x00000001) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_DEF (0x00000000) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_TxOn_OFF ( 4) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_TxOn_WID ( 1) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_TxOn_MSK (0x00000010) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_TxOn_MAX (0x00000001) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_TxOn_DEF (0x00000000) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RfOn_OFF ( 5) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RfOn_WID ( 1) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RfOn_MSK (0x00000020) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RfOn_MAX (0x00000001) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RfOn_DEF (0x00000000) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RxPiOn_OFF ( 6) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RxPiOn_WID ( 1) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RxPiOn_MSK (0x00000040) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RxPiOn_MAX (0x00000001) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RxPiOn_DEF (0x00000000) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_TxPiOn_OFF ( 7) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_TxPiOn_WID ( 1) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_TxPiOn_MSK (0x00000080) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_TxPiOn_MAX (0x00000001) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_TxPiOn_DEF (0x00000000) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_OFF ( 8) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_WID ( 1) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_MSK (0x00000100) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_MAX (0x00000001) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_DEF (0x00000000) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_OFF ( 9) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_WID ( 1) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MSK (0x00000200) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MAX (0x00000001) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_DEF (0x00000000) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_TxDisable_OFF (10) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_TxDisable_WID ( 1) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_TxDisable_MSK (0x00000400) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_TxDisable_MAX (0x00000001) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_TxDisable_DEF (0x00000000) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RxDisable_OFF (11) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RxDisable_WID ( 1) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RxDisable_MSK (0x00000800) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RxDisable_MAX (0x00000001) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RxDisable_DEF (0x00000000) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_TxLong_OFF (12) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_TxLong_WID ( 1) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_TxLong_MSK (0x00001000) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_TxLong_MAX (0x00000001) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_TxLong_DEF (0x00000000) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_OFF (13) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_WID ( 2) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_MSK (0x00006000) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_MAX (0x00000003) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_DEF (0x00000000) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RxReadPointer_OFF (15) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RxReadPointer_WID ( 3) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RxReadPointer_MSK (0x00038000) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RxReadPointer_MAX (0x00000007) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RxReadPointer_DEF (0x00000000) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_OFF (18) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_WID ( 1) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_MSK (0x00040000) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_MAX (0x00000001) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_DEF (0x00000000) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_OFF (19) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_WID ( 1) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_MSK (0x00080000) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_MAX (0x00000001) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_DEF (0x00000000) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_ReadRFRd_OFF (20) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_ReadRFRd_WID ( 1) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_ReadRFRd_MSK (0x00100000) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_ReadRFRd_MAX (0x00000001) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_ReadRFRd_DEF (0x00000000) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_ReadRFWr_OFF (21) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_ReadRFWr_WID ( 1) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_ReadRFWr_MSK (0x00200000) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_ReadRFWr_MAX (0x00000001) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_ReadRFWr_DEF (0x00000000) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_ReadRFRank_OFF (22) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_ReadRFRank_WID ( 2) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_ReadRFRank_MSK (0x00C00000) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_ReadRFRank_MAX (0x00000003) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_ReadRFRank_DEF (0x00000000) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_OFF (24) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_WID ( 1) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_MSK (0x01000000) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_MAX (0x00000001) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_DEF (0x00000000) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_OdtSampOff_OFF (25) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_OdtSampOff_WID ( 1) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_OdtSampOff_MSK (0x02000000) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_OdtSampOff_MAX (0x00000001) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_OdtSampOff_DEF (0x00000000) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_OFF (26) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_WID ( 1) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_MSK (0x04000000) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_MAX (0x00000001) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_DEF (0x00000000) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_OFF (27) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_WID ( 1) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MSK (0x08000000) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MAX (0x00000001) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_DEF (0x00000000) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_OFF (28) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_WID ( 1) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_MSK (0x10000000) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_MAX (0x00000001) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_DEF (0x00000000) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_OFF (29) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_WID ( 1) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_MSK (0x20000000) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_MAX (0x00000001) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_DEF (0x00000000) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_OFF (30) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_WID ( 1) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MSK (0x40000000) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MAX (0x00000001) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_DEF (0x00000000) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_OFF (31) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_WID ( 1) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_MSK (0x80000000) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_MAX (0x00000001) + #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_DEF (0x00000000) + +#define DDRDATA3CH0_CR_DDRCRVREFADJUST1_REG (0x00000678) + #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_OFF ( 0) + #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_WID ( 7) + #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_MSK (0x0000007F) + #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_MAX (0x0000007F) + #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_DEF (0x00000000) + #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_OFF ( 7) + #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_WID ( 7) + #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_MSK (0x00003F80) + #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_MAX (0x0000007F) + #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_DEF (0x00000000) + #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_OFF (14) + #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_WID ( 7) + #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_MSK (0x001FC000) + #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_MAX (0x0000007F) + #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_DEF (0x00000000) + #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_OFF (21) + #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_WID ( 1) + #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_MSK (0x00200000) + #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_MAX (0x00000001) + #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_DEF (0x00000000) + #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_OFF (22) + #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_WID ( 1) + #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_MSK (0x00400000) + #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_MAX (0x00000001) + #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_DEF (0x00000000) + #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_OFF (23) + #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_WID ( 1) + #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_MSK (0x00800000) + #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_MAX (0x00000001) + #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_DEF (0x00000000) + #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_OFF (24) + #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_WID ( 2) + #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_MSK (0x03000000) + #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_MAX (0x00000003) + #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_DEF (0x00000000) + #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_OFF (26) + #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_WID ( 1) + #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_MSK (0x04000000) + #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_MAX (0x00000001) + #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_DEF (0x00000000) + #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_Rsvd_OFF (27) + #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_Rsvd_WID ( 2) + #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_Rsvd_MSK (0x18000000) + #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_Rsvd_MAX (0x00000003) + #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_Rsvd_DEF (0x00000000) + #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_caSlowBW_OFF (29) + #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_caSlowBW_WID ( 1) + #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_caSlowBW_MSK (0x20000000) + #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_caSlowBW_MAX (0x00000001) + #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_caSlowBW_DEF (0x00000000) + #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_OFF (30) + #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_WID ( 1) + #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_MSK (0x40000000) + #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_MAX (0x00000001) + #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_DEF (0x00000000) + #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_OFF (31) + #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_WID ( 1) + #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_MSK (0x80000000) + #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_MAX (0x00000001) + #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_DEF (0x00000000) + +#define DDRDATA3CH1_CR_RXTRAINRANK0_REG (0x00000700) + #define DDRDATA3CH1_CR_RXTRAINRANK0_RxRcvEnPi_OFF ( 0) + #define DDRDATA3CH1_CR_RXTRAINRANK0_RxRcvEnPi_WID ( 9) + #define DDRDATA3CH1_CR_RXTRAINRANK0_RxRcvEnPi_MSK (0x000001FF) + #define DDRDATA3CH1_CR_RXTRAINRANK0_RxRcvEnPi_MAX (0x000001FF) + #define DDRDATA3CH1_CR_RXTRAINRANK0_RxDqsPPi_OFF ( 9) + #define DDRDATA3CH1_CR_RXTRAINRANK0_RxDqsPPi_WID ( 6) + #define DDRDATA3CH1_CR_RXTRAINRANK0_RxDqsPPi_MSK (0x00007E00) + #define DDRDATA3CH1_CR_RXTRAINRANK0_RxDqsPPi_MAX (0x0000003F) + #define DDRDATA3CH1_CR_RXTRAINRANK0_RxEq_OFF (15) + #define DDRDATA3CH1_CR_RXTRAINRANK0_RxEq_WID ( 5) + #define DDRDATA3CH1_CR_RXTRAINRANK0_RxEq_MSK (0x000F8000) + #define DDRDATA3CH1_CR_RXTRAINRANK0_RxEq_MAX (0x0000001F) + #define DDRDATA3CH1_CR_RXTRAINRANK0_RxDqsNPi_OFF (20) + #define DDRDATA3CH1_CR_RXTRAINRANK0_RxDqsNPi_WID ( 6) + #define DDRDATA3CH1_CR_RXTRAINRANK0_RxDqsNPi_MSK (0x03F00000) + #define DDRDATA3CH1_CR_RXTRAINRANK0_RxDqsNPi_MAX (0x0000003F) + #define DDRDATA3CH1_CR_RXTRAINRANK0_RxVref_OFF (26) + #define DDRDATA3CH1_CR_RXTRAINRANK0_RxVref_WID ( 6) + #define DDRDATA3CH1_CR_RXTRAINRANK0_RxVref_MSK (0xFC000000) + #define DDRDATA3CH1_CR_RXTRAINRANK0_RxVref_MAX (0x0000003F) + +#define DDRDATA3CH1_CR_RXTRAINRANK1_REG (0x00000704) + #define DDRDATA3CH1_CR_RXTRAINRANK1_RxRcvEnPi_OFF ( 0) + #define DDRDATA3CH1_CR_RXTRAINRANK1_RxRcvEnPi_WID ( 9) + #define DDRDATA3CH1_CR_RXTRAINRANK1_RxRcvEnPi_MSK (0x000001FF) + #define DDRDATA3CH1_CR_RXTRAINRANK1_RxRcvEnPi_MAX (0x000001FF) + #define DDRDATA3CH1_CR_RXTRAINRANK1_RxDqsPPi_OFF ( 9) + #define DDRDATA3CH1_CR_RXTRAINRANK1_RxDqsPPi_WID ( 6) + #define DDRDATA3CH1_CR_RXTRAINRANK1_RxDqsPPi_MSK (0x00007E00) + #define DDRDATA3CH1_CR_RXTRAINRANK1_RxDqsPPi_MAX (0x0000003F) + #define DDRDATA3CH1_CR_RXTRAINRANK1_RxEq_OFF (15) + #define DDRDATA3CH1_CR_RXTRAINRANK1_RxEq_WID ( 5) + #define DDRDATA3CH1_CR_RXTRAINRANK1_RxEq_MSK (0x000F8000) + #define DDRDATA3CH1_CR_RXTRAINRANK1_RxEq_MAX (0x0000001F) + #define DDRDATA3CH1_CR_RXTRAINRANK1_RxDqsNPi_OFF (20) + #define DDRDATA3CH1_CR_RXTRAINRANK1_RxDqsNPi_WID ( 6) + #define DDRDATA3CH1_CR_RXTRAINRANK1_RxDqsNPi_MSK (0x03F00000) + #define DDRDATA3CH1_CR_RXTRAINRANK1_RxDqsNPi_MAX (0x0000003F) + #define DDRDATA3CH1_CR_RXTRAINRANK1_RxVref_OFF (26) + #define DDRDATA3CH1_CR_RXTRAINRANK1_RxVref_WID ( 6) + #define DDRDATA3CH1_CR_RXTRAINRANK1_RxVref_MSK (0xFC000000) + #define DDRDATA3CH1_CR_RXTRAINRANK1_RxVref_MAX (0x0000003F) + +#define DDRDATA3CH1_CR_RXTRAINRANK2_REG (0x00000708) + #define DDRDATA3CH1_CR_RXTRAINRANK2_RxRcvEnPi_OFF ( 0) + #define DDRDATA3CH1_CR_RXTRAINRANK2_RxRcvEnPi_WID ( 9) + #define DDRDATA3CH1_CR_RXTRAINRANK2_RxRcvEnPi_MSK (0x000001FF) + #define DDRDATA3CH1_CR_RXTRAINRANK2_RxRcvEnPi_MAX (0x000001FF) + #define DDRDATA3CH1_CR_RXTRAINRANK2_RxDqsPPi_OFF ( 9) + #define DDRDATA3CH1_CR_RXTRAINRANK2_RxDqsPPi_WID ( 6) + #define DDRDATA3CH1_CR_RXTRAINRANK2_RxDqsPPi_MSK (0x00007E00) + #define DDRDATA3CH1_CR_RXTRAINRANK2_RxDqsPPi_MAX (0x0000003F) + #define DDRDATA3CH1_CR_RXTRAINRANK2_RxEq_OFF (15) + #define DDRDATA3CH1_CR_RXTRAINRANK2_RxEq_WID ( 5) + #define DDRDATA3CH1_CR_RXTRAINRANK2_RxEq_MSK (0x000F8000) + #define DDRDATA3CH1_CR_RXTRAINRANK2_RxEq_MAX (0x0000001F) + #define DDRDATA3CH1_CR_RXTRAINRANK2_RxDqsNPi_OFF (20) + #define DDRDATA3CH1_CR_RXTRAINRANK2_RxDqsNPi_WID ( 6) + #define DDRDATA3CH1_CR_RXTRAINRANK2_RxDqsNPi_MSK (0x03F00000) + #define DDRDATA3CH1_CR_RXTRAINRANK2_RxDqsNPi_MAX (0x0000003F) + #define DDRDATA3CH1_CR_RXTRAINRANK2_RxVref_OFF (26) + #define DDRDATA3CH1_CR_RXTRAINRANK2_RxVref_WID ( 6) + #define DDRDATA3CH1_CR_RXTRAINRANK2_RxVref_MSK (0xFC000000) + #define DDRDATA3CH1_CR_RXTRAINRANK2_RxVref_MAX (0x0000003F) + +#define DDRDATA3CH1_CR_RXTRAINRANK3_REG (0x0000070C) + #define DDRDATA3CH1_CR_RXTRAINRANK3_RxRcvEnPi_OFF ( 0) + #define DDRDATA3CH1_CR_RXTRAINRANK3_RxRcvEnPi_WID ( 9) + #define DDRDATA3CH1_CR_RXTRAINRANK3_RxRcvEnPi_MSK (0x000001FF) + #define DDRDATA3CH1_CR_RXTRAINRANK3_RxRcvEnPi_MAX (0x000001FF) + #define DDRDATA3CH1_CR_RXTRAINRANK3_RxDqsPPi_OFF ( 9) + #define DDRDATA3CH1_CR_RXTRAINRANK3_RxDqsPPi_WID ( 6) + #define DDRDATA3CH1_CR_RXTRAINRANK3_RxDqsPPi_MSK (0x00007E00) + #define DDRDATA3CH1_CR_RXTRAINRANK3_RxDqsPPi_MAX (0x0000003F) + #define DDRDATA3CH1_CR_RXTRAINRANK3_RxEq_OFF (15) + #define DDRDATA3CH1_CR_RXTRAINRANK3_RxEq_WID ( 5) + #define DDRDATA3CH1_CR_RXTRAINRANK3_RxEq_MSK (0x000F8000) + #define DDRDATA3CH1_CR_RXTRAINRANK3_RxEq_MAX (0x0000001F) + #define DDRDATA3CH1_CR_RXTRAINRANK3_RxDqsNPi_OFF (20) + #define DDRDATA3CH1_CR_RXTRAINRANK3_RxDqsNPi_WID ( 6) + #define DDRDATA3CH1_CR_RXTRAINRANK3_RxDqsNPi_MSK (0x03F00000) + #define DDRDATA3CH1_CR_RXTRAINRANK3_RxDqsNPi_MAX (0x0000003F) + #define DDRDATA3CH1_CR_RXTRAINRANK3_RxVref_OFF (26) + #define DDRDATA3CH1_CR_RXTRAINRANK3_RxVref_WID ( 6) + #define DDRDATA3CH1_CR_RXTRAINRANK3_RxVref_MSK (0xFC000000) + #define DDRDATA3CH1_CR_RXTRAINRANK3_RxVref_MAX (0x0000003F) + +#define DDRDATA3CH1_CR_RXPERBITRANK0_REG (0x00000710) + #define DDRDATA3CH1_CR_RXPERBITRANK0_Lane0_OFF ( 0) + #define DDRDATA3CH1_CR_RXPERBITRANK0_Lane0_WID ( 4) + #define DDRDATA3CH1_CR_RXPERBITRANK0_Lane0_MSK (0x0000000F) + #define DDRDATA3CH1_CR_RXPERBITRANK0_Lane0_MAX (0x0000000F) + #define DDRDATA3CH1_CR_RXPERBITRANK0_Lane1_OFF ( 4) + #define DDRDATA3CH1_CR_RXPERBITRANK0_Lane1_WID ( 4) + #define DDRDATA3CH1_CR_RXPERBITRANK0_Lane1_MSK (0x000000F0) + #define DDRDATA3CH1_CR_RXPERBITRANK0_Lane1_MAX (0x0000000F) + #define DDRDATA3CH1_CR_RXPERBITRANK0_Lane2_OFF ( 8) + #define DDRDATA3CH1_CR_RXPERBITRANK0_Lane2_WID ( 4) + #define DDRDATA3CH1_CR_RXPERBITRANK0_Lane2_MSK (0x00000F00) + #define DDRDATA3CH1_CR_RXPERBITRANK0_Lane2_MAX (0x0000000F) + #define DDRDATA3CH1_CR_RXPERBITRANK0_Lane3_OFF (12) + #define DDRDATA3CH1_CR_RXPERBITRANK0_Lane3_WID ( 4) + #define DDRDATA3CH1_CR_RXPERBITRANK0_Lane3_MSK (0x0000F000) + #define DDRDATA3CH1_CR_RXPERBITRANK0_Lane3_MAX (0x0000000F) + #define DDRDATA3CH1_CR_RXPERBITRANK0_Lane4_OFF (16) + #define DDRDATA3CH1_CR_RXPERBITRANK0_Lane4_WID ( 4) + #define DDRDATA3CH1_CR_RXPERBITRANK0_Lane4_MSK (0x000F0000) + #define DDRDATA3CH1_CR_RXPERBITRANK0_Lane4_MAX (0x0000000F) + #define DDRDATA3CH1_CR_RXPERBITRANK0_Lane5_OFF (20) + #define DDRDATA3CH1_CR_RXPERBITRANK0_Lane5_WID ( 4) + #define DDRDATA3CH1_CR_RXPERBITRANK0_Lane5_MSK (0x00F00000) + #define DDRDATA3CH1_CR_RXPERBITRANK0_Lane5_MAX (0x0000000F) + #define DDRDATA3CH1_CR_RXPERBITRANK0_Lane6_OFF (24) + #define DDRDATA3CH1_CR_RXPERBITRANK0_Lane6_WID ( 4) + #define DDRDATA3CH1_CR_RXPERBITRANK0_Lane6_MSK (0x0F000000) + #define DDRDATA3CH1_CR_RXPERBITRANK0_Lane6_MAX (0x0000000F) + #define DDRDATA3CH1_CR_RXPERBITRANK0_Lane7_OFF (28) + #define DDRDATA3CH1_CR_RXPERBITRANK0_Lane7_WID ( 4) + #define DDRDATA3CH1_CR_RXPERBITRANK0_Lane7_MSK (0xF0000000) + #define DDRDATA3CH1_CR_RXPERBITRANK0_Lane7_MAX (0x0000000F) + +#define DDRDATA3CH1_CR_RXPERBITRANK1_REG (0x00000714) + #define DDRDATA3CH1_CR_RXPERBITRANK1_Lane0_OFF ( 0) + #define DDRDATA3CH1_CR_RXPERBITRANK1_Lane0_WID ( 4) + #define DDRDATA3CH1_CR_RXPERBITRANK1_Lane0_MSK (0x0000000F) + #define DDRDATA3CH1_CR_RXPERBITRANK1_Lane0_MAX (0x0000000F) + #define DDRDATA3CH1_CR_RXPERBITRANK1_Lane1_OFF ( 4) + #define DDRDATA3CH1_CR_RXPERBITRANK1_Lane1_WID ( 4) + #define DDRDATA3CH1_CR_RXPERBITRANK1_Lane1_MSK (0x000000F0) + #define DDRDATA3CH1_CR_RXPERBITRANK1_Lane1_MAX (0x0000000F) + #define DDRDATA3CH1_CR_RXPERBITRANK1_Lane2_OFF ( 8) + #define DDRDATA3CH1_CR_RXPERBITRANK1_Lane2_WID ( 4) + #define DDRDATA3CH1_CR_RXPERBITRANK1_Lane2_MSK (0x00000F00) + #define DDRDATA3CH1_CR_RXPERBITRANK1_Lane2_MAX (0x0000000F) + #define DDRDATA3CH1_CR_RXPERBITRANK1_Lane3_OFF (12) + #define DDRDATA3CH1_CR_RXPERBITRANK1_Lane3_WID ( 4) + #define DDRDATA3CH1_CR_RXPERBITRANK1_Lane3_MSK (0x0000F000) + #define DDRDATA3CH1_CR_RXPERBITRANK1_Lane3_MAX (0x0000000F) + #define DDRDATA3CH1_CR_RXPERBITRANK1_Lane4_OFF (16) + #define DDRDATA3CH1_CR_RXPERBITRANK1_Lane4_WID ( 4) + #define DDRDATA3CH1_CR_RXPERBITRANK1_Lane4_MSK (0x000F0000) + #define DDRDATA3CH1_CR_RXPERBITRANK1_Lane4_MAX (0x0000000F) + #define DDRDATA3CH1_CR_RXPERBITRANK1_Lane5_OFF (20) + #define DDRDATA3CH1_CR_RXPERBITRANK1_Lane5_WID ( 4) + #define DDRDATA3CH1_CR_RXPERBITRANK1_Lane5_MSK (0x00F00000) + #define DDRDATA3CH1_CR_RXPERBITRANK1_Lane5_MAX (0x0000000F) + #define DDRDATA3CH1_CR_RXPERBITRANK1_Lane6_OFF (24) + #define DDRDATA3CH1_CR_RXPERBITRANK1_Lane6_WID ( 4) + #define DDRDATA3CH1_CR_RXPERBITRANK1_Lane6_MSK (0x0F000000) + #define DDRDATA3CH1_CR_RXPERBITRANK1_Lane6_MAX (0x0000000F) + #define DDRDATA3CH1_CR_RXPERBITRANK1_Lane7_OFF (28) + #define DDRDATA3CH1_CR_RXPERBITRANK1_Lane7_WID ( 4) + #define DDRDATA3CH1_CR_RXPERBITRANK1_Lane7_MSK (0xF0000000) + #define DDRDATA3CH1_CR_RXPERBITRANK1_Lane7_MAX (0x0000000F) + +#define DDRDATA3CH1_CR_RXPERBITRANK2_REG (0x00000718) + #define DDRDATA3CH1_CR_RXPERBITRANK2_Lane0_OFF ( 0) + #define DDRDATA3CH1_CR_RXPERBITRANK2_Lane0_WID ( 4) + #define DDRDATA3CH1_CR_RXPERBITRANK2_Lane0_MSK (0x0000000F) + #define DDRDATA3CH1_CR_RXPERBITRANK2_Lane0_MAX (0x0000000F) + #define DDRDATA3CH1_CR_RXPERBITRANK2_Lane1_OFF ( 4) + #define DDRDATA3CH1_CR_RXPERBITRANK2_Lane1_WID ( 4) + #define DDRDATA3CH1_CR_RXPERBITRANK2_Lane1_MSK (0x000000F0) + #define DDRDATA3CH1_CR_RXPERBITRANK2_Lane1_MAX (0x0000000F) + #define DDRDATA3CH1_CR_RXPERBITRANK2_Lane2_OFF ( 8) + #define DDRDATA3CH1_CR_RXPERBITRANK2_Lane2_WID ( 4) + #define DDRDATA3CH1_CR_RXPERBITRANK2_Lane2_MSK (0x00000F00) + #define DDRDATA3CH1_CR_RXPERBITRANK2_Lane2_MAX (0x0000000F) + #define DDRDATA3CH1_CR_RXPERBITRANK2_Lane3_OFF (12) + #define DDRDATA3CH1_CR_RXPERBITRANK2_Lane3_WID ( 4) + #define DDRDATA3CH1_CR_RXPERBITRANK2_Lane3_MSK (0x0000F000) + #define DDRDATA3CH1_CR_RXPERBITRANK2_Lane3_MAX (0x0000000F) + #define DDRDATA3CH1_CR_RXPERBITRANK2_Lane4_OFF (16) + #define DDRDATA3CH1_CR_RXPERBITRANK2_Lane4_WID ( 4) + #define DDRDATA3CH1_CR_RXPERBITRANK2_Lane4_MSK (0x000F0000) + #define DDRDATA3CH1_CR_RXPERBITRANK2_Lane4_MAX (0x0000000F) + #define DDRDATA3CH1_CR_RXPERBITRANK2_Lane5_OFF (20) + #define DDRDATA3CH1_CR_RXPERBITRANK2_Lane5_WID ( 4) + #define DDRDATA3CH1_CR_RXPERBITRANK2_Lane5_MSK (0x00F00000) + #define DDRDATA3CH1_CR_RXPERBITRANK2_Lane5_MAX (0x0000000F) + #define DDRDATA3CH1_CR_RXPERBITRANK2_Lane6_OFF (24) + #define DDRDATA3CH1_CR_RXPERBITRANK2_Lane6_WID ( 4) + #define DDRDATA3CH1_CR_RXPERBITRANK2_Lane6_MSK (0x0F000000) + #define DDRDATA3CH1_CR_RXPERBITRANK2_Lane6_MAX (0x0000000F) + #define DDRDATA3CH1_CR_RXPERBITRANK2_Lane7_OFF (28) + #define DDRDATA3CH1_CR_RXPERBITRANK2_Lane7_WID ( 4) + #define DDRDATA3CH1_CR_RXPERBITRANK2_Lane7_MSK (0xF0000000) + #define DDRDATA3CH1_CR_RXPERBITRANK2_Lane7_MAX (0x0000000F) + +#define DDRDATA3CH1_CR_RXPERBITRANK3_REG (0x0000071C) + #define DDRDATA3CH1_CR_RXPERBITRANK3_Lane0_OFF ( 0) + #define DDRDATA3CH1_CR_RXPERBITRANK3_Lane0_WID ( 4) + #define DDRDATA3CH1_CR_RXPERBITRANK3_Lane0_MSK (0x0000000F) + #define DDRDATA3CH1_CR_RXPERBITRANK3_Lane0_MAX (0x0000000F) + #define DDRDATA3CH1_CR_RXPERBITRANK3_Lane1_OFF ( 4) + #define DDRDATA3CH1_CR_RXPERBITRANK3_Lane1_WID ( 4) + #define DDRDATA3CH1_CR_RXPERBITRANK3_Lane1_MSK (0x000000F0) + #define DDRDATA3CH1_CR_RXPERBITRANK3_Lane1_MAX (0x0000000F) + #define DDRDATA3CH1_CR_RXPERBITRANK3_Lane2_OFF ( 8) + #define DDRDATA3CH1_CR_RXPERBITRANK3_Lane2_WID ( 4) + #define DDRDATA3CH1_CR_RXPERBITRANK3_Lane2_MSK (0x00000F00) + #define DDRDATA3CH1_CR_RXPERBITRANK3_Lane2_MAX (0x0000000F) + #define DDRDATA3CH1_CR_RXPERBITRANK3_Lane3_OFF (12) + #define DDRDATA3CH1_CR_RXPERBITRANK3_Lane3_WID ( 4) + #define DDRDATA3CH1_CR_RXPERBITRANK3_Lane3_MSK (0x0000F000) + #define DDRDATA3CH1_CR_RXPERBITRANK3_Lane3_MAX (0x0000000F) + #define DDRDATA3CH1_CR_RXPERBITRANK3_Lane4_OFF (16) + #define DDRDATA3CH1_CR_RXPERBITRANK3_Lane4_WID ( 4) + #define DDRDATA3CH1_CR_RXPERBITRANK3_Lane4_MSK (0x000F0000) + #define DDRDATA3CH1_CR_RXPERBITRANK3_Lane4_MAX (0x0000000F) + #define DDRDATA3CH1_CR_RXPERBITRANK3_Lane5_OFF (20) + #define DDRDATA3CH1_CR_RXPERBITRANK3_Lane5_WID ( 4) + #define DDRDATA3CH1_CR_RXPERBITRANK3_Lane5_MSK (0x00F00000) + #define DDRDATA3CH1_CR_RXPERBITRANK3_Lane5_MAX (0x0000000F) + #define DDRDATA3CH1_CR_RXPERBITRANK3_Lane6_OFF (24) + #define DDRDATA3CH1_CR_RXPERBITRANK3_Lane6_WID ( 4) + #define DDRDATA3CH1_CR_RXPERBITRANK3_Lane6_MSK (0x0F000000) + #define DDRDATA3CH1_CR_RXPERBITRANK3_Lane6_MAX (0x0000000F) + #define DDRDATA3CH1_CR_RXPERBITRANK3_Lane7_OFF (28) + #define DDRDATA3CH1_CR_RXPERBITRANK3_Lane7_WID ( 4) + #define DDRDATA3CH1_CR_RXPERBITRANK3_Lane7_MSK (0xF0000000) + #define DDRDATA3CH1_CR_RXPERBITRANK3_Lane7_MAX (0x0000000F) + +#define DDRDATA3CH1_CR_TXTRAINRANK0_REG (0x00000720) + #define DDRDATA3CH1_CR_TXTRAINRANK0_TxDqDelay_OFF ( 0) + #define DDRDATA3CH1_CR_TXTRAINRANK0_TxDqDelay_WID ( 9) + #define DDRDATA3CH1_CR_TXTRAINRANK0_TxDqDelay_MSK (0x000001FF) + #define DDRDATA3CH1_CR_TXTRAINRANK0_TxDqDelay_MAX (0x000001FF) + #define DDRDATA3CH1_CR_TXTRAINRANK0_TxDqsDelay_OFF ( 9) + #define DDRDATA3CH1_CR_TXTRAINRANK0_TxDqsDelay_WID ( 9) + #define DDRDATA3CH1_CR_TXTRAINRANK0_TxDqsDelay_MSK (0x0003FE00) + #define DDRDATA3CH1_CR_TXTRAINRANK0_TxDqsDelay_MAX (0x000001FF) + #define DDRDATA3CH1_CR_TXTRAINRANK0_Spare0_OFF (18) + #define DDRDATA3CH1_CR_TXTRAINRANK0_Spare0_WID ( 2) + #define DDRDATA3CH1_CR_TXTRAINRANK0_Spare0_MSK (0x000C0000) + #define DDRDATA3CH1_CR_TXTRAINRANK0_Spare0_MAX (0x00000003) + #define DDRDATA3CH1_CR_TXTRAINRANK0_TxEqualization_OFF (20) + #define DDRDATA3CH1_CR_TXTRAINRANK0_TxEqualization_WID ( 6) + #define DDRDATA3CH1_CR_TXTRAINRANK0_TxEqualization_MSK (0x03F00000) + #define DDRDATA3CH1_CR_TXTRAINRANK0_TxEqualization_MAX (0x0000003F) + #define DDRDATA3CH1_CR_TXTRAINRANK0_Spare1_OFF (26) + #define DDRDATA3CH1_CR_TXTRAINRANK0_Spare1_WID ( 6) + #define DDRDATA3CH1_CR_TXTRAINRANK0_Spare1_MSK (0xFC000000) + #define DDRDATA3CH1_CR_TXTRAINRANK0_Spare1_MAX (0x0000003F) + +#define DDRDATA3CH1_CR_TXTRAINRANK1_REG (0x00000724) + #define DDRDATA3CH1_CR_TXTRAINRANK1_TxDqDelay_OFF ( 0) + #define DDRDATA3CH1_CR_TXTRAINRANK1_TxDqDelay_WID ( 9) + #define DDRDATA3CH1_CR_TXTRAINRANK1_TxDqDelay_MSK (0x000001FF) + #define DDRDATA3CH1_CR_TXTRAINRANK1_TxDqDelay_MAX (0x000001FF) + #define DDRDATA3CH1_CR_TXTRAINRANK1_TxDqsDelay_OFF ( 9) + #define DDRDATA3CH1_CR_TXTRAINRANK1_TxDqsDelay_WID ( 9) + #define DDRDATA3CH1_CR_TXTRAINRANK1_TxDqsDelay_MSK (0x0003FE00) + #define DDRDATA3CH1_CR_TXTRAINRANK1_TxDqsDelay_MAX (0x000001FF) + #define DDRDATA3CH1_CR_TXTRAINRANK1_Spare0_OFF (18) + #define DDRDATA3CH1_CR_TXTRAINRANK1_Spare0_WID ( 2) + #define DDRDATA3CH1_CR_TXTRAINRANK1_Spare0_MSK (0x000C0000) + #define DDRDATA3CH1_CR_TXTRAINRANK1_Spare0_MAX (0x00000003) + #define DDRDATA3CH1_CR_TXTRAINRANK1_TxEqualization_OFF (20) + #define DDRDATA3CH1_CR_TXTRAINRANK1_TxEqualization_WID ( 6) + #define DDRDATA3CH1_CR_TXTRAINRANK1_TxEqualization_MSK (0x03F00000) + #define DDRDATA3CH1_CR_TXTRAINRANK1_TxEqualization_MAX (0x0000003F) + #define DDRDATA3CH1_CR_TXTRAINRANK1_Spare1_OFF (26) + #define DDRDATA3CH1_CR_TXTRAINRANK1_Spare1_WID ( 6) + #define DDRDATA3CH1_CR_TXTRAINRANK1_Spare1_MSK (0xFC000000) + #define DDRDATA3CH1_CR_TXTRAINRANK1_Spare1_MAX (0x0000003F) + +#define DDRDATA3CH1_CR_TXTRAINRANK2_REG (0x00000728) + #define DDRDATA3CH1_CR_TXTRAINRANK2_TxDqDelay_OFF ( 0) + #define DDRDATA3CH1_CR_TXTRAINRANK2_TxDqDelay_WID ( 9) + #define DDRDATA3CH1_CR_TXTRAINRANK2_TxDqDelay_MSK (0x000001FF) + #define DDRDATA3CH1_CR_TXTRAINRANK2_TxDqDelay_MAX (0x000001FF) + #define DDRDATA3CH1_CR_TXTRAINRANK2_TxDqsDelay_OFF ( 9) + #define DDRDATA3CH1_CR_TXTRAINRANK2_TxDqsDelay_WID ( 9) + #define DDRDATA3CH1_CR_TXTRAINRANK2_TxDqsDelay_MSK (0x0003FE00) + #define DDRDATA3CH1_CR_TXTRAINRANK2_TxDqsDelay_MAX (0x000001FF) + #define DDRDATA3CH1_CR_TXTRAINRANK2_Spare0_OFF (18) + #define DDRDATA3CH1_CR_TXTRAINRANK2_Spare0_WID ( 2) + #define DDRDATA3CH1_CR_TXTRAINRANK2_Spare0_MSK (0x000C0000) + #define DDRDATA3CH1_CR_TXTRAINRANK2_Spare0_MAX (0x00000003) + #define DDRDATA3CH1_CR_TXTRAINRANK2_TxEqualization_OFF (20) + #define DDRDATA3CH1_CR_TXTRAINRANK2_TxEqualization_WID ( 6) + #define DDRDATA3CH1_CR_TXTRAINRANK2_TxEqualization_MSK (0x03F00000) + #define DDRDATA3CH1_CR_TXTRAINRANK2_TxEqualization_MAX (0x0000003F) + #define DDRDATA3CH1_CR_TXTRAINRANK2_Spare1_OFF (26) + #define DDRDATA3CH1_CR_TXTRAINRANK2_Spare1_WID ( 6) + #define DDRDATA3CH1_CR_TXTRAINRANK2_Spare1_MSK (0xFC000000) + #define DDRDATA3CH1_CR_TXTRAINRANK2_Spare1_MAX (0x0000003F) + +#define DDRDATA3CH1_CR_TXTRAINRANK3_REG (0x0000072C) + #define DDRDATA3CH1_CR_TXTRAINRANK3_TxDqDelay_OFF ( 0) + #define DDRDATA3CH1_CR_TXTRAINRANK3_TxDqDelay_WID ( 9) + #define DDRDATA3CH1_CR_TXTRAINRANK3_TxDqDelay_MSK (0x000001FF) + #define DDRDATA3CH1_CR_TXTRAINRANK3_TxDqDelay_MAX (0x000001FF) + #define DDRDATA3CH1_CR_TXTRAINRANK3_TxDqsDelay_OFF ( 9) + #define DDRDATA3CH1_CR_TXTRAINRANK3_TxDqsDelay_WID ( 9) + #define DDRDATA3CH1_CR_TXTRAINRANK3_TxDqsDelay_MSK (0x0003FE00) + #define DDRDATA3CH1_CR_TXTRAINRANK3_TxDqsDelay_MAX (0x000001FF) + #define DDRDATA3CH1_CR_TXTRAINRANK3_Spare0_OFF (18) + #define DDRDATA3CH1_CR_TXTRAINRANK3_Spare0_WID ( 2) + #define DDRDATA3CH1_CR_TXTRAINRANK3_Spare0_MSK (0x000C0000) + #define DDRDATA3CH1_CR_TXTRAINRANK3_Spare0_MAX (0x00000003) + #define DDRDATA3CH1_CR_TXTRAINRANK3_TxEqualization_OFF (20) + #define DDRDATA3CH1_CR_TXTRAINRANK3_TxEqualization_WID ( 6) + #define DDRDATA3CH1_CR_TXTRAINRANK3_TxEqualization_MSK (0x03F00000) + #define DDRDATA3CH1_CR_TXTRAINRANK3_TxEqualization_MAX (0x0000003F) + #define DDRDATA3CH1_CR_TXTRAINRANK3_Spare1_OFF (26) + #define DDRDATA3CH1_CR_TXTRAINRANK3_Spare1_WID ( 6) + #define DDRDATA3CH1_CR_TXTRAINRANK3_Spare1_MSK (0xFC000000) + #define DDRDATA3CH1_CR_TXTRAINRANK3_Spare1_MAX (0x0000003F) + +#define DDRDATA3CH1_CR_TXPERBITRANK0_REG (0x00000730) + #define DDRDATA3CH1_CR_TXPERBITRANK0_Lane0_OFF ( 0) + #define DDRDATA3CH1_CR_TXPERBITRANK0_Lane0_WID ( 4) + #define DDRDATA3CH1_CR_TXPERBITRANK0_Lane0_MSK (0x0000000F) + #define DDRDATA3CH1_CR_TXPERBITRANK0_Lane0_MAX (0x0000000F) + #define DDRDATA3CH1_CR_TXPERBITRANK0_Lane1_OFF ( 4) + #define DDRDATA3CH1_CR_TXPERBITRANK0_Lane1_WID ( 4) + #define DDRDATA3CH1_CR_TXPERBITRANK0_Lane1_MSK (0x000000F0) + #define DDRDATA3CH1_CR_TXPERBITRANK0_Lane1_MAX (0x0000000F) + #define DDRDATA3CH1_CR_TXPERBITRANK0_Lane2_OFF ( 8) + #define DDRDATA3CH1_CR_TXPERBITRANK0_Lane2_WID ( 4) + #define DDRDATA3CH1_CR_TXPERBITRANK0_Lane2_MSK (0x00000F00) + #define DDRDATA3CH1_CR_TXPERBITRANK0_Lane2_MAX (0x0000000F) + #define DDRDATA3CH1_CR_TXPERBITRANK0_Lane3_OFF (12) + #define DDRDATA3CH1_CR_TXPERBITRANK0_Lane3_WID ( 4) + #define DDRDATA3CH1_CR_TXPERBITRANK0_Lane3_MSK (0x0000F000) + #define DDRDATA3CH1_CR_TXPERBITRANK0_Lane3_MAX (0x0000000F) + #define DDRDATA3CH1_CR_TXPERBITRANK0_Lane4_OFF (16) + #define DDRDATA3CH1_CR_TXPERBITRANK0_Lane4_WID ( 4) + #define DDRDATA3CH1_CR_TXPERBITRANK0_Lane4_MSK (0x000F0000) + #define DDRDATA3CH1_CR_TXPERBITRANK0_Lane4_MAX (0x0000000F) + #define DDRDATA3CH1_CR_TXPERBITRANK0_Lane5_OFF (20) + #define DDRDATA3CH1_CR_TXPERBITRANK0_Lane5_WID ( 4) + #define DDRDATA3CH1_CR_TXPERBITRANK0_Lane5_MSK (0x00F00000) + #define DDRDATA3CH1_CR_TXPERBITRANK0_Lane5_MAX (0x0000000F) + #define DDRDATA3CH1_CR_TXPERBITRANK0_Lane6_OFF (24) + #define DDRDATA3CH1_CR_TXPERBITRANK0_Lane6_WID ( 4) + #define DDRDATA3CH1_CR_TXPERBITRANK0_Lane6_MSK (0x0F000000) + #define DDRDATA3CH1_CR_TXPERBITRANK0_Lane6_MAX (0x0000000F) + #define DDRDATA3CH1_CR_TXPERBITRANK0_Lane7_OFF (28) + #define DDRDATA3CH1_CR_TXPERBITRANK0_Lane7_WID ( 4) + #define DDRDATA3CH1_CR_TXPERBITRANK0_Lane7_MSK (0xF0000000) + #define DDRDATA3CH1_CR_TXPERBITRANK0_Lane7_MAX (0x0000000F) + +#define DDRDATA3CH1_CR_TXPERBITRANK1_REG (0x00000734) + #define DDRDATA3CH1_CR_TXPERBITRANK1_Lane0_OFF ( 0) + #define DDRDATA3CH1_CR_TXPERBITRANK1_Lane0_WID ( 4) + #define DDRDATA3CH1_CR_TXPERBITRANK1_Lane0_MSK (0x0000000F) + #define DDRDATA3CH1_CR_TXPERBITRANK1_Lane0_MAX (0x0000000F) + #define DDRDATA3CH1_CR_TXPERBITRANK1_Lane1_OFF ( 4) + #define DDRDATA3CH1_CR_TXPERBITRANK1_Lane1_WID ( 4) + #define DDRDATA3CH1_CR_TXPERBITRANK1_Lane1_MSK (0x000000F0) + #define DDRDATA3CH1_CR_TXPERBITRANK1_Lane1_MAX (0x0000000F) + #define DDRDATA3CH1_CR_TXPERBITRANK1_Lane2_OFF ( 8) + #define DDRDATA3CH1_CR_TXPERBITRANK1_Lane2_WID ( 4) + #define DDRDATA3CH1_CR_TXPERBITRANK1_Lane2_MSK (0x00000F00) + #define DDRDATA3CH1_CR_TXPERBITRANK1_Lane2_MAX (0x0000000F) + #define DDRDATA3CH1_CR_TXPERBITRANK1_Lane3_OFF (12) + #define DDRDATA3CH1_CR_TXPERBITRANK1_Lane3_WID ( 4) + #define DDRDATA3CH1_CR_TXPERBITRANK1_Lane3_MSK (0x0000F000) + #define DDRDATA3CH1_CR_TXPERBITRANK1_Lane3_MAX (0x0000000F) + #define DDRDATA3CH1_CR_TXPERBITRANK1_Lane4_OFF (16) + #define DDRDATA3CH1_CR_TXPERBITRANK1_Lane4_WID ( 4) + #define DDRDATA3CH1_CR_TXPERBITRANK1_Lane4_MSK (0x000F0000) + #define DDRDATA3CH1_CR_TXPERBITRANK1_Lane4_MAX (0x0000000F) + #define DDRDATA3CH1_CR_TXPERBITRANK1_Lane5_OFF (20) + #define DDRDATA3CH1_CR_TXPERBITRANK1_Lane5_WID ( 4) + #define DDRDATA3CH1_CR_TXPERBITRANK1_Lane5_MSK (0x00F00000) + #define DDRDATA3CH1_CR_TXPERBITRANK1_Lane5_MAX (0x0000000F) + #define DDRDATA3CH1_CR_TXPERBITRANK1_Lane6_OFF (24) + #define DDRDATA3CH1_CR_TXPERBITRANK1_Lane6_WID ( 4) + #define DDRDATA3CH1_CR_TXPERBITRANK1_Lane6_MSK (0x0F000000) + #define DDRDATA3CH1_CR_TXPERBITRANK1_Lane6_MAX (0x0000000F) + #define DDRDATA3CH1_CR_TXPERBITRANK1_Lane7_OFF (28) + #define DDRDATA3CH1_CR_TXPERBITRANK1_Lane7_WID ( 4) + #define DDRDATA3CH1_CR_TXPERBITRANK1_Lane7_MSK (0xF0000000) + #define DDRDATA3CH1_CR_TXPERBITRANK1_Lane7_MAX (0x0000000F) + +#define DDRDATA3CH1_CR_TXPERBITRANK2_REG (0x00000738) + #define DDRDATA3CH1_CR_TXPERBITRANK2_Lane0_OFF ( 0) + #define DDRDATA3CH1_CR_TXPERBITRANK2_Lane0_WID ( 4) + #define DDRDATA3CH1_CR_TXPERBITRANK2_Lane0_MSK (0x0000000F) + #define DDRDATA3CH1_CR_TXPERBITRANK2_Lane0_MAX (0x0000000F) + #define DDRDATA3CH1_CR_TXPERBITRANK2_Lane1_OFF ( 4) + #define DDRDATA3CH1_CR_TXPERBITRANK2_Lane1_WID ( 4) + #define DDRDATA3CH1_CR_TXPERBITRANK2_Lane1_MSK (0x000000F0) + #define DDRDATA3CH1_CR_TXPERBITRANK2_Lane1_MAX (0x0000000F) + #define DDRDATA3CH1_CR_TXPERBITRANK2_Lane2_OFF ( 8) + #define DDRDATA3CH1_CR_TXPERBITRANK2_Lane2_WID ( 4) + #define DDRDATA3CH1_CR_TXPERBITRANK2_Lane2_MSK (0x00000F00) + #define DDRDATA3CH1_CR_TXPERBITRANK2_Lane2_MAX (0x0000000F) + #define DDRDATA3CH1_CR_TXPERBITRANK2_Lane3_OFF (12) + #define DDRDATA3CH1_CR_TXPERBITRANK2_Lane3_WID ( 4) + #define DDRDATA3CH1_CR_TXPERBITRANK2_Lane3_MSK (0x0000F000) + #define DDRDATA3CH1_CR_TXPERBITRANK2_Lane3_MAX (0x0000000F) + #define DDRDATA3CH1_CR_TXPERBITRANK2_Lane4_OFF (16) + #define DDRDATA3CH1_CR_TXPERBITRANK2_Lane4_WID ( 4) + #define DDRDATA3CH1_CR_TXPERBITRANK2_Lane4_MSK (0x000F0000) + #define DDRDATA3CH1_CR_TXPERBITRANK2_Lane4_MAX (0x0000000F) + #define DDRDATA3CH1_CR_TXPERBITRANK2_Lane5_OFF (20) + #define DDRDATA3CH1_CR_TXPERBITRANK2_Lane5_WID ( 4) + #define DDRDATA3CH1_CR_TXPERBITRANK2_Lane5_MSK (0x00F00000) + #define DDRDATA3CH1_CR_TXPERBITRANK2_Lane5_MAX (0x0000000F) + #define DDRDATA3CH1_CR_TXPERBITRANK2_Lane6_OFF (24) + #define DDRDATA3CH1_CR_TXPERBITRANK2_Lane6_WID ( 4) + #define DDRDATA3CH1_CR_TXPERBITRANK2_Lane6_MSK (0x0F000000) + #define DDRDATA3CH1_CR_TXPERBITRANK2_Lane6_MAX (0x0000000F) + #define DDRDATA3CH1_CR_TXPERBITRANK2_Lane7_OFF (28) + #define DDRDATA3CH1_CR_TXPERBITRANK2_Lane7_WID ( 4) + #define DDRDATA3CH1_CR_TXPERBITRANK2_Lane7_MSK (0xF0000000) + #define DDRDATA3CH1_CR_TXPERBITRANK2_Lane7_MAX (0x0000000F) + +#define DDRDATA3CH1_CR_TXPERBITRANK3_REG (0x0000073C) + #define DDRDATA3CH1_CR_TXPERBITRANK3_Lane0_OFF ( 0) + #define DDRDATA3CH1_CR_TXPERBITRANK3_Lane0_WID ( 4) + #define DDRDATA3CH1_CR_TXPERBITRANK3_Lane0_MSK (0x0000000F) + #define DDRDATA3CH1_CR_TXPERBITRANK3_Lane0_MAX (0x0000000F) + #define DDRDATA3CH1_CR_TXPERBITRANK3_Lane1_OFF ( 4) + #define DDRDATA3CH1_CR_TXPERBITRANK3_Lane1_WID ( 4) + #define DDRDATA3CH1_CR_TXPERBITRANK3_Lane1_MSK (0x000000F0) + #define DDRDATA3CH1_CR_TXPERBITRANK3_Lane1_MAX (0x0000000F) + #define DDRDATA3CH1_CR_TXPERBITRANK3_Lane2_OFF ( 8) + #define DDRDATA3CH1_CR_TXPERBITRANK3_Lane2_WID ( 4) + #define DDRDATA3CH1_CR_TXPERBITRANK3_Lane2_MSK (0x00000F00) + #define DDRDATA3CH1_CR_TXPERBITRANK3_Lane2_MAX (0x0000000F) + #define DDRDATA3CH1_CR_TXPERBITRANK3_Lane3_OFF (12) + #define DDRDATA3CH1_CR_TXPERBITRANK3_Lane3_WID ( 4) + #define DDRDATA3CH1_CR_TXPERBITRANK3_Lane3_MSK (0x0000F000) + #define DDRDATA3CH1_CR_TXPERBITRANK3_Lane3_MAX (0x0000000F) + #define DDRDATA3CH1_CR_TXPERBITRANK3_Lane4_OFF (16) + #define DDRDATA3CH1_CR_TXPERBITRANK3_Lane4_WID ( 4) + #define DDRDATA3CH1_CR_TXPERBITRANK3_Lane4_MSK (0x000F0000) + #define DDRDATA3CH1_CR_TXPERBITRANK3_Lane4_MAX (0x0000000F) + #define DDRDATA3CH1_CR_TXPERBITRANK3_Lane5_OFF (20) + #define DDRDATA3CH1_CR_TXPERBITRANK3_Lane5_WID ( 4) + #define DDRDATA3CH1_CR_TXPERBITRANK3_Lane5_MSK (0x00F00000) + #define DDRDATA3CH1_CR_TXPERBITRANK3_Lane5_MAX (0x0000000F) + #define DDRDATA3CH1_CR_TXPERBITRANK3_Lane6_OFF (24) + #define DDRDATA3CH1_CR_TXPERBITRANK3_Lane6_WID ( 4) + #define DDRDATA3CH1_CR_TXPERBITRANK3_Lane6_MSK (0x0F000000) + #define DDRDATA3CH1_CR_TXPERBITRANK3_Lane6_MAX (0x0000000F) + #define DDRDATA3CH1_CR_TXPERBITRANK3_Lane7_OFF (28) + #define DDRDATA3CH1_CR_TXPERBITRANK3_Lane7_WID ( 4) + #define DDRDATA3CH1_CR_TXPERBITRANK3_Lane7_MSK (0xF0000000) + #define DDRDATA3CH1_CR_TXPERBITRANK3_Lane7_MAX (0x0000000F) + +#define DDRDATA3CH1_CR_RCOMPDATA0_REG (0x00000740) + #define DDRDATA3CH1_CR_RCOMPDATA0_RcompDrvUp_OFF ( 0) + #define DDRDATA3CH1_CR_RCOMPDATA0_RcompDrvUp_WID ( 6) + #define DDRDATA3CH1_CR_RCOMPDATA0_RcompDrvUp_MSK (0x0000003F) + #define DDRDATA3CH1_CR_RCOMPDATA0_RcompDrvUp_MAX (0x0000003F) + #define DDRDATA3CH1_CR_RCOMPDATA0_Spare0_OFF ( 6) + #define DDRDATA3CH1_CR_RCOMPDATA0_Spare0_WID ( 3) + #define DDRDATA3CH1_CR_RCOMPDATA0_Spare0_MSK (0x000001C0) + #define DDRDATA3CH1_CR_RCOMPDATA0_Spare0_MAX (0x00000007) + #define DDRDATA3CH1_CR_RCOMPDATA0_RcompDrvDown_OFF ( 9) + #define DDRDATA3CH1_CR_RCOMPDATA0_RcompDrvDown_WID ( 6) + #define DDRDATA3CH1_CR_RCOMPDATA0_RcompDrvDown_MSK (0x00007E00) + #define DDRDATA3CH1_CR_RCOMPDATA0_RcompDrvDown_MAX (0x0000003F) + #define DDRDATA3CH1_CR_RCOMPDATA0_VTComp_OFF (15) + #define DDRDATA3CH1_CR_RCOMPDATA0_VTComp_WID ( 5) + #define DDRDATA3CH1_CR_RCOMPDATA0_VTComp_MSK (0x000F8000) + #define DDRDATA3CH1_CR_RCOMPDATA0_VTComp_MAX (0x0000001F) + #define DDRDATA3CH1_CR_RCOMPDATA0_TcoComp_OFF (20) + #define DDRDATA3CH1_CR_RCOMPDATA0_TcoComp_WID ( 6) + #define DDRDATA3CH1_CR_RCOMPDATA0_TcoComp_MSK (0x03F00000) + #define DDRDATA3CH1_CR_RCOMPDATA0_TcoComp_MAX (0x0000003F) + #define DDRDATA3CH1_CR_RCOMPDATA0_SlewRateComp_OFF (26) + #define DDRDATA3CH1_CR_RCOMPDATA0_SlewRateComp_WID ( 5) + #define DDRDATA3CH1_CR_RCOMPDATA0_SlewRateComp_MSK (0x7C000000) + #define DDRDATA3CH1_CR_RCOMPDATA0_SlewRateComp_MAX (0x0000001F) + #define DDRDATA3CH1_CR_RCOMPDATA0_Spare2_OFF (31) + #define DDRDATA3CH1_CR_RCOMPDATA0_Spare2_WID ( 1) + #define DDRDATA3CH1_CR_RCOMPDATA0_Spare2_MSK (0x80000000) + #define DDRDATA3CH1_CR_RCOMPDATA0_Spare2_MAX (0x00000001) + +#define DDRDATA3CH1_CR_RCOMPDATA1_REG (0x00000744) + #define DDRDATA3CH1_CR_RCOMPDATA1_RcompOdtUp_OFF ( 0) + #define DDRDATA3CH1_CR_RCOMPDATA1_RcompOdtUp_WID ( 6) + #define DDRDATA3CH1_CR_RCOMPDATA1_RcompOdtUp_MSK (0x0000003F) + #define DDRDATA3CH1_CR_RCOMPDATA1_RcompOdtUp_MAX (0x0000003F) + #define DDRDATA3CH1_CR_RCOMPDATA1_Spare0_OFF ( 6) + #define DDRDATA3CH1_CR_RCOMPDATA1_Spare0_WID ( 3) + #define DDRDATA3CH1_CR_RCOMPDATA1_Spare0_MSK (0x000001C0) + #define DDRDATA3CH1_CR_RCOMPDATA1_Spare0_MAX (0x00000007) + #define DDRDATA3CH1_CR_RCOMPDATA1_RcompOdtDown_OFF ( 9) + #define DDRDATA3CH1_CR_RCOMPDATA1_RcompOdtDown_WID ( 6) + #define DDRDATA3CH1_CR_RCOMPDATA1_RcompOdtDown_MSK (0x00007E00) + #define DDRDATA3CH1_CR_RCOMPDATA1_RcompOdtDown_MAX (0x0000003F) + #define DDRDATA3CH1_CR_RCOMPDATA1_Spare1_OFF (15) + #define DDRDATA3CH1_CR_RCOMPDATA1_Spare1_WID ( 1) + #define DDRDATA3CH1_CR_RCOMPDATA1_Spare1_MSK (0x00008000) + #define DDRDATA3CH1_CR_RCOMPDATA1_Spare1_MAX (0x00000001) + #define DDRDATA3CH1_CR_RCOMPDATA1_PanicDrvDn_OFF (16) + #define DDRDATA3CH1_CR_RCOMPDATA1_PanicDrvDn_WID ( 6) + #define DDRDATA3CH1_CR_RCOMPDATA1_PanicDrvDn_MSK (0x003F0000) + #define DDRDATA3CH1_CR_RCOMPDATA1_PanicDrvDn_MAX (0x0000003F) + #define DDRDATA3CH1_CR_RCOMPDATA1_PanicDrvUp_OFF (22) + #define DDRDATA3CH1_CR_RCOMPDATA1_PanicDrvUp_WID ( 6) + #define DDRDATA3CH1_CR_RCOMPDATA1_PanicDrvUp_MSK (0x0FC00000) + #define DDRDATA3CH1_CR_RCOMPDATA1_PanicDrvUp_MAX (0x0000003F) + #define DDRDATA3CH1_CR_RCOMPDATA1_LevelShifterComp_OFF (28) + #define DDRDATA3CH1_CR_RCOMPDATA1_LevelShifterComp_WID ( 3) + #define DDRDATA3CH1_CR_RCOMPDATA1_LevelShifterComp_MSK (0x70000000) + #define DDRDATA3CH1_CR_RCOMPDATA1_LevelShifterComp_MAX (0x00000007) + #define DDRDATA3CH1_CR_RCOMPDATA1_Spare2_OFF (31) + #define DDRDATA3CH1_CR_RCOMPDATA1_Spare2_WID ( 1) + #define DDRDATA3CH1_CR_RCOMPDATA1_Spare2_MSK (0x80000000) + #define DDRDATA3CH1_CR_RCOMPDATA1_Spare2_MAX (0x00000001) + +#define DDRDATA3CH1_CR_TXXTALK_REG (0x00000748) + #define DDRDATA3CH1_CR_TXXTALK_Lane0_OFF ( 0) + #define DDRDATA3CH1_CR_TXXTALK_Lane0_WID ( 4) + #define DDRDATA3CH1_CR_TXXTALK_Lane0_MSK (0x0000000F) + #define DDRDATA3CH1_CR_TXXTALK_Lane0_MAX (0x0000000F) + #define DDRDATA3CH1_CR_TXXTALK_Lane1_OFF ( 4) + #define DDRDATA3CH1_CR_TXXTALK_Lane1_WID ( 4) + #define DDRDATA3CH1_CR_TXXTALK_Lane1_MSK (0x000000F0) + #define DDRDATA3CH1_CR_TXXTALK_Lane1_MAX (0x0000000F) + #define DDRDATA3CH1_CR_TXXTALK_Lane2_OFF ( 8) + #define DDRDATA3CH1_CR_TXXTALK_Lane2_WID ( 4) + #define DDRDATA3CH1_CR_TXXTALK_Lane2_MSK (0x00000F00) + #define DDRDATA3CH1_CR_TXXTALK_Lane2_MAX (0x0000000F) + #define DDRDATA3CH1_CR_TXXTALK_Lane3_OFF (12) + #define DDRDATA3CH1_CR_TXXTALK_Lane3_WID ( 4) + #define DDRDATA3CH1_CR_TXXTALK_Lane3_MSK (0x0000F000) + #define DDRDATA3CH1_CR_TXXTALK_Lane3_MAX (0x0000000F) + #define DDRDATA3CH1_CR_TXXTALK_Lane4_OFF (16) + #define DDRDATA3CH1_CR_TXXTALK_Lane4_WID ( 4) + #define DDRDATA3CH1_CR_TXXTALK_Lane4_MSK (0x000F0000) + #define DDRDATA3CH1_CR_TXXTALK_Lane4_MAX (0x0000000F) + #define DDRDATA3CH1_CR_TXXTALK_Lane5_OFF (20) + #define DDRDATA3CH1_CR_TXXTALK_Lane5_WID ( 4) + #define DDRDATA3CH1_CR_TXXTALK_Lane5_MSK (0x00F00000) + #define DDRDATA3CH1_CR_TXXTALK_Lane5_MAX (0x0000000F) + #define DDRDATA3CH1_CR_TXXTALK_Lane6_OFF (24) + #define DDRDATA3CH1_CR_TXXTALK_Lane6_WID ( 4) + #define DDRDATA3CH1_CR_TXXTALK_Lane6_MSK (0x0F000000) + #define DDRDATA3CH1_CR_TXXTALK_Lane6_MAX (0x0000000F) + #define DDRDATA3CH1_CR_TXXTALK_Lane7_OFF (28) + #define DDRDATA3CH1_CR_TXXTALK_Lane7_WID ( 4) + #define DDRDATA3CH1_CR_TXXTALK_Lane7_MSK (0xF0000000) + #define DDRDATA3CH1_CR_TXXTALK_Lane7_MAX (0x0000000F) + +#define DDRDATA3CH1_CR_RXOFFSETVDQ_REG (0x0000074C) + #define DDRDATA3CH1_CR_RXOFFSETVDQ_Lane0_OFF ( 0) + #define DDRDATA3CH1_CR_RXOFFSETVDQ_Lane0_WID ( 4) + #define DDRDATA3CH1_CR_RXOFFSETVDQ_Lane0_MSK (0x0000000F) + #define DDRDATA3CH1_CR_RXOFFSETVDQ_Lane0_MAX (0x0000000F) + #define DDRDATA3CH1_CR_RXOFFSETVDQ_Lane1_OFF ( 4) + #define DDRDATA3CH1_CR_RXOFFSETVDQ_Lane1_WID ( 4) + #define DDRDATA3CH1_CR_RXOFFSETVDQ_Lane1_MSK (0x000000F0) + #define DDRDATA3CH1_CR_RXOFFSETVDQ_Lane1_MAX (0x0000000F) + #define DDRDATA3CH1_CR_RXOFFSETVDQ_Lane2_OFF ( 8) + #define DDRDATA3CH1_CR_RXOFFSETVDQ_Lane2_WID ( 4) + #define DDRDATA3CH1_CR_RXOFFSETVDQ_Lane2_MSK (0x00000F00) + #define DDRDATA3CH1_CR_RXOFFSETVDQ_Lane2_MAX (0x0000000F) + #define DDRDATA3CH1_CR_RXOFFSETVDQ_Lane3_OFF (12) + #define DDRDATA3CH1_CR_RXOFFSETVDQ_Lane3_WID ( 4) + #define DDRDATA3CH1_CR_RXOFFSETVDQ_Lane3_MSK (0x0000F000) + #define DDRDATA3CH1_CR_RXOFFSETVDQ_Lane3_MAX (0x0000000F) + #define DDRDATA3CH1_CR_RXOFFSETVDQ_Lane4_OFF (16) + #define DDRDATA3CH1_CR_RXOFFSETVDQ_Lane4_WID ( 4) + #define DDRDATA3CH1_CR_RXOFFSETVDQ_Lane4_MSK (0x000F0000) + #define DDRDATA3CH1_CR_RXOFFSETVDQ_Lane4_MAX (0x0000000F) + #define DDRDATA3CH1_CR_RXOFFSETVDQ_Lane5_OFF (20) + #define DDRDATA3CH1_CR_RXOFFSETVDQ_Lane5_WID ( 4) + #define DDRDATA3CH1_CR_RXOFFSETVDQ_Lane5_MSK (0x00F00000) + #define DDRDATA3CH1_CR_RXOFFSETVDQ_Lane5_MAX (0x0000000F) + #define DDRDATA3CH1_CR_RXOFFSETVDQ_Lane6_OFF (24) + #define DDRDATA3CH1_CR_RXOFFSETVDQ_Lane6_WID ( 4) + #define DDRDATA3CH1_CR_RXOFFSETVDQ_Lane6_MSK (0x0F000000) + #define DDRDATA3CH1_CR_RXOFFSETVDQ_Lane6_MAX (0x0000000F) + #define DDRDATA3CH1_CR_RXOFFSETVDQ_Lane7_OFF (28) + #define DDRDATA3CH1_CR_RXOFFSETVDQ_Lane7_WID ( 4) + #define DDRDATA3CH1_CR_RXOFFSETVDQ_Lane7_MSK (0xF0000000) + #define DDRDATA3CH1_CR_RXOFFSETVDQ_Lane7_MAX (0x0000000F) + +#define DDRDATA3CH1_CR_DDRDATARESERVED_REG (0x00000750) + #define DDRDATA3CH1_CR_DDRDATARESERVED_Spare_OFF ( 0) + #define DDRDATA3CH1_CR_DDRDATARESERVED_Spare_WID (32) + #define DDRDATA3CH1_CR_DDRDATARESERVED_Spare_MSK (0xFFFFFFFF) + #define DDRDATA3CH1_CR_DDRDATARESERVED_Spare_MAX (0xFFFFFFFF) + +#define DDRDATA3CH1_CR_DATATRAINFEEDBACK_REG (0x00000754) + #define DDRDATA3CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_OFF ( 0) + #define DDRDATA3CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_WID ( 9) + #define DDRDATA3CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_MSK (0x000001FF) + #define DDRDATA3CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_MAX (0x000001FF) + #define DDRDATA3CH1_CR_DATATRAINFEEDBACK_Spare_OFF ( 9) + #define DDRDATA3CH1_CR_DATATRAINFEEDBACK_Spare_WID (23) + #define DDRDATA3CH1_CR_DATATRAINFEEDBACK_Spare_MSK (0xFFFFFE00) + #define DDRDATA3CH1_CR_DATATRAINFEEDBACK_Spare_MAX (0x007FFFFF) + +#define DDRDATA3CH1_CR_DLLPITESTANDADC_REG (0x00000758) + #define DDRDATA3CH1_CR_DLLPITESTANDADC_RunTest_OFF ( 0) + #define DDRDATA3CH1_CR_DLLPITESTANDADC_RunTest_WID ( 1) + #define DDRDATA3CH1_CR_DLLPITESTANDADC_RunTest_MSK (0x00000001) + #define DDRDATA3CH1_CR_DLLPITESTANDADC_RunTest_MAX (0x00000001) + #define DDRDATA3CH1_CR_DLLPITESTANDADC_RunTest_DEF (0x00000000) + #define DDRDATA3CH1_CR_DLLPITESTANDADC_Load_OFF ( 1) + #define DDRDATA3CH1_CR_DLLPITESTANDADC_Load_WID ( 1) + #define DDRDATA3CH1_CR_DLLPITESTANDADC_Load_MSK (0x00000002) + #define DDRDATA3CH1_CR_DLLPITESTANDADC_Load_MAX (0x00000001) + #define DDRDATA3CH1_CR_DLLPITESTANDADC_Load_DEF (0x00000000) + #define DDRDATA3CH1_CR_DLLPITESTANDADC_ModeHVM_OFF ( 2) + #define DDRDATA3CH1_CR_DLLPITESTANDADC_ModeHVM_WID ( 1) + #define DDRDATA3CH1_CR_DLLPITESTANDADC_ModeHVM_MSK (0x00000004) + #define DDRDATA3CH1_CR_DLLPITESTANDADC_ModeHVM_MAX (0x00000001) + #define DDRDATA3CH1_CR_DLLPITESTANDADC_ModeHVM_DEF (0x00000000) + #define DDRDATA3CH1_CR_DLLPITESTANDADC_ModeDV_OFF ( 3) + #define DDRDATA3CH1_CR_DLLPITESTANDADC_ModeDV_WID ( 1) + #define DDRDATA3CH1_CR_DLLPITESTANDADC_ModeDV_MSK (0x00000008) + #define DDRDATA3CH1_CR_DLLPITESTANDADC_ModeDV_MAX (0x00000001) + #define DDRDATA3CH1_CR_DLLPITESTANDADC_ModeDV_DEF (0x00000000) + #define DDRDATA3CH1_CR_DLLPITESTANDADC_ModeADC_OFF ( 4) + #define DDRDATA3CH1_CR_DLLPITESTANDADC_ModeADC_WID ( 1) + #define DDRDATA3CH1_CR_DLLPITESTANDADC_ModeADC_MSK (0x00000010) + #define DDRDATA3CH1_CR_DLLPITESTANDADC_ModeADC_MAX (0x00000001) + #define DDRDATA3CH1_CR_DLLPITESTANDADC_ModeADC_DEF (0x00000000) + #define DDRDATA3CH1_CR_DLLPITESTANDADC_LoadCount_OFF ( 5) + #define DDRDATA3CH1_CR_DLLPITESTANDADC_LoadCount_WID (10) + #define DDRDATA3CH1_CR_DLLPITESTANDADC_LoadCount_MSK (0x00007FE0) + #define DDRDATA3CH1_CR_DLLPITESTANDADC_LoadCount_MAX (0x000003FF) + #define DDRDATA3CH1_CR_DLLPITESTANDADC_CountStatus_OFF (15) + #define DDRDATA3CH1_CR_DLLPITESTANDADC_CountStatus_WID (10) + #define DDRDATA3CH1_CR_DLLPITESTANDADC_CountStatus_MSK (0x01FF8000) + #define DDRDATA3CH1_CR_DLLPITESTANDADC_CountStatus_MAX (0x000003FF) + #define DDRDATA3CH1_CR_DLLPITESTANDADC_CountStatus_DEF (0x00000000) + #define DDRDATA3CH1_CR_DLLPITESTANDADC_Spare_OFF (25) + #define DDRDATA3CH1_CR_DLLPITESTANDADC_Spare_WID ( 7) + #define DDRDATA3CH1_CR_DLLPITESTANDADC_Spare_MSK (0xFE000000) + #define DDRDATA3CH1_CR_DLLPITESTANDADC_Spare_MAX (0x0000007F) + +#define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_REG (0x0000075C) + #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_OFF ( 0) + #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_WID ( 6) + #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MSK (0x0000003F) + #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MAX (0x0000003F) + #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_DEF (0x00000000) + #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_OFF ( 6) + #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_WID ( 6) + #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MSK (0x00000FC0) + #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MAX (0x0000003F) + #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_DEF (0x00000000) + #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_OFF (12) + #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_WID ( 5) + #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MSK (0x0001F000) + #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MAX (0x0000001F) + #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_DEF (0x00000000) + #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_OFF (17) + #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_WID ( 5) + #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MSK (0x003E0000) + #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MAX (0x0000001F) + #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_DEF (0x00000000) + #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_OFF (22) + #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_WID ( 5) + #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_MSK (0x07C00000) + #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_MAX (0x0000001F) + #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_DEF (0x00000000) + #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_OFF (27) + #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_WID ( 5) + #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MSK (0xF8000000) + #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MAX (0x0000001F) + #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_DEF (0x00000000) + +#define DDRDATA3CH1_CR_DDRCRDATACONTROL1_REG (0x00000760) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_RefPi_OFF ( 0) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_RefPi_WID ( 4) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_RefPi_MSK (0x0000000F) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_RefPi_MAX (0x0000000F) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_RefPi_DEF (0x00000000) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_DllMask_OFF ( 4) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_DllMask_WID ( 2) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_DllMask_MSK (0x00000030) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_DllMask_MAX (0x00000003) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_DllMask_DEF (0x00000000) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_DllWeakLock_OFF ( 6) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_DllWeakLock_WID ( 1) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_DllWeakLock_MSK (0x00000040) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_DllWeakLock_MAX (0x00000001) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_DllWeakLock_DEF (0x00000000) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_OFF ( 7) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_WID ( 3) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MSK (0x00000380) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MAX (0x00000007) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_DEF (0x00000000) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_OFF (10) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_WID ( 3) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_MSK (0x00001C00) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_MAX (0x00000007) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_DEF (0x00000000) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_OdtDelay_OFF (13) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_OdtDelay_WID ( 4) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_OdtDelay_MSK (0x0001E000) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_OdtDelay_MAX (0x0000000F) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_OdtDelay_DEF (0x00000000) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_OdtDuration_OFF (17) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_OdtDuration_WID ( 3) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_OdtDuration_MSK (0x000E0000) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_OdtDuration_MAX (0x00000007) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_OdtDuration_DEF (0x00000000) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_OFF (20) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_WID ( 4) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_MSK (0x00F00000) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_MAX (0x0000000F) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_DEF (0x00000000) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_OFF (24) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_WID ( 3) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_MSK (0x07000000) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_MAX (0x00000007) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_DEF (0x00000000) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_OFF (27) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_WID ( 3) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_MSK (0x38000000) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_MAX (0x00000007) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_DEF (0x00000000) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_OFF (30) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_WID ( 1) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_MSK (0x40000000) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_MAX (0x00000001) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_DEF (0x00000000) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_Rsvd1_OFF (31) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_Rsvd1_WID ( 1) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_Rsvd1_MSK (0x80000000) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_Rsvd1_MAX (0x00000001) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_Rsvd1_DEF (0x00000000) + +#define DDRDATA3CH1_CR_DDRCRDATACONTROL2_REG (0x00000764) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_OFF ( 0) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_WID ( 5) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_MSK (0x0000001F) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_MAX (0x0000001F) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_DEF (0x00000000) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_OFF ( 5) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_WID ( 1) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_MSK (0x00000020) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_MAX (0x00000001) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_DEF (0x00000000) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_ForceRxOn_OFF ( 6) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_ForceRxOn_WID ( 1) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_ForceRxOn_MSK (0x00000040) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_ForceRxOn_MAX (0x00000001) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_ForceRxOn_DEF (0x00000000) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_LeakerComp_OFF ( 7) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_LeakerComp_WID ( 2) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_LeakerComp_MSK (0x00000180) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_LeakerComp_MAX (0x00000003) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_LeakerComp_DEF (0x00000000) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_OFF ( 9) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_WID ( 4) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_MSK (0x00001E00) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_MAX (0x0000000F) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_DEF (0x00000008) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_OFF (13) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_WID ( 5) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_MSK (0x0003E000) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_MAX (0x0000001F) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_DEF (0x00000011) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_OFF (18) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_WID ( 1) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_MSK (0x00040000) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_MAX (0x00000001) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_DEF (0x00000000) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_Spare_OFF (19) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_Spare_WID (13) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_Spare_MSK (0xFFF80000) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_Spare_MAX (0x00001FFF) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_Spare_DEF (0x00000000) + +#define DDRDATA3CH1_CR_DDRCRVSSHIORVREFCONTROL_REG (0x0000076C) + #define DDRDATA3CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_OFF ( 0) + #define DDRDATA3CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_WID (24) + #define DDRDATA3CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_MSK (0x00FFFFFF) + #define DDRDATA3CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_MAX (0x00FFFFFF) + #define DDRDATA3CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_DEF (0x00000000) + #define DDRDATA3CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_OFF (24) + #define DDRDATA3CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_WID ( 8) + #define DDRDATA3CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_MSK (0xFF000000) + #define DDRDATA3CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_MAX (0x000000FF) + #define DDRDATA3CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_DEF (0x00000000) + +#define DDRDATA3CH1_CR_DDRCRDATAOFFSETTRAIN_REG (0x00000770) + #define DDRDATA3CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_OFF ( 0) + #define DDRDATA3CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_WID ( 6) + #define DDRDATA3CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MSK (0x0000003F) + #define DDRDATA3CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MAX (0x0000003F) + #define DDRDATA3CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_DEF (0x00000000) + #define DDRDATA3CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_OFF ( 6) + #define DDRDATA3CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_WID ( 6) + #define DDRDATA3CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MSK (0x00000FC0) + #define DDRDATA3CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MAX (0x0000003F) + #define DDRDATA3CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_DEF (0x00000000) + #define DDRDATA3CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_OFF (12) + #define DDRDATA3CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_WID ( 6) + #define DDRDATA3CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MSK (0x0003F000) + #define DDRDATA3CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MAX (0x0000003F) + #define DDRDATA3CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_DEF (0x00000000) + #define DDRDATA3CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_OFF (18) + #define DDRDATA3CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_WID ( 6) + #define DDRDATA3CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MSK (0x00FC0000) + #define DDRDATA3CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MAX (0x0000003F) + #define DDRDATA3CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_DEF (0x00000000) + #define DDRDATA3CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_OFF (24) + #define DDRDATA3CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_WID ( 7) + #define DDRDATA3CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MSK (0x7F000000) + #define DDRDATA3CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MAX (0x0000007F) + #define DDRDATA3CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_DEF (0x00000000) + #define DDRDATA3CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_OFF (31) + #define DDRDATA3CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_WID ( 1) + #define DDRDATA3CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_MSK (0x80000000) + #define DDRDATA3CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_MAX (0x00000001) + #define DDRDATA3CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_DEF (0x00000000) + +#define DDRDATA3CH1_CR_DDRCRDATACONTROL0_REG (0x00000774) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_OFF ( 0) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_WID ( 1) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_MSK (0x00000001) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_MAX (0x00000001) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_DEF (0x00000000) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_OFF ( 1) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_WID ( 1) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_MSK (0x00000002) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_MAX (0x00000001) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_DEF (0x00000000) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_OFF ( 2) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_WID ( 1) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_MSK (0x00000004) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_MAX (0x00000001) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_DEF (0x00000000) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_OFF ( 3) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_WID ( 1) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MSK (0x00000008) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MAX (0x00000001) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_DEF (0x00000000) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_TxOn_OFF ( 4) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_TxOn_WID ( 1) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_TxOn_MSK (0x00000010) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_TxOn_MAX (0x00000001) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_TxOn_DEF (0x00000000) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RfOn_OFF ( 5) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RfOn_WID ( 1) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RfOn_MSK (0x00000020) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RfOn_MAX (0x00000001) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RfOn_DEF (0x00000000) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RxPiOn_OFF ( 6) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RxPiOn_WID ( 1) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RxPiOn_MSK (0x00000040) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RxPiOn_MAX (0x00000001) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RxPiOn_DEF (0x00000000) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_TxPiOn_OFF ( 7) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_TxPiOn_WID ( 1) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_TxPiOn_MSK (0x00000080) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_TxPiOn_MAX (0x00000001) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_TxPiOn_DEF (0x00000000) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_OFF ( 8) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_WID ( 1) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_MSK (0x00000100) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_MAX (0x00000001) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_DEF (0x00000000) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_OFF ( 9) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_WID ( 1) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MSK (0x00000200) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MAX (0x00000001) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_DEF (0x00000000) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_TxDisable_OFF (10) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_TxDisable_WID ( 1) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_TxDisable_MSK (0x00000400) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_TxDisable_MAX (0x00000001) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_TxDisable_DEF (0x00000000) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RxDisable_OFF (11) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RxDisable_WID ( 1) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RxDisable_MSK (0x00000800) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RxDisable_MAX (0x00000001) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RxDisable_DEF (0x00000000) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_TxLong_OFF (12) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_TxLong_WID ( 1) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_TxLong_MSK (0x00001000) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_TxLong_MAX (0x00000001) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_TxLong_DEF (0x00000000) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_OFF (13) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_WID ( 2) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_MSK (0x00006000) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_MAX (0x00000003) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_DEF (0x00000000) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RxReadPointer_OFF (15) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RxReadPointer_WID ( 3) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RxReadPointer_MSK (0x00038000) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RxReadPointer_MAX (0x00000007) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RxReadPointer_DEF (0x00000000) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_OFF (18) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_WID ( 1) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_MSK (0x00040000) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_MAX (0x00000001) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_DEF (0x00000000) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_OFF (19) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_WID ( 1) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_MSK (0x00080000) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_MAX (0x00000001) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_DEF (0x00000000) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_ReadRFRd_OFF (20) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_ReadRFRd_WID ( 1) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_ReadRFRd_MSK (0x00100000) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_ReadRFRd_MAX (0x00000001) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_ReadRFRd_DEF (0x00000000) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_ReadRFWr_OFF (21) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_ReadRFWr_WID ( 1) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_ReadRFWr_MSK (0x00200000) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_ReadRFWr_MAX (0x00000001) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_ReadRFWr_DEF (0x00000000) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_ReadRFRank_OFF (22) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_ReadRFRank_WID ( 2) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_ReadRFRank_MSK (0x00C00000) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_ReadRFRank_MAX (0x00000003) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_ReadRFRank_DEF (0x00000000) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_OFF (24) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_WID ( 1) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_MSK (0x01000000) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_MAX (0x00000001) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_DEF (0x00000000) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_OdtSampOff_OFF (25) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_OdtSampOff_WID ( 1) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_OdtSampOff_MSK (0x02000000) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_OdtSampOff_MAX (0x00000001) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_OdtSampOff_DEF (0x00000000) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_OFF (26) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_WID ( 1) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_MSK (0x04000000) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_MAX (0x00000001) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_DEF (0x00000000) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_OFF (27) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_WID ( 1) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MSK (0x08000000) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MAX (0x00000001) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_DEF (0x00000000) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_OFF (28) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_WID ( 1) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_MSK (0x10000000) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_MAX (0x00000001) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_DEF (0x00000000) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_OFF (29) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_WID ( 1) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_MSK (0x20000000) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_MAX (0x00000001) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_DEF (0x00000000) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_OFF (30) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_WID ( 1) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MSK (0x40000000) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MAX (0x00000001) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_DEF (0x00000000) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_OFF (31) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_WID ( 1) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_MSK (0x80000000) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_MAX (0x00000001) + #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_DEF (0x00000000) + +#define DDRDATA3CH1_CR_DDRCRVREFADJUST1_REG (0x00000778) + #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_OFF ( 0) + #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_WID ( 7) + #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_MSK (0x0000007F) + #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_MAX (0x0000007F) + #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_DEF (0x00000000) + #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_OFF ( 7) + #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_WID ( 7) + #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_MSK (0x00003F80) + #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_MAX (0x0000007F) + #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_DEF (0x00000000) + #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_OFF (14) + #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_WID ( 7) + #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_MSK (0x001FC000) + #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_MAX (0x0000007F) + #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_DEF (0x00000000) + #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_OFF (21) + #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_WID ( 1) + #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_MSK (0x00200000) + #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_MAX (0x00000001) + #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_DEF (0x00000000) + #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_OFF (22) + #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_WID ( 1) + #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_MSK (0x00400000) + #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_MAX (0x00000001) + #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_DEF (0x00000000) + #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_OFF (23) + #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_WID ( 1) + #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_MSK (0x00800000) + #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_MAX (0x00000001) + #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_DEF (0x00000000) + #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_OFF (24) + #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_WID ( 2) + #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_MSK (0x03000000) + #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_MAX (0x00000003) + #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_DEF (0x00000000) + #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_OFF (26) + #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_WID ( 1) + #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_MSK (0x04000000) + #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_MAX (0x00000001) + #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_DEF (0x00000000) + #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_Rsvd_OFF (27) + #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_Rsvd_WID ( 2) + #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_Rsvd_MSK (0x18000000) + #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_Rsvd_MAX (0x00000003) + #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_Rsvd_DEF (0x00000000) + #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_caSlowBW_OFF (29) + #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_caSlowBW_WID ( 1) + #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_caSlowBW_MSK (0x20000000) + #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_caSlowBW_MAX (0x00000001) + #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_caSlowBW_DEF (0x00000000) + #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_OFF (30) + #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_WID ( 1) + #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_MSK (0x40000000) + #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_MAX (0x00000001) + #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_DEF (0x00000000) + #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_OFF (31) + #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_WID ( 1) + #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_MSK (0x80000000) + #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_MAX (0x00000001) + #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_DEF (0x00000000) + +#define DDRDATA4CH0_CR_RXTRAINRANK0_REG (0x00000800) + #define DDRDATA4CH0_CR_RXTRAINRANK0_RxRcvEnPi_OFF ( 0) + #define DDRDATA4CH0_CR_RXTRAINRANK0_RxRcvEnPi_WID ( 9) + #define DDRDATA4CH0_CR_RXTRAINRANK0_RxRcvEnPi_MSK (0x000001FF) + #define DDRDATA4CH0_CR_RXTRAINRANK0_RxRcvEnPi_MAX (0x000001FF) + #define DDRDATA4CH0_CR_RXTRAINRANK0_RxDqsPPi_OFF ( 9) + #define DDRDATA4CH0_CR_RXTRAINRANK0_RxDqsPPi_WID ( 6) + #define DDRDATA4CH0_CR_RXTRAINRANK0_RxDqsPPi_MSK (0x00007E00) + #define DDRDATA4CH0_CR_RXTRAINRANK0_RxDqsPPi_MAX (0x0000003F) + #define DDRDATA4CH0_CR_RXTRAINRANK0_RxEq_OFF (15) + #define DDRDATA4CH0_CR_RXTRAINRANK0_RxEq_WID ( 5) + #define DDRDATA4CH0_CR_RXTRAINRANK0_RxEq_MSK (0x000F8000) + #define DDRDATA4CH0_CR_RXTRAINRANK0_RxEq_MAX (0x0000001F) + #define DDRDATA4CH0_CR_RXTRAINRANK0_RxDqsNPi_OFF (20) + #define DDRDATA4CH0_CR_RXTRAINRANK0_RxDqsNPi_WID ( 6) + #define DDRDATA4CH0_CR_RXTRAINRANK0_RxDqsNPi_MSK (0x03F00000) + #define DDRDATA4CH0_CR_RXTRAINRANK0_RxDqsNPi_MAX (0x0000003F) + #define DDRDATA4CH0_CR_RXTRAINRANK0_RxVref_OFF (26) + #define DDRDATA4CH0_CR_RXTRAINRANK0_RxVref_WID ( 6) + #define DDRDATA4CH0_CR_RXTRAINRANK0_RxVref_MSK (0xFC000000) + #define DDRDATA4CH0_CR_RXTRAINRANK0_RxVref_MAX (0x0000003F) + +#define DDRDATA4CH0_CR_RXTRAINRANK1_REG (0x00000804) + #define DDRDATA4CH0_CR_RXTRAINRANK1_RxRcvEnPi_OFF ( 0) + #define DDRDATA4CH0_CR_RXTRAINRANK1_RxRcvEnPi_WID ( 9) + #define DDRDATA4CH0_CR_RXTRAINRANK1_RxRcvEnPi_MSK (0x000001FF) + #define DDRDATA4CH0_CR_RXTRAINRANK1_RxRcvEnPi_MAX (0x000001FF) + #define DDRDATA4CH0_CR_RXTRAINRANK1_RxDqsPPi_OFF ( 9) + #define DDRDATA4CH0_CR_RXTRAINRANK1_RxDqsPPi_WID ( 6) + #define DDRDATA4CH0_CR_RXTRAINRANK1_RxDqsPPi_MSK (0x00007E00) + #define DDRDATA4CH0_CR_RXTRAINRANK1_RxDqsPPi_MAX (0x0000003F) + #define DDRDATA4CH0_CR_RXTRAINRANK1_RxEq_OFF (15) + #define DDRDATA4CH0_CR_RXTRAINRANK1_RxEq_WID ( 5) + #define DDRDATA4CH0_CR_RXTRAINRANK1_RxEq_MSK (0x000F8000) + #define DDRDATA4CH0_CR_RXTRAINRANK1_RxEq_MAX (0x0000001F) + #define DDRDATA4CH0_CR_RXTRAINRANK1_RxDqsNPi_OFF (20) + #define DDRDATA4CH0_CR_RXTRAINRANK1_RxDqsNPi_WID ( 6) + #define DDRDATA4CH0_CR_RXTRAINRANK1_RxDqsNPi_MSK (0x03F00000) + #define DDRDATA4CH0_CR_RXTRAINRANK1_RxDqsNPi_MAX (0x0000003F) + #define DDRDATA4CH0_CR_RXTRAINRANK1_RxVref_OFF (26) + #define DDRDATA4CH0_CR_RXTRAINRANK1_RxVref_WID ( 6) + #define DDRDATA4CH0_CR_RXTRAINRANK1_RxVref_MSK (0xFC000000) + #define DDRDATA4CH0_CR_RXTRAINRANK1_RxVref_MAX (0x0000003F) + +#define DDRDATA4CH0_CR_RXTRAINRANK2_REG (0x00000808) + #define DDRDATA4CH0_CR_RXTRAINRANK2_RxRcvEnPi_OFF ( 0) + #define DDRDATA4CH0_CR_RXTRAINRANK2_RxRcvEnPi_WID ( 9) + #define DDRDATA4CH0_CR_RXTRAINRANK2_RxRcvEnPi_MSK (0x000001FF) + #define DDRDATA4CH0_CR_RXTRAINRANK2_RxRcvEnPi_MAX (0x000001FF) + #define DDRDATA4CH0_CR_RXTRAINRANK2_RxDqsPPi_OFF ( 9) + #define DDRDATA4CH0_CR_RXTRAINRANK2_RxDqsPPi_WID ( 6) + #define DDRDATA4CH0_CR_RXTRAINRANK2_RxDqsPPi_MSK (0x00007E00) + #define DDRDATA4CH0_CR_RXTRAINRANK2_RxDqsPPi_MAX (0x0000003F) + #define DDRDATA4CH0_CR_RXTRAINRANK2_RxEq_OFF (15) + #define DDRDATA4CH0_CR_RXTRAINRANK2_RxEq_WID ( 5) + #define DDRDATA4CH0_CR_RXTRAINRANK2_RxEq_MSK (0x000F8000) + #define DDRDATA4CH0_CR_RXTRAINRANK2_RxEq_MAX (0x0000001F) + #define DDRDATA4CH0_CR_RXTRAINRANK2_RxDqsNPi_OFF (20) + #define DDRDATA4CH0_CR_RXTRAINRANK2_RxDqsNPi_WID ( 6) + #define DDRDATA4CH0_CR_RXTRAINRANK2_RxDqsNPi_MSK (0x03F00000) + #define DDRDATA4CH0_CR_RXTRAINRANK2_RxDqsNPi_MAX (0x0000003F) + #define DDRDATA4CH0_CR_RXTRAINRANK2_RxVref_OFF (26) + #define DDRDATA4CH0_CR_RXTRAINRANK2_RxVref_WID ( 6) + #define DDRDATA4CH0_CR_RXTRAINRANK2_RxVref_MSK (0xFC000000) + #define DDRDATA4CH0_CR_RXTRAINRANK2_RxVref_MAX (0x0000003F) + +#define DDRDATA4CH0_CR_RXTRAINRANK3_REG (0x0000080C) + #define DDRDATA4CH0_CR_RXTRAINRANK3_RxRcvEnPi_OFF ( 0) + #define DDRDATA4CH0_CR_RXTRAINRANK3_RxRcvEnPi_WID ( 9) + #define DDRDATA4CH0_CR_RXTRAINRANK3_RxRcvEnPi_MSK (0x000001FF) + #define DDRDATA4CH0_CR_RXTRAINRANK3_RxRcvEnPi_MAX (0x000001FF) + #define DDRDATA4CH0_CR_RXTRAINRANK3_RxDqsPPi_OFF ( 9) + #define DDRDATA4CH0_CR_RXTRAINRANK3_RxDqsPPi_WID ( 6) + #define DDRDATA4CH0_CR_RXTRAINRANK3_RxDqsPPi_MSK (0x00007E00) + #define DDRDATA4CH0_CR_RXTRAINRANK3_RxDqsPPi_MAX (0x0000003F) + #define DDRDATA4CH0_CR_RXTRAINRANK3_RxEq_OFF (15) + #define DDRDATA4CH0_CR_RXTRAINRANK3_RxEq_WID ( 5) + #define DDRDATA4CH0_CR_RXTRAINRANK3_RxEq_MSK (0x000F8000) + #define DDRDATA4CH0_CR_RXTRAINRANK3_RxEq_MAX (0x0000001F) + #define DDRDATA4CH0_CR_RXTRAINRANK3_RxDqsNPi_OFF (20) + #define DDRDATA4CH0_CR_RXTRAINRANK3_RxDqsNPi_WID ( 6) + #define DDRDATA4CH0_CR_RXTRAINRANK3_RxDqsNPi_MSK (0x03F00000) + #define DDRDATA4CH0_CR_RXTRAINRANK3_RxDqsNPi_MAX (0x0000003F) + #define DDRDATA4CH0_CR_RXTRAINRANK3_RxVref_OFF (26) + #define DDRDATA4CH0_CR_RXTRAINRANK3_RxVref_WID ( 6) + #define DDRDATA4CH0_CR_RXTRAINRANK3_RxVref_MSK (0xFC000000) + #define DDRDATA4CH0_CR_RXTRAINRANK3_RxVref_MAX (0x0000003F) + +#define DDRDATA4CH0_CR_RXPERBITRANK0_REG (0x00000810) + #define DDRDATA4CH0_CR_RXPERBITRANK0_Lane0_OFF ( 0) + #define DDRDATA4CH0_CR_RXPERBITRANK0_Lane0_WID ( 4) + #define DDRDATA4CH0_CR_RXPERBITRANK0_Lane0_MSK (0x0000000F) + #define DDRDATA4CH0_CR_RXPERBITRANK0_Lane0_MAX (0x0000000F) + #define DDRDATA4CH0_CR_RXPERBITRANK0_Lane1_OFF ( 4) + #define DDRDATA4CH0_CR_RXPERBITRANK0_Lane1_WID ( 4) + #define DDRDATA4CH0_CR_RXPERBITRANK0_Lane1_MSK (0x000000F0) + #define DDRDATA4CH0_CR_RXPERBITRANK0_Lane1_MAX (0x0000000F) + #define DDRDATA4CH0_CR_RXPERBITRANK0_Lane2_OFF ( 8) + #define DDRDATA4CH0_CR_RXPERBITRANK0_Lane2_WID ( 4) + #define DDRDATA4CH0_CR_RXPERBITRANK0_Lane2_MSK (0x00000F00) + #define DDRDATA4CH0_CR_RXPERBITRANK0_Lane2_MAX (0x0000000F) + #define DDRDATA4CH0_CR_RXPERBITRANK0_Lane3_OFF (12) + #define DDRDATA4CH0_CR_RXPERBITRANK0_Lane3_WID ( 4) + #define DDRDATA4CH0_CR_RXPERBITRANK0_Lane3_MSK (0x0000F000) + #define DDRDATA4CH0_CR_RXPERBITRANK0_Lane3_MAX (0x0000000F) + #define DDRDATA4CH0_CR_RXPERBITRANK0_Lane4_OFF (16) + #define DDRDATA4CH0_CR_RXPERBITRANK0_Lane4_WID ( 4) + #define DDRDATA4CH0_CR_RXPERBITRANK0_Lane4_MSK (0x000F0000) + #define DDRDATA4CH0_CR_RXPERBITRANK0_Lane4_MAX (0x0000000F) + #define DDRDATA4CH0_CR_RXPERBITRANK0_Lane5_OFF (20) + #define DDRDATA4CH0_CR_RXPERBITRANK0_Lane5_WID ( 4) + #define DDRDATA4CH0_CR_RXPERBITRANK0_Lane5_MSK (0x00F00000) + #define DDRDATA4CH0_CR_RXPERBITRANK0_Lane5_MAX (0x0000000F) + #define DDRDATA4CH0_CR_RXPERBITRANK0_Lane6_OFF (24) + #define DDRDATA4CH0_CR_RXPERBITRANK0_Lane6_WID ( 4) + #define DDRDATA4CH0_CR_RXPERBITRANK0_Lane6_MSK (0x0F000000) + #define DDRDATA4CH0_CR_RXPERBITRANK0_Lane6_MAX (0x0000000F) + #define DDRDATA4CH0_CR_RXPERBITRANK0_Lane7_OFF (28) + #define DDRDATA4CH0_CR_RXPERBITRANK0_Lane7_WID ( 4) + #define DDRDATA4CH0_CR_RXPERBITRANK0_Lane7_MSK (0xF0000000) + #define DDRDATA4CH0_CR_RXPERBITRANK0_Lane7_MAX (0x0000000F) + +#define DDRDATA4CH0_CR_RXPERBITRANK1_REG (0x00000814) + #define DDRDATA4CH0_CR_RXPERBITRANK1_Lane0_OFF ( 0) + #define DDRDATA4CH0_CR_RXPERBITRANK1_Lane0_WID ( 4) + #define DDRDATA4CH0_CR_RXPERBITRANK1_Lane0_MSK (0x0000000F) + #define DDRDATA4CH0_CR_RXPERBITRANK1_Lane0_MAX (0x0000000F) + #define DDRDATA4CH0_CR_RXPERBITRANK1_Lane1_OFF ( 4) + #define DDRDATA4CH0_CR_RXPERBITRANK1_Lane1_WID ( 4) + #define DDRDATA4CH0_CR_RXPERBITRANK1_Lane1_MSK (0x000000F0) + #define DDRDATA4CH0_CR_RXPERBITRANK1_Lane1_MAX (0x0000000F) + #define DDRDATA4CH0_CR_RXPERBITRANK1_Lane2_OFF ( 8) + #define DDRDATA4CH0_CR_RXPERBITRANK1_Lane2_WID ( 4) + #define DDRDATA4CH0_CR_RXPERBITRANK1_Lane2_MSK (0x00000F00) + #define DDRDATA4CH0_CR_RXPERBITRANK1_Lane2_MAX (0x0000000F) + #define DDRDATA4CH0_CR_RXPERBITRANK1_Lane3_OFF (12) + #define DDRDATA4CH0_CR_RXPERBITRANK1_Lane3_WID ( 4) + #define DDRDATA4CH0_CR_RXPERBITRANK1_Lane3_MSK (0x0000F000) + #define DDRDATA4CH0_CR_RXPERBITRANK1_Lane3_MAX (0x0000000F) + #define DDRDATA4CH0_CR_RXPERBITRANK1_Lane4_OFF (16) + #define DDRDATA4CH0_CR_RXPERBITRANK1_Lane4_WID ( 4) + #define DDRDATA4CH0_CR_RXPERBITRANK1_Lane4_MSK (0x000F0000) + #define DDRDATA4CH0_CR_RXPERBITRANK1_Lane4_MAX (0x0000000F) + #define DDRDATA4CH0_CR_RXPERBITRANK1_Lane5_OFF (20) + #define DDRDATA4CH0_CR_RXPERBITRANK1_Lane5_WID ( 4) + #define DDRDATA4CH0_CR_RXPERBITRANK1_Lane5_MSK (0x00F00000) + #define DDRDATA4CH0_CR_RXPERBITRANK1_Lane5_MAX (0x0000000F) + #define DDRDATA4CH0_CR_RXPERBITRANK1_Lane6_OFF (24) + #define DDRDATA4CH0_CR_RXPERBITRANK1_Lane6_WID ( 4) + #define DDRDATA4CH0_CR_RXPERBITRANK1_Lane6_MSK (0x0F000000) + #define DDRDATA4CH0_CR_RXPERBITRANK1_Lane6_MAX (0x0000000F) + #define DDRDATA4CH0_CR_RXPERBITRANK1_Lane7_OFF (28) + #define DDRDATA4CH0_CR_RXPERBITRANK1_Lane7_WID ( 4) + #define DDRDATA4CH0_CR_RXPERBITRANK1_Lane7_MSK (0xF0000000) + #define DDRDATA4CH0_CR_RXPERBITRANK1_Lane7_MAX (0x0000000F) + +#define DDRDATA4CH0_CR_RXPERBITRANK2_REG (0x00000818) + #define DDRDATA4CH0_CR_RXPERBITRANK2_Lane0_OFF ( 0) + #define DDRDATA4CH0_CR_RXPERBITRANK2_Lane0_WID ( 4) + #define DDRDATA4CH0_CR_RXPERBITRANK2_Lane0_MSK (0x0000000F) + #define DDRDATA4CH0_CR_RXPERBITRANK2_Lane0_MAX (0x0000000F) + #define DDRDATA4CH0_CR_RXPERBITRANK2_Lane1_OFF ( 4) + #define DDRDATA4CH0_CR_RXPERBITRANK2_Lane1_WID ( 4) + #define DDRDATA4CH0_CR_RXPERBITRANK2_Lane1_MSK (0x000000F0) + #define DDRDATA4CH0_CR_RXPERBITRANK2_Lane1_MAX (0x0000000F) + #define DDRDATA4CH0_CR_RXPERBITRANK2_Lane2_OFF ( 8) + #define DDRDATA4CH0_CR_RXPERBITRANK2_Lane2_WID ( 4) + #define DDRDATA4CH0_CR_RXPERBITRANK2_Lane2_MSK (0x00000F00) + #define DDRDATA4CH0_CR_RXPERBITRANK2_Lane2_MAX (0x0000000F) + #define DDRDATA4CH0_CR_RXPERBITRANK2_Lane3_OFF (12) + #define DDRDATA4CH0_CR_RXPERBITRANK2_Lane3_WID ( 4) + #define DDRDATA4CH0_CR_RXPERBITRANK2_Lane3_MSK (0x0000F000) + #define DDRDATA4CH0_CR_RXPERBITRANK2_Lane3_MAX (0x0000000F) + #define DDRDATA4CH0_CR_RXPERBITRANK2_Lane4_OFF (16) + #define DDRDATA4CH0_CR_RXPERBITRANK2_Lane4_WID ( 4) + #define DDRDATA4CH0_CR_RXPERBITRANK2_Lane4_MSK (0x000F0000) + #define DDRDATA4CH0_CR_RXPERBITRANK2_Lane4_MAX (0x0000000F) + #define DDRDATA4CH0_CR_RXPERBITRANK2_Lane5_OFF (20) + #define DDRDATA4CH0_CR_RXPERBITRANK2_Lane5_WID ( 4) + #define DDRDATA4CH0_CR_RXPERBITRANK2_Lane5_MSK (0x00F00000) + #define DDRDATA4CH0_CR_RXPERBITRANK2_Lane5_MAX (0x0000000F) + #define DDRDATA4CH0_CR_RXPERBITRANK2_Lane6_OFF (24) + #define DDRDATA4CH0_CR_RXPERBITRANK2_Lane6_WID ( 4) + #define DDRDATA4CH0_CR_RXPERBITRANK2_Lane6_MSK (0x0F000000) + #define DDRDATA4CH0_CR_RXPERBITRANK2_Lane6_MAX (0x0000000F) + #define DDRDATA4CH0_CR_RXPERBITRANK2_Lane7_OFF (28) + #define DDRDATA4CH0_CR_RXPERBITRANK2_Lane7_WID ( 4) + #define DDRDATA4CH0_CR_RXPERBITRANK2_Lane7_MSK (0xF0000000) + #define DDRDATA4CH0_CR_RXPERBITRANK2_Lane7_MAX (0x0000000F) + +#define DDRDATA4CH0_CR_RXPERBITRANK3_REG (0x0000081C) + #define DDRDATA4CH0_CR_RXPERBITRANK3_Lane0_OFF ( 0) + #define DDRDATA4CH0_CR_RXPERBITRANK3_Lane0_WID ( 4) + #define DDRDATA4CH0_CR_RXPERBITRANK3_Lane0_MSK (0x0000000F) + #define DDRDATA4CH0_CR_RXPERBITRANK3_Lane0_MAX (0x0000000F) + #define DDRDATA4CH0_CR_RXPERBITRANK3_Lane1_OFF ( 4) + #define DDRDATA4CH0_CR_RXPERBITRANK3_Lane1_WID ( 4) + #define DDRDATA4CH0_CR_RXPERBITRANK3_Lane1_MSK (0x000000F0) + #define DDRDATA4CH0_CR_RXPERBITRANK3_Lane1_MAX (0x0000000F) + #define DDRDATA4CH0_CR_RXPERBITRANK3_Lane2_OFF ( 8) + #define DDRDATA4CH0_CR_RXPERBITRANK3_Lane2_WID ( 4) + #define DDRDATA4CH0_CR_RXPERBITRANK3_Lane2_MSK (0x00000F00) + #define DDRDATA4CH0_CR_RXPERBITRANK3_Lane2_MAX (0x0000000F) + #define DDRDATA4CH0_CR_RXPERBITRANK3_Lane3_OFF (12) + #define DDRDATA4CH0_CR_RXPERBITRANK3_Lane3_WID ( 4) + #define DDRDATA4CH0_CR_RXPERBITRANK3_Lane3_MSK (0x0000F000) + #define DDRDATA4CH0_CR_RXPERBITRANK3_Lane3_MAX (0x0000000F) + #define DDRDATA4CH0_CR_RXPERBITRANK3_Lane4_OFF (16) + #define DDRDATA4CH0_CR_RXPERBITRANK3_Lane4_WID ( 4) + #define DDRDATA4CH0_CR_RXPERBITRANK3_Lane4_MSK (0x000F0000) + #define DDRDATA4CH0_CR_RXPERBITRANK3_Lane4_MAX (0x0000000F) + #define DDRDATA4CH0_CR_RXPERBITRANK3_Lane5_OFF (20) + #define DDRDATA4CH0_CR_RXPERBITRANK3_Lane5_WID ( 4) + #define DDRDATA4CH0_CR_RXPERBITRANK3_Lane5_MSK (0x00F00000) + #define DDRDATA4CH0_CR_RXPERBITRANK3_Lane5_MAX (0x0000000F) + #define DDRDATA4CH0_CR_RXPERBITRANK3_Lane6_OFF (24) + #define DDRDATA4CH0_CR_RXPERBITRANK3_Lane6_WID ( 4) + #define DDRDATA4CH0_CR_RXPERBITRANK3_Lane6_MSK (0x0F000000) + #define DDRDATA4CH0_CR_RXPERBITRANK3_Lane6_MAX (0x0000000F) + #define DDRDATA4CH0_CR_RXPERBITRANK3_Lane7_OFF (28) + #define DDRDATA4CH0_CR_RXPERBITRANK3_Lane7_WID ( 4) + #define DDRDATA4CH0_CR_RXPERBITRANK3_Lane7_MSK (0xF0000000) + #define DDRDATA4CH0_CR_RXPERBITRANK3_Lane7_MAX (0x0000000F) + +#define DDRDATA4CH0_CR_TXTRAINRANK0_REG (0x00000820) + #define DDRDATA4CH0_CR_TXTRAINRANK0_TxDqDelay_OFF ( 0) + #define DDRDATA4CH0_CR_TXTRAINRANK0_TxDqDelay_WID ( 9) + #define DDRDATA4CH0_CR_TXTRAINRANK0_TxDqDelay_MSK (0x000001FF) + #define DDRDATA4CH0_CR_TXTRAINRANK0_TxDqDelay_MAX (0x000001FF) + #define DDRDATA4CH0_CR_TXTRAINRANK0_TxDqsDelay_OFF ( 9) + #define DDRDATA4CH0_CR_TXTRAINRANK0_TxDqsDelay_WID ( 9) + #define DDRDATA4CH0_CR_TXTRAINRANK0_TxDqsDelay_MSK (0x0003FE00) + #define DDRDATA4CH0_CR_TXTRAINRANK0_TxDqsDelay_MAX (0x000001FF) + #define DDRDATA4CH0_CR_TXTRAINRANK0_Spare0_OFF (18) + #define DDRDATA4CH0_CR_TXTRAINRANK0_Spare0_WID ( 2) + #define DDRDATA4CH0_CR_TXTRAINRANK0_Spare0_MSK (0x000C0000) + #define DDRDATA4CH0_CR_TXTRAINRANK0_Spare0_MAX (0x00000003) + #define DDRDATA4CH0_CR_TXTRAINRANK0_TxEqualization_OFF (20) + #define DDRDATA4CH0_CR_TXTRAINRANK0_TxEqualization_WID ( 6) + #define DDRDATA4CH0_CR_TXTRAINRANK0_TxEqualization_MSK (0x03F00000) + #define DDRDATA4CH0_CR_TXTRAINRANK0_TxEqualization_MAX (0x0000003F) + #define DDRDATA4CH0_CR_TXTRAINRANK0_Spare1_OFF (26) + #define DDRDATA4CH0_CR_TXTRAINRANK0_Spare1_WID ( 6) + #define DDRDATA4CH0_CR_TXTRAINRANK0_Spare1_MSK (0xFC000000) + #define DDRDATA4CH0_CR_TXTRAINRANK0_Spare1_MAX (0x0000003F) + +#define DDRDATA4CH0_CR_TXTRAINRANK1_REG (0x00000824) + #define DDRDATA4CH0_CR_TXTRAINRANK1_TxDqDelay_OFF ( 0) + #define DDRDATA4CH0_CR_TXTRAINRANK1_TxDqDelay_WID ( 9) + #define DDRDATA4CH0_CR_TXTRAINRANK1_TxDqDelay_MSK (0x000001FF) + #define DDRDATA4CH0_CR_TXTRAINRANK1_TxDqDelay_MAX (0x000001FF) + #define DDRDATA4CH0_CR_TXTRAINRANK1_TxDqsDelay_OFF ( 9) + #define DDRDATA4CH0_CR_TXTRAINRANK1_TxDqsDelay_WID ( 9) + #define DDRDATA4CH0_CR_TXTRAINRANK1_TxDqsDelay_MSK (0x0003FE00) + #define DDRDATA4CH0_CR_TXTRAINRANK1_TxDqsDelay_MAX (0x000001FF) + #define DDRDATA4CH0_CR_TXTRAINRANK1_Spare0_OFF (18) + #define DDRDATA4CH0_CR_TXTRAINRANK1_Spare0_WID ( 2) + #define DDRDATA4CH0_CR_TXTRAINRANK1_Spare0_MSK (0x000C0000) + #define DDRDATA4CH0_CR_TXTRAINRANK1_Spare0_MAX (0x00000003) + #define DDRDATA4CH0_CR_TXTRAINRANK1_TxEqualization_OFF (20) + #define DDRDATA4CH0_CR_TXTRAINRANK1_TxEqualization_WID ( 6) + #define DDRDATA4CH0_CR_TXTRAINRANK1_TxEqualization_MSK (0x03F00000) + #define DDRDATA4CH0_CR_TXTRAINRANK1_TxEqualization_MAX (0x0000003F) + #define DDRDATA4CH0_CR_TXTRAINRANK1_Spare1_OFF (26) + #define DDRDATA4CH0_CR_TXTRAINRANK1_Spare1_WID ( 6) + #define DDRDATA4CH0_CR_TXTRAINRANK1_Spare1_MSK (0xFC000000) + #define DDRDATA4CH0_CR_TXTRAINRANK1_Spare1_MAX (0x0000003F) + +#define DDRDATA4CH0_CR_TXTRAINRANK2_REG (0x00000828) + #define DDRDATA4CH0_CR_TXTRAINRANK2_TxDqDelay_OFF ( 0) + #define DDRDATA4CH0_CR_TXTRAINRANK2_TxDqDelay_WID ( 9) + #define DDRDATA4CH0_CR_TXTRAINRANK2_TxDqDelay_MSK (0x000001FF) + #define DDRDATA4CH0_CR_TXTRAINRANK2_TxDqDelay_MAX (0x000001FF) + #define DDRDATA4CH0_CR_TXTRAINRANK2_TxDqsDelay_OFF ( 9) + #define DDRDATA4CH0_CR_TXTRAINRANK2_TxDqsDelay_WID ( 9) + #define DDRDATA4CH0_CR_TXTRAINRANK2_TxDqsDelay_MSK (0x0003FE00) + #define DDRDATA4CH0_CR_TXTRAINRANK2_TxDqsDelay_MAX (0x000001FF) + #define DDRDATA4CH0_CR_TXTRAINRANK2_Spare0_OFF (18) + #define DDRDATA4CH0_CR_TXTRAINRANK2_Spare0_WID ( 2) + #define DDRDATA4CH0_CR_TXTRAINRANK2_Spare0_MSK (0x000C0000) + #define DDRDATA4CH0_CR_TXTRAINRANK2_Spare0_MAX (0x00000003) + #define DDRDATA4CH0_CR_TXTRAINRANK2_TxEqualization_OFF (20) + #define DDRDATA4CH0_CR_TXTRAINRANK2_TxEqualization_WID ( 6) + #define DDRDATA4CH0_CR_TXTRAINRANK2_TxEqualization_MSK (0x03F00000) + #define DDRDATA4CH0_CR_TXTRAINRANK2_TxEqualization_MAX (0x0000003F) + #define DDRDATA4CH0_CR_TXTRAINRANK2_Spare1_OFF (26) + #define DDRDATA4CH0_CR_TXTRAINRANK2_Spare1_WID ( 6) + #define DDRDATA4CH0_CR_TXTRAINRANK2_Spare1_MSK (0xFC000000) + #define DDRDATA4CH0_CR_TXTRAINRANK2_Spare1_MAX (0x0000003F) + +#define DDRDATA4CH0_CR_TXTRAINRANK3_REG (0x0000082C) + #define DDRDATA4CH0_CR_TXTRAINRANK3_TxDqDelay_OFF ( 0) + #define DDRDATA4CH0_CR_TXTRAINRANK3_TxDqDelay_WID ( 9) + #define DDRDATA4CH0_CR_TXTRAINRANK3_TxDqDelay_MSK (0x000001FF) + #define DDRDATA4CH0_CR_TXTRAINRANK3_TxDqDelay_MAX (0x000001FF) + #define DDRDATA4CH0_CR_TXTRAINRANK3_TxDqsDelay_OFF ( 9) + #define DDRDATA4CH0_CR_TXTRAINRANK3_TxDqsDelay_WID ( 9) + #define DDRDATA4CH0_CR_TXTRAINRANK3_TxDqsDelay_MSK (0x0003FE00) + #define DDRDATA4CH0_CR_TXTRAINRANK3_TxDqsDelay_MAX (0x000001FF) + #define DDRDATA4CH0_CR_TXTRAINRANK3_Spare0_OFF (18) + #define DDRDATA4CH0_CR_TXTRAINRANK3_Spare0_WID ( 2) + #define DDRDATA4CH0_CR_TXTRAINRANK3_Spare0_MSK (0x000C0000) + #define DDRDATA4CH0_CR_TXTRAINRANK3_Spare0_MAX (0x00000003) + #define DDRDATA4CH0_CR_TXTRAINRANK3_TxEqualization_OFF (20) + #define DDRDATA4CH0_CR_TXTRAINRANK3_TxEqualization_WID ( 6) + #define DDRDATA4CH0_CR_TXTRAINRANK3_TxEqualization_MSK (0x03F00000) + #define DDRDATA4CH0_CR_TXTRAINRANK3_TxEqualization_MAX (0x0000003F) + #define DDRDATA4CH0_CR_TXTRAINRANK3_Spare1_OFF (26) + #define DDRDATA4CH0_CR_TXTRAINRANK3_Spare1_WID ( 6) + #define DDRDATA4CH0_CR_TXTRAINRANK3_Spare1_MSK (0xFC000000) + #define DDRDATA4CH0_CR_TXTRAINRANK3_Spare1_MAX (0x0000003F) + +#define DDRDATA4CH0_CR_TXPERBITRANK0_REG (0x00000830) + #define DDRDATA4CH0_CR_TXPERBITRANK0_Lane0_OFF ( 0) + #define DDRDATA4CH0_CR_TXPERBITRANK0_Lane0_WID ( 4) + #define DDRDATA4CH0_CR_TXPERBITRANK0_Lane0_MSK (0x0000000F) + #define DDRDATA4CH0_CR_TXPERBITRANK0_Lane0_MAX (0x0000000F) + #define DDRDATA4CH0_CR_TXPERBITRANK0_Lane1_OFF ( 4) + #define DDRDATA4CH0_CR_TXPERBITRANK0_Lane1_WID ( 4) + #define DDRDATA4CH0_CR_TXPERBITRANK0_Lane1_MSK (0x000000F0) + #define DDRDATA4CH0_CR_TXPERBITRANK0_Lane1_MAX (0x0000000F) + #define DDRDATA4CH0_CR_TXPERBITRANK0_Lane2_OFF ( 8) + #define DDRDATA4CH0_CR_TXPERBITRANK0_Lane2_WID ( 4) + #define DDRDATA4CH0_CR_TXPERBITRANK0_Lane2_MSK (0x00000F00) + #define DDRDATA4CH0_CR_TXPERBITRANK0_Lane2_MAX (0x0000000F) + #define DDRDATA4CH0_CR_TXPERBITRANK0_Lane3_OFF (12) + #define DDRDATA4CH0_CR_TXPERBITRANK0_Lane3_WID ( 4) + #define DDRDATA4CH0_CR_TXPERBITRANK0_Lane3_MSK (0x0000F000) + #define DDRDATA4CH0_CR_TXPERBITRANK0_Lane3_MAX (0x0000000F) + #define DDRDATA4CH0_CR_TXPERBITRANK0_Lane4_OFF (16) + #define DDRDATA4CH0_CR_TXPERBITRANK0_Lane4_WID ( 4) + #define DDRDATA4CH0_CR_TXPERBITRANK0_Lane4_MSK (0x000F0000) + #define DDRDATA4CH0_CR_TXPERBITRANK0_Lane4_MAX (0x0000000F) + #define DDRDATA4CH0_CR_TXPERBITRANK0_Lane5_OFF (20) + #define DDRDATA4CH0_CR_TXPERBITRANK0_Lane5_WID ( 4) + #define DDRDATA4CH0_CR_TXPERBITRANK0_Lane5_MSK (0x00F00000) + #define DDRDATA4CH0_CR_TXPERBITRANK0_Lane5_MAX (0x0000000F) + #define DDRDATA4CH0_CR_TXPERBITRANK0_Lane6_OFF (24) + #define DDRDATA4CH0_CR_TXPERBITRANK0_Lane6_WID ( 4) + #define DDRDATA4CH0_CR_TXPERBITRANK0_Lane6_MSK (0x0F000000) + #define DDRDATA4CH0_CR_TXPERBITRANK0_Lane6_MAX (0x0000000F) + #define DDRDATA4CH0_CR_TXPERBITRANK0_Lane7_OFF (28) + #define DDRDATA4CH0_CR_TXPERBITRANK0_Lane7_WID ( 4) + #define DDRDATA4CH0_CR_TXPERBITRANK0_Lane7_MSK (0xF0000000) + #define DDRDATA4CH0_CR_TXPERBITRANK0_Lane7_MAX (0x0000000F) + +#define DDRDATA4CH0_CR_TXPERBITRANK1_REG (0x00000834) + #define DDRDATA4CH0_CR_TXPERBITRANK1_Lane0_OFF ( 0) + #define DDRDATA4CH0_CR_TXPERBITRANK1_Lane0_WID ( 4) + #define DDRDATA4CH0_CR_TXPERBITRANK1_Lane0_MSK (0x0000000F) + #define DDRDATA4CH0_CR_TXPERBITRANK1_Lane0_MAX (0x0000000F) + #define DDRDATA4CH0_CR_TXPERBITRANK1_Lane1_OFF ( 4) + #define DDRDATA4CH0_CR_TXPERBITRANK1_Lane1_WID ( 4) + #define DDRDATA4CH0_CR_TXPERBITRANK1_Lane1_MSK (0x000000F0) + #define DDRDATA4CH0_CR_TXPERBITRANK1_Lane1_MAX (0x0000000F) + #define DDRDATA4CH0_CR_TXPERBITRANK1_Lane2_OFF ( 8) + #define DDRDATA4CH0_CR_TXPERBITRANK1_Lane2_WID ( 4) + #define DDRDATA4CH0_CR_TXPERBITRANK1_Lane2_MSK (0x00000F00) + #define DDRDATA4CH0_CR_TXPERBITRANK1_Lane2_MAX (0x0000000F) + #define DDRDATA4CH0_CR_TXPERBITRANK1_Lane3_OFF (12) + #define DDRDATA4CH0_CR_TXPERBITRANK1_Lane3_WID ( 4) + #define DDRDATA4CH0_CR_TXPERBITRANK1_Lane3_MSK (0x0000F000) + #define DDRDATA4CH0_CR_TXPERBITRANK1_Lane3_MAX (0x0000000F) + #define DDRDATA4CH0_CR_TXPERBITRANK1_Lane4_OFF (16) + #define DDRDATA4CH0_CR_TXPERBITRANK1_Lane4_WID ( 4) + #define DDRDATA4CH0_CR_TXPERBITRANK1_Lane4_MSK (0x000F0000) + #define DDRDATA4CH0_CR_TXPERBITRANK1_Lane4_MAX (0x0000000F) + #define DDRDATA4CH0_CR_TXPERBITRANK1_Lane5_OFF (20) + #define DDRDATA4CH0_CR_TXPERBITRANK1_Lane5_WID ( 4) + #define DDRDATA4CH0_CR_TXPERBITRANK1_Lane5_MSK (0x00F00000) + #define DDRDATA4CH0_CR_TXPERBITRANK1_Lane5_MAX (0x0000000F) + #define DDRDATA4CH0_CR_TXPERBITRANK1_Lane6_OFF (24) + #define DDRDATA4CH0_CR_TXPERBITRANK1_Lane6_WID ( 4) + #define DDRDATA4CH0_CR_TXPERBITRANK1_Lane6_MSK (0x0F000000) + #define DDRDATA4CH0_CR_TXPERBITRANK1_Lane6_MAX (0x0000000F) + #define DDRDATA4CH0_CR_TXPERBITRANK1_Lane7_OFF (28) + #define DDRDATA4CH0_CR_TXPERBITRANK1_Lane7_WID ( 4) + #define DDRDATA4CH0_CR_TXPERBITRANK1_Lane7_MSK (0xF0000000) + #define DDRDATA4CH0_CR_TXPERBITRANK1_Lane7_MAX (0x0000000F) + +#define DDRDATA4CH0_CR_TXPERBITRANK2_REG (0x00000838) + #define DDRDATA4CH0_CR_TXPERBITRANK2_Lane0_OFF ( 0) + #define DDRDATA4CH0_CR_TXPERBITRANK2_Lane0_WID ( 4) + #define DDRDATA4CH0_CR_TXPERBITRANK2_Lane0_MSK (0x0000000F) + #define DDRDATA4CH0_CR_TXPERBITRANK2_Lane0_MAX (0x0000000F) + #define DDRDATA4CH0_CR_TXPERBITRANK2_Lane1_OFF ( 4) + #define DDRDATA4CH0_CR_TXPERBITRANK2_Lane1_WID ( 4) + #define DDRDATA4CH0_CR_TXPERBITRANK2_Lane1_MSK (0x000000F0) + #define DDRDATA4CH0_CR_TXPERBITRANK2_Lane1_MAX (0x0000000F) + #define DDRDATA4CH0_CR_TXPERBITRANK2_Lane2_OFF ( 8) + #define DDRDATA4CH0_CR_TXPERBITRANK2_Lane2_WID ( 4) + #define DDRDATA4CH0_CR_TXPERBITRANK2_Lane2_MSK (0x00000F00) + #define DDRDATA4CH0_CR_TXPERBITRANK2_Lane2_MAX (0x0000000F) + #define DDRDATA4CH0_CR_TXPERBITRANK2_Lane3_OFF (12) + #define DDRDATA4CH0_CR_TXPERBITRANK2_Lane3_WID ( 4) + #define DDRDATA4CH0_CR_TXPERBITRANK2_Lane3_MSK (0x0000F000) + #define DDRDATA4CH0_CR_TXPERBITRANK2_Lane3_MAX (0x0000000F) + #define DDRDATA4CH0_CR_TXPERBITRANK2_Lane4_OFF (16) + #define DDRDATA4CH0_CR_TXPERBITRANK2_Lane4_WID ( 4) + #define DDRDATA4CH0_CR_TXPERBITRANK2_Lane4_MSK (0x000F0000) + #define DDRDATA4CH0_CR_TXPERBITRANK2_Lane4_MAX (0x0000000F) + #define DDRDATA4CH0_CR_TXPERBITRANK2_Lane5_OFF (20) + #define DDRDATA4CH0_CR_TXPERBITRANK2_Lane5_WID ( 4) + #define DDRDATA4CH0_CR_TXPERBITRANK2_Lane5_MSK (0x00F00000) + #define DDRDATA4CH0_CR_TXPERBITRANK2_Lane5_MAX (0x0000000F) + #define DDRDATA4CH0_CR_TXPERBITRANK2_Lane6_OFF (24) + #define DDRDATA4CH0_CR_TXPERBITRANK2_Lane6_WID ( 4) + #define DDRDATA4CH0_CR_TXPERBITRANK2_Lane6_MSK (0x0F000000) + #define DDRDATA4CH0_CR_TXPERBITRANK2_Lane6_MAX (0x0000000F) + #define DDRDATA4CH0_CR_TXPERBITRANK2_Lane7_OFF (28) + #define DDRDATA4CH0_CR_TXPERBITRANK2_Lane7_WID ( 4) + #define DDRDATA4CH0_CR_TXPERBITRANK2_Lane7_MSK (0xF0000000) + #define DDRDATA4CH0_CR_TXPERBITRANK2_Lane7_MAX (0x0000000F) + +#define DDRDATA4CH0_CR_TXPERBITRANK3_REG (0x0000083C) + #define DDRDATA4CH0_CR_TXPERBITRANK3_Lane0_OFF ( 0) + #define DDRDATA4CH0_CR_TXPERBITRANK3_Lane0_WID ( 4) + #define DDRDATA4CH0_CR_TXPERBITRANK3_Lane0_MSK (0x0000000F) + #define DDRDATA4CH0_CR_TXPERBITRANK3_Lane0_MAX (0x0000000F) + #define DDRDATA4CH0_CR_TXPERBITRANK3_Lane1_OFF ( 4) + #define DDRDATA4CH0_CR_TXPERBITRANK3_Lane1_WID ( 4) + #define DDRDATA4CH0_CR_TXPERBITRANK3_Lane1_MSK (0x000000F0) + #define DDRDATA4CH0_CR_TXPERBITRANK3_Lane1_MAX (0x0000000F) + #define DDRDATA4CH0_CR_TXPERBITRANK3_Lane2_OFF ( 8) + #define DDRDATA4CH0_CR_TXPERBITRANK3_Lane2_WID ( 4) + #define DDRDATA4CH0_CR_TXPERBITRANK3_Lane2_MSK (0x00000F00) + #define DDRDATA4CH0_CR_TXPERBITRANK3_Lane2_MAX (0x0000000F) + #define DDRDATA4CH0_CR_TXPERBITRANK3_Lane3_OFF (12) + #define DDRDATA4CH0_CR_TXPERBITRANK3_Lane3_WID ( 4) + #define DDRDATA4CH0_CR_TXPERBITRANK3_Lane3_MSK (0x0000F000) + #define DDRDATA4CH0_CR_TXPERBITRANK3_Lane3_MAX (0x0000000F) + #define DDRDATA4CH0_CR_TXPERBITRANK3_Lane4_OFF (16) + #define DDRDATA4CH0_CR_TXPERBITRANK3_Lane4_WID ( 4) + #define DDRDATA4CH0_CR_TXPERBITRANK3_Lane4_MSK (0x000F0000) + #define DDRDATA4CH0_CR_TXPERBITRANK3_Lane4_MAX (0x0000000F) + #define DDRDATA4CH0_CR_TXPERBITRANK3_Lane5_OFF (20) + #define DDRDATA4CH0_CR_TXPERBITRANK3_Lane5_WID ( 4) + #define DDRDATA4CH0_CR_TXPERBITRANK3_Lane5_MSK (0x00F00000) + #define DDRDATA4CH0_CR_TXPERBITRANK3_Lane5_MAX (0x0000000F) + #define DDRDATA4CH0_CR_TXPERBITRANK3_Lane6_OFF (24) + #define DDRDATA4CH0_CR_TXPERBITRANK3_Lane6_WID ( 4) + #define DDRDATA4CH0_CR_TXPERBITRANK3_Lane6_MSK (0x0F000000) + #define DDRDATA4CH0_CR_TXPERBITRANK3_Lane6_MAX (0x0000000F) + #define DDRDATA4CH0_CR_TXPERBITRANK3_Lane7_OFF (28) + #define DDRDATA4CH0_CR_TXPERBITRANK3_Lane7_WID ( 4) + #define DDRDATA4CH0_CR_TXPERBITRANK3_Lane7_MSK (0xF0000000) + #define DDRDATA4CH0_CR_TXPERBITRANK3_Lane7_MAX (0x0000000F) + +#define DDRDATA4CH0_CR_RCOMPDATA0_REG (0x00000840) + #define DDRDATA4CH0_CR_RCOMPDATA0_RcompDrvUp_OFF ( 0) + #define DDRDATA4CH0_CR_RCOMPDATA0_RcompDrvUp_WID ( 6) + #define DDRDATA4CH0_CR_RCOMPDATA0_RcompDrvUp_MSK (0x0000003F) + #define DDRDATA4CH0_CR_RCOMPDATA0_RcompDrvUp_MAX (0x0000003F) + #define DDRDATA4CH0_CR_RCOMPDATA0_Spare0_OFF ( 6) + #define DDRDATA4CH0_CR_RCOMPDATA0_Spare0_WID ( 3) + #define DDRDATA4CH0_CR_RCOMPDATA0_Spare0_MSK (0x000001C0) + #define DDRDATA4CH0_CR_RCOMPDATA0_Spare0_MAX (0x00000007) + #define DDRDATA4CH0_CR_RCOMPDATA0_RcompDrvDown_OFF ( 9) + #define DDRDATA4CH0_CR_RCOMPDATA0_RcompDrvDown_WID ( 6) + #define DDRDATA4CH0_CR_RCOMPDATA0_RcompDrvDown_MSK (0x00007E00) + #define DDRDATA4CH0_CR_RCOMPDATA0_RcompDrvDown_MAX (0x0000003F) + #define DDRDATA4CH0_CR_RCOMPDATA0_VTComp_OFF (15) + #define DDRDATA4CH0_CR_RCOMPDATA0_VTComp_WID ( 5) + #define DDRDATA4CH0_CR_RCOMPDATA0_VTComp_MSK (0x000F8000) + #define DDRDATA4CH0_CR_RCOMPDATA0_VTComp_MAX (0x0000001F) + #define DDRDATA4CH0_CR_RCOMPDATA0_TcoComp_OFF (20) + #define DDRDATA4CH0_CR_RCOMPDATA0_TcoComp_WID ( 6) + #define DDRDATA4CH0_CR_RCOMPDATA0_TcoComp_MSK (0x03F00000) + #define DDRDATA4CH0_CR_RCOMPDATA0_TcoComp_MAX (0x0000003F) + #define DDRDATA4CH0_CR_RCOMPDATA0_SlewRateComp_OFF (26) + #define DDRDATA4CH0_CR_RCOMPDATA0_SlewRateComp_WID ( 5) + #define DDRDATA4CH0_CR_RCOMPDATA0_SlewRateComp_MSK (0x7C000000) + #define DDRDATA4CH0_CR_RCOMPDATA0_SlewRateComp_MAX (0x0000001F) + #define DDRDATA4CH0_CR_RCOMPDATA0_Spare2_OFF (31) + #define DDRDATA4CH0_CR_RCOMPDATA0_Spare2_WID ( 1) + #define DDRDATA4CH0_CR_RCOMPDATA0_Spare2_MSK (0x80000000) + #define DDRDATA4CH0_CR_RCOMPDATA0_Spare2_MAX (0x00000001) + +#define DDRDATA4CH0_CR_RCOMPDATA1_REG (0x00000844) + #define DDRDATA4CH0_CR_RCOMPDATA1_RcompOdtUp_OFF ( 0) + #define DDRDATA4CH0_CR_RCOMPDATA1_RcompOdtUp_WID ( 6) + #define DDRDATA4CH0_CR_RCOMPDATA1_RcompOdtUp_MSK (0x0000003F) + #define DDRDATA4CH0_CR_RCOMPDATA1_RcompOdtUp_MAX (0x0000003F) + #define DDRDATA4CH0_CR_RCOMPDATA1_Spare0_OFF ( 6) + #define DDRDATA4CH0_CR_RCOMPDATA1_Spare0_WID ( 3) + #define DDRDATA4CH0_CR_RCOMPDATA1_Spare0_MSK (0x000001C0) + #define DDRDATA4CH0_CR_RCOMPDATA1_Spare0_MAX (0x00000007) + #define DDRDATA4CH0_CR_RCOMPDATA1_RcompOdtDown_OFF ( 9) + #define DDRDATA4CH0_CR_RCOMPDATA1_RcompOdtDown_WID ( 6) + #define DDRDATA4CH0_CR_RCOMPDATA1_RcompOdtDown_MSK (0x00007E00) + #define DDRDATA4CH0_CR_RCOMPDATA1_RcompOdtDown_MAX (0x0000003F) + #define DDRDATA4CH0_CR_RCOMPDATA1_Spare1_OFF (15) + #define DDRDATA4CH0_CR_RCOMPDATA1_Spare1_WID ( 1) + #define DDRDATA4CH0_CR_RCOMPDATA1_Spare1_MSK (0x00008000) + #define DDRDATA4CH0_CR_RCOMPDATA1_Spare1_MAX (0x00000001) + #define DDRDATA4CH0_CR_RCOMPDATA1_PanicDrvDn_OFF (16) + #define DDRDATA4CH0_CR_RCOMPDATA1_PanicDrvDn_WID ( 6) + #define DDRDATA4CH0_CR_RCOMPDATA1_PanicDrvDn_MSK (0x003F0000) + #define DDRDATA4CH0_CR_RCOMPDATA1_PanicDrvDn_MAX (0x0000003F) + #define DDRDATA4CH0_CR_RCOMPDATA1_PanicDrvUp_OFF (22) + #define DDRDATA4CH0_CR_RCOMPDATA1_PanicDrvUp_WID ( 6) + #define DDRDATA4CH0_CR_RCOMPDATA1_PanicDrvUp_MSK (0x0FC00000) + #define DDRDATA4CH0_CR_RCOMPDATA1_PanicDrvUp_MAX (0x0000003F) + #define DDRDATA4CH0_CR_RCOMPDATA1_LevelShifterComp_OFF (28) + #define DDRDATA4CH0_CR_RCOMPDATA1_LevelShifterComp_WID ( 3) + #define DDRDATA4CH0_CR_RCOMPDATA1_LevelShifterComp_MSK (0x70000000) + #define DDRDATA4CH0_CR_RCOMPDATA1_LevelShifterComp_MAX (0x00000007) + #define DDRDATA4CH0_CR_RCOMPDATA1_Spare2_OFF (31) + #define DDRDATA4CH0_CR_RCOMPDATA1_Spare2_WID ( 1) + #define DDRDATA4CH0_CR_RCOMPDATA1_Spare2_MSK (0x80000000) + #define DDRDATA4CH0_CR_RCOMPDATA1_Spare2_MAX (0x00000001) + +#define DDRDATA4CH0_CR_TXXTALK_REG (0x00000848) + #define DDRDATA4CH0_CR_TXXTALK_Lane0_OFF ( 0) + #define DDRDATA4CH0_CR_TXXTALK_Lane0_WID ( 4) + #define DDRDATA4CH0_CR_TXXTALK_Lane0_MSK (0x0000000F) + #define DDRDATA4CH0_CR_TXXTALK_Lane0_MAX (0x0000000F) + #define DDRDATA4CH0_CR_TXXTALK_Lane1_OFF ( 4) + #define DDRDATA4CH0_CR_TXXTALK_Lane1_WID ( 4) + #define DDRDATA4CH0_CR_TXXTALK_Lane1_MSK (0x000000F0) + #define DDRDATA4CH0_CR_TXXTALK_Lane1_MAX (0x0000000F) + #define DDRDATA4CH0_CR_TXXTALK_Lane2_OFF ( 8) + #define DDRDATA4CH0_CR_TXXTALK_Lane2_WID ( 4) + #define DDRDATA4CH0_CR_TXXTALK_Lane2_MSK (0x00000F00) + #define DDRDATA4CH0_CR_TXXTALK_Lane2_MAX (0x0000000F) + #define DDRDATA4CH0_CR_TXXTALK_Lane3_OFF (12) + #define DDRDATA4CH0_CR_TXXTALK_Lane3_WID ( 4) + #define DDRDATA4CH0_CR_TXXTALK_Lane3_MSK (0x0000F000) + #define DDRDATA4CH0_CR_TXXTALK_Lane3_MAX (0x0000000F) + #define DDRDATA4CH0_CR_TXXTALK_Lane4_OFF (16) + #define DDRDATA4CH0_CR_TXXTALK_Lane4_WID ( 4) + #define DDRDATA4CH0_CR_TXXTALK_Lane4_MSK (0x000F0000) + #define DDRDATA4CH0_CR_TXXTALK_Lane4_MAX (0x0000000F) + #define DDRDATA4CH0_CR_TXXTALK_Lane5_OFF (20) + #define DDRDATA4CH0_CR_TXXTALK_Lane5_WID ( 4) + #define DDRDATA4CH0_CR_TXXTALK_Lane5_MSK (0x00F00000) + #define DDRDATA4CH0_CR_TXXTALK_Lane5_MAX (0x0000000F) + #define DDRDATA4CH0_CR_TXXTALK_Lane6_OFF (24) + #define DDRDATA4CH0_CR_TXXTALK_Lane6_WID ( 4) + #define DDRDATA4CH0_CR_TXXTALK_Lane6_MSK (0x0F000000) + #define DDRDATA4CH0_CR_TXXTALK_Lane6_MAX (0x0000000F) + #define DDRDATA4CH0_CR_TXXTALK_Lane7_OFF (28) + #define DDRDATA4CH0_CR_TXXTALK_Lane7_WID ( 4) + #define DDRDATA4CH0_CR_TXXTALK_Lane7_MSK (0xF0000000) + #define DDRDATA4CH0_CR_TXXTALK_Lane7_MAX (0x0000000F) + +#define DDRDATA4CH0_CR_RXOFFSETVDQ_REG (0x0000084C) + #define DDRDATA4CH0_CR_RXOFFSETVDQ_Lane0_OFF ( 0) + #define DDRDATA4CH0_CR_RXOFFSETVDQ_Lane0_WID ( 4) + #define DDRDATA4CH0_CR_RXOFFSETVDQ_Lane0_MSK (0x0000000F) + #define DDRDATA4CH0_CR_RXOFFSETVDQ_Lane0_MAX (0x0000000F) + #define DDRDATA4CH0_CR_RXOFFSETVDQ_Lane1_OFF ( 4) + #define DDRDATA4CH0_CR_RXOFFSETVDQ_Lane1_WID ( 4) + #define DDRDATA4CH0_CR_RXOFFSETVDQ_Lane1_MSK (0x000000F0) + #define DDRDATA4CH0_CR_RXOFFSETVDQ_Lane1_MAX (0x0000000F) + #define DDRDATA4CH0_CR_RXOFFSETVDQ_Lane2_OFF ( 8) + #define DDRDATA4CH0_CR_RXOFFSETVDQ_Lane2_WID ( 4) + #define DDRDATA4CH0_CR_RXOFFSETVDQ_Lane2_MSK (0x00000F00) + #define DDRDATA4CH0_CR_RXOFFSETVDQ_Lane2_MAX (0x0000000F) + #define DDRDATA4CH0_CR_RXOFFSETVDQ_Lane3_OFF (12) + #define DDRDATA4CH0_CR_RXOFFSETVDQ_Lane3_WID ( 4) + #define DDRDATA4CH0_CR_RXOFFSETVDQ_Lane3_MSK (0x0000F000) + #define DDRDATA4CH0_CR_RXOFFSETVDQ_Lane3_MAX (0x0000000F) + #define DDRDATA4CH0_CR_RXOFFSETVDQ_Lane4_OFF (16) + #define DDRDATA4CH0_CR_RXOFFSETVDQ_Lane4_WID ( 4) + #define DDRDATA4CH0_CR_RXOFFSETVDQ_Lane4_MSK (0x000F0000) + #define DDRDATA4CH0_CR_RXOFFSETVDQ_Lane4_MAX (0x0000000F) + #define DDRDATA4CH0_CR_RXOFFSETVDQ_Lane5_OFF (20) + #define DDRDATA4CH0_CR_RXOFFSETVDQ_Lane5_WID ( 4) + #define DDRDATA4CH0_CR_RXOFFSETVDQ_Lane5_MSK (0x00F00000) + #define DDRDATA4CH0_CR_RXOFFSETVDQ_Lane5_MAX (0x0000000F) + #define DDRDATA4CH0_CR_RXOFFSETVDQ_Lane6_OFF (24) + #define DDRDATA4CH0_CR_RXOFFSETVDQ_Lane6_WID ( 4) + #define DDRDATA4CH0_CR_RXOFFSETVDQ_Lane6_MSK (0x0F000000) + #define DDRDATA4CH0_CR_RXOFFSETVDQ_Lane6_MAX (0x0000000F) + #define DDRDATA4CH0_CR_RXOFFSETVDQ_Lane7_OFF (28) + #define DDRDATA4CH0_CR_RXOFFSETVDQ_Lane7_WID ( 4) + #define DDRDATA4CH0_CR_RXOFFSETVDQ_Lane7_MSK (0xF0000000) + #define DDRDATA4CH0_CR_RXOFFSETVDQ_Lane7_MAX (0x0000000F) + +#define DDRDATA4CH0_CR_DDRDATARESERVED_REG (0x00000850) + #define DDRDATA4CH0_CR_DDRDATARESERVED_Spare_OFF ( 0) + #define DDRDATA4CH0_CR_DDRDATARESERVED_Spare_WID (32) + #define DDRDATA4CH0_CR_DDRDATARESERVED_Spare_MSK (0xFFFFFFFF) + #define DDRDATA4CH0_CR_DDRDATARESERVED_Spare_MAX (0xFFFFFFFF) + +#define DDRDATA4CH0_CR_DATATRAINFEEDBACK_REG (0x00000854) + #define DDRDATA4CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_OFF ( 0) + #define DDRDATA4CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_WID ( 9) + #define DDRDATA4CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_MSK (0x000001FF) + #define DDRDATA4CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_MAX (0x000001FF) + #define DDRDATA4CH0_CR_DATATRAINFEEDBACK_Spare_OFF ( 9) + #define DDRDATA4CH0_CR_DATATRAINFEEDBACK_Spare_WID (23) + #define DDRDATA4CH0_CR_DATATRAINFEEDBACK_Spare_MSK (0xFFFFFE00) + #define DDRDATA4CH0_CR_DATATRAINFEEDBACK_Spare_MAX (0x007FFFFF) + +#define DDRDATA4CH0_CR_DLLPITESTANDADC_REG (0x00000858) + #define DDRDATA4CH0_CR_DLLPITESTANDADC_RunTest_OFF ( 0) + #define DDRDATA4CH0_CR_DLLPITESTANDADC_RunTest_WID ( 1) + #define DDRDATA4CH0_CR_DLLPITESTANDADC_RunTest_MSK (0x00000001) + #define DDRDATA4CH0_CR_DLLPITESTANDADC_RunTest_MAX (0x00000001) + #define DDRDATA4CH0_CR_DLLPITESTANDADC_RunTest_DEF (0x00000000) + #define DDRDATA4CH0_CR_DLLPITESTANDADC_Load_OFF ( 1) + #define DDRDATA4CH0_CR_DLLPITESTANDADC_Load_WID ( 1) + #define DDRDATA4CH0_CR_DLLPITESTANDADC_Load_MSK (0x00000002) + #define DDRDATA4CH0_CR_DLLPITESTANDADC_Load_MAX (0x00000001) + #define DDRDATA4CH0_CR_DLLPITESTANDADC_Load_DEF (0x00000000) + #define DDRDATA4CH0_CR_DLLPITESTANDADC_ModeHVM_OFF ( 2) + #define DDRDATA4CH0_CR_DLLPITESTANDADC_ModeHVM_WID ( 1) + #define DDRDATA4CH0_CR_DLLPITESTANDADC_ModeHVM_MSK (0x00000004) + #define DDRDATA4CH0_CR_DLLPITESTANDADC_ModeHVM_MAX (0x00000001) + #define DDRDATA4CH0_CR_DLLPITESTANDADC_ModeHVM_DEF (0x00000000) + #define DDRDATA4CH0_CR_DLLPITESTANDADC_ModeDV_OFF ( 3) + #define DDRDATA4CH0_CR_DLLPITESTANDADC_ModeDV_WID ( 1) + #define DDRDATA4CH0_CR_DLLPITESTANDADC_ModeDV_MSK (0x00000008) + #define DDRDATA4CH0_CR_DLLPITESTANDADC_ModeDV_MAX (0x00000001) + #define DDRDATA4CH0_CR_DLLPITESTANDADC_ModeDV_DEF (0x00000000) + #define DDRDATA4CH0_CR_DLLPITESTANDADC_ModeADC_OFF ( 4) + #define DDRDATA4CH0_CR_DLLPITESTANDADC_ModeADC_WID ( 1) + #define DDRDATA4CH0_CR_DLLPITESTANDADC_ModeADC_MSK (0x00000010) + #define DDRDATA4CH0_CR_DLLPITESTANDADC_ModeADC_MAX (0x00000001) + #define DDRDATA4CH0_CR_DLLPITESTANDADC_ModeADC_DEF (0x00000000) + #define DDRDATA4CH0_CR_DLLPITESTANDADC_LoadCount_OFF ( 5) + #define DDRDATA4CH0_CR_DLLPITESTANDADC_LoadCount_WID (10) + #define DDRDATA4CH0_CR_DLLPITESTANDADC_LoadCount_MSK (0x00007FE0) + #define DDRDATA4CH0_CR_DLLPITESTANDADC_LoadCount_MAX (0x000003FF) + #define DDRDATA4CH0_CR_DLLPITESTANDADC_CountStatus_OFF (15) + #define DDRDATA4CH0_CR_DLLPITESTANDADC_CountStatus_WID (10) + #define DDRDATA4CH0_CR_DLLPITESTANDADC_CountStatus_MSK (0x01FF8000) + #define DDRDATA4CH0_CR_DLLPITESTANDADC_CountStatus_MAX (0x000003FF) + #define DDRDATA4CH0_CR_DLLPITESTANDADC_CountStatus_DEF (0x00000000) + #define DDRDATA4CH0_CR_DLLPITESTANDADC_Spare_OFF (25) + #define DDRDATA4CH0_CR_DLLPITESTANDADC_Spare_WID ( 7) + #define DDRDATA4CH0_CR_DLLPITESTANDADC_Spare_MSK (0xFE000000) + #define DDRDATA4CH0_CR_DLLPITESTANDADC_Spare_MAX (0x0000007F) + +#define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_REG (0x0000085C) + #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_OFF ( 0) + #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_WID ( 6) + #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MSK (0x0000003F) + #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MAX (0x0000003F) + #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_DEF (0x00000000) + #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_OFF ( 6) + #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_WID ( 6) + #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MSK (0x00000FC0) + #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MAX (0x0000003F) + #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_DEF (0x00000000) + #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_OFF (12) + #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_WID ( 5) + #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MSK (0x0001F000) + #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MAX (0x0000001F) + #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_DEF (0x00000000) + #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_OFF (17) + #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_WID ( 5) + #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MSK (0x003E0000) + #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MAX (0x0000001F) + #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_DEF (0x00000000) + #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_OFF (22) + #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_WID ( 5) + #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_MSK (0x07C00000) + #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_MAX (0x0000001F) + #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_DEF (0x00000000) + #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_OFF (27) + #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_WID ( 5) + #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MSK (0xF8000000) + #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MAX (0x0000001F) + #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_DEF (0x00000000) + +#define DDRDATA4CH0_CR_DDRCRDATACONTROL1_REG (0x00000860) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_RefPi_OFF ( 0) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_RefPi_WID ( 4) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_RefPi_MSK (0x0000000F) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_RefPi_MAX (0x0000000F) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_RefPi_DEF (0x00000000) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_DllMask_OFF ( 4) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_DllMask_WID ( 2) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_DllMask_MSK (0x00000030) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_DllMask_MAX (0x00000003) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_DllMask_DEF (0x00000000) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_DllWeakLock_OFF ( 6) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_DllWeakLock_WID ( 1) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_DllWeakLock_MSK (0x00000040) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_DllWeakLock_MAX (0x00000001) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_DllWeakLock_DEF (0x00000000) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_OFF ( 7) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_WID ( 3) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MSK (0x00000380) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MAX (0x00000007) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_DEF (0x00000000) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_OFF (10) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_WID ( 3) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_MSK (0x00001C00) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_MAX (0x00000007) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_DEF (0x00000000) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_OdtDelay_OFF (13) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_OdtDelay_WID ( 4) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_OdtDelay_MSK (0x0001E000) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_OdtDelay_MAX (0x0000000F) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_OdtDelay_DEF (0x00000000) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_OdtDuration_OFF (17) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_OdtDuration_WID ( 3) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_OdtDuration_MSK (0x000E0000) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_OdtDuration_MAX (0x00000007) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_OdtDuration_DEF (0x00000000) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_OFF (20) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_WID ( 4) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_MSK (0x00F00000) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_MAX (0x0000000F) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_DEF (0x00000000) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_OFF (24) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_WID ( 3) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_MSK (0x07000000) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_MAX (0x00000007) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_DEF (0x00000000) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_OFF (27) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_WID ( 3) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_MSK (0x38000000) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_MAX (0x00000007) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_DEF (0x00000000) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_OFF (30) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_WID ( 1) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_MSK (0x40000000) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_MAX (0x00000001) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_DEF (0x00000000) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_Rsvd1_OFF (31) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_Rsvd1_WID ( 1) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_Rsvd1_MSK (0x80000000) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_Rsvd1_MAX (0x00000001) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_Rsvd1_DEF (0x00000000) + +#define DDRDATA4CH0_CR_DDRCRDATACONTROL2_REG (0x00000864) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_OFF ( 0) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_WID ( 5) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_MSK (0x0000001F) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_MAX (0x0000001F) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_DEF (0x00000000) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_OFF ( 5) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_WID ( 1) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_MSK (0x00000020) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_MAX (0x00000001) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_DEF (0x00000000) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_ForceRxOn_OFF ( 6) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_ForceRxOn_WID ( 1) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_ForceRxOn_MSK (0x00000040) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_ForceRxOn_MAX (0x00000001) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_ForceRxOn_DEF (0x00000000) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_LeakerComp_OFF ( 7) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_LeakerComp_WID ( 2) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_LeakerComp_MSK (0x00000180) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_LeakerComp_MAX (0x00000003) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_LeakerComp_DEF (0x00000000) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_OFF ( 9) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_WID ( 4) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_MSK (0x00001E00) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_MAX (0x0000000F) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_DEF (0x00000008) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_OFF (13) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_WID ( 5) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_MSK (0x0003E000) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_MAX (0x0000001F) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_DEF (0x00000011) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_OFF (18) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_WID ( 1) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_MSK (0x00040000) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_MAX (0x00000001) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_DEF (0x00000000) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_Spare_OFF (19) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_Spare_WID (13) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_Spare_MSK (0xFFF80000) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_Spare_MAX (0x00001FFF) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_Spare_DEF (0x00000000) + +#define DDRDATA4CH0_CR_DDRCRVSSHIORVREFCONTROL_REG (0x0000086C) + #define DDRDATA4CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_OFF ( 0) + #define DDRDATA4CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_WID (24) + #define DDRDATA4CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_MSK (0x00FFFFFF) + #define DDRDATA4CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_MAX (0x00FFFFFF) + #define DDRDATA4CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_DEF (0x00000000) + #define DDRDATA4CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_OFF (24) + #define DDRDATA4CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_WID ( 8) + #define DDRDATA4CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_MSK (0xFF000000) + #define DDRDATA4CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_MAX (0x000000FF) + #define DDRDATA4CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_DEF (0x00000000) + +#define DDRDATA4CH0_CR_DDRCRDATAOFFSETTRAIN_REG (0x00000870) + #define DDRDATA4CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_OFF ( 0) + #define DDRDATA4CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_WID ( 6) + #define DDRDATA4CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MSK (0x0000003F) + #define DDRDATA4CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MAX (0x0000003F) + #define DDRDATA4CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_DEF (0x00000000) + #define DDRDATA4CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_OFF ( 6) + #define DDRDATA4CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_WID ( 6) + #define DDRDATA4CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MSK (0x00000FC0) + #define DDRDATA4CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MAX (0x0000003F) + #define DDRDATA4CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_DEF (0x00000000) + #define DDRDATA4CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_OFF (12) + #define DDRDATA4CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_WID ( 6) + #define DDRDATA4CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MSK (0x0003F000) + #define DDRDATA4CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MAX (0x0000003F) + #define DDRDATA4CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_DEF (0x00000000) + #define DDRDATA4CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_OFF (18) + #define DDRDATA4CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_WID ( 6) + #define DDRDATA4CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MSK (0x00FC0000) + #define DDRDATA4CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MAX (0x0000003F) + #define DDRDATA4CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_DEF (0x00000000) + #define DDRDATA4CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_OFF (24) + #define DDRDATA4CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_WID ( 7) + #define DDRDATA4CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MSK (0x7F000000) + #define DDRDATA4CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MAX (0x0000007F) + #define DDRDATA4CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_DEF (0x00000000) + #define DDRDATA4CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_OFF (31) + #define DDRDATA4CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_WID ( 1) + #define DDRDATA4CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_MSK (0x80000000) + #define DDRDATA4CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_MAX (0x00000001) + #define DDRDATA4CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_DEF (0x00000000) + +#define DDRDATA4CH0_CR_DDRCRDATACONTROL0_REG (0x00000874) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_OFF ( 0) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_WID ( 1) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_MSK (0x00000001) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_MAX (0x00000001) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_DEF (0x00000000) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_OFF ( 1) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_WID ( 1) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_MSK (0x00000002) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_MAX (0x00000001) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_DEF (0x00000000) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_OFF ( 2) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_WID ( 1) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_MSK (0x00000004) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_MAX (0x00000001) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_DEF (0x00000000) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_OFF ( 3) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_WID ( 1) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MSK (0x00000008) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MAX (0x00000001) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_DEF (0x00000000) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_TxOn_OFF ( 4) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_TxOn_WID ( 1) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_TxOn_MSK (0x00000010) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_TxOn_MAX (0x00000001) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_TxOn_DEF (0x00000000) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RfOn_OFF ( 5) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RfOn_WID ( 1) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RfOn_MSK (0x00000020) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RfOn_MAX (0x00000001) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RfOn_DEF (0x00000000) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RxPiOn_OFF ( 6) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RxPiOn_WID ( 1) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RxPiOn_MSK (0x00000040) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RxPiOn_MAX (0x00000001) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RxPiOn_DEF (0x00000000) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_TxPiOn_OFF ( 7) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_TxPiOn_WID ( 1) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_TxPiOn_MSK (0x00000080) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_TxPiOn_MAX (0x00000001) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_TxPiOn_DEF (0x00000000) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_OFF ( 8) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_WID ( 1) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_MSK (0x00000100) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_MAX (0x00000001) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_DEF (0x00000000) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_OFF ( 9) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_WID ( 1) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MSK (0x00000200) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MAX (0x00000001) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_DEF (0x00000000) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_TxDisable_OFF (10) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_TxDisable_WID ( 1) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_TxDisable_MSK (0x00000400) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_TxDisable_MAX (0x00000001) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_TxDisable_DEF (0x00000000) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RxDisable_OFF (11) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RxDisable_WID ( 1) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RxDisable_MSK (0x00000800) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RxDisable_MAX (0x00000001) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RxDisable_DEF (0x00000000) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_TxLong_OFF (12) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_TxLong_WID ( 1) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_TxLong_MSK (0x00001000) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_TxLong_MAX (0x00000001) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_TxLong_DEF (0x00000000) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_OFF (13) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_WID ( 2) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_MSK (0x00006000) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_MAX (0x00000003) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_DEF (0x00000000) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RxReadPointer_OFF (15) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RxReadPointer_WID ( 3) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RxReadPointer_MSK (0x00038000) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RxReadPointer_MAX (0x00000007) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RxReadPointer_DEF (0x00000000) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_OFF (18) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_WID ( 1) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_MSK (0x00040000) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_MAX (0x00000001) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_DEF (0x00000000) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_OFF (19) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_WID ( 1) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_MSK (0x00080000) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_MAX (0x00000001) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_DEF (0x00000000) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_ReadRFRd_OFF (20) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_ReadRFRd_WID ( 1) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_ReadRFRd_MSK (0x00100000) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_ReadRFRd_MAX (0x00000001) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_ReadRFRd_DEF (0x00000000) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_ReadRFWr_OFF (21) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_ReadRFWr_WID ( 1) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_ReadRFWr_MSK (0x00200000) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_ReadRFWr_MAX (0x00000001) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_ReadRFWr_DEF (0x00000000) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_ReadRFRank_OFF (22) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_ReadRFRank_WID ( 2) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_ReadRFRank_MSK (0x00C00000) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_ReadRFRank_MAX (0x00000003) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_ReadRFRank_DEF (0x00000000) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_OFF (24) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_WID ( 1) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_MSK (0x01000000) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_MAX (0x00000001) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_DEF (0x00000000) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_OdtSampOff_OFF (25) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_OdtSampOff_WID ( 1) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_OdtSampOff_MSK (0x02000000) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_OdtSampOff_MAX (0x00000001) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_OdtSampOff_DEF (0x00000000) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_OFF (26) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_WID ( 1) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_MSK (0x04000000) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_MAX (0x00000001) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_DEF (0x00000000) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_OFF (27) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_WID ( 1) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MSK (0x08000000) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MAX (0x00000001) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_DEF (0x00000000) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_OFF (28) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_WID ( 1) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_MSK (0x10000000) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_MAX (0x00000001) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_DEF (0x00000000) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_OFF (29) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_WID ( 1) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_MSK (0x20000000) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_MAX (0x00000001) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_DEF (0x00000000) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_OFF (30) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_WID ( 1) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MSK (0x40000000) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MAX (0x00000001) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_DEF (0x00000000) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_OFF (31) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_WID ( 1) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_MSK (0x80000000) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_MAX (0x00000001) + #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_DEF (0x00000000) + +#define DDRDATA4CH0_CR_DDRCRVREFADJUST1_REG (0x00000878) + #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_OFF ( 0) + #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_WID ( 7) + #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_MSK (0x0000007F) + #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_MAX (0x0000007F) + #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_DEF (0x00000000) + #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_OFF ( 7) + #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_WID ( 7) + #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_MSK (0x00003F80) + #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_MAX (0x0000007F) + #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_DEF (0x00000000) + #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_OFF (14) + #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_WID ( 7) + #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_MSK (0x001FC000) + #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_MAX (0x0000007F) + #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_DEF (0x00000000) + #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_OFF (21) + #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_WID ( 1) + #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_MSK (0x00200000) + #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_MAX (0x00000001) + #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_DEF (0x00000000) + #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_OFF (22) + #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_WID ( 1) + #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_MSK (0x00400000) + #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_MAX (0x00000001) + #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_DEF (0x00000000) + #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_OFF (23) + #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_WID ( 1) + #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_MSK (0x00800000) + #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_MAX (0x00000001) + #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_DEF (0x00000000) + #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_OFF (24) + #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_WID ( 2) + #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_MSK (0x03000000) + #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_MAX (0x00000003) + #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_DEF (0x00000000) + #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_OFF (26) + #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_WID ( 1) + #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_MSK (0x04000000) + #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_MAX (0x00000001) + #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_DEF (0x00000000) + #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_Rsvd_OFF (27) + #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_Rsvd_WID ( 2) + #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_Rsvd_MSK (0x18000000) + #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_Rsvd_MAX (0x00000003) + #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_Rsvd_DEF (0x00000000) + #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_caSlowBW_OFF (29) + #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_caSlowBW_WID ( 1) + #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_caSlowBW_MSK (0x20000000) + #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_caSlowBW_MAX (0x00000001) + #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_caSlowBW_DEF (0x00000000) + #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_OFF (30) + #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_WID ( 1) + #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_MSK (0x40000000) + #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_MAX (0x00000001) + #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_DEF (0x00000000) + #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_OFF (31) + #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_WID ( 1) + #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_MSK (0x80000000) + #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_MAX (0x00000001) + #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_DEF (0x00000000) + +#define DDRDATA4CH1_CR_RXTRAINRANK0_REG (0x00000900) + #define DDRDATA4CH1_CR_RXTRAINRANK0_RxRcvEnPi_OFF ( 0) + #define DDRDATA4CH1_CR_RXTRAINRANK0_RxRcvEnPi_WID ( 9) + #define DDRDATA4CH1_CR_RXTRAINRANK0_RxRcvEnPi_MSK (0x000001FF) + #define DDRDATA4CH1_CR_RXTRAINRANK0_RxRcvEnPi_MAX (0x000001FF) + #define DDRDATA4CH1_CR_RXTRAINRANK0_RxDqsPPi_OFF ( 9) + #define DDRDATA4CH1_CR_RXTRAINRANK0_RxDqsPPi_WID ( 6) + #define DDRDATA4CH1_CR_RXTRAINRANK0_RxDqsPPi_MSK (0x00007E00) + #define DDRDATA4CH1_CR_RXTRAINRANK0_RxDqsPPi_MAX (0x0000003F) + #define DDRDATA4CH1_CR_RXTRAINRANK0_RxEq_OFF (15) + #define DDRDATA4CH1_CR_RXTRAINRANK0_RxEq_WID ( 5) + #define DDRDATA4CH1_CR_RXTRAINRANK0_RxEq_MSK (0x000F8000) + #define DDRDATA4CH1_CR_RXTRAINRANK0_RxEq_MAX (0x0000001F) + #define DDRDATA4CH1_CR_RXTRAINRANK0_RxDqsNPi_OFF (20) + #define DDRDATA4CH1_CR_RXTRAINRANK0_RxDqsNPi_WID ( 6) + #define DDRDATA4CH1_CR_RXTRAINRANK0_RxDqsNPi_MSK (0x03F00000) + #define DDRDATA4CH1_CR_RXTRAINRANK0_RxDqsNPi_MAX (0x0000003F) + #define DDRDATA4CH1_CR_RXTRAINRANK0_RxVref_OFF (26) + #define DDRDATA4CH1_CR_RXTRAINRANK0_RxVref_WID ( 6) + #define DDRDATA4CH1_CR_RXTRAINRANK0_RxVref_MSK (0xFC000000) + #define DDRDATA4CH1_CR_RXTRAINRANK0_RxVref_MAX (0x0000003F) + +#define DDRDATA4CH1_CR_RXTRAINRANK1_REG (0x00000904) + #define DDRDATA4CH1_CR_RXTRAINRANK1_RxRcvEnPi_OFF ( 0) + #define DDRDATA4CH1_CR_RXTRAINRANK1_RxRcvEnPi_WID ( 9) + #define DDRDATA4CH1_CR_RXTRAINRANK1_RxRcvEnPi_MSK (0x000001FF) + #define DDRDATA4CH1_CR_RXTRAINRANK1_RxRcvEnPi_MAX (0x000001FF) + #define DDRDATA4CH1_CR_RXTRAINRANK1_RxDqsPPi_OFF ( 9) + #define DDRDATA4CH1_CR_RXTRAINRANK1_RxDqsPPi_WID ( 6) + #define DDRDATA4CH1_CR_RXTRAINRANK1_RxDqsPPi_MSK (0x00007E00) + #define DDRDATA4CH1_CR_RXTRAINRANK1_RxDqsPPi_MAX (0x0000003F) + #define DDRDATA4CH1_CR_RXTRAINRANK1_RxEq_OFF (15) + #define DDRDATA4CH1_CR_RXTRAINRANK1_RxEq_WID ( 5) + #define DDRDATA4CH1_CR_RXTRAINRANK1_RxEq_MSK (0x000F8000) + #define DDRDATA4CH1_CR_RXTRAINRANK1_RxEq_MAX (0x0000001F) + #define DDRDATA4CH1_CR_RXTRAINRANK1_RxDqsNPi_OFF (20) + #define DDRDATA4CH1_CR_RXTRAINRANK1_RxDqsNPi_WID ( 6) + #define DDRDATA4CH1_CR_RXTRAINRANK1_RxDqsNPi_MSK (0x03F00000) + #define DDRDATA4CH1_CR_RXTRAINRANK1_RxDqsNPi_MAX (0x0000003F) + #define DDRDATA4CH1_CR_RXTRAINRANK1_RxVref_OFF (26) + #define DDRDATA4CH1_CR_RXTRAINRANK1_RxVref_WID ( 6) + #define DDRDATA4CH1_CR_RXTRAINRANK1_RxVref_MSK (0xFC000000) + #define DDRDATA4CH1_CR_RXTRAINRANK1_RxVref_MAX (0x0000003F) + +#define DDRDATA4CH1_CR_RXTRAINRANK2_REG (0x00000908) + #define DDRDATA4CH1_CR_RXTRAINRANK2_RxRcvEnPi_OFF ( 0) + #define DDRDATA4CH1_CR_RXTRAINRANK2_RxRcvEnPi_WID ( 9) + #define DDRDATA4CH1_CR_RXTRAINRANK2_RxRcvEnPi_MSK (0x000001FF) + #define DDRDATA4CH1_CR_RXTRAINRANK2_RxRcvEnPi_MAX (0x000001FF) + #define DDRDATA4CH1_CR_RXTRAINRANK2_RxDqsPPi_OFF ( 9) + #define DDRDATA4CH1_CR_RXTRAINRANK2_RxDqsPPi_WID ( 6) + #define DDRDATA4CH1_CR_RXTRAINRANK2_RxDqsPPi_MSK (0x00007E00) + #define DDRDATA4CH1_CR_RXTRAINRANK2_RxDqsPPi_MAX (0x0000003F) + #define DDRDATA4CH1_CR_RXTRAINRANK2_RxEq_OFF (15) + #define DDRDATA4CH1_CR_RXTRAINRANK2_RxEq_WID ( 5) + #define DDRDATA4CH1_CR_RXTRAINRANK2_RxEq_MSK (0x000F8000) + #define DDRDATA4CH1_CR_RXTRAINRANK2_RxEq_MAX (0x0000001F) + #define DDRDATA4CH1_CR_RXTRAINRANK2_RxDqsNPi_OFF (20) + #define DDRDATA4CH1_CR_RXTRAINRANK2_RxDqsNPi_WID ( 6) + #define DDRDATA4CH1_CR_RXTRAINRANK2_RxDqsNPi_MSK (0x03F00000) + #define DDRDATA4CH1_CR_RXTRAINRANK2_RxDqsNPi_MAX (0x0000003F) + #define DDRDATA4CH1_CR_RXTRAINRANK2_RxVref_OFF (26) + #define DDRDATA4CH1_CR_RXTRAINRANK2_RxVref_WID ( 6) + #define DDRDATA4CH1_CR_RXTRAINRANK2_RxVref_MSK (0xFC000000) + #define DDRDATA4CH1_CR_RXTRAINRANK2_RxVref_MAX (0x0000003F) + +#define DDRDATA4CH1_CR_RXTRAINRANK3_REG (0x0000090C) + #define DDRDATA4CH1_CR_RXTRAINRANK3_RxRcvEnPi_OFF ( 0) + #define DDRDATA4CH1_CR_RXTRAINRANK3_RxRcvEnPi_WID ( 9) + #define DDRDATA4CH1_CR_RXTRAINRANK3_RxRcvEnPi_MSK (0x000001FF) + #define DDRDATA4CH1_CR_RXTRAINRANK3_RxRcvEnPi_MAX (0x000001FF) + #define DDRDATA4CH1_CR_RXTRAINRANK3_RxDqsPPi_OFF ( 9) + #define DDRDATA4CH1_CR_RXTRAINRANK3_RxDqsPPi_WID ( 6) + #define DDRDATA4CH1_CR_RXTRAINRANK3_RxDqsPPi_MSK (0x00007E00) + #define DDRDATA4CH1_CR_RXTRAINRANK3_RxDqsPPi_MAX (0x0000003F) + #define DDRDATA4CH1_CR_RXTRAINRANK3_RxEq_OFF (15) + #define DDRDATA4CH1_CR_RXTRAINRANK3_RxEq_WID ( 5) + #define DDRDATA4CH1_CR_RXTRAINRANK3_RxEq_MSK (0x000F8000) + #define DDRDATA4CH1_CR_RXTRAINRANK3_RxEq_MAX (0x0000001F) + #define DDRDATA4CH1_CR_RXTRAINRANK3_RxDqsNPi_OFF (20) + #define DDRDATA4CH1_CR_RXTRAINRANK3_RxDqsNPi_WID ( 6) + #define DDRDATA4CH1_CR_RXTRAINRANK3_RxDqsNPi_MSK (0x03F00000) + #define DDRDATA4CH1_CR_RXTRAINRANK3_RxDqsNPi_MAX (0x0000003F) + #define DDRDATA4CH1_CR_RXTRAINRANK3_RxVref_OFF (26) + #define DDRDATA4CH1_CR_RXTRAINRANK3_RxVref_WID ( 6) + #define DDRDATA4CH1_CR_RXTRAINRANK3_RxVref_MSK (0xFC000000) + #define DDRDATA4CH1_CR_RXTRAINRANK3_RxVref_MAX (0x0000003F) + +#define DDRDATA4CH1_CR_RXPERBITRANK0_REG (0x00000910) + #define DDRDATA4CH1_CR_RXPERBITRANK0_Lane0_OFF ( 0) + #define DDRDATA4CH1_CR_RXPERBITRANK0_Lane0_WID ( 4) + #define DDRDATA4CH1_CR_RXPERBITRANK0_Lane0_MSK (0x0000000F) + #define DDRDATA4CH1_CR_RXPERBITRANK0_Lane0_MAX (0x0000000F) + #define DDRDATA4CH1_CR_RXPERBITRANK0_Lane1_OFF ( 4) + #define DDRDATA4CH1_CR_RXPERBITRANK0_Lane1_WID ( 4) + #define DDRDATA4CH1_CR_RXPERBITRANK0_Lane1_MSK (0x000000F0) + #define DDRDATA4CH1_CR_RXPERBITRANK0_Lane1_MAX (0x0000000F) + #define DDRDATA4CH1_CR_RXPERBITRANK0_Lane2_OFF ( 8) + #define DDRDATA4CH1_CR_RXPERBITRANK0_Lane2_WID ( 4) + #define DDRDATA4CH1_CR_RXPERBITRANK0_Lane2_MSK (0x00000F00) + #define DDRDATA4CH1_CR_RXPERBITRANK0_Lane2_MAX (0x0000000F) + #define DDRDATA4CH1_CR_RXPERBITRANK0_Lane3_OFF (12) + #define DDRDATA4CH1_CR_RXPERBITRANK0_Lane3_WID ( 4) + #define DDRDATA4CH1_CR_RXPERBITRANK0_Lane3_MSK (0x0000F000) + #define DDRDATA4CH1_CR_RXPERBITRANK0_Lane3_MAX (0x0000000F) + #define DDRDATA4CH1_CR_RXPERBITRANK0_Lane4_OFF (16) + #define DDRDATA4CH1_CR_RXPERBITRANK0_Lane4_WID ( 4) + #define DDRDATA4CH1_CR_RXPERBITRANK0_Lane4_MSK (0x000F0000) + #define DDRDATA4CH1_CR_RXPERBITRANK0_Lane4_MAX (0x0000000F) + #define DDRDATA4CH1_CR_RXPERBITRANK0_Lane5_OFF (20) + #define DDRDATA4CH1_CR_RXPERBITRANK0_Lane5_WID ( 4) + #define DDRDATA4CH1_CR_RXPERBITRANK0_Lane5_MSK (0x00F00000) + #define DDRDATA4CH1_CR_RXPERBITRANK0_Lane5_MAX (0x0000000F) + #define DDRDATA4CH1_CR_RXPERBITRANK0_Lane6_OFF (24) + #define DDRDATA4CH1_CR_RXPERBITRANK0_Lane6_WID ( 4) + #define DDRDATA4CH1_CR_RXPERBITRANK0_Lane6_MSK (0x0F000000) + #define DDRDATA4CH1_CR_RXPERBITRANK0_Lane6_MAX (0x0000000F) + #define DDRDATA4CH1_CR_RXPERBITRANK0_Lane7_OFF (28) + #define DDRDATA4CH1_CR_RXPERBITRANK0_Lane7_WID ( 4) + #define DDRDATA4CH1_CR_RXPERBITRANK0_Lane7_MSK (0xF0000000) + #define DDRDATA4CH1_CR_RXPERBITRANK0_Lane7_MAX (0x0000000F) + +#define DDRDATA4CH1_CR_RXPERBITRANK1_REG (0x00000914) + #define DDRDATA4CH1_CR_RXPERBITRANK1_Lane0_OFF ( 0) + #define DDRDATA4CH1_CR_RXPERBITRANK1_Lane0_WID ( 4) + #define DDRDATA4CH1_CR_RXPERBITRANK1_Lane0_MSK (0x0000000F) + #define DDRDATA4CH1_CR_RXPERBITRANK1_Lane0_MAX (0x0000000F) + #define DDRDATA4CH1_CR_RXPERBITRANK1_Lane1_OFF ( 4) + #define DDRDATA4CH1_CR_RXPERBITRANK1_Lane1_WID ( 4) + #define DDRDATA4CH1_CR_RXPERBITRANK1_Lane1_MSK (0x000000F0) + #define DDRDATA4CH1_CR_RXPERBITRANK1_Lane1_MAX (0x0000000F) + #define DDRDATA4CH1_CR_RXPERBITRANK1_Lane2_OFF ( 8) + #define DDRDATA4CH1_CR_RXPERBITRANK1_Lane2_WID ( 4) + #define DDRDATA4CH1_CR_RXPERBITRANK1_Lane2_MSK (0x00000F00) + #define DDRDATA4CH1_CR_RXPERBITRANK1_Lane2_MAX (0x0000000F) + #define DDRDATA4CH1_CR_RXPERBITRANK1_Lane3_OFF (12) + #define DDRDATA4CH1_CR_RXPERBITRANK1_Lane3_WID ( 4) + #define DDRDATA4CH1_CR_RXPERBITRANK1_Lane3_MSK (0x0000F000) + #define DDRDATA4CH1_CR_RXPERBITRANK1_Lane3_MAX (0x0000000F) + #define DDRDATA4CH1_CR_RXPERBITRANK1_Lane4_OFF (16) + #define DDRDATA4CH1_CR_RXPERBITRANK1_Lane4_WID ( 4) + #define DDRDATA4CH1_CR_RXPERBITRANK1_Lane4_MSK (0x000F0000) + #define DDRDATA4CH1_CR_RXPERBITRANK1_Lane4_MAX (0x0000000F) + #define DDRDATA4CH1_CR_RXPERBITRANK1_Lane5_OFF (20) + #define DDRDATA4CH1_CR_RXPERBITRANK1_Lane5_WID ( 4) + #define DDRDATA4CH1_CR_RXPERBITRANK1_Lane5_MSK (0x00F00000) + #define DDRDATA4CH1_CR_RXPERBITRANK1_Lane5_MAX (0x0000000F) + #define DDRDATA4CH1_CR_RXPERBITRANK1_Lane6_OFF (24) + #define DDRDATA4CH1_CR_RXPERBITRANK1_Lane6_WID ( 4) + #define DDRDATA4CH1_CR_RXPERBITRANK1_Lane6_MSK (0x0F000000) + #define DDRDATA4CH1_CR_RXPERBITRANK1_Lane6_MAX (0x0000000F) + #define DDRDATA4CH1_CR_RXPERBITRANK1_Lane7_OFF (28) + #define DDRDATA4CH1_CR_RXPERBITRANK1_Lane7_WID ( 4) + #define DDRDATA4CH1_CR_RXPERBITRANK1_Lane7_MSK (0xF0000000) + #define DDRDATA4CH1_CR_RXPERBITRANK1_Lane7_MAX (0x0000000F) + +#define DDRDATA4CH1_CR_RXPERBITRANK2_REG (0x00000918) + #define DDRDATA4CH1_CR_RXPERBITRANK2_Lane0_OFF ( 0) + #define DDRDATA4CH1_CR_RXPERBITRANK2_Lane0_WID ( 4) + #define DDRDATA4CH1_CR_RXPERBITRANK2_Lane0_MSK (0x0000000F) + #define DDRDATA4CH1_CR_RXPERBITRANK2_Lane0_MAX (0x0000000F) + #define DDRDATA4CH1_CR_RXPERBITRANK2_Lane1_OFF ( 4) + #define DDRDATA4CH1_CR_RXPERBITRANK2_Lane1_WID ( 4) + #define DDRDATA4CH1_CR_RXPERBITRANK2_Lane1_MSK (0x000000F0) + #define DDRDATA4CH1_CR_RXPERBITRANK2_Lane1_MAX (0x0000000F) + #define DDRDATA4CH1_CR_RXPERBITRANK2_Lane2_OFF ( 8) + #define DDRDATA4CH1_CR_RXPERBITRANK2_Lane2_WID ( 4) + #define DDRDATA4CH1_CR_RXPERBITRANK2_Lane2_MSK (0x00000F00) + #define DDRDATA4CH1_CR_RXPERBITRANK2_Lane2_MAX (0x0000000F) + #define DDRDATA4CH1_CR_RXPERBITRANK2_Lane3_OFF (12) + #define DDRDATA4CH1_CR_RXPERBITRANK2_Lane3_WID ( 4) + #define DDRDATA4CH1_CR_RXPERBITRANK2_Lane3_MSK (0x0000F000) + #define DDRDATA4CH1_CR_RXPERBITRANK2_Lane3_MAX (0x0000000F) + #define DDRDATA4CH1_CR_RXPERBITRANK2_Lane4_OFF (16) + #define DDRDATA4CH1_CR_RXPERBITRANK2_Lane4_WID ( 4) + #define DDRDATA4CH1_CR_RXPERBITRANK2_Lane4_MSK (0x000F0000) + #define DDRDATA4CH1_CR_RXPERBITRANK2_Lane4_MAX (0x0000000F) + #define DDRDATA4CH1_CR_RXPERBITRANK2_Lane5_OFF (20) + #define DDRDATA4CH1_CR_RXPERBITRANK2_Lane5_WID ( 4) + #define DDRDATA4CH1_CR_RXPERBITRANK2_Lane5_MSK (0x00F00000) + #define DDRDATA4CH1_CR_RXPERBITRANK2_Lane5_MAX (0x0000000F) + #define DDRDATA4CH1_CR_RXPERBITRANK2_Lane6_OFF (24) + #define DDRDATA4CH1_CR_RXPERBITRANK2_Lane6_WID ( 4) + #define DDRDATA4CH1_CR_RXPERBITRANK2_Lane6_MSK (0x0F000000) + #define DDRDATA4CH1_CR_RXPERBITRANK2_Lane6_MAX (0x0000000F) + #define DDRDATA4CH1_CR_RXPERBITRANK2_Lane7_OFF (28) + #define DDRDATA4CH1_CR_RXPERBITRANK2_Lane7_WID ( 4) + #define DDRDATA4CH1_CR_RXPERBITRANK2_Lane7_MSK (0xF0000000) + #define DDRDATA4CH1_CR_RXPERBITRANK2_Lane7_MAX (0x0000000F) + +#define DDRDATA4CH1_CR_RXPERBITRANK3_REG (0x0000091C) + #define DDRDATA4CH1_CR_RXPERBITRANK3_Lane0_OFF ( 0) + #define DDRDATA4CH1_CR_RXPERBITRANK3_Lane0_WID ( 4) + #define DDRDATA4CH1_CR_RXPERBITRANK3_Lane0_MSK (0x0000000F) + #define DDRDATA4CH1_CR_RXPERBITRANK3_Lane0_MAX (0x0000000F) + #define DDRDATA4CH1_CR_RXPERBITRANK3_Lane1_OFF ( 4) + #define DDRDATA4CH1_CR_RXPERBITRANK3_Lane1_WID ( 4) + #define DDRDATA4CH1_CR_RXPERBITRANK3_Lane1_MSK (0x000000F0) + #define DDRDATA4CH1_CR_RXPERBITRANK3_Lane1_MAX (0x0000000F) + #define DDRDATA4CH1_CR_RXPERBITRANK3_Lane2_OFF ( 8) + #define DDRDATA4CH1_CR_RXPERBITRANK3_Lane2_WID ( 4) + #define DDRDATA4CH1_CR_RXPERBITRANK3_Lane2_MSK (0x00000F00) + #define DDRDATA4CH1_CR_RXPERBITRANK3_Lane2_MAX (0x0000000F) + #define DDRDATA4CH1_CR_RXPERBITRANK3_Lane3_OFF (12) + #define DDRDATA4CH1_CR_RXPERBITRANK3_Lane3_WID ( 4) + #define DDRDATA4CH1_CR_RXPERBITRANK3_Lane3_MSK (0x0000F000) + #define DDRDATA4CH1_CR_RXPERBITRANK3_Lane3_MAX (0x0000000F) + #define DDRDATA4CH1_CR_RXPERBITRANK3_Lane4_OFF (16) + #define DDRDATA4CH1_CR_RXPERBITRANK3_Lane4_WID ( 4) + #define DDRDATA4CH1_CR_RXPERBITRANK3_Lane4_MSK (0x000F0000) + #define DDRDATA4CH1_CR_RXPERBITRANK3_Lane4_MAX (0x0000000F) + #define DDRDATA4CH1_CR_RXPERBITRANK3_Lane5_OFF (20) + #define DDRDATA4CH1_CR_RXPERBITRANK3_Lane5_WID ( 4) + #define DDRDATA4CH1_CR_RXPERBITRANK3_Lane5_MSK (0x00F00000) + #define DDRDATA4CH1_CR_RXPERBITRANK3_Lane5_MAX (0x0000000F) + #define DDRDATA4CH1_CR_RXPERBITRANK3_Lane6_OFF (24) + #define DDRDATA4CH1_CR_RXPERBITRANK3_Lane6_WID ( 4) + #define DDRDATA4CH1_CR_RXPERBITRANK3_Lane6_MSK (0x0F000000) + #define DDRDATA4CH1_CR_RXPERBITRANK3_Lane6_MAX (0x0000000F) + #define DDRDATA4CH1_CR_RXPERBITRANK3_Lane7_OFF (28) + #define DDRDATA4CH1_CR_RXPERBITRANK3_Lane7_WID ( 4) + #define DDRDATA4CH1_CR_RXPERBITRANK3_Lane7_MSK (0xF0000000) + #define DDRDATA4CH1_CR_RXPERBITRANK3_Lane7_MAX (0x0000000F) + +#define DDRDATA4CH1_CR_TXTRAINRANK0_REG (0x00000920) + #define DDRDATA4CH1_CR_TXTRAINRANK0_TxDqDelay_OFF ( 0) + #define DDRDATA4CH1_CR_TXTRAINRANK0_TxDqDelay_WID ( 9) + #define DDRDATA4CH1_CR_TXTRAINRANK0_TxDqDelay_MSK (0x000001FF) + #define DDRDATA4CH1_CR_TXTRAINRANK0_TxDqDelay_MAX (0x000001FF) + #define DDRDATA4CH1_CR_TXTRAINRANK0_TxDqsDelay_OFF ( 9) + #define DDRDATA4CH1_CR_TXTRAINRANK0_TxDqsDelay_WID ( 9) + #define DDRDATA4CH1_CR_TXTRAINRANK0_TxDqsDelay_MSK (0x0003FE00) + #define DDRDATA4CH1_CR_TXTRAINRANK0_TxDqsDelay_MAX (0x000001FF) + #define DDRDATA4CH1_CR_TXTRAINRANK0_Spare0_OFF (18) + #define DDRDATA4CH1_CR_TXTRAINRANK0_Spare0_WID ( 2) + #define DDRDATA4CH1_CR_TXTRAINRANK0_Spare0_MSK (0x000C0000) + #define DDRDATA4CH1_CR_TXTRAINRANK0_Spare0_MAX (0x00000003) + #define DDRDATA4CH1_CR_TXTRAINRANK0_TxEqualization_OFF (20) + #define DDRDATA4CH1_CR_TXTRAINRANK0_TxEqualization_WID ( 6) + #define DDRDATA4CH1_CR_TXTRAINRANK0_TxEqualization_MSK (0x03F00000) + #define DDRDATA4CH1_CR_TXTRAINRANK0_TxEqualization_MAX (0x0000003F) + #define DDRDATA4CH1_CR_TXTRAINRANK0_Spare1_OFF (26) + #define DDRDATA4CH1_CR_TXTRAINRANK0_Spare1_WID ( 6) + #define DDRDATA4CH1_CR_TXTRAINRANK0_Spare1_MSK (0xFC000000) + #define DDRDATA4CH1_CR_TXTRAINRANK0_Spare1_MAX (0x0000003F) + +#define DDRDATA4CH1_CR_TXTRAINRANK1_REG (0x00000924) + #define DDRDATA4CH1_CR_TXTRAINRANK1_TxDqDelay_OFF ( 0) + #define DDRDATA4CH1_CR_TXTRAINRANK1_TxDqDelay_WID ( 9) + #define DDRDATA4CH1_CR_TXTRAINRANK1_TxDqDelay_MSK (0x000001FF) + #define DDRDATA4CH1_CR_TXTRAINRANK1_TxDqDelay_MAX (0x000001FF) + #define DDRDATA4CH1_CR_TXTRAINRANK1_TxDqsDelay_OFF ( 9) + #define DDRDATA4CH1_CR_TXTRAINRANK1_TxDqsDelay_WID ( 9) + #define DDRDATA4CH1_CR_TXTRAINRANK1_TxDqsDelay_MSK (0x0003FE00) + #define DDRDATA4CH1_CR_TXTRAINRANK1_TxDqsDelay_MAX (0x000001FF) + #define DDRDATA4CH1_CR_TXTRAINRANK1_Spare0_OFF (18) + #define DDRDATA4CH1_CR_TXTRAINRANK1_Spare0_WID ( 2) + #define DDRDATA4CH1_CR_TXTRAINRANK1_Spare0_MSK (0x000C0000) + #define DDRDATA4CH1_CR_TXTRAINRANK1_Spare0_MAX (0x00000003) + #define DDRDATA4CH1_CR_TXTRAINRANK1_TxEqualization_OFF (20) + #define DDRDATA4CH1_CR_TXTRAINRANK1_TxEqualization_WID ( 6) + #define DDRDATA4CH1_CR_TXTRAINRANK1_TxEqualization_MSK (0x03F00000) + #define DDRDATA4CH1_CR_TXTRAINRANK1_TxEqualization_MAX (0x0000003F) + #define DDRDATA4CH1_CR_TXTRAINRANK1_Spare1_OFF (26) + #define DDRDATA4CH1_CR_TXTRAINRANK1_Spare1_WID ( 6) + #define DDRDATA4CH1_CR_TXTRAINRANK1_Spare1_MSK (0xFC000000) + #define DDRDATA4CH1_CR_TXTRAINRANK1_Spare1_MAX (0x0000003F) + +#define DDRDATA4CH1_CR_TXTRAINRANK2_REG (0x00000928) + #define DDRDATA4CH1_CR_TXTRAINRANK2_TxDqDelay_OFF ( 0) + #define DDRDATA4CH1_CR_TXTRAINRANK2_TxDqDelay_WID ( 9) + #define DDRDATA4CH1_CR_TXTRAINRANK2_TxDqDelay_MSK (0x000001FF) + #define DDRDATA4CH1_CR_TXTRAINRANK2_TxDqDelay_MAX (0x000001FF) + #define DDRDATA4CH1_CR_TXTRAINRANK2_TxDqsDelay_OFF ( 9) + #define DDRDATA4CH1_CR_TXTRAINRANK2_TxDqsDelay_WID ( 9) + #define DDRDATA4CH1_CR_TXTRAINRANK2_TxDqsDelay_MSK (0x0003FE00) + #define DDRDATA4CH1_CR_TXTRAINRANK2_TxDqsDelay_MAX (0x000001FF) + #define DDRDATA4CH1_CR_TXTRAINRANK2_Spare0_OFF (18) + #define DDRDATA4CH1_CR_TXTRAINRANK2_Spare0_WID ( 2) + #define DDRDATA4CH1_CR_TXTRAINRANK2_Spare0_MSK (0x000C0000) + #define DDRDATA4CH1_CR_TXTRAINRANK2_Spare0_MAX (0x00000003) + #define DDRDATA4CH1_CR_TXTRAINRANK2_TxEqualization_OFF (20) + #define DDRDATA4CH1_CR_TXTRAINRANK2_TxEqualization_WID ( 6) + #define DDRDATA4CH1_CR_TXTRAINRANK2_TxEqualization_MSK (0x03F00000) + #define DDRDATA4CH1_CR_TXTRAINRANK2_TxEqualization_MAX (0x0000003F) + #define DDRDATA4CH1_CR_TXTRAINRANK2_Spare1_OFF (26) + #define DDRDATA4CH1_CR_TXTRAINRANK2_Spare1_WID ( 6) + #define DDRDATA4CH1_CR_TXTRAINRANK2_Spare1_MSK (0xFC000000) + #define DDRDATA4CH1_CR_TXTRAINRANK2_Spare1_MAX (0x0000003F) + +#define DDRDATA4CH1_CR_TXTRAINRANK3_REG (0x0000092C) + #define DDRDATA4CH1_CR_TXTRAINRANK3_TxDqDelay_OFF ( 0) + #define DDRDATA4CH1_CR_TXTRAINRANK3_TxDqDelay_WID ( 9) + #define DDRDATA4CH1_CR_TXTRAINRANK3_TxDqDelay_MSK (0x000001FF) + #define DDRDATA4CH1_CR_TXTRAINRANK3_TxDqDelay_MAX (0x000001FF) + #define DDRDATA4CH1_CR_TXTRAINRANK3_TxDqsDelay_OFF ( 9) + #define DDRDATA4CH1_CR_TXTRAINRANK3_TxDqsDelay_WID ( 9) + #define DDRDATA4CH1_CR_TXTRAINRANK3_TxDqsDelay_MSK (0x0003FE00) + #define DDRDATA4CH1_CR_TXTRAINRANK3_TxDqsDelay_MAX (0x000001FF) + #define DDRDATA4CH1_CR_TXTRAINRANK3_Spare0_OFF (18) + #define DDRDATA4CH1_CR_TXTRAINRANK3_Spare0_WID ( 2) + #define DDRDATA4CH1_CR_TXTRAINRANK3_Spare0_MSK (0x000C0000) + #define DDRDATA4CH1_CR_TXTRAINRANK3_Spare0_MAX (0x00000003) + #define DDRDATA4CH1_CR_TXTRAINRANK3_TxEqualization_OFF (20) + #define DDRDATA4CH1_CR_TXTRAINRANK3_TxEqualization_WID ( 6) + #define DDRDATA4CH1_CR_TXTRAINRANK3_TxEqualization_MSK (0x03F00000) + #define DDRDATA4CH1_CR_TXTRAINRANK3_TxEqualization_MAX (0x0000003F) + #define DDRDATA4CH1_CR_TXTRAINRANK3_Spare1_OFF (26) + #define DDRDATA4CH1_CR_TXTRAINRANK3_Spare1_WID ( 6) + #define DDRDATA4CH1_CR_TXTRAINRANK3_Spare1_MSK (0xFC000000) + #define DDRDATA4CH1_CR_TXTRAINRANK3_Spare1_MAX (0x0000003F) + +#define DDRDATA4CH1_CR_TXPERBITRANK0_REG (0x00000930) + #define DDRDATA4CH1_CR_TXPERBITRANK0_Lane0_OFF ( 0) + #define DDRDATA4CH1_CR_TXPERBITRANK0_Lane0_WID ( 4) + #define DDRDATA4CH1_CR_TXPERBITRANK0_Lane0_MSK (0x0000000F) + #define DDRDATA4CH1_CR_TXPERBITRANK0_Lane0_MAX (0x0000000F) + #define DDRDATA4CH1_CR_TXPERBITRANK0_Lane1_OFF ( 4) + #define DDRDATA4CH1_CR_TXPERBITRANK0_Lane1_WID ( 4) + #define DDRDATA4CH1_CR_TXPERBITRANK0_Lane1_MSK (0x000000F0) + #define DDRDATA4CH1_CR_TXPERBITRANK0_Lane1_MAX (0x0000000F) + #define DDRDATA4CH1_CR_TXPERBITRANK0_Lane2_OFF ( 8) + #define DDRDATA4CH1_CR_TXPERBITRANK0_Lane2_WID ( 4) + #define DDRDATA4CH1_CR_TXPERBITRANK0_Lane2_MSK (0x00000F00) + #define DDRDATA4CH1_CR_TXPERBITRANK0_Lane2_MAX (0x0000000F) + #define DDRDATA4CH1_CR_TXPERBITRANK0_Lane3_OFF (12) + #define DDRDATA4CH1_CR_TXPERBITRANK0_Lane3_WID ( 4) + #define DDRDATA4CH1_CR_TXPERBITRANK0_Lane3_MSK (0x0000F000) + #define DDRDATA4CH1_CR_TXPERBITRANK0_Lane3_MAX (0x0000000F) + #define DDRDATA4CH1_CR_TXPERBITRANK0_Lane4_OFF (16) + #define DDRDATA4CH1_CR_TXPERBITRANK0_Lane4_WID ( 4) + #define DDRDATA4CH1_CR_TXPERBITRANK0_Lane4_MSK (0x000F0000) + #define DDRDATA4CH1_CR_TXPERBITRANK0_Lane4_MAX (0x0000000F) + #define DDRDATA4CH1_CR_TXPERBITRANK0_Lane5_OFF (20) + #define DDRDATA4CH1_CR_TXPERBITRANK0_Lane5_WID ( 4) + #define DDRDATA4CH1_CR_TXPERBITRANK0_Lane5_MSK (0x00F00000) + #define DDRDATA4CH1_CR_TXPERBITRANK0_Lane5_MAX (0x0000000F) + #define DDRDATA4CH1_CR_TXPERBITRANK0_Lane6_OFF (24) + #define DDRDATA4CH1_CR_TXPERBITRANK0_Lane6_WID ( 4) + #define DDRDATA4CH1_CR_TXPERBITRANK0_Lane6_MSK (0x0F000000) + #define DDRDATA4CH1_CR_TXPERBITRANK0_Lane6_MAX (0x0000000F) + #define DDRDATA4CH1_CR_TXPERBITRANK0_Lane7_OFF (28) + #define DDRDATA4CH1_CR_TXPERBITRANK0_Lane7_WID ( 4) + #define DDRDATA4CH1_CR_TXPERBITRANK0_Lane7_MSK (0xF0000000) + #define DDRDATA4CH1_CR_TXPERBITRANK0_Lane7_MAX (0x0000000F) + +#define DDRDATA4CH1_CR_TXPERBITRANK1_REG (0x00000934) + #define DDRDATA4CH1_CR_TXPERBITRANK1_Lane0_OFF ( 0) + #define DDRDATA4CH1_CR_TXPERBITRANK1_Lane0_WID ( 4) + #define DDRDATA4CH1_CR_TXPERBITRANK1_Lane0_MSK (0x0000000F) + #define DDRDATA4CH1_CR_TXPERBITRANK1_Lane0_MAX (0x0000000F) + #define DDRDATA4CH1_CR_TXPERBITRANK1_Lane1_OFF ( 4) + #define DDRDATA4CH1_CR_TXPERBITRANK1_Lane1_WID ( 4) + #define DDRDATA4CH1_CR_TXPERBITRANK1_Lane1_MSK (0x000000F0) + #define DDRDATA4CH1_CR_TXPERBITRANK1_Lane1_MAX (0x0000000F) + #define DDRDATA4CH1_CR_TXPERBITRANK1_Lane2_OFF ( 8) + #define DDRDATA4CH1_CR_TXPERBITRANK1_Lane2_WID ( 4) + #define DDRDATA4CH1_CR_TXPERBITRANK1_Lane2_MSK (0x00000F00) + #define DDRDATA4CH1_CR_TXPERBITRANK1_Lane2_MAX (0x0000000F) + #define DDRDATA4CH1_CR_TXPERBITRANK1_Lane3_OFF (12) + #define DDRDATA4CH1_CR_TXPERBITRANK1_Lane3_WID ( 4) + #define DDRDATA4CH1_CR_TXPERBITRANK1_Lane3_MSK (0x0000F000) + #define DDRDATA4CH1_CR_TXPERBITRANK1_Lane3_MAX (0x0000000F) + #define DDRDATA4CH1_CR_TXPERBITRANK1_Lane4_OFF (16) + #define DDRDATA4CH1_CR_TXPERBITRANK1_Lane4_WID ( 4) + #define DDRDATA4CH1_CR_TXPERBITRANK1_Lane4_MSK (0x000F0000) + #define DDRDATA4CH1_CR_TXPERBITRANK1_Lane4_MAX (0x0000000F) + #define DDRDATA4CH1_CR_TXPERBITRANK1_Lane5_OFF (20) + #define DDRDATA4CH1_CR_TXPERBITRANK1_Lane5_WID ( 4) + #define DDRDATA4CH1_CR_TXPERBITRANK1_Lane5_MSK (0x00F00000) + #define DDRDATA4CH1_CR_TXPERBITRANK1_Lane5_MAX (0x0000000F) + #define DDRDATA4CH1_CR_TXPERBITRANK1_Lane6_OFF (24) + #define DDRDATA4CH1_CR_TXPERBITRANK1_Lane6_WID ( 4) + #define DDRDATA4CH1_CR_TXPERBITRANK1_Lane6_MSK (0x0F000000) + #define DDRDATA4CH1_CR_TXPERBITRANK1_Lane6_MAX (0x0000000F) + #define DDRDATA4CH1_CR_TXPERBITRANK1_Lane7_OFF (28) + #define DDRDATA4CH1_CR_TXPERBITRANK1_Lane7_WID ( 4) + #define DDRDATA4CH1_CR_TXPERBITRANK1_Lane7_MSK (0xF0000000) + #define DDRDATA4CH1_CR_TXPERBITRANK1_Lane7_MAX (0x0000000F) + +#define DDRDATA4CH1_CR_TXPERBITRANK2_REG (0x00000938) + #define DDRDATA4CH1_CR_TXPERBITRANK2_Lane0_OFF ( 0) + #define DDRDATA4CH1_CR_TXPERBITRANK2_Lane0_WID ( 4) + #define DDRDATA4CH1_CR_TXPERBITRANK2_Lane0_MSK (0x0000000F) + #define DDRDATA4CH1_CR_TXPERBITRANK2_Lane0_MAX (0x0000000F) + #define DDRDATA4CH1_CR_TXPERBITRANK2_Lane1_OFF ( 4) + #define DDRDATA4CH1_CR_TXPERBITRANK2_Lane1_WID ( 4) + #define DDRDATA4CH1_CR_TXPERBITRANK2_Lane1_MSK (0x000000F0) + #define DDRDATA4CH1_CR_TXPERBITRANK2_Lane1_MAX (0x0000000F) + #define DDRDATA4CH1_CR_TXPERBITRANK2_Lane2_OFF ( 8) + #define DDRDATA4CH1_CR_TXPERBITRANK2_Lane2_WID ( 4) + #define DDRDATA4CH1_CR_TXPERBITRANK2_Lane2_MSK (0x00000F00) + #define DDRDATA4CH1_CR_TXPERBITRANK2_Lane2_MAX (0x0000000F) + #define DDRDATA4CH1_CR_TXPERBITRANK2_Lane3_OFF (12) + #define DDRDATA4CH1_CR_TXPERBITRANK2_Lane3_WID ( 4) + #define DDRDATA4CH1_CR_TXPERBITRANK2_Lane3_MSK (0x0000F000) + #define DDRDATA4CH1_CR_TXPERBITRANK2_Lane3_MAX (0x0000000F) + #define DDRDATA4CH1_CR_TXPERBITRANK2_Lane4_OFF (16) + #define DDRDATA4CH1_CR_TXPERBITRANK2_Lane4_WID ( 4) + #define DDRDATA4CH1_CR_TXPERBITRANK2_Lane4_MSK (0x000F0000) + #define DDRDATA4CH1_CR_TXPERBITRANK2_Lane4_MAX (0x0000000F) + #define DDRDATA4CH1_CR_TXPERBITRANK2_Lane5_OFF (20) + #define DDRDATA4CH1_CR_TXPERBITRANK2_Lane5_WID ( 4) + #define DDRDATA4CH1_CR_TXPERBITRANK2_Lane5_MSK (0x00F00000) + #define DDRDATA4CH1_CR_TXPERBITRANK2_Lane5_MAX (0x0000000F) + #define DDRDATA4CH1_CR_TXPERBITRANK2_Lane6_OFF (24) + #define DDRDATA4CH1_CR_TXPERBITRANK2_Lane6_WID ( 4) + #define DDRDATA4CH1_CR_TXPERBITRANK2_Lane6_MSK (0x0F000000) + #define DDRDATA4CH1_CR_TXPERBITRANK2_Lane6_MAX (0x0000000F) + #define DDRDATA4CH1_CR_TXPERBITRANK2_Lane7_OFF (28) + #define DDRDATA4CH1_CR_TXPERBITRANK2_Lane7_WID ( 4) + #define DDRDATA4CH1_CR_TXPERBITRANK2_Lane7_MSK (0xF0000000) + #define DDRDATA4CH1_CR_TXPERBITRANK2_Lane7_MAX (0x0000000F) + +#define DDRDATA4CH1_CR_TXPERBITRANK3_REG (0x0000093C) + #define DDRDATA4CH1_CR_TXPERBITRANK3_Lane0_OFF ( 0) + #define DDRDATA4CH1_CR_TXPERBITRANK3_Lane0_WID ( 4) + #define DDRDATA4CH1_CR_TXPERBITRANK3_Lane0_MSK (0x0000000F) + #define DDRDATA4CH1_CR_TXPERBITRANK3_Lane0_MAX (0x0000000F) + #define DDRDATA4CH1_CR_TXPERBITRANK3_Lane1_OFF ( 4) + #define DDRDATA4CH1_CR_TXPERBITRANK3_Lane1_WID ( 4) + #define DDRDATA4CH1_CR_TXPERBITRANK3_Lane1_MSK (0x000000F0) + #define DDRDATA4CH1_CR_TXPERBITRANK3_Lane1_MAX (0x0000000F) + #define DDRDATA4CH1_CR_TXPERBITRANK3_Lane2_OFF ( 8) + #define DDRDATA4CH1_CR_TXPERBITRANK3_Lane2_WID ( 4) + #define DDRDATA4CH1_CR_TXPERBITRANK3_Lane2_MSK (0x00000F00) + #define DDRDATA4CH1_CR_TXPERBITRANK3_Lane2_MAX (0x0000000F) + #define DDRDATA4CH1_CR_TXPERBITRANK3_Lane3_OFF (12) + #define DDRDATA4CH1_CR_TXPERBITRANK3_Lane3_WID ( 4) + #define DDRDATA4CH1_CR_TXPERBITRANK3_Lane3_MSK (0x0000F000) + #define DDRDATA4CH1_CR_TXPERBITRANK3_Lane3_MAX (0x0000000F) + #define DDRDATA4CH1_CR_TXPERBITRANK3_Lane4_OFF (16) + #define DDRDATA4CH1_CR_TXPERBITRANK3_Lane4_WID ( 4) + #define DDRDATA4CH1_CR_TXPERBITRANK3_Lane4_MSK (0x000F0000) + #define DDRDATA4CH1_CR_TXPERBITRANK3_Lane4_MAX (0x0000000F) + #define DDRDATA4CH1_CR_TXPERBITRANK3_Lane5_OFF (20) + #define DDRDATA4CH1_CR_TXPERBITRANK3_Lane5_WID ( 4) + #define DDRDATA4CH1_CR_TXPERBITRANK3_Lane5_MSK (0x00F00000) + #define DDRDATA4CH1_CR_TXPERBITRANK3_Lane5_MAX (0x0000000F) + #define DDRDATA4CH1_CR_TXPERBITRANK3_Lane6_OFF (24) + #define DDRDATA4CH1_CR_TXPERBITRANK3_Lane6_WID ( 4) + #define DDRDATA4CH1_CR_TXPERBITRANK3_Lane6_MSK (0x0F000000) + #define DDRDATA4CH1_CR_TXPERBITRANK3_Lane6_MAX (0x0000000F) + #define DDRDATA4CH1_CR_TXPERBITRANK3_Lane7_OFF (28) + #define DDRDATA4CH1_CR_TXPERBITRANK3_Lane7_WID ( 4) + #define DDRDATA4CH1_CR_TXPERBITRANK3_Lane7_MSK (0xF0000000) + #define DDRDATA4CH1_CR_TXPERBITRANK3_Lane7_MAX (0x0000000F) + +#define DDRDATA4CH1_CR_RCOMPDATA0_REG (0x00000940) + #define DDRDATA4CH1_CR_RCOMPDATA0_RcompDrvUp_OFF ( 0) + #define DDRDATA4CH1_CR_RCOMPDATA0_RcompDrvUp_WID ( 6) + #define DDRDATA4CH1_CR_RCOMPDATA0_RcompDrvUp_MSK (0x0000003F) + #define DDRDATA4CH1_CR_RCOMPDATA0_RcompDrvUp_MAX (0x0000003F) + #define DDRDATA4CH1_CR_RCOMPDATA0_Spare0_OFF ( 6) + #define DDRDATA4CH1_CR_RCOMPDATA0_Spare0_WID ( 3) + #define DDRDATA4CH1_CR_RCOMPDATA0_Spare0_MSK (0x000001C0) + #define DDRDATA4CH1_CR_RCOMPDATA0_Spare0_MAX (0x00000007) + #define DDRDATA4CH1_CR_RCOMPDATA0_RcompDrvDown_OFF ( 9) + #define DDRDATA4CH1_CR_RCOMPDATA0_RcompDrvDown_WID ( 6) + #define DDRDATA4CH1_CR_RCOMPDATA0_RcompDrvDown_MSK (0x00007E00) + #define DDRDATA4CH1_CR_RCOMPDATA0_RcompDrvDown_MAX (0x0000003F) + #define DDRDATA4CH1_CR_RCOMPDATA0_VTComp_OFF (15) + #define DDRDATA4CH1_CR_RCOMPDATA0_VTComp_WID ( 5) + #define DDRDATA4CH1_CR_RCOMPDATA0_VTComp_MSK (0x000F8000) + #define DDRDATA4CH1_CR_RCOMPDATA0_VTComp_MAX (0x0000001F) + #define DDRDATA4CH1_CR_RCOMPDATA0_TcoComp_OFF (20) + #define DDRDATA4CH1_CR_RCOMPDATA0_TcoComp_WID ( 6) + #define DDRDATA4CH1_CR_RCOMPDATA0_TcoComp_MSK (0x03F00000) + #define DDRDATA4CH1_CR_RCOMPDATA0_TcoComp_MAX (0x0000003F) + #define DDRDATA4CH1_CR_RCOMPDATA0_SlewRateComp_OFF (26) + #define DDRDATA4CH1_CR_RCOMPDATA0_SlewRateComp_WID ( 5) + #define DDRDATA4CH1_CR_RCOMPDATA0_SlewRateComp_MSK (0x7C000000) + #define DDRDATA4CH1_CR_RCOMPDATA0_SlewRateComp_MAX (0x0000001F) + #define DDRDATA4CH1_CR_RCOMPDATA0_Spare2_OFF (31) + #define DDRDATA4CH1_CR_RCOMPDATA0_Spare2_WID ( 1) + #define DDRDATA4CH1_CR_RCOMPDATA0_Spare2_MSK (0x80000000) + #define DDRDATA4CH1_CR_RCOMPDATA0_Spare2_MAX (0x00000001) + +#define DDRDATA4CH1_CR_RCOMPDATA1_REG (0x00000944) + #define DDRDATA4CH1_CR_RCOMPDATA1_RcompOdtUp_OFF ( 0) + #define DDRDATA4CH1_CR_RCOMPDATA1_RcompOdtUp_WID ( 6) + #define DDRDATA4CH1_CR_RCOMPDATA1_RcompOdtUp_MSK (0x0000003F) + #define DDRDATA4CH1_CR_RCOMPDATA1_RcompOdtUp_MAX (0x0000003F) + #define DDRDATA4CH1_CR_RCOMPDATA1_Spare0_OFF ( 6) + #define DDRDATA4CH1_CR_RCOMPDATA1_Spare0_WID ( 3) + #define DDRDATA4CH1_CR_RCOMPDATA1_Spare0_MSK (0x000001C0) + #define DDRDATA4CH1_CR_RCOMPDATA1_Spare0_MAX (0x00000007) + #define DDRDATA4CH1_CR_RCOMPDATA1_RcompOdtDown_OFF ( 9) + #define DDRDATA4CH1_CR_RCOMPDATA1_RcompOdtDown_WID ( 6) + #define DDRDATA4CH1_CR_RCOMPDATA1_RcompOdtDown_MSK (0x00007E00) + #define DDRDATA4CH1_CR_RCOMPDATA1_RcompOdtDown_MAX (0x0000003F) + #define DDRDATA4CH1_CR_RCOMPDATA1_Spare1_OFF (15) + #define DDRDATA4CH1_CR_RCOMPDATA1_Spare1_WID ( 1) + #define DDRDATA4CH1_CR_RCOMPDATA1_Spare1_MSK (0x00008000) + #define DDRDATA4CH1_CR_RCOMPDATA1_Spare1_MAX (0x00000001) + #define DDRDATA4CH1_CR_RCOMPDATA1_PanicDrvDn_OFF (16) + #define DDRDATA4CH1_CR_RCOMPDATA1_PanicDrvDn_WID ( 6) + #define DDRDATA4CH1_CR_RCOMPDATA1_PanicDrvDn_MSK (0x003F0000) + #define DDRDATA4CH1_CR_RCOMPDATA1_PanicDrvDn_MAX (0x0000003F) + #define DDRDATA4CH1_CR_RCOMPDATA1_PanicDrvUp_OFF (22) + #define DDRDATA4CH1_CR_RCOMPDATA1_PanicDrvUp_WID ( 6) + #define DDRDATA4CH1_CR_RCOMPDATA1_PanicDrvUp_MSK (0x0FC00000) + #define DDRDATA4CH1_CR_RCOMPDATA1_PanicDrvUp_MAX (0x0000003F) + #define DDRDATA4CH1_CR_RCOMPDATA1_LevelShifterComp_OFF (28) + #define DDRDATA4CH1_CR_RCOMPDATA1_LevelShifterComp_WID ( 3) + #define DDRDATA4CH1_CR_RCOMPDATA1_LevelShifterComp_MSK (0x70000000) + #define DDRDATA4CH1_CR_RCOMPDATA1_LevelShifterComp_MAX (0x00000007) + #define DDRDATA4CH1_CR_RCOMPDATA1_Spare2_OFF (31) + #define DDRDATA4CH1_CR_RCOMPDATA1_Spare2_WID ( 1) + #define DDRDATA4CH1_CR_RCOMPDATA1_Spare2_MSK (0x80000000) + #define DDRDATA4CH1_CR_RCOMPDATA1_Spare2_MAX (0x00000001) + +#define DDRDATA4CH1_CR_TXXTALK_REG (0x00000948) + #define DDRDATA4CH1_CR_TXXTALK_Lane0_OFF ( 0) + #define DDRDATA4CH1_CR_TXXTALK_Lane0_WID ( 4) + #define DDRDATA4CH1_CR_TXXTALK_Lane0_MSK (0x0000000F) + #define DDRDATA4CH1_CR_TXXTALK_Lane0_MAX (0x0000000F) + #define DDRDATA4CH1_CR_TXXTALK_Lane1_OFF ( 4) + #define DDRDATA4CH1_CR_TXXTALK_Lane1_WID ( 4) + #define DDRDATA4CH1_CR_TXXTALK_Lane1_MSK (0x000000F0) + #define DDRDATA4CH1_CR_TXXTALK_Lane1_MAX (0x0000000F) + #define DDRDATA4CH1_CR_TXXTALK_Lane2_OFF ( 8) + #define DDRDATA4CH1_CR_TXXTALK_Lane2_WID ( 4) + #define DDRDATA4CH1_CR_TXXTALK_Lane2_MSK (0x00000F00) + #define DDRDATA4CH1_CR_TXXTALK_Lane2_MAX (0x0000000F) + #define DDRDATA4CH1_CR_TXXTALK_Lane3_OFF (12) + #define DDRDATA4CH1_CR_TXXTALK_Lane3_WID ( 4) + #define DDRDATA4CH1_CR_TXXTALK_Lane3_MSK (0x0000F000) + #define DDRDATA4CH1_CR_TXXTALK_Lane3_MAX (0x0000000F) + #define DDRDATA4CH1_CR_TXXTALK_Lane4_OFF (16) + #define DDRDATA4CH1_CR_TXXTALK_Lane4_WID ( 4) + #define DDRDATA4CH1_CR_TXXTALK_Lane4_MSK (0x000F0000) + #define DDRDATA4CH1_CR_TXXTALK_Lane4_MAX (0x0000000F) + #define DDRDATA4CH1_CR_TXXTALK_Lane5_OFF (20) + #define DDRDATA4CH1_CR_TXXTALK_Lane5_WID ( 4) + #define DDRDATA4CH1_CR_TXXTALK_Lane5_MSK (0x00F00000) + #define DDRDATA4CH1_CR_TXXTALK_Lane5_MAX (0x0000000F) + #define DDRDATA4CH1_CR_TXXTALK_Lane6_OFF (24) + #define DDRDATA4CH1_CR_TXXTALK_Lane6_WID ( 4) + #define DDRDATA4CH1_CR_TXXTALK_Lane6_MSK (0x0F000000) + #define DDRDATA4CH1_CR_TXXTALK_Lane6_MAX (0x0000000F) + #define DDRDATA4CH1_CR_TXXTALK_Lane7_OFF (28) + #define DDRDATA4CH1_CR_TXXTALK_Lane7_WID ( 4) + #define DDRDATA4CH1_CR_TXXTALK_Lane7_MSK (0xF0000000) + #define DDRDATA4CH1_CR_TXXTALK_Lane7_MAX (0x0000000F) + +#define DDRDATA4CH1_CR_RXOFFSETVDQ_REG (0x0000094C) + #define DDRDATA4CH1_CR_RXOFFSETVDQ_Lane0_OFF ( 0) + #define DDRDATA4CH1_CR_RXOFFSETVDQ_Lane0_WID ( 4) + #define DDRDATA4CH1_CR_RXOFFSETVDQ_Lane0_MSK (0x0000000F) + #define DDRDATA4CH1_CR_RXOFFSETVDQ_Lane0_MAX (0x0000000F) + #define DDRDATA4CH1_CR_RXOFFSETVDQ_Lane1_OFF ( 4) + #define DDRDATA4CH1_CR_RXOFFSETVDQ_Lane1_WID ( 4) + #define DDRDATA4CH1_CR_RXOFFSETVDQ_Lane1_MSK (0x000000F0) + #define DDRDATA4CH1_CR_RXOFFSETVDQ_Lane1_MAX (0x0000000F) + #define DDRDATA4CH1_CR_RXOFFSETVDQ_Lane2_OFF ( 8) + #define DDRDATA4CH1_CR_RXOFFSETVDQ_Lane2_WID ( 4) + #define DDRDATA4CH1_CR_RXOFFSETVDQ_Lane2_MSK (0x00000F00) + #define DDRDATA4CH1_CR_RXOFFSETVDQ_Lane2_MAX (0x0000000F) + #define DDRDATA4CH1_CR_RXOFFSETVDQ_Lane3_OFF (12) + #define DDRDATA4CH1_CR_RXOFFSETVDQ_Lane3_WID ( 4) + #define DDRDATA4CH1_CR_RXOFFSETVDQ_Lane3_MSK (0x0000F000) + #define DDRDATA4CH1_CR_RXOFFSETVDQ_Lane3_MAX (0x0000000F) + #define DDRDATA4CH1_CR_RXOFFSETVDQ_Lane4_OFF (16) + #define DDRDATA4CH1_CR_RXOFFSETVDQ_Lane4_WID ( 4) + #define DDRDATA4CH1_CR_RXOFFSETVDQ_Lane4_MSK (0x000F0000) + #define DDRDATA4CH1_CR_RXOFFSETVDQ_Lane4_MAX (0x0000000F) + #define DDRDATA4CH1_CR_RXOFFSETVDQ_Lane5_OFF (20) + #define DDRDATA4CH1_CR_RXOFFSETVDQ_Lane5_WID ( 4) + #define DDRDATA4CH1_CR_RXOFFSETVDQ_Lane5_MSK (0x00F00000) + #define DDRDATA4CH1_CR_RXOFFSETVDQ_Lane5_MAX (0x0000000F) + #define DDRDATA4CH1_CR_RXOFFSETVDQ_Lane6_OFF (24) + #define DDRDATA4CH1_CR_RXOFFSETVDQ_Lane6_WID ( 4) + #define DDRDATA4CH1_CR_RXOFFSETVDQ_Lane6_MSK (0x0F000000) + #define DDRDATA4CH1_CR_RXOFFSETVDQ_Lane6_MAX (0x0000000F) + #define DDRDATA4CH1_CR_RXOFFSETVDQ_Lane7_OFF (28) + #define DDRDATA4CH1_CR_RXOFFSETVDQ_Lane7_WID ( 4) + #define DDRDATA4CH1_CR_RXOFFSETVDQ_Lane7_MSK (0xF0000000) + #define DDRDATA4CH1_CR_RXOFFSETVDQ_Lane7_MAX (0x0000000F) + +#define DDRDATA4CH1_CR_DDRDATARESERVED_REG (0x00000950) + #define DDRDATA4CH1_CR_DDRDATARESERVED_Spare_OFF ( 0) + #define DDRDATA4CH1_CR_DDRDATARESERVED_Spare_WID (32) + #define DDRDATA4CH1_CR_DDRDATARESERVED_Spare_MSK (0xFFFFFFFF) + #define DDRDATA4CH1_CR_DDRDATARESERVED_Spare_MAX (0xFFFFFFFF) + +#define DDRDATA4CH1_CR_DATATRAINFEEDBACK_REG (0x00000954) + #define DDRDATA4CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_OFF ( 0) + #define DDRDATA4CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_WID ( 9) + #define DDRDATA4CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_MSK (0x000001FF) + #define DDRDATA4CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_MAX (0x000001FF) + #define DDRDATA4CH1_CR_DATATRAINFEEDBACK_Spare_OFF ( 9) + #define DDRDATA4CH1_CR_DATATRAINFEEDBACK_Spare_WID (23) + #define DDRDATA4CH1_CR_DATATRAINFEEDBACK_Spare_MSK (0xFFFFFE00) + #define DDRDATA4CH1_CR_DATATRAINFEEDBACK_Spare_MAX (0x007FFFFF) + +#define DDRDATA4CH1_CR_DLLPITESTANDADC_REG (0x00000958) + #define DDRDATA4CH1_CR_DLLPITESTANDADC_RunTest_OFF ( 0) + #define DDRDATA4CH1_CR_DLLPITESTANDADC_RunTest_WID ( 1) + #define DDRDATA4CH1_CR_DLLPITESTANDADC_RunTest_MSK (0x00000001) + #define DDRDATA4CH1_CR_DLLPITESTANDADC_RunTest_MAX (0x00000001) + #define DDRDATA4CH1_CR_DLLPITESTANDADC_RunTest_DEF (0x00000000) + #define DDRDATA4CH1_CR_DLLPITESTANDADC_Load_OFF ( 1) + #define DDRDATA4CH1_CR_DLLPITESTANDADC_Load_WID ( 1) + #define DDRDATA4CH1_CR_DLLPITESTANDADC_Load_MSK (0x00000002) + #define DDRDATA4CH1_CR_DLLPITESTANDADC_Load_MAX (0x00000001) + #define DDRDATA4CH1_CR_DLLPITESTANDADC_Load_DEF (0x00000000) + #define DDRDATA4CH1_CR_DLLPITESTANDADC_ModeHVM_OFF ( 2) + #define DDRDATA4CH1_CR_DLLPITESTANDADC_ModeHVM_WID ( 1) + #define DDRDATA4CH1_CR_DLLPITESTANDADC_ModeHVM_MSK (0x00000004) + #define DDRDATA4CH1_CR_DLLPITESTANDADC_ModeHVM_MAX (0x00000001) + #define DDRDATA4CH1_CR_DLLPITESTANDADC_ModeHVM_DEF (0x00000000) + #define DDRDATA4CH1_CR_DLLPITESTANDADC_ModeDV_OFF ( 3) + #define DDRDATA4CH1_CR_DLLPITESTANDADC_ModeDV_WID ( 1) + #define DDRDATA4CH1_CR_DLLPITESTANDADC_ModeDV_MSK (0x00000008) + #define DDRDATA4CH1_CR_DLLPITESTANDADC_ModeDV_MAX (0x00000001) + #define DDRDATA4CH1_CR_DLLPITESTANDADC_ModeDV_DEF (0x00000000) + #define DDRDATA4CH1_CR_DLLPITESTANDADC_ModeADC_OFF ( 4) + #define DDRDATA4CH1_CR_DLLPITESTANDADC_ModeADC_WID ( 1) + #define DDRDATA4CH1_CR_DLLPITESTANDADC_ModeADC_MSK (0x00000010) + #define DDRDATA4CH1_CR_DLLPITESTANDADC_ModeADC_MAX (0x00000001) + #define DDRDATA4CH1_CR_DLLPITESTANDADC_ModeADC_DEF (0x00000000) + #define DDRDATA4CH1_CR_DLLPITESTANDADC_LoadCount_OFF ( 5) + #define DDRDATA4CH1_CR_DLLPITESTANDADC_LoadCount_WID (10) + #define DDRDATA4CH1_CR_DLLPITESTANDADC_LoadCount_MSK (0x00007FE0) + #define DDRDATA4CH1_CR_DLLPITESTANDADC_LoadCount_MAX (0x000003FF) + #define DDRDATA4CH1_CR_DLLPITESTANDADC_CountStatus_OFF (15) + #define DDRDATA4CH1_CR_DLLPITESTANDADC_CountStatus_WID (10) + #define DDRDATA4CH1_CR_DLLPITESTANDADC_CountStatus_MSK (0x01FF8000) + #define DDRDATA4CH1_CR_DLLPITESTANDADC_CountStatus_MAX (0x000003FF) + #define DDRDATA4CH1_CR_DLLPITESTANDADC_CountStatus_DEF (0x00000000) + #define DDRDATA4CH1_CR_DLLPITESTANDADC_Spare_OFF (25) + #define DDRDATA4CH1_CR_DLLPITESTANDADC_Spare_WID ( 7) + #define DDRDATA4CH1_CR_DLLPITESTANDADC_Spare_MSK (0xFE000000) + #define DDRDATA4CH1_CR_DLLPITESTANDADC_Spare_MAX (0x0000007F) + +#define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_REG (0x0000095C) + #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_OFF ( 0) + #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_WID ( 6) + #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MSK (0x0000003F) + #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MAX (0x0000003F) + #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_DEF (0x00000000) + #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_OFF ( 6) + #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_WID ( 6) + #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MSK (0x00000FC0) + #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MAX (0x0000003F) + #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_DEF (0x00000000) + #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_OFF (12) + #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_WID ( 5) + #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MSK (0x0001F000) + #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MAX (0x0000001F) + #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_DEF (0x00000000) + #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_OFF (17) + #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_WID ( 5) + #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MSK (0x003E0000) + #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MAX (0x0000001F) + #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_DEF (0x00000000) + #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_OFF (22) + #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_WID ( 5) + #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_MSK (0x07C00000) + #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_MAX (0x0000001F) + #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_DEF (0x00000000) + #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_OFF (27) + #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_WID ( 5) + #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MSK (0xF8000000) + #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MAX (0x0000001F) + #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_DEF (0x00000000) + +#define DDRDATA4CH1_CR_DDRCRDATACONTROL1_REG (0x00000960) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_RefPi_OFF ( 0) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_RefPi_WID ( 4) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_RefPi_MSK (0x0000000F) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_RefPi_MAX (0x0000000F) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_RefPi_DEF (0x00000000) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_DllMask_OFF ( 4) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_DllMask_WID ( 2) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_DllMask_MSK (0x00000030) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_DllMask_MAX (0x00000003) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_DllMask_DEF (0x00000000) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_DllWeakLock_OFF ( 6) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_DllWeakLock_WID ( 1) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_DllWeakLock_MSK (0x00000040) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_DllWeakLock_MAX (0x00000001) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_DllWeakLock_DEF (0x00000000) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_OFF ( 7) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_WID ( 3) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MSK (0x00000380) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MAX (0x00000007) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_DEF (0x00000000) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_OFF (10) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_WID ( 3) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_MSK (0x00001C00) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_MAX (0x00000007) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_DEF (0x00000000) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_OdtDelay_OFF (13) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_OdtDelay_WID ( 4) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_OdtDelay_MSK (0x0001E000) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_OdtDelay_MAX (0x0000000F) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_OdtDelay_DEF (0x00000000) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_OdtDuration_OFF (17) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_OdtDuration_WID ( 3) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_OdtDuration_MSK (0x000E0000) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_OdtDuration_MAX (0x00000007) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_OdtDuration_DEF (0x00000000) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_OFF (20) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_WID ( 4) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_MSK (0x00F00000) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_MAX (0x0000000F) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_DEF (0x00000000) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_OFF (24) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_WID ( 3) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_MSK (0x07000000) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_MAX (0x00000007) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_DEF (0x00000000) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_OFF (27) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_WID ( 3) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_MSK (0x38000000) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_MAX (0x00000007) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_DEF (0x00000000) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_OFF (30) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_WID ( 1) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_MSK (0x40000000) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_MAX (0x00000001) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_DEF (0x00000000) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_Rsvd1_OFF (31) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_Rsvd1_WID ( 1) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_Rsvd1_MSK (0x80000000) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_Rsvd1_MAX (0x00000001) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_Rsvd1_DEF (0x00000000) + +#define DDRDATA4CH1_CR_DDRCRDATACONTROL2_REG (0x00000964) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_OFF ( 0) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_WID ( 5) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_MSK (0x0000001F) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_MAX (0x0000001F) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_DEF (0x00000000) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_OFF ( 5) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_WID ( 1) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_MSK (0x00000020) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_MAX (0x00000001) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_DEF (0x00000000) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_ForceRxOn_OFF ( 6) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_ForceRxOn_WID ( 1) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_ForceRxOn_MSK (0x00000040) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_ForceRxOn_MAX (0x00000001) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_ForceRxOn_DEF (0x00000000) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_LeakerComp_OFF ( 7) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_LeakerComp_WID ( 2) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_LeakerComp_MSK (0x00000180) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_LeakerComp_MAX (0x00000003) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_LeakerComp_DEF (0x00000000) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_OFF ( 9) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_WID ( 4) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_MSK (0x00001E00) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_MAX (0x0000000F) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_DEF (0x00000008) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_OFF (13) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_WID ( 5) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_MSK (0x0003E000) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_MAX (0x0000001F) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_DEF (0x00000011) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_OFF (18) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_WID ( 1) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_MSK (0x00040000) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_MAX (0x00000001) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_DEF (0x00000000) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_Spare_OFF (19) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_Spare_WID (13) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_Spare_MSK (0xFFF80000) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_Spare_MAX (0x00001FFF) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_Spare_DEF (0x00000000) + +#define DDRDATA4CH1_CR_DDRCRVSSHIORVREFCONTROL_REG (0x0000096C) + #define DDRDATA4CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_OFF ( 0) + #define DDRDATA4CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_WID (24) + #define DDRDATA4CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_MSK (0x00FFFFFF) + #define DDRDATA4CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_MAX (0x00FFFFFF) + #define DDRDATA4CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_DEF (0x00000000) + #define DDRDATA4CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_OFF (24) + #define DDRDATA4CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_WID ( 8) + #define DDRDATA4CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_MSK (0xFF000000) + #define DDRDATA4CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_MAX (0x000000FF) + #define DDRDATA4CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_DEF (0x00000000) + +#define DDRDATA4CH1_CR_DDRCRDATAOFFSETTRAIN_REG (0x00000970) + #define DDRDATA4CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_OFF ( 0) + #define DDRDATA4CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_WID ( 6) + #define DDRDATA4CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MSK (0x0000003F) + #define DDRDATA4CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MAX (0x0000003F) + #define DDRDATA4CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_DEF (0x00000000) + #define DDRDATA4CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_OFF ( 6) + #define DDRDATA4CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_WID ( 6) + #define DDRDATA4CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MSK (0x00000FC0) + #define DDRDATA4CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MAX (0x0000003F) + #define DDRDATA4CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_DEF (0x00000000) + #define DDRDATA4CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_OFF (12) + #define DDRDATA4CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_WID ( 6) + #define DDRDATA4CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MSK (0x0003F000) + #define DDRDATA4CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MAX (0x0000003F) + #define DDRDATA4CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_DEF (0x00000000) + #define DDRDATA4CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_OFF (18) + #define DDRDATA4CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_WID ( 6) + #define DDRDATA4CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MSK (0x00FC0000) + #define DDRDATA4CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MAX (0x0000003F) + #define DDRDATA4CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_DEF (0x00000000) + #define DDRDATA4CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_OFF (24) + #define DDRDATA4CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_WID ( 7) + #define DDRDATA4CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MSK (0x7F000000) + #define DDRDATA4CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MAX (0x0000007F) + #define DDRDATA4CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_DEF (0x00000000) + #define DDRDATA4CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_OFF (31) + #define DDRDATA4CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_WID ( 1) + #define DDRDATA4CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_MSK (0x80000000) + #define DDRDATA4CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_MAX (0x00000001) + #define DDRDATA4CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_DEF (0x00000000) + +#define DDRDATA4CH1_CR_DDRCRDATACONTROL0_REG (0x00000974) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_OFF ( 0) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_WID ( 1) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_MSK (0x00000001) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_MAX (0x00000001) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_DEF (0x00000000) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_OFF ( 1) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_WID ( 1) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_MSK (0x00000002) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_MAX (0x00000001) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_DEF (0x00000000) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_OFF ( 2) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_WID ( 1) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_MSK (0x00000004) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_MAX (0x00000001) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_DEF (0x00000000) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_OFF ( 3) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_WID ( 1) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MSK (0x00000008) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MAX (0x00000001) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_DEF (0x00000000) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_TxOn_OFF ( 4) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_TxOn_WID ( 1) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_TxOn_MSK (0x00000010) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_TxOn_MAX (0x00000001) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_TxOn_DEF (0x00000000) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RfOn_OFF ( 5) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RfOn_WID ( 1) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RfOn_MSK (0x00000020) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RfOn_MAX (0x00000001) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RfOn_DEF (0x00000000) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RxPiOn_OFF ( 6) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RxPiOn_WID ( 1) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RxPiOn_MSK (0x00000040) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RxPiOn_MAX (0x00000001) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RxPiOn_DEF (0x00000000) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_TxPiOn_OFF ( 7) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_TxPiOn_WID ( 1) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_TxPiOn_MSK (0x00000080) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_TxPiOn_MAX (0x00000001) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_TxPiOn_DEF (0x00000000) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_OFF ( 8) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_WID ( 1) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_MSK (0x00000100) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_MAX (0x00000001) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_DEF (0x00000000) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_OFF ( 9) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_WID ( 1) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MSK (0x00000200) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MAX (0x00000001) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_DEF (0x00000000) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_TxDisable_OFF (10) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_TxDisable_WID ( 1) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_TxDisable_MSK (0x00000400) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_TxDisable_MAX (0x00000001) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_TxDisable_DEF (0x00000000) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RxDisable_OFF (11) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RxDisable_WID ( 1) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RxDisable_MSK (0x00000800) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RxDisable_MAX (0x00000001) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RxDisable_DEF (0x00000000) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_TxLong_OFF (12) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_TxLong_WID ( 1) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_TxLong_MSK (0x00001000) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_TxLong_MAX (0x00000001) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_TxLong_DEF (0x00000000) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_OFF (13) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_WID ( 2) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_MSK (0x00006000) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_MAX (0x00000003) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_DEF (0x00000000) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RxReadPointer_OFF (15) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RxReadPointer_WID ( 3) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RxReadPointer_MSK (0x00038000) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RxReadPointer_MAX (0x00000007) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RxReadPointer_DEF (0x00000000) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_OFF (18) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_WID ( 1) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_MSK (0x00040000) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_MAX (0x00000001) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_DEF (0x00000000) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_OFF (19) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_WID ( 1) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_MSK (0x00080000) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_MAX (0x00000001) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_DEF (0x00000000) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_ReadRFRd_OFF (20) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_ReadRFRd_WID ( 1) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_ReadRFRd_MSK (0x00100000) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_ReadRFRd_MAX (0x00000001) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_ReadRFRd_DEF (0x00000000) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_ReadRFWr_OFF (21) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_ReadRFWr_WID ( 1) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_ReadRFWr_MSK (0x00200000) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_ReadRFWr_MAX (0x00000001) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_ReadRFWr_DEF (0x00000000) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_ReadRFRank_OFF (22) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_ReadRFRank_WID ( 2) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_ReadRFRank_MSK (0x00C00000) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_ReadRFRank_MAX (0x00000003) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_ReadRFRank_DEF (0x00000000) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_OFF (24) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_WID ( 1) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_MSK (0x01000000) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_MAX (0x00000001) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_DEF (0x00000000) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_OdtSampOff_OFF (25) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_OdtSampOff_WID ( 1) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_OdtSampOff_MSK (0x02000000) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_OdtSampOff_MAX (0x00000001) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_OdtSampOff_DEF (0x00000000) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_OFF (26) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_WID ( 1) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_MSK (0x04000000) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_MAX (0x00000001) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_DEF (0x00000000) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_OFF (27) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_WID ( 1) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MSK (0x08000000) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MAX (0x00000001) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_DEF (0x00000000) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_OFF (28) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_WID ( 1) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_MSK (0x10000000) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_MAX (0x00000001) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_DEF (0x00000000) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_OFF (29) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_WID ( 1) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_MSK (0x20000000) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_MAX (0x00000001) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_DEF (0x00000000) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_OFF (30) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_WID ( 1) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MSK (0x40000000) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MAX (0x00000001) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_DEF (0x00000000) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_OFF (31) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_WID ( 1) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_MSK (0x80000000) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_MAX (0x00000001) + #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_DEF (0x00000000) + +#define DDRDATA4CH1_CR_DDRCRVREFADJUST1_REG (0x00000978) + #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_OFF ( 0) + #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_WID ( 7) + #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_MSK (0x0000007F) + #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_MAX (0x0000007F) + #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_DEF (0x00000000) + #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_OFF ( 7) + #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_WID ( 7) + #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_MSK (0x00003F80) + #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_MAX (0x0000007F) + #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_DEF (0x00000000) + #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_OFF (14) + #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_WID ( 7) + #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_MSK (0x001FC000) + #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_MAX (0x0000007F) + #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_DEF (0x00000000) + #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_OFF (21) + #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_WID ( 1) + #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_MSK (0x00200000) + #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_MAX (0x00000001) + #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_DEF (0x00000000) + #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_OFF (22) + #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_WID ( 1) + #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_MSK (0x00400000) + #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_MAX (0x00000001) + #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_DEF (0x00000000) + #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_OFF (23) + #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_WID ( 1) + #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_MSK (0x00800000) + #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_MAX (0x00000001) + #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_DEF (0x00000000) + #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_OFF (24) + #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_WID ( 2) + #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_MSK (0x03000000) + #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_MAX (0x00000003) + #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_DEF (0x00000000) + #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_OFF (26) + #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_WID ( 1) + #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_MSK (0x04000000) + #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_MAX (0x00000001) + #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_DEF (0x00000000) + #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_Rsvd_OFF (27) + #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_Rsvd_WID ( 2) + #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_Rsvd_MSK (0x18000000) + #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_Rsvd_MAX (0x00000003) + #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_Rsvd_DEF (0x00000000) + #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_caSlowBW_OFF (29) + #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_caSlowBW_WID ( 1) + #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_caSlowBW_MSK (0x20000000) + #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_caSlowBW_MAX (0x00000001) + #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_caSlowBW_DEF (0x00000000) + #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_OFF (30) + #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_WID ( 1) + #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_MSK (0x40000000) + #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_MAX (0x00000001) + #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_DEF (0x00000000) + #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_OFF (31) + #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_WID ( 1) + #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_MSK (0x80000000) + #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_MAX (0x00000001) + #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_DEF (0x00000000) + +#define DDRDATA5CH0_CR_RXTRAINRANK0_REG (0x00000A00) + #define DDRDATA5CH0_CR_RXTRAINRANK0_RxRcvEnPi_OFF ( 0) + #define DDRDATA5CH0_CR_RXTRAINRANK0_RxRcvEnPi_WID ( 9) + #define DDRDATA5CH0_CR_RXTRAINRANK0_RxRcvEnPi_MSK (0x000001FF) + #define DDRDATA5CH0_CR_RXTRAINRANK0_RxRcvEnPi_MAX (0x000001FF) + #define DDRDATA5CH0_CR_RXTRAINRANK0_RxDqsPPi_OFF ( 9) + #define DDRDATA5CH0_CR_RXTRAINRANK0_RxDqsPPi_WID ( 6) + #define DDRDATA5CH0_CR_RXTRAINRANK0_RxDqsPPi_MSK (0x00007E00) + #define DDRDATA5CH0_CR_RXTRAINRANK0_RxDqsPPi_MAX (0x0000003F) + #define DDRDATA5CH0_CR_RXTRAINRANK0_RxEq_OFF (15) + #define DDRDATA5CH0_CR_RXTRAINRANK0_RxEq_WID ( 5) + #define DDRDATA5CH0_CR_RXTRAINRANK0_RxEq_MSK (0x000F8000) + #define DDRDATA5CH0_CR_RXTRAINRANK0_RxEq_MAX (0x0000001F) + #define DDRDATA5CH0_CR_RXTRAINRANK0_RxDqsNPi_OFF (20) + #define DDRDATA5CH0_CR_RXTRAINRANK0_RxDqsNPi_WID ( 6) + #define DDRDATA5CH0_CR_RXTRAINRANK0_RxDqsNPi_MSK (0x03F00000) + #define DDRDATA5CH0_CR_RXTRAINRANK0_RxDqsNPi_MAX (0x0000003F) + #define DDRDATA5CH0_CR_RXTRAINRANK0_RxVref_OFF (26) + #define DDRDATA5CH0_CR_RXTRAINRANK0_RxVref_WID ( 6) + #define DDRDATA5CH0_CR_RXTRAINRANK0_RxVref_MSK (0xFC000000) + #define DDRDATA5CH0_CR_RXTRAINRANK0_RxVref_MAX (0x0000003F) + +#define DDRDATA5CH0_CR_RXTRAINRANK1_REG (0x00000A04) + #define DDRDATA5CH0_CR_RXTRAINRANK1_RxRcvEnPi_OFF ( 0) + #define DDRDATA5CH0_CR_RXTRAINRANK1_RxRcvEnPi_WID ( 9) + #define DDRDATA5CH0_CR_RXTRAINRANK1_RxRcvEnPi_MSK (0x000001FF) + #define DDRDATA5CH0_CR_RXTRAINRANK1_RxRcvEnPi_MAX (0x000001FF) + #define DDRDATA5CH0_CR_RXTRAINRANK1_RxDqsPPi_OFF ( 9) + #define DDRDATA5CH0_CR_RXTRAINRANK1_RxDqsPPi_WID ( 6) + #define DDRDATA5CH0_CR_RXTRAINRANK1_RxDqsPPi_MSK (0x00007E00) + #define DDRDATA5CH0_CR_RXTRAINRANK1_RxDqsPPi_MAX (0x0000003F) + #define DDRDATA5CH0_CR_RXTRAINRANK1_RxEq_OFF (15) + #define DDRDATA5CH0_CR_RXTRAINRANK1_RxEq_WID ( 5) + #define DDRDATA5CH0_CR_RXTRAINRANK1_RxEq_MSK (0x000F8000) + #define DDRDATA5CH0_CR_RXTRAINRANK1_RxEq_MAX (0x0000001F) + #define DDRDATA5CH0_CR_RXTRAINRANK1_RxDqsNPi_OFF (20) + #define DDRDATA5CH0_CR_RXTRAINRANK1_RxDqsNPi_WID ( 6) + #define DDRDATA5CH0_CR_RXTRAINRANK1_RxDqsNPi_MSK (0x03F00000) + #define DDRDATA5CH0_CR_RXTRAINRANK1_RxDqsNPi_MAX (0x0000003F) + #define DDRDATA5CH0_CR_RXTRAINRANK1_RxVref_OFF (26) + #define DDRDATA5CH0_CR_RXTRAINRANK1_RxVref_WID ( 6) + #define DDRDATA5CH0_CR_RXTRAINRANK1_RxVref_MSK (0xFC000000) + #define DDRDATA5CH0_CR_RXTRAINRANK1_RxVref_MAX (0x0000003F) + +#define DDRDATA5CH0_CR_RXTRAINRANK2_REG (0x00000A08) + #define DDRDATA5CH0_CR_RXTRAINRANK2_RxRcvEnPi_OFF ( 0) + #define DDRDATA5CH0_CR_RXTRAINRANK2_RxRcvEnPi_WID ( 9) + #define DDRDATA5CH0_CR_RXTRAINRANK2_RxRcvEnPi_MSK (0x000001FF) + #define DDRDATA5CH0_CR_RXTRAINRANK2_RxRcvEnPi_MAX (0x000001FF) + #define DDRDATA5CH0_CR_RXTRAINRANK2_RxDqsPPi_OFF ( 9) + #define DDRDATA5CH0_CR_RXTRAINRANK2_RxDqsPPi_WID ( 6) + #define DDRDATA5CH0_CR_RXTRAINRANK2_RxDqsPPi_MSK (0x00007E00) + #define DDRDATA5CH0_CR_RXTRAINRANK2_RxDqsPPi_MAX (0x0000003F) + #define DDRDATA5CH0_CR_RXTRAINRANK2_RxEq_OFF (15) + #define DDRDATA5CH0_CR_RXTRAINRANK2_RxEq_WID ( 5) + #define DDRDATA5CH0_CR_RXTRAINRANK2_RxEq_MSK (0x000F8000) + #define DDRDATA5CH0_CR_RXTRAINRANK2_RxEq_MAX (0x0000001F) + #define DDRDATA5CH0_CR_RXTRAINRANK2_RxDqsNPi_OFF (20) + #define DDRDATA5CH0_CR_RXTRAINRANK2_RxDqsNPi_WID ( 6) + #define DDRDATA5CH0_CR_RXTRAINRANK2_RxDqsNPi_MSK (0x03F00000) + #define DDRDATA5CH0_CR_RXTRAINRANK2_RxDqsNPi_MAX (0x0000003F) + #define DDRDATA5CH0_CR_RXTRAINRANK2_RxVref_OFF (26) + #define DDRDATA5CH0_CR_RXTRAINRANK2_RxVref_WID ( 6) + #define DDRDATA5CH0_CR_RXTRAINRANK2_RxVref_MSK (0xFC000000) + #define DDRDATA5CH0_CR_RXTRAINRANK2_RxVref_MAX (0x0000003F) + +#define DDRDATA5CH0_CR_RXTRAINRANK3_REG (0x00000A0C) + #define DDRDATA5CH0_CR_RXTRAINRANK3_RxRcvEnPi_OFF ( 0) + #define DDRDATA5CH0_CR_RXTRAINRANK3_RxRcvEnPi_WID ( 9) + #define DDRDATA5CH0_CR_RXTRAINRANK3_RxRcvEnPi_MSK (0x000001FF) + #define DDRDATA5CH0_CR_RXTRAINRANK3_RxRcvEnPi_MAX (0x000001FF) + #define DDRDATA5CH0_CR_RXTRAINRANK3_RxDqsPPi_OFF ( 9) + #define DDRDATA5CH0_CR_RXTRAINRANK3_RxDqsPPi_WID ( 6) + #define DDRDATA5CH0_CR_RXTRAINRANK3_RxDqsPPi_MSK (0x00007E00) + #define DDRDATA5CH0_CR_RXTRAINRANK3_RxDqsPPi_MAX (0x0000003F) + #define DDRDATA5CH0_CR_RXTRAINRANK3_RxEq_OFF (15) + #define DDRDATA5CH0_CR_RXTRAINRANK3_RxEq_WID ( 5) + #define DDRDATA5CH0_CR_RXTRAINRANK3_RxEq_MSK (0x000F8000) + #define DDRDATA5CH0_CR_RXTRAINRANK3_RxEq_MAX (0x0000001F) + #define DDRDATA5CH0_CR_RXTRAINRANK3_RxDqsNPi_OFF (20) + #define DDRDATA5CH0_CR_RXTRAINRANK3_RxDqsNPi_WID ( 6) + #define DDRDATA5CH0_CR_RXTRAINRANK3_RxDqsNPi_MSK (0x03F00000) + #define DDRDATA5CH0_CR_RXTRAINRANK3_RxDqsNPi_MAX (0x0000003F) + #define DDRDATA5CH0_CR_RXTRAINRANK3_RxVref_OFF (26) + #define DDRDATA5CH0_CR_RXTRAINRANK3_RxVref_WID ( 6) + #define DDRDATA5CH0_CR_RXTRAINRANK3_RxVref_MSK (0xFC000000) + #define DDRDATA5CH0_CR_RXTRAINRANK3_RxVref_MAX (0x0000003F) + +#define DDRDATA5CH0_CR_RXPERBITRANK0_REG (0x00000A10) + #define DDRDATA5CH0_CR_RXPERBITRANK0_Lane0_OFF ( 0) + #define DDRDATA5CH0_CR_RXPERBITRANK0_Lane0_WID ( 4) + #define DDRDATA5CH0_CR_RXPERBITRANK0_Lane0_MSK (0x0000000F) + #define DDRDATA5CH0_CR_RXPERBITRANK0_Lane0_MAX (0x0000000F) + #define DDRDATA5CH0_CR_RXPERBITRANK0_Lane1_OFF ( 4) + #define DDRDATA5CH0_CR_RXPERBITRANK0_Lane1_WID ( 4) + #define DDRDATA5CH0_CR_RXPERBITRANK0_Lane1_MSK (0x000000F0) + #define DDRDATA5CH0_CR_RXPERBITRANK0_Lane1_MAX (0x0000000F) + #define DDRDATA5CH0_CR_RXPERBITRANK0_Lane2_OFF ( 8) + #define DDRDATA5CH0_CR_RXPERBITRANK0_Lane2_WID ( 4) + #define DDRDATA5CH0_CR_RXPERBITRANK0_Lane2_MSK (0x00000F00) + #define DDRDATA5CH0_CR_RXPERBITRANK0_Lane2_MAX (0x0000000F) + #define DDRDATA5CH0_CR_RXPERBITRANK0_Lane3_OFF (12) + #define DDRDATA5CH0_CR_RXPERBITRANK0_Lane3_WID ( 4) + #define DDRDATA5CH0_CR_RXPERBITRANK0_Lane3_MSK (0x0000F000) + #define DDRDATA5CH0_CR_RXPERBITRANK0_Lane3_MAX (0x0000000F) + #define DDRDATA5CH0_CR_RXPERBITRANK0_Lane4_OFF (16) + #define DDRDATA5CH0_CR_RXPERBITRANK0_Lane4_WID ( 4) + #define DDRDATA5CH0_CR_RXPERBITRANK0_Lane4_MSK (0x000F0000) + #define DDRDATA5CH0_CR_RXPERBITRANK0_Lane4_MAX (0x0000000F) + #define DDRDATA5CH0_CR_RXPERBITRANK0_Lane5_OFF (20) + #define DDRDATA5CH0_CR_RXPERBITRANK0_Lane5_WID ( 4) + #define DDRDATA5CH0_CR_RXPERBITRANK0_Lane5_MSK (0x00F00000) + #define DDRDATA5CH0_CR_RXPERBITRANK0_Lane5_MAX (0x0000000F) + #define DDRDATA5CH0_CR_RXPERBITRANK0_Lane6_OFF (24) + #define DDRDATA5CH0_CR_RXPERBITRANK0_Lane6_WID ( 4) + #define DDRDATA5CH0_CR_RXPERBITRANK0_Lane6_MSK (0x0F000000) + #define DDRDATA5CH0_CR_RXPERBITRANK0_Lane6_MAX (0x0000000F) + #define DDRDATA5CH0_CR_RXPERBITRANK0_Lane7_OFF (28) + #define DDRDATA5CH0_CR_RXPERBITRANK0_Lane7_WID ( 4) + #define DDRDATA5CH0_CR_RXPERBITRANK0_Lane7_MSK (0xF0000000) + #define DDRDATA5CH0_CR_RXPERBITRANK0_Lane7_MAX (0x0000000F) + +#define DDRDATA5CH0_CR_RXPERBITRANK1_REG (0x00000A14) + #define DDRDATA5CH0_CR_RXPERBITRANK1_Lane0_OFF ( 0) + #define DDRDATA5CH0_CR_RXPERBITRANK1_Lane0_WID ( 4) + #define DDRDATA5CH0_CR_RXPERBITRANK1_Lane0_MSK (0x0000000F) + #define DDRDATA5CH0_CR_RXPERBITRANK1_Lane0_MAX (0x0000000F) + #define DDRDATA5CH0_CR_RXPERBITRANK1_Lane1_OFF ( 4) + #define DDRDATA5CH0_CR_RXPERBITRANK1_Lane1_WID ( 4) + #define DDRDATA5CH0_CR_RXPERBITRANK1_Lane1_MSK (0x000000F0) + #define DDRDATA5CH0_CR_RXPERBITRANK1_Lane1_MAX (0x0000000F) + #define DDRDATA5CH0_CR_RXPERBITRANK1_Lane2_OFF ( 8) + #define DDRDATA5CH0_CR_RXPERBITRANK1_Lane2_WID ( 4) + #define DDRDATA5CH0_CR_RXPERBITRANK1_Lane2_MSK (0x00000F00) + #define DDRDATA5CH0_CR_RXPERBITRANK1_Lane2_MAX (0x0000000F) + #define DDRDATA5CH0_CR_RXPERBITRANK1_Lane3_OFF (12) + #define DDRDATA5CH0_CR_RXPERBITRANK1_Lane3_WID ( 4) + #define DDRDATA5CH0_CR_RXPERBITRANK1_Lane3_MSK (0x0000F000) + #define DDRDATA5CH0_CR_RXPERBITRANK1_Lane3_MAX (0x0000000F) + #define DDRDATA5CH0_CR_RXPERBITRANK1_Lane4_OFF (16) + #define DDRDATA5CH0_CR_RXPERBITRANK1_Lane4_WID ( 4) + #define DDRDATA5CH0_CR_RXPERBITRANK1_Lane4_MSK (0x000F0000) + #define DDRDATA5CH0_CR_RXPERBITRANK1_Lane4_MAX (0x0000000F) + #define DDRDATA5CH0_CR_RXPERBITRANK1_Lane5_OFF (20) + #define DDRDATA5CH0_CR_RXPERBITRANK1_Lane5_WID ( 4) + #define DDRDATA5CH0_CR_RXPERBITRANK1_Lane5_MSK (0x00F00000) + #define DDRDATA5CH0_CR_RXPERBITRANK1_Lane5_MAX (0x0000000F) + #define DDRDATA5CH0_CR_RXPERBITRANK1_Lane6_OFF (24) + #define DDRDATA5CH0_CR_RXPERBITRANK1_Lane6_WID ( 4) + #define DDRDATA5CH0_CR_RXPERBITRANK1_Lane6_MSK (0x0F000000) + #define DDRDATA5CH0_CR_RXPERBITRANK1_Lane6_MAX (0x0000000F) + #define DDRDATA5CH0_CR_RXPERBITRANK1_Lane7_OFF (28) + #define DDRDATA5CH0_CR_RXPERBITRANK1_Lane7_WID ( 4) + #define DDRDATA5CH0_CR_RXPERBITRANK1_Lane7_MSK (0xF0000000) + #define DDRDATA5CH0_CR_RXPERBITRANK1_Lane7_MAX (0x0000000F) + +#define DDRDATA5CH0_CR_RXPERBITRANK2_REG (0x00000A18) + #define DDRDATA5CH0_CR_RXPERBITRANK2_Lane0_OFF ( 0) + #define DDRDATA5CH0_CR_RXPERBITRANK2_Lane0_WID ( 4) + #define DDRDATA5CH0_CR_RXPERBITRANK2_Lane0_MSK (0x0000000F) + #define DDRDATA5CH0_CR_RXPERBITRANK2_Lane0_MAX (0x0000000F) + #define DDRDATA5CH0_CR_RXPERBITRANK2_Lane1_OFF ( 4) + #define DDRDATA5CH0_CR_RXPERBITRANK2_Lane1_WID ( 4) + #define DDRDATA5CH0_CR_RXPERBITRANK2_Lane1_MSK (0x000000F0) + #define DDRDATA5CH0_CR_RXPERBITRANK2_Lane1_MAX (0x0000000F) + #define DDRDATA5CH0_CR_RXPERBITRANK2_Lane2_OFF ( 8) + #define DDRDATA5CH0_CR_RXPERBITRANK2_Lane2_WID ( 4) + #define DDRDATA5CH0_CR_RXPERBITRANK2_Lane2_MSK (0x00000F00) + #define DDRDATA5CH0_CR_RXPERBITRANK2_Lane2_MAX (0x0000000F) + #define DDRDATA5CH0_CR_RXPERBITRANK2_Lane3_OFF (12) + #define DDRDATA5CH0_CR_RXPERBITRANK2_Lane3_WID ( 4) + #define DDRDATA5CH0_CR_RXPERBITRANK2_Lane3_MSK (0x0000F000) + #define DDRDATA5CH0_CR_RXPERBITRANK2_Lane3_MAX (0x0000000F) + #define DDRDATA5CH0_CR_RXPERBITRANK2_Lane4_OFF (16) + #define DDRDATA5CH0_CR_RXPERBITRANK2_Lane4_WID ( 4) + #define DDRDATA5CH0_CR_RXPERBITRANK2_Lane4_MSK (0x000F0000) + #define DDRDATA5CH0_CR_RXPERBITRANK2_Lane4_MAX (0x0000000F) + #define DDRDATA5CH0_CR_RXPERBITRANK2_Lane5_OFF (20) + #define DDRDATA5CH0_CR_RXPERBITRANK2_Lane5_WID ( 4) + #define DDRDATA5CH0_CR_RXPERBITRANK2_Lane5_MSK (0x00F00000) + #define DDRDATA5CH0_CR_RXPERBITRANK2_Lane5_MAX (0x0000000F) + #define DDRDATA5CH0_CR_RXPERBITRANK2_Lane6_OFF (24) + #define DDRDATA5CH0_CR_RXPERBITRANK2_Lane6_WID ( 4) + #define DDRDATA5CH0_CR_RXPERBITRANK2_Lane6_MSK (0x0F000000) + #define DDRDATA5CH0_CR_RXPERBITRANK2_Lane6_MAX (0x0000000F) + #define DDRDATA5CH0_CR_RXPERBITRANK2_Lane7_OFF (28) + #define DDRDATA5CH0_CR_RXPERBITRANK2_Lane7_WID ( 4) + #define DDRDATA5CH0_CR_RXPERBITRANK2_Lane7_MSK (0xF0000000) + #define DDRDATA5CH0_CR_RXPERBITRANK2_Lane7_MAX (0x0000000F) + +#define DDRDATA5CH0_CR_RXPERBITRANK3_REG (0x00000A1C) + #define DDRDATA5CH0_CR_RXPERBITRANK3_Lane0_OFF ( 0) + #define DDRDATA5CH0_CR_RXPERBITRANK3_Lane0_WID ( 4) + #define DDRDATA5CH0_CR_RXPERBITRANK3_Lane0_MSK (0x0000000F) + #define DDRDATA5CH0_CR_RXPERBITRANK3_Lane0_MAX (0x0000000F) + #define DDRDATA5CH0_CR_RXPERBITRANK3_Lane1_OFF ( 4) + #define DDRDATA5CH0_CR_RXPERBITRANK3_Lane1_WID ( 4) + #define DDRDATA5CH0_CR_RXPERBITRANK3_Lane1_MSK (0x000000F0) + #define DDRDATA5CH0_CR_RXPERBITRANK3_Lane1_MAX (0x0000000F) + #define DDRDATA5CH0_CR_RXPERBITRANK3_Lane2_OFF ( 8) + #define DDRDATA5CH0_CR_RXPERBITRANK3_Lane2_WID ( 4) + #define DDRDATA5CH0_CR_RXPERBITRANK3_Lane2_MSK (0x00000F00) + #define DDRDATA5CH0_CR_RXPERBITRANK3_Lane2_MAX (0x0000000F) + #define DDRDATA5CH0_CR_RXPERBITRANK3_Lane3_OFF (12) + #define DDRDATA5CH0_CR_RXPERBITRANK3_Lane3_WID ( 4) + #define DDRDATA5CH0_CR_RXPERBITRANK3_Lane3_MSK (0x0000F000) + #define DDRDATA5CH0_CR_RXPERBITRANK3_Lane3_MAX (0x0000000F) + #define DDRDATA5CH0_CR_RXPERBITRANK3_Lane4_OFF (16) + #define DDRDATA5CH0_CR_RXPERBITRANK3_Lane4_WID ( 4) + #define DDRDATA5CH0_CR_RXPERBITRANK3_Lane4_MSK (0x000F0000) + #define DDRDATA5CH0_CR_RXPERBITRANK3_Lane4_MAX (0x0000000F) + #define DDRDATA5CH0_CR_RXPERBITRANK3_Lane5_OFF (20) + #define DDRDATA5CH0_CR_RXPERBITRANK3_Lane5_WID ( 4) + #define DDRDATA5CH0_CR_RXPERBITRANK3_Lane5_MSK (0x00F00000) + #define DDRDATA5CH0_CR_RXPERBITRANK3_Lane5_MAX (0x0000000F) + #define DDRDATA5CH0_CR_RXPERBITRANK3_Lane6_OFF (24) + #define DDRDATA5CH0_CR_RXPERBITRANK3_Lane6_WID ( 4) + #define DDRDATA5CH0_CR_RXPERBITRANK3_Lane6_MSK (0x0F000000) + #define DDRDATA5CH0_CR_RXPERBITRANK3_Lane6_MAX (0x0000000F) + #define DDRDATA5CH0_CR_RXPERBITRANK3_Lane7_OFF (28) + #define DDRDATA5CH0_CR_RXPERBITRANK3_Lane7_WID ( 4) + #define DDRDATA5CH0_CR_RXPERBITRANK3_Lane7_MSK (0xF0000000) + #define DDRDATA5CH0_CR_RXPERBITRANK3_Lane7_MAX (0x0000000F) + +#define DDRDATA5CH0_CR_TXTRAINRANK0_REG (0x00000A20) + #define DDRDATA5CH0_CR_TXTRAINRANK0_TxDqDelay_OFF ( 0) + #define DDRDATA5CH0_CR_TXTRAINRANK0_TxDqDelay_WID ( 9) + #define DDRDATA5CH0_CR_TXTRAINRANK0_TxDqDelay_MSK (0x000001FF) + #define DDRDATA5CH0_CR_TXTRAINRANK0_TxDqDelay_MAX (0x000001FF) + #define DDRDATA5CH0_CR_TXTRAINRANK0_TxDqsDelay_OFF ( 9) + #define DDRDATA5CH0_CR_TXTRAINRANK0_TxDqsDelay_WID ( 9) + #define DDRDATA5CH0_CR_TXTRAINRANK0_TxDqsDelay_MSK (0x0003FE00) + #define DDRDATA5CH0_CR_TXTRAINRANK0_TxDqsDelay_MAX (0x000001FF) + #define DDRDATA5CH0_CR_TXTRAINRANK0_Spare0_OFF (18) + #define DDRDATA5CH0_CR_TXTRAINRANK0_Spare0_WID ( 2) + #define DDRDATA5CH0_CR_TXTRAINRANK0_Spare0_MSK (0x000C0000) + #define DDRDATA5CH0_CR_TXTRAINRANK0_Spare0_MAX (0x00000003) + #define DDRDATA5CH0_CR_TXTRAINRANK0_TxEqualization_OFF (20) + #define DDRDATA5CH0_CR_TXTRAINRANK0_TxEqualization_WID ( 6) + #define DDRDATA5CH0_CR_TXTRAINRANK0_TxEqualization_MSK (0x03F00000) + #define DDRDATA5CH0_CR_TXTRAINRANK0_TxEqualization_MAX (0x0000003F) + #define DDRDATA5CH0_CR_TXTRAINRANK0_Spare1_OFF (26) + #define DDRDATA5CH0_CR_TXTRAINRANK0_Spare1_WID ( 6) + #define DDRDATA5CH0_CR_TXTRAINRANK0_Spare1_MSK (0xFC000000) + #define DDRDATA5CH0_CR_TXTRAINRANK0_Spare1_MAX (0x0000003F) + +#define DDRDATA5CH0_CR_TXTRAINRANK1_REG (0x00000A24) + #define DDRDATA5CH0_CR_TXTRAINRANK1_TxDqDelay_OFF ( 0) + #define DDRDATA5CH0_CR_TXTRAINRANK1_TxDqDelay_WID ( 9) + #define DDRDATA5CH0_CR_TXTRAINRANK1_TxDqDelay_MSK (0x000001FF) + #define DDRDATA5CH0_CR_TXTRAINRANK1_TxDqDelay_MAX (0x000001FF) + #define DDRDATA5CH0_CR_TXTRAINRANK1_TxDqsDelay_OFF ( 9) + #define DDRDATA5CH0_CR_TXTRAINRANK1_TxDqsDelay_WID ( 9) + #define DDRDATA5CH0_CR_TXTRAINRANK1_TxDqsDelay_MSK (0x0003FE00) + #define DDRDATA5CH0_CR_TXTRAINRANK1_TxDqsDelay_MAX (0x000001FF) + #define DDRDATA5CH0_CR_TXTRAINRANK1_Spare0_OFF (18) + #define DDRDATA5CH0_CR_TXTRAINRANK1_Spare0_WID ( 2) + #define DDRDATA5CH0_CR_TXTRAINRANK1_Spare0_MSK (0x000C0000) + #define DDRDATA5CH0_CR_TXTRAINRANK1_Spare0_MAX (0x00000003) + #define DDRDATA5CH0_CR_TXTRAINRANK1_TxEqualization_OFF (20) + #define DDRDATA5CH0_CR_TXTRAINRANK1_TxEqualization_WID ( 6) + #define DDRDATA5CH0_CR_TXTRAINRANK1_TxEqualization_MSK (0x03F00000) + #define DDRDATA5CH0_CR_TXTRAINRANK1_TxEqualization_MAX (0x0000003F) + #define DDRDATA5CH0_CR_TXTRAINRANK1_Spare1_OFF (26) + #define DDRDATA5CH0_CR_TXTRAINRANK1_Spare1_WID ( 6) + #define DDRDATA5CH0_CR_TXTRAINRANK1_Spare1_MSK (0xFC000000) + #define DDRDATA5CH0_CR_TXTRAINRANK1_Spare1_MAX (0x0000003F) + +#define DDRDATA5CH0_CR_TXTRAINRANK2_REG (0x00000A28) + #define DDRDATA5CH0_CR_TXTRAINRANK2_TxDqDelay_OFF ( 0) + #define DDRDATA5CH0_CR_TXTRAINRANK2_TxDqDelay_WID ( 9) + #define DDRDATA5CH0_CR_TXTRAINRANK2_TxDqDelay_MSK (0x000001FF) + #define DDRDATA5CH0_CR_TXTRAINRANK2_TxDqDelay_MAX (0x000001FF) + #define DDRDATA5CH0_CR_TXTRAINRANK2_TxDqsDelay_OFF ( 9) + #define DDRDATA5CH0_CR_TXTRAINRANK2_TxDqsDelay_WID ( 9) + #define DDRDATA5CH0_CR_TXTRAINRANK2_TxDqsDelay_MSK (0x0003FE00) + #define DDRDATA5CH0_CR_TXTRAINRANK2_TxDqsDelay_MAX (0x000001FF) + #define DDRDATA5CH0_CR_TXTRAINRANK2_Spare0_OFF (18) + #define DDRDATA5CH0_CR_TXTRAINRANK2_Spare0_WID ( 2) + #define DDRDATA5CH0_CR_TXTRAINRANK2_Spare0_MSK (0x000C0000) + #define DDRDATA5CH0_CR_TXTRAINRANK2_Spare0_MAX (0x00000003) + #define DDRDATA5CH0_CR_TXTRAINRANK2_TxEqualization_OFF (20) + #define DDRDATA5CH0_CR_TXTRAINRANK2_TxEqualization_WID ( 6) + #define DDRDATA5CH0_CR_TXTRAINRANK2_TxEqualization_MSK (0x03F00000) + #define DDRDATA5CH0_CR_TXTRAINRANK2_TxEqualization_MAX (0x0000003F) + #define DDRDATA5CH0_CR_TXTRAINRANK2_Spare1_OFF (26) + #define DDRDATA5CH0_CR_TXTRAINRANK2_Spare1_WID ( 6) + #define DDRDATA5CH0_CR_TXTRAINRANK2_Spare1_MSK (0xFC000000) + #define DDRDATA5CH0_CR_TXTRAINRANK2_Spare1_MAX (0x0000003F) + +#define DDRDATA5CH0_CR_TXTRAINRANK3_REG (0x00000A2C) + #define DDRDATA5CH0_CR_TXTRAINRANK3_TxDqDelay_OFF ( 0) + #define DDRDATA5CH0_CR_TXTRAINRANK3_TxDqDelay_WID ( 9) + #define DDRDATA5CH0_CR_TXTRAINRANK3_TxDqDelay_MSK (0x000001FF) + #define DDRDATA5CH0_CR_TXTRAINRANK3_TxDqDelay_MAX (0x000001FF) + #define DDRDATA5CH0_CR_TXTRAINRANK3_TxDqsDelay_OFF ( 9) + #define DDRDATA5CH0_CR_TXTRAINRANK3_TxDqsDelay_WID ( 9) + #define DDRDATA5CH0_CR_TXTRAINRANK3_TxDqsDelay_MSK (0x0003FE00) + #define DDRDATA5CH0_CR_TXTRAINRANK3_TxDqsDelay_MAX (0x000001FF) + #define DDRDATA5CH0_CR_TXTRAINRANK3_Spare0_OFF (18) + #define DDRDATA5CH0_CR_TXTRAINRANK3_Spare0_WID ( 2) + #define DDRDATA5CH0_CR_TXTRAINRANK3_Spare0_MSK (0x000C0000) + #define DDRDATA5CH0_CR_TXTRAINRANK3_Spare0_MAX (0x00000003) + #define DDRDATA5CH0_CR_TXTRAINRANK3_TxEqualization_OFF (20) + #define DDRDATA5CH0_CR_TXTRAINRANK3_TxEqualization_WID ( 6) + #define DDRDATA5CH0_CR_TXTRAINRANK3_TxEqualization_MSK (0x03F00000) + #define DDRDATA5CH0_CR_TXTRAINRANK3_TxEqualization_MAX (0x0000003F) + #define DDRDATA5CH0_CR_TXTRAINRANK3_Spare1_OFF (26) + #define DDRDATA5CH0_CR_TXTRAINRANK3_Spare1_WID ( 6) + #define DDRDATA5CH0_CR_TXTRAINRANK3_Spare1_MSK (0xFC000000) + #define DDRDATA5CH0_CR_TXTRAINRANK3_Spare1_MAX (0x0000003F) + +#define DDRDATA5CH0_CR_TXPERBITRANK0_REG (0x00000A30) + #define DDRDATA5CH0_CR_TXPERBITRANK0_Lane0_OFF ( 0) + #define DDRDATA5CH0_CR_TXPERBITRANK0_Lane0_WID ( 4) + #define DDRDATA5CH0_CR_TXPERBITRANK0_Lane0_MSK (0x0000000F) + #define DDRDATA5CH0_CR_TXPERBITRANK0_Lane0_MAX (0x0000000F) + #define DDRDATA5CH0_CR_TXPERBITRANK0_Lane1_OFF ( 4) + #define DDRDATA5CH0_CR_TXPERBITRANK0_Lane1_WID ( 4) + #define DDRDATA5CH0_CR_TXPERBITRANK0_Lane1_MSK (0x000000F0) + #define DDRDATA5CH0_CR_TXPERBITRANK0_Lane1_MAX (0x0000000F) + #define DDRDATA5CH0_CR_TXPERBITRANK0_Lane2_OFF ( 8) + #define DDRDATA5CH0_CR_TXPERBITRANK0_Lane2_WID ( 4) + #define DDRDATA5CH0_CR_TXPERBITRANK0_Lane2_MSK (0x00000F00) + #define DDRDATA5CH0_CR_TXPERBITRANK0_Lane2_MAX (0x0000000F) + #define DDRDATA5CH0_CR_TXPERBITRANK0_Lane3_OFF (12) + #define DDRDATA5CH0_CR_TXPERBITRANK0_Lane3_WID ( 4) + #define DDRDATA5CH0_CR_TXPERBITRANK0_Lane3_MSK (0x0000F000) + #define DDRDATA5CH0_CR_TXPERBITRANK0_Lane3_MAX (0x0000000F) + #define DDRDATA5CH0_CR_TXPERBITRANK0_Lane4_OFF (16) + #define DDRDATA5CH0_CR_TXPERBITRANK0_Lane4_WID ( 4) + #define DDRDATA5CH0_CR_TXPERBITRANK0_Lane4_MSK (0x000F0000) + #define DDRDATA5CH0_CR_TXPERBITRANK0_Lane4_MAX (0x0000000F) + #define DDRDATA5CH0_CR_TXPERBITRANK0_Lane5_OFF (20) + #define DDRDATA5CH0_CR_TXPERBITRANK0_Lane5_WID ( 4) + #define DDRDATA5CH0_CR_TXPERBITRANK0_Lane5_MSK (0x00F00000) + #define DDRDATA5CH0_CR_TXPERBITRANK0_Lane5_MAX (0x0000000F) + #define DDRDATA5CH0_CR_TXPERBITRANK0_Lane6_OFF (24) + #define DDRDATA5CH0_CR_TXPERBITRANK0_Lane6_WID ( 4) + #define DDRDATA5CH0_CR_TXPERBITRANK0_Lane6_MSK (0x0F000000) + #define DDRDATA5CH0_CR_TXPERBITRANK0_Lane6_MAX (0x0000000F) + #define DDRDATA5CH0_CR_TXPERBITRANK0_Lane7_OFF (28) + #define DDRDATA5CH0_CR_TXPERBITRANK0_Lane7_WID ( 4) + #define DDRDATA5CH0_CR_TXPERBITRANK0_Lane7_MSK (0xF0000000) + #define DDRDATA5CH0_CR_TXPERBITRANK0_Lane7_MAX (0x0000000F) + +#define DDRDATA5CH0_CR_TXPERBITRANK1_REG (0x00000A34) + #define DDRDATA5CH0_CR_TXPERBITRANK1_Lane0_OFF ( 0) + #define DDRDATA5CH0_CR_TXPERBITRANK1_Lane0_WID ( 4) + #define DDRDATA5CH0_CR_TXPERBITRANK1_Lane0_MSK (0x0000000F) + #define DDRDATA5CH0_CR_TXPERBITRANK1_Lane0_MAX (0x0000000F) + #define DDRDATA5CH0_CR_TXPERBITRANK1_Lane1_OFF ( 4) + #define DDRDATA5CH0_CR_TXPERBITRANK1_Lane1_WID ( 4) + #define DDRDATA5CH0_CR_TXPERBITRANK1_Lane1_MSK (0x000000F0) + #define DDRDATA5CH0_CR_TXPERBITRANK1_Lane1_MAX (0x0000000F) + #define DDRDATA5CH0_CR_TXPERBITRANK1_Lane2_OFF ( 8) + #define DDRDATA5CH0_CR_TXPERBITRANK1_Lane2_WID ( 4) + #define DDRDATA5CH0_CR_TXPERBITRANK1_Lane2_MSK (0x00000F00) + #define DDRDATA5CH0_CR_TXPERBITRANK1_Lane2_MAX (0x0000000F) + #define DDRDATA5CH0_CR_TXPERBITRANK1_Lane3_OFF (12) + #define DDRDATA5CH0_CR_TXPERBITRANK1_Lane3_WID ( 4) + #define DDRDATA5CH0_CR_TXPERBITRANK1_Lane3_MSK (0x0000F000) + #define DDRDATA5CH0_CR_TXPERBITRANK1_Lane3_MAX (0x0000000F) + #define DDRDATA5CH0_CR_TXPERBITRANK1_Lane4_OFF (16) + #define DDRDATA5CH0_CR_TXPERBITRANK1_Lane4_WID ( 4) + #define DDRDATA5CH0_CR_TXPERBITRANK1_Lane4_MSK (0x000F0000) + #define DDRDATA5CH0_CR_TXPERBITRANK1_Lane4_MAX (0x0000000F) + #define DDRDATA5CH0_CR_TXPERBITRANK1_Lane5_OFF (20) + #define DDRDATA5CH0_CR_TXPERBITRANK1_Lane5_WID ( 4) + #define DDRDATA5CH0_CR_TXPERBITRANK1_Lane5_MSK (0x00F00000) + #define DDRDATA5CH0_CR_TXPERBITRANK1_Lane5_MAX (0x0000000F) + #define DDRDATA5CH0_CR_TXPERBITRANK1_Lane6_OFF (24) + #define DDRDATA5CH0_CR_TXPERBITRANK1_Lane6_WID ( 4) + #define DDRDATA5CH0_CR_TXPERBITRANK1_Lane6_MSK (0x0F000000) + #define DDRDATA5CH0_CR_TXPERBITRANK1_Lane6_MAX (0x0000000F) + #define DDRDATA5CH0_CR_TXPERBITRANK1_Lane7_OFF (28) + #define DDRDATA5CH0_CR_TXPERBITRANK1_Lane7_WID ( 4) + #define DDRDATA5CH0_CR_TXPERBITRANK1_Lane7_MSK (0xF0000000) + #define DDRDATA5CH0_CR_TXPERBITRANK1_Lane7_MAX (0x0000000F) + +#define DDRDATA5CH0_CR_TXPERBITRANK2_REG (0x00000A38) + #define DDRDATA5CH0_CR_TXPERBITRANK2_Lane0_OFF ( 0) + #define DDRDATA5CH0_CR_TXPERBITRANK2_Lane0_WID ( 4) + #define DDRDATA5CH0_CR_TXPERBITRANK2_Lane0_MSK (0x0000000F) + #define DDRDATA5CH0_CR_TXPERBITRANK2_Lane0_MAX (0x0000000F) + #define DDRDATA5CH0_CR_TXPERBITRANK2_Lane1_OFF ( 4) + #define DDRDATA5CH0_CR_TXPERBITRANK2_Lane1_WID ( 4) + #define DDRDATA5CH0_CR_TXPERBITRANK2_Lane1_MSK (0x000000F0) + #define DDRDATA5CH0_CR_TXPERBITRANK2_Lane1_MAX (0x0000000F) + #define DDRDATA5CH0_CR_TXPERBITRANK2_Lane2_OFF ( 8) + #define DDRDATA5CH0_CR_TXPERBITRANK2_Lane2_WID ( 4) + #define DDRDATA5CH0_CR_TXPERBITRANK2_Lane2_MSK (0x00000F00) + #define DDRDATA5CH0_CR_TXPERBITRANK2_Lane2_MAX (0x0000000F) + #define DDRDATA5CH0_CR_TXPERBITRANK2_Lane3_OFF (12) + #define DDRDATA5CH0_CR_TXPERBITRANK2_Lane3_WID ( 4) + #define DDRDATA5CH0_CR_TXPERBITRANK2_Lane3_MSK (0x0000F000) + #define DDRDATA5CH0_CR_TXPERBITRANK2_Lane3_MAX (0x0000000F) + #define DDRDATA5CH0_CR_TXPERBITRANK2_Lane4_OFF (16) + #define DDRDATA5CH0_CR_TXPERBITRANK2_Lane4_WID ( 4) + #define DDRDATA5CH0_CR_TXPERBITRANK2_Lane4_MSK (0x000F0000) + #define DDRDATA5CH0_CR_TXPERBITRANK2_Lane4_MAX (0x0000000F) + #define DDRDATA5CH0_CR_TXPERBITRANK2_Lane5_OFF (20) + #define DDRDATA5CH0_CR_TXPERBITRANK2_Lane5_WID ( 4) + #define DDRDATA5CH0_CR_TXPERBITRANK2_Lane5_MSK (0x00F00000) + #define DDRDATA5CH0_CR_TXPERBITRANK2_Lane5_MAX (0x0000000F) + #define DDRDATA5CH0_CR_TXPERBITRANK2_Lane6_OFF (24) + #define DDRDATA5CH0_CR_TXPERBITRANK2_Lane6_WID ( 4) + #define DDRDATA5CH0_CR_TXPERBITRANK2_Lane6_MSK (0x0F000000) + #define DDRDATA5CH0_CR_TXPERBITRANK2_Lane6_MAX (0x0000000F) + #define DDRDATA5CH0_CR_TXPERBITRANK2_Lane7_OFF (28) + #define DDRDATA5CH0_CR_TXPERBITRANK2_Lane7_WID ( 4) + #define DDRDATA5CH0_CR_TXPERBITRANK2_Lane7_MSK (0xF0000000) + #define DDRDATA5CH0_CR_TXPERBITRANK2_Lane7_MAX (0x0000000F) + +#define DDRDATA5CH0_CR_TXPERBITRANK3_REG (0x00000A3C) + #define DDRDATA5CH0_CR_TXPERBITRANK3_Lane0_OFF ( 0) + #define DDRDATA5CH0_CR_TXPERBITRANK3_Lane0_WID ( 4) + #define DDRDATA5CH0_CR_TXPERBITRANK3_Lane0_MSK (0x0000000F) + #define DDRDATA5CH0_CR_TXPERBITRANK3_Lane0_MAX (0x0000000F) + #define DDRDATA5CH0_CR_TXPERBITRANK3_Lane1_OFF ( 4) + #define DDRDATA5CH0_CR_TXPERBITRANK3_Lane1_WID ( 4) + #define DDRDATA5CH0_CR_TXPERBITRANK3_Lane1_MSK (0x000000F0) + #define DDRDATA5CH0_CR_TXPERBITRANK3_Lane1_MAX (0x0000000F) + #define DDRDATA5CH0_CR_TXPERBITRANK3_Lane2_OFF ( 8) + #define DDRDATA5CH0_CR_TXPERBITRANK3_Lane2_WID ( 4) + #define DDRDATA5CH0_CR_TXPERBITRANK3_Lane2_MSK (0x00000F00) + #define DDRDATA5CH0_CR_TXPERBITRANK3_Lane2_MAX (0x0000000F) + #define DDRDATA5CH0_CR_TXPERBITRANK3_Lane3_OFF (12) + #define DDRDATA5CH0_CR_TXPERBITRANK3_Lane3_WID ( 4) + #define DDRDATA5CH0_CR_TXPERBITRANK3_Lane3_MSK (0x0000F000) + #define DDRDATA5CH0_CR_TXPERBITRANK3_Lane3_MAX (0x0000000F) + #define DDRDATA5CH0_CR_TXPERBITRANK3_Lane4_OFF (16) + #define DDRDATA5CH0_CR_TXPERBITRANK3_Lane4_WID ( 4) + #define DDRDATA5CH0_CR_TXPERBITRANK3_Lane4_MSK (0x000F0000) + #define DDRDATA5CH0_CR_TXPERBITRANK3_Lane4_MAX (0x0000000F) + #define DDRDATA5CH0_CR_TXPERBITRANK3_Lane5_OFF (20) + #define DDRDATA5CH0_CR_TXPERBITRANK3_Lane5_WID ( 4) + #define DDRDATA5CH0_CR_TXPERBITRANK3_Lane5_MSK (0x00F00000) + #define DDRDATA5CH0_CR_TXPERBITRANK3_Lane5_MAX (0x0000000F) + #define DDRDATA5CH0_CR_TXPERBITRANK3_Lane6_OFF (24) + #define DDRDATA5CH0_CR_TXPERBITRANK3_Lane6_WID ( 4) + #define DDRDATA5CH0_CR_TXPERBITRANK3_Lane6_MSK (0x0F000000) + #define DDRDATA5CH0_CR_TXPERBITRANK3_Lane6_MAX (0x0000000F) + #define DDRDATA5CH0_CR_TXPERBITRANK3_Lane7_OFF (28) + #define DDRDATA5CH0_CR_TXPERBITRANK3_Lane7_WID ( 4) + #define DDRDATA5CH0_CR_TXPERBITRANK3_Lane7_MSK (0xF0000000) + #define DDRDATA5CH0_CR_TXPERBITRANK3_Lane7_MAX (0x0000000F) + +#define DDRDATA5CH0_CR_RCOMPDATA0_REG (0x00000A40) + #define DDRDATA5CH0_CR_RCOMPDATA0_RcompDrvUp_OFF ( 0) + #define DDRDATA5CH0_CR_RCOMPDATA0_RcompDrvUp_WID ( 6) + #define DDRDATA5CH0_CR_RCOMPDATA0_RcompDrvUp_MSK (0x0000003F) + #define DDRDATA5CH0_CR_RCOMPDATA0_RcompDrvUp_MAX (0x0000003F) + #define DDRDATA5CH0_CR_RCOMPDATA0_Spare0_OFF ( 6) + #define DDRDATA5CH0_CR_RCOMPDATA0_Spare0_WID ( 3) + #define DDRDATA5CH0_CR_RCOMPDATA0_Spare0_MSK (0x000001C0) + #define DDRDATA5CH0_CR_RCOMPDATA0_Spare0_MAX (0x00000007) + #define DDRDATA5CH0_CR_RCOMPDATA0_RcompDrvDown_OFF ( 9) + #define DDRDATA5CH0_CR_RCOMPDATA0_RcompDrvDown_WID ( 6) + #define DDRDATA5CH0_CR_RCOMPDATA0_RcompDrvDown_MSK (0x00007E00) + #define DDRDATA5CH0_CR_RCOMPDATA0_RcompDrvDown_MAX (0x0000003F) + #define DDRDATA5CH0_CR_RCOMPDATA0_VTComp_OFF (15) + #define DDRDATA5CH0_CR_RCOMPDATA0_VTComp_WID ( 5) + #define DDRDATA5CH0_CR_RCOMPDATA0_VTComp_MSK (0x000F8000) + #define DDRDATA5CH0_CR_RCOMPDATA0_VTComp_MAX (0x0000001F) + #define DDRDATA5CH0_CR_RCOMPDATA0_TcoComp_OFF (20) + #define DDRDATA5CH0_CR_RCOMPDATA0_TcoComp_WID ( 6) + #define DDRDATA5CH0_CR_RCOMPDATA0_TcoComp_MSK (0x03F00000) + #define DDRDATA5CH0_CR_RCOMPDATA0_TcoComp_MAX (0x0000003F) + #define DDRDATA5CH0_CR_RCOMPDATA0_SlewRateComp_OFF (26) + #define DDRDATA5CH0_CR_RCOMPDATA0_SlewRateComp_WID ( 5) + #define DDRDATA5CH0_CR_RCOMPDATA0_SlewRateComp_MSK (0x7C000000) + #define DDRDATA5CH0_CR_RCOMPDATA0_SlewRateComp_MAX (0x0000001F) + #define DDRDATA5CH0_CR_RCOMPDATA0_Spare2_OFF (31) + #define DDRDATA5CH0_CR_RCOMPDATA0_Spare2_WID ( 1) + #define DDRDATA5CH0_CR_RCOMPDATA0_Spare2_MSK (0x80000000) + #define DDRDATA5CH0_CR_RCOMPDATA0_Spare2_MAX (0x00000001) + +#define DDRDATA5CH0_CR_RCOMPDATA1_REG (0x00000A44) + #define DDRDATA5CH0_CR_RCOMPDATA1_RcompOdtUp_OFF ( 0) + #define DDRDATA5CH0_CR_RCOMPDATA1_RcompOdtUp_WID ( 6) + #define DDRDATA5CH0_CR_RCOMPDATA1_RcompOdtUp_MSK (0x0000003F) + #define DDRDATA5CH0_CR_RCOMPDATA1_RcompOdtUp_MAX (0x0000003F) + #define DDRDATA5CH0_CR_RCOMPDATA1_Spare0_OFF ( 6) + #define DDRDATA5CH0_CR_RCOMPDATA1_Spare0_WID ( 3) + #define DDRDATA5CH0_CR_RCOMPDATA1_Spare0_MSK (0x000001C0) + #define DDRDATA5CH0_CR_RCOMPDATA1_Spare0_MAX (0x00000007) + #define DDRDATA5CH0_CR_RCOMPDATA1_RcompOdtDown_OFF ( 9) + #define DDRDATA5CH0_CR_RCOMPDATA1_RcompOdtDown_WID ( 6) + #define DDRDATA5CH0_CR_RCOMPDATA1_RcompOdtDown_MSK (0x00007E00) + #define DDRDATA5CH0_CR_RCOMPDATA1_RcompOdtDown_MAX (0x0000003F) + #define DDRDATA5CH0_CR_RCOMPDATA1_Spare1_OFF (15) + #define DDRDATA5CH0_CR_RCOMPDATA1_Spare1_WID ( 1) + #define DDRDATA5CH0_CR_RCOMPDATA1_Spare1_MSK (0x00008000) + #define DDRDATA5CH0_CR_RCOMPDATA1_Spare1_MAX (0x00000001) + #define DDRDATA5CH0_CR_RCOMPDATA1_PanicDrvDn_OFF (16) + #define DDRDATA5CH0_CR_RCOMPDATA1_PanicDrvDn_WID ( 6) + #define DDRDATA5CH0_CR_RCOMPDATA1_PanicDrvDn_MSK (0x003F0000) + #define DDRDATA5CH0_CR_RCOMPDATA1_PanicDrvDn_MAX (0x0000003F) + #define DDRDATA5CH0_CR_RCOMPDATA1_PanicDrvUp_OFF (22) + #define DDRDATA5CH0_CR_RCOMPDATA1_PanicDrvUp_WID ( 6) + #define DDRDATA5CH0_CR_RCOMPDATA1_PanicDrvUp_MSK (0x0FC00000) + #define DDRDATA5CH0_CR_RCOMPDATA1_PanicDrvUp_MAX (0x0000003F) + #define DDRDATA5CH0_CR_RCOMPDATA1_LevelShifterComp_OFF (28) + #define DDRDATA5CH0_CR_RCOMPDATA1_LevelShifterComp_WID ( 3) + #define DDRDATA5CH0_CR_RCOMPDATA1_LevelShifterComp_MSK (0x70000000) + #define DDRDATA5CH0_CR_RCOMPDATA1_LevelShifterComp_MAX (0x00000007) + #define DDRDATA5CH0_CR_RCOMPDATA1_Spare2_OFF (31) + #define DDRDATA5CH0_CR_RCOMPDATA1_Spare2_WID ( 1) + #define DDRDATA5CH0_CR_RCOMPDATA1_Spare2_MSK (0x80000000) + #define DDRDATA5CH0_CR_RCOMPDATA1_Spare2_MAX (0x00000001) + +#define DDRDATA5CH0_CR_TXXTALK_REG (0x00000A48) + #define DDRDATA5CH0_CR_TXXTALK_Lane0_OFF ( 0) + #define DDRDATA5CH0_CR_TXXTALK_Lane0_WID ( 4) + #define DDRDATA5CH0_CR_TXXTALK_Lane0_MSK (0x0000000F) + #define DDRDATA5CH0_CR_TXXTALK_Lane0_MAX (0x0000000F) + #define DDRDATA5CH0_CR_TXXTALK_Lane1_OFF ( 4) + #define DDRDATA5CH0_CR_TXXTALK_Lane1_WID ( 4) + #define DDRDATA5CH0_CR_TXXTALK_Lane1_MSK (0x000000F0) + #define DDRDATA5CH0_CR_TXXTALK_Lane1_MAX (0x0000000F) + #define DDRDATA5CH0_CR_TXXTALK_Lane2_OFF ( 8) + #define DDRDATA5CH0_CR_TXXTALK_Lane2_WID ( 4) + #define DDRDATA5CH0_CR_TXXTALK_Lane2_MSK (0x00000F00) + #define DDRDATA5CH0_CR_TXXTALK_Lane2_MAX (0x0000000F) + #define DDRDATA5CH0_CR_TXXTALK_Lane3_OFF (12) + #define DDRDATA5CH0_CR_TXXTALK_Lane3_WID ( 4) + #define DDRDATA5CH0_CR_TXXTALK_Lane3_MSK (0x0000F000) + #define DDRDATA5CH0_CR_TXXTALK_Lane3_MAX (0x0000000F) + #define DDRDATA5CH0_CR_TXXTALK_Lane4_OFF (16) + #define DDRDATA5CH0_CR_TXXTALK_Lane4_WID ( 4) + #define DDRDATA5CH0_CR_TXXTALK_Lane4_MSK (0x000F0000) + #define DDRDATA5CH0_CR_TXXTALK_Lane4_MAX (0x0000000F) + #define DDRDATA5CH0_CR_TXXTALK_Lane5_OFF (20) + #define DDRDATA5CH0_CR_TXXTALK_Lane5_WID ( 4) + #define DDRDATA5CH0_CR_TXXTALK_Lane5_MSK (0x00F00000) + #define DDRDATA5CH0_CR_TXXTALK_Lane5_MAX (0x0000000F) + #define DDRDATA5CH0_CR_TXXTALK_Lane6_OFF (24) + #define DDRDATA5CH0_CR_TXXTALK_Lane6_WID ( 4) + #define DDRDATA5CH0_CR_TXXTALK_Lane6_MSK (0x0F000000) + #define DDRDATA5CH0_CR_TXXTALK_Lane6_MAX (0x0000000F) + #define DDRDATA5CH0_CR_TXXTALK_Lane7_OFF (28) + #define DDRDATA5CH0_CR_TXXTALK_Lane7_WID ( 4) + #define DDRDATA5CH0_CR_TXXTALK_Lane7_MSK (0xF0000000) + #define DDRDATA5CH0_CR_TXXTALK_Lane7_MAX (0x0000000F) + +#define DDRDATA5CH0_CR_RXOFFSETVDQ_REG (0x00000A4C) + #define DDRDATA5CH0_CR_RXOFFSETVDQ_Lane0_OFF ( 0) + #define DDRDATA5CH0_CR_RXOFFSETVDQ_Lane0_WID ( 4) + #define DDRDATA5CH0_CR_RXOFFSETVDQ_Lane0_MSK (0x0000000F) + #define DDRDATA5CH0_CR_RXOFFSETVDQ_Lane0_MAX (0x0000000F) + #define DDRDATA5CH0_CR_RXOFFSETVDQ_Lane1_OFF ( 4) + #define DDRDATA5CH0_CR_RXOFFSETVDQ_Lane1_WID ( 4) + #define DDRDATA5CH0_CR_RXOFFSETVDQ_Lane1_MSK (0x000000F0) + #define DDRDATA5CH0_CR_RXOFFSETVDQ_Lane1_MAX (0x0000000F) + #define DDRDATA5CH0_CR_RXOFFSETVDQ_Lane2_OFF ( 8) + #define DDRDATA5CH0_CR_RXOFFSETVDQ_Lane2_WID ( 4) + #define DDRDATA5CH0_CR_RXOFFSETVDQ_Lane2_MSK (0x00000F00) + #define DDRDATA5CH0_CR_RXOFFSETVDQ_Lane2_MAX (0x0000000F) + #define DDRDATA5CH0_CR_RXOFFSETVDQ_Lane3_OFF (12) + #define DDRDATA5CH0_CR_RXOFFSETVDQ_Lane3_WID ( 4) + #define DDRDATA5CH0_CR_RXOFFSETVDQ_Lane3_MSK (0x0000F000) + #define DDRDATA5CH0_CR_RXOFFSETVDQ_Lane3_MAX (0x0000000F) + #define DDRDATA5CH0_CR_RXOFFSETVDQ_Lane4_OFF (16) + #define DDRDATA5CH0_CR_RXOFFSETVDQ_Lane4_WID ( 4) + #define DDRDATA5CH0_CR_RXOFFSETVDQ_Lane4_MSK (0x000F0000) + #define DDRDATA5CH0_CR_RXOFFSETVDQ_Lane4_MAX (0x0000000F) + #define DDRDATA5CH0_CR_RXOFFSETVDQ_Lane5_OFF (20) + #define DDRDATA5CH0_CR_RXOFFSETVDQ_Lane5_WID ( 4) + #define DDRDATA5CH0_CR_RXOFFSETVDQ_Lane5_MSK (0x00F00000) + #define DDRDATA5CH0_CR_RXOFFSETVDQ_Lane5_MAX (0x0000000F) + #define DDRDATA5CH0_CR_RXOFFSETVDQ_Lane6_OFF (24) + #define DDRDATA5CH0_CR_RXOFFSETVDQ_Lane6_WID ( 4) + #define DDRDATA5CH0_CR_RXOFFSETVDQ_Lane6_MSK (0x0F000000) + #define DDRDATA5CH0_CR_RXOFFSETVDQ_Lane6_MAX (0x0000000F) + #define DDRDATA5CH0_CR_RXOFFSETVDQ_Lane7_OFF (28) + #define DDRDATA5CH0_CR_RXOFFSETVDQ_Lane7_WID ( 4) + #define DDRDATA5CH0_CR_RXOFFSETVDQ_Lane7_MSK (0xF0000000) + #define DDRDATA5CH0_CR_RXOFFSETVDQ_Lane7_MAX (0x0000000F) + +#define DDRDATA5CH0_CR_DDRDATARESERVED_REG (0x00000A50) + #define DDRDATA5CH0_CR_DDRDATARESERVED_Spare_OFF ( 0) + #define DDRDATA5CH0_CR_DDRDATARESERVED_Spare_WID (32) + #define DDRDATA5CH0_CR_DDRDATARESERVED_Spare_MSK (0xFFFFFFFF) + #define DDRDATA5CH0_CR_DDRDATARESERVED_Spare_MAX (0xFFFFFFFF) + +#define DDRDATA5CH0_CR_DATATRAINFEEDBACK_REG (0x00000A54) + #define DDRDATA5CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_OFF ( 0) + #define DDRDATA5CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_WID ( 9) + #define DDRDATA5CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_MSK (0x000001FF) + #define DDRDATA5CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_MAX (0x000001FF) + #define DDRDATA5CH0_CR_DATATRAINFEEDBACK_Spare_OFF ( 9) + #define DDRDATA5CH0_CR_DATATRAINFEEDBACK_Spare_WID (23) + #define DDRDATA5CH0_CR_DATATRAINFEEDBACK_Spare_MSK (0xFFFFFE00) + #define DDRDATA5CH0_CR_DATATRAINFEEDBACK_Spare_MAX (0x007FFFFF) + +#define DDRDATA5CH0_CR_DLLPITESTANDADC_REG (0x00000A58) + #define DDRDATA5CH0_CR_DLLPITESTANDADC_RunTest_OFF ( 0) + #define DDRDATA5CH0_CR_DLLPITESTANDADC_RunTest_WID ( 1) + #define DDRDATA5CH0_CR_DLLPITESTANDADC_RunTest_MSK (0x00000001) + #define DDRDATA5CH0_CR_DLLPITESTANDADC_RunTest_MAX (0x00000001) + #define DDRDATA5CH0_CR_DLLPITESTANDADC_RunTest_DEF (0x00000000) + #define DDRDATA5CH0_CR_DLLPITESTANDADC_Load_OFF ( 1) + #define DDRDATA5CH0_CR_DLLPITESTANDADC_Load_WID ( 1) + #define DDRDATA5CH0_CR_DLLPITESTANDADC_Load_MSK (0x00000002) + #define DDRDATA5CH0_CR_DLLPITESTANDADC_Load_MAX (0x00000001) + #define DDRDATA5CH0_CR_DLLPITESTANDADC_Load_DEF (0x00000000) + #define DDRDATA5CH0_CR_DLLPITESTANDADC_ModeHVM_OFF ( 2) + #define DDRDATA5CH0_CR_DLLPITESTANDADC_ModeHVM_WID ( 1) + #define DDRDATA5CH0_CR_DLLPITESTANDADC_ModeHVM_MSK (0x00000004) + #define DDRDATA5CH0_CR_DLLPITESTANDADC_ModeHVM_MAX (0x00000001) + #define DDRDATA5CH0_CR_DLLPITESTANDADC_ModeHVM_DEF (0x00000000) + #define DDRDATA5CH0_CR_DLLPITESTANDADC_ModeDV_OFF ( 3) + #define DDRDATA5CH0_CR_DLLPITESTANDADC_ModeDV_WID ( 1) + #define DDRDATA5CH0_CR_DLLPITESTANDADC_ModeDV_MSK (0x00000008) + #define DDRDATA5CH0_CR_DLLPITESTANDADC_ModeDV_MAX (0x00000001) + #define DDRDATA5CH0_CR_DLLPITESTANDADC_ModeDV_DEF (0x00000000) + #define DDRDATA5CH0_CR_DLLPITESTANDADC_ModeADC_OFF ( 4) + #define DDRDATA5CH0_CR_DLLPITESTANDADC_ModeADC_WID ( 1) + #define DDRDATA5CH0_CR_DLLPITESTANDADC_ModeADC_MSK (0x00000010) + #define DDRDATA5CH0_CR_DLLPITESTANDADC_ModeADC_MAX (0x00000001) + #define DDRDATA5CH0_CR_DLLPITESTANDADC_ModeADC_DEF (0x00000000) + #define DDRDATA5CH0_CR_DLLPITESTANDADC_LoadCount_OFF ( 5) + #define DDRDATA5CH0_CR_DLLPITESTANDADC_LoadCount_WID (10) + #define DDRDATA5CH0_CR_DLLPITESTANDADC_LoadCount_MSK (0x00007FE0) + #define DDRDATA5CH0_CR_DLLPITESTANDADC_LoadCount_MAX (0x000003FF) + #define DDRDATA5CH0_CR_DLLPITESTANDADC_CountStatus_OFF (15) + #define DDRDATA5CH0_CR_DLLPITESTANDADC_CountStatus_WID (10) + #define DDRDATA5CH0_CR_DLLPITESTANDADC_CountStatus_MSK (0x01FF8000) + #define DDRDATA5CH0_CR_DLLPITESTANDADC_CountStatus_MAX (0x000003FF) + #define DDRDATA5CH0_CR_DLLPITESTANDADC_CountStatus_DEF (0x00000000) + #define DDRDATA5CH0_CR_DLLPITESTANDADC_Spare_OFF (25) + #define DDRDATA5CH0_CR_DLLPITESTANDADC_Spare_WID ( 7) + #define DDRDATA5CH0_CR_DLLPITESTANDADC_Spare_MSK (0xFE000000) + #define DDRDATA5CH0_CR_DLLPITESTANDADC_Spare_MAX (0x0000007F) + +#define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_REG (0x00000A5C) + #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_OFF ( 0) + #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_WID ( 6) + #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MSK (0x0000003F) + #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MAX (0x0000003F) + #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_DEF (0x00000000) + #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_OFF ( 6) + #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_WID ( 6) + #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MSK (0x00000FC0) + #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MAX (0x0000003F) + #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_DEF (0x00000000) + #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_OFF (12) + #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_WID ( 5) + #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MSK (0x0001F000) + #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MAX (0x0000001F) + #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_DEF (0x00000000) + #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_OFF (17) + #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_WID ( 5) + #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MSK (0x003E0000) + #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MAX (0x0000001F) + #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_DEF (0x00000000) + #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_OFF (22) + #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_WID ( 5) + #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_MSK (0x07C00000) + #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_MAX (0x0000001F) + #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_DEF (0x00000000) + #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_OFF (27) + #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_WID ( 5) + #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MSK (0xF8000000) + #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MAX (0x0000001F) + #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_DEF (0x00000000) + +#define DDRDATA5CH0_CR_DDRCRDATACONTROL1_REG (0x00000A60) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_RefPi_OFF ( 0) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_RefPi_WID ( 4) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_RefPi_MSK (0x0000000F) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_RefPi_MAX (0x0000000F) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_RefPi_DEF (0x00000000) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_DllMask_OFF ( 4) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_DllMask_WID ( 2) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_DllMask_MSK (0x00000030) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_DllMask_MAX (0x00000003) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_DllMask_DEF (0x00000000) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_DllWeakLock_OFF ( 6) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_DllWeakLock_WID ( 1) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_DllWeakLock_MSK (0x00000040) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_DllWeakLock_MAX (0x00000001) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_DllWeakLock_DEF (0x00000000) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_OFF ( 7) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_WID ( 3) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MSK (0x00000380) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MAX (0x00000007) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_DEF (0x00000000) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_OFF (10) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_WID ( 3) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_MSK (0x00001C00) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_MAX (0x00000007) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_DEF (0x00000000) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_OdtDelay_OFF (13) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_OdtDelay_WID ( 4) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_OdtDelay_MSK (0x0001E000) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_OdtDelay_MAX (0x0000000F) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_OdtDelay_DEF (0x00000000) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_OdtDuration_OFF (17) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_OdtDuration_WID ( 3) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_OdtDuration_MSK (0x000E0000) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_OdtDuration_MAX (0x00000007) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_OdtDuration_DEF (0x00000000) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_OFF (20) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_WID ( 4) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_MSK (0x00F00000) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_MAX (0x0000000F) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_DEF (0x00000000) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_OFF (24) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_WID ( 3) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_MSK (0x07000000) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_MAX (0x00000007) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_DEF (0x00000000) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_OFF (27) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_WID ( 3) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_MSK (0x38000000) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_MAX (0x00000007) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_DEF (0x00000000) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_OFF (30) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_WID ( 1) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_MSK (0x40000000) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_MAX (0x00000001) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_DEF (0x00000000) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_Rsvd1_OFF (31) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_Rsvd1_WID ( 1) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_Rsvd1_MSK (0x80000000) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_Rsvd1_MAX (0x00000001) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_Rsvd1_DEF (0x00000000) + +#define DDRDATA5CH0_CR_DDRCRDATACONTROL2_REG (0x00000A64) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_OFF ( 0) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_WID ( 5) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_MSK (0x0000001F) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_MAX (0x0000001F) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_DEF (0x00000000) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_OFF ( 5) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_WID ( 1) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_MSK (0x00000020) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_MAX (0x00000001) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_DEF (0x00000000) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_ForceRxOn_OFF ( 6) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_ForceRxOn_WID ( 1) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_ForceRxOn_MSK (0x00000040) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_ForceRxOn_MAX (0x00000001) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_ForceRxOn_DEF (0x00000000) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_LeakerComp_OFF ( 7) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_LeakerComp_WID ( 2) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_LeakerComp_MSK (0x00000180) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_LeakerComp_MAX (0x00000003) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_LeakerComp_DEF (0x00000000) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_OFF ( 9) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_WID ( 4) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_MSK (0x00001E00) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_MAX (0x0000000F) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_DEF (0x00000008) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_OFF (13) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_WID ( 5) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_MSK (0x0003E000) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_MAX (0x0000001F) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_DEF (0x00000011) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_OFF (18) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_WID ( 1) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_MSK (0x00040000) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_MAX (0x00000001) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_DEF (0x00000000) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_Spare_OFF (19) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_Spare_WID (13) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_Spare_MSK (0xFFF80000) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_Spare_MAX (0x00001FFF) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_Spare_DEF (0x00000000) + +#define DDRDATA5CH0_CR_DDRCRVSSHIORVREFCONTROL_REG (0x00000A6C) + #define DDRDATA5CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_OFF ( 0) + #define DDRDATA5CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_WID (24) + #define DDRDATA5CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_MSK (0x00FFFFFF) + #define DDRDATA5CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_MAX (0x00FFFFFF) + #define DDRDATA5CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_DEF (0x00000000) + #define DDRDATA5CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_OFF (24) + #define DDRDATA5CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_WID ( 8) + #define DDRDATA5CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_MSK (0xFF000000) + #define DDRDATA5CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_MAX (0x000000FF) + #define DDRDATA5CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_DEF (0x00000000) + +#define DDRDATA5CH0_CR_DDRCRDATAOFFSETTRAIN_REG (0x00000A70) + #define DDRDATA5CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_OFF ( 0) + #define DDRDATA5CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_WID ( 6) + #define DDRDATA5CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MSK (0x0000003F) + #define DDRDATA5CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MAX (0x0000003F) + #define DDRDATA5CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_DEF (0x00000000) + #define DDRDATA5CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_OFF ( 6) + #define DDRDATA5CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_WID ( 6) + #define DDRDATA5CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MSK (0x00000FC0) + #define DDRDATA5CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MAX (0x0000003F) + #define DDRDATA5CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_DEF (0x00000000) + #define DDRDATA5CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_OFF (12) + #define DDRDATA5CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_WID ( 6) + #define DDRDATA5CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MSK (0x0003F000) + #define DDRDATA5CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MAX (0x0000003F) + #define DDRDATA5CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_DEF (0x00000000) + #define DDRDATA5CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_OFF (18) + #define DDRDATA5CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_WID ( 6) + #define DDRDATA5CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MSK (0x00FC0000) + #define DDRDATA5CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MAX (0x0000003F) + #define DDRDATA5CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_DEF (0x00000000) + #define DDRDATA5CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_OFF (24) + #define DDRDATA5CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_WID ( 7) + #define DDRDATA5CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MSK (0x7F000000) + #define DDRDATA5CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MAX (0x0000007F) + #define DDRDATA5CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_DEF (0x00000000) + #define DDRDATA5CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_OFF (31) + #define DDRDATA5CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_WID ( 1) + #define DDRDATA5CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_MSK (0x80000000) + #define DDRDATA5CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_MAX (0x00000001) + #define DDRDATA5CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_DEF (0x00000000) + +#define DDRDATA5CH0_CR_DDRCRDATACONTROL0_REG (0x00000A74) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_OFF ( 0) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_WID ( 1) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_MSK (0x00000001) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_MAX (0x00000001) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_DEF (0x00000000) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_OFF ( 1) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_WID ( 1) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_MSK (0x00000002) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_MAX (0x00000001) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_DEF (0x00000000) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_OFF ( 2) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_WID ( 1) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_MSK (0x00000004) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_MAX (0x00000001) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_DEF (0x00000000) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_OFF ( 3) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_WID ( 1) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MSK (0x00000008) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MAX (0x00000001) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_DEF (0x00000000) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_TxOn_OFF ( 4) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_TxOn_WID ( 1) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_TxOn_MSK (0x00000010) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_TxOn_MAX (0x00000001) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_TxOn_DEF (0x00000000) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RfOn_OFF ( 5) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RfOn_WID ( 1) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RfOn_MSK (0x00000020) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RfOn_MAX (0x00000001) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RfOn_DEF (0x00000000) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RxPiOn_OFF ( 6) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RxPiOn_WID ( 1) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RxPiOn_MSK (0x00000040) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RxPiOn_MAX (0x00000001) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RxPiOn_DEF (0x00000000) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_TxPiOn_OFF ( 7) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_TxPiOn_WID ( 1) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_TxPiOn_MSK (0x00000080) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_TxPiOn_MAX (0x00000001) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_TxPiOn_DEF (0x00000000) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_OFF ( 8) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_WID ( 1) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_MSK (0x00000100) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_MAX (0x00000001) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_DEF (0x00000000) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_OFF ( 9) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_WID ( 1) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MSK (0x00000200) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MAX (0x00000001) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_DEF (0x00000000) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_TxDisable_OFF (10) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_TxDisable_WID ( 1) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_TxDisable_MSK (0x00000400) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_TxDisable_MAX (0x00000001) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_TxDisable_DEF (0x00000000) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RxDisable_OFF (11) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RxDisable_WID ( 1) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RxDisable_MSK (0x00000800) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RxDisable_MAX (0x00000001) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RxDisable_DEF (0x00000000) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_TxLong_OFF (12) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_TxLong_WID ( 1) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_TxLong_MSK (0x00001000) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_TxLong_MAX (0x00000001) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_TxLong_DEF (0x00000000) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_OFF (13) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_WID ( 2) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_MSK (0x00006000) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_MAX (0x00000003) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_DEF (0x00000000) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RxReadPointer_OFF (15) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RxReadPointer_WID ( 3) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RxReadPointer_MSK (0x00038000) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RxReadPointer_MAX (0x00000007) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RxReadPointer_DEF (0x00000000) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_OFF (18) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_WID ( 1) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_MSK (0x00040000) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_MAX (0x00000001) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_DEF (0x00000000) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_OFF (19) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_WID ( 1) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_MSK (0x00080000) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_MAX (0x00000001) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_DEF (0x00000000) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_ReadRFRd_OFF (20) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_ReadRFRd_WID ( 1) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_ReadRFRd_MSK (0x00100000) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_ReadRFRd_MAX (0x00000001) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_ReadRFRd_DEF (0x00000000) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_ReadRFWr_OFF (21) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_ReadRFWr_WID ( 1) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_ReadRFWr_MSK (0x00200000) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_ReadRFWr_MAX (0x00000001) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_ReadRFWr_DEF (0x00000000) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_ReadRFRank_OFF (22) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_ReadRFRank_WID ( 2) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_ReadRFRank_MSK (0x00C00000) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_ReadRFRank_MAX (0x00000003) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_ReadRFRank_DEF (0x00000000) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_OFF (24) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_WID ( 1) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_MSK (0x01000000) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_MAX (0x00000001) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_DEF (0x00000000) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_OdtSampOff_OFF (25) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_OdtSampOff_WID ( 1) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_OdtSampOff_MSK (0x02000000) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_OdtSampOff_MAX (0x00000001) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_OdtSampOff_DEF (0x00000000) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_OFF (26) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_WID ( 1) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_MSK (0x04000000) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_MAX (0x00000001) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_DEF (0x00000000) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_OFF (27) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_WID ( 1) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MSK (0x08000000) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MAX (0x00000001) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_DEF (0x00000000) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_OFF (28) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_WID ( 1) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_MSK (0x10000000) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_MAX (0x00000001) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_DEF (0x00000000) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_OFF (29) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_WID ( 1) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_MSK (0x20000000) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_MAX (0x00000001) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_DEF (0x00000000) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_OFF (30) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_WID ( 1) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MSK (0x40000000) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MAX (0x00000001) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_DEF (0x00000000) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_OFF (31) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_WID ( 1) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_MSK (0x80000000) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_MAX (0x00000001) + #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_DEF (0x00000000) + +#define DDRDATA5CH0_CR_DDRCRVREFADJUST1_REG (0x00000A78) + #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_OFF ( 0) + #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_WID ( 7) + #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_MSK (0x0000007F) + #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_MAX (0x0000007F) + #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_DEF (0x00000000) + #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_OFF ( 7) + #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_WID ( 7) + #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_MSK (0x00003F80) + #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_MAX (0x0000007F) + #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_DEF (0x00000000) + #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_OFF (14) + #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_WID ( 7) + #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_MSK (0x001FC000) + #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_MAX (0x0000007F) + #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_DEF (0x00000000) + #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_OFF (21) + #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_WID ( 1) + #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_MSK (0x00200000) + #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_MAX (0x00000001) + #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_DEF (0x00000000) + #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_OFF (22) + #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_WID ( 1) + #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_MSK (0x00400000) + #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_MAX (0x00000001) + #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_DEF (0x00000000) + #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_OFF (23) + #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_WID ( 1) + #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_MSK (0x00800000) + #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_MAX (0x00000001) + #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_DEF (0x00000000) + #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_OFF (24) + #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_WID ( 2) + #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_MSK (0x03000000) + #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_MAX (0x00000003) + #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_DEF (0x00000000) + #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_OFF (26) + #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_WID ( 1) + #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_MSK (0x04000000) + #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_MAX (0x00000001) + #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_DEF (0x00000000) + #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_Rsvd_OFF (27) + #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_Rsvd_WID ( 2) + #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_Rsvd_MSK (0x18000000) + #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_Rsvd_MAX (0x00000003) + #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_Rsvd_DEF (0x00000000) + #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_caSlowBW_OFF (29) + #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_caSlowBW_WID ( 1) + #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_caSlowBW_MSK (0x20000000) + #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_caSlowBW_MAX (0x00000001) + #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_caSlowBW_DEF (0x00000000) + #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_OFF (30) + #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_WID ( 1) + #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_MSK (0x40000000) + #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_MAX (0x00000001) + #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_DEF (0x00000000) + #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_OFF (31) + #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_WID ( 1) + #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_MSK (0x80000000) + #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_MAX (0x00000001) + #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_DEF (0x00000000) + +#define DDRDATA5CH1_CR_RXTRAINRANK0_REG (0x00000B00) + #define DDRDATA5CH1_CR_RXTRAINRANK0_RxRcvEnPi_OFF ( 0) + #define DDRDATA5CH1_CR_RXTRAINRANK0_RxRcvEnPi_WID ( 9) + #define DDRDATA5CH1_CR_RXTRAINRANK0_RxRcvEnPi_MSK (0x000001FF) + #define DDRDATA5CH1_CR_RXTRAINRANK0_RxRcvEnPi_MAX (0x000001FF) + #define DDRDATA5CH1_CR_RXTRAINRANK0_RxDqsPPi_OFF ( 9) + #define DDRDATA5CH1_CR_RXTRAINRANK0_RxDqsPPi_WID ( 6) + #define DDRDATA5CH1_CR_RXTRAINRANK0_RxDqsPPi_MSK (0x00007E00) + #define DDRDATA5CH1_CR_RXTRAINRANK0_RxDqsPPi_MAX (0x0000003F) + #define DDRDATA5CH1_CR_RXTRAINRANK0_RxEq_OFF (15) + #define DDRDATA5CH1_CR_RXTRAINRANK0_RxEq_WID ( 5) + #define DDRDATA5CH1_CR_RXTRAINRANK0_RxEq_MSK (0x000F8000) + #define DDRDATA5CH1_CR_RXTRAINRANK0_RxEq_MAX (0x0000001F) + #define DDRDATA5CH1_CR_RXTRAINRANK0_RxDqsNPi_OFF (20) + #define DDRDATA5CH1_CR_RXTRAINRANK0_RxDqsNPi_WID ( 6) + #define DDRDATA5CH1_CR_RXTRAINRANK0_RxDqsNPi_MSK (0x03F00000) + #define DDRDATA5CH1_CR_RXTRAINRANK0_RxDqsNPi_MAX (0x0000003F) + #define DDRDATA5CH1_CR_RXTRAINRANK0_RxVref_OFF (26) + #define DDRDATA5CH1_CR_RXTRAINRANK0_RxVref_WID ( 6) + #define DDRDATA5CH1_CR_RXTRAINRANK0_RxVref_MSK (0xFC000000) + #define DDRDATA5CH1_CR_RXTRAINRANK0_RxVref_MAX (0x0000003F) + +#define DDRDATA5CH1_CR_RXTRAINRANK1_REG (0x00000B04) + #define DDRDATA5CH1_CR_RXTRAINRANK1_RxRcvEnPi_OFF ( 0) + #define DDRDATA5CH1_CR_RXTRAINRANK1_RxRcvEnPi_WID ( 9) + #define DDRDATA5CH1_CR_RXTRAINRANK1_RxRcvEnPi_MSK (0x000001FF) + #define DDRDATA5CH1_CR_RXTRAINRANK1_RxRcvEnPi_MAX (0x000001FF) + #define DDRDATA5CH1_CR_RXTRAINRANK1_RxDqsPPi_OFF ( 9) + #define DDRDATA5CH1_CR_RXTRAINRANK1_RxDqsPPi_WID ( 6) + #define DDRDATA5CH1_CR_RXTRAINRANK1_RxDqsPPi_MSK (0x00007E00) + #define DDRDATA5CH1_CR_RXTRAINRANK1_RxDqsPPi_MAX (0x0000003F) + #define DDRDATA5CH1_CR_RXTRAINRANK1_RxEq_OFF (15) + #define DDRDATA5CH1_CR_RXTRAINRANK1_RxEq_WID ( 5) + #define DDRDATA5CH1_CR_RXTRAINRANK1_RxEq_MSK (0x000F8000) + #define DDRDATA5CH1_CR_RXTRAINRANK1_RxEq_MAX (0x0000001F) + #define DDRDATA5CH1_CR_RXTRAINRANK1_RxDqsNPi_OFF (20) + #define DDRDATA5CH1_CR_RXTRAINRANK1_RxDqsNPi_WID ( 6) + #define DDRDATA5CH1_CR_RXTRAINRANK1_RxDqsNPi_MSK (0x03F00000) + #define DDRDATA5CH1_CR_RXTRAINRANK1_RxDqsNPi_MAX (0x0000003F) + #define DDRDATA5CH1_CR_RXTRAINRANK1_RxVref_OFF (26) + #define DDRDATA5CH1_CR_RXTRAINRANK1_RxVref_WID ( 6) + #define DDRDATA5CH1_CR_RXTRAINRANK1_RxVref_MSK (0xFC000000) + #define DDRDATA5CH1_CR_RXTRAINRANK1_RxVref_MAX (0x0000003F) + +#define DDRDATA5CH1_CR_RXTRAINRANK2_REG (0x00000B08) + #define DDRDATA5CH1_CR_RXTRAINRANK2_RxRcvEnPi_OFF ( 0) + #define DDRDATA5CH1_CR_RXTRAINRANK2_RxRcvEnPi_WID ( 9) + #define DDRDATA5CH1_CR_RXTRAINRANK2_RxRcvEnPi_MSK (0x000001FF) + #define DDRDATA5CH1_CR_RXTRAINRANK2_RxRcvEnPi_MAX (0x000001FF) + #define DDRDATA5CH1_CR_RXTRAINRANK2_RxDqsPPi_OFF ( 9) + #define DDRDATA5CH1_CR_RXTRAINRANK2_RxDqsPPi_WID ( 6) + #define DDRDATA5CH1_CR_RXTRAINRANK2_RxDqsPPi_MSK (0x00007E00) + #define DDRDATA5CH1_CR_RXTRAINRANK2_RxDqsPPi_MAX (0x0000003F) + #define DDRDATA5CH1_CR_RXTRAINRANK2_RxEq_OFF (15) + #define DDRDATA5CH1_CR_RXTRAINRANK2_RxEq_WID ( 5) + #define DDRDATA5CH1_CR_RXTRAINRANK2_RxEq_MSK (0x000F8000) + #define DDRDATA5CH1_CR_RXTRAINRANK2_RxEq_MAX (0x0000001F) + #define DDRDATA5CH1_CR_RXTRAINRANK2_RxDqsNPi_OFF (20) + #define DDRDATA5CH1_CR_RXTRAINRANK2_RxDqsNPi_WID ( 6) + #define DDRDATA5CH1_CR_RXTRAINRANK2_RxDqsNPi_MSK (0x03F00000) + #define DDRDATA5CH1_CR_RXTRAINRANK2_RxDqsNPi_MAX (0x0000003F) + #define DDRDATA5CH1_CR_RXTRAINRANK2_RxVref_OFF (26) + #define DDRDATA5CH1_CR_RXTRAINRANK2_RxVref_WID ( 6) + #define DDRDATA5CH1_CR_RXTRAINRANK2_RxVref_MSK (0xFC000000) + #define DDRDATA5CH1_CR_RXTRAINRANK2_RxVref_MAX (0x0000003F) + +#define DDRDATA5CH1_CR_RXTRAINRANK3_REG (0x00000B0C) + #define DDRDATA5CH1_CR_RXTRAINRANK3_RxRcvEnPi_OFF ( 0) + #define DDRDATA5CH1_CR_RXTRAINRANK3_RxRcvEnPi_WID ( 9) + #define DDRDATA5CH1_CR_RXTRAINRANK3_RxRcvEnPi_MSK (0x000001FF) + #define DDRDATA5CH1_CR_RXTRAINRANK3_RxRcvEnPi_MAX (0x000001FF) + #define DDRDATA5CH1_CR_RXTRAINRANK3_RxDqsPPi_OFF ( 9) + #define DDRDATA5CH1_CR_RXTRAINRANK3_RxDqsPPi_WID ( 6) + #define DDRDATA5CH1_CR_RXTRAINRANK3_RxDqsPPi_MSK (0x00007E00) + #define DDRDATA5CH1_CR_RXTRAINRANK3_RxDqsPPi_MAX (0x0000003F) + #define DDRDATA5CH1_CR_RXTRAINRANK3_RxEq_OFF (15) + #define DDRDATA5CH1_CR_RXTRAINRANK3_RxEq_WID ( 5) + #define DDRDATA5CH1_CR_RXTRAINRANK3_RxEq_MSK (0x000F8000) + #define DDRDATA5CH1_CR_RXTRAINRANK3_RxEq_MAX (0x0000001F) + #define DDRDATA5CH1_CR_RXTRAINRANK3_RxDqsNPi_OFF (20) + #define DDRDATA5CH1_CR_RXTRAINRANK3_RxDqsNPi_WID ( 6) + #define DDRDATA5CH1_CR_RXTRAINRANK3_RxDqsNPi_MSK (0x03F00000) + #define DDRDATA5CH1_CR_RXTRAINRANK3_RxDqsNPi_MAX (0x0000003F) + #define DDRDATA5CH1_CR_RXTRAINRANK3_RxVref_OFF (26) + #define DDRDATA5CH1_CR_RXTRAINRANK3_RxVref_WID ( 6) + #define DDRDATA5CH1_CR_RXTRAINRANK3_RxVref_MSK (0xFC000000) + #define DDRDATA5CH1_CR_RXTRAINRANK3_RxVref_MAX (0x0000003F) + +#define DDRDATA5CH1_CR_RXPERBITRANK0_REG (0x00000B10) + #define DDRDATA5CH1_CR_RXPERBITRANK0_Lane0_OFF ( 0) + #define DDRDATA5CH1_CR_RXPERBITRANK0_Lane0_WID ( 4) + #define DDRDATA5CH1_CR_RXPERBITRANK0_Lane0_MSK (0x0000000F) + #define DDRDATA5CH1_CR_RXPERBITRANK0_Lane0_MAX (0x0000000F) + #define DDRDATA5CH1_CR_RXPERBITRANK0_Lane1_OFF ( 4) + #define DDRDATA5CH1_CR_RXPERBITRANK0_Lane1_WID ( 4) + #define DDRDATA5CH1_CR_RXPERBITRANK0_Lane1_MSK (0x000000F0) + #define DDRDATA5CH1_CR_RXPERBITRANK0_Lane1_MAX (0x0000000F) + #define DDRDATA5CH1_CR_RXPERBITRANK0_Lane2_OFF ( 8) + #define DDRDATA5CH1_CR_RXPERBITRANK0_Lane2_WID ( 4) + #define DDRDATA5CH1_CR_RXPERBITRANK0_Lane2_MSK (0x00000F00) + #define DDRDATA5CH1_CR_RXPERBITRANK0_Lane2_MAX (0x0000000F) + #define DDRDATA5CH1_CR_RXPERBITRANK0_Lane3_OFF (12) + #define DDRDATA5CH1_CR_RXPERBITRANK0_Lane3_WID ( 4) + #define DDRDATA5CH1_CR_RXPERBITRANK0_Lane3_MSK (0x0000F000) + #define DDRDATA5CH1_CR_RXPERBITRANK0_Lane3_MAX (0x0000000F) + #define DDRDATA5CH1_CR_RXPERBITRANK0_Lane4_OFF (16) + #define DDRDATA5CH1_CR_RXPERBITRANK0_Lane4_WID ( 4) + #define DDRDATA5CH1_CR_RXPERBITRANK0_Lane4_MSK (0x000F0000) + #define DDRDATA5CH1_CR_RXPERBITRANK0_Lane4_MAX (0x0000000F) + #define DDRDATA5CH1_CR_RXPERBITRANK0_Lane5_OFF (20) + #define DDRDATA5CH1_CR_RXPERBITRANK0_Lane5_WID ( 4) + #define DDRDATA5CH1_CR_RXPERBITRANK0_Lane5_MSK (0x00F00000) + #define DDRDATA5CH1_CR_RXPERBITRANK0_Lane5_MAX (0x0000000F) + #define DDRDATA5CH1_CR_RXPERBITRANK0_Lane6_OFF (24) + #define DDRDATA5CH1_CR_RXPERBITRANK0_Lane6_WID ( 4) + #define DDRDATA5CH1_CR_RXPERBITRANK0_Lane6_MSK (0x0F000000) + #define DDRDATA5CH1_CR_RXPERBITRANK0_Lane6_MAX (0x0000000F) + #define DDRDATA5CH1_CR_RXPERBITRANK0_Lane7_OFF (28) + #define DDRDATA5CH1_CR_RXPERBITRANK0_Lane7_WID ( 4) + #define DDRDATA5CH1_CR_RXPERBITRANK0_Lane7_MSK (0xF0000000) + #define DDRDATA5CH1_CR_RXPERBITRANK0_Lane7_MAX (0x0000000F) + +#define DDRDATA5CH1_CR_RXPERBITRANK1_REG (0x00000B14) + #define DDRDATA5CH1_CR_RXPERBITRANK1_Lane0_OFF ( 0) + #define DDRDATA5CH1_CR_RXPERBITRANK1_Lane0_WID ( 4) + #define DDRDATA5CH1_CR_RXPERBITRANK1_Lane0_MSK (0x0000000F) + #define DDRDATA5CH1_CR_RXPERBITRANK1_Lane0_MAX (0x0000000F) + #define DDRDATA5CH1_CR_RXPERBITRANK1_Lane1_OFF ( 4) + #define DDRDATA5CH1_CR_RXPERBITRANK1_Lane1_WID ( 4) + #define DDRDATA5CH1_CR_RXPERBITRANK1_Lane1_MSK (0x000000F0) + #define DDRDATA5CH1_CR_RXPERBITRANK1_Lane1_MAX (0x0000000F) + #define DDRDATA5CH1_CR_RXPERBITRANK1_Lane2_OFF ( 8) + #define DDRDATA5CH1_CR_RXPERBITRANK1_Lane2_WID ( 4) + #define DDRDATA5CH1_CR_RXPERBITRANK1_Lane2_MSK (0x00000F00) + #define DDRDATA5CH1_CR_RXPERBITRANK1_Lane2_MAX (0x0000000F) + #define DDRDATA5CH1_CR_RXPERBITRANK1_Lane3_OFF (12) + #define DDRDATA5CH1_CR_RXPERBITRANK1_Lane3_WID ( 4) + #define DDRDATA5CH1_CR_RXPERBITRANK1_Lane3_MSK (0x0000F000) + #define DDRDATA5CH1_CR_RXPERBITRANK1_Lane3_MAX (0x0000000F) + #define DDRDATA5CH1_CR_RXPERBITRANK1_Lane4_OFF (16) + #define DDRDATA5CH1_CR_RXPERBITRANK1_Lane4_WID ( 4) + #define DDRDATA5CH1_CR_RXPERBITRANK1_Lane4_MSK (0x000F0000) + #define DDRDATA5CH1_CR_RXPERBITRANK1_Lane4_MAX (0x0000000F) + #define DDRDATA5CH1_CR_RXPERBITRANK1_Lane5_OFF (20) + #define DDRDATA5CH1_CR_RXPERBITRANK1_Lane5_WID ( 4) + #define DDRDATA5CH1_CR_RXPERBITRANK1_Lane5_MSK (0x00F00000) + #define DDRDATA5CH1_CR_RXPERBITRANK1_Lane5_MAX (0x0000000F) + #define DDRDATA5CH1_CR_RXPERBITRANK1_Lane6_OFF (24) + #define DDRDATA5CH1_CR_RXPERBITRANK1_Lane6_WID ( 4) + #define DDRDATA5CH1_CR_RXPERBITRANK1_Lane6_MSK (0x0F000000) + #define DDRDATA5CH1_CR_RXPERBITRANK1_Lane6_MAX (0x0000000F) + #define DDRDATA5CH1_CR_RXPERBITRANK1_Lane7_OFF (28) + #define DDRDATA5CH1_CR_RXPERBITRANK1_Lane7_WID ( 4) + #define DDRDATA5CH1_CR_RXPERBITRANK1_Lane7_MSK (0xF0000000) + #define DDRDATA5CH1_CR_RXPERBITRANK1_Lane7_MAX (0x0000000F) + +#define DDRDATA5CH1_CR_RXPERBITRANK2_REG (0x00000B18) + #define DDRDATA5CH1_CR_RXPERBITRANK2_Lane0_OFF ( 0) + #define DDRDATA5CH1_CR_RXPERBITRANK2_Lane0_WID ( 4) + #define DDRDATA5CH1_CR_RXPERBITRANK2_Lane0_MSK (0x0000000F) + #define DDRDATA5CH1_CR_RXPERBITRANK2_Lane0_MAX (0x0000000F) + #define DDRDATA5CH1_CR_RXPERBITRANK2_Lane1_OFF ( 4) + #define DDRDATA5CH1_CR_RXPERBITRANK2_Lane1_WID ( 4) + #define DDRDATA5CH1_CR_RXPERBITRANK2_Lane1_MSK (0x000000F0) + #define DDRDATA5CH1_CR_RXPERBITRANK2_Lane1_MAX (0x0000000F) + #define DDRDATA5CH1_CR_RXPERBITRANK2_Lane2_OFF ( 8) + #define DDRDATA5CH1_CR_RXPERBITRANK2_Lane2_WID ( 4) + #define DDRDATA5CH1_CR_RXPERBITRANK2_Lane2_MSK (0x00000F00) + #define DDRDATA5CH1_CR_RXPERBITRANK2_Lane2_MAX (0x0000000F) + #define DDRDATA5CH1_CR_RXPERBITRANK2_Lane3_OFF (12) + #define DDRDATA5CH1_CR_RXPERBITRANK2_Lane3_WID ( 4) + #define DDRDATA5CH1_CR_RXPERBITRANK2_Lane3_MSK (0x0000F000) + #define DDRDATA5CH1_CR_RXPERBITRANK2_Lane3_MAX (0x0000000F) + #define DDRDATA5CH1_CR_RXPERBITRANK2_Lane4_OFF (16) + #define DDRDATA5CH1_CR_RXPERBITRANK2_Lane4_WID ( 4) + #define DDRDATA5CH1_CR_RXPERBITRANK2_Lane4_MSK (0x000F0000) + #define DDRDATA5CH1_CR_RXPERBITRANK2_Lane4_MAX (0x0000000F) + #define DDRDATA5CH1_CR_RXPERBITRANK2_Lane5_OFF (20) + #define DDRDATA5CH1_CR_RXPERBITRANK2_Lane5_WID ( 4) + #define DDRDATA5CH1_CR_RXPERBITRANK2_Lane5_MSK (0x00F00000) + #define DDRDATA5CH1_CR_RXPERBITRANK2_Lane5_MAX (0x0000000F) + #define DDRDATA5CH1_CR_RXPERBITRANK2_Lane6_OFF (24) + #define DDRDATA5CH1_CR_RXPERBITRANK2_Lane6_WID ( 4) + #define DDRDATA5CH1_CR_RXPERBITRANK2_Lane6_MSK (0x0F000000) + #define DDRDATA5CH1_CR_RXPERBITRANK2_Lane6_MAX (0x0000000F) + #define DDRDATA5CH1_CR_RXPERBITRANK2_Lane7_OFF (28) + #define DDRDATA5CH1_CR_RXPERBITRANK2_Lane7_WID ( 4) + #define DDRDATA5CH1_CR_RXPERBITRANK2_Lane7_MSK (0xF0000000) + #define DDRDATA5CH1_CR_RXPERBITRANK2_Lane7_MAX (0x0000000F) + +#define DDRDATA5CH1_CR_RXPERBITRANK3_REG (0x00000B1C) + #define DDRDATA5CH1_CR_RXPERBITRANK3_Lane0_OFF ( 0) + #define DDRDATA5CH1_CR_RXPERBITRANK3_Lane0_WID ( 4) + #define DDRDATA5CH1_CR_RXPERBITRANK3_Lane0_MSK (0x0000000F) + #define DDRDATA5CH1_CR_RXPERBITRANK3_Lane0_MAX (0x0000000F) + #define DDRDATA5CH1_CR_RXPERBITRANK3_Lane1_OFF ( 4) + #define DDRDATA5CH1_CR_RXPERBITRANK3_Lane1_WID ( 4) + #define DDRDATA5CH1_CR_RXPERBITRANK3_Lane1_MSK (0x000000F0) + #define DDRDATA5CH1_CR_RXPERBITRANK3_Lane1_MAX (0x0000000F) + #define DDRDATA5CH1_CR_RXPERBITRANK3_Lane2_OFF ( 8) + #define DDRDATA5CH1_CR_RXPERBITRANK3_Lane2_WID ( 4) + #define DDRDATA5CH1_CR_RXPERBITRANK3_Lane2_MSK (0x00000F00) + #define DDRDATA5CH1_CR_RXPERBITRANK3_Lane2_MAX (0x0000000F) + #define DDRDATA5CH1_CR_RXPERBITRANK3_Lane3_OFF (12) + #define DDRDATA5CH1_CR_RXPERBITRANK3_Lane3_WID ( 4) + #define DDRDATA5CH1_CR_RXPERBITRANK3_Lane3_MSK (0x0000F000) + #define DDRDATA5CH1_CR_RXPERBITRANK3_Lane3_MAX (0x0000000F) + #define DDRDATA5CH1_CR_RXPERBITRANK3_Lane4_OFF (16) + #define DDRDATA5CH1_CR_RXPERBITRANK3_Lane4_WID ( 4) + #define DDRDATA5CH1_CR_RXPERBITRANK3_Lane4_MSK (0x000F0000) + #define DDRDATA5CH1_CR_RXPERBITRANK3_Lane4_MAX (0x0000000F) + #define DDRDATA5CH1_CR_RXPERBITRANK3_Lane5_OFF (20) + #define DDRDATA5CH1_CR_RXPERBITRANK3_Lane5_WID ( 4) + #define DDRDATA5CH1_CR_RXPERBITRANK3_Lane5_MSK (0x00F00000) + #define DDRDATA5CH1_CR_RXPERBITRANK3_Lane5_MAX (0x0000000F) + #define DDRDATA5CH1_CR_RXPERBITRANK3_Lane6_OFF (24) + #define DDRDATA5CH1_CR_RXPERBITRANK3_Lane6_WID ( 4) + #define DDRDATA5CH1_CR_RXPERBITRANK3_Lane6_MSK (0x0F000000) + #define DDRDATA5CH1_CR_RXPERBITRANK3_Lane6_MAX (0x0000000F) + #define DDRDATA5CH1_CR_RXPERBITRANK3_Lane7_OFF (28) + #define DDRDATA5CH1_CR_RXPERBITRANK3_Lane7_WID ( 4) + #define DDRDATA5CH1_CR_RXPERBITRANK3_Lane7_MSK (0xF0000000) + #define DDRDATA5CH1_CR_RXPERBITRANK3_Lane7_MAX (0x0000000F) + +#define DDRDATA5CH1_CR_TXTRAINRANK0_REG (0x00000B20) + #define DDRDATA5CH1_CR_TXTRAINRANK0_TxDqDelay_OFF ( 0) + #define DDRDATA5CH1_CR_TXTRAINRANK0_TxDqDelay_WID ( 9) + #define DDRDATA5CH1_CR_TXTRAINRANK0_TxDqDelay_MSK (0x000001FF) + #define DDRDATA5CH1_CR_TXTRAINRANK0_TxDqDelay_MAX (0x000001FF) + #define DDRDATA5CH1_CR_TXTRAINRANK0_TxDqsDelay_OFF ( 9) + #define DDRDATA5CH1_CR_TXTRAINRANK0_TxDqsDelay_WID ( 9) + #define DDRDATA5CH1_CR_TXTRAINRANK0_TxDqsDelay_MSK (0x0003FE00) + #define DDRDATA5CH1_CR_TXTRAINRANK0_TxDqsDelay_MAX (0x000001FF) + #define DDRDATA5CH1_CR_TXTRAINRANK0_Spare0_OFF (18) + #define DDRDATA5CH1_CR_TXTRAINRANK0_Spare0_WID ( 2) + #define DDRDATA5CH1_CR_TXTRAINRANK0_Spare0_MSK (0x000C0000) + #define DDRDATA5CH1_CR_TXTRAINRANK0_Spare0_MAX (0x00000003) + #define DDRDATA5CH1_CR_TXTRAINRANK0_TxEqualization_OFF (20) + #define DDRDATA5CH1_CR_TXTRAINRANK0_TxEqualization_WID ( 6) + #define DDRDATA5CH1_CR_TXTRAINRANK0_TxEqualization_MSK (0x03F00000) + #define DDRDATA5CH1_CR_TXTRAINRANK0_TxEqualization_MAX (0x0000003F) + #define DDRDATA5CH1_CR_TXTRAINRANK0_Spare1_OFF (26) + #define DDRDATA5CH1_CR_TXTRAINRANK0_Spare1_WID ( 6) + #define DDRDATA5CH1_CR_TXTRAINRANK0_Spare1_MSK (0xFC000000) + #define DDRDATA5CH1_CR_TXTRAINRANK0_Spare1_MAX (0x0000003F) + +#define DDRDATA5CH1_CR_TXTRAINRANK1_REG (0x00000B24) + #define DDRDATA5CH1_CR_TXTRAINRANK1_TxDqDelay_OFF ( 0) + #define DDRDATA5CH1_CR_TXTRAINRANK1_TxDqDelay_WID ( 9) + #define DDRDATA5CH1_CR_TXTRAINRANK1_TxDqDelay_MSK (0x000001FF) + #define DDRDATA5CH1_CR_TXTRAINRANK1_TxDqDelay_MAX (0x000001FF) + #define DDRDATA5CH1_CR_TXTRAINRANK1_TxDqsDelay_OFF ( 9) + #define DDRDATA5CH1_CR_TXTRAINRANK1_TxDqsDelay_WID ( 9) + #define DDRDATA5CH1_CR_TXTRAINRANK1_TxDqsDelay_MSK (0x0003FE00) + #define DDRDATA5CH1_CR_TXTRAINRANK1_TxDqsDelay_MAX (0x000001FF) + #define DDRDATA5CH1_CR_TXTRAINRANK1_Spare0_OFF (18) + #define DDRDATA5CH1_CR_TXTRAINRANK1_Spare0_WID ( 2) + #define DDRDATA5CH1_CR_TXTRAINRANK1_Spare0_MSK (0x000C0000) + #define DDRDATA5CH1_CR_TXTRAINRANK1_Spare0_MAX (0x00000003) + #define DDRDATA5CH1_CR_TXTRAINRANK1_TxEqualization_OFF (20) + #define DDRDATA5CH1_CR_TXTRAINRANK1_TxEqualization_WID ( 6) + #define DDRDATA5CH1_CR_TXTRAINRANK1_TxEqualization_MSK (0x03F00000) + #define DDRDATA5CH1_CR_TXTRAINRANK1_TxEqualization_MAX (0x0000003F) + #define DDRDATA5CH1_CR_TXTRAINRANK1_Spare1_OFF (26) + #define DDRDATA5CH1_CR_TXTRAINRANK1_Spare1_WID ( 6) + #define DDRDATA5CH1_CR_TXTRAINRANK1_Spare1_MSK (0xFC000000) + #define DDRDATA5CH1_CR_TXTRAINRANK1_Spare1_MAX (0x0000003F) + +#define DDRDATA5CH1_CR_TXTRAINRANK2_REG (0x00000B28) + #define DDRDATA5CH1_CR_TXTRAINRANK2_TxDqDelay_OFF ( 0) + #define DDRDATA5CH1_CR_TXTRAINRANK2_TxDqDelay_WID ( 9) + #define DDRDATA5CH1_CR_TXTRAINRANK2_TxDqDelay_MSK (0x000001FF) + #define DDRDATA5CH1_CR_TXTRAINRANK2_TxDqDelay_MAX (0x000001FF) + #define DDRDATA5CH1_CR_TXTRAINRANK2_TxDqsDelay_OFF ( 9) + #define DDRDATA5CH1_CR_TXTRAINRANK2_TxDqsDelay_WID ( 9) + #define DDRDATA5CH1_CR_TXTRAINRANK2_TxDqsDelay_MSK (0x0003FE00) + #define DDRDATA5CH1_CR_TXTRAINRANK2_TxDqsDelay_MAX (0x000001FF) + #define DDRDATA5CH1_CR_TXTRAINRANK2_Spare0_OFF (18) + #define DDRDATA5CH1_CR_TXTRAINRANK2_Spare0_WID ( 2) + #define DDRDATA5CH1_CR_TXTRAINRANK2_Spare0_MSK (0x000C0000) + #define DDRDATA5CH1_CR_TXTRAINRANK2_Spare0_MAX (0x00000003) + #define DDRDATA5CH1_CR_TXTRAINRANK2_TxEqualization_OFF (20) + #define DDRDATA5CH1_CR_TXTRAINRANK2_TxEqualization_WID ( 6) + #define DDRDATA5CH1_CR_TXTRAINRANK2_TxEqualization_MSK (0x03F00000) + #define DDRDATA5CH1_CR_TXTRAINRANK2_TxEqualization_MAX (0x0000003F) + #define DDRDATA5CH1_CR_TXTRAINRANK2_Spare1_OFF (26) + #define DDRDATA5CH1_CR_TXTRAINRANK2_Spare1_WID ( 6) + #define DDRDATA5CH1_CR_TXTRAINRANK2_Spare1_MSK (0xFC000000) + #define DDRDATA5CH1_CR_TXTRAINRANK2_Spare1_MAX (0x0000003F) + +#define DDRDATA5CH1_CR_TXTRAINRANK3_REG (0x00000B2C) + #define DDRDATA5CH1_CR_TXTRAINRANK3_TxDqDelay_OFF ( 0) + #define DDRDATA5CH1_CR_TXTRAINRANK3_TxDqDelay_WID ( 9) + #define DDRDATA5CH1_CR_TXTRAINRANK3_TxDqDelay_MSK (0x000001FF) + #define DDRDATA5CH1_CR_TXTRAINRANK3_TxDqDelay_MAX (0x000001FF) + #define DDRDATA5CH1_CR_TXTRAINRANK3_TxDqsDelay_OFF ( 9) + #define DDRDATA5CH1_CR_TXTRAINRANK3_TxDqsDelay_WID ( 9) + #define DDRDATA5CH1_CR_TXTRAINRANK3_TxDqsDelay_MSK (0x0003FE00) + #define DDRDATA5CH1_CR_TXTRAINRANK3_TxDqsDelay_MAX (0x000001FF) + #define DDRDATA5CH1_CR_TXTRAINRANK3_Spare0_OFF (18) + #define DDRDATA5CH1_CR_TXTRAINRANK3_Spare0_WID ( 2) + #define DDRDATA5CH1_CR_TXTRAINRANK3_Spare0_MSK (0x000C0000) + #define DDRDATA5CH1_CR_TXTRAINRANK3_Spare0_MAX (0x00000003) + #define DDRDATA5CH1_CR_TXTRAINRANK3_TxEqualization_OFF (20) + #define DDRDATA5CH1_CR_TXTRAINRANK3_TxEqualization_WID ( 6) + #define DDRDATA5CH1_CR_TXTRAINRANK3_TxEqualization_MSK (0x03F00000) + #define DDRDATA5CH1_CR_TXTRAINRANK3_TxEqualization_MAX (0x0000003F) + #define DDRDATA5CH1_CR_TXTRAINRANK3_Spare1_OFF (26) + #define DDRDATA5CH1_CR_TXTRAINRANK3_Spare1_WID ( 6) + #define DDRDATA5CH1_CR_TXTRAINRANK3_Spare1_MSK (0xFC000000) + #define DDRDATA5CH1_CR_TXTRAINRANK3_Spare1_MAX (0x0000003F) + +#define DDRDATA5CH1_CR_TXPERBITRANK0_REG (0x00000B30) + #define DDRDATA5CH1_CR_TXPERBITRANK0_Lane0_OFF ( 0) + #define DDRDATA5CH1_CR_TXPERBITRANK0_Lane0_WID ( 4) + #define DDRDATA5CH1_CR_TXPERBITRANK0_Lane0_MSK (0x0000000F) + #define DDRDATA5CH1_CR_TXPERBITRANK0_Lane0_MAX (0x0000000F) + #define DDRDATA5CH1_CR_TXPERBITRANK0_Lane1_OFF ( 4) + #define DDRDATA5CH1_CR_TXPERBITRANK0_Lane1_WID ( 4) + #define DDRDATA5CH1_CR_TXPERBITRANK0_Lane1_MSK (0x000000F0) + #define DDRDATA5CH1_CR_TXPERBITRANK0_Lane1_MAX (0x0000000F) + #define DDRDATA5CH1_CR_TXPERBITRANK0_Lane2_OFF ( 8) + #define DDRDATA5CH1_CR_TXPERBITRANK0_Lane2_WID ( 4) + #define DDRDATA5CH1_CR_TXPERBITRANK0_Lane2_MSK (0x00000F00) + #define DDRDATA5CH1_CR_TXPERBITRANK0_Lane2_MAX (0x0000000F) + #define DDRDATA5CH1_CR_TXPERBITRANK0_Lane3_OFF (12) + #define DDRDATA5CH1_CR_TXPERBITRANK0_Lane3_WID ( 4) + #define DDRDATA5CH1_CR_TXPERBITRANK0_Lane3_MSK (0x0000F000) + #define DDRDATA5CH1_CR_TXPERBITRANK0_Lane3_MAX (0x0000000F) + #define DDRDATA5CH1_CR_TXPERBITRANK0_Lane4_OFF (16) + #define DDRDATA5CH1_CR_TXPERBITRANK0_Lane4_WID ( 4) + #define DDRDATA5CH1_CR_TXPERBITRANK0_Lane4_MSK (0x000F0000) + #define DDRDATA5CH1_CR_TXPERBITRANK0_Lane4_MAX (0x0000000F) + #define DDRDATA5CH1_CR_TXPERBITRANK0_Lane5_OFF (20) + #define DDRDATA5CH1_CR_TXPERBITRANK0_Lane5_WID ( 4) + #define DDRDATA5CH1_CR_TXPERBITRANK0_Lane5_MSK (0x00F00000) + #define DDRDATA5CH1_CR_TXPERBITRANK0_Lane5_MAX (0x0000000F) + #define DDRDATA5CH1_CR_TXPERBITRANK0_Lane6_OFF (24) + #define DDRDATA5CH1_CR_TXPERBITRANK0_Lane6_WID ( 4) + #define DDRDATA5CH1_CR_TXPERBITRANK0_Lane6_MSK (0x0F000000) + #define DDRDATA5CH1_CR_TXPERBITRANK0_Lane6_MAX (0x0000000F) + #define DDRDATA5CH1_CR_TXPERBITRANK0_Lane7_OFF (28) + #define DDRDATA5CH1_CR_TXPERBITRANK0_Lane7_WID ( 4) + #define DDRDATA5CH1_CR_TXPERBITRANK0_Lane7_MSK (0xF0000000) + #define DDRDATA5CH1_CR_TXPERBITRANK0_Lane7_MAX (0x0000000F) + +#define DDRDATA5CH1_CR_TXPERBITRANK1_REG (0x00000B34) + #define DDRDATA5CH1_CR_TXPERBITRANK1_Lane0_OFF ( 0) + #define DDRDATA5CH1_CR_TXPERBITRANK1_Lane0_WID ( 4) + #define DDRDATA5CH1_CR_TXPERBITRANK1_Lane0_MSK (0x0000000F) + #define DDRDATA5CH1_CR_TXPERBITRANK1_Lane0_MAX (0x0000000F) + #define DDRDATA5CH1_CR_TXPERBITRANK1_Lane1_OFF ( 4) + #define DDRDATA5CH1_CR_TXPERBITRANK1_Lane1_WID ( 4) + #define DDRDATA5CH1_CR_TXPERBITRANK1_Lane1_MSK (0x000000F0) + #define DDRDATA5CH1_CR_TXPERBITRANK1_Lane1_MAX (0x0000000F) + #define DDRDATA5CH1_CR_TXPERBITRANK1_Lane2_OFF ( 8) + #define DDRDATA5CH1_CR_TXPERBITRANK1_Lane2_WID ( 4) + #define DDRDATA5CH1_CR_TXPERBITRANK1_Lane2_MSK (0x00000F00) + #define DDRDATA5CH1_CR_TXPERBITRANK1_Lane2_MAX (0x0000000F) + #define DDRDATA5CH1_CR_TXPERBITRANK1_Lane3_OFF (12) + #define DDRDATA5CH1_CR_TXPERBITRANK1_Lane3_WID ( 4) + #define DDRDATA5CH1_CR_TXPERBITRANK1_Lane3_MSK (0x0000F000) + #define DDRDATA5CH1_CR_TXPERBITRANK1_Lane3_MAX (0x0000000F) + #define DDRDATA5CH1_CR_TXPERBITRANK1_Lane4_OFF (16) + #define DDRDATA5CH1_CR_TXPERBITRANK1_Lane4_WID ( 4) + #define DDRDATA5CH1_CR_TXPERBITRANK1_Lane4_MSK (0x000F0000) + #define DDRDATA5CH1_CR_TXPERBITRANK1_Lane4_MAX (0x0000000F) + #define DDRDATA5CH1_CR_TXPERBITRANK1_Lane5_OFF (20) + #define DDRDATA5CH1_CR_TXPERBITRANK1_Lane5_WID ( 4) + #define DDRDATA5CH1_CR_TXPERBITRANK1_Lane5_MSK (0x00F00000) + #define DDRDATA5CH1_CR_TXPERBITRANK1_Lane5_MAX (0x0000000F) + #define DDRDATA5CH1_CR_TXPERBITRANK1_Lane6_OFF (24) + #define DDRDATA5CH1_CR_TXPERBITRANK1_Lane6_WID ( 4) + #define DDRDATA5CH1_CR_TXPERBITRANK1_Lane6_MSK (0x0F000000) + #define DDRDATA5CH1_CR_TXPERBITRANK1_Lane6_MAX (0x0000000F) + #define DDRDATA5CH1_CR_TXPERBITRANK1_Lane7_OFF (28) + #define DDRDATA5CH1_CR_TXPERBITRANK1_Lane7_WID ( 4) + #define DDRDATA5CH1_CR_TXPERBITRANK1_Lane7_MSK (0xF0000000) + #define DDRDATA5CH1_CR_TXPERBITRANK1_Lane7_MAX (0x0000000F) + +#define DDRDATA5CH1_CR_TXPERBITRANK2_REG (0x00000B38) + #define DDRDATA5CH1_CR_TXPERBITRANK2_Lane0_OFF ( 0) + #define DDRDATA5CH1_CR_TXPERBITRANK2_Lane0_WID ( 4) + #define DDRDATA5CH1_CR_TXPERBITRANK2_Lane0_MSK (0x0000000F) + #define DDRDATA5CH1_CR_TXPERBITRANK2_Lane0_MAX (0x0000000F) + #define DDRDATA5CH1_CR_TXPERBITRANK2_Lane1_OFF ( 4) + #define DDRDATA5CH1_CR_TXPERBITRANK2_Lane1_WID ( 4) + #define DDRDATA5CH1_CR_TXPERBITRANK2_Lane1_MSK (0x000000F0) + #define DDRDATA5CH1_CR_TXPERBITRANK2_Lane1_MAX (0x0000000F) + #define DDRDATA5CH1_CR_TXPERBITRANK2_Lane2_OFF ( 8) + #define DDRDATA5CH1_CR_TXPERBITRANK2_Lane2_WID ( 4) + #define DDRDATA5CH1_CR_TXPERBITRANK2_Lane2_MSK (0x00000F00) + #define DDRDATA5CH1_CR_TXPERBITRANK2_Lane2_MAX (0x0000000F) + #define DDRDATA5CH1_CR_TXPERBITRANK2_Lane3_OFF (12) + #define DDRDATA5CH1_CR_TXPERBITRANK2_Lane3_WID ( 4) + #define DDRDATA5CH1_CR_TXPERBITRANK2_Lane3_MSK (0x0000F000) + #define DDRDATA5CH1_CR_TXPERBITRANK2_Lane3_MAX (0x0000000F) + #define DDRDATA5CH1_CR_TXPERBITRANK2_Lane4_OFF (16) + #define DDRDATA5CH1_CR_TXPERBITRANK2_Lane4_WID ( 4) + #define DDRDATA5CH1_CR_TXPERBITRANK2_Lane4_MSK (0x000F0000) + #define DDRDATA5CH1_CR_TXPERBITRANK2_Lane4_MAX (0x0000000F) + #define DDRDATA5CH1_CR_TXPERBITRANK2_Lane5_OFF (20) + #define DDRDATA5CH1_CR_TXPERBITRANK2_Lane5_WID ( 4) + #define DDRDATA5CH1_CR_TXPERBITRANK2_Lane5_MSK (0x00F00000) + #define DDRDATA5CH1_CR_TXPERBITRANK2_Lane5_MAX (0x0000000F) + #define DDRDATA5CH1_CR_TXPERBITRANK2_Lane6_OFF (24) + #define DDRDATA5CH1_CR_TXPERBITRANK2_Lane6_WID ( 4) + #define DDRDATA5CH1_CR_TXPERBITRANK2_Lane6_MSK (0x0F000000) + #define DDRDATA5CH1_CR_TXPERBITRANK2_Lane6_MAX (0x0000000F) + #define DDRDATA5CH1_CR_TXPERBITRANK2_Lane7_OFF (28) + #define DDRDATA5CH1_CR_TXPERBITRANK2_Lane7_WID ( 4) + #define DDRDATA5CH1_CR_TXPERBITRANK2_Lane7_MSK (0xF0000000) + #define DDRDATA5CH1_CR_TXPERBITRANK2_Lane7_MAX (0x0000000F) + +#define DDRDATA5CH1_CR_TXPERBITRANK3_REG (0x00000B3C) + #define DDRDATA5CH1_CR_TXPERBITRANK3_Lane0_OFF ( 0) + #define DDRDATA5CH1_CR_TXPERBITRANK3_Lane0_WID ( 4) + #define DDRDATA5CH1_CR_TXPERBITRANK3_Lane0_MSK (0x0000000F) + #define DDRDATA5CH1_CR_TXPERBITRANK3_Lane0_MAX (0x0000000F) + #define DDRDATA5CH1_CR_TXPERBITRANK3_Lane1_OFF ( 4) + #define DDRDATA5CH1_CR_TXPERBITRANK3_Lane1_WID ( 4) + #define DDRDATA5CH1_CR_TXPERBITRANK3_Lane1_MSK (0x000000F0) + #define DDRDATA5CH1_CR_TXPERBITRANK3_Lane1_MAX (0x0000000F) + #define DDRDATA5CH1_CR_TXPERBITRANK3_Lane2_OFF ( 8) + #define DDRDATA5CH1_CR_TXPERBITRANK3_Lane2_WID ( 4) + #define DDRDATA5CH1_CR_TXPERBITRANK3_Lane2_MSK (0x00000F00) + #define DDRDATA5CH1_CR_TXPERBITRANK3_Lane2_MAX (0x0000000F) + #define DDRDATA5CH1_CR_TXPERBITRANK3_Lane3_OFF (12) + #define DDRDATA5CH1_CR_TXPERBITRANK3_Lane3_WID ( 4) + #define DDRDATA5CH1_CR_TXPERBITRANK3_Lane3_MSK (0x0000F000) + #define DDRDATA5CH1_CR_TXPERBITRANK3_Lane3_MAX (0x0000000F) + #define DDRDATA5CH1_CR_TXPERBITRANK3_Lane4_OFF (16) + #define DDRDATA5CH1_CR_TXPERBITRANK3_Lane4_WID ( 4) + #define DDRDATA5CH1_CR_TXPERBITRANK3_Lane4_MSK (0x000F0000) + #define DDRDATA5CH1_CR_TXPERBITRANK3_Lane4_MAX (0x0000000F) + #define DDRDATA5CH1_CR_TXPERBITRANK3_Lane5_OFF (20) + #define DDRDATA5CH1_CR_TXPERBITRANK3_Lane5_WID ( 4) + #define DDRDATA5CH1_CR_TXPERBITRANK3_Lane5_MSK (0x00F00000) + #define DDRDATA5CH1_CR_TXPERBITRANK3_Lane5_MAX (0x0000000F) + #define DDRDATA5CH1_CR_TXPERBITRANK3_Lane6_OFF (24) + #define DDRDATA5CH1_CR_TXPERBITRANK3_Lane6_WID ( 4) + #define DDRDATA5CH1_CR_TXPERBITRANK3_Lane6_MSK (0x0F000000) + #define DDRDATA5CH1_CR_TXPERBITRANK3_Lane6_MAX (0x0000000F) + #define DDRDATA5CH1_CR_TXPERBITRANK3_Lane7_OFF (28) + #define DDRDATA5CH1_CR_TXPERBITRANK3_Lane7_WID ( 4) + #define DDRDATA5CH1_CR_TXPERBITRANK3_Lane7_MSK (0xF0000000) + #define DDRDATA5CH1_CR_TXPERBITRANK3_Lane7_MAX (0x0000000F) + +#define DDRDATA5CH1_CR_RCOMPDATA0_REG (0x00000B40) + #define DDRDATA5CH1_CR_RCOMPDATA0_RcompDrvUp_OFF ( 0) + #define DDRDATA5CH1_CR_RCOMPDATA0_RcompDrvUp_WID ( 6) + #define DDRDATA5CH1_CR_RCOMPDATA0_RcompDrvUp_MSK (0x0000003F) + #define DDRDATA5CH1_CR_RCOMPDATA0_RcompDrvUp_MAX (0x0000003F) + #define DDRDATA5CH1_CR_RCOMPDATA0_Spare0_OFF ( 6) + #define DDRDATA5CH1_CR_RCOMPDATA0_Spare0_WID ( 3) + #define DDRDATA5CH1_CR_RCOMPDATA0_Spare0_MSK (0x000001C0) + #define DDRDATA5CH1_CR_RCOMPDATA0_Spare0_MAX (0x00000007) + #define DDRDATA5CH1_CR_RCOMPDATA0_RcompDrvDown_OFF ( 9) + #define DDRDATA5CH1_CR_RCOMPDATA0_RcompDrvDown_WID ( 6) + #define DDRDATA5CH1_CR_RCOMPDATA0_RcompDrvDown_MSK (0x00007E00) + #define DDRDATA5CH1_CR_RCOMPDATA0_RcompDrvDown_MAX (0x0000003F) + #define DDRDATA5CH1_CR_RCOMPDATA0_VTComp_OFF (15) + #define DDRDATA5CH1_CR_RCOMPDATA0_VTComp_WID ( 5) + #define DDRDATA5CH1_CR_RCOMPDATA0_VTComp_MSK (0x000F8000) + #define DDRDATA5CH1_CR_RCOMPDATA0_VTComp_MAX (0x0000001F) + #define DDRDATA5CH1_CR_RCOMPDATA0_TcoComp_OFF (20) + #define DDRDATA5CH1_CR_RCOMPDATA0_TcoComp_WID ( 6) + #define DDRDATA5CH1_CR_RCOMPDATA0_TcoComp_MSK (0x03F00000) + #define DDRDATA5CH1_CR_RCOMPDATA0_TcoComp_MAX (0x0000003F) + #define DDRDATA5CH1_CR_RCOMPDATA0_SlewRateComp_OFF (26) + #define DDRDATA5CH1_CR_RCOMPDATA0_SlewRateComp_WID ( 5) + #define DDRDATA5CH1_CR_RCOMPDATA0_SlewRateComp_MSK (0x7C000000) + #define DDRDATA5CH1_CR_RCOMPDATA0_SlewRateComp_MAX (0x0000001F) + #define DDRDATA5CH1_CR_RCOMPDATA0_Spare2_OFF (31) + #define DDRDATA5CH1_CR_RCOMPDATA0_Spare2_WID ( 1) + #define DDRDATA5CH1_CR_RCOMPDATA0_Spare2_MSK (0x80000000) + #define DDRDATA5CH1_CR_RCOMPDATA0_Spare2_MAX (0x00000001) + +#define DDRDATA5CH1_CR_RCOMPDATA1_REG (0x00000B44) + #define DDRDATA5CH1_CR_RCOMPDATA1_RcompOdtUp_OFF ( 0) + #define DDRDATA5CH1_CR_RCOMPDATA1_RcompOdtUp_WID ( 6) + #define DDRDATA5CH1_CR_RCOMPDATA1_RcompOdtUp_MSK (0x0000003F) + #define DDRDATA5CH1_CR_RCOMPDATA1_RcompOdtUp_MAX (0x0000003F) + #define DDRDATA5CH1_CR_RCOMPDATA1_Spare0_OFF ( 6) + #define DDRDATA5CH1_CR_RCOMPDATA1_Spare0_WID ( 3) + #define DDRDATA5CH1_CR_RCOMPDATA1_Spare0_MSK (0x000001C0) + #define DDRDATA5CH1_CR_RCOMPDATA1_Spare0_MAX (0x00000007) + #define DDRDATA5CH1_CR_RCOMPDATA1_RcompOdtDown_OFF ( 9) + #define DDRDATA5CH1_CR_RCOMPDATA1_RcompOdtDown_WID ( 6) + #define DDRDATA5CH1_CR_RCOMPDATA1_RcompOdtDown_MSK (0x00007E00) + #define DDRDATA5CH1_CR_RCOMPDATA1_RcompOdtDown_MAX (0x0000003F) + #define DDRDATA5CH1_CR_RCOMPDATA1_Spare1_OFF (15) + #define DDRDATA5CH1_CR_RCOMPDATA1_Spare1_WID ( 1) + #define DDRDATA5CH1_CR_RCOMPDATA1_Spare1_MSK (0x00008000) + #define DDRDATA5CH1_CR_RCOMPDATA1_Spare1_MAX (0x00000001) + #define DDRDATA5CH1_CR_RCOMPDATA1_PanicDrvDn_OFF (16) + #define DDRDATA5CH1_CR_RCOMPDATA1_PanicDrvDn_WID ( 6) + #define DDRDATA5CH1_CR_RCOMPDATA1_PanicDrvDn_MSK (0x003F0000) + #define DDRDATA5CH1_CR_RCOMPDATA1_PanicDrvDn_MAX (0x0000003F) + #define DDRDATA5CH1_CR_RCOMPDATA1_PanicDrvUp_OFF (22) + #define DDRDATA5CH1_CR_RCOMPDATA1_PanicDrvUp_WID ( 6) + #define DDRDATA5CH1_CR_RCOMPDATA1_PanicDrvUp_MSK (0x0FC00000) + #define DDRDATA5CH1_CR_RCOMPDATA1_PanicDrvUp_MAX (0x0000003F) + #define DDRDATA5CH1_CR_RCOMPDATA1_LevelShifterComp_OFF (28) + #define DDRDATA5CH1_CR_RCOMPDATA1_LevelShifterComp_WID ( 3) + #define DDRDATA5CH1_CR_RCOMPDATA1_LevelShifterComp_MSK (0x70000000) + #define DDRDATA5CH1_CR_RCOMPDATA1_LevelShifterComp_MAX (0x00000007) + #define DDRDATA5CH1_CR_RCOMPDATA1_Spare2_OFF (31) + #define DDRDATA5CH1_CR_RCOMPDATA1_Spare2_WID ( 1) + #define DDRDATA5CH1_CR_RCOMPDATA1_Spare2_MSK (0x80000000) + #define DDRDATA5CH1_CR_RCOMPDATA1_Spare2_MAX (0x00000001) + +#define DDRDATA5CH1_CR_TXXTALK_REG (0x00000B48) + #define DDRDATA5CH1_CR_TXXTALK_Lane0_OFF ( 0) + #define DDRDATA5CH1_CR_TXXTALK_Lane0_WID ( 4) + #define DDRDATA5CH1_CR_TXXTALK_Lane0_MSK (0x0000000F) + #define DDRDATA5CH1_CR_TXXTALK_Lane0_MAX (0x0000000F) + #define DDRDATA5CH1_CR_TXXTALK_Lane1_OFF ( 4) + #define DDRDATA5CH1_CR_TXXTALK_Lane1_WID ( 4) + #define DDRDATA5CH1_CR_TXXTALK_Lane1_MSK (0x000000F0) + #define DDRDATA5CH1_CR_TXXTALK_Lane1_MAX (0x0000000F) + #define DDRDATA5CH1_CR_TXXTALK_Lane2_OFF ( 8) + #define DDRDATA5CH1_CR_TXXTALK_Lane2_WID ( 4) + #define DDRDATA5CH1_CR_TXXTALK_Lane2_MSK (0x00000F00) + #define DDRDATA5CH1_CR_TXXTALK_Lane2_MAX (0x0000000F) + #define DDRDATA5CH1_CR_TXXTALK_Lane3_OFF (12) + #define DDRDATA5CH1_CR_TXXTALK_Lane3_WID ( 4) + #define DDRDATA5CH1_CR_TXXTALK_Lane3_MSK (0x0000F000) + #define DDRDATA5CH1_CR_TXXTALK_Lane3_MAX (0x0000000F) + #define DDRDATA5CH1_CR_TXXTALK_Lane4_OFF (16) + #define DDRDATA5CH1_CR_TXXTALK_Lane4_WID ( 4) + #define DDRDATA5CH1_CR_TXXTALK_Lane4_MSK (0x000F0000) + #define DDRDATA5CH1_CR_TXXTALK_Lane4_MAX (0x0000000F) + #define DDRDATA5CH1_CR_TXXTALK_Lane5_OFF (20) + #define DDRDATA5CH1_CR_TXXTALK_Lane5_WID ( 4) + #define DDRDATA5CH1_CR_TXXTALK_Lane5_MSK (0x00F00000) + #define DDRDATA5CH1_CR_TXXTALK_Lane5_MAX (0x0000000F) + #define DDRDATA5CH1_CR_TXXTALK_Lane6_OFF (24) + #define DDRDATA5CH1_CR_TXXTALK_Lane6_WID ( 4) + #define DDRDATA5CH1_CR_TXXTALK_Lane6_MSK (0x0F000000) + #define DDRDATA5CH1_CR_TXXTALK_Lane6_MAX (0x0000000F) + #define DDRDATA5CH1_CR_TXXTALK_Lane7_OFF (28) + #define DDRDATA5CH1_CR_TXXTALK_Lane7_WID ( 4) + #define DDRDATA5CH1_CR_TXXTALK_Lane7_MSK (0xF0000000) + #define DDRDATA5CH1_CR_TXXTALK_Lane7_MAX (0x0000000F) + +#define DDRDATA5CH1_CR_RXOFFSETVDQ_REG (0x00000B4C) + #define DDRDATA5CH1_CR_RXOFFSETVDQ_Lane0_OFF ( 0) + #define DDRDATA5CH1_CR_RXOFFSETVDQ_Lane0_WID ( 4) + #define DDRDATA5CH1_CR_RXOFFSETVDQ_Lane0_MSK (0x0000000F) + #define DDRDATA5CH1_CR_RXOFFSETVDQ_Lane0_MAX (0x0000000F) + #define DDRDATA5CH1_CR_RXOFFSETVDQ_Lane1_OFF ( 4) + #define DDRDATA5CH1_CR_RXOFFSETVDQ_Lane1_WID ( 4) + #define DDRDATA5CH1_CR_RXOFFSETVDQ_Lane1_MSK (0x000000F0) + #define DDRDATA5CH1_CR_RXOFFSETVDQ_Lane1_MAX (0x0000000F) + #define DDRDATA5CH1_CR_RXOFFSETVDQ_Lane2_OFF ( 8) + #define DDRDATA5CH1_CR_RXOFFSETVDQ_Lane2_WID ( 4) + #define DDRDATA5CH1_CR_RXOFFSETVDQ_Lane2_MSK (0x00000F00) + #define DDRDATA5CH1_CR_RXOFFSETVDQ_Lane2_MAX (0x0000000F) + #define DDRDATA5CH1_CR_RXOFFSETVDQ_Lane3_OFF (12) + #define DDRDATA5CH1_CR_RXOFFSETVDQ_Lane3_WID ( 4) + #define DDRDATA5CH1_CR_RXOFFSETVDQ_Lane3_MSK (0x0000F000) + #define DDRDATA5CH1_CR_RXOFFSETVDQ_Lane3_MAX (0x0000000F) + #define DDRDATA5CH1_CR_RXOFFSETVDQ_Lane4_OFF (16) + #define DDRDATA5CH1_CR_RXOFFSETVDQ_Lane4_WID ( 4) + #define DDRDATA5CH1_CR_RXOFFSETVDQ_Lane4_MSK (0x000F0000) + #define DDRDATA5CH1_CR_RXOFFSETVDQ_Lane4_MAX (0x0000000F) + #define DDRDATA5CH1_CR_RXOFFSETVDQ_Lane5_OFF (20) + #define DDRDATA5CH1_CR_RXOFFSETVDQ_Lane5_WID ( 4) + #define DDRDATA5CH1_CR_RXOFFSETVDQ_Lane5_MSK (0x00F00000) + #define DDRDATA5CH1_CR_RXOFFSETVDQ_Lane5_MAX (0x0000000F) + #define DDRDATA5CH1_CR_RXOFFSETVDQ_Lane6_OFF (24) + #define DDRDATA5CH1_CR_RXOFFSETVDQ_Lane6_WID ( 4) + #define DDRDATA5CH1_CR_RXOFFSETVDQ_Lane6_MSK (0x0F000000) + #define DDRDATA5CH1_CR_RXOFFSETVDQ_Lane6_MAX (0x0000000F) + #define DDRDATA5CH1_CR_RXOFFSETVDQ_Lane7_OFF (28) + #define DDRDATA5CH1_CR_RXOFFSETVDQ_Lane7_WID ( 4) + #define DDRDATA5CH1_CR_RXOFFSETVDQ_Lane7_MSK (0xF0000000) + #define DDRDATA5CH1_CR_RXOFFSETVDQ_Lane7_MAX (0x0000000F) + +#define DDRDATA5CH1_CR_DDRDATARESERVED_REG (0x00000B50) + #define DDRDATA5CH1_CR_DDRDATARESERVED_Spare_OFF ( 0) + #define DDRDATA5CH1_CR_DDRDATARESERVED_Spare_WID (32) + #define DDRDATA5CH1_CR_DDRDATARESERVED_Spare_MSK (0xFFFFFFFF) + #define DDRDATA5CH1_CR_DDRDATARESERVED_Spare_MAX (0xFFFFFFFF) + +#define DDRDATA5CH1_CR_DATATRAINFEEDBACK_REG (0x00000B54) + #define DDRDATA5CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_OFF ( 0) + #define DDRDATA5CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_WID ( 9) + #define DDRDATA5CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_MSK (0x000001FF) + #define DDRDATA5CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_MAX (0x000001FF) + #define DDRDATA5CH1_CR_DATATRAINFEEDBACK_Spare_OFF ( 9) + #define DDRDATA5CH1_CR_DATATRAINFEEDBACK_Spare_WID (23) + #define DDRDATA5CH1_CR_DATATRAINFEEDBACK_Spare_MSK (0xFFFFFE00) + #define DDRDATA5CH1_CR_DATATRAINFEEDBACK_Spare_MAX (0x007FFFFF) + +#define DDRDATA5CH1_CR_DLLPITESTANDADC_REG (0x00000B58) + #define DDRDATA5CH1_CR_DLLPITESTANDADC_RunTest_OFF ( 0) + #define DDRDATA5CH1_CR_DLLPITESTANDADC_RunTest_WID ( 1) + #define DDRDATA5CH1_CR_DLLPITESTANDADC_RunTest_MSK (0x00000001) + #define DDRDATA5CH1_CR_DLLPITESTANDADC_RunTest_MAX (0x00000001) + #define DDRDATA5CH1_CR_DLLPITESTANDADC_RunTest_DEF (0x00000000) + #define DDRDATA5CH1_CR_DLLPITESTANDADC_Load_OFF ( 1) + #define DDRDATA5CH1_CR_DLLPITESTANDADC_Load_WID ( 1) + #define DDRDATA5CH1_CR_DLLPITESTANDADC_Load_MSK (0x00000002) + #define DDRDATA5CH1_CR_DLLPITESTANDADC_Load_MAX (0x00000001) + #define DDRDATA5CH1_CR_DLLPITESTANDADC_Load_DEF (0x00000000) + #define DDRDATA5CH1_CR_DLLPITESTANDADC_ModeHVM_OFF ( 2) + #define DDRDATA5CH1_CR_DLLPITESTANDADC_ModeHVM_WID ( 1) + #define DDRDATA5CH1_CR_DLLPITESTANDADC_ModeHVM_MSK (0x00000004) + #define DDRDATA5CH1_CR_DLLPITESTANDADC_ModeHVM_MAX (0x00000001) + #define DDRDATA5CH1_CR_DLLPITESTANDADC_ModeHVM_DEF (0x00000000) + #define DDRDATA5CH1_CR_DLLPITESTANDADC_ModeDV_OFF ( 3) + #define DDRDATA5CH1_CR_DLLPITESTANDADC_ModeDV_WID ( 1) + #define DDRDATA5CH1_CR_DLLPITESTANDADC_ModeDV_MSK (0x00000008) + #define DDRDATA5CH1_CR_DLLPITESTANDADC_ModeDV_MAX (0x00000001) + #define DDRDATA5CH1_CR_DLLPITESTANDADC_ModeDV_DEF (0x00000000) + #define DDRDATA5CH1_CR_DLLPITESTANDADC_ModeADC_OFF ( 4) + #define DDRDATA5CH1_CR_DLLPITESTANDADC_ModeADC_WID ( 1) + #define DDRDATA5CH1_CR_DLLPITESTANDADC_ModeADC_MSK (0x00000010) + #define DDRDATA5CH1_CR_DLLPITESTANDADC_ModeADC_MAX (0x00000001) + #define DDRDATA5CH1_CR_DLLPITESTANDADC_ModeADC_DEF (0x00000000) + #define DDRDATA5CH1_CR_DLLPITESTANDADC_LoadCount_OFF ( 5) + #define DDRDATA5CH1_CR_DLLPITESTANDADC_LoadCount_WID (10) + #define DDRDATA5CH1_CR_DLLPITESTANDADC_LoadCount_MSK (0x00007FE0) + #define DDRDATA5CH1_CR_DLLPITESTANDADC_LoadCount_MAX (0x000003FF) + #define DDRDATA5CH1_CR_DLLPITESTANDADC_CountStatus_OFF (15) + #define DDRDATA5CH1_CR_DLLPITESTANDADC_CountStatus_WID (10) + #define DDRDATA5CH1_CR_DLLPITESTANDADC_CountStatus_MSK (0x01FF8000) + #define DDRDATA5CH1_CR_DLLPITESTANDADC_CountStatus_MAX (0x000003FF) + #define DDRDATA5CH1_CR_DLLPITESTANDADC_CountStatus_DEF (0x00000000) + #define DDRDATA5CH1_CR_DLLPITESTANDADC_Spare_OFF (25) + #define DDRDATA5CH1_CR_DLLPITESTANDADC_Spare_WID ( 7) + #define DDRDATA5CH1_CR_DLLPITESTANDADC_Spare_MSK (0xFE000000) + #define DDRDATA5CH1_CR_DLLPITESTANDADC_Spare_MAX (0x0000007F) + +#define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_REG (0x00000B5C) + #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_OFF ( 0) + #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_WID ( 6) + #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MSK (0x0000003F) + #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MAX (0x0000003F) + #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_DEF (0x00000000) + #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_OFF ( 6) + #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_WID ( 6) + #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MSK (0x00000FC0) + #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MAX (0x0000003F) + #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_DEF (0x00000000) + #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_OFF (12) + #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_WID ( 5) + #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MSK (0x0001F000) + #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MAX (0x0000001F) + #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_DEF (0x00000000) + #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_OFF (17) + #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_WID ( 5) + #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MSK (0x003E0000) + #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MAX (0x0000001F) + #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_DEF (0x00000000) + #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_OFF (22) + #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_WID ( 5) + #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_MSK (0x07C00000) + #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_MAX (0x0000001F) + #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_DEF (0x00000000) + #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_OFF (27) + #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_WID ( 5) + #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MSK (0xF8000000) + #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MAX (0x0000001F) + #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_DEF (0x00000000) + +#define DDRDATA5CH1_CR_DDRCRDATACONTROL1_REG (0x00000B60) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_RefPi_OFF ( 0) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_RefPi_WID ( 4) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_RefPi_MSK (0x0000000F) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_RefPi_MAX (0x0000000F) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_RefPi_DEF (0x00000000) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_DllMask_OFF ( 4) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_DllMask_WID ( 2) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_DllMask_MSK (0x00000030) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_DllMask_MAX (0x00000003) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_DllMask_DEF (0x00000000) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_DllWeakLock_OFF ( 6) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_DllWeakLock_WID ( 1) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_DllWeakLock_MSK (0x00000040) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_DllWeakLock_MAX (0x00000001) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_DllWeakLock_DEF (0x00000000) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_OFF ( 7) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_WID ( 3) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MSK (0x00000380) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MAX (0x00000007) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_DEF (0x00000000) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_OFF (10) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_WID ( 3) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_MSK (0x00001C00) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_MAX (0x00000007) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_DEF (0x00000000) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_OdtDelay_OFF (13) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_OdtDelay_WID ( 4) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_OdtDelay_MSK (0x0001E000) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_OdtDelay_MAX (0x0000000F) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_OdtDelay_DEF (0x00000000) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_OdtDuration_OFF (17) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_OdtDuration_WID ( 3) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_OdtDuration_MSK (0x000E0000) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_OdtDuration_MAX (0x00000007) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_OdtDuration_DEF (0x00000000) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_OFF (20) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_WID ( 4) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_MSK (0x00F00000) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_MAX (0x0000000F) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_DEF (0x00000000) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_OFF (24) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_WID ( 3) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_MSK (0x07000000) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_MAX (0x00000007) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_DEF (0x00000000) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_OFF (27) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_WID ( 3) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_MSK (0x38000000) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_MAX (0x00000007) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_DEF (0x00000000) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_OFF (30) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_WID ( 1) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_MSK (0x40000000) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_MAX (0x00000001) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_DEF (0x00000000) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_Rsvd1_OFF (31) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_Rsvd1_WID ( 1) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_Rsvd1_MSK (0x80000000) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_Rsvd1_MAX (0x00000001) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_Rsvd1_DEF (0x00000000) + +#define DDRDATA5CH1_CR_DDRCRDATACONTROL2_REG (0x00000B64) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_OFF ( 0) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_WID ( 5) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_MSK (0x0000001F) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_MAX (0x0000001F) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_DEF (0x00000000) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_OFF ( 5) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_WID ( 1) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_MSK (0x00000020) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_MAX (0x00000001) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_DEF (0x00000000) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_ForceRxOn_OFF ( 6) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_ForceRxOn_WID ( 1) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_ForceRxOn_MSK (0x00000040) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_ForceRxOn_MAX (0x00000001) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_ForceRxOn_DEF (0x00000000) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_LeakerComp_OFF ( 7) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_LeakerComp_WID ( 2) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_LeakerComp_MSK (0x00000180) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_LeakerComp_MAX (0x00000003) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_LeakerComp_DEF (0x00000000) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_OFF ( 9) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_WID ( 4) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_MSK (0x00001E00) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_MAX (0x0000000F) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_DEF (0x00000008) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_OFF (13) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_WID ( 5) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_MSK (0x0003E000) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_MAX (0x0000001F) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_DEF (0x00000011) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_OFF (18) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_WID ( 1) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_MSK (0x00040000) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_MAX (0x00000001) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_DEF (0x00000000) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_Spare_OFF (19) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_Spare_WID (13) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_Spare_MSK (0xFFF80000) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_Spare_MAX (0x00001FFF) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_Spare_DEF (0x00000000) + +#define DDRDATA5CH1_CR_DDRCRVSSHIORVREFCONTROL_REG (0x00000B6C) + #define DDRDATA5CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_OFF ( 0) + #define DDRDATA5CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_WID (24) + #define DDRDATA5CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_MSK (0x00FFFFFF) + #define DDRDATA5CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_MAX (0x00FFFFFF) + #define DDRDATA5CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_DEF (0x00000000) + #define DDRDATA5CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_OFF (24) + #define DDRDATA5CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_WID ( 8) + #define DDRDATA5CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_MSK (0xFF000000) + #define DDRDATA5CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_MAX (0x000000FF) + #define DDRDATA5CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_DEF (0x00000000) + +#define DDRDATA5CH1_CR_DDRCRDATAOFFSETTRAIN_REG (0x00000B70) + #define DDRDATA5CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_OFF ( 0) + #define DDRDATA5CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_WID ( 6) + #define DDRDATA5CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MSK (0x0000003F) + #define DDRDATA5CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MAX (0x0000003F) + #define DDRDATA5CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_DEF (0x00000000) + #define DDRDATA5CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_OFF ( 6) + #define DDRDATA5CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_WID ( 6) + #define DDRDATA5CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MSK (0x00000FC0) + #define DDRDATA5CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MAX (0x0000003F) + #define DDRDATA5CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_DEF (0x00000000) + #define DDRDATA5CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_OFF (12) + #define DDRDATA5CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_WID ( 6) + #define DDRDATA5CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MSK (0x0003F000) + #define DDRDATA5CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MAX (0x0000003F) + #define DDRDATA5CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_DEF (0x00000000) + #define DDRDATA5CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_OFF (18) + #define DDRDATA5CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_WID ( 6) + #define DDRDATA5CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MSK (0x00FC0000) + #define DDRDATA5CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MAX (0x0000003F) + #define DDRDATA5CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_DEF (0x00000000) + #define DDRDATA5CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_OFF (24) + #define DDRDATA5CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_WID ( 7) + #define DDRDATA5CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MSK (0x7F000000) + #define DDRDATA5CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MAX (0x0000007F) + #define DDRDATA5CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_DEF (0x00000000) + #define DDRDATA5CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_OFF (31) + #define DDRDATA5CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_WID ( 1) + #define DDRDATA5CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_MSK (0x80000000) + #define DDRDATA5CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_MAX (0x00000001) + #define DDRDATA5CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_DEF (0x00000000) + +#define DDRDATA5CH1_CR_DDRCRDATACONTROL0_REG (0x00000B74) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_OFF ( 0) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_WID ( 1) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_MSK (0x00000001) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_MAX (0x00000001) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_DEF (0x00000000) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_OFF ( 1) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_WID ( 1) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_MSK (0x00000002) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_MAX (0x00000001) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_DEF (0x00000000) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_OFF ( 2) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_WID ( 1) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_MSK (0x00000004) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_MAX (0x00000001) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_DEF (0x00000000) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_OFF ( 3) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_WID ( 1) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MSK (0x00000008) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MAX (0x00000001) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_DEF (0x00000000) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_TxOn_OFF ( 4) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_TxOn_WID ( 1) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_TxOn_MSK (0x00000010) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_TxOn_MAX (0x00000001) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_TxOn_DEF (0x00000000) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RfOn_OFF ( 5) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RfOn_WID ( 1) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RfOn_MSK (0x00000020) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RfOn_MAX (0x00000001) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RfOn_DEF (0x00000000) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RxPiOn_OFF ( 6) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RxPiOn_WID ( 1) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RxPiOn_MSK (0x00000040) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RxPiOn_MAX (0x00000001) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RxPiOn_DEF (0x00000000) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_TxPiOn_OFF ( 7) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_TxPiOn_WID ( 1) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_TxPiOn_MSK (0x00000080) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_TxPiOn_MAX (0x00000001) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_TxPiOn_DEF (0x00000000) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_OFF ( 8) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_WID ( 1) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_MSK (0x00000100) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_MAX (0x00000001) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_DEF (0x00000000) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_OFF ( 9) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_WID ( 1) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MSK (0x00000200) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MAX (0x00000001) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_DEF (0x00000000) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_TxDisable_OFF (10) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_TxDisable_WID ( 1) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_TxDisable_MSK (0x00000400) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_TxDisable_MAX (0x00000001) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_TxDisable_DEF (0x00000000) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RxDisable_OFF (11) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RxDisable_WID ( 1) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RxDisable_MSK (0x00000800) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RxDisable_MAX (0x00000001) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RxDisable_DEF (0x00000000) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_TxLong_OFF (12) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_TxLong_WID ( 1) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_TxLong_MSK (0x00001000) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_TxLong_MAX (0x00000001) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_TxLong_DEF (0x00000000) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_OFF (13) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_WID ( 2) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_MSK (0x00006000) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_MAX (0x00000003) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_DEF (0x00000000) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RxReadPointer_OFF (15) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RxReadPointer_WID ( 3) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RxReadPointer_MSK (0x00038000) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RxReadPointer_MAX (0x00000007) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RxReadPointer_DEF (0x00000000) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_OFF (18) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_WID ( 1) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_MSK (0x00040000) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_MAX (0x00000001) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_DEF (0x00000000) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_OFF (19) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_WID ( 1) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_MSK (0x00080000) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_MAX (0x00000001) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_DEF (0x00000000) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_ReadRFRd_OFF (20) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_ReadRFRd_WID ( 1) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_ReadRFRd_MSK (0x00100000) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_ReadRFRd_MAX (0x00000001) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_ReadRFRd_DEF (0x00000000) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_ReadRFWr_OFF (21) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_ReadRFWr_WID ( 1) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_ReadRFWr_MSK (0x00200000) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_ReadRFWr_MAX (0x00000001) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_ReadRFWr_DEF (0x00000000) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_ReadRFRank_OFF (22) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_ReadRFRank_WID ( 2) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_ReadRFRank_MSK (0x00C00000) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_ReadRFRank_MAX (0x00000003) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_ReadRFRank_DEF (0x00000000) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_OFF (24) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_WID ( 1) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_MSK (0x01000000) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_MAX (0x00000001) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_DEF (0x00000000) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_OdtSampOff_OFF (25) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_OdtSampOff_WID ( 1) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_OdtSampOff_MSK (0x02000000) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_OdtSampOff_MAX (0x00000001) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_OdtSampOff_DEF (0x00000000) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_OFF (26) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_WID ( 1) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_MSK (0x04000000) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_MAX (0x00000001) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_DEF (0x00000000) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_OFF (27) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_WID ( 1) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MSK (0x08000000) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MAX (0x00000001) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_DEF (0x00000000) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_OFF (28) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_WID ( 1) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_MSK (0x10000000) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_MAX (0x00000001) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_DEF (0x00000000) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_OFF (29) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_WID ( 1) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_MSK (0x20000000) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_MAX (0x00000001) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_DEF (0x00000000) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_OFF (30) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_WID ( 1) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MSK (0x40000000) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MAX (0x00000001) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_DEF (0x00000000) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_OFF (31) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_WID ( 1) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_MSK (0x80000000) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_MAX (0x00000001) + #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_DEF (0x00000000) + +#define DDRDATA5CH1_CR_DDRCRVREFADJUST1_REG (0x00000B78) + #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_OFF ( 0) + #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_WID ( 7) + #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_MSK (0x0000007F) + #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_MAX (0x0000007F) + #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_DEF (0x00000000) + #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_OFF ( 7) + #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_WID ( 7) + #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_MSK (0x00003F80) + #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_MAX (0x0000007F) + #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_DEF (0x00000000) + #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_OFF (14) + #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_WID ( 7) + #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_MSK (0x001FC000) + #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_MAX (0x0000007F) + #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_DEF (0x00000000) + #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_OFF (21) + #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_WID ( 1) + #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_MSK (0x00200000) + #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_MAX (0x00000001) + #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_DEF (0x00000000) + #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_OFF (22) + #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_WID ( 1) + #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_MSK (0x00400000) + #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_MAX (0x00000001) + #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_DEF (0x00000000) + #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_OFF (23) + #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_WID ( 1) + #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_MSK (0x00800000) + #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_MAX (0x00000001) + #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_DEF (0x00000000) + #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_OFF (24) + #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_WID ( 2) + #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_MSK (0x03000000) + #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_MAX (0x00000003) + #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_DEF (0x00000000) + #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_OFF (26) + #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_WID ( 1) + #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_MSK (0x04000000) + #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_MAX (0x00000001) + #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_DEF (0x00000000) + #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_Rsvd_OFF (27) + #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_Rsvd_WID ( 2) + #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_Rsvd_MSK (0x18000000) + #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_Rsvd_MAX (0x00000003) + #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_Rsvd_DEF (0x00000000) + #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_caSlowBW_OFF (29) + #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_caSlowBW_WID ( 1) + #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_caSlowBW_MSK (0x20000000) + #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_caSlowBW_MAX (0x00000001) + #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_caSlowBW_DEF (0x00000000) + #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_OFF (30) + #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_WID ( 1) + #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_MSK (0x40000000) + #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_MAX (0x00000001) + #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_DEF (0x00000000) + #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_OFF (31) + #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_WID ( 1) + #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_MSK (0x80000000) + #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_MAX (0x00000001) + #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_DEF (0x00000000) + +#define DDRDATA6CH0_CR_RXTRAINRANK0_REG (0x00000C00) + #define DDRDATA6CH0_CR_RXTRAINRANK0_RxRcvEnPi_OFF ( 0) + #define DDRDATA6CH0_CR_RXTRAINRANK0_RxRcvEnPi_WID ( 9) + #define DDRDATA6CH0_CR_RXTRAINRANK0_RxRcvEnPi_MSK (0x000001FF) + #define DDRDATA6CH0_CR_RXTRAINRANK0_RxRcvEnPi_MAX (0x000001FF) + #define DDRDATA6CH0_CR_RXTRAINRANK0_RxDqsPPi_OFF ( 9) + #define DDRDATA6CH0_CR_RXTRAINRANK0_RxDqsPPi_WID ( 6) + #define DDRDATA6CH0_CR_RXTRAINRANK0_RxDqsPPi_MSK (0x00007E00) + #define DDRDATA6CH0_CR_RXTRAINRANK0_RxDqsPPi_MAX (0x0000003F) + #define DDRDATA6CH0_CR_RXTRAINRANK0_RxEq_OFF (15) + #define DDRDATA6CH0_CR_RXTRAINRANK0_RxEq_WID ( 5) + #define DDRDATA6CH0_CR_RXTRAINRANK0_RxEq_MSK (0x000F8000) + #define DDRDATA6CH0_CR_RXTRAINRANK0_RxEq_MAX (0x0000001F) + #define DDRDATA6CH0_CR_RXTRAINRANK0_RxDqsNPi_OFF (20) + #define DDRDATA6CH0_CR_RXTRAINRANK0_RxDqsNPi_WID ( 6) + #define DDRDATA6CH0_CR_RXTRAINRANK0_RxDqsNPi_MSK (0x03F00000) + #define DDRDATA6CH0_CR_RXTRAINRANK0_RxDqsNPi_MAX (0x0000003F) + #define DDRDATA6CH0_CR_RXTRAINRANK0_RxVref_OFF (26) + #define DDRDATA6CH0_CR_RXTRAINRANK0_RxVref_WID ( 6) + #define DDRDATA6CH0_CR_RXTRAINRANK0_RxVref_MSK (0xFC000000) + #define DDRDATA6CH0_CR_RXTRAINRANK0_RxVref_MAX (0x0000003F) + +#define DDRDATA6CH0_CR_RXTRAINRANK1_REG (0x00000C04) + #define DDRDATA6CH0_CR_RXTRAINRANK1_RxRcvEnPi_OFF ( 0) + #define DDRDATA6CH0_CR_RXTRAINRANK1_RxRcvEnPi_WID ( 9) + #define DDRDATA6CH0_CR_RXTRAINRANK1_RxRcvEnPi_MSK (0x000001FF) + #define DDRDATA6CH0_CR_RXTRAINRANK1_RxRcvEnPi_MAX (0x000001FF) + #define DDRDATA6CH0_CR_RXTRAINRANK1_RxDqsPPi_OFF ( 9) + #define DDRDATA6CH0_CR_RXTRAINRANK1_RxDqsPPi_WID ( 6) + #define DDRDATA6CH0_CR_RXTRAINRANK1_RxDqsPPi_MSK (0x00007E00) + #define DDRDATA6CH0_CR_RXTRAINRANK1_RxDqsPPi_MAX (0x0000003F) + #define DDRDATA6CH0_CR_RXTRAINRANK1_RxEq_OFF (15) + #define DDRDATA6CH0_CR_RXTRAINRANK1_RxEq_WID ( 5) + #define DDRDATA6CH0_CR_RXTRAINRANK1_RxEq_MSK (0x000F8000) + #define DDRDATA6CH0_CR_RXTRAINRANK1_RxEq_MAX (0x0000001F) + #define DDRDATA6CH0_CR_RXTRAINRANK1_RxDqsNPi_OFF (20) + #define DDRDATA6CH0_CR_RXTRAINRANK1_RxDqsNPi_WID ( 6) + #define DDRDATA6CH0_CR_RXTRAINRANK1_RxDqsNPi_MSK (0x03F00000) + #define DDRDATA6CH0_CR_RXTRAINRANK1_RxDqsNPi_MAX (0x0000003F) + #define DDRDATA6CH0_CR_RXTRAINRANK1_RxVref_OFF (26) + #define DDRDATA6CH0_CR_RXTRAINRANK1_RxVref_WID ( 6) + #define DDRDATA6CH0_CR_RXTRAINRANK1_RxVref_MSK (0xFC000000) + #define DDRDATA6CH0_CR_RXTRAINRANK1_RxVref_MAX (0x0000003F) + +#define DDRDATA6CH0_CR_RXTRAINRANK2_REG (0x00000C08) + #define DDRDATA6CH0_CR_RXTRAINRANK2_RxRcvEnPi_OFF ( 0) + #define DDRDATA6CH0_CR_RXTRAINRANK2_RxRcvEnPi_WID ( 9) + #define DDRDATA6CH0_CR_RXTRAINRANK2_RxRcvEnPi_MSK (0x000001FF) + #define DDRDATA6CH0_CR_RXTRAINRANK2_RxRcvEnPi_MAX (0x000001FF) + #define DDRDATA6CH0_CR_RXTRAINRANK2_RxDqsPPi_OFF ( 9) + #define DDRDATA6CH0_CR_RXTRAINRANK2_RxDqsPPi_WID ( 6) + #define DDRDATA6CH0_CR_RXTRAINRANK2_RxDqsPPi_MSK (0x00007E00) + #define DDRDATA6CH0_CR_RXTRAINRANK2_RxDqsPPi_MAX (0x0000003F) + #define DDRDATA6CH0_CR_RXTRAINRANK2_RxEq_OFF (15) + #define DDRDATA6CH0_CR_RXTRAINRANK2_RxEq_WID ( 5) + #define DDRDATA6CH0_CR_RXTRAINRANK2_RxEq_MSK (0x000F8000) + #define DDRDATA6CH0_CR_RXTRAINRANK2_RxEq_MAX (0x0000001F) + #define DDRDATA6CH0_CR_RXTRAINRANK2_RxDqsNPi_OFF (20) + #define DDRDATA6CH0_CR_RXTRAINRANK2_RxDqsNPi_WID ( 6) + #define DDRDATA6CH0_CR_RXTRAINRANK2_RxDqsNPi_MSK (0x03F00000) + #define DDRDATA6CH0_CR_RXTRAINRANK2_RxDqsNPi_MAX (0x0000003F) + #define DDRDATA6CH0_CR_RXTRAINRANK2_RxVref_OFF (26) + #define DDRDATA6CH0_CR_RXTRAINRANK2_RxVref_WID ( 6) + #define DDRDATA6CH0_CR_RXTRAINRANK2_RxVref_MSK (0xFC000000) + #define DDRDATA6CH0_CR_RXTRAINRANK2_RxVref_MAX (0x0000003F) + +#define DDRDATA6CH0_CR_RXTRAINRANK3_REG (0x00000C0C) + #define DDRDATA6CH0_CR_RXTRAINRANK3_RxRcvEnPi_OFF ( 0) + #define DDRDATA6CH0_CR_RXTRAINRANK3_RxRcvEnPi_WID ( 9) + #define DDRDATA6CH0_CR_RXTRAINRANK3_RxRcvEnPi_MSK (0x000001FF) + #define DDRDATA6CH0_CR_RXTRAINRANK3_RxRcvEnPi_MAX (0x000001FF) + #define DDRDATA6CH0_CR_RXTRAINRANK3_RxDqsPPi_OFF ( 9) + #define DDRDATA6CH0_CR_RXTRAINRANK3_RxDqsPPi_WID ( 6) + #define DDRDATA6CH0_CR_RXTRAINRANK3_RxDqsPPi_MSK (0x00007E00) + #define DDRDATA6CH0_CR_RXTRAINRANK3_RxDqsPPi_MAX (0x0000003F) + #define DDRDATA6CH0_CR_RXTRAINRANK3_RxEq_OFF (15) + #define DDRDATA6CH0_CR_RXTRAINRANK3_RxEq_WID ( 5) + #define DDRDATA6CH0_CR_RXTRAINRANK3_RxEq_MSK (0x000F8000) + #define DDRDATA6CH0_CR_RXTRAINRANK3_RxEq_MAX (0x0000001F) + #define DDRDATA6CH0_CR_RXTRAINRANK3_RxDqsNPi_OFF (20) + #define DDRDATA6CH0_CR_RXTRAINRANK3_RxDqsNPi_WID ( 6) + #define DDRDATA6CH0_CR_RXTRAINRANK3_RxDqsNPi_MSK (0x03F00000) + #define DDRDATA6CH0_CR_RXTRAINRANK3_RxDqsNPi_MAX (0x0000003F) + #define DDRDATA6CH0_CR_RXTRAINRANK3_RxVref_OFF (26) + #define DDRDATA6CH0_CR_RXTRAINRANK3_RxVref_WID ( 6) + #define DDRDATA6CH0_CR_RXTRAINRANK3_RxVref_MSK (0xFC000000) + #define DDRDATA6CH0_CR_RXTRAINRANK3_RxVref_MAX (0x0000003F) + +#define DDRDATA6CH0_CR_RXPERBITRANK0_REG (0x00000C10) + #define DDRDATA6CH0_CR_RXPERBITRANK0_Lane0_OFF ( 0) + #define DDRDATA6CH0_CR_RXPERBITRANK0_Lane0_WID ( 4) + #define DDRDATA6CH0_CR_RXPERBITRANK0_Lane0_MSK (0x0000000F) + #define DDRDATA6CH0_CR_RXPERBITRANK0_Lane0_MAX (0x0000000F) + #define DDRDATA6CH0_CR_RXPERBITRANK0_Lane1_OFF ( 4) + #define DDRDATA6CH0_CR_RXPERBITRANK0_Lane1_WID ( 4) + #define DDRDATA6CH0_CR_RXPERBITRANK0_Lane1_MSK (0x000000F0) + #define DDRDATA6CH0_CR_RXPERBITRANK0_Lane1_MAX (0x0000000F) + #define DDRDATA6CH0_CR_RXPERBITRANK0_Lane2_OFF ( 8) + #define DDRDATA6CH0_CR_RXPERBITRANK0_Lane2_WID ( 4) + #define DDRDATA6CH0_CR_RXPERBITRANK0_Lane2_MSK (0x00000F00) + #define DDRDATA6CH0_CR_RXPERBITRANK0_Lane2_MAX (0x0000000F) + #define DDRDATA6CH0_CR_RXPERBITRANK0_Lane3_OFF (12) + #define DDRDATA6CH0_CR_RXPERBITRANK0_Lane3_WID ( 4) + #define DDRDATA6CH0_CR_RXPERBITRANK0_Lane3_MSK (0x0000F000) + #define DDRDATA6CH0_CR_RXPERBITRANK0_Lane3_MAX (0x0000000F) + #define DDRDATA6CH0_CR_RXPERBITRANK0_Lane4_OFF (16) + #define DDRDATA6CH0_CR_RXPERBITRANK0_Lane4_WID ( 4) + #define DDRDATA6CH0_CR_RXPERBITRANK0_Lane4_MSK (0x000F0000) + #define DDRDATA6CH0_CR_RXPERBITRANK0_Lane4_MAX (0x0000000F) + #define DDRDATA6CH0_CR_RXPERBITRANK0_Lane5_OFF (20) + #define DDRDATA6CH0_CR_RXPERBITRANK0_Lane5_WID ( 4) + #define DDRDATA6CH0_CR_RXPERBITRANK0_Lane5_MSK (0x00F00000) + #define DDRDATA6CH0_CR_RXPERBITRANK0_Lane5_MAX (0x0000000F) + #define DDRDATA6CH0_CR_RXPERBITRANK0_Lane6_OFF (24) + #define DDRDATA6CH0_CR_RXPERBITRANK0_Lane6_WID ( 4) + #define DDRDATA6CH0_CR_RXPERBITRANK0_Lane6_MSK (0x0F000000) + #define DDRDATA6CH0_CR_RXPERBITRANK0_Lane6_MAX (0x0000000F) + #define DDRDATA6CH0_CR_RXPERBITRANK0_Lane7_OFF (28) + #define DDRDATA6CH0_CR_RXPERBITRANK0_Lane7_WID ( 4) + #define DDRDATA6CH0_CR_RXPERBITRANK0_Lane7_MSK (0xF0000000) + #define DDRDATA6CH0_CR_RXPERBITRANK0_Lane7_MAX (0x0000000F) + +#define DDRDATA6CH0_CR_RXPERBITRANK1_REG (0x00000C14) + #define DDRDATA6CH0_CR_RXPERBITRANK1_Lane0_OFF ( 0) + #define DDRDATA6CH0_CR_RXPERBITRANK1_Lane0_WID ( 4) + #define DDRDATA6CH0_CR_RXPERBITRANK1_Lane0_MSK (0x0000000F) + #define DDRDATA6CH0_CR_RXPERBITRANK1_Lane0_MAX (0x0000000F) + #define DDRDATA6CH0_CR_RXPERBITRANK1_Lane1_OFF ( 4) + #define DDRDATA6CH0_CR_RXPERBITRANK1_Lane1_WID ( 4) + #define DDRDATA6CH0_CR_RXPERBITRANK1_Lane1_MSK (0x000000F0) + #define DDRDATA6CH0_CR_RXPERBITRANK1_Lane1_MAX (0x0000000F) + #define DDRDATA6CH0_CR_RXPERBITRANK1_Lane2_OFF ( 8) + #define DDRDATA6CH0_CR_RXPERBITRANK1_Lane2_WID ( 4) + #define DDRDATA6CH0_CR_RXPERBITRANK1_Lane2_MSK (0x00000F00) + #define DDRDATA6CH0_CR_RXPERBITRANK1_Lane2_MAX (0x0000000F) + #define DDRDATA6CH0_CR_RXPERBITRANK1_Lane3_OFF (12) + #define DDRDATA6CH0_CR_RXPERBITRANK1_Lane3_WID ( 4) + #define DDRDATA6CH0_CR_RXPERBITRANK1_Lane3_MSK (0x0000F000) + #define DDRDATA6CH0_CR_RXPERBITRANK1_Lane3_MAX (0x0000000F) + #define DDRDATA6CH0_CR_RXPERBITRANK1_Lane4_OFF (16) + #define DDRDATA6CH0_CR_RXPERBITRANK1_Lane4_WID ( 4) + #define DDRDATA6CH0_CR_RXPERBITRANK1_Lane4_MSK (0x000F0000) + #define DDRDATA6CH0_CR_RXPERBITRANK1_Lane4_MAX (0x0000000F) + #define DDRDATA6CH0_CR_RXPERBITRANK1_Lane5_OFF (20) + #define DDRDATA6CH0_CR_RXPERBITRANK1_Lane5_WID ( 4) + #define DDRDATA6CH0_CR_RXPERBITRANK1_Lane5_MSK (0x00F00000) + #define DDRDATA6CH0_CR_RXPERBITRANK1_Lane5_MAX (0x0000000F) + #define DDRDATA6CH0_CR_RXPERBITRANK1_Lane6_OFF (24) + #define DDRDATA6CH0_CR_RXPERBITRANK1_Lane6_WID ( 4) + #define DDRDATA6CH0_CR_RXPERBITRANK1_Lane6_MSK (0x0F000000) + #define DDRDATA6CH0_CR_RXPERBITRANK1_Lane6_MAX (0x0000000F) + #define DDRDATA6CH0_CR_RXPERBITRANK1_Lane7_OFF (28) + #define DDRDATA6CH0_CR_RXPERBITRANK1_Lane7_WID ( 4) + #define DDRDATA6CH0_CR_RXPERBITRANK1_Lane7_MSK (0xF0000000) + #define DDRDATA6CH0_CR_RXPERBITRANK1_Lane7_MAX (0x0000000F) + +#define DDRDATA6CH0_CR_RXPERBITRANK2_REG (0x00000C18) + #define DDRDATA6CH0_CR_RXPERBITRANK2_Lane0_OFF ( 0) + #define DDRDATA6CH0_CR_RXPERBITRANK2_Lane0_WID ( 4) + #define DDRDATA6CH0_CR_RXPERBITRANK2_Lane0_MSK (0x0000000F) + #define DDRDATA6CH0_CR_RXPERBITRANK2_Lane0_MAX (0x0000000F) + #define DDRDATA6CH0_CR_RXPERBITRANK2_Lane1_OFF ( 4) + #define DDRDATA6CH0_CR_RXPERBITRANK2_Lane1_WID ( 4) + #define DDRDATA6CH0_CR_RXPERBITRANK2_Lane1_MSK (0x000000F0) + #define DDRDATA6CH0_CR_RXPERBITRANK2_Lane1_MAX (0x0000000F) + #define DDRDATA6CH0_CR_RXPERBITRANK2_Lane2_OFF ( 8) + #define DDRDATA6CH0_CR_RXPERBITRANK2_Lane2_WID ( 4) + #define DDRDATA6CH0_CR_RXPERBITRANK2_Lane2_MSK (0x00000F00) + #define DDRDATA6CH0_CR_RXPERBITRANK2_Lane2_MAX (0x0000000F) + #define DDRDATA6CH0_CR_RXPERBITRANK2_Lane3_OFF (12) + #define DDRDATA6CH0_CR_RXPERBITRANK2_Lane3_WID ( 4) + #define DDRDATA6CH0_CR_RXPERBITRANK2_Lane3_MSK (0x0000F000) + #define DDRDATA6CH0_CR_RXPERBITRANK2_Lane3_MAX (0x0000000F) + #define DDRDATA6CH0_CR_RXPERBITRANK2_Lane4_OFF (16) + #define DDRDATA6CH0_CR_RXPERBITRANK2_Lane4_WID ( 4) + #define DDRDATA6CH0_CR_RXPERBITRANK2_Lane4_MSK (0x000F0000) + #define DDRDATA6CH0_CR_RXPERBITRANK2_Lane4_MAX (0x0000000F) + #define DDRDATA6CH0_CR_RXPERBITRANK2_Lane5_OFF (20) + #define DDRDATA6CH0_CR_RXPERBITRANK2_Lane5_WID ( 4) + #define DDRDATA6CH0_CR_RXPERBITRANK2_Lane5_MSK (0x00F00000) + #define DDRDATA6CH0_CR_RXPERBITRANK2_Lane5_MAX (0x0000000F) + #define DDRDATA6CH0_CR_RXPERBITRANK2_Lane6_OFF (24) + #define DDRDATA6CH0_CR_RXPERBITRANK2_Lane6_WID ( 4) + #define DDRDATA6CH0_CR_RXPERBITRANK2_Lane6_MSK (0x0F000000) + #define DDRDATA6CH0_CR_RXPERBITRANK2_Lane6_MAX (0x0000000F) + #define DDRDATA6CH0_CR_RXPERBITRANK2_Lane7_OFF (28) + #define DDRDATA6CH0_CR_RXPERBITRANK2_Lane7_WID ( 4) + #define DDRDATA6CH0_CR_RXPERBITRANK2_Lane7_MSK (0xF0000000) + #define DDRDATA6CH0_CR_RXPERBITRANK2_Lane7_MAX (0x0000000F) + +#define DDRDATA6CH0_CR_RXPERBITRANK3_REG (0x00000C1C) + #define DDRDATA6CH0_CR_RXPERBITRANK3_Lane0_OFF ( 0) + #define DDRDATA6CH0_CR_RXPERBITRANK3_Lane0_WID ( 4) + #define DDRDATA6CH0_CR_RXPERBITRANK3_Lane0_MSK (0x0000000F) + #define DDRDATA6CH0_CR_RXPERBITRANK3_Lane0_MAX (0x0000000F) + #define DDRDATA6CH0_CR_RXPERBITRANK3_Lane1_OFF ( 4) + #define DDRDATA6CH0_CR_RXPERBITRANK3_Lane1_WID ( 4) + #define DDRDATA6CH0_CR_RXPERBITRANK3_Lane1_MSK (0x000000F0) + #define DDRDATA6CH0_CR_RXPERBITRANK3_Lane1_MAX (0x0000000F) + #define DDRDATA6CH0_CR_RXPERBITRANK3_Lane2_OFF ( 8) + #define DDRDATA6CH0_CR_RXPERBITRANK3_Lane2_WID ( 4) + #define DDRDATA6CH0_CR_RXPERBITRANK3_Lane2_MSK (0x00000F00) + #define DDRDATA6CH0_CR_RXPERBITRANK3_Lane2_MAX (0x0000000F) + #define DDRDATA6CH0_CR_RXPERBITRANK3_Lane3_OFF (12) + #define DDRDATA6CH0_CR_RXPERBITRANK3_Lane3_WID ( 4) + #define DDRDATA6CH0_CR_RXPERBITRANK3_Lane3_MSK (0x0000F000) + #define DDRDATA6CH0_CR_RXPERBITRANK3_Lane3_MAX (0x0000000F) + #define DDRDATA6CH0_CR_RXPERBITRANK3_Lane4_OFF (16) + #define DDRDATA6CH0_CR_RXPERBITRANK3_Lane4_WID ( 4) + #define DDRDATA6CH0_CR_RXPERBITRANK3_Lane4_MSK (0x000F0000) + #define DDRDATA6CH0_CR_RXPERBITRANK3_Lane4_MAX (0x0000000F) + #define DDRDATA6CH0_CR_RXPERBITRANK3_Lane5_OFF (20) + #define DDRDATA6CH0_CR_RXPERBITRANK3_Lane5_WID ( 4) + #define DDRDATA6CH0_CR_RXPERBITRANK3_Lane5_MSK (0x00F00000) + #define DDRDATA6CH0_CR_RXPERBITRANK3_Lane5_MAX (0x0000000F) + #define DDRDATA6CH0_CR_RXPERBITRANK3_Lane6_OFF (24) + #define DDRDATA6CH0_CR_RXPERBITRANK3_Lane6_WID ( 4) + #define DDRDATA6CH0_CR_RXPERBITRANK3_Lane6_MSK (0x0F000000) + #define DDRDATA6CH0_CR_RXPERBITRANK3_Lane6_MAX (0x0000000F) + #define DDRDATA6CH0_CR_RXPERBITRANK3_Lane7_OFF (28) + #define DDRDATA6CH0_CR_RXPERBITRANK3_Lane7_WID ( 4) + #define DDRDATA6CH0_CR_RXPERBITRANK3_Lane7_MSK (0xF0000000) + #define DDRDATA6CH0_CR_RXPERBITRANK3_Lane7_MAX (0x0000000F) + +#define DDRDATA6CH0_CR_TXTRAINRANK0_REG (0x00000C20) + #define DDRDATA6CH0_CR_TXTRAINRANK0_TxDqDelay_OFF ( 0) + #define DDRDATA6CH0_CR_TXTRAINRANK0_TxDqDelay_WID ( 9) + #define DDRDATA6CH0_CR_TXTRAINRANK0_TxDqDelay_MSK (0x000001FF) + #define DDRDATA6CH0_CR_TXTRAINRANK0_TxDqDelay_MAX (0x000001FF) + #define DDRDATA6CH0_CR_TXTRAINRANK0_TxDqsDelay_OFF ( 9) + #define DDRDATA6CH0_CR_TXTRAINRANK0_TxDqsDelay_WID ( 9) + #define DDRDATA6CH0_CR_TXTRAINRANK0_TxDqsDelay_MSK (0x0003FE00) + #define DDRDATA6CH0_CR_TXTRAINRANK0_TxDqsDelay_MAX (0x000001FF) + #define DDRDATA6CH0_CR_TXTRAINRANK0_Spare0_OFF (18) + #define DDRDATA6CH0_CR_TXTRAINRANK0_Spare0_WID ( 2) + #define DDRDATA6CH0_CR_TXTRAINRANK0_Spare0_MSK (0x000C0000) + #define DDRDATA6CH0_CR_TXTRAINRANK0_Spare0_MAX (0x00000003) + #define DDRDATA6CH0_CR_TXTRAINRANK0_TxEqualization_OFF (20) + #define DDRDATA6CH0_CR_TXTRAINRANK0_TxEqualization_WID ( 6) + #define DDRDATA6CH0_CR_TXTRAINRANK0_TxEqualization_MSK (0x03F00000) + #define DDRDATA6CH0_CR_TXTRAINRANK0_TxEqualization_MAX (0x0000003F) + #define DDRDATA6CH0_CR_TXTRAINRANK0_Spare1_OFF (26) + #define DDRDATA6CH0_CR_TXTRAINRANK0_Spare1_WID ( 6) + #define DDRDATA6CH0_CR_TXTRAINRANK0_Spare1_MSK (0xFC000000) + #define DDRDATA6CH0_CR_TXTRAINRANK0_Spare1_MAX (0x0000003F) + +#define DDRDATA6CH0_CR_TXTRAINRANK1_REG (0x00000C24) + #define DDRDATA6CH0_CR_TXTRAINRANK1_TxDqDelay_OFF ( 0) + #define DDRDATA6CH0_CR_TXTRAINRANK1_TxDqDelay_WID ( 9) + #define DDRDATA6CH0_CR_TXTRAINRANK1_TxDqDelay_MSK (0x000001FF) + #define DDRDATA6CH0_CR_TXTRAINRANK1_TxDqDelay_MAX (0x000001FF) + #define DDRDATA6CH0_CR_TXTRAINRANK1_TxDqsDelay_OFF ( 9) + #define DDRDATA6CH0_CR_TXTRAINRANK1_TxDqsDelay_WID ( 9) + #define DDRDATA6CH0_CR_TXTRAINRANK1_TxDqsDelay_MSK (0x0003FE00) + #define DDRDATA6CH0_CR_TXTRAINRANK1_TxDqsDelay_MAX (0x000001FF) + #define DDRDATA6CH0_CR_TXTRAINRANK1_Spare0_OFF (18) + #define DDRDATA6CH0_CR_TXTRAINRANK1_Spare0_WID ( 2) + #define DDRDATA6CH0_CR_TXTRAINRANK1_Spare0_MSK (0x000C0000) + #define DDRDATA6CH0_CR_TXTRAINRANK1_Spare0_MAX (0x00000003) + #define DDRDATA6CH0_CR_TXTRAINRANK1_TxEqualization_OFF (20) + #define DDRDATA6CH0_CR_TXTRAINRANK1_TxEqualization_WID ( 6) + #define DDRDATA6CH0_CR_TXTRAINRANK1_TxEqualization_MSK (0x03F00000) + #define DDRDATA6CH0_CR_TXTRAINRANK1_TxEqualization_MAX (0x0000003F) + #define DDRDATA6CH0_CR_TXTRAINRANK1_Spare1_OFF (26) + #define DDRDATA6CH0_CR_TXTRAINRANK1_Spare1_WID ( 6) + #define DDRDATA6CH0_CR_TXTRAINRANK1_Spare1_MSK (0xFC000000) + #define DDRDATA6CH0_CR_TXTRAINRANK1_Spare1_MAX (0x0000003F) + +#define DDRDATA6CH0_CR_TXTRAINRANK2_REG (0x00000C28) + #define DDRDATA6CH0_CR_TXTRAINRANK2_TxDqDelay_OFF ( 0) + #define DDRDATA6CH0_CR_TXTRAINRANK2_TxDqDelay_WID ( 9) + #define DDRDATA6CH0_CR_TXTRAINRANK2_TxDqDelay_MSK (0x000001FF) + #define DDRDATA6CH0_CR_TXTRAINRANK2_TxDqDelay_MAX (0x000001FF) + #define DDRDATA6CH0_CR_TXTRAINRANK2_TxDqsDelay_OFF ( 9) + #define DDRDATA6CH0_CR_TXTRAINRANK2_TxDqsDelay_WID ( 9) + #define DDRDATA6CH0_CR_TXTRAINRANK2_TxDqsDelay_MSK (0x0003FE00) + #define DDRDATA6CH0_CR_TXTRAINRANK2_TxDqsDelay_MAX (0x000001FF) + #define DDRDATA6CH0_CR_TXTRAINRANK2_Spare0_OFF (18) + #define DDRDATA6CH0_CR_TXTRAINRANK2_Spare0_WID ( 2) + #define DDRDATA6CH0_CR_TXTRAINRANK2_Spare0_MSK (0x000C0000) + #define DDRDATA6CH0_CR_TXTRAINRANK2_Spare0_MAX (0x00000003) + #define DDRDATA6CH0_CR_TXTRAINRANK2_TxEqualization_OFF (20) + #define DDRDATA6CH0_CR_TXTRAINRANK2_TxEqualization_WID ( 6) + #define DDRDATA6CH0_CR_TXTRAINRANK2_TxEqualization_MSK (0x03F00000) + #define DDRDATA6CH0_CR_TXTRAINRANK2_TxEqualization_MAX (0x0000003F) + #define DDRDATA6CH0_CR_TXTRAINRANK2_Spare1_OFF (26) + #define DDRDATA6CH0_CR_TXTRAINRANK2_Spare1_WID ( 6) + #define DDRDATA6CH0_CR_TXTRAINRANK2_Spare1_MSK (0xFC000000) + #define DDRDATA6CH0_CR_TXTRAINRANK2_Spare1_MAX (0x0000003F) + +#define DDRDATA6CH0_CR_TXTRAINRANK3_REG (0x00000C2C) + #define DDRDATA6CH0_CR_TXTRAINRANK3_TxDqDelay_OFF ( 0) + #define DDRDATA6CH0_CR_TXTRAINRANK3_TxDqDelay_WID ( 9) + #define DDRDATA6CH0_CR_TXTRAINRANK3_TxDqDelay_MSK (0x000001FF) + #define DDRDATA6CH0_CR_TXTRAINRANK3_TxDqDelay_MAX (0x000001FF) + #define DDRDATA6CH0_CR_TXTRAINRANK3_TxDqsDelay_OFF ( 9) + #define DDRDATA6CH0_CR_TXTRAINRANK3_TxDqsDelay_WID ( 9) + #define DDRDATA6CH0_CR_TXTRAINRANK3_TxDqsDelay_MSK (0x0003FE00) + #define DDRDATA6CH0_CR_TXTRAINRANK3_TxDqsDelay_MAX (0x000001FF) + #define DDRDATA6CH0_CR_TXTRAINRANK3_Spare0_OFF (18) + #define DDRDATA6CH0_CR_TXTRAINRANK3_Spare0_WID ( 2) + #define DDRDATA6CH0_CR_TXTRAINRANK3_Spare0_MSK (0x000C0000) + #define DDRDATA6CH0_CR_TXTRAINRANK3_Spare0_MAX (0x00000003) + #define DDRDATA6CH0_CR_TXTRAINRANK3_TxEqualization_OFF (20) + #define DDRDATA6CH0_CR_TXTRAINRANK3_TxEqualization_WID ( 6) + #define DDRDATA6CH0_CR_TXTRAINRANK3_TxEqualization_MSK (0x03F00000) + #define DDRDATA6CH0_CR_TXTRAINRANK3_TxEqualization_MAX (0x0000003F) + #define DDRDATA6CH0_CR_TXTRAINRANK3_Spare1_OFF (26) + #define DDRDATA6CH0_CR_TXTRAINRANK3_Spare1_WID ( 6) + #define DDRDATA6CH0_CR_TXTRAINRANK3_Spare1_MSK (0xFC000000) + #define DDRDATA6CH0_CR_TXTRAINRANK3_Spare1_MAX (0x0000003F) + +#define DDRDATA6CH0_CR_TXPERBITRANK0_REG (0x00000C30) + #define DDRDATA6CH0_CR_TXPERBITRANK0_Lane0_OFF ( 0) + #define DDRDATA6CH0_CR_TXPERBITRANK0_Lane0_WID ( 4) + #define DDRDATA6CH0_CR_TXPERBITRANK0_Lane0_MSK (0x0000000F) + #define DDRDATA6CH0_CR_TXPERBITRANK0_Lane0_MAX (0x0000000F) + #define DDRDATA6CH0_CR_TXPERBITRANK0_Lane1_OFF ( 4) + #define DDRDATA6CH0_CR_TXPERBITRANK0_Lane1_WID ( 4) + #define DDRDATA6CH0_CR_TXPERBITRANK0_Lane1_MSK (0x000000F0) + #define DDRDATA6CH0_CR_TXPERBITRANK0_Lane1_MAX (0x0000000F) + #define DDRDATA6CH0_CR_TXPERBITRANK0_Lane2_OFF ( 8) + #define DDRDATA6CH0_CR_TXPERBITRANK0_Lane2_WID ( 4) + #define DDRDATA6CH0_CR_TXPERBITRANK0_Lane2_MSK (0x00000F00) + #define DDRDATA6CH0_CR_TXPERBITRANK0_Lane2_MAX (0x0000000F) + #define DDRDATA6CH0_CR_TXPERBITRANK0_Lane3_OFF (12) + #define DDRDATA6CH0_CR_TXPERBITRANK0_Lane3_WID ( 4) + #define DDRDATA6CH0_CR_TXPERBITRANK0_Lane3_MSK (0x0000F000) + #define DDRDATA6CH0_CR_TXPERBITRANK0_Lane3_MAX (0x0000000F) + #define DDRDATA6CH0_CR_TXPERBITRANK0_Lane4_OFF (16) + #define DDRDATA6CH0_CR_TXPERBITRANK0_Lane4_WID ( 4) + #define DDRDATA6CH0_CR_TXPERBITRANK0_Lane4_MSK (0x000F0000) + #define DDRDATA6CH0_CR_TXPERBITRANK0_Lane4_MAX (0x0000000F) + #define DDRDATA6CH0_CR_TXPERBITRANK0_Lane5_OFF (20) + #define DDRDATA6CH0_CR_TXPERBITRANK0_Lane5_WID ( 4) + #define DDRDATA6CH0_CR_TXPERBITRANK0_Lane5_MSK (0x00F00000) + #define DDRDATA6CH0_CR_TXPERBITRANK0_Lane5_MAX (0x0000000F) + #define DDRDATA6CH0_CR_TXPERBITRANK0_Lane6_OFF (24) + #define DDRDATA6CH0_CR_TXPERBITRANK0_Lane6_WID ( 4) + #define DDRDATA6CH0_CR_TXPERBITRANK0_Lane6_MSK (0x0F000000) + #define DDRDATA6CH0_CR_TXPERBITRANK0_Lane6_MAX (0x0000000F) + #define DDRDATA6CH0_CR_TXPERBITRANK0_Lane7_OFF (28) + #define DDRDATA6CH0_CR_TXPERBITRANK0_Lane7_WID ( 4) + #define DDRDATA6CH0_CR_TXPERBITRANK0_Lane7_MSK (0xF0000000) + #define DDRDATA6CH0_CR_TXPERBITRANK0_Lane7_MAX (0x0000000F) + +#define DDRDATA6CH0_CR_TXPERBITRANK1_REG (0x00000C34) + #define DDRDATA6CH0_CR_TXPERBITRANK1_Lane0_OFF ( 0) + #define DDRDATA6CH0_CR_TXPERBITRANK1_Lane0_WID ( 4) + #define DDRDATA6CH0_CR_TXPERBITRANK1_Lane0_MSK (0x0000000F) + #define DDRDATA6CH0_CR_TXPERBITRANK1_Lane0_MAX (0x0000000F) + #define DDRDATA6CH0_CR_TXPERBITRANK1_Lane1_OFF ( 4) + #define DDRDATA6CH0_CR_TXPERBITRANK1_Lane1_WID ( 4) + #define DDRDATA6CH0_CR_TXPERBITRANK1_Lane1_MSK (0x000000F0) + #define DDRDATA6CH0_CR_TXPERBITRANK1_Lane1_MAX (0x0000000F) + #define DDRDATA6CH0_CR_TXPERBITRANK1_Lane2_OFF ( 8) + #define DDRDATA6CH0_CR_TXPERBITRANK1_Lane2_WID ( 4) + #define DDRDATA6CH0_CR_TXPERBITRANK1_Lane2_MSK (0x00000F00) + #define DDRDATA6CH0_CR_TXPERBITRANK1_Lane2_MAX (0x0000000F) + #define DDRDATA6CH0_CR_TXPERBITRANK1_Lane3_OFF (12) + #define DDRDATA6CH0_CR_TXPERBITRANK1_Lane3_WID ( 4) + #define DDRDATA6CH0_CR_TXPERBITRANK1_Lane3_MSK (0x0000F000) + #define DDRDATA6CH0_CR_TXPERBITRANK1_Lane3_MAX (0x0000000F) + #define DDRDATA6CH0_CR_TXPERBITRANK1_Lane4_OFF (16) + #define DDRDATA6CH0_CR_TXPERBITRANK1_Lane4_WID ( 4) + #define DDRDATA6CH0_CR_TXPERBITRANK1_Lane4_MSK (0x000F0000) + #define DDRDATA6CH0_CR_TXPERBITRANK1_Lane4_MAX (0x0000000F) + #define DDRDATA6CH0_CR_TXPERBITRANK1_Lane5_OFF (20) + #define DDRDATA6CH0_CR_TXPERBITRANK1_Lane5_WID ( 4) + #define DDRDATA6CH0_CR_TXPERBITRANK1_Lane5_MSK (0x00F00000) + #define DDRDATA6CH0_CR_TXPERBITRANK1_Lane5_MAX (0x0000000F) + #define DDRDATA6CH0_CR_TXPERBITRANK1_Lane6_OFF (24) + #define DDRDATA6CH0_CR_TXPERBITRANK1_Lane6_WID ( 4) + #define DDRDATA6CH0_CR_TXPERBITRANK1_Lane6_MSK (0x0F000000) + #define DDRDATA6CH0_CR_TXPERBITRANK1_Lane6_MAX (0x0000000F) + #define DDRDATA6CH0_CR_TXPERBITRANK1_Lane7_OFF (28) + #define DDRDATA6CH0_CR_TXPERBITRANK1_Lane7_WID ( 4) + #define DDRDATA6CH0_CR_TXPERBITRANK1_Lane7_MSK (0xF0000000) + #define DDRDATA6CH0_CR_TXPERBITRANK1_Lane7_MAX (0x0000000F) + +#define DDRDATA6CH0_CR_TXPERBITRANK2_REG (0x00000C38) + #define DDRDATA6CH0_CR_TXPERBITRANK2_Lane0_OFF ( 0) + #define DDRDATA6CH0_CR_TXPERBITRANK2_Lane0_WID ( 4) + #define DDRDATA6CH0_CR_TXPERBITRANK2_Lane0_MSK (0x0000000F) + #define DDRDATA6CH0_CR_TXPERBITRANK2_Lane0_MAX (0x0000000F) + #define DDRDATA6CH0_CR_TXPERBITRANK2_Lane1_OFF ( 4) + #define DDRDATA6CH0_CR_TXPERBITRANK2_Lane1_WID ( 4) + #define DDRDATA6CH0_CR_TXPERBITRANK2_Lane1_MSK (0x000000F0) + #define DDRDATA6CH0_CR_TXPERBITRANK2_Lane1_MAX (0x0000000F) + #define DDRDATA6CH0_CR_TXPERBITRANK2_Lane2_OFF ( 8) + #define DDRDATA6CH0_CR_TXPERBITRANK2_Lane2_WID ( 4) + #define DDRDATA6CH0_CR_TXPERBITRANK2_Lane2_MSK (0x00000F00) + #define DDRDATA6CH0_CR_TXPERBITRANK2_Lane2_MAX (0x0000000F) + #define DDRDATA6CH0_CR_TXPERBITRANK2_Lane3_OFF (12) + #define DDRDATA6CH0_CR_TXPERBITRANK2_Lane3_WID ( 4) + #define DDRDATA6CH0_CR_TXPERBITRANK2_Lane3_MSK (0x0000F000) + #define DDRDATA6CH0_CR_TXPERBITRANK2_Lane3_MAX (0x0000000F) + #define DDRDATA6CH0_CR_TXPERBITRANK2_Lane4_OFF (16) + #define DDRDATA6CH0_CR_TXPERBITRANK2_Lane4_WID ( 4) + #define DDRDATA6CH0_CR_TXPERBITRANK2_Lane4_MSK (0x000F0000) + #define DDRDATA6CH0_CR_TXPERBITRANK2_Lane4_MAX (0x0000000F) + #define DDRDATA6CH0_CR_TXPERBITRANK2_Lane5_OFF (20) + #define DDRDATA6CH0_CR_TXPERBITRANK2_Lane5_WID ( 4) + #define DDRDATA6CH0_CR_TXPERBITRANK2_Lane5_MSK (0x00F00000) + #define DDRDATA6CH0_CR_TXPERBITRANK2_Lane5_MAX (0x0000000F) + #define DDRDATA6CH0_CR_TXPERBITRANK2_Lane6_OFF (24) + #define DDRDATA6CH0_CR_TXPERBITRANK2_Lane6_WID ( 4) + #define DDRDATA6CH0_CR_TXPERBITRANK2_Lane6_MSK (0x0F000000) + #define DDRDATA6CH0_CR_TXPERBITRANK2_Lane6_MAX (0x0000000F) + #define DDRDATA6CH0_CR_TXPERBITRANK2_Lane7_OFF (28) + #define DDRDATA6CH0_CR_TXPERBITRANK2_Lane7_WID ( 4) + #define DDRDATA6CH0_CR_TXPERBITRANK2_Lane7_MSK (0xF0000000) + #define DDRDATA6CH0_CR_TXPERBITRANK2_Lane7_MAX (0x0000000F) + +#define DDRDATA6CH0_CR_TXPERBITRANK3_REG (0x00000C3C) + #define DDRDATA6CH0_CR_TXPERBITRANK3_Lane0_OFF ( 0) + #define DDRDATA6CH0_CR_TXPERBITRANK3_Lane0_WID ( 4) + #define DDRDATA6CH0_CR_TXPERBITRANK3_Lane0_MSK (0x0000000F) + #define DDRDATA6CH0_CR_TXPERBITRANK3_Lane0_MAX (0x0000000F) + #define DDRDATA6CH0_CR_TXPERBITRANK3_Lane1_OFF ( 4) + #define DDRDATA6CH0_CR_TXPERBITRANK3_Lane1_WID ( 4) + #define DDRDATA6CH0_CR_TXPERBITRANK3_Lane1_MSK (0x000000F0) + #define DDRDATA6CH0_CR_TXPERBITRANK3_Lane1_MAX (0x0000000F) + #define DDRDATA6CH0_CR_TXPERBITRANK3_Lane2_OFF ( 8) + #define DDRDATA6CH0_CR_TXPERBITRANK3_Lane2_WID ( 4) + #define DDRDATA6CH0_CR_TXPERBITRANK3_Lane2_MSK (0x00000F00) + #define DDRDATA6CH0_CR_TXPERBITRANK3_Lane2_MAX (0x0000000F) + #define DDRDATA6CH0_CR_TXPERBITRANK3_Lane3_OFF (12) + #define DDRDATA6CH0_CR_TXPERBITRANK3_Lane3_WID ( 4) + #define DDRDATA6CH0_CR_TXPERBITRANK3_Lane3_MSK (0x0000F000) + #define DDRDATA6CH0_CR_TXPERBITRANK3_Lane3_MAX (0x0000000F) + #define DDRDATA6CH0_CR_TXPERBITRANK3_Lane4_OFF (16) + #define DDRDATA6CH0_CR_TXPERBITRANK3_Lane4_WID ( 4) + #define DDRDATA6CH0_CR_TXPERBITRANK3_Lane4_MSK (0x000F0000) + #define DDRDATA6CH0_CR_TXPERBITRANK3_Lane4_MAX (0x0000000F) + #define DDRDATA6CH0_CR_TXPERBITRANK3_Lane5_OFF (20) + #define DDRDATA6CH0_CR_TXPERBITRANK3_Lane5_WID ( 4) + #define DDRDATA6CH0_CR_TXPERBITRANK3_Lane5_MSK (0x00F00000) + #define DDRDATA6CH0_CR_TXPERBITRANK3_Lane5_MAX (0x0000000F) + #define DDRDATA6CH0_CR_TXPERBITRANK3_Lane6_OFF (24) + #define DDRDATA6CH0_CR_TXPERBITRANK3_Lane6_WID ( 4) + #define DDRDATA6CH0_CR_TXPERBITRANK3_Lane6_MSK (0x0F000000) + #define DDRDATA6CH0_CR_TXPERBITRANK3_Lane6_MAX (0x0000000F) + #define DDRDATA6CH0_CR_TXPERBITRANK3_Lane7_OFF (28) + #define DDRDATA6CH0_CR_TXPERBITRANK3_Lane7_WID ( 4) + #define DDRDATA6CH0_CR_TXPERBITRANK3_Lane7_MSK (0xF0000000) + #define DDRDATA6CH0_CR_TXPERBITRANK3_Lane7_MAX (0x0000000F) + +#define DDRDATA6CH0_CR_RCOMPDATA0_REG (0x00000C40) + #define DDRDATA6CH0_CR_RCOMPDATA0_RcompDrvUp_OFF ( 0) + #define DDRDATA6CH0_CR_RCOMPDATA0_RcompDrvUp_WID ( 6) + #define DDRDATA6CH0_CR_RCOMPDATA0_RcompDrvUp_MSK (0x0000003F) + #define DDRDATA6CH0_CR_RCOMPDATA0_RcompDrvUp_MAX (0x0000003F) + #define DDRDATA6CH0_CR_RCOMPDATA0_Spare0_OFF ( 6) + #define DDRDATA6CH0_CR_RCOMPDATA0_Spare0_WID ( 3) + #define DDRDATA6CH0_CR_RCOMPDATA0_Spare0_MSK (0x000001C0) + #define DDRDATA6CH0_CR_RCOMPDATA0_Spare0_MAX (0x00000007) + #define DDRDATA6CH0_CR_RCOMPDATA0_RcompDrvDown_OFF ( 9) + #define DDRDATA6CH0_CR_RCOMPDATA0_RcompDrvDown_WID ( 6) + #define DDRDATA6CH0_CR_RCOMPDATA0_RcompDrvDown_MSK (0x00007E00) + #define DDRDATA6CH0_CR_RCOMPDATA0_RcompDrvDown_MAX (0x0000003F) + #define DDRDATA6CH0_CR_RCOMPDATA0_VTComp_OFF (15) + #define DDRDATA6CH0_CR_RCOMPDATA0_VTComp_WID ( 5) + #define DDRDATA6CH0_CR_RCOMPDATA0_VTComp_MSK (0x000F8000) + #define DDRDATA6CH0_CR_RCOMPDATA0_VTComp_MAX (0x0000001F) + #define DDRDATA6CH0_CR_RCOMPDATA0_TcoComp_OFF (20) + #define DDRDATA6CH0_CR_RCOMPDATA0_TcoComp_WID ( 6) + #define DDRDATA6CH0_CR_RCOMPDATA0_TcoComp_MSK (0x03F00000) + #define DDRDATA6CH0_CR_RCOMPDATA0_TcoComp_MAX (0x0000003F) + #define DDRDATA6CH0_CR_RCOMPDATA0_SlewRateComp_OFF (26) + #define DDRDATA6CH0_CR_RCOMPDATA0_SlewRateComp_WID ( 5) + #define DDRDATA6CH0_CR_RCOMPDATA0_SlewRateComp_MSK (0x7C000000) + #define DDRDATA6CH0_CR_RCOMPDATA0_SlewRateComp_MAX (0x0000001F) + #define DDRDATA6CH0_CR_RCOMPDATA0_Spare2_OFF (31) + #define DDRDATA6CH0_CR_RCOMPDATA0_Spare2_WID ( 1) + #define DDRDATA6CH0_CR_RCOMPDATA0_Spare2_MSK (0x80000000) + #define DDRDATA6CH0_CR_RCOMPDATA0_Spare2_MAX (0x00000001) + +#define DDRDATA6CH0_CR_RCOMPDATA1_REG (0x00000C44) + #define DDRDATA6CH0_CR_RCOMPDATA1_RcompOdtUp_OFF ( 0) + #define DDRDATA6CH0_CR_RCOMPDATA1_RcompOdtUp_WID ( 6) + #define DDRDATA6CH0_CR_RCOMPDATA1_RcompOdtUp_MSK (0x0000003F) + #define DDRDATA6CH0_CR_RCOMPDATA1_RcompOdtUp_MAX (0x0000003F) + #define DDRDATA6CH0_CR_RCOMPDATA1_Spare0_OFF ( 6) + #define DDRDATA6CH0_CR_RCOMPDATA1_Spare0_WID ( 3) + #define DDRDATA6CH0_CR_RCOMPDATA1_Spare0_MSK (0x000001C0) + #define DDRDATA6CH0_CR_RCOMPDATA1_Spare0_MAX (0x00000007) + #define DDRDATA6CH0_CR_RCOMPDATA1_RcompOdtDown_OFF ( 9) + #define DDRDATA6CH0_CR_RCOMPDATA1_RcompOdtDown_WID ( 6) + #define DDRDATA6CH0_CR_RCOMPDATA1_RcompOdtDown_MSK (0x00007E00) + #define DDRDATA6CH0_CR_RCOMPDATA1_RcompOdtDown_MAX (0x0000003F) + #define DDRDATA6CH0_CR_RCOMPDATA1_Spare1_OFF (15) + #define DDRDATA6CH0_CR_RCOMPDATA1_Spare1_WID ( 1) + #define DDRDATA6CH0_CR_RCOMPDATA1_Spare1_MSK (0x00008000) + #define DDRDATA6CH0_CR_RCOMPDATA1_Spare1_MAX (0x00000001) + #define DDRDATA6CH0_CR_RCOMPDATA1_PanicDrvDn_OFF (16) + #define DDRDATA6CH0_CR_RCOMPDATA1_PanicDrvDn_WID ( 6) + #define DDRDATA6CH0_CR_RCOMPDATA1_PanicDrvDn_MSK (0x003F0000) + #define DDRDATA6CH0_CR_RCOMPDATA1_PanicDrvDn_MAX (0x0000003F) + #define DDRDATA6CH0_CR_RCOMPDATA1_PanicDrvUp_OFF (22) + #define DDRDATA6CH0_CR_RCOMPDATA1_PanicDrvUp_WID ( 6) + #define DDRDATA6CH0_CR_RCOMPDATA1_PanicDrvUp_MSK (0x0FC00000) + #define DDRDATA6CH0_CR_RCOMPDATA1_PanicDrvUp_MAX (0x0000003F) + #define DDRDATA6CH0_CR_RCOMPDATA1_LevelShifterComp_OFF (28) + #define DDRDATA6CH0_CR_RCOMPDATA1_LevelShifterComp_WID ( 3) + #define DDRDATA6CH0_CR_RCOMPDATA1_LevelShifterComp_MSK (0x70000000) + #define DDRDATA6CH0_CR_RCOMPDATA1_LevelShifterComp_MAX (0x00000007) + #define DDRDATA6CH0_CR_RCOMPDATA1_Spare2_OFF (31) + #define DDRDATA6CH0_CR_RCOMPDATA1_Spare2_WID ( 1) + #define DDRDATA6CH0_CR_RCOMPDATA1_Spare2_MSK (0x80000000) + #define DDRDATA6CH0_CR_RCOMPDATA1_Spare2_MAX (0x00000001) + +#define DDRDATA6CH0_CR_TXXTALK_REG (0x00000C48) + #define DDRDATA6CH0_CR_TXXTALK_Lane0_OFF ( 0) + #define DDRDATA6CH0_CR_TXXTALK_Lane0_WID ( 4) + #define DDRDATA6CH0_CR_TXXTALK_Lane0_MSK (0x0000000F) + #define DDRDATA6CH0_CR_TXXTALK_Lane0_MAX (0x0000000F) + #define DDRDATA6CH0_CR_TXXTALK_Lane1_OFF ( 4) + #define DDRDATA6CH0_CR_TXXTALK_Lane1_WID ( 4) + #define DDRDATA6CH0_CR_TXXTALK_Lane1_MSK (0x000000F0) + #define DDRDATA6CH0_CR_TXXTALK_Lane1_MAX (0x0000000F) + #define DDRDATA6CH0_CR_TXXTALK_Lane2_OFF ( 8) + #define DDRDATA6CH0_CR_TXXTALK_Lane2_WID ( 4) + #define DDRDATA6CH0_CR_TXXTALK_Lane2_MSK (0x00000F00) + #define DDRDATA6CH0_CR_TXXTALK_Lane2_MAX (0x0000000F) + #define DDRDATA6CH0_CR_TXXTALK_Lane3_OFF (12) + #define DDRDATA6CH0_CR_TXXTALK_Lane3_WID ( 4) + #define DDRDATA6CH0_CR_TXXTALK_Lane3_MSK (0x0000F000) + #define DDRDATA6CH0_CR_TXXTALK_Lane3_MAX (0x0000000F) + #define DDRDATA6CH0_CR_TXXTALK_Lane4_OFF (16) + #define DDRDATA6CH0_CR_TXXTALK_Lane4_WID ( 4) + #define DDRDATA6CH0_CR_TXXTALK_Lane4_MSK (0x000F0000) + #define DDRDATA6CH0_CR_TXXTALK_Lane4_MAX (0x0000000F) + #define DDRDATA6CH0_CR_TXXTALK_Lane5_OFF (20) + #define DDRDATA6CH0_CR_TXXTALK_Lane5_WID ( 4) + #define DDRDATA6CH0_CR_TXXTALK_Lane5_MSK (0x00F00000) + #define DDRDATA6CH0_CR_TXXTALK_Lane5_MAX (0x0000000F) + #define DDRDATA6CH0_CR_TXXTALK_Lane6_OFF (24) + #define DDRDATA6CH0_CR_TXXTALK_Lane6_WID ( 4) + #define DDRDATA6CH0_CR_TXXTALK_Lane6_MSK (0x0F000000) + #define DDRDATA6CH0_CR_TXXTALK_Lane6_MAX (0x0000000F) + #define DDRDATA6CH0_CR_TXXTALK_Lane7_OFF (28) + #define DDRDATA6CH0_CR_TXXTALK_Lane7_WID ( 4) + #define DDRDATA6CH0_CR_TXXTALK_Lane7_MSK (0xF0000000) + #define DDRDATA6CH0_CR_TXXTALK_Lane7_MAX (0x0000000F) + +#define DDRDATA6CH0_CR_RXOFFSETVDQ_REG (0x00000C4C) + #define DDRDATA6CH0_CR_RXOFFSETVDQ_Lane0_OFF ( 0) + #define DDRDATA6CH0_CR_RXOFFSETVDQ_Lane0_WID ( 4) + #define DDRDATA6CH0_CR_RXOFFSETVDQ_Lane0_MSK (0x0000000F) + #define DDRDATA6CH0_CR_RXOFFSETVDQ_Lane0_MAX (0x0000000F) + #define DDRDATA6CH0_CR_RXOFFSETVDQ_Lane1_OFF ( 4) + #define DDRDATA6CH0_CR_RXOFFSETVDQ_Lane1_WID ( 4) + #define DDRDATA6CH0_CR_RXOFFSETVDQ_Lane1_MSK (0x000000F0) + #define DDRDATA6CH0_CR_RXOFFSETVDQ_Lane1_MAX (0x0000000F) + #define DDRDATA6CH0_CR_RXOFFSETVDQ_Lane2_OFF ( 8) + #define DDRDATA6CH0_CR_RXOFFSETVDQ_Lane2_WID ( 4) + #define DDRDATA6CH0_CR_RXOFFSETVDQ_Lane2_MSK (0x00000F00) + #define DDRDATA6CH0_CR_RXOFFSETVDQ_Lane2_MAX (0x0000000F) + #define DDRDATA6CH0_CR_RXOFFSETVDQ_Lane3_OFF (12) + #define DDRDATA6CH0_CR_RXOFFSETVDQ_Lane3_WID ( 4) + #define DDRDATA6CH0_CR_RXOFFSETVDQ_Lane3_MSK (0x0000F000) + #define DDRDATA6CH0_CR_RXOFFSETVDQ_Lane3_MAX (0x0000000F) + #define DDRDATA6CH0_CR_RXOFFSETVDQ_Lane4_OFF (16) + #define DDRDATA6CH0_CR_RXOFFSETVDQ_Lane4_WID ( 4) + #define DDRDATA6CH0_CR_RXOFFSETVDQ_Lane4_MSK (0x000F0000) + #define DDRDATA6CH0_CR_RXOFFSETVDQ_Lane4_MAX (0x0000000F) + #define DDRDATA6CH0_CR_RXOFFSETVDQ_Lane5_OFF (20) + #define DDRDATA6CH0_CR_RXOFFSETVDQ_Lane5_WID ( 4) + #define DDRDATA6CH0_CR_RXOFFSETVDQ_Lane5_MSK (0x00F00000) + #define DDRDATA6CH0_CR_RXOFFSETVDQ_Lane5_MAX (0x0000000F) + #define DDRDATA6CH0_CR_RXOFFSETVDQ_Lane6_OFF (24) + #define DDRDATA6CH0_CR_RXOFFSETVDQ_Lane6_WID ( 4) + #define DDRDATA6CH0_CR_RXOFFSETVDQ_Lane6_MSK (0x0F000000) + #define DDRDATA6CH0_CR_RXOFFSETVDQ_Lane6_MAX (0x0000000F) + #define DDRDATA6CH0_CR_RXOFFSETVDQ_Lane7_OFF (28) + #define DDRDATA6CH0_CR_RXOFFSETVDQ_Lane7_WID ( 4) + #define DDRDATA6CH0_CR_RXOFFSETVDQ_Lane7_MSK (0xF0000000) + #define DDRDATA6CH0_CR_RXOFFSETVDQ_Lane7_MAX (0x0000000F) + +#define DDRDATA6CH0_CR_DDRDATARESERVED_REG (0x00000C50) + #define DDRDATA6CH0_CR_DDRDATARESERVED_Spare_OFF ( 0) + #define DDRDATA6CH0_CR_DDRDATARESERVED_Spare_WID (32) + #define DDRDATA6CH0_CR_DDRDATARESERVED_Spare_MSK (0xFFFFFFFF) + #define DDRDATA6CH0_CR_DDRDATARESERVED_Spare_MAX (0xFFFFFFFF) + +#define DDRDATA6CH0_CR_DATATRAINFEEDBACK_REG (0x00000C54) + #define DDRDATA6CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_OFF ( 0) + #define DDRDATA6CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_WID ( 9) + #define DDRDATA6CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_MSK (0x000001FF) + #define DDRDATA6CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_MAX (0x000001FF) + #define DDRDATA6CH0_CR_DATATRAINFEEDBACK_Spare_OFF ( 9) + #define DDRDATA6CH0_CR_DATATRAINFEEDBACK_Spare_WID (23) + #define DDRDATA6CH0_CR_DATATRAINFEEDBACK_Spare_MSK (0xFFFFFE00) + #define DDRDATA6CH0_CR_DATATRAINFEEDBACK_Spare_MAX (0x007FFFFF) + +#define DDRDATA6CH0_CR_DLLPITESTANDADC_REG (0x00000C58) + #define DDRDATA6CH0_CR_DLLPITESTANDADC_RunTest_OFF ( 0) + #define DDRDATA6CH0_CR_DLLPITESTANDADC_RunTest_WID ( 1) + #define DDRDATA6CH0_CR_DLLPITESTANDADC_RunTest_MSK (0x00000001) + #define DDRDATA6CH0_CR_DLLPITESTANDADC_RunTest_MAX (0x00000001) + #define DDRDATA6CH0_CR_DLLPITESTANDADC_RunTest_DEF (0x00000000) + #define DDRDATA6CH0_CR_DLLPITESTANDADC_Load_OFF ( 1) + #define DDRDATA6CH0_CR_DLLPITESTANDADC_Load_WID ( 1) + #define DDRDATA6CH0_CR_DLLPITESTANDADC_Load_MSK (0x00000002) + #define DDRDATA6CH0_CR_DLLPITESTANDADC_Load_MAX (0x00000001) + #define DDRDATA6CH0_CR_DLLPITESTANDADC_Load_DEF (0x00000000) + #define DDRDATA6CH0_CR_DLLPITESTANDADC_ModeHVM_OFF ( 2) + #define DDRDATA6CH0_CR_DLLPITESTANDADC_ModeHVM_WID ( 1) + #define DDRDATA6CH0_CR_DLLPITESTANDADC_ModeHVM_MSK (0x00000004) + #define DDRDATA6CH0_CR_DLLPITESTANDADC_ModeHVM_MAX (0x00000001) + #define DDRDATA6CH0_CR_DLLPITESTANDADC_ModeHVM_DEF (0x00000000) + #define DDRDATA6CH0_CR_DLLPITESTANDADC_ModeDV_OFF ( 3) + #define DDRDATA6CH0_CR_DLLPITESTANDADC_ModeDV_WID ( 1) + #define DDRDATA6CH0_CR_DLLPITESTANDADC_ModeDV_MSK (0x00000008) + #define DDRDATA6CH0_CR_DLLPITESTANDADC_ModeDV_MAX (0x00000001) + #define DDRDATA6CH0_CR_DLLPITESTANDADC_ModeDV_DEF (0x00000000) + #define DDRDATA6CH0_CR_DLLPITESTANDADC_ModeADC_OFF ( 4) + #define DDRDATA6CH0_CR_DLLPITESTANDADC_ModeADC_WID ( 1) + #define DDRDATA6CH0_CR_DLLPITESTANDADC_ModeADC_MSK (0x00000010) + #define DDRDATA6CH0_CR_DLLPITESTANDADC_ModeADC_MAX (0x00000001) + #define DDRDATA6CH0_CR_DLLPITESTANDADC_ModeADC_DEF (0x00000000) + #define DDRDATA6CH0_CR_DLLPITESTANDADC_LoadCount_OFF ( 5) + #define DDRDATA6CH0_CR_DLLPITESTANDADC_LoadCount_WID (10) + #define DDRDATA6CH0_CR_DLLPITESTANDADC_LoadCount_MSK (0x00007FE0) + #define DDRDATA6CH0_CR_DLLPITESTANDADC_LoadCount_MAX (0x000003FF) + #define DDRDATA6CH0_CR_DLLPITESTANDADC_CountStatus_OFF (15) + #define DDRDATA6CH0_CR_DLLPITESTANDADC_CountStatus_WID (10) + #define DDRDATA6CH0_CR_DLLPITESTANDADC_CountStatus_MSK (0x01FF8000) + #define DDRDATA6CH0_CR_DLLPITESTANDADC_CountStatus_MAX (0x000003FF) + #define DDRDATA6CH0_CR_DLLPITESTANDADC_CountStatus_DEF (0x00000000) + #define DDRDATA6CH0_CR_DLLPITESTANDADC_Spare_OFF (25) + #define DDRDATA6CH0_CR_DLLPITESTANDADC_Spare_WID ( 7) + #define DDRDATA6CH0_CR_DLLPITESTANDADC_Spare_MSK (0xFE000000) + #define DDRDATA6CH0_CR_DLLPITESTANDADC_Spare_MAX (0x0000007F) + +#define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_REG (0x00000C5C) + #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_OFF ( 0) + #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_WID ( 6) + #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MSK (0x0000003F) + #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MAX (0x0000003F) + #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_DEF (0x00000000) + #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_OFF ( 6) + #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_WID ( 6) + #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MSK (0x00000FC0) + #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MAX (0x0000003F) + #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_DEF (0x00000000) + #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_OFF (12) + #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_WID ( 5) + #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MSK (0x0001F000) + #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MAX (0x0000001F) + #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_DEF (0x00000000) + #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_OFF (17) + #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_WID ( 5) + #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MSK (0x003E0000) + #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MAX (0x0000001F) + #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_DEF (0x00000000) + #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_OFF (22) + #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_WID ( 5) + #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_MSK (0x07C00000) + #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_MAX (0x0000001F) + #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_DEF (0x00000000) + #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_OFF (27) + #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_WID ( 5) + #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MSK (0xF8000000) + #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MAX (0x0000001F) + #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_DEF (0x00000000) + +#define DDRDATA6CH0_CR_DDRCRDATACONTROL1_REG (0x00000C60) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_RefPi_OFF ( 0) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_RefPi_WID ( 4) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_RefPi_MSK (0x0000000F) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_RefPi_MAX (0x0000000F) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_RefPi_DEF (0x00000000) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_DllMask_OFF ( 4) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_DllMask_WID ( 2) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_DllMask_MSK (0x00000030) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_DllMask_MAX (0x00000003) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_DllMask_DEF (0x00000000) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_DllWeakLock_OFF ( 6) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_DllWeakLock_WID ( 1) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_DllWeakLock_MSK (0x00000040) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_DllWeakLock_MAX (0x00000001) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_DllWeakLock_DEF (0x00000000) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_OFF ( 7) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_WID ( 3) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MSK (0x00000380) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MAX (0x00000007) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_DEF (0x00000000) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_OFF (10) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_WID ( 3) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_MSK (0x00001C00) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_MAX (0x00000007) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_DEF (0x00000000) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_OdtDelay_OFF (13) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_OdtDelay_WID ( 4) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_OdtDelay_MSK (0x0001E000) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_OdtDelay_MAX (0x0000000F) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_OdtDelay_DEF (0x00000000) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_OdtDuration_OFF (17) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_OdtDuration_WID ( 3) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_OdtDuration_MSK (0x000E0000) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_OdtDuration_MAX (0x00000007) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_OdtDuration_DEF (0x00000000) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_OFF (20) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_WID ( 4) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_MSK (0x00F00000) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_MAX (0x0000000F) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_DEF (0x00000000) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_OFF (24) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_WID ( 3) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_MSK (0x07000000) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_MAX (0x00000007) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_DEF (0x00000000) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_OFF (27) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_WID ( 3) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_MSK (0x38000000) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_MAX (0x00000007) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_DEF (0x00000000) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_OFF (30) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_WID ( 1) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_MSK (0x40000000) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_MAX (0x00000001) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_DEF (0x00000000) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_Rsvd1_OFF (31) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_Rsvd1_WID ( 1) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_Rsvd1_MSK (0x80000000) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_Rsvd1_MAX (0x00000001) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_Rsvd1_DEF (0x00000000) + +#define DDRDATA6CH0_CR_DDRCRDATACONTROL2_REG (0x00000C64) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_OFF ( 0) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_WID ( 5) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_MSK (0x0000001F) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_MAX (0x0000001F) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_DEF (0x00000000) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_OFF ( 5) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_WID ( 1) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_MSK (0x00000020) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_MAX (0x00000001) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_DEF (0x00000000) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_ForceRxOn_OFF ( 6) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_ForceRxOn_WID ( 1) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_ForceRxOn_MSK (0x00000040) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_ForceRxOn_MAX (0x00000001) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_ForceRxOn_DEF (0x00000000) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_LeakerComp_OFF ( 7) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_LeakerComp_WID ( 2) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_LeakerComp_MSK (0x00000180) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_LeakerComp_MAX (0x00000003) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_LeakerComp_DEF (0x00000000) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_OFF ( 9) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_WID ( 4) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_MSK (0x00001E00) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_MAX (0x0000000F) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_DEF (0x00000008) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_OFF (13) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_WID ( 5) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_MSK (0x0003E000) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_MAX (0x0000001F) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_DEF (0x00000011) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_OFF (18) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_WID ( 1) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_MSK (0x00040000) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_MAX (0x00000001) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_DEF (0x00000000) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_Spare_OFF (19) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_Spare_WID (13) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_Spare_MSK (0xFFF80000) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_Spare_MAX (0x00001FFF) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_Spare_DEF (0x00000000) + +#define DDRDATA6CH0_CR_DDRCRVSSHIORVREFCONTROL_REG (0x00000C6C) + #define DDRDATA6CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_OFF ( 0) + #define DDRDATA6CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_WID (24) + #define DDRDATA6CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_MSK (0x00FFFFFF) + #define DDRDATA6CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_MAX (0x00FFFFFF) + #define DDRDATA6CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_DEF (0x00000000) + #define DDRDATA6CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_OFF (24) + #define DDRDATA6CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_WID ( 8) + #define DDRDATA6CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_MSK (0xFF000000) + #define DDRDATA6CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_MAX (0x000000FF) + #define DDRDATA6CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_DEF (0x00000000) + +#define DDRDATA6CH0_CR_DDRCRDATAOFFSETTRAIN_REG (0x00000C70) + #define DDRDATA6CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_OFF ( 0) + #define DDRDATA6CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_WID ( 6) + #define DDRDATA6CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MSK (0x0000003F) + #define DDRDATA6CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MAX (0x0000003F) + #define DDRDATA6CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_DEF (0x00000000) + #define DDRDATA6CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_OFF ( 6) + #define DDRDATA6CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_WID ( 6) + #define DDRDATA6CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MSK (0x00000FC0) + #define DDRDATA6CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MAX (0x0000003F) + #define DDRDATA6CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_DEF (0x00000000) + #define DDRDATA6CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_OFF (12) + #define DDRDATA6CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_WID ( 6) + #define DDRDATA6CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MSK (0x0003F000) + #define DDRDATA6CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MAX (0x0000003F) + #define DDRDATA6CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_DEF (0x00000000) + #define DDRDATA6CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_OFF (18) + #define DDRDATA6CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_WID ( 6) + #define DDRDATA6CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MSK (0x00FC0000) + #define DDRDATA6CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MAX (0x0000003F) + #define DDRDATA6CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_DEF (0x00000000) + #define DDRDATA6CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_OFF (24) + #define DDRDATA6CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_WID ( 7) + #define DDRDATA6CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MSK (0x7F000000) + #define DDRDATA6CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MAX (0x0000007F) + #define DDRDATA6CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_DEF (0x00000000) + #define DDRDATA6CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_OFF (31) + #define DDRDATA6CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_WID ( 1) + #define DDRDATA6CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_MSK (0x80000000) + #define DDRDATA6CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_MAX (0x00000001) + #define DDRDATA6CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_DEF (0x00000000) + +#define DDRDATA6CH0_CR_DDRCRDATACONTROL0_REG (0x00000C74) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_OFF ( 0) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_WID ( 1) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_MSK (0x00000001) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_MAX (0x00000001) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_DEF (0x00000000) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_OFF ( 1) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_WID ( 1) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_MSK (0x00000002) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_MAX (0x00000001) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_DEF (0x00000000) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_OFF ( 2) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_WID ( 1) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_MSK (0x00000004) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_MAX (0x00000001) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_DEF (0x00000000) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_OFF ( 3) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_WID ( 1) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MSK (0x00000008) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MAX (0x00000001) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_DEF (0x00000000) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_TxOn_OFF ( 4) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_TxOn_WID ( 1) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_TxOn_MSK (0x00000010) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_TxOn_MAX (0x00000001) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_TxOn_DEF (0x00000000) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RfOn_OFF ( 5) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RfOn_WID ( 1) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RfOn_MSK (0x00000020) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RfOn_MAX (0x00000001) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RfOn_DEF (0x00000000) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RxPiOn_OFF ( 6) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RxPiOn_WID ( 1) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RxPiOn_MSK (0x00000040) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RxPiOn_MAX (0x00000001) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RxPiOn_DEF (0x00000000) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_TxPiOn_OFF ( 7) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_TxPiOn_WID ( 1) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_TxPiOn_MSK (0x00000080) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_TxPiOn_MAX (0x00000001) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_TxPiOn_DEF (0x00000000) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_OFF ( 8) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_WID ( 1) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_MSK (0x00000100) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_MAX (0x00000001) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_DEF (0x00000000) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_OFF ( 9) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_WID ( 1) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MSK (0x00000200) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MAX (0x00000001) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_DEF (0x00000000) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_TxDisable_OFF (10) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_TxDisable_WID ( 1) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_TxDisable_MSK (0x00000400) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_TxDisable_MAX (0x00000001) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_TxDisable_DEF (0x00000000) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RxDisable_OFF (11) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RxDisable_WID ( 1) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RxDisable_MSK (0x00000800) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RxDisable_MAX (0x00000001) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RxDisable_DEF (0x00000000) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_TxLong_OFF (12) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_TxLong_WID ( 1) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_TxLong_MSK (0x00001000) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_TxLong_MAX (0x00000001) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_TxLong_DEF (0x00000000) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_OFF (13) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_WID ( 2) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_MSK (0x00006000) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_MAX (0x00000003) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_DEF (0x00000000) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RxReadPointer_OFF (15) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RxReadPointer_WID ( 3) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RxReadPointer_MSK (0x00038000) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RxReadPointer_MAX (0x00000007) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RxReadPointer_DEF (0x00000000) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_OFF (18) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_WID ( 1) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_MSK (0x00040000) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_MAX (0x00000001) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_DEF (0x00000000) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_OFF (19) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_WID ( 1) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_MSK (0x00080000) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_MAX (0x00000001) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_DEF (0x00000000) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_ReadRFRd_OFF (20) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_ReadRFRd_WID ( 1) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_ReadRFRd_MSK (0x00100000) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_ReadRFRd_MAX (0x00000001) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_ReadRFRd_DEF (0x00000000) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_ReadRFWr_OFF (21) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_ReadRFWr_WID ( 1) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_ReadRFWr_MSK (0x00200000) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_ReadRFWr_MAX (0x00000001) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_ReadRFWr_DEF (0x00000000) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_ReadRFRank_OFF (22) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_ReadRFRank_WID ( 2) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_ReadRFRank_MSK (0x00C00000) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_ReadRFRank_MAX (0x00000003) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_ReadRFRank_DEF (0x00000000) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_OFF (24) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_WID ( 1) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_MSK (0x01000000) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_MAX (0x00000001) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_DEF (0x00000000) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_OdtSampOff_OFF (25) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_OdtSampOff_WID ( 1) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_OdtSampOff_MSK (0x02000000) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_OdtSampOff_MAX (0x00000001) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_OdtSampOff_DEF (0x00000000) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_OFF (26) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_WID ( 1) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_MSK (0x04000000) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_MAX (0x00000001) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_DEF (0x00000000) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_OFF (27) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_WID ( 1) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MSK (0x08000000) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MAX (0x00000001) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_DEF (0x00000000) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_OFF (28) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_WID ( 1) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_MSK (0x10000000) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_MAX (0x00000001) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_DEF (0x00000000) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_OFF (29) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_WID ( 1) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_MSK (0x20000000) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_MAX (0x00000001) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_DEF (0x00000000) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_OFF (30) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_WID ( 1) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MSK (0x40000000) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MAX (0x00000001) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_DEF (0x00000000) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_OFF (31) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_WID ( 1) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_MSK (0x80000000) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_MAX (0x00000001) + #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_DEF (0x00000000) + +#define DDRDATA6CH0_CR_DDRCRVREFADJUST1_REG (0x00000C78) + #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_OFF ( 0) + #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_WID ( 7) + #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_MSK (0x0000007F) + #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_MAX (0x0000007F) + #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_DEF (0x00000000) + #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_OFF ( 7) + #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_WID ( 7) + #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_MSK (0x00003F80) + #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_MAX (0x0000007F) + #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_DEF (0x00000000) + #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_OFF (14) + #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_WID ( 7) + #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_MSK (0x001FC000) + #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_MAX (0x0000007F) + #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_DEF (0x00000000) + #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_OFF (21) + #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_WID ( 1) + #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_MSK (0x00200000) + #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_MAX (0x00000001) + #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_DEF (0x00000000) + #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_OFF (22) + #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_WID ( 1) + #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_MSK (0x00400000) + #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_MAX (0x00000001) + #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_DEF (0x00000000) + #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_OFF (23) + #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_WID ( 1) + #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_MSK (0x00800000) + #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_MAX (0x00000001) + #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_DEF (0x00000000) + #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_OFF (24) + #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_WID ( 2) + #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_MSK (0x03000000) + #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_MAX (0x00000003) + #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_DEF (0x00000000) + #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_OFF (26) + #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_WID ( 1) + #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_MSK (0x04000000) + #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_MAX (0x00000001) + #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_DEF (0x00000000) + #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_Rsvd_OFF (27) + #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_Rsvd_WID ( 2) + #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_Rsvd_MSK (0x18000000) + #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_Rsvd_MAX (0x00000003) + #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_Rsvd_DEF (0x00000000) + #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_caSlowBW_OFF (29) + #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_caSlowBW_WID ( 1) + #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_caSlowBW_MSK (0x20000000) + #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_caSlowBW_MAX (0x00000001) + #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_caSlowBW_DEF (0x00000000) + #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_OFF (30) + #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_WID ( 1) + #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_MSK (0x40000000) + #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_MAX (0x00000001) + #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_DEF (0x00000000) + #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_OFF (31) + #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_WID ( 1) + #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_MSK (0x80000000) + #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_MAX (0x00000001) + #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_DEF (0x00000000) + +#define DDRDATA6CH1_CR_RXTRAINRANK0_REG (0x00000D00) + #define DDRDATA6CH1_CR_RXTRAINRANK0_RxRcvEnPi_OFF ( 0) + #define DDRDATA6CH1_CR_RXTRAINRANK0_RxRcvEnPi_WID ( 9) + #define DDRDATA6CH1_CR_RXTRAINRANK0_RxRcvEnPi_MSK (0x000001FF) + #define DDRDATA6CH1_CR_RXTRAINRANK0_RxRcvEnPi_MAX (0x000001FF) + #define DDRDATA6CH1_CR_RXTRAINRANK0_RxDqsPPi_OFF ( 9) + #define DDRDATA6CH1_CR_RXTRAINRANK0_RxDqsPPi_WID ( 6) + #define DDRDATA6CH1_CR_RXTRAINRANK0_RxDqsPPi_MSK (0x00007E00) + #define DDRDATA6CH1_CR_RXTRAINRANK0_RxDqsPPi_MAX (0x0000003F) + #define DDRDATA6CH1_CR_RXTRAINRANK0_RxEq_OFF (15) + #define DDRDATA6CH1_CR_RXTRAINRANK0_RxEq_WID ( 5) + #define DDRDATA6CH1_CR_RXTRAINRANK0_RxEq_MSK (0x000F8000) + #define DDRDATA6CH1_CR_RXTRAINRANK0_RxEq_MAX (0x0000001F) + #define DDRDATA6CH1_CR_RXTRAINRANK0_RxDqsNPi_OFF (20) + #define DDRDATA6CH1_CR_RXTRAINRANK0_RxDqsNPi_WID ( 6) + #define DDRDATA6CH1_CR_RXTRAINRANK0_RxDqsNPi_MSK (0x03F00000) + #define DDRDATA6CH1_CR_RXTRAINRANK0_RxDqsNPi_MAX (0x0000003F) + #define DDRDATA6CH1_CR_RXTRAINRANK0_RxVref_OFF (26) + #define DDRDATA6CH1_CR_RXTRAINRANK0_RxVref_WID ( 6) + #define DDRDATA6CH1_CR_RXTRAINRANK0_RxVref_MSK (0xFC000000) + #define DDRDATA6CH1_CR_RXTRAINRANK0_RxVref_MAX (0x0000003F) + +#define DDRDATA6CH1_CR_RXTRAINRANK1_REG (0x00000D04) + #define DDRDATA6CH1_CR_RXTRAINRANK1_RxRcvEnPi_OFF ( 0) + #define DDRDATA6CH1_CR_RXTRAINRANK1_RxRcvEnPi_WID ( 9) + #define DDRDATA6CH1_CR_RXTRAINRANK1_RxRcvEnPi_MSK (0x000001FF) + #define DDRDATA6CH1_CR_RXTRAINRANK1_RxRcvEnPi_MAX (0x000001FF) + #define DDRDATA6CH1_CR_RXTRAINRANK1_RxDqsPPi_OFF ( 9) + #define DDRDATA6CH1_CR_RXTRAINRANK1_RxDqsPPi_WID ( 6) + #define DDRDATA6CH1_CR_RXTRAINRANK1_RxDqsPPi_MSK (0x00007E00) + #define DDRDATA6CH1_CR_RXTRAINRANK1_RxDqsPPi_MAX (0x0000003F) + #define DDRDATA6CH1_CR_RXTRAINRANK1_RxEq_OFF (15) + #define DDRDATA6CH1_CR_RXTRAINRANK1_RxEq_WID ( 5) + #define DDRDATA6CH1_CR_RXTRAINRANK1_RxEq_MSK (0x000F8000) + #define DDRDATA6CH1_CR_RXTRAINRANK1_RxEq_MAX (0x0000001F) + #define DDRDATA6CH1_CR_RXTRAINRANK1_RxDqsNPi_OFF (20) + #define DDRDATA6CH1_CR_RXTRAINRANK1_RxDqsNPi_WID ( 6) + #define DDRDATA6CH1_CR_RXTRAINRANK1_RxDqsNPi_MSK (0x03F00000) + #define DDRDATA6CH1_CR_RXTRAINRANK1_RxDqsNPi_MAX (0x0000003F) + #define DDRDATA6CH1_CR_RXTRAINRANK1_RxVref_OFF (26) + #define DDRDATA6CH1_CR_RXTRAINRANK1_RxVref_WID ( 6) + #define DDRDATA6CH1_CR_RXTRAINRANK1_RxVref_MSK (0xFC000000) + #define DDRDATA6CH1_CR_RXTRAINRANK1_RxVref_MAX (0x0000003F) + +#define DDRDATA6CH1_CR_RXTRAINRANK2_REG (0x00000D08) + #define DDRDATA6CH1_CR_RXTRAINRANK2_RxRcvEnPi_OFF ( 0) + #define DDRDATA6CH1_CR_RXTRAINRANK2_RxRcvEnPi_WID ( 9) + #define DDRDATA6CH1_CR_RXTRAINRANK2_RxRcvEnPi_MSK (0x000001FF) + #define DDRDATA6CH1_CR_RXTRAINRANK2_RxRcvEnPi_MAX (0x000001FF) + #define DDRDATA6CH1_CR_RXTRAINRANK2_RxDqsPPi_OFF ( 9) + #define DDRDATA6CH1_CR_RXTRAINRANK2_RxDqsPPi_WID ( 6) + #define DDRDATA6CH1_CR_RXTRAINRANK2_RxDqsPPi_MSK (0x00007E00) + #define DDRDATA6CH1_CR_RXTRAINRANK2_RxDqsPPi_MAX (0x0000003F) + #define DDRDATA6CH1_CR_RXTRAINRANK2_RxEq_OFF (15) + #define DDRDATA6CH1_CR_RXTRAINRANK2_RxEq_WID ( 5) + #define DDRDATA6CH1_CR_RXTRAINRANK2_RxEq_MSK (0x000F8000) + #define DDRDATA6CH1_CR_RXTRAINRANK2_RxEq_MAX (0x0000001F) + #define DDRDATA6CH1_CR_RXTRAINRANK2_RxDqsNPi_OFF (20) + #define DDRDATA6CH1_CR_RXTRAINRANK2_RxDqsNPi_WID ( 6) + #define DDRDATA6CH1_CR_RXTRAINRANK2_RxDqsNPi_MSK (0x03F00000) + #define DDRDATA6CH1_CR_RXTRAINRANK2_RxDqsNPi_MAX (0x0000003F) + #define DDRDATA6CH1_CR_RXTRAINRANK2_RxVref_OFF (26) + #define DDRDATA6CH1_CR_RXTRAINRANK2_RxVref_WID ( 6) + #define DDRDATA6CH1_CR_RXTRAINRANK2_RxVref_MSK (0xFC000000) + #define DDRDATA6CH1_CR_RXTRAINRANK2_RxVref_MAX (0x0000003F) + +#define DDRDATA6CH1_CR_RXTRAINRANK3_REG (0x00000D0C) + #define DDRDATA6CH1_CR_RXTRAINRANK3_RxRcvEnPi_OFF ( 0) + #define DDRDATA6CH1_CR_RXTRAINRANK3_RxRcvEnPi_WID ( 9) + #define DDRDATA6CH1_CR_RXTRAINRANK3_RxRcvEnPi_MSK (0x000001FF) + #define DDRDATA6CH1_CR_RXTRAINRANK3_RxRcvEnPi_MAX (0x000001FF) + #define DDRDATA6CH1_CR_RXTRAINRANK3_RxDqsPPi_OFF ( 9) + #define DDRDATA6CH1_CR_RXTRAINRANK3_RxDqsPPi_WID ( 6) + #define DDRDATA6CH1_CR_RXTRAINRANK3_RxDqsPPi_MSK (0x00007E00) + #define DDRDATA6CH1_CR_RXTRAINRANK3_RxDqsPPi_MAX (0x0000003F) + #define DDRDATA6CH1_CR_RXTRAINRANK3_RxEq_OFF (15) + #define DDRDATA6CH1_CR_RXTRAINRANK3_RxEq_WID ( 5) + #define DDRDATA6CH1_CR_RXTRAINRANK3_RxEq_MSK (0x000F8000) + #define DDRDATA6CH1_CR_RXTRAINRANK3_RxEq_MAX (0x0000001F) + #define DDRDATA6CH1_CR_RXTRAINRANK3_RxDqsNPi_OFF (20) + #define DDRDATA6CH1_CR_RXTRAINRANK3_RxDqsNPi_WID ( 6) + #define DDRDATA6CH1_CR_RXTRAINRANK3_RxDqsNPi_MSK (0x03F00000) + #define DDRDATA6CH1_CR_RXTRAINRANK3_RxDqsNPi_MAX (0x0000003F) + #define DDRDATA6CH1_CR_RXTRAINRANK3_RxVref_OFF (26) + #define DDRDATA6CH1_CR_RXTRAINRANK3_RxVref_WID ( 6) + #define DDRDATA6CH1_CR_RXTRAINRANK3_RxVref_MSK (0xFC000000) + #define DDRDATA6CH1_CR_RXTRAINRANK3_RxVref_MAX (0x0000003F) + +#define DDRDATA6CH1_CR_RXPERBITRANK0_REG (0x00000D10) + #define DDRDATA6CH1_CR_RXPERBITRANK0_Lane0_OFF ( 0) + #define DDRDATA6CH1_CR_RXPERBITRANK0_Lane0_WID ( 4) + #define DDRDATA6CH1_CR_RXPERBITRANK0_Lane0_MSK (0x0000000F) + #define DDRDATA6CH1_CR_RXPERBITRANK0_Lane0_MAX (0x0000000F) + #define DDRDATA6CH1_CR_RXPERBITRANK0_Lane1_OFF ( 4) + #define DDRDATA6CH1_CR_RXPERBITRANK0_Lane1_WID ( 4) + #define DDRDATA6CH1_CR_RXPERBITRANK0_Lane1_MSK (0x000000F0) + #define DDRDATA6CH1_CR_RXPERBITRANK0_Lane1_MAX (0x0000000F) + #define DDRDATA6CH1_CR_RXPERBITRANK0_Lane2_OFF ( 8) + #define DDRDATA6CH1_CR_RXPERBITRANK0_Lane2_WID ( 4) + #define DDRDATA6CH1_CR_RXPERBITRANK0_Lane2_MSK (0x00000F00) + #define DDRDATA6CH1_CR_RXPERBITRANK0_Lane2_MAX (0x0000000F) + #define DDRDATA6CH1_CR_RXPERBITRANK0_Lane3_OFF (12) + #define DDRDATA6CH1_CR_RXPERBITRANK0_Lane3_WID ( 4) + #define DDRDATA6CH1_CR_RXPERBITRANK0_Lane3_MSK (0x0000F000) + #define DDRDATA6CH1_CR_RXPERBITRANK0_Lane3_MAX (0x0000000F) + #define DDRDATA6CH1_CR_RXPERBITRANK0_Lane4_OFF (16) + #define DDRDATA6CH1_CR_RXPERBITRANK0_Lane4_WID ( 4) + #define DDRDATA6CH1_CR_RXPERBITRANK0_Lane4_MSK (0x000F0000) + #define DDRDATA6CH1_CR_RXPERBITRANK0_Lane4_MAX (0x0000000F) + #define DDRDATA6CH1_CR_RXPERBITRANK0_Lane5_OFF (20) + #define DDRDATA6CH1_CR_RXPERBITRANK0_Lane5_WID ( 4) + #define DDRDATA6CH1_CR_RXPERBITRANK0_Lane5_MSK (0x00F00000) + #define DDRDATA6CH1_CR_RXPERBITRANK0_Lane5_MAX (0x0000000F) + #define DDRDATA6CH1_CR_RXPERBITRANK0_Lane6_OFF (24) + #define DDRDATA6CH1_CR_RXPERBITRANK0_Lane6_WID ( 4) + #define DDRDATA6CH1_CR_RXPERBITRANK0_Lane6_MSK (0x0F000000) + #define DDRDATA6CH1_CR_RXPERBITRANK0_Lane6_MAX (0x0000000F) + #define DDRDATA6CH1_CR_RXPERBITRANK0_Lane7_OFF (28) + #define DDRDATA6CH1_CR_RXPERBITRANK0_Lane7_WID ( 4) + #define DDRDATA6CH1_CR_RXPERBITRANK0_Lane7_MSK (0xF0000000) + #define DDRDATA6CH1_CR_RXPERBITRANK0_Lane7_MAX (0x0000000F) + +#define DDRDATA6CH1_CR_RXPERBITRANK1_REG (0x00000D14) + #define DDRDATA6CH1_CR_RXPERBITRANK1_Lane0_OFF ( 0) + #define DDRDATA6CH1_CR_RXPERBITRANK1_Lane0_WID ( 4) + #define DDRDATA6CH1_CR_RXPERBITRANK1_Lane0_MSK (0x0000000F) + #define DDRDATA6CH1_CR_RXPERBITRANK1_Lane0_MAX (0x0000000F) + #define DDRDATA6CH1_CR_RXPERBITRANK1_Lane1_OFF ( 4) + #define DDRDATA6CH1_CR_RXPERBITRANK1_Lane1_WID ( 4) + #define DDRDATA6CH1_CR_RXPERBITRANK1_Lane1_MSK (0x000000F0) + #define DDRDATA6CH1_CR_RXPERBITRANK1_Lane1_MAX (0x0000000F) + #define DDRDATA6CH1_CR_RXPERBITRANK1_Lane2_OFF ( 8) + #define DDRDATA6CH1_CR_RXPERBITRANK1_Lane2_WID ( 4) + #define DDRDATA6CH1_CR_RXPERBITRANK1_Lane2_MSK (0x00000F00) + #define DDRDATA6CH1_CR_RXPERBITRANK1_Lane2_MAX (0x0000000F) + #define DDRDATA6CH1_CR_RXPERBITRANK1_Lane3_OFF (12) + #define DDRDATA6CH1_CR_RXPERBITRANK1_Lane3_WID ( 4) + #define DDRDATA6CH1_CR_RXPERBITRANK1_Lane3_MSK (0x0000F000) + #define DDRDATA6CH1_CR_RXPERBITRANK1_Lane3_MAX (0x0000000F) + #define DDRDATA6CH1_CR_RXPERBITRANK1_Lane4_OFF (16) + #define DDRDATA6CH1_CR_RXPERBITRANK1_Lane4_WID ( 4) + #define DDRDATA6CH1_CR_RXPERBITRANK1_Lane4_MSK (0x000F0000) + #define DDRDATA6CH1_CR_RXPERBITRANK1_Lane4_MAX (0x0000000F) + #define DDRDATA6CH1_CR_RXPERBITRANK1_Lane5_OFF (20) + #define DDRDATA6CH1_CR_RXPERBITRANK1_Lane5_WID ( 4) + #define DDRDATA6CH1_CR_RXPERBITRANK1_Lane5_MSK (0x00F00000) + #define DDRDATA6CH1_CR_RXPERBITRANK1_Lane5_MAX (0x0000000F) + #define DDRDATA6CH1_CR_RXPERBITRANK1_Lane6_OFF (24) + #define DDRDATA6CH1_CR_RXPERBITRANK1_Lane6_WID ( 4) + #define DDRDATA6CH1_CR_RXPERBITRANK1_Lane6_MSK (0x0F000000) + #define DDRDATA6CH1_CR_RXPERBITRANK1_Lane6_MAX (0x0000000F) + #define DDRDATA6CH1_CR_RXPERBITRANK1_Lane7_OFF (28) + #define DDRDATA6CH1_CR_RXPERBITRANK1_Lane7_WID ( 4) + #define DDRDATA6CH1_CR_RXPERBITRANK1_Lane7_MSK (0xF0000000) + #define DDRDATA6CH1_CR_RXPERBITRANK1_Lane7_MAX (0x0000000F) + +#define DDRDATA6CH1_CR_RXPERBITRANK2_REG (0x00000D18) + #define DDRDATA6CH1_CR_RXPERBITRANK2_Lane0_OFF ( 0) + #define DDRDATA6CH1_CR_RXPERBITRANK2_Lane0_WID ( 4) + #define DDRDATA6CH1_CR_RXPERBITRANK2_Lane0_MSK (0x0000000F) + #define DDRDATA6CH1_CR_RXPERBITRANK2_Lane0_MAX (0x0000000F) + #define DDRDATA6CH1_CR_RXPERBITRANK2_Lane1_OFF ( 4) + #define DDRDATA6CH1_CR_RXPERBITRANK2_Lane1_WID ( 4) + #define DDRDATA6CH1_CR_RXPERBITRANK2_Lane1_MSK (0x000000F0) + #define DDRDATA6CH1_CR_RXPERBITRANK2_Lane1_MAX (0x0000000F) + #define DDRDATA6CH1_CR_RXPERBITRANK2_Lane2_OFF ( 8) + #define DDRDATA6CH1_CR_RXPERBITRANK2_Lane2_WID ( 4) + #define DDRDATA6CH1_CR_RXPERBITRANK2_Lane2_MSK (0x00000F00) + #define DDRDATA6CH1_CR_RXPERBITRANK2_Lane2_MAX (0x0000000F) + #define DDRDATA6CH1_CR_RXPERBITRANK2_Lane3_OFF (12) + #define DDRDATA6CH1_CR_RXPERBITRANK2_Lane3_WID ( 4) + #define DDRDATA6CH1_CR_RXPERBITRANK2_Lane3_MSK (0x0000F000) + #define DDRDATA6CH1_CR_RXPERBITRANK2_Lane3_MAX (0x0000000F) + #define DDRDATA6CH1_CR_RXPERBITRANK2_Lane4_OFF (16) + #define DDRDATA6CH1_CR_RXPERBITRANK2_Lane4_WID ( 4) + #define DDRDATA6CH1_CR_RXPERBITRANK2_Lane4_MSK (0x000F0000) + #define DDRDATA6CH1_CR_RXPERBITRANK2_Lane4_MAX (0x0000000F) + #define DDRDATA6CH1_CR_RXPERBITRANK2_Lane5_OFF (20) + #define DDRDATA6CH1_CR_RXPERBITRANK2_Lane5_WID ( 4) + #define DDRDATA6CH1_CR_RXPERBITRANK2_Lane5_MSK (0x00F00000) + #define DDRDATA6CH1_CR_RXPERBITRANK2_Lane5_MAX (0x0000000F) + #define DDRDATA6CH1_CR_RXPERBITRANK2_Lane6_OFF (24) + #define DDRDATA6CH1_CR_RXPERBITRANK2_Lane6_WID ( 4) + #define DDRDATA6CH1_CR_RXPERBITRANK2_Lane6_MSK (0x0F000000) + #define DDRDATA6CH1_CR_RXPERBITRANK2_Lane6_MAX (0x0000000F) + #define DDRDATA6CH1_CR_RXPERBITRANK2_Lane7_OFF (28) + #define DDRDATA6CH1_CR_RXPERBITRANK2_Lane7_WID ( 4) + #define DDRDATA6CH1_CR_RXPERBITRANK2_Lane7_MSK (0xF0000000) + #define DDRDATA6CH1_CR_RXPERBITRANK2_Lane7_MAX (0x0000000F) + +#define DDRDATA6CH1_CR_RXPERBITRANK3_REG (0x00000D1C) + #define DDRDATA6CH1_CR_RXPERBITRANK3_Lane0_OFF ( 0) + #define DDRDATA6CH1_CR_RXPERBITRANK3_Lane0_WID ( 4) + #define DDRDATA6CH1_CR_RXPERBITRANK3_Lane0_MSK (0x0000000F) + #define DDRDATA6CH1_CR_RXPERBITRANK3_Lane0_MAX (0x0000000F) + #define DDRDATA6CH1_CR_RXPERBITRANK3_Lane1_OFF ( 4) + #define DDRDATA6CH1_CR_RXPERBITRANK3_Lane1_WID ( 4) + #define DDRDATA6CH1_CR_RXPERBITRANK3_Lane1_MSK (0x000000F0) + #define DDRDATA6CH1_CR_RXPERBITRANK3_Lane1_MAX (0x0000000F) + #define DDRDATA6CH1_CR_RXPERBITRANK3_Lane2_OFF ( 8) + #define DDRDATA6CH1_CR_RXPERBITRANK3_Lane2_WID ( 4) + #define DDRDATA6CH1_CR_RXPERBITRANK3_Lane2_MSK (0x00000F00) + #define DDRDATA6CH1_CR_RXPERBITRANK3_Lane2_MAX (0x0000000F) + #define DDRDATA6CH1_CR_RXPERBITRANK3_Lane3_OFF (12) + #define DDRDATA6CH1_CR_RXPERBITRANK3_Lane3_WID ( 4) + #define DDRDATA6CH1_CR_RXPERBITRANK3_Lane3_MSK (0x0000F000) + #define DDRDATA6CH1_CR_RXPERBITRANK3_Lane3_MAX (0x0000000F) + #define DDRDATA6CH1_CR_RXPERBITRANK3_Lane4_OFF (16) + #define DDRDATA6CH1_CR_RXPERBITRANK3_Lane4_WID ( 4) + #define DDRDATA6CH1_CR_RXPERBITRANK3_Lane4_MSK (0x000F0000) + #define DDRDATA6CH1_CR_RXPERBITRANK3_Lane4_MAX (0x0000000F) + #define DDRDATA6CH1_CR_RXPERBITRANK3_Lane5_OFF (20) + #define DDRDATA6CH1_CR_RXPERBITRANK3_Lane5_WID ( 4) + #define DDRDATA6CH1_CR_RXPERBITRANK3_Lane5_MSK (0x00F00000) + #define DDRDATA6CH1_CR_RXPERBITRANK3_Lane5_MAX (0x0000000F) + #define DDRDATA6CH1_CR_RXPERBITRANK3_Lane6_OFF (24) + #define DDRDATA6CH1_CR_RXPERBITRANK3_Lane6_WID ( 4) + #define DDRDATA6CH1_CR_RXPERBITRANK3_Lane6_MSK (0x0F000000) + #define DDRDATA6CH1_CR_RXPERBITRANK3_Lane6_MAX (0x0000000F) + #define DDRDATA6CH1_CR_RXPERBITRANK3_Lane7_OFF (28) + #define DDRDATA6CH1_CR_RXPERBITRANK3_Lane7_WID ( 4) + #define DDRDATA6CH1_CR_RXPERBITRANK3_Lane7_MSK (0xF0000000) + #define DDRDATA6CH1_CR_RXPERBITRANK3_Lane7_MAX (0x0000000F) + +#define DDRDATA6CH1_CR_TXTRAINRANK0_REG (0x00000D20) + #define DDRDATA6CH1_CR_TXTRAINRANK0_TxDqDelay_OFF ( 0) + #define DDRDATA6CH1_CR_TXTRAINRANK0_TxDqDelay_WID ( 9) + #define DDRDATA6CH1_CR_TXTRAINRANK0_TxDqDelay_MSK (0x000001FF) + #define DDRDATA6CH1_CR_TXTRAINRANK0_TxDqDelay_MAX (0x000001FF) + #define DDRDATA6CH1_CR_TXTRAINRANK0_TxDqsDelay_OFF ( 9) + #define DDRDATA6CH1_CR_TXTRAINRANK0_TxDqsDelay_WID ( 9) + #define DDRDATA6CH1_CR_TXTRAINRANK0_TxDqsDelay_MSK (0x0003FE00) + #define DDRDATA6CH1_CR_TXTRAINRANK0_TxDqsDelay_MAX (0x000001FF) + #define DDRDATA6CH1_CR_TXTRAINRANK0_Spare0_OFF (18) + #define DDRDATA6CH1_CR_TXTRAINRANK0_Spare0_WID ( 2) + #define DDRDATA6CH1_CR_TXTRAINRANK0_Spare0_MSK (0x000C0000) + #define DDRDATA6CH1_CR_TXTRAINRANK0_Spare0_MAX (0x00000003) + #define DDRDATA6CH1_CR_TXTRAINRANK0_TxEqualization_OFF (20) + #define DDRDATA6CH1_CR_TXTRAINRANK0_TxEqualization_WID ( 6) + #define DDRDATA6CH1_CR_TXTRAINRANK0_TxEqualization_MSK (0x03F00000) + #define DDRDATA6CH1_CR_TXTRAINRANK0_TxEqualization_MAX (0x0000003F) + #define DDRDATA6CH1_CR_TXTRAINRANK0_Spare1_OFF (26) + #define DDRDATA6CH1_CR_TXTRAINRANK0_Spare1_WID ( 6) + #define DDRDATA6CH1_CR_TXTRAINRANK0_Spare1_MSK (0xFC000000) + #define DDRDATA6CH1_CR_TXTRAINRANK0_Spare1_MAX (0x0000003F) + +#define DDRDATA6CH1_CR_TXTRAINRANK1_REG (0x00000D24) + #define DDRDATA6CH1_CR_TXTRAINRANK1_TxDqDelay_OFF ( 0) + #define DDRDATA6CH1_CR_TXTRAINRANK1_TxDqDelay_WID ( 9) + #define DDRDATA6CH1_CR_TXTRAINRANK1_TxDqDelay_MSK (0x000001FF) + #define DDRDATA6CH1_CR_TXTRAINRANK1_TxDqDelay_MAX (0x000001FF) + #define DDRDATA6CH1_CR_TXTRAINRANK1_TxDqsDelay_OFF ( 9) + #define DDRDATA6CH1_CR_TXTRAINRANK1_TxDqsDelay_WID ( 9) + #define DDRDATA6CH1_CR_TXTRAINRANK1_TxDqsDelay_MSK (0x0003FE00) + #define DDRDATA6CH1_CR_TXTRAINRANK1_TxDqsDelay_MAX (0x000001FF) + #define DDRDATA6CH1_CR_TXTRAINRANK1_Spare0_OFF (18) + #define DDRDATA6CH1_CR_TXTRAINRANK1_Spare0_WID ( 2) + #define DDRDATA6CH1_CR_TXTRAINRANK1_Spare0_MSK (0x000C0000) + #define DDRDATA6CH1_CR_TXTRAINRANK1_Spare0_MAX (0x00000003) + #define DDRDATA6CH1_CR_TXTRAINRANK1_TxEqualization_OFF (20) + #define DDRDATA6CH1_CR_TXTRAINRANK1_TxEqualization_WID ( 6) + #define DDRDATA6CH1_CR_TXTRAINRANK1_TxEqualization_MSK (0x03F00000) + #define DDRDATA6CH1_CR_TXTRAINRANK1_TxEqualization_MAX (0x0000003F) + #define DDRDATA6CH1_CR_TXTRAINRANK1_Spare1_OFF (26) + #define DDRDATA6CH1_CR_TXTRAINRANK1_Spare1_WID ( 6) + #define DDRDATA6CH1_CR_TXTRAINRANK1_Spare1_MSK (0xFC000000) + #define DDRDATA6CH1_CR_TXTRAINRANK1_Spare1_MAX (0x0000003F) + +#define DDRDATA6CH1_CR_TXTRAINRANK2_REG (0x00000D28) + #define DDRDATA6CH1_CR_TXTRAINRANK2_TxDqDelay_OFF ( 0) + #define DDRDATA6CH1_CR_TXTRAINRANK2_TxDqDelay_WID ( 9) + #define DDRDATA6CH1_CR_TXTRAINRANK2_TxDqDelay_MSK (0x000001FF) + #define DDRDATA6CH1_CR_TXTRAINRANK2_TxDqDelay_MAX (0x000001FF) + #define DDRDATA6CH1_CR_TXTRAINRANK2_TxDqsDelay_OFF ( 9) + #define DDRDATA6CH1_CR_TXTRAINRANK2_TxDqsDelay_WID ( 9) + #define DDRDATA6CH1_CR_TXTRAINRANK2_TxDqsDelay_MSK (0x0003FE00) + #define DDRDATA6CH1_CR_TXTRAINRANK2_TxDqsDelay_MAX (0x000001FF) + #define DDRDATA6CH1_CR_TXTRAINRANK2_Spare0_OFF (18) + #define DDRDATA6CH1_CR_TXTRAINRANK2_Spare0_WID ( 2) + #define DDRDATA6CH1_CR_TXTRAINRANK2_Spare0_MSK (0x000C0000) + #define DDRDATA6CH1_CR_TXTRAINRANK2_Spare0_MAX (0x00000003) + #define DDRDATA6CH1_CR_TXTRAINRANK2_TxEqualization_OFF (20) + #define DDRDATA6CH1_CR_TXTRAINRANK2_TxEqualization_WID ( 6) + #define DDRDATA6CH1_CR_TXTRAINRANK2_TxEqualization_MSK (0x03F00000) + #define DDRDATA6CH1_CR_TXTRAINRANK2_TxEqualization_MAX (0x0000003F) + #define DDRDATA6CH1_CR_TXTRAINRANK2_Spare1_OFF (26) + #define DDRDATA6CH1_CR_TXTRAINRANK2_Spare1_WID ( 6) + #define DDRDATA6CH1_CR_TXTRAINRANK2_Spare1_MSK (0xFC000000) + #define DDRDATA6CH1_CR_TXTRAINRANK2_Spare1_MAX (0x0000003F) + +#define DDRDATA6CH1_CR_TXTRAINRANK3_REG (0x00000D2C) + #define DDRDATA6CH1_CR_TXTRAINRANK3_TxDqDelay_OFF ( 0) + #define DDRDATA6CH1_CR_TXTRAINRANK3_TxDqDelay_WID ( 9) + #define DDRDATA6CH1_CR_TXTRAINRANK3_TxDqDelay_MSK (0x000001FF) + #define DDRDATA6CH1_CR_TXTRAINRANK3_TxDqDelay_MAX (0x000001FF) + #define DDRDATA6CH1_CR_TXTRAINRANK3_TxDqsDelay_OFF ( 9) + #define DDRDATA6CH1_CR_TXTRAINRANK3_TxDqsDelay_WID ( 9) + #define DDRDATA6CH1_CR_TXTRAINRANK3_TxDqsDelay_MSK (0x0003FE00) + #define DDRDATA6CH1_CR_TXTRAINRANK3_TxDqsDelay_MAX (0x000001FF) + #define DDRDATA6CH1_CR_TXTRAINRANK3_Spare0_OFF (18) + #define DDRDATA6CH1_CR_TXTRAINRANK3_Spare0_WID ( 2) + #define DDRDATA6CH1_CR_TXTRAINRANK3_Spare0_MSK (0x000C0000) + #define DDRDATA6CH1_CR_TXTRAINRANK3_Spare0_MAX (0x00000003) + #define DDRDATA6CH1_CR_TXTRAINRANK3_TxEqualization_OFF (20) + #define DDRDATA6CH1_CR_TXTRAINRANK3_TxEqualization_WID ( 6) + #define DDRDATA6CH1_CR_TXTRAINRANK3_TxEqualization_MSK (0x03F00000) + #define DDRDATA6CH1_CR_TXTRAINRANK3_TxEqualization_MAX (0x0000003F) + #define DDRDATA6CH1_CR_TXTRAINRANK3_Spare1_OFF (26) + #define DDRDATA6CH1_CR_TXTRAINRANK3_Spare1_WID ( 6) + #define DDRDATA6CH1_CR_TXTRAINRANK3_Spare1_MSK (0xFC000000) + #define DDRDATA6CH1_CR_TXTRAINRANK3_Spare1_MAX (0x0000003F) + +#define DDRDATA6CH1_CR_TXPERBITRANK0_REG (0x00000D30) + #define DDRDATA6CH1_CR_TXPERBITRANK0_Lane0_OFF ( 0) + #define DDRDATA6CH1_CR_TXPERBITRANK0_Lane0_WID ( 4) + #define DDRDATA6CH1_CR_TXPERBITRANK0_Lane0_MSK (0x0000000F) + #define DDRDATA6CH1_CR_TXPERBITRANK0_Lane0_MAX (0x0000000F) + #define DDRDATA6CH1_CR_TXPERBITRANK0_Lane1_OFF ( 4) + #define DDRDATA6CH1_CR_TXPERBITRANK0_Lane1_WID ( 4) + #define DDRDATA6CH1_CR_TXPERBITRANK0_Lane1_MSK (0x000000F0) + #define DDRDATA6CH1_CR_TXPERBITRANK0_Lane1_MAX (0x0000000F) + #define DDRDATA6CH1_CR_TXPERBITRANK0_Lane2_OFF ( 8) + #define DDRDATA6CH1_CR_TXPERBITRANK0_Lane2_WID ( 4) + #define DDRDATA6CH1_CR_TXPERBITRANK0_Lane2_MSK (0x00000F00) + #define DDRDATA6CH1_CR_TXPERBITRANK0_Lane2_MAX (0x0000000F) + #define DDRDATA6CH1_CR_TXPERBITRANK0_Lane3_OFF (12) + #define DDRDATA6CH1_CR_TXPERBITRANK0_Lane3_WID ( 4) + #define DDRDATA6CH1_CR_TXPERBITRANK0_Lane3_MSK (0x0000F000) + #define DDRDATA6CH1_CR_TXPERBITRANK0_Lane3_MAX (0x0000000F) + #define DDRDATA6CH1_CR_TXPERBITRANK0_Lane4_OFF (16) + #define DDRDATA6CH1_CR_TXPERBITRANK0_Lane4_WID ( 4) + #define DDRDATA6CH1_CR_TXPERBITRANK0_Lane4_MSK (0x000F0000) + #define DDRDATA6CH1_CR_TXPERBITRANK0_Lane4_MAX (0x0000000F) + #define DDRDATA6CH1_CR_TXPERBITRANK0_Lane5_OFF (20) + #define DDRDATA6CH1_CR_TXPERBITRANK0_Lane5_WID ( 4) + #define DDRDATA6CH1_CR_TXPERBITRANK0_Lane5_MSK (0x00F00000) + #define DDRDATA6CH1_CR_TXPERBITRANK0_Lane5_MAX (0x0000000F) + #define DDRDATA6CH1_CR_TXPERBITRANK0_Lane6_OFF (24) + #define DDRDATA6CH1_CR_TXPERBITRANK0_Lane6_WID ( 4) + #define DDRDATA6CH1_CR_TXPERBITRANK0_Lane6_MSK (0x0F000000) + #define DDRDATA6CH1_CR_TXPERBITRANK0_Lane6_MAX (0x0000000F) + #define DDRDATA6CH1_CR_TXPERBITRANK0_Lane7_OFF (28) + #define DDRDATA6CH1_CR_TXPERBITRANK0_Lane7_WID ( 4) + #define DDRDATA6CH1_CR_TXPERBITRANK0_Lane7_MSK (0xF0000000) + #define DDRDATA6CH1_CR_TXPERBITRANK0_Lane7_MAX (0x0000000F) + +#define DDRDATA6CH1_CR_TXPERBITRANK1_REG (0x00000D34) + #define DDRDATA6CH1_CR_TXPERBITRANK1_Lane0_OFF ( 0) + #define DDRDATA6CH1_CR_TXPERBITRANK1_Lane0_WID ( 4) + #define DDRDATA6CH1_CR_TXPERBITRANK1_Lane0_MSK (0x0000000F) + #define DDRDATA6CH1_CR_TXPERBITRANK1_Lane0_MAX (0x0000000F) + #define DDRDATA6CH1_CR_TXPERBITRANK1_Lane1_OFF ( 4) + #define DDRDATA6CH1_CR_TXPERBITRANK1_Lane1_WID ( 4) + #define DDRDATA6CH1_CR_TXPERBITRANK1_Lane1_MSK (0x000000F0) + #define DDRDATA6CH1_CR_TXPERBITRANK1_Lane1_MAX (0x0000000F) + #define DDRDATA6CH1_CR_TXPERBITRANK1_Lane2_OFF ( 8) + #define DDRDATA6CH1_CR_TXPERBITRANK1_Lane2_WID ( 4) + #define DDRDATA6CH1_CR_TXPERBITRANK1_Lane2_MSK (0x00000F00) + #define DDRDATA6CH1_CR_TXPERBITRANK1_Lane2_MAX (0x0000000F) + #define DDRDATA6CH1_CR_TXPERBITRANK1_Lane3_OFF (12) + #define DDRDATA6CH1_CR_TXPERBITRANK1_Lane3_WID ( 4) + #define DDRDATA6CH1_CR_TXPERBITRANK1_Lane3_MSK (0x0000F000) + #define DDRDATA6CH1_CR_TXPERBITRANK1_Lane3_MAX (0x0000000F) + #define DDRDATA6CH1_CR_TXPERBITRANK1_Lane4_OFF (16) + #define DDRDATA6CH1_CR_TXPERBITRANK1_Lane4_WID ( 4) + #define DDRDATA6CH1_CR_TXPERBITRANK1_Lane4_MSK (0x000F0000) + #define DDRDATA6CH1_CR_TXPERBITRANK1_Lane4_MAX (0x0000000F) + #define DDRDATA6CH1_CR_TXPERBITRANK1_Lane5_OFF (20) + #define DDRDATA6CH1_CR_TXPERBITRANK1_Lane5_WID ( 4) + #define DDRDATA6CH1_CR_TXPERBITRANK1_Lane5_MSK (0x00F00000) + #define DDRDATA6CH1_CR_TXPERBITRANK1_Lane5_MAX (0x0000000F) + #define DDRDATA6CH1_CR_TXPERBITRANK1_Lane6_OFF (24) + #define DDRDATA6CH1_CR_TXPERBITRANK1_Lane6_WID ( 4) + #define DDRDATA6CH1_CR_TXPERBITRANK1_Lane6_MSK (0x0F000000) + #define DDRDATA6CH1_CR_TXPERBITRANK1_Lane6_MAX (0x0000000F) + #define DDRDATA6CH1_CR_TXPERBITRANK1_Lane7_OFF (28) + #define DDRDATA6CH1_CR_TXPERBITRANK1_Lane7_WID ( 4) + #define DDRDATA6CH1_CR_TXPERBITRANK1_Lane7_MSK (0xF0000000) + #define DDRDATA6CH1_CR_TXPERBITRANK1_Lane7_MAX (0x0000000F) + +#define DDRDATA6CH1_CR_TXPERBITRANK2_REG (0x00000D38) + #define DDRDATA6CH1_CR_TXPERBITRANK2_Lane0_OFF ( 0) + #define DDRDATA6CH1_CR_TXPERBITRANK2_Lane0_WID ( 4) + #define DDRDATA6CH1_CR_TXPERBITRANK2_Lane0_MSK (0x0000000F) + #define DDRDATA6CH1_CR_TXPERBITRANK2_Lane0_MAX (0x0000000F) + #define DDRDATA6CH1_CR_TXPERBITRANK2_Lane1_OFF ( 4) + #define DDRDATA6CH1_CR_TXPERBITRANK2_Lane1_WID ( 4) + #define DDRDATA6CH1_CR_TXPERBITRANK2_Lane1_MSK (0x000000F0) + #define DDRDATA6CH1_CR_TXPERBITRANK2_Lane1_MAX (0x0000000F) + #define DDRDATA6CH1_CR_TXPERBITRANK2_Lane2_OFF ( 8) + #define DDRDATA6CH1_CR_TXPERBITRANK2_Lane2_WID ( 4) + #define DDRDATA6CH1_CR_TXPERBITRANK2_Lane2_MSK (0x00000F00) + #define DDRDATA6CH1_CR_TXPERBITRANK2_Lane2_MAX (0x0000000F) + #define DDRDATA6CH1_CR_TXPERBITRANK2_Lane3_OFF (12) + #define DDRDATA6CH1_CR_TXPERBITRANK2_Lane3_WID ( 4) + #define DDRDATA6CH1_CR_TXPERBITRANK2_Lane3_MSK (0x0000F000) + #define DDRDATA6CH1_CR_TXPERBITRANK2_Lane3_MAX (0x0000000F) + #define DDRDATA6CH1_CR_TXPERBITRANK2_Lane4_OFF (16) + #define DDRDATA6CH1_CR_TXPERBITRANK2_Lane4_WID ( 4) + #define DDRDATA6CH1_CR_TXPERBITRANK2_Lane4_MSK (0x000F0000) + #define DDRDATA6CH1_CR_TXPERBITRANK2_Lane4_MAX (0x0000000F) + #define DDRDATA6CH1_CR_TXPERBITRANK2_Lane5_OFF (20) + #define DDRDATA6CH1_CR_TXPERBITRANK2_Lane5_WID ( 4) + #define DDRDATA6CH1_CR_TXPERBITRANK2_Lane5_MSK (0x00F00000) + #define DDRDATA6CH1_CR_TXPERBITRANK2_Lane5_MAX (0x0000000F) + #define DDRDATA6CH1_CR_TXPERBITRANK2_Lane6_OFF (24) + #define DDRDATA6CH1_CR_TXPERBITRANK2_Lane6_WID ( 4) + #define DDRDATA6CH1_CR_TXPERBITRANK2_Lane6_MSK (0x0F000000) + #define DDRDATA6CH1_CR_TXPERBITRANK2_Lane6_MAX (0x0000000F) + #define DDRDATA6CH1_CR_TXPERBITRANK2_Lane7_OFF (28) + #define DDRDATA6CH1_CR_TXPERBITRANK2_Lane7_WID ( 4) + #define DDRDATA6CH1_CR_TXPERBITRANK2_Lane7_MSK (0xF0000000) + #define DDRDATA6CH1_CR_TXPERBITRANK2_Lane7_MAX (0x0000000F) + +#define DDRDATA6CH1_CR_TXPERBITRANK3_REG (0x00000D3C) + #define DDRDATA6CH1_CR_TXPERBITRANK3_Lane0_OFF ( 0) + #define DDRDATA6CH1_CR_TXPERBITRANK3_Lane0_WID ( 4) + #define DDRDATA6CH1_CR_TXPERBITRANK3_Lane0_MSK (0x0000000F) + #define DDRDATA6CH1_CR_TXPERBITRANK3_Lane0_MAX (0x0000000F) + #define DDRDATA6CH1_CR_TXPERBITRANK3_Lane1_OFF ( 4) + #define DDRDATA6CH1_CR_TXPERBITRANK3_Lane1_WID ( 4) + #define DDRDATA6CH1_CR_TXPERBITRANK3_Lane1_MSK (0x000000F0) + #define DDRDATA6CH1_CR_TXPERBITRANK3_Lane1_MAX (0x0000000F) + #define DDRDATA6CH1_CR_TXPERBITRANK3_Lane2_OFF ( 8) + #define DDRDATA6CH1_CR_TXPERBITRANK3_Lane2_WID ( 4) + #define DDRDATA6CH1_CR_TXPERBITRANK3_Lane2_MSK (0x00000F00) + #define DDRDATA6CH1_CR_TXPERBITRANK3_Lane2_MAX (0x0000000F) + #define DDRDATA6CH1_CR_TXPERBITRANK3_Lane3_OFF (12) + #define DDRDATA6CH1_CR_TXPERBITRANK3_Lane3_WID ( 4) + #define DDRDATA6CH1_CR_TXPERBITRANK3_Lane3_MSK (0x0000F000) + #define DDRDATA6CH1_CR_TXPERBITRANK3_Lane3_MAX (0x0000000F) + #define DDRDATA6CH1_CR_TXPERBITRANK3_Lane4_OFF (16) + #define DDRDATA6CH1_CR_TXPERBITRANK3_Lane4_WID ( 4) + #define DDRDATA6CH1_CR_TXPERBITRANK3_Lane4_MSK (0x000F0000) + #define DDRDATA6CH1_CR_TXPERBITRANK3_Lane4_MAX (0x0000000F) + #define DDRDATA6CH1_CR_TXPERBITRANK3_Lane5_OFF (20) + #define DDRDATA6CH1_CR_TXPERBITRANK3_Lane5_WID ( 4) + #define DDRDATA6CH1_CR_TXPERBITRANK3_Lane5_MSK (0x00F00000) + #define DDRDATA6CH1_CR_TXPERBITRANK3_Lane5_MAX (0x0000000F) + #define DDRDATA6CH1_CR_TXPERBITRANK3_Lane6_OFF (24) + #define DDRDATA6CH1_CR_TXPERBITRANK3_Lane6_WID ( 4) + #define DDRDATA6CH1_CR_TXPERBITRANK3_Lane6_MSK (0x0F000000) + #define DDRDATA6CH1_CR_TXPERBITRANK3_Lane6_MAX (0x0000000F) + #define DDRDATA6CH1_CR_TXPERBITRANK3_Lane7_OFF (28) + #define DDRDATA6CH1_CR_TXPERBITRANK3_Lane7_WID ( 4) + #define DDRDATA6CH1_CR_TXPERBITRANK3_Lane7_MSK (0xF0000000) + #define DDRDATA6CH1_CR_TXPERBITRANK3_Lane7_MAX (0x0000000F) + +#define DDRDATA6CH1_CR_RCOMPDATA0_REG (0x00000D40) + #define DDRDATA6CH1_CR_RCOMPDATA0_RcompDrvUp_OFF ( 0) + #define DDRDATA6CH1_CR_RCOMPDATA0_RcompDrvUp_WID ( 6) + #define DDRDATA6CH1_CR_RCOMPDATA0_RcompDrvUp_MSK (0x0000003F) + #define DDRDATA6CH1_CR_RCOMPDATA0_RcompDrvUp_MAX (0x0000003F) + #define DDRDATA6CH1_CR_RCOMPDATA0_Spare0_OFF ( 6) + #define DDRDATA6CH1_CR_RCOMPDATA0_Spare0_WID ( 3) + #define DDRDATA6CH1_CR_RCOMPDATA0_Spare0_MSK (0x000001C0) + #define DDRDATA6CH1_CR_RCOMPDATA0_Spare0_MAX (0x00000007) + #define DDRDATA6CH1_CR_RCOMPDATA0_RcompDrvDown_OFF ( 9) + #define DDRDATA6CH1_CR_RCOMPDATA0_RcompDrvDown_WID ( 6) + #define DDRDATA6CH1_CR_RCOMPDATA0_RcompDrvDown_MSK (0x00007E00) + #define DDRDATA6CH1_CR_RCOMPDATA0_RcompDrvDown_MAX (0x0000003F) + #define DDRDATA6CH1_CR_RCOMPDATA0_VTComp_OFF (15) + #define DDRDATA6CH1_CR_RCOMPDATA0_VTComp_WID ( 5) + #define DDRDATA6CH1_CR_RCOMPDATA0_VTComp_MSK (0x000F8000) + #define DDRDATA6CH1_CR_RCOMPDATA0_VTComp_MAX (0x0000001F) + #define DDRDATA6CH1_CR_RCOMPDATA0_TcoComp_OFF (20) + #define DDRDATA6CH1_CR_RCOMPDATA0_TcoComp_WID ( 6) + #define DDRDATA6CH1_CR_RCOMPDATA0_TcoComp_MSK (0x03F00000) + #define DDRDATA6CH1_CR_RCOMPDATA0_TcoComp_MAX (0x0000003F) + #define DDRDATA6CH1_CR_RCOMPDATA0_SlewRateComp_OFF (26) + #define DDRDATA6CH1_CR_RCOMPDATA0_SlewRateComp_WID ( 5) + #define DDRDATA6CH1_CR_RCOMPDATA0_SlewRateComp_MSK (0x7C000000) + #define DDRDATA6CH1_CR_RCOMPDATA0_SlewRateComp_MAX (0x0000001F) + #define DDRDATA6CH1_CR_RCOMPDATA0_Spare2_OFF (31) + #define DDRDATA6CH1_CR_RCOMPDATA0_Spare2_WID ( 1) + #define DDRDATA6CH1_CR_RCOMPDATA0_Spare2_MSK (0x80000000) + #define DDRDATA6CH1_CR_RCOMPDATA0_Spare2_MAX (0x00000001) + +#define DDRDATA6CH1_CR_RCOMPDATA1_REG (0x00000D44) + #define DDRDATA6CH1_CR_RCOMPDATA1_RcompOdtUp_OFF ( 0) + #define DDRDATA6CH1_CR_RCOMPDATA1_RcompOdtUp_WID ( 6) + #define DDRDATA6CH1_CR_RCOMPDATA1_RcompOdtUp_MSK (0x0000003F) + #define DDRDATA6CH1_CR_RCOMPDATA1_RcompOdtUp_MAX (0x0000003F) + #define DDRDATA6CH1_CR_RCOMPDATA1_Spare0_OFF ( 6) + #define DDRDATA6CH1_CR_RCOMPDATA1_Spare0_WID ( 3) + #define DDRDATA6CH1_CR_RCOMPDATA1_Spare0_MSK (0x000001C0) + #define DDRDATA6CH1_CR_RCOMPDATA1_Spare0_MAX (0x00000007) + #define DDRDATA6CH1_CR_RCOMPDATA1_RcompOdtDown_OFF ( 9) + #define DDRDATA6CH1_CR_RCOMPDATA1_RcompOdtDown_WID ( 6) + #define DDRDATA6CH1_CR_RCOMPDATA1_RcompOdtDown_MSK (0x00007E00) + #define DDRDATA6CH1_CR_RCOMPDATA1_RcompOdtDown_MAX (0x0000003F) + #define DDRDATA6CH1_CR_RCOMPDATA1_Spare1_OFF (15) + #define DDRDATA6CH1_CR_RCOMPDATA1_Spare1_WID ( 1) + #define DDRDATA6CH1_CR_RCOMPDATA1_Spare1_MSK (0x00008000) + #define DDRDATA6CH1_CR_RCOMPDATA1_Spare1_MAX (0x00000001) + #define DDRDATA6CH1_CR_RCOMPDATA1_PanicDrvDn_OFF (16) + #define DDRDATA6CH1_CR_RCOMPDATA1_PanicDrvDn_WID ( 6) + #define DDRDATA6CH1_CR_RCOMPDATA1_PanicDrvDn_MSK (0x003F0000) + #define DDRDATA6CH1_CR_RCOMPDATA1_PanicDrvDn_MAX (0x0000003F) + #define DDRDATA6CH1_CR_RCOMPDATA1_PanicDrvUp_OFF (22) + #define DDRDATA6CH1_CR_RCOMPDATA1_PanicDrvUp_WID ( 6) + #define DDRDATA6CH1_CR_RCOMPDATA1_PanicDrvUp_MSK (0x0FC00000) + #define DDRDATA6CH1_CR_RCOMPDATA1_PanicDrvUp_MAX (0x0000003F) + #define DDRDATA6CH1_CR_RCOMPDATA1_LevelShifterComp_OFF (28) + #define DDRDATA6CH1_CR_RCOMPDATA1_LevelShifterComp_WID ( 3) + #define DDRDATA6CH1_CR_RCOMPDATA1_LevelShifterComp_MSK (0x70000000) + #define DDRDATA6CH1_CR_RCOMPDATA1_LevelShifterComp_MAX (0x00000007) + #define DDRDATA6CH1_CR_RCOMPDATA1_Spare2_OFF (31) + #define DDRDATA6CH1_CR_RCOMPDATA1_Spare2_WID ( 1) + #define DDRDATA6CH1_CR_RCOMPDATA1_Spare2_MSK (0x80000000) + #define DDRDATA6CH1_CR_RCOMPDATA1_Spare2_MAX (0x00000001) + +#define DDRDATA6CH1_CR_TXXTALK_REG (0x00000D48) + #define DDRDATA6CH1_CR_TXXTALK_Lane0_OFF ( 0) + #define DDRDATA6CH1_CR_TXXTALK_Lane0_WID ( 4) + #define DDRDATA6CH1_CR_TXXTALK_Lane0_MSK (0x0000000F) + #define DDRDATA6CH1_CR_TXXTALK_Lane0_MAX (0x0000000F) + #define DDRDATA6CH1_CR_TXXTALK_Lane1_OFF ( 4) + #define DDRDATA6CH1_CR_TXXTALK_Lane1_WID ( 4) + #define DDRDATA6CH1_CR_TXXTALK_Lane1_MSK (0x000000F0) + #define DDRDATA6CH1_CR_TXXTALK_Lane1_MAX (0x0000000F) + #define DDRDATA6CH1_CR_TXXTALK_Lane2_OFF ( 8) + #define DDRDATA6CH1_CR_TXXTALK_Lane2_WID ( 4) + #define DDRDATA6CH1_CR_TXXTALK_Lane2_MSK (0x00000F00) + #define DDRDATA6CH1_CR_TXXTALK_Lane2_MAX (0x0000000F) + #define DDRDATA6CH1_CR_TXXTALK_Lane3_OFF (12) + #define DDRDATA6CH1_CR_TXXTALK_Lane3_WID ( 4) + #define DDRDATA6CH1_CR_TXXTALK_Lane3_MSK (0x0000F000) + #define DDRDATA6CH1_CR_TXXTALK_Lane3_MAX (0x0000000F) + #define DDRDATA6CH1_CR_TXXTALK_Lane4_OFF (16) + #define DDRDATA6CH1_CR_TXXTALK_Lane4_WID ( 4) + #define DDRDATA6CH1_CR_TXXTALK_Lane4_MSK (0x000F0000) + #define DDRDATA6CH1_CR_TXXTALK_Lane4_MAX (0x0000000F) + #define DDRDATA6CH1_CR_TXXTALK_Lane5_OFF (20) + #define DDRDATA6CH1_CR_TXXTALK_Lane5_WID ( 4) + #define DDRDATA6CH1_CR_TXXTALK_Lane5_MSK (0x00F00000) + #define DDRDATA6CH1_CR_TXXTALK_Lane5_MAX (0x0000000F) + #define DDRDATA6CH1_CR_TXXTALK_Lane6_OFF (24) + #define DDRDATA6CH1_CR_TXXTALK_Lane6_WID ( 4) + #define DDRDATA6CH1_CR_TXXTALK_Lane6_MSK (0x0F000000) + #define DDRDATA6CH1_CR_TXXTALK_Lane6_MAX (0x0000000F) + #define DDRDATA6CH1_CR_TXXTALK_Lane7_OFF (28) + #define DDRDATA6CH1_CR_TXXTALK_Lane7_WID ( 4) + #define DDRDATA6CH1_CR_TXXTALK_Lane7_MSK (0xF0000000) + #define DDRDATA6CH1_CR_TXXTALK_Lane7_MAX (0x0000000F) + +#define DDRDATA6CH1_CR_RXOFFSETVDQ_REG (0x00000D4C) + #define DDRDATA6CH1_CR_RXOFFSETVDQ_Lane0_OFF ( 0) + #define DDRDATA6CH1_CR_RXOFFSETVDQ_Lane0_WID ( 4) + #define DDRDATA6CH1_CR_RXOFFSETVDQ_Lane0_MSK (0x0000000F) + #define DDRDATA6CH1_CR_RXOFFSETVDQ_Lane0_MAX (0x0000000F) + #define DDRDATA6CH1_CR_RXOFFSETVDQ_Lane1_OFF ( 4) + #define DDRDATA6CH1_CR_RXOFFSETVDQ_Lane1_WID ( 4) + #define DDRDATA6CH1_CR_RXOFFSETVDQ_Lane1_MSK (0x000000F0) + #define DDRDATA6CH1_CR_RXOFFSETVDQ_Lane1_MAX (0x0000000F) + #define DDRDATA6CH1_CR_RXOFFSETVDQ_Lane2_OFF ( 8) + #define DDRDATA6CH1_CR_RXOFFSETVDQ_Lane2_WID ( 4) + #define DDRDATA6CH1_CR_RXOFFSETVDQ_Lane2_MSK (0x00000F00) + #define DDRDATA6CH1_CR_RXOFFSETVDQ_Lane2_MAX (0x0000000F) + #define DDRDATA6CH1_CR_RXOFFSETVDQ_Lane3_OFF (12) + #define DDRDATA6CH1_CR_RXOFFSETVDQ_Lane3_WID ( 4) + #define DDRDATA6CH1_CR_RXOFFSETVDQ_Lane3_MSK (0x0000F000) + #define DDRDATA6CH1_CR_RXOFFSETVDQ_Lane3_MAX (0x0000000F) + #define DDRDATA6CH1_CR_RXOFFSETVDQ_Lane4_OFF (16) + #define DDRDATA6CH1_CR_RXOFFSETVDQ_Lane4_WID ( 4) + #define DDRDATA6CH1_CR_RXOFFSETVDQ_Lane4_MSK (0x000F0000) + #define DDRDATA6CH1_CR_RXOFFSETVDQ_Lane4_MAX (0x0000000F) + #define DDRDATA6CH1_CR_RXOFFSETVDQ_Lane5_OFF (20) + #define DDRDATA6CH1_CR_RXOFFSETVDQ_Lane5_WID ( 4) + #define DDRDATA6CH1_CR_RXOFFSETVDQ_Lane5_MSK (0x00F00000) + #define DDRDATA6CH1_CR_RXOFFSETVDQ_Lane5_MAX (0x0000000F) + #define DDRDATA6CH1_CR_RXOFFSETVDQ_Lane6_OFF (24) + #define DDRDATA6CH1_CR_RXOFFSETVDQ_Lane6_WID ( 4) + #define DDRDATA6CH1_CR_RXOFFSETVDQ_Lane6_MSK (0x0F000000) + #define DDRDATA6CH1_CR_RXOFFSETVDQ_Lane6_MAX (0x0000000F) + #define DDRDATA6CH1_CR_RXOFFSETVDQ_Lane7_OFF (28) + #define DDRDATA6CH1_CR_RXOFFSETVDQ_Lane7_WID ( 4) + #define DDRDATA6CH1_CR_RXOFFSETVDQ_Lane7_MSK (0xF0000000) + #define DDRDATA6CH1_CR_RXOFFSETVDQ_Lane7_MAX (0x0000000F) + +#define DDRDATA6CH1_CR_DDRDATARESERVED_REG (0x00000D50) + #define DDRDATA6CH1_CR_DDRDATARESERVED_Spare_OFF ( 0) + #define DDRDATA6CH1_CR_DDRDATARESERVED_Spare_WID (32) + #define DDRDATA6CH1_CR_DDRDATARESERVED_Spare_MSK (0xFFFFFFFF) + #define DDRDATA6CH1_CR_DDRDATARESERVED_Spare_MAX (0xFFFFFFFF) + +#define DDRDATA6CH1_CR_DATATRAINFEEDBACK_REG (0x00000D54) + #define DDRDATA6CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_OFF ( 0) + #define DDRDATA6CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_WID ( 9) + #define DDRDATA6CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_MSK (0x000001FF) + #define DDRDATA6CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_MAX (0x000001FF) + #define DDRDATA6CH1_CR_DATATRAINFEEDBACK_Spare_OFF ( 9) + #define DDRDATA6CH1_CR_DATATRAINFEEDBACK_Spare_WID (23) + #define DDRDATA6CH1_CR_DATATRAINFEEDBACK_Spare_MSK (0xFFFFFE00) + #define DDRDATA6CH1_CR_DATATRAINFEEDBACK_Spare_MAX (0x007FFFFF) + +#define DDRDATA6CH1_CR_DLLPITESTANDADC_REG (0x00000D58) + #define DDRDATA6CH1_CR_DLLPITESTANDADC_RunTest_OFF ( 0) + #define DDRDATA6CH1_CR_DLLPITESTANDADC_RunTest_WID ( 1) + #define DDRDATA6CH1_CR_DLLPITESTANDADC_RunTest_MSK (0x00000001) + #define DDRDATA6CH1_CR_DLLPITESTANDADC_RunTest_MAX (0x00000001) + #define DDRDATA6CH1_CR_DLLPITESTANDADC_RunTest_DEF (0x00000000) + #define DDRDATA6CH1_CR_DLLPITESTANDADC_Load_OFF ( 1) + #define DDRDATA6CH1_CR_DLLPITESTANDADC_Load_WID ( 1) + #define DDRDATA6CH1_CR_DLLPITESTANDADC_Load_MSK (0x00000002) + #define DDRDATA6CH1_CR_DLLPITESTANDADC_Load_MAX (0x00000001) + #define DDRDATA6CH1_CR_DLLPITESTANDADC_Load_DEF (0x00000000) + #define DDRDATA6CH1_CR_DLLPITESTANDADC_ModeHVM_OFF ( 2) + #define DDRDATA6CH1_CR_DLLPITESTANDADC_ModeHVM_WID ( 1) + #define DDRDATA6CH1_CR_DLLPITESTANDADC_ModeHVM_MSK (0x00000004) + #define DDRDATA6CH1_CR_DLLPITESTANDADC_ModeHVM_MAX (0x00000001) + #define DDRDATA6CH1_CR_DLLPITESTANDADC_ModeHVM_DEF (0x00000000) + #define DDRDATA6CH1_CR_DLLPITESTANDADC_ModeDV_OFF ( 3) + #define DDRDATA6CH1_CR_DLLPITESTANDADC_ModeDV_WID ( 1) + #define DDRDATA6CH1_CR_DLLPITESTANDADC_ModeDV_MSK (0x00000008) + #define DDRDATA6CH1_CR_DLLPITESTANDADC_ModeDV_MAX (0x00000001) + #define DDRDATA6CH1_CR_DLLPITESTANDADC_ModeDV_DEF (0x00000000) + #define DDRDATA6CH1_CR_DLLPITESTANDADC_ModeADC_OFF ( 4) + #define DDRDATA6CH1_CR_DLLPITESTANDADC_ModeADC_WID ( 1) + #define DDRDATA6CH1_CR_DLLPITESTANDADC_ModeADC_MSK (0x00000010) + #define DDRDATA6CH1_CR_DLLPITESTANDADC_ModeADC_MAX (0x00000001) + #define DDRDATA6CH1_CR_DLLPITESTANDADC_ModeADC_DEF (0x00000000) + #define DDRDATA6CH1_CR_DLLPITESTANDADC_LoadCount_OFF ( 5) + #define DDRDATA6CH1_CR_DLLPITESTANDADC_LoadCount_WID (10) + #define DDRDATA6CH1_CR_DLLPITESTANDADC_LoadCount_MSK (0x00007FE0) + #define DDRDATA6CH1_CR_DLLPITESTANDADC_LoadCount_MAX (0x000003FF) + #define DDRDATA6CH1_CR_DLLPITESTANDADC_CountStatus_OFF (15) + #define DDRDATA6CH1_CR_DLLPITESTANDADC_CountStatus_WID (10) + #define DDRDATA6CH1_CR_DLLPITESTANDADC_CountStatus_MSK (0x01FF8000) + #define DDRDATA6CH1_CR_DLLPITESTANDADC_CountStatus_MAX (0x000003FF) + #define DDRDATA6CH1_CR_DLLPITESTANDADC_CountStatus_DEF (0x00000000) + #define DDRDATA6CH1_CR_DLLPITESTANDADC_Spare_OFF (25) + #define DDRDATA6CH1_CR_DLLPITESTANDADC_Spare_WID ( 7) + #define DDRDATA6CH1_CR_DLLPITESTANDADC_Spare_MSK (0xFE000000) + #define DDRDATA6CH1_CR_DLLPITESTANDADC_Spare_MAX (0x0000007F) + +#define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_REG (0x00000D5C) + #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_OFF ( 0) + #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_WID ( 6) + #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MSK (0x0000003F) + #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MAX (0x0000003F) + #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_DEF (0x00000000) + #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_OFF ( 6) + #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_WID ( 6) + #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MSK (0x00000FC0) + #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MAX (0x0000003F) + #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_DEF (0x00000000) + #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_OFF (12) + #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_WID ( 5) + #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MSK (0x0001F000) + #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MAX (0x0000001F) + #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_DEF (0x00000000) + #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_OFF (17) + #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_WID ( 5) + #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MSK (0x003E0000) + #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MAX (0x0000001F) + #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_DEF (0x00000000) + #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_OFF (22) + #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_WID ( 5) + #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_MSK (0x07C00000) + #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_MAX (0x0000001F) + #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_DEF (0x00000000) + #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_OFF (27) + #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_WID ( 5) + #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MSK (0xF8000000) + #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MAX (0x0000001F) + #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_DEF (0x00000000) + +#define DDRDATA6CH1_CR_DDRCRDATACONTROL1_REG (0x00000D60) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_RefPi_OFF ( 0) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_RefPi_WID ( 4) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_RefPi_MSK (0x0000000F) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_RefPi_MAX (0x0000000F) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_RefPi_DEF (0x00000000) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_DllMask_OFF ( 4) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_DllMask_WID ( 2) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_DllMask_MSK (0x00000030) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_DllMask_MAX (0x00000003) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_DllMask_DEF (0x00000000) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_DllWeakLock_OFF ( 6) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_DllWeakLock_WID ( 1) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_DllWeakLock_MSK (0x00000040) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_DllWeakLock_MAX (0x00000001) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_DllWeakLock_DEF (0x00000000) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_OFF ( 7) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_WID ( 3) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MSK (0x00000380) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MAX (0x00000007) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_DEF (0x00000000) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_OFF (10) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_WID ( 3) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_MSK (0x00001C00) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_MAX (0x00000007) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_DEF (0x00000000) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_OdtDelay_OFF (13) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_OdtDelay_WID ( 4) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_OdtDelay_MSK (0x0001E000) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_OdtDelay_MAX (0x0000000F) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_OdtDelay_DEF (0x00000000) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_OdtDuration_OFF (17) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_OdtDuration_WID ( 3) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_OdtDuration_MSK (0x000E0000) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_OdtDuration_MAX (0x00000007) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_OdtDuration_DEF (0x00000000) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_OFF (20) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_WID ( 4) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_MSK (0x00F00000) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_MAX (0x0000000F) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_DEF (0x00000000) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_OFF (24) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_WID ( 3) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_MSK (0x07000000) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_MAX (0x00000007) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_DEF (0x00000000) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_OFF (27) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_WID ( 3) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_MSK (0x38000000) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_MAX (0x00000007) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_DEF (0x00000000) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_OFF (30) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_WID ( 1) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_MSK (0x40000000) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_MAX (0x00000001) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_DEF (0x00000000) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_Rsvd1_OFF (31) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_Rsvd1_WID ( 1) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_Rsvd1_MSK (0x80000000) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_Rsvd1_MAX (0x00000001) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_Rsvd1_DEF (0x00000000) + +#define DDRDATA6CH1_CR_DDRCRDATACONTROL2_REG (0x00000D64) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_OFF ( 0) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_WID ( 5) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_MSK (0x0000001F) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_MAX (0x0000001F) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_DEF (0x00000000) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_OFF ( 5) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_WID ( 1) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_MSK (0x00000020) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_MAX (0x00000001) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_DEF (0x00000000) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_ForceRxOn_OFF ( 6) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_ForceRxOn_WID ( 1) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_ForceRxOn_MSK (0x00000040) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_ForceRxOn_MAX (0x00000001) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_ForceRxOn_DEF (0x00000000) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_LeakerComp_OFF ( 7) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_LeakerComp_WID ( 2) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_LeakerComp_MSK (0x00000180) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_LeakerComp_MAX (0x00000003) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_LeakerComp_DEF (0x00000000) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_OFF ( 9) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_WID ( 4) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_MSK (0x00001E00) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_MAX (0x0000000F) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_DEF (0x00000008) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_OFF (13) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_WID ( 5) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_MSK (0x0003E000) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_MAX (0x0000001F) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_DEF (0x00000011) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_OFF (18) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_WID ( 1) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_MSK (0x00040000) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_MAX (0x00000001) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_DEF (0x00000000) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_Spare_OFF (19) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_Spare_WID (13) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_Spare_MSK (0xFFF80000) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_Spare_MAX (0x00001FFF) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_Spare_DEF (0x00000000) + +#define DDRDATA6CH1_CR_DDRCRVSSHIORVREFCONTROL_REG (0x00000D6C) + #define DDRDATA6CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_OFF ( 0) + #define DDRDATA6CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_WID (24) + #define DDRDATA6CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_MSK (0x00FFFFFF) + #define DDRDATA6CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_MAX (0x00FFFFFF) + #define DDRDATA6CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_DEF (0x00000000) + #define DDRDATA6CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_OFF (24) + #define DDRDATA6CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_WID ( 8) + #define DDRDATA6CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_MSK (0xFF000000) + #define DDRDATA6CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_MAX (0x000000FF) + #define DDRDATA6CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_DEF (0x00000000) + +#define DDRDATA6CH1_CR_DDRCRDATAOFFSETTRAIN_REG (0x00000D70) + #define DDRDATA6CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_OFF ( 0) + #define DDRDATA6CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_WID ( 6) + #define DDRDATA6CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MSK (0x0000003F) + #define DDRDATA6CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MAX (0x0000003F) + #define DDRDATA6CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_DEF (0x00000000) + #define DDRDATA6CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_OFF ( 6) + #define DDRDATA6CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_WID ( 6) + #define DDRDATA6CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MSK (0x00000FC0) + #define DDRDATA6CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MAX (0x0000003F) + #define DDRDATA6CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_DEF (0x00000000) + #define DDRDATA6CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_OFF (12) + #define DDRDATA6CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_WID ( 6) + #define DDRDATA6CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MSK (0x0003F000) + #define DDRDATA6CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MAX (0x0000003F) + #define DDRDATA6CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_DEF (0x00000000) + #define DDRDATA6CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_OFF (18) + #define DDRDATA6CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_WID ( 6) + #define DDRDATA6CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MSK (0x00FC0000) + #define DDRDATA6CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MAX (0x0000003F) + #define DDRDATA6CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_DEF (0x00000000) + #define DDRDATA6CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_OFF (24) + #define DDRDATA6CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_WID ( 7) + #define DDRDATA6CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MSK (0x7F000000) + #define DDRDATA6CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MAX (0x0000007F) + #define DDRDATA6CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_DEF (0x00000000) + #define DDRDATA6CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_OFF (31) + #define DDRDATA6CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_WID ( 1) + #define DDRDATA6CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_MSK (0x80000000) + #define DDRDATA6CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_MAX (0x00000001) + #define DDRDATA6CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_DEF (0x00000000) + +#define DDRDATA6CH1_CR_DDRCRDATACONTROL0_REG (0x00000D74) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_OFF ( 0) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_WID ( 1) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_MSK (0x00000001) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_MAX (0x00000001) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_DEF (0x00000000) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_OFF ( 1) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_WID ( 1) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_MSK (0x00000002) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_MAX (0x00000001) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_DEF (0x00000000) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_OFF ( 2) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_WID ( 1) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_MSK (0x00000004) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_MAX (0x00000001) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_DEF (0x00000000) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_OFF ( 3) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_WID ( 1) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MSK (0x00000008) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MAX (0x00000001) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_DEF (0x00000000) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_TxOn_OFF ( 4) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_TxOn_WID ( 1) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_TxOn_MSK (0x00000010) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_TxOn_MAX (0x00000001) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_TxOn_DEF (0x00000000) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RfOn_OFF ( 5) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RfOn_WID ( 1) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RfOn_MSK (0x00000020) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RfOn_MAX (0x00000001) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RfOn_DEF (0x00000000) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RxPiOn_OFF ( 6) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RxPiOn_WID ( 1) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RxPiOn_MSK (0x00000040) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RxPiOn_MAX (0x00000001) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RxPiOn_DEF (0x00000000) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_TxPiOn_OFF ( 7) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_TxPiOn_WID ( 1) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_TxPiOn_MSK (0x00000080) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_TxPiOn_MAX (0x00000001) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_TxPiOn_DEF (0x00000000) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_OFF ( 8) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_WID ( 1) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_MSK (0x00000100) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_MAX (0x00000001) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_DEF (0x00000000) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_OFF ( 9) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_WID ( 1) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MSK (0x00000200) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MAX (0x00000001) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_DEF (0x00000000) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_TxDisable_OFF (10) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_TxDisable_WID ( 1) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_TxDisable_MSK (0x00000400) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_TxDisable_MAX (0x00000001) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_TxDisable_DEF (0x00000000) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RxDisable_OFF (11) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RxDisable_WID ( 1) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RxDisable_MSK (0x00000800) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RxDisable_MAX (0x00000001) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RxDisable_DEF (0x00000000) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_TxLong_OFF (12) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_TxLong_WID ( 1) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_TxLong_MSK (0x00001000) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_TxLong_MAX (0x00000001) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_TxLong_DEF (0x00000000) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_OFF (13) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_WID ( 2) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_MSK (0x00006000) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_MAX (0x00000003) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_DEF (0x00000000) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RxReadPointer_OFF (15) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RxReadPointer_WID ( 3) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RxReadPointer_MSK (0x00038000) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RxReadPointer_MAX (0x00000007) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RxReadPointer_DEF (0x00000000) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_OFF (18) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_WID ( 1) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_MSK (0x00040000) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_MAX (0x00000001) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_DEF (0x00000000) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_OFF (19) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_WID ( 1) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_MSK (0x00080000) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_MAX (0x00000001) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_DEF (0x00000000) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_ReadRFRd_OFF (20) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_ReadRFRd_WID ( 1) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_ReadRFRd_MSK (0x00100000) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_ReadRFRd_MAX (0x00000001) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_ReadRFRd_DEF (0x00000000) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_ReadRFWr_OFF (21) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_ReadRFWr_WID ( 1) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_ReadRFWr_MSK (0x00200000) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_ReadRFWr_MAX (0x00000001) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_ReadRFWr_DEF (0x00000000) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_ReadRFRank_OFF (22) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_ReadRFRank_WID ( 2) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_ReadRFRank_MSK (0x00C00000) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_ReadRFRank_MAX (0x00000003) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_ReadRFRank_DEF (0x00000000) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_OFF (24) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_WID ( 1) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_MSK (0x01000000) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_MAX (0x00000001) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_DEF (0x00000000) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_OdtSampOff_OFF (25) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_OdtSampOff_WID ( 1) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_OdtSampOff_MSK (0x02000000) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_OdtSampOff_MAX (0x00000001) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_OdtSampOff_DEF (0x00000000) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_OFF (26) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_WID ( 1) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_MSK (0x04000000) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_MAX (0x00000001) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_DEF (0x00000000) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_OFF (27) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_WID ( 1) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MSK (0x08000000) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MAX (0x00000001) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_DEF (0x00000000) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_OFF (28) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_WID ( 1) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_MSK (0x10000000) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_MAX (0x00000001) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_DEF (0x00000000) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_OFF (29) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_WID ( 1) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_MSK (0x20000000) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_MAX (0x00000001) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_DEF (0x00000000) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_OFF (30) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_WID ( 1) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MSK (0x40000000) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MAX (0x00000001) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_DEF (0x00000000) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_OFF (31) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_WID ( 1) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_MSK (0x80000000) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_MAX (0x00000001) + #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_DEF (0x00000000) + +#define DDRDATA6CH1_CR_DDRCRVREFADJUST1_REG (0x00000D78) + #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_OFF ( 0) + #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_WID ( 7) + #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_MSK (0x0000007F) + #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_MAX (0x0000007F) + #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_DEF (0x00000000) + #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_OFF ( 7) + #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_WID ( 7) + #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_MSK (0x00003F80) + #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_MAX (0x0000007F) + #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_DEF (0x00000000) + #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_OFF (14) + #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_WID ( 7) + #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_MSK (0x001FC000) + #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_MAX (0x0000007F) + #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_DEF (0x00000000) + #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_OFF (21) + #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_WID ( 1) + #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_MSK (0x00200000) + #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_MAX (0x00000001) + #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_DEF (0x00000000) + #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_OFF (22) + #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_WID ( 1) + #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_MSK (0x00400000) + #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_MAX (0x00000001) + #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_DEF (0x00000000) + #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_OFF (23) + #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_WID ( 1) + #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_MSK (0x00800000) + #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_MAX (0x00000001) + #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_DEF (0x00000000) + #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_OFF (24) + #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_WID ( 2) + #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_MSK (0x03000000) + #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_MAX (0x00000003) + #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_DEF (0x00000000) + #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_OFF (26) + #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_WID ( 1) + #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_MSK (0x04000000) + #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_MAX (0x00000001) + #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_DEF (0x00000000) + #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_Rsvd_OFF (27) + #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_Rsvd_WID ( 2) + #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_Rsvd_MSK (0x18000000) + #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_Rsvd_MAX (0x00000003) + #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_Rsvd_DEF (0x00000000) + #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_caSlowBW_OFF (29) + #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_caSlowBW_WID ( 1) + #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_caSlowBW_MSK (0x20000000) + #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_caSlowBW_MAX (0x00000001) + #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_caSlowBW_DEF (0x00000000) + #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_OFF (30) + #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_WID ( 1) + #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_MSK (0x40000000) + #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_MAX (0x00000001) + #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_DEF (0x00000000) + #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_OFF (31) + #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_WID ( 1) + #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_MSK (0x80000000) + #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_MAX (0x00000001) + #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_DEF (0x00000000) + +#define DDRDATA7CH0_CR_RXTRAINRANK0_REG (0x00000E00) + #define DDRDATA7CH0_CR_RXTRAINRANK0_RxRcvEnPi_OFF ( 0) + #define DDRDATA7CH0_CR_RXTRAINRANK0_RxRcvEnPi_WID ( 9) + #define DDRDATA7CH0_CR_RXTRAINRANK0_RxRcvEnPi_MSK (0x000001FF) + #define DDRDATA7CH0_CR_RXTRAINRANK0_RxRcvEnPi_MAX (0x000001FF) + #define DDRDATA7CH0_CR_RXTRAINRANK0_RxDqsPPi_OFF ( 9) + #define DDRDATA7CH0_CR_RXTRAINRANK0_RxDqsPPi_WID ( 6) + #define DDRDATA7CH0_CR_RXTRAINRANK0_RxDqsPPi_MSK (0x00007E00) + #define DDRDATA7CH0_CR_RXTRAINRANK0_RxDqsPPi_MAX (0x0000003F) + #define DDRDATA7CH0_CR_RXTRAINRANK0_RxEq_OFF (15) + #define DDRDATA7CH0_CR_RXTRAINRANK0_RxEq_WID ( 5) + #define DDRDATA7CH0_CR_RXTRAINRANK0_RxEq_MSK (0x000F8000) + #define DDRDATA7CH0_CR_RXTRAINRANK0_RxEq_MAX (0x0000001F) + #define DDRDATA7CH0_CR_RXTRAINRANK0_RxDqsNPi_OFF (20) + #define DDRDATA7CH0_CR_RXTRAINRANK0_RxDqsNPi_WID ( 6) + #define DDRDATA7CH0_CR_RXTRAINRANK0_RxDqsNPi_MSK (0x03F00000) + #define DDRDATA7CH0_CR_RXTRAINRANK0_RxDqsNPi_MAX (0x0000003F) + #define DDRDATA7CH0_CR_RXTRAINRANK0_RxVref_OFF (26) + #define DDRDATA7CH0_CR_RXTRAINRANK0_RxVref_WID ( 6) + #define DDRDATA7CH0_CR_RXTRAINRANK0_RxVref_MSK (0xFC000000) + #define DDRDATA7CH0_CR_RXTRAINRANK0_RxVref_MAX (0x0000003F) + +#define DDRDATA7CH0_CR_RXTRAINRANK1_REG (0x00000E04) + #define DDRDATA7CH0_CR_RXTRAINRANK1_RxRcvEnPi_OFF ( 0) + #define DDRDATA7CH0_CR_RXTRAINRANK1_RxRcvEnPi_WID ( 9) + #define DDRDATA7CH0_CR_RXTRAINRANK1_RxRcvEnPi_MSK (0x000001FF) + #define DDRDATA7CH0_CR_RXTRAINRANK1_RxRcvEnPi_MAX (0x000001FF) + #define DDRDATA7CH0_CR_RXTRAINRANK1_RxDqsPPi_OFF ( 9) + #define DDRDATA7CH0_CR_RXTRAINRANK1_RxDqsPPi_WID ( 6) + #define DDRDATA7CH0_CR_RXTRAINRANK1_RxDqsPPi_MSK (0x00007E00) + #define DDRDATA7CH0_CR_RXTRAINRANK1_RxDqsPPi_MAX (0x0000003F) + #define DDRDATA7CH0_CR_RXTRAINRANK1_RxEq_OFF (15) + #define DDRDATA7CH0_CR_RXTRAINRANK1_RxEq_WID ( 5) + #define DDRDATA7CH0_CR_RXTRAINRANK1_RxEq_MSK (0x000F8000) + #define DDRDATA7CH0_CR_RXTRAINRANK1_RxEq_MAX (0x0000001F) + #define DDRDATA7CH0_CR_RXTRAINRANK1_RxDqsNPi_OFF (20) + #define DDRDATA7CH0_CR_RXTRAINRANK1_RxDqsNPi_WID ( 6) + #define DDRDATA7CH0_CR_RXTRAINRANK1_RxDqsNPi_MSK (0x03F00000) + #define DDRDATA7CH0_CR_RXTRAINRANK1_RxDqsNPi_MAX (0x0000003F) + #define DDRDATA7CH0_CR_RXTRAINRANK1_RxVref_OFF (26) + #define DDRDATA7CH0_CR_RXTRAINRANK1_RxVref_WID ( 6) + #define DDRDATA7CH0_CR_RXTRAINRANK1_RxVref_MSK (0xFC000000) + #define DDRDATA7CH0_CR_RXTRAINRANK1_RxVref_MAX (0x0000003F) + +#define DDRDATA7CH0_CR_RXTRAINRANK2_REG (0x00000E08) + #define DDRDATA7CH0_CR_RXTRAINRANK2_RxRcvEnPi_OFF ( 0) + #define DDRDATA7CH0_CR_RXTRAINRANK2_RxRcvEnPi_WID ( 9) + #define DDRDATA7CH0_CR_RXTRAINRANK2_RxRcvEnPi_MSK (0x000001FF) + #define DDRDATA7CH0_CR_RXTRAINRANK2_RxRcvEnPi_MAX (0x000001FF) + #define DDRDATA7CH0_CR_RXTRAINRANK2_RxDqsPPi_OFF ( 9) + #define DDRDATA7CH0_CR_RXTRAINRANK2_RxDqsPPi_WID ( 6) + #define DDRDATA7CH0_CR_RXTRAINRANK2_RxDqsPPi_MSK (0x00007E00) + #define DDRDATA7CH0_CR_RXTRAINRANK2_RxDqsPPi_MAX (0x0000003F) + #define DDRDATA7CH0_CR_RXTRAINRANK2_RxEq_OFF (15) + #define DDRDATA7CH0_CR_RXTRAINRANK2_RxEq_WID ( 5) + #define DDRDATA7CH0_CR_RXTRAINRANK2_RxEq_MSK (0x000F8000) + #define DDRDATA7CH0_CR_RXTRAINRANK2_RxEq_MAX (0x0000001F) + #define DDRDATA7CH0_CR_RXTRAINRANK2_RxDqsNPi_OFF (20) + #define DDRDATA7CH0_CR_RXTRAINRANK2_RxDqsNPi_WID ( 6) + #define DDRDATA7CH0_CR_RXTRAINRANK2_RxDqsNPi_MSK (0x03F00000) + #define DDRDATA7CH0_CR_RXTRAINRANK2_RxDqsNPi_MAX (0x0000003F) + #define DDRDATA7CH0_CR_RXTRAINRANK2_RxVref_OFF (26) + #define DDRDATA7CH0_CR_RXTRAINRANK2_RxVref_WID ( 6) + #define DDRDATA7CH0_CR_RXTRAINRANK2_RxVref_MSK (0xFC000000) + #define DDRDATA7CH0_CR_RXTRAINRANK2_RxVref_MAX (0x0000003F) + +#define DDRDATA7CH0_CR_RXTRAINRANK3_REG (0x00000E0C) + #define DDRDATA7CH0_CR_RXTRAINRANK3_RxRcvEnPi_OFF ( 0) + #define DDRDATA7CH0_CR_RXTRAINRANK3_RxRcvEnPi_WID ( 9) + #define DDRDATA7CH0_CR_RXTRAINRANK3_RxRcvEnPi_MSK (0x000001FF) + #define DDRDATA7CH0_CR_RXTRAINRANK3_RxRcvEnPi_MAX (0x000001FF) + #define DDRDATA7CH0_CR_RXTRAINRANK3_RxDqsPPi_OFF ( 9) + #define DDRDATA7CH0_CR_RXTRAINRANK3_RxDqsPPi_WID ( 6) + #define DDRDATA7CH0_CR_RXTRAINRANK3_RxDqsPPi_MSK (0x00007E00) + #define DDRDATA7CH0_CR_RXTRAINRANK3_RxDqsPPi_MAX (0x0000003F) + #define DDRDATA7CH0_CR_RXTRAINRANK3_RxEq_OFF (15) + #define DDRDATA7CH0_CR_RXTRAINRANK3_RxEq_WID ( 5) + #define DDRDATA7CH0_CR_RXTRAINRANK3_RxEq_MSK (0x000F8000) + #define DDRDATA7CH0_CR_RXTRAINRANK3_RxEq_MAX (0x0000001F) + #define DDRDATA7CH0_CR_RXTRAINRANK3_RxDqsNPi_OFF (20) + #define DDRDATA7CH0_CR_RXTRAINRANK3_RxDqsNPi_WID ( 6) + #define DDRDATA7CH0_CR_RXTRAINRANK3_RxDqsNPi_MSK (0x03F00000) + #define DDRDATA7CH0_CR_RXTRAINRANK3_RxDqsNPi_MAX (0x0000003F) + #define DDRDATA7CH0_CR_RXTRAINRANK3_RxVref_OFF (26) + #define DDRDATA7CH0_CR_RXTRAINRANK3_RxVref_WID ( 6) + #define DDRDATA7CH0_CR_RXTRAINRANK3_RxVref_MSK (0xFC000000) + #define DDRDATA7CH0_CR_RXTRAINRANK3_RxVref_MAX (0x0000003F) + +#define DDRDATA7CH0_CR_RXPERBITRANK0_REG (0x00000E10) + #define DDRDATA7CH0_CR_RXPERBITRANK0_Lane0_OFF ( 0) + #define DDRDATA7CH0_CR_RXPERBITRANK0_Lane0_WID ( 4) + #define DDRDATA7CH0_CR_RXPERBITRANK0_Lane0_MSK (0x0000000F) + #define DDRDATA7CH0_CR_RXPERBITRANK0_Lane0_MAX (0x0000000F) + #define DDRDATA7CH0_CR_RXPERBITRANK0_Lane1_OFF ( 4) + #define DDRDATA7CH0_CR_RXPERBITRANK0_Lane1_WID ( 4) + #define DDRDATA7CH0_CR_RXPERBITRANK0_Lane1_MSK (0x000000F0) + #define DDRDATA7CH0_CR_RXPERBITRANK0_Lane1_MAX (0x0000000F) + #define DDRDATA7CH0_CR_RXPERBITRANK0_Lane2_OFF ( 8) + #define DDRDATA7CH0_CR_RXPERBITRANK0_Lane2_WID ( 4) + #define DDRDATA7CH0_CR_RXPERBITRANK0_Lane2_MSK (0x00000F00) + #define DDRDATA7CH0_CR_RXPERBITRANK0_Lane2_MAX (0x0000000F) + #define DDRDATA7CH0_CR_RXPERBITRANK0_Lane3_OFF (12) + #define DDRDATA7CH0_CR_RXPERBITRANK0_Lane3_WID ( 4) + #define DDRDATA7CH0_CR_RXPERBITRANK0_Lane3_MSK (0x0000F000) + #define DDRDATA7CH0_CR_RXPERBITRANK0_Lane3_MAX (0x0000000F) + #define DDRDATA7CH0_CR_RXPERBITRANK0_Lane4_OFF (16) + #define DDRDATA7CH0_CR_RXPERBITRANK0_Lane4_WID ( 4) + #define DDRDATA7CH0_CR_RXPERBITRANK0_Lane4_MSK (0x000F0000) + #define DDRDATA7CH0_CR_RXPERBITRANK0_Lane4_MAX (0x0000000F) + #define DDRDATA7CH0_CR_RXPERBITRANK0_Lane5_OFF (20) + #define DDRDATA7CH0_CR_RXPERBITRANK0_Lane5_WID ( 4) + #define DDRDATA7CH0_CR_RXPERBITRANK0_Lane5_MSK (0x00F00000) + #define DDRDATA7CH0_CR_RXPERBITRANK0_Lane5_MAX (0x0000000F) + #define DDRDATA7CH0_CR_RXPERBITRANK0_Lane6_OFF (24) + #define DDRDATA7CH0_CR_RXPERBITRANK0_Lane6_WID ( 4) + #define DDRDATA7CH0_CR_RXPERBITRANK0_Lane6_MSK (0x0F000000) + #define DDRDATA7CH0_CR_RXPERBITRANK0_Lane6_MAX (0x0000000F) + #define DDRDATA7CH0_CR_RXPERBITRANK0_Lane7_OFF (28) + #define DDRDATA7CH0_CR_RXPERBITRANK0_Lane7_WID ( 4) + #define DDRDATA7CH0_CR_RXPERBITRANK0_Lane7_MSK (0xF0000000) + #define DDRDATA7CH0_CR_RXPERBITRANK0_Lane7_MAX (0x0000000F) + +#define DDRDATA7CH0_CR_RXPERBITRANK1_REG (0x00000E14) + #define DDRDATA7CH0_CR_RXPERBITRANK1_Lane0_OFF ( 0) + #define DDRDATA7CH0_CR_RXPERBITRANK1_Lane0_WID ( 4) + #define DDRDATA7CH0_CR_RXPERBITRANK1_Lane0_MSK (0x0000000F) + #define DDRDATA7CH0_CR_RXPERBITRANK1_Lane0_MAX (0x0000000F) + #define DDRDATA7CH0_CR_RXPERBITRANK1_Lane1_OFF ( 4) + #define DDRDATA7CH0_CR_RXPERBITRANK1_Lane1_WID ( 4) + #define DDRDATA7CH0_CR_RXPERBITRANK1_Lane1_MSK (0x000000F0) + #define DDRDATA7CH0_CR_RXPERBITRANK1_Lane1_MAX (0x0000000F) + #define DDRDATA7CH0_CR_RXPERBITRANK1_Lane2_OFF ( 8) + #define DDRDATA7CH0_CR_RXPERBITRANK1_Lane2_WID ( 4) + #define DDRDATA7CH0_CR_RXPERBITRANK1_Lane2_MSK (0x00000F00) + #define DDRDATA7CH0_CR_RXPERBITRANK1_Lane2_MAX (0x0000000F) + #define DDRDATA7CH0_CR_RXPERBITRANK1_Lane3_OFF (12) + #define DDRDATA7CH0_CR_RXPERBITRANK1_Lane3_WID ( 4) + #define DDRDATA7CH0_CR_RXPERBITRANK1_Lane3_MSK (0x0000F000) + #define DDRDATA7CH0_CR_RXPERBITRANK1_Lane3_MAX (0x0000000F) + #define DDRDATA7CH0_CR_RXPERBITRANK1_Lane4_OFF (16) + #define DDRDATA7CH0_CR_RXPERBITRANK1_Lane4_WID ( 4) + #define DDRDATA7CH0_CR_RXPERBITRANK1_Lane4_MSK (0x000F0000) + #define DDRDATA7CH0_CR_RXPERBITRANK1_Lane4_MAX (0x0000000F) + #define DDRDATA7CH0_CR_RXPERBITRANK1_Lane5_OFF (20) + #define DDRDATA7CH0_CR_RXPERBITRANK1_Lane5_WID ( 4) + #define DDRDATA7CH0_CR_RXPERBITRANK1_Lane5_MSK (0x00F00000) + #define DDRDATA7CH0_CR_RXPERBITRANK1_Lane5_MAX (0x0000000F) + #define DDRDATA7CH0_CR_RXPERBITRANK1_Lane6_OFF (24) + #define DDRDATA7CH0_CR_RXPERBITRANK1_Lane6_WID ( 4) + #define DDRDATA7CH0_CR_RXPERBITRANK1_Lane6_MSK (0x0F000000) + #define DDRDATA7CH0_CR_RXPERBITRANK1_Lane6_MAX (0x0000000F) + #define DDRDATA7CH0_CR_RXPERBITRANK1_Lane7_OFF (28) + #define DDRDATA7CH0_CR_RXPERBITRANK1_Lane7_WID ( 4) + #define DDRDATA7CH0_CR_RXPERBITRANK1_Lane7_MSK (0xF0000000) + #define DDRDATA7CH0_CR_RXPERBITRANK1_Lane7_MAX (0x0000000F) + +#define DDRDATA7CH0_CR_RXPERBITRANK2_REG (0x00000E18) + #define DDRDATA7CH0_CR_RXPERBITRANK2_Lane0_OFF ( 0) + #define DDRDATA7CH0_CR_RXPERBITRANK2_Lane0_WID ( 4) + #define DDRDATA7CH0_CR_RXPERBITRANK2_Lane0_MSK (0x0000000F) + #define DDRDATA7CH0_CR_RXPERBITRANK2_Lane0_MAX (0x0000000F) + #define DDRDATA7CH0_CR_RXPERBITRANK2_Lane1_OFF ( 4) + #define DDRDATA7CH0_CR_RXPERBITRANK2_Lane1_WID ( 4) + #define DDRDATA7CH0_CR_RXPERBITRANK2_Lane1_MSK (0x000000F0) + #define DDRDATA7CH0_CR_RXPERBITRANK2_Lane1_MAX (0x0000000F) + #define DDRDATA7CH0_CR_RXPERBITRANK2_Lane2_OFF ( 8) + #define DDRDATA7CH0_CR_RXPERBITRANK2_Lane2_WID ( 4) + #define DDRDATA7CH0_CR_RXPERBITRANK2_Lane2_MSK (0x00000F00) + #define DDRDATA7CH0_CR_RXPERBITRANK2_Lane2_MAX (0x0000000F) + #define DDRDATA7CH0_CR_RXPERBITRANK2_Lane3_OFF (12) + #define DDRDATA7CH0_CR_RXPERBITRANK2_Lane3_WID ( 4) + #define DDRDATA7CH0_CR_RXPERBITRANK2_Lane3_MSK (0x0000F000) + #define DDRDATA7CH0_CR_RXPERBITRANK2_Lane3_MAX (0x0000000F) + #define DDRDATA7CH0_CR_RXPERBITRANK2_Lane4_OFF (16) + #define DDRDATA7CH0_CR_RXPERBITRANK2_Lane4_WID ( 4) + #define DDRDATA7CH0_CR_RXPERBITRANK2_Lane4_MSK (0x000F0000) + #define DDRDATA7CH0_CR_RXPERBITRANK2_Lane4_MAX (0x0000000F) + #define DDRDATA7CH0_CR_RXPERBITRANK2_Lane5_OFF (20) + #define DDRDATA7CH0_CR_RXPERBITRANK2_Lane5_WID ( 4) + #define DDRDATA7CH0_CR_RXPERBITRANK2_Lane5_MSK (0x00F00000) + #define DDRDATA7CH0_CR_RXPERBITRANK2_Lane5_MAX (0x0000000F) + #define DDRDATA7CH0_CR_RXPERBITRANK2_Lane6_OFF (24) + #define DDRDATA7CH0_CR_RXPERBITRANK2_Lane6_WID ( 4) + #define DDRDATA7CH0_CR_RXPERBITRANK2_Lane6_MSK (0x0F000000) + #define DDRDATA7CH0_CR_RXPERBITRANK2_Lane6_MAX (0x0000000F) + #define DDRDATA7CH0_CR_RXPERBITRANK2_Lane7_OFF (28) + #define DDRDATA7CH0_CR_RXPERBITRANK2_Lane7_WID ( 4) + #define DDRDATA7CH0_CR_RXPERBITRANK2_Lane7_MSK (0xF0000000) + #define DDRDATA7CH0_CR_RXPERBITRANK2_Lane7_MAX (0x0000000F) + +#define DDRDATA7CH0_CR_RXPERBITRANK3_REG (0x00000E1C) + #define DDRDATA7CH0_CR_RXPERBITRANK3_Lane0_OFF ( 0) + #define DDRDATA7CH0_CR_RXPERBITRANK3_Lane0_WID ( 4) + #define DDRDATA7CH0_CR_RXPERBITRANK3_Lane0_MSK (0x0000000F) + #define DDRDATA7CH0_CR_RXPERBITRANK3_Lane0_MAX (0x0000000F) + #define DDRDATA7CH0_CR_RXPERBITRANK3_Lane1_OFF ( 4) + #define DDRDATA7CH0_CR_RXPERBITRANK3_Lane1_WID ( 4) + #define DDRDATA7CH0_CR_RXPERBITRANK3_Lane1_MSK (0x000000F0) + #define DDRDATA7CH0_CR_RXPERBITRANK3_Lane1_MAX (0x0000000F) + #define DDRDATA7CH0_CR_RXPERBITRANK3_Lane2_OFF ( 8) + #define DDRDATA7CH0_CR_RXPERBITRANK3_Lane2_WID ( 4) + #define DDRDATA7CH0_CR_RXPERBITRANK3_Lane2_MSK (0x00000F00) + #define DDRDATA7CH0_CR_RXPERBITRANK3_Lane2_MAX (0x0000000F) + #define DDRDATA7CH0_CR_RXPERBITRANK3_Lane3_OFF (12) + #define DDRDATA7CH0_CR_RXPERBITRANK3_Lane3_WID ( 4) + #define DDRDATA7CH0_CR_RXPERBITRANK3_Lane3_MSK (0x0000F000) + #define DDRDATA7CH0_CR_RXPERBITRANK3_Lane3_MAX (0x0000000F) + #define DDRDATA7CH0_CR_RXPERBITRANK3_Lane4_OFF (16) + #define DDRDATA7CH0_CR_RXPERBITRANK3_Lane4_WID ( 4) + #define DDRDATA7CH0_CR_RXPERBITRANK3_Lane4_MSK (0x000F0000) + #define DDRDATA7CH0_CR_RXPERBITRANK3_Lane4_MAX (0x0000000F) + #define DDRDATA7CH0_CR_RXPERBITRANK3_Lane5_OFF (20) + #define DDRDATA7CH0_CR_RXPERBITRANK3_Lane5_WID ( 4) + #define DDRDATA7CH0_CR_RXPERBITRANK3_Lane5_MSK (0x00F00000) + #define DDRDATA7CH0_CR_RXPERBITRANK3_Lane5_MAX (0x0000000F) + #define DDRDATA7CH0_CR_RXPERBITRANK3_Lane6_OFF (24) + #define DDRDATA7CH0_CR_RXPERBITRANK3_Lane6_WID ( 4) + #define DDRDATA7CH0_CR_RXPERBITRANK3_Lane6_MSK (0x0F000000) + #define DDRDATA7CH0_CR_RXPERBITRANK3_Lane6_MAX (0x0000000F) + #define DDRDATA7CH0_CR_RXPERBITRANK3_Lane7_OFF (28) + #define DDRDATA7CH0_CR_RXPERBITRANK3_Lane7_WID ( 4) + #define DDRDATA7CH0_CR_RXPERBITRANK3_Lane7_MSK (0xF0000000) + #define DDRDATA7CH0_CR_RXPERBITRANK3_Lane7_MAX (0x0000000F) + +#define DDRDATA7CH0_CR_TXTRAINRANK0_REG (0x00000E20) + #define DDRDATA7CH0_CR_TXTRAINRANK0_TxDqDelay_OFF ( 0) + #define DDRDATA7CH0_CR_TXTRAINRANK0_TxDqDelay_WID ( 9) + #define DDRDATA7CH0_CR_TXTRAINRANK0_TxDqDelay_MSK (0x000001FF) + #define DDRDATA7CH0_CR_TXTRAINRANK0_TxDqDelay_MAX (0x000001FF) + #define DDRDATA7CH0_CR_TXTRAINRANK0_TxDqsDelay_OFF ( 9) + #define DDRDATA7CH0_CR_TXTRAINRANK0_TxDqsDelay_WID ( 9) + #define DDRDATA7CH0_CR_TXTRAINRANK0_TxDqsDelay_MSK (0x0003FE00) + #define DDRDATA7CH0_CR_TXTRAINRANK0_TxDqsDelay_MAX (0x000001FF) + #define DDRDATA7CH0_CR_TXTRAINRANK0_Spare0_OFF (18) + #define DDRDATA7CH0_CR_TXTRAINRANK0_Spare0_WID ( 2) + #define DDRDATA7CH0_CR_TXTRAINRANK0_Spare0_MSK (0x000C0000) + #define DDRDATA7CH0_CR_TXTRAINRANK0_Spare0_MAX (0x00000003) + #define DDRDATA7CH0_CR_TXTRAINRANK0_TxEqualization_OFF (20) + #define DDRDATA7CH0_CR_TXTRAINRANK0_TxEqualization_WID ( 6) + #define DDRDATA7CH0_CR_TXTRAINRANK0_TxEqualization_MSK (0x03F00000) + #define DDRDATA7CH0_CR_TXTRAINRANK0_TxEqualization_MAX (0x0000003F) + #define DDRDATA7CH0_CR_TXTRAINRANK0_Spare1_OFF (26) + #define DDRDATA7CH0_CR_TXTRAINRANK0_Spare1_WID ( 6) + #define DDRDATA7CH0_CR_TXTRAINRANK0_Spare1_MSK (0xFC000000) + #define DDRDATA7CH0_CR_TXTRAINRANK0_Spare1_MAX (0x0000003F) + +#define DDRDATA7CH0_CR_TXTRAINRANK1_REG (0x00000E24) + #define DDRDATA7CH0_CR_TXTRAINRANK1_TxDqDelay_OFF ( 0) + #define DDRDATA7CH0_CR_TXTRAINRANK1_TxDqDelay_WID ( 9) + #define DDRDATA7CH0_CR_TXTRAINRANK1_TxDqDelay_MSK (0x000001FF) + #define DDRDATA7CH0_CR_TXTRAINRANK1_TxDqDelay_MAX (0x000001FF) + #define DDRDATA7CH0_CR_TXTRAINRANK1_TxDqsDelay_OFF ( 9) + #define DDRDATA7CH0_CR_TXTRAINRANK1_TxDqsDelay_WID ( 9) + #define DDRDATA7CH0_CR_TXTRAINRANK1_TxDqsDelay_MSK (0x0003FE00) + #define DDRDATA7CH0_CR_TXTRAINRANK1_TxDqsDelay_MAX (0x000001FF) + #define DDRDATA7CH0_CR_TXTRAINRANK1_Spare0_OFF (18) + #define DDRDATA7CH0_CR_TXTRAINRANK1_Spare0_WID ( 2) + #define DDRDATA7CH0_CR_TXTRAINRANK1_Spare0_MSK (0x000C0000) + #define DDRDATA7CH0_CR_TXTRAINRANK1_Spare0_MAX (0x00000003) + #define DDRDATA7CH0_CR_TXTRAINRANK1_TxEqualization_OFF (20) + #define DDRDATA7CH0_CR_TXTRAINRANK1_TxEqualization_WID ( 6) + #define DDRDATA7CH0_CR_TXTRAINRANK1_TxEqualization_MSK (0x03F00000) + #define DDRDATA7CH0_CR_TXTRAINRANK1_TxEqualization_MAX (0x0000003F) + #define DDRDATA7CH0_CR_TXTRAINRANK1_Spare1_OFF (26) + #define DDRDATA7CH0_CR_TXTRAINRANK1_Spare1_WID ( 6) + #define DDRDATA7CH0_CR_TXTRAINRANK1_Spare1_MSK (0xFC000000) + #define DDRDATA7CH0_CR_TXTRAINRANK1_Spare1_MAX (0x0000003F) + +#define DDRDATA7CH0_CR_TXTRAINRANK2_REG (0x00000E28) + #define DDRDATA7CH0_CR_TXTRAINRANK2_TxDqDelay_OFF ( 0) + #define DDRDATA7CH0_CR_TXTRAINRANK2_TxDqDelay_WID ( 9) + #define DDRDATA7CH0_CR_TXTRAINRANK2_TxDqDelay_MSK (0x000001FF) + #define DDRDATA7CH0_CR_TXTRAINRANK2_TxDqDelay_MAX (0x000001FF) + #define DDRDATA7CH0_CR_TXTRAINRANK2_TxDqsDelay_OFF ( 9) + #define DDRDATA7CH0_CR_TXTRAINRANK2_TxDqsDelay_WID ( 9) + #define DDRDATA7CH0_CR_TXTRAINRANK2_TxDqsDelay_MSK (0x0003FE00) + #define DDRDATA7CH0_CR_TXTRAINRANK2_TxDqsDelay_MAX (0x000001FF) + #define DDRDATA7CH0_CR_TXTRAINRANK2_Spare0_OFF (18) + #define DDRDATA7CH0_CR_TXTRAINRANK2_Spare0_WID ( 2) + #define DDRDATA7CH0_CR_TXTRAINRANK2_Spare0_MSK (0x000C0000) + #define DDRDATA7CH0_CR_TXTRAINRANK2_Spare0_MAX (0x00000003) + #define DDRDATA7CH0_CR_TXTRAINRANK2_TxEqualization_OFF (20) + #define DDRDATA7CH0_CR_TXTRAINRANK2_TxEqualization_WID ( 6) + #define DDRDATA7CH0_CR_TXTRAINRANK2_TxEqualization_MSK (0x03F00000) + #define DDRDATA7CH0_CR_TXTRAINRANK2_TxEqualization_MAX (0x0000003F) + #define DDRDATA7CH0_CR_TXTRAINRANK2_Spare1_OFF (26) + #define DDRDATA7CH0_CR_TXTRAINRANK2_Spare1_WID ( 6) + #define DDRDATA7CH0_CR_TXTRAINRANK2_Spare1_MSK (0xFC000000) + #define DDRDATA7CH0_CR_TXTRAINRANK2_Spare1_MAX (0x0000003F) + +#define DDRDATA7CH0_CR_TXTRAINRANK3_REG (0x00000E2C) + #define DDRDATA7CH0_CR_TXTRAINRANK3_TxDqDelay_OFF ( 0) + #define DDRDATA7CH0_CR_TXTRAINRANK3_TxDqDelay_WID ( 9) + #define DDRDATA7CH0_CR_TXTRAINRANK3_TxDqDelay_MSK (0x000001FF) + #define DDRDATA7CH0_CR_TXTRAINRANK3_TxDqDelay_MAX (0x000001FF) + #define DDRDATA7CH0_CR_TXTRAINRANK3_TxDqsDelay_OFF ( 9) + #define DDRDATA7CH0_CR_TXTRAINRANK3_TxDqsDelay_WID ( 9) + #define DDRDATA7CH0_CR_TXTRAINRANK3_TxDqsDelay_MSK (0x0003FE00) + #define DDRDATA7CH0_CR_TXTRAINRANK3_TxDqsDelay_MAX (0x000001FF) + #define DDRDATA7CH0_CR_TXTRAINRANK3_Spare0_OFF (18) + #define DDRDATA7CH0_CR_TXTRAINRANK3_Spare0_WID ( 2) + #define DDRDATA7CH0_CR_TXTRAINRANK3_Spare0_MSK (0x000C0000) + #define DDRDATA7CH0_CR_TXTRAINRANK3_Spare0_MAX (0x00000003) + #define DDRDATA7CH0_CR_TXTRAINRANK3_TxEqualization_OFF (20) + #define DDRDATA7CH0_CR_TXTRAINRANK3_TxEqualization_WID ( 6) + #define DDRDATA7CH0_CR_TXTRAINRANK3_TxEqualization_MSK (0x03F00000) + #define DDRDATA7CH0_CR_TXTRAINRANK3_TxEqualization_MAX (0x0000003F) + #define DDRDATA7CH0_CR_TXTRAINRANK3_Spare1_OFF (26) + #define DDRDATA7CH0_CR_TXTRAINRANK3_Spare1_WID ( 6) + #define DDRDATA7CH0_CR_TXTRAINRANK3_Spare1_MSK (0xFC000000) + #define DDRDATA7CH0_CR_TXTRAINRANK3_Spare1_MAX (0x0000003F) + +#define DDRDATA7CH0_CR_TXPERBITRANK0_REG (0x00000E30) + #define DDRDATA7CH0_CR_TXPERBITRANK0_Lane0_OFF ( 0) + #define DDRDATA7CH0_CR_TXPERBITRANK0_Lane0_WID ( 4) + #define DDRDATA7CH0_CR_TXPERBITRANK0_Lane0_MSK (0x0000000F) + #define DDRDATA7CH0_CR_TXPERBITRANK0_Lane0_MAX (0x0000000F) + #define DDRDATA7CH0_CR_TXPERBITRANK0_Lane1_OFF ( 4) + #define DDRDATA7CH0_CR_TXPERBITRANK0_Lane1_WID ( 4) + #define DDRDATA7CH0_CR_TXPERBITRANK0_Lane1_MSK (0x000000F0) + #define DDRDATA7CH0_CR_TXPERBITRANK0_Lane1_MAX (0x0000000F) + #define DDRDATA7CH0_CR_TXPERBITRANK0_Lane2_OFF ( 8) + #define DDRDATA7CH0_CR_TXPERBITRANK0_Lane2_WID ( 4) + #define DDRDATA7CH0_CR_TXPERBITRANK0_Lane2_MSK (0x00000F00) + #define DDRDATA7CH0_CR_TXPERBITRANK0_Lane2_MAX (0x0000000F) + #define DDRDATA7CH0_CR_TXPERBITRANK0_Lane3_OFF (12) + #define DDRDATA7CH0_CR_TXPERBITRANK0_Lane3_WID ( 4) + #define DDRDATA7CH0_CR_TXPERBITRANK0_Lane3_MSK (0x0000F000) + #define DDRDATA7CH0_CR_TXPERBITRANK0_Lane3_MAX (0x0000000F) + #define DDRDATA7CH0_CR_TXPERBITRANK0_Lane4_OFF (16) + #define DDRDATA7CH0_CR_TXPERBITRANK0_Lane4_WID ( 4) + #define DDRDATA7CH0_CR_TXPERBITRANK0_Lane4_MSK (0x000F0000) + #define DDRDATA7CH0_CR_TXPERBITRANK0_Lane4_MAX (0x0000000F) + #define DDRDATA7CH0_CR_TXPERBITRANK0_Lane5_OFF (20) + #define DDRDATA7CH0_CR_TXPERBITRANK0_Lane5_WID ( 4) + #define DDRDATA7CH0_CR_TXPERBITRANK0_Lane5_MSK (0x00F00000) + #define DDRDATA7CH0_CR_TXPERBITRANK0_Lane5_MAX (0x0000000F) + #define DDRDATA7CH0_CR_TXPERBITRANK0_Lane6_OFF (24) + #define DDRDATA7CH0_CR_TXPERBITRANK0_Lane6_WID ( 4) + #define DDRDATA7CH0_CR_TXPERBITRANK0_Lane6_MSK (0x0F000000) + #define DDRDATA7CH0_CR_TXPERBITRANK0_Lane6_MAX (0x0000000F) + #define DDRDATA7CH0_CR_TXPERBITRANK0_Lane7_OFF (28) + #define DDRDATA7CH0_CR_TXPERBITRANK0_Lane7_WID ( 4) + #define DDRDATA7CH0_CR_TXPERBITRANK0_Lane7_MSK (0xF0000000) + #define DDRDATA7CH0_CR_TXPERBITRANK0_Lane7_MAX (0x0000000F) + +#define DDRDATA7CH0_CR_TXPERBITRANK1_REG (0x00000E34) + #define DDRDATA7CH0_CR_TXPERBITRANK1_Lane0_OFF ( 0) + #define DDRDATA7CH0_CR_TXPERBITRANK1_Lane0_WID ( 4) + #define DDRDATA7CH0_CR_TXPERBITRANK1_Lane0_MSK (0x0000000F) + #define DDRDATA7CH0_CR_TXPERBITRANK1_Lane0_MAX (0x0000000F) + #define DDRDATA7CH0_CR_TXPERBITRANK1_Lane1_OFF ( 4) + #define DDRDATA7CH0_CR_TXPERBITRANK1_Lane1_WID ( 4) + #define DDRDATA7CH0_CR_TXPERBITRANK1_Lane1_MSK (0x000000F0) + #define DDRDATA7CH0_CR_TXPERBITRANK1_Lane1_MAX (0x0000000F) + #define DDRDATA7CH0_CR_TXPERBITRANK1_Lane2_OFF ( 8) + #define DDRDATA7CH0_CR_TXPERBITRANK1_Lane2_WID ( 4) + #define DDRDATA7CH0_CR_TXPERBITRANK1_Lane2_MSK (0x00000F00) + #define DDRDATA7CH0_CR_TXPERBITRANK1_Lane2_MAX (0x0000000F) + #define DDRDATA7CH0_CR_TXPERBITRANK1_Lane3_OFF (12) + #define DDRDATA7CH0_CR_TXPERBITRANK1_Lane3_WID ( 4) + #define DDRDATA7CH0_CR_TXPERBITRANK1_Lane3_MSK (0x0000F000) + #define DDRDATA7CH0_CR_TXPERBITRANK1_Lane3_MAX (0x0000000F) + #define DDRDATA7CH0_CR_TXPERBITRANK1_Lane4_OFF (16) + #define DDRDATA7CH0_CR_TXPERBITRANK1_Lane4_WID ( 4) + #define DDRDATA7CH0_CR_TXPERBITRANK1_Lane4_MSK (0x000F0000) + #define DDRDATA7CH0_CR_TXPERBITRANK1_Lane4_MAX (0x0000000F) + #define DDRDATA7CH0_CR_TXPERBITRANK1_Lane5_OFF (20) + #define DDRDATA7CH0_CR_TXPERBITRANK1_Lane5_WID ( 4) + #define DDRDATA7CH0_CR_TXPERBITRANK1_Lane5_MSK (0x00F00000) + #define DDRDATA7CH0_CR_TXPERBITRANK1_Lane5_MAX (0x0000000F) + #define DDRDATA7CH0_CR_TXPERBITRANK1_Lane6_OFF (24) + #define DDRDATA7CH0_CR_TXPERBITRANK1_Lane6_WID ( 4) + #define DDRDATA7CH0_CR_TXPERBITRANK1_Lane6_MSK (0x0F000000) + #define DDRDATA7CH0_CR_TXPERBITRANK1_Lane6_MAX (0x0000000F) + #define DDRDATA7CH0_CR_TXPERBITRANK1_Lane7_OFF (28) + #define DDRDATA7CH0_CR_TXPERBITRANK1_Lane7_WID ( 4) + #define DDRDATA7CH0_CR_TXPERBITRANK1_Lane7_MSK (0xF0000000) + #define DDRDATA7CH0_CR_TXPERBITRANK1_Lane7_MAX (0x0000000F) + +#define DDRDATA7CH0_CR_TXPERBITRANK2_REG (0x00000E38) + #define DDRDATA7CH0_CR_TXPERBITRANK2_Lane0_OFF ( 0) + #define DDRDATA7CH0_CR_TXPERBITRANK2_Lane0_WID ( 4) + #define DDRDATA7CH0_CR_TXPERBITRANK2_Lane0_MSK (0x0000000F) + #define DDRDATA7CH0_CR_TXPERBITRANK2_Lane0_MAX (0x0000000F) + #define DDRDATA7CH0_CR_TXPERBITRANK2_Lane1_OFF ( 4) + #define DDRDATA7CH0_CR_TXPERBITRANK2_Lane1_WID ( 4) + #define DDRDATA7CH0_CR_TXPERBITRANK2_Lane1_MSK (0x000000F0) + #define DDRDATA7CH0_CR_TXPERBITRANK2_Lane1_MAX (0x0000000F) + #define DDRDATA7CH0_CR_TXPERBITRANK2_Lane2_OFF ( 8) + #define DDRDATA7CH0_CR_TXPERBITRANK2_Lane2_WID ( 4) + #define DDRDATA7CH0_CR_TXPERBITRANK2_Lane2_MSK (0x00000F00) + #define DDRDATA7CH0_CR_TXPERBITRANK2_Lane2_MAX (0x0000000F) + #define DDRDATA7CH0_CR_TXPERBITRANK2_Lane3_OFF (12) + #define DDRDATA7CH0_CR_TXPERBITRANK2_Lane3_WID ( 4) + #define DDRDATA7CH0_CR_TXPERBITRANK2_Lane3_MSK (0x0000F000) + #define DDRDATA7CH0_CR_TXPERBITRANK2_Lane3_MAX (0x0000000F) + #define DDRDATA7CH0_CR_TXPERBITRANK2_Lane4_OFF (16) + #define DDRDATA7CH0_CR_TXPERBITRANK2_Lane4_WID ( 4) + #define DDRDATA7CH0_CR_TXPERBITRANK2_Lane4_MSK (0x000F0000) + #define DDRDATA7CH0_CR_TXPERBITRANK2_Lane4_MAX (0x0000000F) + #define DDRDATA7CH0_CR_TXPERBITRANK2_Lane5_OFF (20) + #define DDRDATA7CH0_CR_TXPERBITRANK2_Lane5_WID ( 4) + #define DDRDATA7CH0_CR_TXPERBITRANK2_Lane5_MSK (0x00F00000) + #define DDRDATA7CH0_CR_TXPERBITRANK2_Lane5_MAX (0x0000000F) + #define DDRDATA7CH0_CR_TXPERBITRANK2_Lane6_OFF (24) + #define DDRDATA7CH0_CR_TXPERBITRANK2_Lane6_WID ( 4) + #define DDRDATA7CH0_CR_TXPERBITRANK2_Lane6_MSK (0x0F000000) + #define DDRDATA7CH0_CR_TXPERBITRANK2_Lane6_MAX (0x0000000F) + #define DDRDATA7CH0_CR_TXPERBITRANK2_Lane7_OFF (28) + #define DDRDATA7CH0_CR_TXPERBITRANK2_Lane7_WID ( 4) + #define DDRDATA7CH0_CR_TXPERBITRANK2_Lane7_MSK (0xF0000000) + #define DDRDATA7CH0_CR_TXPERBITRANK2_Lane7_MAX (0x0000000F) + +#define DDRDATA7CH0_CR_TXPERBITRANK3_REG (0x00000E3C) + #define DDRDATA7CH0_CR_TXPERBITRANK3_Lane0_OFF ( 0) + #define DDRDATA7CH0_CR_TXPERBITRANK3_Lane0_WID ( 4) + #define DDRDATA7CH0_CR_TXPERBITRANK3_Lane0_MSK (0x0000000F) + #define DDRDATA7CH0_CR_TXPERBITRANK3_Lane0_MAX (0x0000000F) + #define DDRDATA7CH0_CR_TXPERBITRANK3_Lane1_OFF ( 4) + #define DDRDATA7CH0_CR_TXPERBITRANK3_Lane1_WID ( 4) + #define DDRDATA7CH0_CR_TXPERBITRANK3_Lane1_MSK (0x000000F0) + #define DDRDATA7CH0_CR_TXPERBITRANK3_Lane1_MAX (0x0000000F) + #define DDRDATA7CH0_CR_TXPERBITRANK3_Lane2_OFF ( 8) + #define DDRDATA7CH0_CR_TXPERBITRANK3_Lane2_WID ( 4) + #define DDRDATA7CH0_CR_TXPERBITRANK3_Lane2_MSK (0x00000F00) + #define DDRDATA7CH0_CR_TXPERBITRANK3_Lane2_MAX (0x0000000F) + #define DDRDATA7CH0_CR_TXPERBITRANK3_Lane3_OFF (12) + #define DDRDATA7CH0_CR_TXPERBITRANK3_Lane3_WID ( 4) + #define DDRDATA7CH0_CR_TXPERBITRANK3_Lane3_MSK (0x0000F000) + #define DDRDATA7CH0_CR_TXPERBITRANK3_Lane3_MAX (0x0000000F) + #define DDRDATA7CH0_CR_TXPERBITRANK3_Lane4_OFF (16) + #define DDRDATA7CH0_CR_TXPERBITRANK3_Lane4_WID ( 4) + #define DDRDATA7CH0_CR_TXPERBITRANK3_Lane4_MSK (0x000F0000) + #define DDRDATA7CH0_CR_TXPERBITRANK3_Lane4_MAX (0x0000000F) + #define DDRDATA7CH0_CR_TXPERBITRANK3_Lane5_OFF (20) + #define DDRDATA7CH0_CR_TXPERBITRANK3_Lane5_WID ( 4) + #define DDRDATA7CH0_CR_TXPERBITRANK3_Lane5_MSK (0x00F00000) + #define DDRDATA7CH0_CR_TXPERBITRANK3_Lane5_MAX (0x0000000F) + #define DDRDATA7CH0_CR_TXPERBITRANK3_Lane6_OFF (24) + #define DDRDATA7CH0_CR_TXPERBITRANK3_Lane6_WID ( 4) + #define DDRDATA7CH0_CR_TXPERBITRANK3_Lane6_MSK (0x0F000000) + #define DDRDATA7CH0_CR_TXPERBITRANK3_Lane6_MAX (0x0000000F) + #define DDRDATA7CH0_CR_TXPERBITRANK3_Lane7_OFF (28) + #define DDRDATA7CH0_CR_TXPERBITRANK3_Lane7_WID ( 4) + #define DDRDATA7CH0_CR_TXPERBITRANK3_Lane7_MSK (0xF0000000) + #define DDRDATA7CH0_CR_TXPERBITRANK3_Lane7_MAX (0x0000000F) + +#define DDRDATA7CH0_CR_RCOMPDATA0_REG (0x00000E40) + #define DDRDATA7CH0_CR_RCOMPDATA0_RcompDrvUp_OFF ( 0) + #define DDRDATA7CH0_CR_RCOMPDATA0_RcompDrvUp_WID ( 6) + #define DDRDATA7CH0_CR_RCOMPDATA0_RcompDrvUp_MSK (0x0000003F) + #define DDRDATA7CH0_CR_RCOMPDATA0_RcompDrvUp_MAX (0x0000003F) + #define DDRDATA7CH0_CR_RCOMPDATA0_Spare0_OFF ( 6) + #define DDRDATA7CH0_CR_RCOMPDATA0_Spare0_WID ( 3) + #define DDRDATA7CH0_CR_RCOMPDATA0_Spare0_MSK (0x000001C0) + #define DDRDATA7CH0_CR_RCOMPDATA0_Spare0_MAX (0x00000007) + #define DDRDATA7CH0_CR_RCOMPDATA0_RcompDrvDown_OFF ( 9) + #define DDRDATA7CH0_CR_RCOMPDATA0_RcompDrvDown_WID ( 6) + #define DDRDATA7CH0_CR_RCOMPDATA0_RcompDrvDown_MSK (0x00007E00) + #define DDRDATA7CH0_CR_RCOMPDATA0_RcompDrvDown_MAX (0x0000003F) + #define DDRDATA7CH0_CR_RCOMPDATA0_VTComp_OFF (15) + #define DDRDATA7CH0_CR_RCOMPDATA0_VTComp_WID ( 5) + #define DDRDATA7CH0_CR_RCOMPDATA0_VTComp_MSK (0x000F8000) + #define DDRDATA7CH0_CR_RCOMPDATA0_VTComp_MAX (0x0000001F) + #define DDRDATA7CH0_CR_RCOMPDATA0_TcoComp_OFF (20) + #define DDRDATA7CH0_CR_RCOMPDATA0_TcoComp_WID ( 6) + #define DDRDATA7CH0_CR_RCOMPDATA0_TcoComp_MSK (0x03F00000) + #define DDRDATA7CH0_CR_RCOMPDATA0_TcoComp_MAX (0x0000003F) + #define DDRDATA7CH0_CR_RCOMPDATA0_SlewRateComp_OFF (26) + #define DDRDATA7CH0_CR_RCOMPDATA0_SlewRateComp_WID ( 5) + #define DDRDATA7CH0_CR_RCOMPDATA0_SlewRateComp_MSK (0x7C000000) + #define DDRDATA7CH0_CR_RCOMPDATA0_SlewRateComp_MAX (0x0000001F) + #define DDRDATA7CH0_CR_RCOMPDATA0_Spare2_OFF (31) + #define DDRDATA7CH0_CR_RCOMPDATA0_Spare2_WID ( 1) + #define DDRDATA7CH0_CR_RCOMPDATA0_Spare2_MSK (0x80000000) + #define DDRDATA7CH0_CR_RCOMPDATA0_Spare2_MAX (0x00000001) + +#define DDRDATA7CH0_CR_RCOMPDATA1_REG (0x00000E44) + #define DDRDATA7CH0_CR_RCOMPDATA1_RcompOdtUp_OFF ( 0) + #define DDRDATA7CH0_CR_RCOMPDATA1_RcompOdtUp_WID ( 6) + #define DDRDATA7CH0_CR_RCOMPDATA1_RcompOdtUp_MSK (0x0000003F) + #define DDRDATA7CH0_CR_RCOMPDATA1_RcompOdtUp_MAX (0x0000003F) + #define DDRDATA7CH0_CR_RCOMPDATA1_Spare0_OFF ( 6) + #define DDRDATA7CH0_CR_RCOMPDATA1_Spare0_WID ( 3) + #define DDRDATA7CH0_CR_RCOMPDATA1_Spare0_MSK (0x000001C0) + #define DDRDATA7CH0_CR_RCOMPDATA1_Spare0_MAX (0x00000007) + #define DDRDATA7CH0_CR_RCOMPDATA1_RcompOdtDown_OFF ( 9) + #define DDRDATA7CH0_CR_RCOMPDATA1_RcompOdtDown_WID ( 6) + #define DDRDATA7CH0_CR_RCOMPDATA1_RcompOdtDown_MSK (0x00007E00) + #define DDRDATA7CH0_CR_RCOMPDATA1_RcompOdtDown_MAX (0x0000003F) + #define DDRDATA7CH0_CR_RCOMPDATA1_Spare1_OFF (15) + #define DDRDATA7CH0_CR_RCOMPDATA1_Spare1_WID ( 1) + #define DDRDATA7CH0_CR_RCOMPDATA1_Spare1_MSK (0x00008000) + #define DDRDATA7CH0_CR_RCOMPDATA1_Spare1_MAX (0x00000001) + #define DDRDATA7CH0_CR_RCOMPDATA1_PanicDrvDn_OFF (16) + #define DDRDATA7CH0_CR_RCOMPDATA1_PanicDrvDn_WID ( 6) + #define DDRDATA7CH0_CR_RCOMPDATA1_PanicDrvDn_MSK (0x003F0000) + #define DDRDATA7CH0_CR_RCOMPDATA1_PanicDrvDn_MAX (0x0000003F) + #define DDRDATA7CH0_CR_RCOMPDATA1_PanicDrvUp_OFF (22) + #define DDRDATA7CH0_CR_RCOMPDATA1_PanicDrvUp_WID ( 6) + #define DDRDATA7CH0_CR_RCOMPDATA1_PanicDrvUp_MSK (0x0FC00000) + #define DDRDATA7CH0_CR_RCOMPDATA1_PanicDrvUp_MAX (0x0000003F) + #define DDRDATA7CH0_CR_RCOMPDATA1_LevelShifterComp_OFF (28) + #define DDRDATA7CH0_CR_RCOMPDATA1_LevelShifterComp_WID ( 3) + #define DDRDATA7CH0_CR_RCOMPDATA1_LevelShifterComp_MSK (0x70000000) + #define DDRDATA7CH0_CR_RCOMPDATA1_LevelShifterComp_MAX (0x00000007) + #define DDRDATA7CH0_CR_RCOMPDATA1_Spare2_OFF (31) + #define DDRDATA7CH0_CR_RCOMPDATA1_Spare2_WID ( 1) + #define DDRDATA7CH0_CR_RCOMPDATA1_Spare2_MSK (0x80000000) + #define DDRDATA7CH0_CR_RCOMPDATA1_Spare2_MAX (0x00000001) + +#define DDRDATA7CH0_CR_TXXTALK_REG (0x00000E48) + #define DDRDATA7CH0_CR_TXXTALK_Lane0_OFF ( 0) + #define DDRDATA7CH0_CR_TXXTALK_Lane0_WID ( 4) + #define DDRDATA7CH0_CR_TXXTALK_Lane0_MSK (0x0000000F) + #define DDRDATA7CH0_CR_TXXTALK_Lane0_MAX (0x0000000F) + #define DDRDATA7CH0_CR_TXXTALK_Lane1_OFF ( 4) + #define DDRDATA7CH0_CR_TXXTALK_Lane1_WID ( 4) + #define DDRDATA7CH0_CR_TXXTALK_Lane1_MSK (0x000000F0) + #define DDRDATA7CH0_CR_TXXTALK_Lane1_MAX (0x0000000F) + #define DDRDATA7CH0_CR_TXXTALK_Lane2_OFF ( 8) + #define DDRDATA7CH0_CR_TXXTALK_Lane2_WID ( 4) + #define DDRDATA7CH0_CR_TXXTALK_Lane2_MSK (0x00000F00) + #define DDRDATA7CH0_CR_TXXTALK_Lane2_MAX (0x0000000F) + #define DDRDATA7CH0_CR_TXXTALK_Lane3_OFF (12) + #define DDRDATA7CH0_CR_TXXTALK_Lane3_WID ( 4) + #define DDRDATA7CH0_CR_TXXTALK_Lane3_MSK (0x0000F000) + #define DDRDATA7CH0_CR_TXXTALK_Lane3_MAX (0x0000000F) + #define DDRDATA7CH0_CR_TXXTALK_Lane4_OFF (16) + #define DDRDATA7CH0_CR_TXXTALK_Lane4_WID ( 4) + #define DDRDATA7CH0_CR_TXXTALK_Lane4_MSK (0x000F0000) + #define DDRDATA7CH0_CR_TXXTALK_Lane4_MAX (0x0000000F) + #define DDRDATA7CH0_CR_TXXTALK_Lane5_OFF (20) + #define DDRDATA7CH0_CR_TXXTALK_Lane5_WID ( 4) + #define DDRDATA7CH0_CR_TXXTALK_Lane5_MSK (0x00F00000) + #define DDRDATA7CH0_CR_TXXTALK_Lane5_MAX (0x0000000F) + #define DDRDATA7CH0_CR_TXXTALK_Lane6_OFF (24) + #define DDRDATA7CH0_CR_TXXTALK_Lane6_WID ( 4) + #define DDRDATA7CH0_CR_TXXTALK_Lane6_MSK (0x0F000000) + #define DDRDATA7CH0_CR_TXXTALK_Lane6_MAX (0x0000000F) + #define DDRDATA7CH0_CR_TXXTALK_Lane7_OFF (28) + #define DDRDATA7CH0_CR_TXXTALK_Lane7_WID ( 4) + #define DDRDATA7CH0_CR_TXXTALK_Lane7_MSK (0xF0000000) + #define DDRDATA7CH0_CR_TXXTALK_Lane7_MAX (0x0000000F) + +#define DDRDATA7CH0_CR_RXOFFSETVDQ_REG (0x00000E4C) + #define DDRDATA7CH0_CR_RXOFFSETVDQ_Lane0_OFF ( 0) + #define DDRDATA7CH0_CR_RXOFFSETVDQ_Lane0_WID ( 4) + #define DDRDATA7CH0_CR_RXOFFSETVDQ_Lane0_MSK (0x0000000F) + #define DDRDATA7CH0_CR_RXOFFSETVDQ_Lane0_MAX (0x0000000F) + #define DDRDATA7CH0_CR_RXOFFSETVDQ_Lane1_OFF ( 4) + #define DDRDATA7CH0_CR_RXOFFSETVDQ_Lane1_WID ( 4) + #define DDRDATA7CH0_CR_RXOFFSETVDQ_Lane1_MSK (0x000000F0) + #define DDRDATA7CH0_CR_RXOFFSETVDQ_Lane1_MAX (0x0000000F) + #define DDRDATA7CH0_CR_RXOFFSETVDQ_Lane2_OFF ( 8) + #define DDRDATA7CH0_CR_RXOFFSETVDQ_Lane2_WID ( 4) + #define DDRDATA7CH0_CR_RXOFFSETVDQ_Lane2_MSK (0x00000F00) + #define DDRDATA7CH0_CR_RXOFFSETVDQ_Lane2_MAX (0x0000000F) + #define DDRDATA7CH0_CR_RXOFFSETVDQ_Lane3_OFF (12) + #define DDRDATA7CH0_CR_RXOFFSETVDQ_Lane3_WID ( 4) + #define DDRDATA7CH0_CR_RXOFFSETVDQ_Lane3_MSK (0x0000F000) + #define DDRDATA7CH0_CR_RXOFFSETVDQ_Lane3_MAX (0x0000000F) + #define DDRDATA7CH0_CR_RXOFFSETVDQ_Lane4_OFF (16) + #define DDRDATA7CH0_CR_RXOFFSETVDQ_Lane4_WID ( 4) + #define DDRDATA7CH0_CR_RXOFFSETVDQ_Lane4_MSK (0x000F0000) + #define DDRDATA7CH0_CR_RXOFFSETVDQ_Lane4_MAX (0x0000000F) + #define DDRDATA7CH0_CR_RXOFFSETVDQ_Lane5_OFF (20) + #define DDRDATA7CH0_CR_RXOFFSETVDQ_Lane5_WID ( 4) + #define DDRDATA7CH0_CR_RXOFFSETVDQ_Lane5_MSK (0x00F00000) + #define DDRDATA7CH0_CR_RXOFFSETVDQ_Lane5_MAX (0x0000000F) + #define DDRDATA7CH0_CR_RXOFFSETVDQ_Lane6_OFF (24) + #define DDRDATA7CH0_CR_RXOFFSETVDQ_Lane6_WID ( 4) + #define DDRDATA7CH0_CR_RXOFFSETVDQ_Lane6_MSK (0x0F000000) + #define DDRDATA7CH0_CR_RXOFFSETVDQ_Lane6_MAX (0x0000000F) + #define DDRDATA7CH0_CR_RXOFFSETVDQ_Lane7_OFF (28) + #define DDRDATA7CH0_CR_RXOFFSETVDQ_Lane7_WID ( 4) + #define DDRDATA7CH0_CR_RXOFFSETVDQ_Lane7_MSK (0xF0000000) + #define DDRDATA7CH0_CR_RXOFFSETVDQ_Lane7_MAX (0x0000000F) + +#define DDRDATA7CH0_CR_DDRDATARESERVED_REG (0x00000E50) + #define DDRDATA7CH0_CR_DDRDATARESERVED_Spare_OFF ( 0) + #define DDRDATA7CH0_CR_DDRDATARESERVED_Spare_WID (32) + #define DDRDATA7CH0_CR_DDRDATARESERVED_Spare_MSK (0xFFFFFFFF) + #define DDRDATA7CH0_CR_DDRDATARESERVED_Spare_MAX (0xFFFFFFFF) + +#define DDRDATA7CH0_CR_DATATRAINFEEDBACK_REG (0x00000E54) + #define DDRDATA7CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_OFF ( 0) + #define DDRDATA7CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_WID ( 9) + #define DDRDATA7CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_MSK (0x000001FF) + #define DDRDATA7CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_MAX (0x000001FF) + #define DDRDATA7CH0_CR_DATATRAINFEEDBACK_Spare_OFF ( 9) + #define DDRDATA7CH0_CR_DATATRAINFEEDBACK_Spare_WID (23) + #define DDRDATA7CH0_CR_DATATRAINFEEDBACK_Spare_MSK (0xFFFFFE00) + #define DDRDATA7CH0_CR_DATATRAINFEEDBACK_Spare_MAX (0x007FFFFF) + +#define DDRDATA7CH0_CR_DLLPITESTANDADC_REG (0x00000E58) + #define DDRDATA7CH0_CR_DLLPITESTANDADC_RunTest_OFF ( 0) + #define DDRDATA7CH0_CR_DLLPITESTANDADC_RunTest_WID ( 1) + #define DDRDATA7CH0_CR_DLLPITESTANDADC_RunTest_MSK (0x00000001) + #define DDRDATA7CH0_CR_DLLPITESTANDADC_RunTest_MAX (0x00000001) + #define DDRDATA7CH0_CR_DLLPITESTANDADC_RunTest_DEF (0x00000000) + #define DDRDATA7CH0_CR_DLLPITESTANDADC_Load_OFF ( 1) + #define DDRDATA7CH0_CR_DLLPITESTANDADC_Load_WID ( 1) + #define DDRDATA7CH0_CR_DLLPITESTANDADC_Load_MSK (0x00000002) + #define DDRDATA7CH0_CR_DLLPITESTANDADC_Load_MAX (0x00000001) + #define DDRDATA7CH0_CR_DLLPITESTANDADC_Load_DEF (0x00000000) + #define DDRDATA7CH0_CR_DLLPITESTANDADC_ModeHVM_OFF ( 2) + #define DDRDATA7CH0_CR_DLLPITESTANDADC_ModeHVM_WID ( 1) + #define DDRDATA7CH0_CR_DLLPITESTANDADC_ModeHVM_MSK (0x00000004) + #define DDRDATA7CH0_CR_DLLPITESTANDADC_ModeHVM_MAX (0x00000001) + #define DDRDATA7CH0_CR_DLLPITESTANDADC_ModeHVM_DEF (0x00000000) + #define DDRDATA7CH0_CR_DLLPITESTANDADC_ModeDV_OFF ( 3) + #define DDRDATA7CH0_CR_DLLPITESTANDADC_ModeDV_WID ( 1) + #define DDRDATA7CH0_CR_DLLPITESTANDADC_ModeDV_MSK (0x00000008) + #define DDRDATA7CH0_CR_DLLPITESTANDADC_ModeDV_MAX (0x00000001) + #define DDRDATA7CH0_CR_DLLPITESTANDADC_ModeDV_DEF (0x00000000) + #define DDRDATA7CH0_CR_DLLPITESTANDADC_ModeADC_OFF ( 4) + #define DDRDATA7CH0_CR_DLLPITESTANDADC_ModeADC_WID ( 1) + #define DDRDATA7CH0_CR_DLLPITESTANDADC_ModeADC_MSK (0x00000010) + #define DDRDATA7CH0_CR_DLLPITESTANDADC_ModeADC_MAX (0x00000001) + #define DDRDATA7CH0_CR_DLLPITESTANDADC_ModeADC_DEF (0x00000000) + #define DDRDATA7CH0_CR_DLLPITESTANDADC_LoadCount_OFF ( 5) + #define DDRDATA7CH0_CR_DLLPITESTANDADC_LoadCount_WID (10) + #define DDRDATA7CH0_CR_DLLPITESTANDADC_LoadCount_MSK (0x00007FE0) + #define DDRDATA7CH0_CR_DLLPITESTANDADC_LoadCount_MAX (0x000003FF) + #define DDRDATA7CH0_CR_DLLPITESTANDADC_CountStatus_OFF (15) + #define DDRDATA7CH0_CR_DLLPITESTANDADC_CountStatus_WID (10) + #define DDRDATA7CH0_CR_DLLPITESTANDADC_CountStatus_MSK (0x01FF8000) + #define DDRDATA7CH0_CR_DLLPITESTANDADC_CountStatus_MAX (0x000003FF) + #define DDRDATA7CH0_CR_DLLPITESTANDADC_CountStatus_DEF (0x00000000) + #define DDRDATA7CH0_CR_DLLPITESTANDADC_Spare_OFF (25) + #define DDRDATA7CH0_CR_DLLPITESTANDADC_Spare_WID ( 7) + #define DDRDATA7CH0_CR_DLLPITESTANDADC_Spare_MSK (0xFE000000) + #define DDRDATA7CH0_CR_DLLPITESTANDADC_Spare_MAX (0x0000007F) + +#define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_REG (0x00000E5C) + #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_OFF ( 0) + #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_WID ( 6) + #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MSK (0x0000003F) + #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MAX (0x0000003F) + #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_DEF (0x00000000) + #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_OFF ( 6) + #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_WID ( 6) + #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MSK (0x00000FC0) + #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MAX (0x0000003F) + #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_DEF (0x00000000) + #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_OFF (12) + #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_WID ( 5) + #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MSK (0x0001F000) + #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MAX (0x0000001F) + #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_DEF (0x00000000) + #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_OFF (17) + #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_WID ( 5) + #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MSK (0x003E0000) + #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MAX (0x0000001F) + #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_DEF (0x00000000) + #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_OFF (22) + #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_WID ( 5) + #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_MSK (0x07C00000) + #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_MAX (0x0000001F) + #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_DEF (0x00000000) + #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_OFF (27) + #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_WID ( 5) + #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MSK (0xF8000000) + #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MAX (0x0000001F) + #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_DEF (0x00000000) + +#define DDRDATA7CH0_CR_DDRCRDATACONTROL1_REG (0x00000E60) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_RefPi_OFF ( 0) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_RefPi_WID ( 4) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_RefPi_MSK (0x0000000F) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_RefPi_MAX (0x0000000F) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_RefPi_DEF (0x00000000) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_DllMask_OFF ( 4) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_DllMask_WID ( 2) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_DllMask_MSK (0x00000030) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_DllMask_MAX (0x00000003) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_DllMask_DEF (0x00000000) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_DllWeakLock_OFF ( 6) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_DllWeakLock_WID ( 1) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_DllWeakLock_MSK (0x00000040) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_DllWeakLock_MAX (0x00000001) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_DllWeakLock_DEF (0x00000000) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_OFF ( 7) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_WID ( 3) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MSK (0x00000380) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MAX (0x00000007) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_DEF (0x00000000) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_OFF (10) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_WID ( 3) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_MSK (0x00001C00) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_MAX (0x00000007) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_DEF (0x00000000) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_OdtDelay_OFF (13) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_OdtDelay_WID ( 4) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_OdtDelay_MSK (0x0001E000) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_OdtDelay_MAX (0x0000000F) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_OdtDelay_DEF (0x00000000) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_OdtDuration_OFF (17) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_OdtDuration_WID ( 3) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_OdtDuration_MSK (0x000E0000) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_OdtDuration_MAX (0x00000007) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_OdtDuration_DEF (0x00000000) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_OFF (20) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_WID ( 4) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_MSK (0x00F00000) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_MAX (0x0000000F) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_DEF (0x00000000) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_OFF (24) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_WID ( 3) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_MSK (0x07000000) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_MAX (0x00000007) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_DEF (0x00000000) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_OFF (27) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_WID ( 3) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_MSK (0x38000000) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_MAX (0x00000007) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_DEF (0x00000000) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_OFF (30) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_WID ( 1) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_MSK (0x40000000) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_MAX (0x00000001) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_DEF (0x00000000) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_Rsvd1_OFF (31) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_Rsvd1_WID ( 1) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_Rsvd1_MSK (0x80000000) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_Rsvd1_MAX (0x00000001) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_Rsvd1_DEF (0x00000000) + +#define DDRDATA7CH0_CR_DDRCRDATACONTROL2_REG (0x00000E64) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_OFF ( 0) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_WID ( 5) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_MSK (0x0000001F) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_MAX (0x0000001F) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_DEF (0x00000000) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_OFF ( 5) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_WID ( 1) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_MSK (0x00000020) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_MAX (0x00000001) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_DEF (0x00000000) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_ForceRxOn_OFF ( 6) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_ForceRxOn_WID ( 1) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_ForceRxOn_MSK (0x00000040) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_ForceRxOn_MAX (0x00000001) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_ForceRxOn_DEF (0x00000000) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_LeakerComp_OFF ( 7) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_LeakerComp_WID ( 2) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_LeakerComp_MSK (0x00000180) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_LeakerComp_MAX (0x00000003) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_LeakerComp_DEF (0x00000000) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_OFF ( 9) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_WID ( 4) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_MSK (0x00001E00) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_MAX (0x0000000F) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_DEF (0x00000008) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_OFF (13) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_WID ( 5) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_MSK (0x0003E000) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_MAX (0x0000001F) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_DEF (0x00000011) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_OFF (18) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_WID ( 1) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_MSK (0x00040000) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_MAX (0x00000001) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_DEF (0x00000000) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_Spare_OFF (19) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_Spare_WID (13) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_Spare_MSK (0xFFF80000) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_Spare_MAX (0x00001FFF) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_Spare_DEF (0x00000000) + +#define DDRDATA7CH0_CR_DDRCRVSSHIORVREFCONTROL_REG (0x00000E6C) + #define DDRDATA7CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_OFF ( 0) + #define DDRDATA7CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_WID (24) + #define DDRDATA7CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_MSK (0x00FFFFFF) + #define DDRDATA7CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_MAX (0x00FFFFFF) + #define DDRDATA7CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_DEF (0x00000000) + #define DDRDATA7CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_OFF (24) + #define DDRDATA7CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_WID ( 8) + #define DDRDATA7CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_MSK (0xFF000000) + #define DDRDATA7CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_MAX (0x000000FF) + #define DDRDATA7CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_DEF (0x00000000) + +#define DDRDATA7CH0_CR_DDRCRDATAOFFSETTRAIN_REG (0x00000E70) + #define DDRDATA7CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_OFF ( 0) + #define DDRDATA7CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_WID ( 6) + #define DDRDATA7CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MSK (0x0000003F) + #define DDRDATA7CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MAX (0x0000003F) + #define DDRDATA7CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_DEF (0x00000000) + #define DDRDATA7CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_OFF ( 6) + #define DDRDATA7CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_WID ( 6) + #define DDRDATA7CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MSK (0x00000FC0) + #define DDRDATA7CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MAX (0x0000003F) + #define DDRDATA7CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_DEF (0x00000000) + #define DDRDATA7CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_OFF (12) + #define DDRDATA7CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_WID ( 6) + #define DDRDATA7CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MSK (0x0003F000) + #define DDRDATA7CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MAX (0x0000003F) + #define DDRDATA7CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_DEF (0x00000000) + #define DDRDATA7CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_OFF (18) + #define DDRDATA7CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_WID ( 6) + #define DDRDATA7CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MSK (0x00FC0000) + #define DDRDATA7CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MAX (0x0000003F) + #define DDRDATA7CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_DEF (0x00000000) + #define DDRDATA7CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_OFF (24) + #define DDRDATA7CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_WID ( 7) + #define DDRDATA7CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MSK (0x7F000000) + #define DDRDATA7CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MAX (0x0000007F) + #define DDRDATA7CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_DEF (0x00000000) + #define DDRDATA7CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_OFF (31) + #define DDRDATA7CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_WID ( 1) + #define DDRDATA7CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_MSK (0x80000000) + #define DDRDATA7CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_MAX (0x00000001) + #define DDRDATA7CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_DEF (0x00000000) + +#define DDRDATA7CH0_CR_DDRCRDATACONTROL0_REG (0x00000E74) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_OFF ( 0) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_WID ( 1) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_MSK (0x00000001) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_MAX (0x00000001) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_DEF (0x00000000) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_OFF ( 1) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_WID ( 1) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_MSK (0x00000002) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_MAX (0x00000001) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_DEF (0x00000000) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_OFF ( 2) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_WID ( 1) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_MSK (0x00000004) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_MAX (0x00000001) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_DEF (0x00000000) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_OFF ( 3) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_WID ( 1) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MSK (0x00000008) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MAX (0x00000001) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_DEF (0x00000000) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_TxOn_OFF ( 4) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_TxOn_WID ( 1) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_TxOn_MSK (0x00000010) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_TxOn_MAX (0x00000001) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_TxOn_DEF (0x00000000) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RfOn_OFF ( 5) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RfOn_WID ( 1) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RfOn_MSK (0x00000020) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RfOn_MAX (0x00000001) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RfOn_DEF (0x00000000) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RxPiOn_OFF ( 6) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RxPiOn_WID ( 1) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RxPiOn_MSK (0x00000040) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RxPiOn_MAX (0x00000001) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RxPiOn_DEF (0x00000000) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_TxPiOn_OFF ( 7) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_TxPiOn_WID ( 1) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_TxPiOn_MSK (0x00000080) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_TxPiOn_MAX (0x00000001) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_TxPiOn_DEF (0x00000000) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_OFF ( 8) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_WID ( 1) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_MSK (0x00000100) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_MAX (0x00000001) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_DEF (0x00000000) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_OFF ( 9) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_WID ( 1) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MSK (0x00000200) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MAX (0x00000001) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_DEF (0x00000000) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_TxDisable_OFF (10) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_TxDisable_WID ( 1) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_TxDisable_MSK (0x00000400) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_TxDisable_MAX (0x00000001) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_TxDisable_DEF (0x00000000) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RxDisable_OFF (11) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RxDisable_WID ( 1) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RxDisable_MSK (0x00000800) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RxDisable_MAX (0x00000001) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RxDisable_DEF (0x00000000) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_TxLong_OFF (12) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_TxLong_WID ( 1) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_TxLong_MSK (0x00001000) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_TxLong_MAX (0x00000001) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_TxLong_DEF (0x00000000) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_OFF (13) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_WID ( 2) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_MSK (0x00006000) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_MAX (0x00000003) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_DEF (0x00000000) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RxReadPointer_OFF (15) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RxReadPointer_WID ( 3) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RxReadPointer_MSK (0x00038000) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RxReadPointer_MAX (0x00000007) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RxReadPointer_DEF (0x00000000) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_OFF (18) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_WID ( 1) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_MSK (0x00040000) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_MAX (0x00000001) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_DEF (0x00000000) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_OFF (19) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_WID ( 1) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_MSK (0x00080000) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_MAX (0x00000001) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_DEF (0x00000000) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_ReadRFRd_OFF (20) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_ReadRFRd_WID ( 1) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_ReadRFRd_MSK (0x00100000) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_ReadRFRd_MAX (0x00000001) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_ReadRFRd_DEF (0x00000000) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_ReadRFWr_OFF (21) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_ReadRFWr_WID ( 1) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_ReadRFWr_MSK (0x00200000) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_ReadRFWr_MAX (0x00000001) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_ReadRFWr_DEF (0x00000000) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_ReadRFRank_OFF (22) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_ReadRFRank_WID ( 2) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_ReadRFRank_MSK (0x00C00000) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_ReadRFRank_MAX (0x00000003) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_ReadRFRank_DEF (0x00000000) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_OFF (24) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_WID ( 1) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_MSK (0x01000000) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_MAX (0x00000001) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_DEF (0x00000000) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_OdtSampOff_OFF (25) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_OdtSampOff_WID ( 1) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_OdtSampOff_MSK (0x02000000) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_OdtSampOff_MAX (0x00000001) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_OdtSampOff_DEF (0x00000000) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_OFF (26) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_WID ( 1) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_MSK (0x04000000) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_MAX (0x00000001) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_DEF (0x00000000) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_OFF (27) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_WID ( 1) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MSK (0x08000000) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MAX (0x00000001) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_DEF (0x00000000) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_OFF (28) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_WID ( 1) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_MSK (0x10000000) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_MAX (0x00000001) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_DEF (0x00000000) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_OFF (29) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_WID ( 1) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_MSK (0x20000000) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_MAX (0x00000001) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_DEF (0x00000000) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_OFF (30) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_WID ( 1) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MSK (0x40000000) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MAX (0x00000001) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_DEF (0x00000000) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_OFF (31) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_WID ( 1) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_MSK (0x80000000) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_MAX (0x00000001) + #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_DEF (0x00000000) + +#define DDRDATA7CH0_CR_DDRCRVREFADJUST1_REG (0x00000E78) + #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_OFF ( 0) + #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_WID ( 7) + #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_MSK (0x0000007F) + #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_MAX (0x0000007F) + #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_DEF (0x00000000) + #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_OFF ( 7) + #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_WID ( 7) + #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_MSK (0x00003F80) + #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_MAX (0x0000007F) + #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_DEF (0x00000000) + #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_OFF (14) + #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_WID ( 7) + #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_MSK (0x001FC000) + #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_MAX (0x0000007F) + #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_DEF (0x00000000) + #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_OFF (21) + #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_WID ( 1) + #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_MSK (0x00200000) + #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_MAX (0x00000001) + #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_DEF (0x00000000) + #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_OFF (22) + #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_WID ( 1) + #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_MSK (0x00400000) + #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_MAX (0x00000001) + #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_DEF (0x00000000) + #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_OFF (23) + #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_WID ( 1) + #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_MSK (0x00800000) + #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_MAX (0x00000001) + #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_DEF (0x00000000) + #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_OFF (24) + #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_WID ( 2) + #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_MSK (0x03000000) + #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_MAX (0x00000003) + #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_DEF (0x00000000) + #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_OFF (26) + #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_WID ( 1) + #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_MSK (0x04000000) + #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_MAX (0x00000001) + #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_DEF (0x00000000) + #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_Rsvd_OFF (27) + #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_Rsvd_WID ( 2) + #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_Rsvd_MSK (0x18000000) + #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_Rsvd_MAX (0x00000003) + #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_Rsvd_DEF (0x00000000) + #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_caSlowBW_OFF (29) + #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_caSlowBW_WID ( 1) + #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_caSlowBW_MSK (0x20000000) + #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_caSlowBW_MAX (0x00000001) + #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_caSlowBW_DEF (0x00000000) + #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_OFF (30) + #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_WID ( 1) + #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_MSK (0x40000000) + #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_MAX (0x00000001) + #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_DEF (0x00000000) + #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_OFF (31) + #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_WID ( 1) + #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_MSK (0x80000000) + #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_MAX (0x00000001) + #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_DEF (0x00000000) + +#define DDRDATA7CH1_CR_RXTRAINRANK0_REG (0x00000F00) + #define DDRDATA7CH1_CR_RXTRAINRANK0_RxRcvEnPi_OFF ( 0) + #define DDRDATA7CH1_CR_RXTRAINRANK0_RxRcvEnPi_WID ( 9) + #define DDRDATA7CH1_CR_RXTRAINRANK0_RxRcvEnPi_MSK (0x000001FF) + #define DDRDATA7CH1_CR_RXTRAINRANK0_RxRcvEnPi_MAX (0x000001FF) + #define DDRDATA7CH1_CR_RXTRAINRANK0_RxDqsPPi_OFF ( 9) + #define DDRDATA7CH1_CR_RXTRAINRANK0_RxDqsPPi_WID ( 6) + #define DDRDATA7CH1_CR_RXTRAINRANK0_RxDqsPPi_MSK (0x00007E00) + #define DDRDATA7CH1_CR_RXTRAINRANK0_RxDqsPPi_MAX (0x0000003F) + #define DDRDATA7CH1_CR_RXTRAINRANK0_RxEq_OFF (15) + #define DDRDATA7CH1_CR_RXTRAINRANK0_RxEq_WID ( 5) + #define DDRDATA7CH1_CR_RXTRAINRANK0_RxEq_MSK (0x000F8000) + #define DDRDATA7CH1_CR_RXTRAINRANK0_RxEq_MAX (0x0000001F) + #define DDRDATA7CH1_CR_RXTRAINRANK0_RxDqsNPi_OFF (20) + #define DDRDATA7CH1_CR_RXTRAINRANK0_RxDqsNPi_WID ( 6) + #define DDRDATA7CH1_CR_RXTRAINRANK0_RxDqsNPi_MSK (0x03F00000) + #define DDRDATA7CH1_CR_RXTRAINRANK0_RxDqsNPi_MAX (0x0000003F) + #define DDRDATA7CH1_CR_RXTRAINRANK0_RxVref_OFF (26) + #define DDRDATA7CH1_CR_RXTRAINRANK0_RxVref_WID ( 6) + #define DDRDATA7CH1_CR_RXTRAINRANK0_RxVref_MSK (0xFC000000) + #define DDRDATA7CH1_CR_RXTRAINRANK0_RxVref_MAX (0x0000003F) + +#define DDRDATA7CH1_CR_RXTRAINRANK1_REG (0x00000F04) + #define DDRDATA7CH1_CR_RXTRAINRANK1_RxRcvEnPi_OFF ( 0) + #define DDRDATA7CH1_CR_RXTRAINRANK1_RxRcvEnPi_WID ( 9) + #define DDRDATA7CH1_CR_RXTRAINRANK1_RxRcvEnPi_MSK (0x000001FF) + #define DDRDATA7CH1_CR_RXTRAINRANK1_RxRcvEnPi_MAX (0x000001FF) + #define DDRDATA7CH1_CR_RXTRAINRANK1_RxDqsPPi_OFF ( 9) + #define DDRDATA7CH1_CR_RXTRAINRANK1_RxDqsPPi_WID ( 6) + #define DDRDATA7CH1_CR_RXTRAINRANK1_RxDqsPPi_MSK (0x00007E00) + #define DDRDATA7CH1_CR_RXTRAINRANK1_RxDqsPPi_MAX (0x0000003F) + #define DDRDATA7CH1_CR_RXTRAINRANK1_RxEq_OFF (15) + #define DDRDATA7CH1_CR_RXTRAINRANK1_RxEq_WID ( 5) + #define DDRDATA7CH1_CR_RXTRAINRANK1_RxEq_MSK (0x000F8000) + #define DDRDATA7CH1_CR_RXTRAINRANK1_RxEq_MAX (0x0000001F) + #define DDRDATA7CH1_CR_RXTRAINRANK1_RxDqsNPi_OFF (20) + #define DDRDATA7CH1_CR_RXTRAINRANK1_RxDqsNPi_WID ( 6) + #define DDRDATA7CH1_CR_RXTRAINRANK1_RxDqsNPi_MSK (0x03F00000) + #define DDRDATA7CH1_CR_RXTRAINRANK1_RxDqsNPi_MAX (0x0000003F) + #define DDRDATA7CH1_CR_RXTRAINRANK1_RxVref_OFF (26) + #define DDRDATA7CH1_CR_RXTRAINRANK1_RxVref_WID ( 6) + #define DDRDATA7CH1_CR_RXTRAINRANK1_RxVref_MSK (0xFC000000) + #define DDRDATA7CH1_CR_RXTRAINRANK1_RxVref_MAX (0x0000003F) + +#define DDRDATA7CH1_CR_RXTRAINRANK2_REG (0x00000F08) + #define DDRDATA7CH1_CR_RXTRAINRANK2_RxRcvEnPi_OFF ( 0) + #define DDRDATA7CH1_CR_RXTRAINRANK2_RxRcvEnPi_WID ( 9) + #define DDRDATA7CH1_CR_RXTRAINRANK2_RxRcvEnPi_MSK (0x000001FF) + #define DDRDATA7CH1_CR_RXTRAINRANK2_RxRcvEnPi_MAX (0x000001FF) + #define DDRDATA7CH1_CR_RXTRAINRANK2_RxDqsPPi_OFF ( 9) + #define DDRDATA7CH1_CR_RXTRAINRANK2_RxDqsPPi_WID ( 6) + #define DDRDATA7CH1_CR_RXTRAINRANK2_RxDqsPPi_MSK (0x00007E00) + #define DDRDATA7CH1_CR_RXTRAINRANK2_RxDqsPPi_MAX (0x0000003F) + #define DDRDATA7CH1_CR_RXTRAINRANK2_RxEq_OFF (15) + #define DDRDATA7CH1_CR_RXTRAINRANK2_RxEq_WID ( 5) + #define DDRDATA7CH1_CR_RXTRAINRANK2_RxEq_MSK (0x000F8000) + #define DDRDATA7CH1_CR_RXTRAINRANK2_RxEq_MAX (0x0000001F) + #define DDRDATA7CH1_CR_RXTRAINRANK2_RxDqsNPi_OFF (20) + #define DDRDATA7CH1_CR_RXTRAINRANK2_RxDqsNPi_WID ( 6) + #define DDRDATA7CH1_CR_RXTRAINRANK2_RxDqsNPi_MSK (0x03F00000) + #define DDRDATA7CH1_CR_RXTRAINRANK2_RxDqsNPi_MAX (0x0000003F) + #define DDRDATA7CH1_CR_RXTRAINRANK2_RxVref_OFF (26) + #define DDRDATA7CH1_CR_RXTRAINRANK2_RxVref_WID ( 6) + #define DDRDATA7CH1_CR_RXTRAINRANK2_RxVref_MSK (0xFC000000) + #define DDRDATA7CH1_CR_RXTRAINRANK2_RxVref_MAX (0x0000003F) + +#define DDRDATA7CH1_CR_RXTRAINRANK3_REG (0x00000F0C) + #define DDRDATA7CH1_CR_RXTRAINRANK3_RxRcvEnPi_OFF ( 0) + #define DDRDATA7CH1_CR_RXTRAINRANK3_RxRcvEnPi_WID ( 9) + #define DDRDATA7CH1_CR_RXTRAINRANK3_RxRcvEnPi_MSK (0x000001FF) + #define DDRDATA7CH1_CR_RXTRAINRANK3_RxRcvEnPi_MAX (0x000001FF) + #define DDRDATA7CH1_CR_RXTRAINRANK3_RxDqsPPi_OFF ( 9) + #define DDRDATA7CH1_CR_RXTRAINRANK3_RxDqsPPi_WID ( 6) + #define DDRDATA7CH1_CR_RXTRAINRANK3_RxDqsPPi_MSK (0x00007E00) + #define DDRDATA7CH1_CR_RXTRAINRANK3_RxDqsPPi_MAX (0x0000003F) + #define DDRDATA7CH1_CR_RXTRAINRANK3_RxEq_OFF (15) + #define DDRDATA7CH1_CR_RXTRAINRANK3_RxEq_WID ( 5) + #define DDRDATA7CH1_CR_RXTRAINRANK3_RxEq_MSK (0x000F8000) + #define DDRDATA7CH1_CR_RXTRAINRANK3_RxEq_MAX (0x0000001F) + #define DDRDATA7CH1_CR_RXTRAINRANK3_RxDqsNPi_OFF (20) + #define DDRDATA7CH1_CR_RXTRAINRANK3_RxDqsNPi_WID ( 6) + #define DDRDATA7CH1_CR_RXTRAINRANK3_RxDqsNPi_MSK (0x03F00000) + #define DDRDATA7CH1_CR_RXTRAINRANK3_RxDqsNPi_MAX (0x0000003F) + #define DDRDATA7CH1_CR_RXTRAINRANK3_RxVref_OFF (26) + #define DDRDATA7CH1_CR_RXTRAINRANK3_RxVref_WID ( 6) + #define DDRDATA7CH1_CR_RXTRAINRANK3_RxVref_MSK (0xFC000000) + #define DDRDATA7CH1_CR_RXTRAINRANK3_RxVref_MAX (0x0000003F) + +#define DDRDATA7CH1_CR_RXPERBITRANK0_REG (0x00000F10) + #define DDRDATA7CH1_CR_RXPERBITRANK0_Lane0_OFF ( 0) + #define DDRDATA7CH1_CR_RXPERBITRANK0_Lane0_WID ( 4) + #define DDRDATA7CH1_CR_RXPERBITRANK0_Lane0_MSK (0x0000000F) + #define DDRDATA7CH1_CR_RXPERBITRANK0_Lane0_MAX (0x0000000F) + #define DDRDATA7CH1_CR_RXPERBITRANK0_Lane1_OFF ( 4) + #define DDRDATA7CH1_CR_RXPERBITRANK0_Lane1_WID ( 4) + #define DDRDATA7CH1_CR_RXPERBITRANK0_Lane1_MSK (0x000000F0) + #define DDRDATA7CH1_CR_RXPERBITRANK0_Lane1_MAX (0x0000000F) + #define DDRDATA7CH1_CR_RXPERBITRANK0_Lane2_OFF ( 8) + #define DDRDATA7CH1_CR_RXPERBITRANK0_Lane2_WID ( 4) + #define DDRDATA7CH1_CR_RXPERBITRANK0_Lane2_MSK (0x00000F00) + #define DDRDATA7CH1_CR_RXPERBITRANK0_Lane2_MAX (0x0000000F) + #define DDRDATA7CH1_CR_RXPERBITRANK0_Lane3_OFF (12) + #define DDRDATA7CH1_CR_RXPERBITRANK0_Lane3_WID ( 4) + #define DDRDATA7CH1_CR_RXPERBITRANK0_Lane3_MSK (0x0000F000) + #define DDRDATA7CH1_CR_RXPERBITRANK0_Lane3_MAX (0x0000000F) + #define DDRDATA7CH1_CR_RXPERBITRANK0_Lane4_OFF (16) + #define DDRDATA7CH1_CR_RXPERBITRANK0_Lane4_WID ( 4) + #define DDRDATA7CH1_CR_RXPERBITRANK0_Lane4_MSK (0x000F0000) + #define DDRDATA7CH1_CR_RXPERBITRANK0_Lane4_MAX (0x0000000F) + #define DDRDATA7CH1_CR_RXPERBITRANK0_Lane5_OFF (20) + #define DDRDATA7CH1_CR_RXPERBITRANK0_Lane5_WID ( 4) + #define DDRDATA7CH1_CR_RXPERBITRANK0_Lane5_MSK (0x00F00000) + #define DDRDATA7CH1_CR_RXPERBITRANK0_Lane5_MAX (0x0000000F) + #define DDRDATA7CH1_CR_RXPERBITRANK0_Lane6_OFF (24) + #define DDRDATA7CH1_CR_RXPERBITRANK0_Lane6_WID ( 4) + #define DDRDATA7CH1_CR_RXPERBITRANK0_Lane6_MSK (0x0F000000) + #define DDRDATA7CH1_CR_RXPERBITRANK0_Lane6_MAX (0x0000000F) + #define DDRDATA7CH1_CR_RXPERBITRANK0_Lane7_OFF (28) + #define DDRDATA7CH1_CR_RXPERBITRANK0_Lane7_WID ( 4) + #define DDRDATA7CH1_CR_RXPERBITRANK0_Lane7_MSK (0xF0000000) + #define DDRDATA7CH1_CR_RXPERBITRANK0_Lane7_MAX (0x0000000F) + +#define DDRDATA7CH1_CR_RXPERBITRANK1_REG (0x00000F14) + #define DDRDATA7CH1_CR_RXPERBITRANK1_Lane0_OFF ( 0) + #define DDRDATA7CH1_CR_RXPERBITRANK1_Lane0_WID ( 4) + #define DDRDATA7CH1_CR_RXPERBITRANK1_Lane0_MSK (0x0000000F) + #define DDRDATA7CH1_CR_RXPERBITRANK1_Lane0_MAX (0x0000000F) + #define DDRDATA7CH1_CR_RXPERBITRANK1_Lane1_OFF ( 4) + #define DDRDATA7CH1_CR_RXPERBITRANK1_Lane1_WID ( 4) + #define DDRDATA7CH1_CR_RXPERBITRANK1_Lane1_MSK (0x000000F0) + #define DDRDATA7CH1_CR_RXPERBITRANK1_Lane1_MAX (0x0000000F) + #define DDRDATA7CH1_CR_RXPERBITRANK1_Lane2_OFF ( 8) + #define DDRDATA7CH1_CR_RXPERBITRANK1_Lane2_WID ( 4) + #define DDRDATA7CH1_CR_RXPERBITRANK1_Lane2_MSK (0x00000F00) + #define DDRDATA7CH1_CR_RXPERBITRANK1_Lane2_MAX (0x0000000F) + #define DDRDATA7CH1_CR_RXPERBITRANK1_Lane3_OFF (12) + #define DDRDATA7CH1_CR_RXPERBITRANK1_Lane3_WID ( 4) + #define DDRDATA7CH1_CR_RXPERBITRANK1_Lane3_MSK (0x0000F000) + #define DDRDATA7CH1_CR_RXPERBITRANK1_Lane3_MAX (0x0000000F) + #define DDRDATA7CH1_CR_RXPERBITRANK1_Lane4_OFF (16) + #define DDRDATA7CH1_CR_RXPERBITRANK1_Lane4_WID ( 4) + #define DDRDATA7CH1_CR_RXPERBITRANK1_Lane4_MSK (0x000F0000) + #define DDRDATA7CH1_CR_RXPERBITRANK1_Lane4_MAX (0x0000000F) + #define DDRDATA7CH1_CR_RXPERBITRANK1_Lane5_OFF (20) + #define DDRDATA7CH1_CR_RXPERBITRANK1_Lane5_WID ( 4) + #define DDRDATA7CH1_CR_RXPERBITRANK1_Lane5_MSK (0x00F00000) + #define DDRDATA7CH1_CR_RXPERBITRANK1_Lane5_MAX (0x0000000F) + #define DDRDATA7CH1_CR_RXPERBITRANK1_Lane6_OFF (24) + #define DDRDATA7CH1_CR_RXPERBITRANK1_Lane6_WID ( 4) + #define DDRDATA7CH1_CR_RXPERBITRANK1_Lane6_MSK (0x0F000000) + #define DDRDATA7CH1_CR_RXPERBITRANK1_Lane6_MAX (0x0000000F) + #define DDRDATA7CH1_CR_RXPERBITRANK1_Lane7_OFF (28) + #define DDRDATA7CH1_CR_RXPERBITRANK1_Lane7_WID ( 4) + #define DDRDATA7CH1_CR_RXPERBITRANK1_Lane7_MSK (0xF0000000) + #define DDRDATA7CH1_CR_RXPERBITRANK1_Lane7_MAX (0x0000000F) + +#define DDRDATA7CH1_CR_RXPERBITRANK2_REG (0x00000F18) + #define DDRDATA7CH1_CR_RXPERBITRANK2_Lane0_OFF ( 0) + #define DDRDATA7CH1_CR_RXPERBITRANK2_Lane0_WID ( 4) + #define DDRDATA7CH1_CR_RXPERBITRANK2_Lane0_MSK (0x0000000F) + #define DDRDATA7CH1_CR_RXPERBITRANK2_Lane0_MAX (0x0000000F) + #define DDRDATA7CH1_CR_RXPERBITRANK2_Lane1_OFF ( 4) + #define DDRDATA7CH1_CR_RXPERBITRANK2_Lane1_WID ( 4) + #define DDRDATA7CH1_CR_RXPERBITRANK2_Lane1_MSK (0x000000F0) + #define DDRDATA7CH1_CR_RXPERBITRANK2_Lane1_MAX (0x0000000F) + #define DDRDATA7CH1_CR_RXPERBITRANK2_Lane2_OFF ( 8) + #define DDRDATA7CH1_CR_RXPERBITRANK2_Lane2_WID ( 4) + #define DDRDATA7CH1_CR_RXPERBITRANK2_Lane2_MSK (0x00000F00) + #define DDRDATA7CH1_CR_RXPERBITRANK2_Lane2_MAX (0x0000000F) + #define DDRDATA7CH1_CR_RXPERBITRANK2_Lane3_OFF (12) + #define DDRDATA7CH1_CR_RXPERBITRANK2_Lane3_WID ( 4) + #define DDRDATA7CH1_CR_RXPERBITRANK2_Lane3_MSK (0x0000F000) + #define DDRDATA7CH1_CR_RXPERBITRANK2_Lane3_MAX (0x0000000F) + #define DDRDATA7CH1_CR_RXPERBITRANK2_Lane4_OFF (16) + #define DDRDATA7CH1_CR_RXPERBITRANK2_Lane4_WID ( 4) + #define DDRDATA7CH1_CR_RXPERBITRANK2_Lane4_MSK (0x000F0000) + #define DDRDATA7CH1_CR_RXPERBITRANK2_Lane4_MAX (0x0000000F) + #define DDRDATA7CH1_CR_RXPERBITRANK2_Lane5_OFF (20) + #define DDRDATA7CH1_CR_RXPERBITRANK2_Lane5_WID ( 4) + #define DDRDATA7CH1_CR_RXPERBITRANK2_Lane5_MSK (0x00F00000) + #define DDRDATA7CH1_CR_RXPERBITRANK2_Lane5_MAX (0x0000000F) + #define DDRDATA7CH1_CR_RXPERBITRANK2_Lane6_OFF (24) + #define DDRDATA7CH1_CR_RXPERBITRANK2_Lane6_WID ( 4) + #define DDRDATA7CH1_CR_RXPERBITRANK2_Lane6_MSK (0x0F000000) + #define DDRDATA7CH1_CR_RXPERBITRANK2_Lane6_MAX (0x0000000F) + #define DDRDATA7CH1_CR_RXPERBITRANK2_Lane7_OFF (28) + #define DDRDATA7CH1_CR_RXPERBITRANK2_Lane7_WID ( 4) + #define DDRDATA7CH1_CR_RXPERBITRANK2_Lane7_MSK (0xF0000000) + #define DDRDATA7CH1_CR_RXPERBITRANK2_Lane7_MAX (0x0000000F) + +#define DDRDATA7CH1_CR_RXPERBITRANK3_REG (0x00000F1C) + #define DDRDATA7CH1_CR_RXPERBITRANK3_Lane0_OFF ( 0) + #define DDRDATA7CH1_CR_RXPERBITRANK3_Lane0_WID ( 4) + #define DDRDATA7CH1_CR_RXPERBITRANK3_Lane0_MSK (0x0000000F) + #define DDRDATA7CH1_CR_RXPERBITRANK3_Lane0_MAX (0x0000000F) + #define DDRDATA7CH1_CR_RXPERBITRANK3_Lane1_OFF ( 4) + #define DDRDATA7CH1_CR_RXPERBITRANK3_Lane1_WID ( 4) + #define DDRDATA7CH1_CR_RXPERBITRANK3_Lane1_MSK (0x000000F0) + #define DDRDATA7CH1_CR_RXPERBITRANK3_Lane1_MAX (0x0000000F) + #define DDRDATA7CH1_CR_RXPERBITRANK3_Lane2_OFF ( 8) + #define DDRDATA7CH1_CR_RXPERBITRANK3_Lane2_WID ( 4) + #define DDRDATA7CH1_CR_RXPERBITRANK3_Lane2_MSK (0x00000F00) + #define DDRDATA7CH1_CR_RXPERBITRANK3_Lane2_MAX (0x0000000F) + #define DDRDATA7CH1_CR_RXPERBITRANK3_Lane3_OFF (12) + #define DDRDATA7CH1_CR_RXPERBITRANK3_Lane3_WID ( 4) + #define DDRDATA7CH1_CR_RXPERBITRANK3_Lane3_MSK (0x0000F000) + #define DDRDATA7CH1_CR_RXPERBITRANK3_Lane3_MAX (0x0000000F) + #define DDRDATA7CH1_CR_RXPERBITRANK3_Lane4_OFF (16) + #define DDRDATA7CH1_CR_RXPERBITRANK3_Lane4_WID ( 4) + #define DDRDATA7CH1_CR_RXPERBITRANK3_Lane4_MSK (0x000F0000) + #define DDRDATA7CH1_CR_RXPERBITRANK3_Lane4_MAX (0x0000000F) + #define DDRDATA7CH1_CR_RXPERBITRANK3_Lane5_OFF (20) + #define DDRDATA7CH1_CR_RXPERBITRANK3_Lane5_WID ( 4) + #define DDRDATA7CH1_CR_RXPERBITRANK3_Lane5_MSK (0x00F00000) + #define DDRDATA7CH1_CR_RXPERBITRANK3_Lane5_MAX (0x0000000F) + #define DDRDATA7CH1_CR_RXPERBITRANK3_Lane6_OFF (24) + #define DDRDATA7CH1_CR_RXPERBITRANK3_Lane6_WID ( 4) + #define DDRDATA7CH1_CR_RXPERBITRANK3_Lane6_MSK (0x0F000000) + #define DDRDATA7CH1_CR_RXPERBITRANK3_Lane6_MAX (0x0000000F) + #define DDRDATA7CH1_CR_RXPERBITRANK3_Lane7_OFF (28) + #define DDRDATA7CH1_CR_RXPERBITRANK3_Lane7_WID ( 4) + #define DDRDATA7CH1_CR_RXPERBITRANK3_Lane7_MSK (0xF0000000) + #define DDRDATA7CH1_CR_RXPERBITRANK3_Lane7_MAX (0x0000000F) + +#define DDRDATA7CH1_CR_TXTRAINRANK0_REG (0x00000F20) + #define DDRDATA7CH1_CR_TXTRAINRANK0_TxDqDelay_OFF ( 0) + #define DDRDATA7CH1_CR_TXTRAINRANK0_TxDqDelay_WID ( 9) + #define DDRDATA7CH1_CR_TXTRAINRANK0_TxDqDelay_MSK (0x000001FF) + #define DDRDATA7CH1_CR_TXTRAINRANK0_TxDqDelay_MAX (0x000001FF) + #define DDRDATA7CH1_CR_TXTRAINRANK0_TxDqsDelay_OFF ( 9) + #define DDRDATA7CH1_CR_TXTRAINRANK0_TxDqsDelay_WID ( 9) + #define DDRDATA7CH1_CR_TXTRAINRANK0_TxDqsDelay_MSK (0x0003FE00) + #define DDRDATA7CH1_CR_TXTRAINRANK0_TxDqsDelay_MAX (0x000001FF) + #define DDRDATA7CH1_CR_TXTRAINRANK0_Spare0_OFF (18) + #define DDRDATA7CH1_CR_TXTRAINRANK0_Spare0_WID ( 2) + #define DDRDATA7CH1_CR_TXTRAINRANK0_Spare0_MSK (0x000C0000) + #define DDRDATA7CH1_CR_TXTRAINRANK0_Spare0_MAX (0x00000003) + #define DDRDATA7CH1_CR_TXTRAINRANK0_TxEqualization_OFF (20) + #define DDRDATA7CH1_CR_TXTRAINRANK0_TxEqualization_WID ( 6) + #define DDRDATA7CH1_CR_TXTRAINRANK0_TxEqualization_MSK (0x03F00000) + #define DDRDATA7CH1_CR_TXTRAINRANK0_TxEqualization_MAX (0x0000003F) + #define DDRDATA7CH1_CR_TXTRAINRANK0_Spare1_OFF (26) + #define DDRDATA7CH1_CR_TXTRAINRANK0_Spare1_WID ( 6) + #define DDRDATA7CH1_CR_TXTRAINRANK0_Spare1_MSK (0xFC000000) + #define DDRDATA7CH1_CR_TXTRAINRANK0_Spare1_MAX (0x0000003F) + +#define DDRDATA7CH1_CR_TXTRAINRANK1_REG (0x00000F24) + #define DDRDATA7CH1_CR_TXTRAINRANK1_TxDqDelay_OFF ( 0) + #define DDRDATA7CH1_CR_TXTRAINRANK1_TxDqDelay_WID ( 9) + #define DDRDATA7CH1_CR_TXTRAINRANK1_TxDqDelay_MSK (0x000001FF) + #define DDRDATA7CH1_CR_TXTRAINRANK1_TxDqDelay_MAX (0x000001FF) + #define DDRDATA7CH1_CR_TXTRAINRANK1_TxDqsDelay_OFF ( 9) + #define DDRDATA7CH1_CR_TXTRAINRANK1_TxDqsDelay_WID ( 9) + #define DDRDATA7CH1_CR_TXTRAINRANK1_TxDqsDelay_MSK (0x0003FE00) + #define DDRDATA7CH1_CR_TXTRAINRANK1_TxDqsDelay_MAX (0x000001FF) + #define DDRDATA7CH1_CR_TXTRAINRANK1_Spare0_OFF (18) + #define DDRDATA7CH1_CR_TXTRAINRANK1_Spare0_WID ( 2) + #define DDRDATA7CH1_CR_TXTRAINRANK1_Spare0_MSK (0x000C0000) + #define DDRDATA7CH1_CR_TXTRAINRANK1_Spare0_MAX (0x00000003) + #define DDRDATA7CH1_CR_TXTRAINRANK1_TxEqualization_OFF (20) + #define DDRDATA7CH1_CR_TXTRAINRANK1_TxEqualization_WID ( 6) + #define DDRDATA7CH1_CR_TXTRAINRANK1_TxEqualization_MSK (0x03F00000) + #define DDRDATA7CH1_CR_TXTRAINRANK1_TxEqualization_MAX (0x0000003F) + #define DDRDATA7CH1_CR_TXTRAINRANK1_Spare1_OFF (26) + #define DDRDATA7CH1_CR_TXTRAINRANK1_Spare1_WID ( 6) + #define DDRDATA7CH1_CR_TXTRAINRANK1_Spare1_MSK (0xFC000000) + #define DDRDATA7CH1_CR_TXTRAINRANK1_Spare1_MAX (0x0000003F) + +#define DDRDATA7CH1_CR_TXTRAINRANK2_REG (0x00000F28) + #define DDRDATA7CH1_CR_TXTRAINRANK2_TxDqDelay_OFF ( 0) + #define DDRDATA7CH1_CR_TXTRAINRANK2_TxDqDelay_WID ( 9) + #define DDRDATA7CH1_CR_TXTRAINRANK2_TxDqDelay_MSK (0x000001FF) + #define DDRDATA7CH1_CR_TXTRAINRANK2_TxDqDelay_MAX (0x000001FF) + #define DDRDATA7CH1_CR_TXTRAINRANK2_TxDqsDelay_OFF ( 9) + #define DDRDATA7CH1_CR_TXTRAINRANK2_TxDqsDelay_WID ( 9) + #define DDRDATA7CH1_CR_TXTRAINRANK2_TxDqsDelay_MSK (0x0003FE00) + #define DDRDATA7CH1_CR_TXTRAINRANK2_TxDqsDelay_MAX (0x000001FF) + #define DDRDATA7CH1_CR_TXTRAINRANK2_Spare0_OFF (18) + #define DDRDATA7CH1_CR_TXTRAINRANK2_Spare0_WID ( 2) + #define DDRDATA7CH1_CR_TXTRAINRANK2_Spare0_MSK (0x000C0000) + #define DDRDATA7CH1_CR_TXTRAINRANK2_Spare0_MAX (0x00000003) + #define DDRDATA7CH1_CR_TXTRAINRANK2_TxEqualization_OFF (20) + #define DDRDATA7CH1_CR_TXTRAINRANK2_TxEqualization_WID ( 6) + #define DDRDATA7CH1_CR_TXTRAINRANK2_TxEqualization_MSK (0x03F00000) + #define DDRDATA7CH1_CR_TXTRAINRANK2_TxEqualization_MAX (0x0000003F) + #define DDRDATA7CH1_CR_TXTRAINRANK2_Spare1_OFF (26) + #define DDRDATA7CH1_CR_TXTRAINRANK2_Spare1_WID ( 6) + #define DDRDATA7CH1_CR_TXTRAINRANK2_Spare1_MSK (0xFC000000) + #define DDRDATA7CH1_CR_TXTRAINRANK2_Spare1_MAX (0x0000003F) + +#define DDRDATA7CH1_CR_TXTRAINRANK3_REG (0x00000F2C) + #define DDRDATA7CH1_CR_TXTRAINRANK3_TxDqDelay_OFF ( 0) + #define DDRDATA7CH1_CR_TXTRAINRANK3_TxDqDelay_WID ( 9) + #define DDRDATA7CH1_CR_TXTRAINRANK3_TxDqDelay_MSK (0x000001FF) + #define DDRDATA7CH1_CR_TXTRAINRANK3_TxDqDelay_MAX (0x000001FF) + #define DDRDATA7CH1_CR_TXTRAINRANK3_TxDqsDelay_OFF ( 9) + #define DDRDATA7CH1_CR_TXTRAINRANK3_TxDqsDelay_WID ( 9) + #define DDRDATA7CH1_CR_TXTRAINRANK3_TxDqsDelay_MSK (0x0003FE00) + #define DDRDATA7CH1_CR_TXTRAINRANK3_TxDqsDelay_MAX (0x000001FF) + #define DDRDATA7CH1_CR_TXTRAINRANK3_Spare0_OFF (18) + #define DDRDATA7CH1_CR_TXTRAINRANK3_Spare0_WID ( 2) + #define DDRDATA7CH1_CR_TXTRAINRANK3_Spare0_MSK (0x000C0000) + #define DDRDATA7CH1_CR_TXTRAINRANK3_Spare0_MAX (0x00000003) + #define DDRDATA7CH1_CR_TXTRAINRANK3_TxEqualization_OFF (20) + #define DDRDATA7CH1_CR_TXTRAINRANK3_TxEqualization_WID ( 6) + #define DDRDATA7CH1_CR_TXTRAINRANK3_TxEqualization_MSK (0x03F00000) + #define DDRDATA7CH1_CR_TXTRAINRANK3_TxEqualization_MAX (0x0000003F) + #define DDRDATA7CH1_CR_TXTRAINRANK3_Spare1_OFF (26) + #define DDRDATA7CH1_CR_TXTRAINRANK3_Spare1_WID ( 6) + #define DDRDATA7CH1_CR_TXTRAINRANK3_Spare1_MSK (0xFC000000) + #define DDRDATA7CH1_CR_TXTRAINRANK3_Spare1_MAX (0x0000003F) + +#define DDRDATA7CH1_CR_TXPERBITRANK0_REG (0x00000F30) + #define DDRDATA7CH1_CR_TXPERBITRANK0_Lane0_OFF ( 0) + #define DDRDATA7CH1_CR_TXPERBITRANK0_Lane0_WID ( 4) + #define DDRDATA7CH1_CR_TXPERBITRANK0_Lane0_MSK (0x0000000F) + #define DDRDATA7CH1_CR_TXPERBITRANK0_Lane0_MAX (0x0000000F) + #define DDRDATA7CH1_CR_TXPERBITRANK0_Lane1_OFF ( 4) + #define DDRDATA7CH1_CR_TXPERBITRANK0_Lane1_WID ( 4) + #define DDRDATA7CH1_CR_TXPERBITRANK0_Lane1_MSK (0x000000F0) + #define DDRDATA7CH1_CR_TXPERBITRANK0_Lane1_MAX (0x0000000F) + #define DDRDATA7CH1_CR_TXPERBITRANK0_Lane2_OFF ( 8) + #define DDRDATA7CH1_CR_TXPERBITRANK0_Lane2_WID ( 4) + #define DDRDATA7CH1_CR_TXPERBITRANK0_Lane2_MSK (0x00000F00) + #define DDRDATA7CH1_CR_TXPERBITRANK0_Lane2_MAX (0x0000000F) + #define DDRDATA7CH1_CR_TXPERBITRANK0_Lane3_OFF (12) + #define DDRDATA7CH1_CR_TXPERBITRANK0_Lane3_WID ( 4) + #define DDRDATA7CH1_CR_TXPERBITRANK0_Lane3_MSK (0x0000F000) + #define DDRDATA7CH1_CR_TXPERBITRANK0_Lane3_MAX (0x0000000F) + #define DDRDATA7CH1_CR_TXPERBITRANK0_Lane4_OFF (16) + #define DDRDATA7CH1_CR_TXPERBITRANK0_Lane4_WID ( 4) + #define DDRDATA7CH1_CR_TXPERBITRANK0_Lane4_MSK (0x000F0000) + #define DDRDATA7CH1_CR_TXPERBITRANK0_Lane4_MAX (0x0000000F) + #define DDRDATA7CH1_CR_TXPERBITRANK0_Lane5_OFF (20) + #define DDRDATA7CH1_CR_TXPERBITRANK0_Lane5_WID ( 4) + #define DDRDATA7CH1_CR_TXPERBITRANK0_Lane5_MSK (0x00F00000) + #define DDRDATA7CH1_CR_TXPERBITRANK0_Lane5_MAX (0x0000000F) + #define DDRDATA7CH1_CR_TXPERBITRANK0_Lane6_OFF (24) + #define DDRDATA7CH1_CR_TXPERBITRANK0_Lane6_WID ( 4) + #define DDRDATA7CH1_CR_TXPERBITRANK0_Lane6_MSK (0x0F000000) + #define DDRDATA7CH1_CR_TXPERBITRANK0_Lane6_MAX (0x0000000F) + #define DDRDATA7CH1_CR_TXPERBITRANK0_Lane7_OFF (28) + #define DDRDATA7CH1_CR_TXPERBITRANK0_Lane7_WID ( 4) + #define DDRDATA7CH1_CR_TXPERBITRANK0_Lane7_MSK (0xF0000000) + #define DDRDATA7CH1_CR_TXPERBITRANK0_Lane7_MAX (0x0000000F) + +#define DDRDATA7CH1_CR_TXPERBITRANK1_REG (0x00000F34) + #define DDRDATA7CH1_CR_TXPERBITRANK1_Lane0_OFF ( 0) + #define DDRDATA7CH1_CR_TXPERBITRANK1_Lane0_WID ( 4) + #define DDRDATA7CH1_CR_TXPERBITRANK1_Lane0_MSK (0x0000000F) + #define DDRDATA7CH1_CR_TXPERBITRANK1_Lane0_MAX (0x0000000F) + #define DDRDATA7CH1_CR_TXPERBITRANK1_Lane1_OFF ( 4) + #define DDRDATA7CH1_CR_TXPERBITRANK1_Lane1_WID ( 4) + #define DDRDATA7CH1_CR_TXPERBITRANK1_Lane1_MSK (0x000000F0) + #define DDRDATA7CH1_CR_TXPERBITRANK1_Lane1_MAX (0x0000000F) + #define DDRDATA7CH1_CR_TXPERBITRANK1_Lane2_OFF ( 8) + #define DDRDATA7CH1_CR_TXPERBITRANK1_Lane2_WID ( 4) + #define DDRDATA7CH1_CR_TXPERBITRANK1_Lane2_MSK (0x00000F00) + #define DDRDATA7CH1_CR_TXPERBITRANK1_Lane2_MAX (0x0000000F) + #define DDRDATA7CH1_CR_TXPERBITRANK1_Lane3_OFF (12) + #define DDRDATA7CH1_CR_TXPERBITRANK1_Lane3_WID ( 4) + #define DDRDATA7CH1_CR_TXPERBITRANK1_Lane3_MSK (0x0000F000) + #define DDRDATA7CH1_CR_TXPERBITRANK1_Lane3_MAX (0x0000000F) + #define DDRDATA7CH1_CR_TXPERBITRANK1_Lane4_OFF (16) + #define DDRDATA7CH1_CR_TXPERBITRANK1_Lane4_WID ( 4) + #define DDRDATA7CH1_CR_TXPERBITRANK1_Lane4_MSK (0x000F0000) + #define DDRDATA7CH1_CR_TXPERBITRANK1_Lane4_MAX (0x0000000F) + #define DDRDATA7CH1_CR_TXPERBITRANK1_Lane5_OFF (20) + #define DDRDATA7CH1_CR_TXPERBITRANK1_Lane5_WID ( 4) + #define DDRDATA7CH1_CR_TXPERBITRANK1_Lane5_MSK (0x00F00000) + #define DDRDATA7CH1_CR_TXPERBITRANK1_Lane5_MAX (0x0000000F) + #define DDRDATA7CH1_CR_TXPERBITRANK1_Lane6_OFF (24) + #define DDRDATA7CH1_CR_TXPERBITRANK1_Lane6_WID ( 4) + #define DDRDATA7CH1_CR_TXPERBITRANK1_Lane6_MSK (0x0F000000) + #define DDRDATA7CH1_CR_TXPERBITRANK1_Lane6_MAX (0x0000000F) + #define DDRDATA7CH1_CR_TXPERBITRANK1_Lane7_OFF (28) + #define DDRDATA7CH1_CR_TXPERBITRANK1_Lane7_WID ( 4) + #define DDRDATA7CH1_CR_TXPERBITRANK1_Lane7_MSK (0xF0000000) + #define DDRDATA7CH1_CR_TXPERBITRANK1_Lane7_MAX (0x0000000F) + +#define DDRDATA7CH1_CR_TXPERBITRANK2_REG (0x00000F38) + #define DDRDATA7CH1_CR_TXPERBITRANK2_Lane0_OFF ( 0) + #define DDRDATA7CH1_CR_TXPERBITRANK2_Lane0_WID ( 4) + #define DDRDATA7CH1_CR_TXPERBITRANK2_Lane0_MSK (0x0000000F) + #define DDRDATA7CH1_CR_TXPERBITRANK2_Lane0_MAX (0x0000000F) + #define DDRDATA7CH1_CR_TXPERBITRANK2_Lane1_OFF ( 4) + #define DDRDATA7CH1_CR_TXPERBITRANK2_Lane1_WID ( 4) + #define DDRDATA7CH1_CR_TXPERBITRANK2_Lane1_MSK (0x000000F0) + #define DDRDATA7CH1_CR_TXPERBITRANK2_Lane1_MAX (0x0000000F) + #define DDRDATA7CH1_CR_TXPERBITRANK2_Lane2_OFF ( 8) + #define DDRDATA7CH1_CR_TXPERBITRANK2_Lane2_WID ( 4) + #define DDRDATA7CH1_CR_TXPERBITRANK2_Lane2_MSK (0x00000F00) + #define DDRDATA7CH1_CR_TXPERBITRANK2_Lane2_MAX (0x0000000F) + #define DDRDATA7CH1_CR_TXPERBITRANK2_Lane3_OFF (12) + #define DDRDATA7CH1_CR_TXPERBITRANK2_Lane3_WID ( 4) + #define DDRDATA7CH1_CR_TXPERBITRANK2_Lane3_MSK (0x0000F000) + #define DDRDATA7CH1_CR_TXPERBITRANK2_Lane3_MAX (0x0000000F) + #define DDRDATA7CH1_CR_TXPERBITRANK2_Lane4_OFF (16) + #define DDRDATA7CH1_CR_TXPERBITRANK2_Lane4_WID ( 4) + #define DDRDATA7CH1_CR_TXPERBITRANK2_Lane4_MSK (0x000F0000) + #define DDRDATA7CH1_CR_TXPERBITRANK2_Lane4_MAX (0x0000000F) + #define DDRDATA7CH1_CR_TXPERBITRANK2_Lane5_OFF (20) + #define DDRDATA7CH1_CR_TXPERBITRANK2_Lane5_WID ( 4) + #define DDRDATA7CH1_CR_TXPERBITRANK2_Lane5_MSK (0x00F00000) + #define DDRDATA7CH1_CR_TXPERBITRANK2_Lane5_MAX (0x0000000F) + #define DDRDATA7CH1_CR_TXPERBITRANK2_Lane6_OFF (24) + #define DDRDATA7CH1_CR_TXPERBITRANK2_Lane6_WID ( 4) + #define DDRDATA7CH1_CR_TXPERBITRANK2_Lane6_MSK (0x0F000000) + #define DDRDATA7CH1_CR_TXPERBITRANK2_Lane6_MAX (0x0000000F) + #define DDRDATA7CH1_CR_TXPERBITRANK2_Lane7_OFF (28) + #define DDRDATA7CH1_CR_TXPERBITRANK2_Lane7_WID ( 4) + #define DDRDATA7CH1_CR_TXPERBITRANK2_Lane7_MSK (0xF0000000) + #define DDRDATA7CH1_CR_TXPERBITRANK2_Lane7_MAX (0x0000000F) + +#define DDRDATA7CH1_CR_TXPERBITRANK3_REG (0x00000F3C) + #define DDRDATA7CH1_CR_TXPERBITRANK3_Lane0_OFF ( 0) + #define DDRDATA7CH1_CR_TXPERBITRANK3_Lane0_WID ( 4) + #define DDRDATA7CH1_CR_TXPERBITRANK3_Lane0_MSK (0x0000000F) + #define DDRDATA7CH1_CR_TXPERBITRANK3_Lane0_MAX (0x0000000F) + #define DDRDATA7CH1_CR_TXPERBITRANK3_Lane1_OFF ( 4) + #define DDRDATA7CH1_CR_TXPERBITRANK3_Lane1_WID ( 4) + #define DDRDATA7CH1_CR_TXPERBITRANK3_Lane1_MSK (0x000000F0) + #define DDRDATA7CH1_CR_TXPERBITRANK3_Lane1_MAX (0x0000000F) + #define DDRDATA7CH1_CR_TXPERBITRANK3_Lane2_OFF ( 8) + #define DDRDATA7CH1_CR_TXPERBITRANK3_Lane2_WID ( 4) + #define DDRDATA7CH1_CR_TXPERBITRANK3_Lane2_MSK (0x00000F00) + #define DDRDATA7CH1_CR_TXPERBITRANK3_Lane2_MAX (0x0000000F) + #define DDRDATA7CH1_CR_TXPERBITRANK3_Lane3_OFF (12) + #define DDRDATA7CH1_CR_TXPERBITRANK3_Lane3_WID ( 4) + #define DDRDATA7CH1_CR_TXPERBITRANK3_Lane3_MSK (0x0000F000) + #define DDRDATA7CH1_CR_TXPERBITRANK3_Lane3_MAX (0x0000000F) + #define DDRDATA7CH1_CR_TXPERBITRANK3_Lane4_OFF (16) + #define DDRDATA7CH1_CR_TXPERBITRANK3_Lane4_WID ( 4) + #define DDRDATA7CH1_CR_TXPERBITRANK3_Lane4_MSK (0x000F0000) + #define DDRDATA7CH1_CR_TXPERBITRANK3_Lane4_MAX (0x0000000F) + #define DDRDATA7CH1_CR_TXPERBITRANK3_Lane5_OFF (20) + #define DDRDATA7CH1_CR_TXPERBITRANK3_Lane5_WID ( 4) + #define DDRDATA7CH1_CR_TXPERBITRANK3_Lane5_MSK (0x00F00000) + #define DDRDATA7CH1_CR_TXPERBITRANK3_Lane5_MAX (0x0000000F) + #define DDRDATA7CH1_CR_TXPERBITRANK3_Lane6_OFF (24) + #define DDRDATA7CH1_CR_TXPERBITRANK3_Lane6_WID ( 4) + #define DDRDATA7CH1_CR_TXPERBITRANK3_Lane6_MSK (0x0F000000) + #define DDRDATA7CH1_CR_TXPERBITRANK3_Lane6_MAX (0x0000000F) + #define DDRDATA7CH1_CR_TXPERBITRANK3_Lane7_OFF (28) + #define DDRDATA7CH1_CR_TXPERBITRANK3_Lane7_WID ( 4) + #define DDRDATA7CH1_CR_TXPERBITRANK3_Lane7_MSK (0xF0000000) + #define DDRDATA7CH1_CR_TXPERBITRANK3_Lane7_MAX (0x0000000F) + +#define DDRDATA7CH1_CR_RCOMPDATA0_REG (0x00000F40) + #define DDRDATA7CH1_CR_RCOMPDATA0_RcompDrvUp_OFF ( 0) + #define DDRDATA7CH1_CR_RCOMPDATA0_RcompDrvUp_WID ( 6) + #define DDRDATA7CH1_CR_RCOMPDATA0_RcompDrvUp_MSK (0x0000003F) + #define DDRDATA7CH1_CR_RCOMPDATA0_RcompDrvUp_MAX (0x0000003F) + #define DDRDATA7CH1_CR_RCOMPDATA0_Spare0_OFF ( 6) + #define DDRDATA7CH1_CR_RCOMPDATA0_Spare0_WID ( 3) + #define DDRDATA7CH1_CR_RCOMPDATA0_Spare0_MSK (0x000001C0) + #define DDRDATA7CH1_CR_RCOMPDATA0_Spare0_MAX (0x00000007) + #define DDRDATA7CH1_CR_RCOMPDATA0_RcompDrvDown_OFF ( 9) + #define DDRDATA7CH1_CR_RCOMPDATA0_RcompDrvDown_WID ( 6) + #define DDRDATA7CH1_CR_RCOMPDATA0_RcompDrvDown_MSK (0x00007E00) + #define DDRDATA7CH1_CR_RCOMPDATA0_RcompDrvDown_MAX (0x0000003F) + #define DDRDATA7CH1_CR_RCOMPDATA0_VTComp_OFF (15) + #define DDRDATA7CH1_CR_RCOMPDATA0_VTComp_WID ( 5) + #define DDRDATA7CH1_CR_RCOMPDATA0_VTComp_MSK (0x000F8000) + #define DDRDATA7CH1_CR_RCOMPDATA0_VTComp_MAX (0x0000001F) + #define DDRDATA7CH1_CR_RCOMPDATA0_TcoComp_OFF (20) + #define DDRDATA7CH1_CR_RCOMPDATA0_TcoComp_WID ( 6) + #define DDRDATA7CH1_CR_RCOMPDATA0_TcoComp_MSK (0x03F00000) + #define DDRDATA7CH1_CR_RCOMPDATA0_TcoComp_MAX (0x0000003F) + #define DDRDATA7CH1_CR_RCOMPDATA0_SlewRateComp_OFF (26) + #define DDRDATA7CH1_CR_RCOMPDATA0_SlewRateComp_WID ( 5) + #define DDRDATA7CH1_CR_RCOMPDATA0_SlewRateComp_MSK (0x7C000000) + #define DDRDATA7CH1_CR_RCOMPDATA0_SlewRateComp_MAX (0x0000001F) + #define DDRDATA7CH1_CR_RCOMPDATA0_Spare2_OFF (31) + #define DDRDATA7CH1_CR_RCOMPDATA0_Spare2_WID ( 1) + #define DDRDATA7CH1_CR_RCOMPDATA0_Spare2_MSK (0x80000000) + #define DDRDATA7CH1_CR_RCOMPDATA0_Spare2_MAX (0x00000001) + +#define DDRDATA7CH1_CR_RCOMPDATA1_REG (0x00000F44) + #define DDRDATA7CH1_CR_RCOMPDATA1_RcompOdtUp_OFF ( 0) + #define DDRDATA7CH1_CR_RCOMPDATA1_RcompOdtUp_WID ( 6) + #define DDRDATA7CH1_CR_RCOMPDATA1_RcompOdtUp_MSK (0x0000003F) + #define DDRDATA7CH1_CR_RCOMPDATA1_RcompOdtUp_MAX (0x0000003F) + #define DDRDATA7CH1_CR_RCOMPDATA1_Spare0_OFF ( 6) + #define DDRDATA7CH1_CR_RCOMPDATA1_Spare0_WID ( 3) + #define DDRDATA7CH1_CR_RCOMPDATA1_Spare0_MSK (0x000001C0) + #define DDRDATA7CH1_CR_RCOMPDATA1_Spare0_MAX (0x00000007) + #define DDRDATA7CH1_CR_RCOMPDATA1_RcompOdtDown_OFF ( 9) + #define DDRDATA7CH1_CR_RCOMPDATA1_RcompOdtDown_WID ( 6) + #define DDRDATA7CH1_CR_RCOMPDATA1_RcompOdtDown_MSK (0x00007E00) + #define DDRDATA7CH1_CR_RCOMPDATA1_RcompOdtDown_MAX (0x0000003F) + #define DDRDATA7CH1_CR_RCOMPDATA1_Spare1_OFF (15) + #define DDRDATA7CH1_CR_RCOMPDATA1_Spare1_WID ( 1) + #define DDRDATA7CH1_CR_RCOMPDATA1_Spare1_MSK (0x00008000) + #define DDRDATA7CH1_CR_RCOMPDATA1_Spare1_MAX (0x00000001) + #define DDRDATA7CH1_CR_RCOMPDATA1_PanicDrvDn_OFF (16) + #define DDRDATA7CH1_CR_RCOMPDATA1_PanicDrvDn_WID ( 6) + #define DDRDATA7CH1_CR_RCOMPDATA1_PanicDrvDn_MSK (0x003F0000) + #define DDRDATA7CH1_CR_RCOMPDATA1_PanicDrvDn_MAX (0x0000003F) + #define DDRDATA7CH1_CR_RCOMPDATA1_PanicDrvUp_OFF (22) + #define DDRDATA7CH1_CR_RCOMPDATA1_PanicDrvUp_WID ( 6) + #define DDRDATA7CH1_CR_RCOMPDATA1_PanicDrvUp_MSK (0x0FC00000) + #define DDRDATA7CH1_CR_RCOMPDATA1_PanicDrvUp_MAX (0x0000003F) + #define DDRDATA7CH1_CR_RCOMPDATA1_LevelShifterComp_OFF (28) + #define DDRDATA7CH1_CR_RCOMPDATA1_LevelShifterComp_WID ( 3) + #define DDRDATA7CH1_CR_RCOMPDATA1_LevelShifterComp_MSK (0x70000000) + #define DDRDATA7CH1_CR_RCOMPDATA1_LevelShifterComp_MAX (0x00000007) + #define DDRDATA7CH1_CR_RCOMPDATA1_Spare2_OFF (31) + #define DDRDATA7CH1_CR_RCOMPDATA1_Spare2_WID ( 1) + #define DDRDATA7CH1_CR_RCOMPDATA1_Spare2_MSK (0x80000000) + #define DDRDATA7CH1_CR_RCOMPDATA1_Spare2_MAX (0x00000001) + +#define DDRDATA7CH1_CR_TXXTALK_REG (0x00000F48) + #define DDRDATA7CH1_CR_TXXTALK_Lane0_OFF ( 0) + #define DDRDATA7CH1_CR_TXXTALK_Lane0_WID ( 4) + #define DDRDATA7CH1_CR_TXXTALK_Lane0_MSK (0x0000000F) + #define DDRDATA7CH1_CR_TXXTALK_Lane0_MAX (0x0000000F) + #define DDRDATA7CH1_CR_TXXTALK_Lane1_OFF ( 4) + #define DDRDATA7CH1_CR_TXXTALK_Lane1_WID ( 4) + #define DDRDATA7CH1_CR_TXXTALK_Lane1_MSK (0x000000F0) + #define DDRDATA7CH1_CR_TXXTALK_Lane1_MAX (0x0000000F) + #define DDRDATA7CH1_CR_TXXTALK_Lane2_OFF ( 8) + #define DDRDATA7CH1_CR_TXXTALK_Lane2_WID ( 4) + #define DDRDATA7CH1_CR_TXXTALK_Lane2_MSK (0x00000F00) + #define DDRDATA7CH1_CR_TXXTALK_Lane2_MAX (0x0000000F) + #define DDRDATA7CH1_CR_TXXTALK_Lane3_OFF (12) + #define DDRDATA7CH1_CR_TXXTALK_Lane3_WID ( 4) + #define DDRDATA7CH1_CR_TXXTALK_Lane3_MSK (0x0000F000) + #define DDRDATA7CH1_CR_TXXTALK_Lane3_MAX (0x0000000F) + #define DDRDATA7CH1_CR_TXXTALK_Lane4_OFF (16) + #define DDRDATA7CH1_CR_TXXTALK_Lane4_WID ( 4) + #define DDRDATA7CH1_CR_TXXTALK_Lane4_MSK (0x000F0000) + #define DDRDATA7CH1_CR_TXXTALK_Lane4_MAX (0x0000000F) + #define DDRDATA7CH1_CR_TXXTALK_Lane5_OFF (20) + #define DDRDATA7CH1_CR_TXXTALK_Lane5_WID ( 4) + #define DDRDATA7CH1_CR_TXXTALK_Lane5_MSK (0x00F00000) + #define DDRDATA7CH1_CR_TXXTALK_Lane5_MAX (0x0000000F) + #define DDRDATA7CH1_CR_TXXTALK_Lane6_OFF (24) + #define DDRDATA7CH1_CR_TXXTALK_Lane6_WID ( 4) + #define DDRDATA7CH1_CR_TXXTALK_Lane6_MSK (0x0F000000) + #define DDRDATA7CH1_CR_TXXTALK_Lane6_MAX (0x0000000F) + #define DDRDATA7CH1_CR_TXXTALK_Lane7_OFF (28) + #define DDRDATA7CH1_CR_TXXTALK_Lane7_WID ( 4) + #define DDRDATA7CH1_CR_TXXTALK_Lane7_MSK (0xF0000000) + #define DDRDATA7CH1_CR_TXXTALK_Lane7_MAX (0x0000000F) + +#define DDRDATA7CH1_CR_RXOFFSETVDQ_REG (0x00000F4C) + #define DDRDATA7CH1_CR_RXOFFSETVDQ_Lane0_OFF ( 0) + #define DDRDATA7CH1_CR_RXOFFSETVDQ_Lane0_WID ( 4) + #define DDRDATA7CH1_CR_RXOFFSETVDQ_Lane0_MSK (0x0000000F) + #define DDRDATA7CH1_CR_RXOFFSETVDQ_Lane0_MAX (0x0000000F) + #define DDRDATA7CH1_CR_RXOFFSETVDQ_Lane1_OFF ( 4) + #define DDRDATA7CH1_CR_RXOFFSETVDQ_Lane1_WID ( 4) + #define DDRDATA7CH1_CR_RXOFFSETVDQ_Lane1_MSK (0x000000F0) + #define DDRDATA7CH1_CR_RXOFFSETVDQ_Lane1_MAX (0x0000000F) + #define DDRDATA7CH1_CR_RXOFFSETVDQ_Lane2_OFF ( 8) + #define DDRDATA7CH1_CR_RXOFFSETVDQ_Lane2_WID ( 4) + #define DDRDATA7CH1_CR_RXOFFSETVDQ_Lane2_MSK (0x00000F00) + #define DDRDATA7CH1_CR_RXOFFSETVDQ_Lane2_MAX (0x0000000F) + #define DDRDATA7CH1_CR_RXOFFSETVDQ_Lane3_OFF (12) + #define DDRDATA7CH1_CR_RXOFFSETVDQ_Lane3_WID ( 4) + #define DDRDATA7CH1_CR_RXOFFSETVDQ_Lane3_MSK (0x0000F000) + #define DDRDATA7CH1_CR_RXOFFSETVDQ_Lane3_MAX (0x0000000F) + #define DDRDATA7CH1_CR_RXOFFSETVDQ_Lane4_OFF (16) + #define DDRDATA7CH1_CR_RXOFFSETVDQ_Lane4_WID ( 4) + #define DDRDATA7CH1_CR_RXOFFSETVDQ_Lane4_MSK (0x000F0000) + #define DDRDATA7CH1_CR_RXOFFSETVDQ_Lane4_MAX (0x0000000F) + #define DDRDATA7CH1_CR_RXOFFSETVDQ_Lane5_OFF (20) + #define DDRDATA7CH1_CR_RXOFFSETVDQ_Lane5_WID ( 4) + #define DDRDATA7CH1_CR_RXOFFSETVDQ_Lane5_MSK (0x00F00000) + #define DDRDATA7CH1_CR_RXOFFSETVDQ_Lane5_MAX (0x0000000F) + #define DDRDATA7CH1_CR_RXOFFSETVDQ_Lane6_OFF (24) + #define DDRDATA7CH1_CR_RXOFFSETVDQ_Lane6_WID ( 4) + #define DDRDATA7CH1_CR_RXOFFSETVDQ_Lane6_MSK (0x0F000000) + #define DDRDATA7CH1_CR_RXOFFSETVDQ_Lane6_MAX (0x0000000F) + #define DDRDATA7CH1_CR_RXOFFSETVDQ_Lane7_OFF (28) + #define DDRDATA7CH1_CR_RXOFFSETVDQ_Lane7_WID ( 4) + #define DDRDATA7CH1_CR_RXOFFSETVDQ_Lane7_MSK (0xF0000000) + #define DDRDATA7CH1_CR_RXOFFSETVDQ_Lane7_MAX (0x0000000F) + +#define DDRDATA7CH1_CR_DDRDATARESERVED_REG (0x00000F50) + #define DDRDATA7CH1_CR_DDRDATARESERVED_Spare_OFF ( 0) + #define DDRDATA7CH1_CR_DDRDATARESERVED_Spare_WID (32) + #define DDRDATA7CH1_CR_DDRDATARESERVED_Spare_MSK (0xFFFFFFFF) + #define DDRDATA7CH1_CR_DDRDATARESERVED_Spare_MAX (0xFFFFFFFF) + +#define DDRDATA7CH1_CR_DATATRAINFEEDBACK_REG (0x00000F54) + #define DDRDATA7CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_OFF ( 0) + #define DDRDATA7CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_WID ( 9) + #define DDRDATA7CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_MSK (0x000001FF) + #define DDRDATA7CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_MAX (0x000001FF) + #define DDRDATA7CH1_CR_DATATRAINFEEDBACK_Spare_OFF ( 9) + #define DDRDATA7CH1_CR_DATATRAINFEEDBACK_Spare_WID (23) + #define DDRDATA7CH1_CR_DATATRAINFEEDBACK_Spare_MSK (0xFFFFFE00) + #define DDRDATA7CH1_CR_DATATRAINFEEDBACK_Spare_MAX (0x007FFFFF) + +#define DDRDATA7CH1_CR_DLLPITESTANDADC_REG (0x00000F58) + #define DDRDATA7CH1_CR_DLLPITESTANDADC_RunTest_OFF ( 0) + #define DDRDATA7CH1_CR_DLLPITESTANDADC_RunTest_WID ( 1) + #define DDRDATA7CH1_CR_DLLPITESTANDADC_RunTest_MSK (0x00000001) + #define DDRDATA7CH1_CR_DLLPITESTANDADC_RunTest_MAX (0x00000001) + #define DDRDATA7CH1_CR_DLLPITESTANDADC_RunTest_DEF (0x00000000) + #define DDRDATA7CH1_CR_DLLPITESTANDADC_Load_OFF ( 1) + #define DDRDATA7CH1_CR_DLLPITESTANDADC_Load_WID ( 1) + #define DDRDATA7CH1_CR_DLLPITESTANDADC_Load_MSK (0x00000002) + #define DDRDATA7CH1_CR_DLLPITESTANDADC_Load_MAX (0x00000001) + #define DDRDATA7CH1_CR_DLLPITESTANDADC_Load_DEF (0x00000000) + #define DDRDATA7CH1_CR_DLLPITESTANDADC_ModeHVM_OFF ( 2) + #define DDRDATA7CH1_CR_DLLPITESTANDADC_ModeHVM_WID ( 1) + #define DDRDATA7CH1_CR_DLLPITESTANDADC_ModeHVM_MSK (0x00000004) + #define DDRDATA7CH1_CR_DLLPITESTANDADC_ModeHVM_MAX (0x00000001) + #define DDRDATA7CH1_CR_DLLPITESTANDADC_ModeHVM_DEF (0x00000000) + #define DDRDATA7CH1_CR_DLLPITESTANDADC_ModeDV_OFF ( 3) + #define DDRDATA7CH1_CR_DLLPITESTANDADC_ModeDV_WID ( 1) + #define DDRDATA7CH1_CR_DLLPITESTANDADC_ModeDV_MSK (0x00000008) + #define DDRDATA7CH1_CR_DLLPITESTANDADC_ModeDV_MAX (0x00000001) + #define DDRDATA7CH1_CR_DLLPITESTANDADC_ModeDV_DEF (0x00000000) + #define DDRDATA7CH1_CR_DLLPITESTANDADC_ModeADC_OFF ( 4) + #define DDRDATA7CH1_CR_DLLPITESTANDADC_ModeADC_WID ( 1) + #define DDRDATA7CH1_CR_DLLPITESTANDADC_ModeADC_MSK (0x00000010) + #define DDRDATA7CH1_CR_DLLPITESTANDADC_ModeADC_MAX (0x00000001) + #define DDRDATA7CH1_CR_DLLPITESTANDADC_ModeADC_DEF (0x00000000) + #define DDRDATA7CH1_CR_DLLPITESTANDADC_LoadCount_OFF ( 5) + #define DDRDATA7CH1_CR_DLLPITESTANDADC_LoadCount_WID (10) + #define DDRDATA7CH1_CR_DLLPITESTANDADC_LoadCount_MSK (0x00007FE0) + #define DDRDATA7CH1_CR_DLLPITESTANDADC_LoadCount_MAX (0x000003FF) + #define DDRDATA7CH1_CR_DLLPITESTANDADC_CountStatus_OFF (15) + #define DDRDATA7CH1_CR_DLLPITESTANDADC_CountStatus_WID (10) + #define DDRDATA7CH1_CR_DLLPITESTANDADC_CountStatus_MSK (0x01FF8000) + #define DDRDATA7CH1_CR_DLLPITESTANDADC_CountStatus_MAX (0x000003FF) + #define DDRDATA7CH1_CR_DLLPITESTANDADC_CountStatus_DEF (0x00000000) + #define DDRDATA7CH1_CR_DLLPITESTANDADC_Spare_OFF (25) + #define DDRDATA7CH1_CR_DLLPITESTANDADC_Spare_WID ( 7) + #define DDRDATA7CH1_CR_DLLPITESTANDADC_Spare_MSK (0xFE000000) + #define DDRDATA7CH1_CR_DLLPITESTANDADC_Spare_MAX (0x0000007F) + +#define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_REG (0x00000F5C) + #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_OFF ( 0) + #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_WID ( 6) + #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MSK (0x0000003F) + #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MAX (0x0000003F) + #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_DEF (0x00000000) + #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_OFF ( 6) + #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_WID ( 6) + #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MSK (0x00000FC0) + #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MAX (0x0000003F) + #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_DEF (0x00000000) + #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_OFF (12) + #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_WID ( 5) + #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MSK (0x0001F000) + #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MAX (0x0000001F) + #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_DEF (0x00000000) + #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_OFF (17) + #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_WID ( 5) + #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MSK (0x003E0000) + #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MAX (0x0000001F) + #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_DEF (0x00000000) + #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_OFF (22) + #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_WID ( 5) + #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_MSK (0x07C00000) + #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_MAX (0x0000001F) + #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_DEF (0x00000000) + #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_OFF (27) + #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_WID ( 5) + #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MSK (0xF8000000) + #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MAX (0x0000001F) + #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_DEF (0x00000000) + +#define DDRDATA7CH1_CR_DDRCRDATACONTROL1_REG (0x00000F60) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_RefPi_OFF ( 0) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_RefPi_WID ( 4) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_RefPi_MSK (0x0000000F) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_RefPi_MAX (0x0000000F) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_RefPi_DEF (0x00000000) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_DllMask_OFF ( 4) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_DllMask_WID ( 2) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_DllMask_MSK (0x00000030) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_DllMask_MAX (0x00000003) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_DllMask_DEF (0x00000000) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_DllWeakLock_OFF ( 6) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_DllWeakLock_WID ( 1) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_DllWeakLock_MSK (0x00000040) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_DllWeakLock_MAX (0x00000001) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_DllWeakLock_DEF (0x00000000) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_OFF ( 7) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_WID ( 3) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MSK (0x00000380) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MAX (0x00000007) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_DEF (0x00000000) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_OFF (10) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_WID ( 3) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_MSK (0x00001C00) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_MAX (0x00000007) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_DEF (0x00000000) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_OdtDelay_OFF (13) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_OdtDelay_WID ( 4) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_OdtDelay_MSK (0x0001E000) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_OdtDelay_MAX (0x0000000F) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_OdtDelay_DEF (0x00000000) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_OdtDuration_OFF (17) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_OdtDuration_WID ( 3) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_OdtDuration_MSK (0x000E0000) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_OdtDuration_MAX (0x00000007) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_OdtDuration_DEF (0x00000000) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_OFF (20) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_WID ( 4) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_MSK (0x00F00000) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_MAX (0x0000000F) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_DEF (0x00000000) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_OFF (24) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_WID ( 3) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_MSK (0x07000000) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_MAX (0x00000007) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_DEF (0x00000000) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_OFF (27) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_WID ( 3) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_MSK (0x38000000) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_MAX (0x00000007) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_DEF (0x00000000) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_OFF (30) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_WID ( 1) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_MSK (0x40000000) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_MAX (0x00000001) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_DEF (0x00000000) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_Rsvd1_OFF (31) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_Rsvd1_WID ( 1) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_Rsvd1_MSK (0x80000000) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_Rsvd1_MAX (0x00000001) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_Rsvd1_DEF (0x00000000) + +#define DDRDATA7CH1_CR_DDRCRDATACONTROL2_REG (0x00000F64) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_OFF ( 0) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_WID ( 5) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_MSK (0x0000001F) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_MAX (0x0000001F) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_DEF (0x00000000) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_OFF ( 5) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_WID ( 1) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_MSK (0x00000020) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_MAX (0x00000001) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_DEF (0x00000000) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_ForceRxOn_OFF ( 6) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_ForceRxOn_WID ( 1) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_ForceRxOn_MSK (0x00000040) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_ForceRxOn_MAX (0x00000001) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_ForceRxOn_DEF (0x00000000) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_LeakerComp_OFF ( 7) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_LeakerComp_WID ( 2) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_LeakerComp_MSK (0x00000180) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_LeakerComp_MAX (0x00000003) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_LeakerComp_DEF (0x00000000) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_OFF ( 9) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_WID ( 4) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_MSK (0x00001E00) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_MAX (0x0000000F) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_DEF (0x00000008) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_OFF (13) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_WID ( 5) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_MSK (0x0003E000) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_MAX (0x0000001F) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_DEF (0x00000011) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_OFF (18) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_WID ( 1) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_MSK (0x00040000) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_MAX (0x00000001) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_DEF (0x00000000) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_Spare_OFF (19) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_Spare_WID (13) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_Spare_MSK (0xFFF80000) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_Spare_MAX (0x00001FFF) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_Spare_DEF (0x00000000) + +#define DDRDATA7CH1_CR_DDRCRVREFCONTROL_REG (0x00000F68) + #define DDRDATA7CH1_CR_DDRCRVREFCONTROL_VrefCtl_OFF ( 0) + #define DDRDATA7CH1_CR_DDRCRVREFCONTROL_VrefCtl_WID (24) + #define DDRDATA7CH1_CR_DDRCRVREFCONTROL_VrefCtl_MSK (0x00FFFFFF) + #define DDRDATA7CH1_CR_DDRCRVREFCONTROL_VrefCtl_MAX (0x00FFFFFF) + #define DDRDATA7CH1_CR_DDRCRVREFCONTROL_VrefCtl_DEF (0x000E453A) + #define DDRDATA7CH1_CR_DDRCRVREFCONTROL_OutputCode_OFF (24) + #define DDRDATA7CH1_CR_DDRCRVREFCONTROL_OutputCode_WID ( 8) + #define DDRDATA7CH1_CR_DDRCRVREFCONTROL_OutputCode_MSK (0xFF000000) + #define DDRDATA7CH1_CR_DDRCRVREFCONTROL_OutputCode_MAX (0x000000FF) + #define DDRDATA7CH1_CR_DDRCRVREFCONTROL_OutputCode_DEF (0x00000000) + +#define DDRDATA7CH1_CR_DDRCRVSSHICONTROL_REG (0x00000F6C) + #define DDRDATA7CH1_CR_DDRCRVSSHICONTROL_VssHiCtl_OFF ( 0) + #define DDRDATA7CH1_CR_DDRCRVSSHICONTROL_VssHiCtl_WID (24) + #define DDRDATA7CH1_CR_DDRCRVSSHICONTROL_VssHiCtl_MSK (0x00FFFFFF) + #define DDRDATA7CH1_CR_DDRCRVSSHICONTROL_VssHiCtl_MAX (0x00FFFFFF) + #define DDRDATA7CH1_CR_DDRCRVSSHICONTROL_VssHiCtl_DEF (0x004D8238) + #define DDRDATA7CH1_CR_DDRCRVSSHICONTROL_OutputCode_OFF (24) + #define DDRDATA7CH1_CR_DDRCRVSSHICONTROL_OutputCode_WID ( 8) + #define DDRDATA7CH1_CR_DDRCRVSSHICONTROL_OutputCode_MSK (0xFF000000) + #define DDRDATA7CH1_CR_DDRCRVSSHICONTROL_OutputCode_MAX (0x000000FF) + #define DDRDATA7CH1_CR_DDRCRVSSHICONTROL_OutputCode_DEF (0x00000000) + +#define DDRDATA7CH1_CR_DDRCRVSSHIORVREFCONTROL_REG (0x00000F6C) + #define DDRDATA7CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_OFF ( 0) + #define DDRDATA7CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_WID (24) + #define DDRDATA7CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_MSK (0x00FFFFFF) + #define DDRDATA7CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_MAX (0x00FFFFFF) + #define DDRDATA7CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_DEF (0x00000000) + #define DDRDATA7CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_OFF (24) + #define DDRDATA7CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_WID ( 8) + #define DDRDATA7CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_MSK (0xFF000000) + #define DDRDATA7CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_MAX (0x000000FF) + #define DDRDATA7CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_DEF (0x00000000) + +#define DDRDATA7CH1_CR_DDRCRDATAOFFSETTRAIN_REG (0x00000F70) + #define DDRDATA7CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_OFF ( 0) + #define DDRDATA7CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_WID ( 6) + #define DDRDATA7CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MSK (0x0000003F) + #define DDRDATA7CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MAX (0x0000003F) + #define DDRDATA7CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_DEF (0x00000000) + #define DDRDATA7CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_OFF ( 6) + #define DDRDATA7CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_WID ( 6) + #define DDRDATA7CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MSK (0x00000FC0) + #define DDRDATA7CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MAX (0x0000003F) + #define DDRDATA7CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_DEF (0x00000000) + #define DDRDATA7CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_OFF (12) + #define DDRDATA7CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_WID ( 6) + #define DDRDATA7CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MSK (0x0003F000) + #define DDRDATA7CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MAX (0x0000003F) + #define DDRDATA7CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_DEF (0x00000000) + #define DDRDATA7CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_OFF (18) + #define DDRDATA7CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_WID ( 6) + #define DDRDATA7CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MSK (0x00FC0000) + #define DDRDATA7CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MAX (0x0000003F) + #define DDRDATA7CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_DEF (0x00000000) + #define DDRDATA7CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_OFF (24) + #define DDRDATA7CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_WID ( 7) + #define DDRDATA7CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MSK (0x7F000000) + #define DDRDATA7CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MAX (0x0000007F) + #define DDRDATA7CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_DEF (0x00000000) + #define DDRDATA7CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_OFF (31) + #define DDRDATA7CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_WID ( 1) + #define DDRDATA7CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_MSK (0x80000000) + #define DDRDATA7CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_MAX (0x00000001) + #define DDRDATA7CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_DEF (0x00000000) + +#define DDRDATA7CH1_CR_DDRCRDATACONTROL0_REG (0x00000F74) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_OFF ( 0) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_WID ( 1) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_MSK (0x00000001) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_MAX (0x00000001) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_DEF (0x00000000) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_OFF ( 1) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_WID ( 1) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_MSK (0x00000002) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_MAX (0x00000001) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_DEF (0x00000000) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_OFF ( 2) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_WID ( 1) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_MSK (0x00000004) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_MAX (0x00000001) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_DEF (0x00000000) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_OFF ( 3) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_WID ( 1) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MSK (0x00000008) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MAX (0x00000001) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_DEF (0x00000000) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_TxOn_OFF ( 4) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_TxOn_WID ( 1) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_TxOn_MSK (0x00000010) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_TxOn_MAX (0x00000001) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_TxOn_DEF (0x00000000) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RfOn_OFF ( 5) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RfOn_WID ( 1) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RfOn_MSK (0x00000020) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RfOn_MAX (0x00000001) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RfOn_DEF (0x00000000) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RxPiOn_OFF ( 6) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RxPiOn_WID ( 1) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RxPiOn_MSK (0x00000040) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RxPiOn_MAX (0x00000001) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RxPiOn_DEF (0x00000000) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_TxPiOn_OFF ( 7) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_TxPiOn_WID ( 1) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_TxPiOn_MSK (0x00000080) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_TxPiOn_MAX (0x00000001) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_TxPiOn_DEF (0x00000000) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_OFF ( 8) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_WID ( 1) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_MSK (0x00000100) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_MAX (0x00000001) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_DEF (0x00000000) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_OFF ( 9) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_WID ( 1) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MSK (0x00000200) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MAX (0x00000001) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_DEF (0x00000000) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_TxDisable_OFF (10) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_TxDisable_WID ( 1) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_TxDisable_MSK (0x00000400) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_TxDisable_MAX (0x00000001) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_TxDisable_DEF (0x00000000) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RxDisable_OFF (11) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RxDisable_WID ( 1) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RxDisable_MSK (0x00000800) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RxDisable_MAX (0x00000001) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RxDisable_DEF (0x00000000) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_TxLong_OFF (12) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_TxLong_WID ( 1) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_TxLong_MSK (0x00001000) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_TxLong_MAX (0x00000001) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_TxLong_DEF (0x00000000) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_OFF (13) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_WID ( 2) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_MSK (0x00006000) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_MAX (0x00000003) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_DEF (0x00000000) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RxReadPointer_OFF (15) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RxReadPointer_WID ( 3) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RxReadPointer_MSK (0x00038000) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RxReadPointer_MAX (0x00000007) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RxReadPointer_DEF (0x00000000) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_OFF (18) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_WID ( 1) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_MSK (0x00040000) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_MAX (0x00000001) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_DEF (0x00000000) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_OFF (19) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_WID ( 1) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_MSK (0x00080000) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_MAX (0x00000001) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_DEF (0x00000000) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_ReadRFRd_OFF (20) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_ReadRFRd_WID ( 1) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_ReadRFRd_MSK (0x00100000) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_ReadRFRd_MAX (0x00000001) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_ReadRFRd_DEF (0x00000000) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_ReadRFWr_OFF (21) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_ReadRFWr_WID ( 1) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_ReadRFWr_MSK (0x00200000) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_ReadRFWr_MAX (0x00000001) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_ReadRFWr_DEF (0x00000000) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_ReadRFRank_OFF (22) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_ReadRFRank_WID ( 2) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_ReadRFRank_MSK (0x00C00000) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_ReadRFRank_MAX (0x00000003) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_ReadRFRank_DEF (0x00000000) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_OFF (24) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_WID ( 1) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_MSK (0x01000000) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_MAX (0x00000001) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_DEF (0x00000000) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_OdtSampOff_OFF (25) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_OdtSampOff_WID ( 1) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_OdtSampOff_MSK (0x02000000) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_OdtSampOff_MAX (0x00000001) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_OdtSampOff_DEF (0x00000000) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_OFF (26) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_WID ( 1) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_MSK (0x04000000) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_MAX (0x00000001) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_DEF (0x00000000) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_OFF (27) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_WID ( 1) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MSK (0x08000000) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MAX (0x00000001) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_DEF (0x00000000) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_OFF (28) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_WID ( 1) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_MSK (0x10000000) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_MAX (0x00000001) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_DEF (0x00000000) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_OFF (29) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_WID ( 1) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_MSK (0x20000000) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_MAX (0x00000001) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_DEF (0x00000000) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_OFF (30) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_WID ( 1) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MSK (0x40000000) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MAX (0x00000001) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_DEF (0x00000000) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_OFF (31) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_WID ( 1) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_MSK (0x80000000) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_MAX (0x00000001) + #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_DEF (0x00000000) + +#define DDRDATA7CH1_CR_DDRCRVREFADJUST1_REG (0x00000F78) + #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_OFF ( 0) + #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_WID ( 7) + #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_MSK (0x0000007F) + #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_MAX (0x0000007F) + #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_DEF (0x00000000) + #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_OFF ( 7) + #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_WID ( 7) + #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_MSK (0x00003F80) + #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_MAX (0x0000007F) + #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_DEF (0x00000000) + #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_OFF (14) + #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_WID ( 7) + #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_MSK (0x001FC000) + #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_MAX (0x0000007F) + #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_DEF (0x00000000) + #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_OFF (21) + #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_WID ( 1) + #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_MSK (0x00200000) + #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_MAX (0x00000001) + #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_DEF (0x00000000) + #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_OFF (22) + #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_WID ( 1) + #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_MSK (0x00400000) + #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_MAX (0x00000001) + #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_DEF (0x00000000) + #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_OFF (23) + #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_WID ( 1) + #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_MSK (0x00800000) + #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_MAX (0x00000001) + #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_DEF (0x00000000) + #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_OFF (24) + #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_WID ( 2) + #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_MSK (0x03000000) + #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_MAX (0x00000003) + #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_DEF (0x00000000) + #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_OFF (26) + #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_WID ( 1) + #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_MSK (0x04000000) + #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_MAX (0x00000001) + #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_DEF (0x00000000) + #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_Rsvd_OFF (27) + #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_Rsvd_WID ( 2) + #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_Rsvd_MSK (0x18000000) + #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_Rsvd_MAX (0x00000003) + #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_Rsvd_DEF (0x00000000) + #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_caSlowBW_OFF (29) + #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_caSlowBW_WID ( 1) + #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_caSlowBW_MSK (0x20000000) + #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_caSlowBW_MAX (0x00000001) + #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_caSlowBW_DEF (0x00000000) + #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_OFF (30) + #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_WID ( 1) + #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_MSK (0x40000000) + #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_MAX (0x00000001) + #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_DEF (0x00000000) + #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_OFF (31) + #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_WID ( 1) + #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_MSK (0x80000000) + #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_MAX (0x00000001) + #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_DEF (0x00000000) + +#define DDRDATA8CH0_CR_RXTRAINRANK0_REG (0x00001000) + #define DDRDATA8CH0_CR_RXTRAINRANK0_RxRcvEnPi_OFF ( 0) + #define DDRDATA8CH0_CR_RXTRAINRANK0_RxRcvEnPi_WID ( 9) + #define DDRDATA8CH0_CR_RXTRAINRANK0_RxRcvEnPi_MSK (0x000001FF) + #define DDRDATA8CH0_CR_RXTRAINRANK0_RxRcvEnPi_MAX (0x000001FF) + #define DDRDATA8CH0_CR_RXTRAINRANK0_RxDqsPPi_OFF ( 9) + #define DDRDATA8CH0_CR_RXTRAINRANK0_RxDqsPPi_WID ( 6) + #define DDRDATA8CH0_CR_RXTRAINRANK0_RxDqsPPi_MSK (0x00007E00) + #define DDRDATA8CH0_CR_RXTRAINRANK0_RxDqsPPi_MAX (0x0000003F) + #define DDRDATA8CH0_CR_RXTRAINRANK0_RxEq_OFF (15) + #define DDRDATA8CH0_CR_RXTRAINRANK0_RxEq_WID ( 5) + #define DDRDATA8CH0_CR_RXTRAINRANK0_RxEq_MSK (0x000F8000) + #define DDRDATA8CH0_CR_RXTRAINRANK0_RxEq_MAX (0x0000001F) + #define DDRDATA8CH0_CR_RXTRAINRANK0_RxDqsNPi_OFF (20) + #define DDRDATA8CH0_CR_RXTRAINRANK0_RxDqsNPi_WID ( 6) + #define DDRDATA8CH0_CR_RXTRAINRANK0_RxDqsNPi_MSK (0x03F00000) + #define DDRDATA8CH0_CR_RXTRAINRANK0_RxDqsNPi_MAX (0x0000003F) + #define DDRDATA8CH0_CR_RXTRAINRANK0_RxVref_OFF (26) + #define DDRDATA8CH0_CR_RXTRAINRANK0_RxVref_WID ( 6) + #define DDRDATA8CH0_CR_RXTRAINRANK0_RxVref_MSK (0xFC000000) + #define DDRDATA8CH0_CR_RXTRAINRANK0_RxVref_MAX (0x0000003F) + +#define DDRDATA8CH0_CR_RXTRAINRANK1_REG (0x00001004) + #define DDRDATA8CH0_CR_RXTRAINRANK1_RxRcvEnPi_OFF ( 0) + #define DDRDATA8CH0_CR_RXTRAINRANK1_RxRcvEnPi_WID ( 9) + #define DDRDATA8CH0_CR_RXTRAINRANK1_RxRcvEnPi_MSK (0x000001FF) + #define DDRDATA8CH0_CR_RXTRAINRANK1_RxRcvEnPi_MAX (0x000001FF) + #define DDRDATA8CH0_CR_RXTRAINRANK1_RxDqsPPi_OFF ( 9) + #define DDRDATA8CH0_CR_RXTRAINRANK1_RxDqsPPi_WID ( 6) + #define DDRDATA8CH0_CR_RXTRAINRANK1_RxDqsPPi_MSK (0x00007E00) + #define DDRDATA8CH0_CR_RXTRAINRANK1_RxDqsPPi_MAX (0x0000003F) + #define DDRDATA8CH0_CR_RXTRAINRANK1_RxEq_OFF (15) + #define DDRDATA8CH0_CR_RXTRAINRANK1_RxEq_WID ( 5) + #define DDRDATA8CH0_CR_RXTRAINRANK1_RxEq_MSK (0x000F8000) + #define DDRDATA8CH0_CR_RXTRAINRANK1_RxEq_MAX (0x0000001F) + #define DDRDATA8CH0_CR_RXTRAINRANK1_RxDqsNPi_OFF (20) + #define DDRDATA8CH0_CR_RXTRAINRANK1_RxDqsNPi_WID ( 6) + #define DDRDATA8CH0_CR_RXTRAINRANK1_RxDqsNPi_MSK (0x03F00000) + #define DDRDATA8CH0_CR_RXTRAINRANK1_RxDqsNPi_MAX (0x0000003F) + #define DDRDATA8CH0_CR_RXTRAINRANK1_RxVref_OFF (26) + #define DDRDATA8CH0_CR_RXTRAINRANK1_RxVref_WID ( 6) + #define DDRDATA8CH0_CR_RXTRAINRANK1_RxVref_MSK (0xFC000000) + #define DDRDATA8CH0_CR_RXTRAINRANK1_RxVref_MAX (0x0000003F) + +#define DDRDATA8CH0_CR_RXTRAINRANK2_REG (0x00001008) + #define DDRDATA8CH0_CR_RXTRAINRANK2_RxRcvEnPi_OFF ( 0) + #define DDRDATA8CH0_CR_RXTRAINRANK2_RxRcvEnPi_WID ( 9) + #define DDRDATA8CH0_CR_RXTRAINRANK2_RxRcvEnPi_MSK (0x000001FF) + #define DDRDATA8CH0_CR_RXTRAINRANK2_RxRcvEnPi_MAX (0x000001FF) + #define DDRDATA8CH0_CR_RXTRAINRANK2_RxDqsPPi_OFF ( 9) + #define DDRDATA8CH0_CR_RXTRAINRANK2_RxDqsPPi_WID ( 6) + #define DDRDATA8CH0_CR_RXTRAINRANK2_RxDqsPPi_MSK (0x00007E00) + #define DDRDATA8CH0_CR_RXTRAINRANK2_RxDqsPPi_MAX (0x0000003F) + #define DDRDATA8CH0_CR_RXTRAINRANK2_RxEq_OFF (15) + #define DDRDATA8CH0_CR_RXTRAINRANK2_RxEq_WID ( 5) + #define DDRDATA8CH0_CR_RXTRAINRANK2_RxEq_MSK (0x000F8000) + #define DDRDATA8CH0_CR_RXTRAINRANK2_RxEq_MAX (0x0000001F) + #define DDRDATA8CH0_CR_RXTRAINRANK2_RxDqsNPi_OFF (20) + #define DDRDATA8CH0_CR_RXTRAINRANK2_RxDqsNPi_WID ( 6) + #define DDRDATA8CH0_CR_RXTRAINRANK2_RxDqsNPi_MSK (0x03F00000) + #define DDRDATA8CH0_CR_RXTRAINRANK2_RxDqsNPi_MAX (0x0000003F) + #define DDRDATA8CH0_CR_RXTRAINRANK2_RxVref_OFF (26) + #define DDRDATA8CH0_CR_RXTRAINRANK2_RxVref_WID ( 6) + #define DDRDATA8CH0_CR_RXTRAINRANK2_RxVref_MSK (0xFC000000) + #define DDRDATA8CH0_CR_RXTRAINRANK2_RxVref_MAX (0x0000003F) + +#define DDRDATA8CH0_CR_RXTRAINRANK3_REG (0x0000100C) + #define DDRDATA8CH0_CR_RXTRAINRANK3_RxRcvEnPi_OFF ( 0) + #define DDRDATA8CH0_CR_RXTRAINRANK3_RxRcvEnPi_WID ( 9) + #define DDRDATA8CH0_CR_RXTRAINRANK3_RxRcvEnPi_MSK (0x000001FF) + #define DDRDATA8CH0_CR_RXTRAINRANK3_RxRcvEnPi_MAX (0x000001FF) + #define DDRDATA8CH0_CR_RXTRAINRANK3_RxDqsPPi_OFF ( 9) + #define DDRDATA8CH0_CR_RXTRAINRANK3_RxDqsPPi_WID ( 6) + #define DDRDATA8CH0_CR_RXTRAINRANK3_RxDqsPPi_MSK (0x00007E00) + #define DDRDATA8CH0_CR_RXTRAINRANK3_RxDqsPPi_MAX (0x0000003F) + #define DDRDATA8CH0_CR_RXTRAINRANK3_RxEq_OFF (15) + #define DDRDATA8CH0_CR_RXTRAINRANK3_RxEq_WID ( 5) + #define DDRDATA8CH0_CR_RXTRAINRANK3_RxEq_MSK (0x000F8000) + #define DDRDATA8CH0_CR_RXTRAINRANK3_RxEq_MAX (0x0000001F) + #define DDRDATA8CH0_CR_RXTRAINRANK3_RxDqsNPi_OFF (20) + #define DDRDATA8CH0_CR_RXTRAINRANK3_RxDqsNPi_WID ( 6) + #define DDRDATA8CH0_CR_RXTRAINRANK3_RxDqsNPi_MSK (0x03F00000) + #define DDRDATA8CH0_CR_RXTRAINRANK3_RxDqsNPi_MAX (0x0000003F) + #define DDRDATA8CH0_CR_RXTRAINRANK3_RxVref_OFF (26) + #define DDRDATA8CH0_CR_RXTRAINRANK3_RxVref_WID ( 6) + #define DDRDATA8CH0_CR_RXTRAINRANK3_RxVref_MSK (0xFC000000) + #define DDRDATA8CH0_CR_RXTRAINRANK3_RxVref_MAX (0x0000003F) + +#define DDRDATA8CH0_CR_RXPERBITRANK0_REG (0x00001010) + #define DDRDATA8CH0_CR_RXPERBITRANK0_Lane0_OFF ( 0) + #define DDRDATA8CH0_CR_RXPERBITRANK0_Lane0_WID ( 4) + #define DDRDATA8CH0_CR_RXPERBITRANK0_Lane0_MSK (0x0000000F) + #define DDRDATA8CH0_CR_RXPERBITRANK0_Lane0_MAX (0x0000000F) + #define DDRDATA8CH0_CR_RXPERBITRANK0_Lane1_OFF ( 4) + #define DDRDATA8CH0_CR_RXPERBITRANK0_Lane1_WID ( 4) + #define DDRDATA8CH0_CR_RXPERBITRANK0_Lane1_MSK (0x000000F0) + #define DDRDATA8CH0_CR_RXPERBITRANK0_Lane1_MAX (0x0000000F) + #define DDRDATA8CH0_CR_RXPERBITRANK0_Lane2_OFF ( 8) + #define DDRDATA8CH0_CR_RXPERBITRANK0_Lane2_WID ( 4) + #define DDRDATA8CH0_CR_RXPERBITRANK0_Lane2_MSK (0x00000F00) + #define DDRDATA8CH0_CR_RXPERBITRANK0_Lane2_MAX (0x0000000F) + #define DDRDATA8CH0_CR_RXPERBITRANK0_Lane3_OFF (12) + #define DDRDATA8CH0_CR_RXPERBITRANK0_Lane3_WID ( 4) + #define DDRDATA8CH0_CR_RXPERBITRANK0_Lane3_MSK (0x0000F000) + #define DDRDATA8CH0_CR_RXPERBITRANK0_Lane3_MAX (0x0000000F) + #define DDRDATA8CH0_CR_RXPERBITRANK0_Lane4_OFF (16) + #define DDRDATA8CH0_CR_RXPERBITRANK0_Lane4_WID ( 4) + #define DDRDATA8CH0_CR_RXPERBITRANK0_Lane4_MSK (0x000F0000) + #define DDRDATA8CH0_CR_RXPERBITRANK0_Lane4_MAX (0x0000000F) + #define DDRDATA8CH0_CR_RXPERBITRANK0_Lane5_OFF (20) + #define DDRDATA8CH0_CR_RXPERBITRANK0_Lane5_WID ( 4) + #define DDRDATA8CH0_CR_RXPERBITRANK0_Lane5_MSK (0x00F00000) + #define DDRDATA8CH0_CR_RXPERBITRANK0_Lane5_MAX (0x0000000F) + #define DDRDATA8CH0_CR_RXPERBITRANK0_Lane6_OFF (24) + #define DDRDATA8CH0_CR_RXPERBITRANK0_Lane6_WID ( 4) + #define DDRDATA8CH0_CR_RXPERBITRANK0_Lane6_MSK (0x0F000000) + #define DDRDATA8CH0_CR_RXPERBITRANK0_Lane6_MAX (0x0000000F) + #define DDRDATA8CH0_CR_RXPERBITRANK0_Lane7_OFF (28) + #define DDRDATA8CH0_CR_RXPERBITRANK0_Lane7_WID ( 4) + #define DDRDATA8CH0_CR_RXPERBITRANK0_Lane7_MSK (0xF0000000) + #define DDRDATA8CH0_CR_RXPERBITRANK0_Lane7_MAX (0x0000000F) + +#define DDRDATA8CH0_CR_RXPERBITRANK1_REG (0x00001014) + #define DDRDATA8CH0_CR_RXPERBITRANK1_Lane0_OFF ( 0) + #define DDRDATA8CH0_CR_RXPERBITRANK1_Lane0_WID ( 4) + #define DDRDATA8CH0_CR_RXPERBITRANK1_Lane0_MSK (0x0000000F) + #define DDRDATA8CH0_CR_RXPERBITRANK1_Lane0_MAX (0x0000000F) + #define DDRDATA8CH0_CR_RXPERBITRANK1_Lane1_OFF ( 4) + #define DDRDATA8CH0_CR_RXPERBITRANK1_Lane1_WID ( 4) + #define DDRDATA8CH0_CR_RXPERBITRANK1_Lane1_MSK (0x000000F0) + #define DDRDATA8CH0_CR_RXPERBITRANK1_Lane1_MAX (0x0000000F) + #define DDRDATA8CH0_CR_RXPERBITRANK1_Lane2_OFF ( 8) + #define DDRDATA8CH0_CR_RXPERBITRANK1_Lane2_WID ( 4) + #define DDRDATA8CH0_CR_RXPERBITRANK1_Lane2_MSK (0x00000F00) + #define DDRDATA8CH0_CR_RXPERBITRANK1_Lane2_MAX (0x0000000F) + #define DDRDATA8CH0_CR_RXPERBITRANK1_Lane3_OFF (12) + #define DDRDATA8CH0_CR_RXPERBITRANK1_Lane3_WID ( 4) + #define DDRDATA8CH0_CR_RXPERBITRANK1_Lane3_MSK (0x0000F000) + #define DDRDATA8CH0_CR_RXPERBITRANK1_Lane3_MAX (0x0000000F) + #define DDRDATA8CH0_CR_RXPERBITRANK1_Lane4_OFF (16) + #define DDRDATA8CH0_CR_RXPERBITRANK1_Lane4_WID ( 4) + #define DDRDATA8CH0_CR_RXPERBITRANK1_Lane4_MSK (0x000F0000) + #define DDRDATA8CH0_CR_RXPERBITRANK1_Lane4_MAX (0x0000000F) + #define DDRDATA8CH0_CR_RXPERBITRANK1_Lane5_OFF (20) + #define DDRDATA8CH0_CR_RXPERBITRANK1_Lane5_WID ( 4) + #define DDRDATA8CH0_CR_RXPERBITRANK1_Lane5_MSK (0x00F00000) + #define DDRDATA8CH0_CR_RXPERBITRANK1_Lane5_MAX (0x0000000F) + #define DDRDATA8CH0_CR_RXPERBITRANK1_Lane6_OFF (24) + #define DDRDATA8CH0_CR_RXPERBITRANK1_Lane6_WID ( 4) + #define DDRDATA8CH0_CR_RXPERBITRANK1_Lane6_MSK (0x0F000000) + #define DDRDATA8CH0_CR_RXPERBITRANK1_Lane6_MAX (0x0000000F) + #define DDRDATA8CH0_CR_RXPERBITRANK1_Lane7_OFF (28) + #define DDRDATA8CH0_CR_RXPERBITRANK1_Lane7_WID ( 4) + #define DDRDATA8CH0_CR_RXPERBITRANK1_Lane7_MSK (0xF0000000) + #define DDRDATA8CH0_CR_RXPERBITRANK1_Lane7_MAX (0x0000000F) + +#define DDRDATA8CH0_CR_RXPERBITRANK2_REG (0x00001018) + #define DDRDATA8CH0_CR_RXPERBITRANK2_Lane0_OFF ( 0) + #define DDRDATA8CH0_CR_RXPERBITRANK2_Lane0_WID ( 4) + #define DDRDATA8CH0_CR_RXPERBITRANK2_Lane0_MSK (0x0000000F) + #define DDRDATA8CH0_CR_RXPERBITRANK2_Lane0_MAX (0x0000000F) + #define DDRDATA8CH0_CR_RXPERBITRANK2_Lane1_OFF ( 4) + #define DDRDATA8CH0_CR_RXPERBITRANK2_Lane1_WID ( 4) + #define DDRDATA8CH0_CR_RXPERBITRANK2_Lane1_MSK (0x000000F0) + #define DDRDATA8CH0_CR_RXPERBITRANK2_Lane1_MAX (0x0000000F) + #define DDRDATA8CH0_CR_RXPERBITRANK2_Lane2_OFF ( 8) + #define DDRDATA8CH0_CR_RXPERBITRANK2_Lane2_WID ( 4) + #define DDRDATA8CH0_CR_RXPERBITRANK2_Lane2_MSK (0x00000F00) + #define DDRDATA8CH0_CR_RXPERBITRANK2_Lane2_MAX (0x0000000F) + #define DDRDATA8CH0_CR_RXPERBITRANK2_Lane3_OFF (12) + #define DDRDATA8CH0_CR_RXPERBITRANK2_Lane3_WID ( 4) + #define DDRDATA8CH0_CR_RXPERBITRANK2_Lane3_MSK (0x0000F000) + #define DDRDATA8CH0_CR_RXPERBITRANK2_Lane3_MAX (0x0000000F) + #define DDRDATA8CH0_CR_RXPERBITRANK2_Lane4_OFF (16) + #define DDRDATA8CH0_CR_RXPERBITRANK2_Lane4_WID ( 4) + #define DDRDATA8CH0_CR_RXPERBITRANK2_Lane4_MSK (0x000F0000) + #define DDRDATA8CH0_CR_RXPERBITRANK2_Lane4_MAX (0x0000000F) + #define DDRDATA8CH0_CR_RXPERBITRANK2_Lane5_OFF (20) + #define DDRDATA8CH0_CR_RXPERBITRANK2_Lane5_WID ( 4) + #define DDRDATA8CH0_CR_RXPERBITRANK2_Lane5_MSK (0x00F00000) + #define DDRDATA8CH0_CR_RXPERBITRANK2_Lane5_MAX (0x0000000F) + #define DDRDATA8CH0_CR_RXPERBITRANK2_Lane6_OFF (24) + #define DDRDATA8CH0_CR_RXPERBITRANK2_Lane6_WID ( 4) + #define DDRDATA8CH0_CR_RXPERBITRANK2_Lane6_MSK (0x0F000000) + #define DDRDATA8CH0_CR_RXPERBITRANK2_Lane6_MAX (0x0000000F) + #define DDRDATA8CH0_CR_RXPERBITRANK2_Lane7_OFF (28) + #define DDRDATA8CH0_CR_RXPERBITRANK2_Lane7_WID ( 4) + #define DDRDATA8CH0_CR_RXPERBITRANK2_Lane7_MSK (0xF0000000) + #define DDRDATA8CH0_CR_RXPERBITRANK2_Lane7_MAX (0x0000000F) + +#define DDRDATA8CH0_CR_RXPERBITRANK3_REG (0x0000101C) + #define DDRDATA8CH0_CR_RXPERBITRANK3_Lane0_OFF ( 0) + #define DDRDATA8CH0_CR_RXPERBITRANK3_Lane0_WID ( 4) + #define DDRDATA8CH0_CR_RXPERBITRANK3_Lane0_MSK (0x0000000F) + #define DDRDATA8CH0_CR_RXPERBITRANK3_Lane0_MAX (0x0000000F) + #define DDRDATA8CH0_CR_RXPERBITRANK3_Lane1_OFF ( 4) + #define DDRDATA8CH0_CR_RXPERBITRANK3_Lane1_WID ( 4) + #define DDRDATA8CH0_CR_RXPERBITRANK3_Lane1_MSK (0x000000F0) + #define DDRDATA8CH0_CR_RXPERBITRANK3_Lane1_MAX (0x0000000F) + #define DDRDATA8CH0_CR_RXPERBITRANK3_Lane2_OFF ( 8) + #define DDRDATA8CH0_CR_RXPERBITRANK3_Lane2_WID ( 4) + #define DDRDATA8CH0_CR_RXPERBITRANK3_Lane2_MSK (0x00000F00) + #define DDRDATA8CH0_CR_RXPERBITRANK3_Lane2_MAX (0x0000000F) + #define DDRDATA8CH0_CR_RXPERBITRANK3_Lane3_OFF (12) + #define DDRDATA8CH0_CR_RXPERBITRANK3_Lane3_WID ( 4) + #define DDRDATA8CH0_CR_RXPERBITRANK3_Lane3_MSK (0x0000F000) + #define DDRDATA8CH0_CR_RXPERBITRANK3_Lane3_MAX (0x0000000F) + #define DDRDATA8CH0_CR_RXPERBITRANK3_Lane4_OFF (16) + #define DDRDATA8CH0_CR_RXPERBITRANK3_Lane4_WID ( 4) + #define DDRDATA8CH0_CR_RXPERBITRANK3_Lane4_MSK (0x000F0000) + #define DDRDATA8CH0_CR_RXPERBITRANK3_Lane4_MAX (0x0000000F) + #define DDRDATA8CH0_CR_RXPERBITRANK3_Lane5_OFF (20) + #define DDRDATA8CH0_CR_RXPERBITRANK3_Lane5_WID ( 4) + #define DDRDATA8CH0_CR_RXPERBITRANK3_Lane5_MSK (0x00F00000) + #define DDRDATA8CH0_CR_RXPERBITRANK3_Lane5_MAX (0x0000000F) + #define DDRDATA8CH0_CR_RXPERBITRANK3_Lane6_OFF (24) + #define DDRDATA8CH0_CR_RXPERBITRANK3_Lane6_WID ( 4) + #define DDRDATA8CH0_CR_RXPERBITRANK3_Lane6_MSK (0x0F000000) + #define DDRDATA8CH0_CR_RXPERBITRANK3_Lane6_MAX (0x0000000F) + #define DDRDATA8CH0_CR_RXPERBITRANK3_Lane7_OFF (28) + #define DDRDATA8CH0_CR_RXPERBITRANK3_Lane7_WID ( 4) + #define DDRDATA8CH0_CR_RXPERBITRANK3_Lane7_MSK (0xF0000000) + #define DDRDATA8CH0_CR_RXPERBITRANK3_Lane7_MAX (0x0000000F) + +#define DDRDATA8CH0_CR_TXTRAINRANK0_REG (0x00001020) + #define DDRDATA8CH0_CR_TXTRAINRANK0_TxDqDelay_OFF ( 0) + #define DDRDATA8CH0_CR_TXTRAINRANK0_TxDqDelay_WID ( 9) + #define DDRDATA8CH0_CR_TXTRAINRANK0_TxDqDelay_MSK (0x000001FF) + #define DDRDATA8CH0_CR_TXTRAINRANK0_TxDqDelay_MAX (0x000001FF) + #define DDRDATA8CH0_CR_TXTRAINRANK0_TxDqsDelay_OFF ( 9) + #define DDRDATA8CH0_CR_TXTRAINRANK0_TxDqsDelay_WID ( 9) + #define DDRDATA8CH0_CR_TXTRAINRANK0_TxDqsDelay_MSK (0x0003FE00) + #define DDRDATA8CH0_CR_TXTRAINRANK0_TxDqsDelay_MAX (0x000001FF) + #define DDRDATA8CH0_CR_TXTRAINRANK0_Spare0_OFF (18) + #define DDRDATA8CH0_CR_TXTRAINRANK0_Spare0_WID ( 2) + #define DDRDATA8CH0_CR_TXTRAINRANK0_Spare0_MSK (0x000C0000) + #define DDRDATA8CH0_CR_TXTRAINRANK0_Spare0_MAX (0x00000003) + #define DDRDATA8CH0_CR_TXTRAINRANK0_TxEqualization_OFF (20) + #define DDRDATA8CH0_CR_TXTRAINRANK0_TxEqualization_WID ( 6) + #define DDRDATA8CH0_CR_TXTRAINRANK0_TxEqualization_MSK (0x03F00000) + #define DDRDATA8CH0_CR_TXTRAINRANK0_TxEqualization_MAX (0x0000003F) + #define DDRDATA8CH0_CR_TXTRAINRANK0_Spare1_OFF (26) + #define DDRDATA8CH0_CR_TXTRAINRANK0_Spare1_WID ( 6) + #define DDRDATA8CH0_CR_TXTRAINRANK0_Spare1_MSK (0xFC000000) + #define DDRDATA8CH0_CR_TXTRAINRANK0_Spare1_MAX (0x0000003F) + +#define DDRDATA8CH0_CR_TXTRAINRANK1_REG (0x00001024) + #define DDRDATA8CH0_CR_TXTRAINRANK1_TxDqDelay_OFF ( 0) + #define DDRDATA8CH0_CR_TXTRAINRANK1_TxDqDelay_WID ( 9) + #define DDRDATA8CH0_CR_TXTRAINRANK1_TxDqDelay_MSK (0x000001FF) + #define DDRDATA8CH0_CR_TXTRAINRANK1_TxDqDelay_MAX (0x000001FF) + #define DDRDATA8CH0_CR_TXTRAINRANK1_TxDqsDelay_OFF ( 9) + #define DDRDATA8CH0_CR_TXTRAINRANK1_TxDqsDelay_WID ( 9) + #define DDRDATA8CH0_CR_TXTRAINRANK1_TxDqsDelay_MSK (0x0003FE00) + #define DDRDATA8CH0_CR_TXTRAINRANK1_TxDqsDelay_MAX (0x000001FF) + #define DDRDATA8CH0_CR_TXTRAINRANK1_Spare0_OFF (18) + #define DDRDATA8CH0_CR_TXTRAINRANK1_Spare0_WID ( 2) + #define DDRDATA8CH0_CR_TXTRAINRANK1_Spare0_MSK (0x000C0000) + #define DDRDATA8CH0_CR_TXTRAINRANK1_Spare0_MAX (0x00000003) + #define DDRDATA8CH0_CR_TXTRAINRANK1_TxEqualization_OFF (20) + #define DDRDATA8CH0_CR_TXTRAINRANK1_TxEqualization_WID ( 6) + #define DDRDATA8CH0_CR_TXTRAINRANK1_TxEqualization_MSK (0x03F00000) + #define DDRDATA8CH0_CR_TXTRAINRANK1_TxEqualization_MAX (0x0000003F) + #define DDRDATA8CH0_CR_TXTRAINRANK1_Spare1_OFF (26) + #define DDRDATA8CH0_CR_TXTRAINRANK1_Spare1_WID ( 6) + #define DDRDATA8CH0_CR_TXTRAINRANK1_Spare1_MSK (0xFC000000) + #define DDRDATA8CH0_CR_TXTRAINRANK1_Spare1_MAX (0x0000003F) + +#define DDRDATA8CH0_CR_TXTRAINRANK2_REG (0x00001028) + #define DDRDATA8CH0_CR_TXTRAINRANK2_TxDqDelay_OFF ( 0) + #define DDRDATA8CH0_CR_TXTRAINRANK2_TxDqDelay_WID ( 9) + #define DDRDATA8CH0_CR_TXTRAINRANK2_TxDqDelay_MSK (0x000001FF) + #define DDRDATA8CH0_CR_TXTRAINRANK2_TxDqDelay_MAX (0x000001FF) + #define DDRDATA8CH0_CR_TXTRAINRANK2_TxDqsDelay_OFF ( 9) + #define DDRDATA8CH0_CR_TXTRAINRANK2_TxDqsDelay_WID ( 9) + #define DDRDATA8CH0_CR_TXTRAINRANK2_TxDqsDelay_MSK (0x0003FE00) + #define DDRDATA8CH0_CR_TXTRAINRANK2_TxDqsDelay_MAX (0x000001FF) + #define DDRDATA8CH0_CR_TXTRAINRANK2_Spare0_OFF (18) + #define DDRDATA8CH0_CR_TXTRAINRANK2_Spare0_WID ( 2) + #define DDRDATA8CH0_CR_TXTRAINRANK2_Spare0_MSK (0x000C0000) + #define DDRDATA8CH0_CR_TXTRAINRANK2_Spare0_MAX (0x00000003) + #define DDRDATA8CH0_CR_TXTRAINRANK2_TxEqualization_OFF (20) + #define DDRDATA8CH0_CR_TXTRAINRANK2_TxEqualization_WID ( 6) + #define DDRDATA8CH0_CR_TXTRAINRANK2_TxEqualization_MSK (0x03F00000) + #define DDRDATA8CH0_CR_TXTRAINRANK2_TxEqualization_MAX (0x0000003F) + #define DDRDATA8CH0_CR_TXTRAINRANK2_Spare1_OFF (26) + #define DDRDATA8CH0_CR_TXTRAINRANK2_Spare1_WID ( 6) + #define DDRDATA8CH0_CR_TXTRAINRANK2_Spare1_MSK (0xFC000000) + #define DDRDATA8CH0_CR_TXTRAINRANK2_Spare1_MAX (0x0000003F) + +#define DDRDATA8CH0_CR_TXTRAINRANK3_REG (0x0000102C) + #define DDRDATA8CH0_CR_TXTRAINRANK3_TxDqDelay_OFF ( 0) + #define DDRDATA8CH0_CR_TXTRAINRANK3_TxDqDelay_WID ( 9) + #define DDRDATA8CH0_CR_TXTRAINRANK3_TxDqDelay_MSK (0x000001FF) + #define DDRDATA8CH0_CR_TXTRAINRANK3_TxDqDelay_MAX (0x000001FF) + #define DDRDATA8CH0_CR_TXTRAINRANK3_TxDqsDelay_OFF ( 9) + #define DDRDATA8CH0_CR_TXTRAINRANK3_TxDqsDelay_WID ( 9) + #define DDRDATA8CH0_CR_TXTRAINRANK3_TxDqsDelay_MSK (0x0003FE00) + #define DDRDATA8CH0_CR_TXTRAINRANK3_TxDqsDelay_MAX (0x000001FF) + #define DDRDATA8CH0_CR_TXTRAINRANK3_Spare0_OFF (18) + #define DDRDATA8CH0_CR_TXTRAINRANK3_Spare0_WID ( 2) + #define DDRDATA8CH0_CR_TXTRAINRANK3_Spare0_MSK (0x000C0000) + #define DDRDATA8CH0_CR_TXTRAINRANK3_Spare0_MAX (0x00000003) + #define DDRDATA8CH0_CR_TXTRAINRANK3_TxEqualization_OFF (20) + #define DDRDATA8CH0_CR_TXTRAINRANK3_TxEqualization_WID ( 6) + #define DDRDATA8CH0_CR_TXTRAINRANK3_TxEqualization_MSK (0x03F00000) + #define DDRDATA8CH0_CR_TXTRAINRANK3_TxEqualization_MAX (0x0000003F) + #define DDRDATA8CH0_CR_TXTRAINRANK3_Spare1_OFF (26) + #define DDRDATA8CH0_CR_TXTRAINRANK3_Spare1_WID ( 6) + #define DDRDATA8CH0_CR_TXTRAINRANK3_Spare1_MSK (0xFC000000) + #define DDRDATA8CH0_CR_TXTRAINRANK3_Spare1_MAX (0x0000003F) + +#define DDRDATA8CH0_CR_TXPERBITRANK0_REG (0x00001030) + #define DDRDATA8CH0_CR_TXPERBITRANK0_Lane0_OFF ( 0) + #define DDRDATA8CH0_CR_TXPERBITRANK0_Lane0_WID ( 4) + #define DDRDATA8CH0_CR_TXPERBITRANK0_Lane0_MSK (0x0000000F) + #define DDRDATA8CH0_CR_TXPERBITRANK0_Lane0_MAX (0x0000000F) + #define DDRDATA8CH0_CR_TXPERBITRANK0_Lane1_OFF ( 4) + #define DDRDATA8CH0_CR_TXPERBITRANK0_Lane1_WID ( 4) + #define DDRDATA8CH0_CR_TXPERBITRANK0_Lane1_MSK (0x000000F0) + #define DDRDATA8CH0_CR_TXPERBITRANK0_Lane1_MAX (0x0000000F) + #define DDRDATA8CH0_CR_TXPERBITRANK0_Lane2_OFF ( 8) + #define DDRDATA8CH0_CR_TXPERBITRANK0_Lane2_WID ( 4) + #define DDRDATA8CH0_CR_TXPERBITRANK0_Lane2_MSK (0x00000F00) + #define DDRDATA8CH0_CR_TXPERBITRANK0_Lane2_MAX (0x0000000F) + #define DDRDATA8CH0_CR_TXPERBITRANK0_Lane3_OFF (12) + #define DDRDATA8CH0_CR_TXPERBITRANK0_Lane3_WID ( 4) + #define DDRDATA8CH0_CR_TXPERBITRANK0_Lane3_MSK (0x0000F000) + #define DDRDATA8CH0_CR_TXPERBITRANK0_Lane3_MAX (0x0000000F) + #define DDRDATA8CH0_CR_TXPERBITRANK0_Lane4_OFF (16) + #define DDRDATA8CH0_CR_TXPERBITRANK0_Lane4_WID ( 4) + #define DDRDATA8CH0_CR_TXPERBITRANK0_Lane4_MSK (0x000F0000) + #define DDRDATA8CH0_CR_TXPERBITRANK0_Lane4_MAX (0x0000000F) + #define DDRDATA8CH0_CR_TXPERBITRANK0_Lane5_OFF (20) + #define DDRDATA8CH0_CR_TXPERBITRANK0_Lane5_WID ( 4) + #define DDRDATA8CH0_CR_TXPERBITRANK0_Lane5_MSK (0x00F00000) + #define DDRDATA8CH0_CR_TXPERBITRANK0_Lane5_MAX (0x0000000F) + #define DDRDATA8CH0_CR_TXPERBITRANK0_Lane6_OFF (24) + #define DDRDATA8CH0_CR_TXPERBITRANK0_Lane6_WID ( 4) + #define DDRDATA8CH0_CR_TXPERBITRANK0_Lane6_MSK (0x0F000000) + #define DDRDATA8CH0_CR_TXPERBITRANK0_Lane6_MAX (0x0000000F) + #define DDRDATA8CH0_CR_TXPERBITRANK0_Lane7_OFF (28) + #define DDRDATA8CH0_CR_TXPERBITRANK0_Lane7_WID ( 4) + #define DDRDATA8CH0_CR_TXPERBITRANK0_Lane7_MSK (0xF0000000) + #define DDRDATA8CH0_CR_TXPERBITRANK0_Lane7_MAX (0x0000000F) + +#define DDRDATA8CH0_CR_TXPERBITRANK1_REG (0x00001034) + #define DDRDATA8CH0_CR_TXPERBITRANK1_Lane0_OFF ( 0) + #define DDRDATA8CH0_CR_TXPERBITRANK1_Lane0_WID ( 4) + #define DDRDATA8CH0_CR_TXPERBITRANK1_Lane0_MSK (0x0000000F) + #define DDRDATA8CH0_CR_TXPERBITRANK1_Lane0_MAX (0x0000000F) + #define DDRDATA8CH0_CR_TXPERBITRANK1_Lane1_OFF ( 4) + #define DDRDATA8CH0_CR_TXPERBITRANK1_Lane1_WID ( 4) + #define DDRDATA8CH0_CR_TXPERBITRANK1_Lane1_MSK (0x000000F0) + #define DDRDATA8CH0_CR_TXPERBITRANK1_Lane1_MAX (0x0000000F) + #define DDRDATA8CH0_CR_TXPERBITRANK1_Lane2_OFF ( 8) + #define DDRDATA8CH0_CR_TXPERBITRANK1_Lane2_WID ( 4) + #define DDRDATA8CH0_CR_TXPERBITRANK1_Lane2_MSK (0x00000F00) + #define DDRDATA8CH0_CR_TXPERBITRANK1_Lane2_MAX (0x0000000F) + #define DDRDATA8CH0_CR_TXPERBITRANK1_Lane3_OFF (12) + #define DDRDATA8CH0_CR_TXPERBITRANK1_Lane3_WID ( 4) + #define DDRDATA8CH0_CR_TXPERBITRANK1_Lane3_MSK (0x0000F000) + #define DDRDATA8CH0_CR_TXPERBITRANK1_Lane3_MAX (0x0000000F) + #define DDRDATA8CH0_CR_TXPERBITRANK1_Lane4_OFF (16) + #define DDRDATA8CH0_CR_TXPERBITRANK1_Lane4_WID ( 4) + #define DDRDATA8CH0_CR_TXPERBITRANK1_Lane4_MSK (0x000F0000) + #define DDRDATA8CH0_CR_TXPERBITRANK1_Lane4_MAX (0x0000000F) + #define DDRDATA8CH0_CR_TXPERBITRANK1_Lane5_OFF (20) + #define DDRDATA8CH0_CR_TXPERBITRANK1_Lane5_WID ( 4) + #define DDRDATA8CH0_CR_TXPERBITRANK1_Lane5_MSK (0x00F00000) + #define DDRDATA8CH0_CR_TXPERBITRANK1_Lane5_MAX (0x0000000F) + #define DDRDATA8CH0_CR_TXPERBITRANK1_Lane6_OFF (24) + #define DDRDATA8CH0_CR_TXPERBITRANK1_Lane6_WID ( 4) + #define DDRDATA8CH0_CR_TXPERBITRANK1_Lane6_MSK (0x0F000000) + #define DDRDATA8CH0_CR_TXPERBITRANK1_Lane6_MAX (0x0000000F) + #define DDRDATA8CH0_CR_TXPERBITRANK1_Lane7_OFF (28) + #define DDRDATA8CH0_CR_TXPERBITRANK1_Lane7_WID ( 4) + #define DDRDATA8CH0_CR_TXPERBITRANK1_Lane7_MSK (0xF0000000) + #define DDRDATA8CH0_CR_TXPERBITRANK1_Lane7_MAX (0x0000000F) + +#define DDRDATA8CH0_CR_TXPERBITRANK2_REG (0x00001038) + #define DDRDATA8CH0_CR_TXPERBITRANK2_Lane0_OFF ( 0) + #define DDRDATA8CH0_CR_TXPERBITRANK2_Lane0_WID ( 4) + #define DDRDATA8CH0_CR_TXPERBITRANK2_Lane0_MSK (0x0000000F) + #define DDRDATA8CH0_CR_TXPERBITRANK2_Lane0_MAX (0x0000000F) + #define DDRDATA8CH0_CR_TXPERBITRANK2_Lane1_OFF ( 4) + #define DDRDATA8CH0_CR_TXPERBITRANK2_Lane1_WID ( 4) + #define DDRDATA8CH0_CR_TXPERBITRANK2_Lane1_MSK (0x000000F0) + #define DDRDATA8CH0_CR_TXPERBITRANK2_Lane1_MAX (0x0000000F) + #define DDRDATA8CH0_CR_TXPERBITRANK2_Lane2_OFF ( 8) + #define DDRDATA8CH0_CR_TXPERBITRANK2_Lane2_WID ( 4) + #define DDRDATA8CH0_CR_TXPERBITRANK2_Lane2_MSK (0x00000F00) + #define DDRDATA8CH0_CR_TXPERBITRANK2_Lane2_MAX (0x0000000F) + #define DDRDATA8CH0_CR_TXPERBITRANK2_Lane3_OFF (12) + #define DDRDATA8CH0_CR_TXPERBITRANK2_Lane3_WID ( 4) + #define DDRDATA8CH0_CR_TXPERBITRANK2_Lane3_MSK (0x0000F000) + #define DDRDATA8CH0_CR_TXPERBITRANK2_Lane3_MAX (0x0000000F) + #define DDRDATA8CH0_CR_TXPERBITRANK2_Lane4_OFF (16) + #define DDRDATA8CH0_CR_TXPERBITRANK2_Lane4_WID ( 4) + #define DDRDATA8CH0_CR_TXPERBITRANK2_Lane4_MSK (0x000F0000) + #define DDRDATA8CH0_CR_TXPERBITRANK2_Lane4_MAX (0x0000000F) + #define DDRDATA8CH0_CR_TXPERBITRANK2_Lane5_OFF (20) + #define DDRDATA8CH0_CR_TXPERBITRANK2_Lane5_WID ( 4) + #define DDRDATA8CH0_CR_TXPERBITRANK2_Lane5_MSK (0x00F00000) + #define DDRDATA8CH0_CR_TXPERBITRANK2_Lane5_MAX (0x0000000F) + #define DDRDATA8CH0_CR_TXPERBITRANK2_Lane6_OFF (24) + #define DDRDATA8CH0_CR_TXPERBITRANK2_Lane6_WID ( 4) + #define DDRDATA8CH0_CR_TXPERBITRANK2_Lane6_MSK (0x0F000000) + #define DDRDATA8CH0_CR_TXPERBITRANK2_Lane6_MAX (0x0000000F) + #define DDRDATA8CH0_CR_TXPERBITRANK2_Lane7_OFF (28) + #define DDRDATA8CH0_CR_TXPERBITRANK2_Lane7_WID ( 4) + #define DDRDATA8CH0_CR_TXPERBITRANK2_Lane7_MSK (0xF0000000) + #define DDRDATA8CH0_CR_TXPERBITRANK2_Lane7_MAX (0x0000000F) + +#define DDRDATA8CH0_CR_TXPERBITRANK3_REG (0x0000103C) + #define DDRDATA8CH0_CR_TXPERBITRANK3_Lane0_OFF ( 0) + #define DDRDATA8CH0_CR_TXPERBITRANK3_Lane0_WID ( 4) + #define DDRDATA8CH0_CR_TXPERBITRANK3_Lane0_MSK (0x0000000F) + #define DDRDATA8CH0_CR_TXPERBITRANK3_Lane0_MAX (0x0000000F) + #define DDRDATA8CH0_CR_TXPERBITRANK3_Lane1_OFF ( 4) + #define DDRDATA8CH0_CR_TXPERBITRANK3_Lane1_WID ( 4) + #define DDRDATA8CH0_CR_TXPERBITRANK3_Lane1_MSK (0x000000F0) + #define DDRDATA8CH0_CR_TXPERBITRANK3_Lane1_MAX (0x0000000F) + #define DDRDATA8CH0_CR_TXPERBITRANK3_Lane2_OFF ( 8) + #define DDRDATA8CH0_CR_TXPERBITRANK3_Lane2_WID ( 4) + #define DDRDATA8CH0_CR_TXPERBITRANK3_Lane2_MSK (0x00000F00) + #define DDRDATA8CH0_CR_TXPERBITRANK3_Lane2_MAX (0x0000000F) + #define DDRDATA8CH0_CR_TXPERBITRANK3_Lane3_OFF (12) + #define DDRDATA8CH0_CR_TXPERBITRANK3_Lane3_WID ( 4) + #define DDRDATA8CH0_CR_TXPERBITRANK3_Lane3_MSK (0x0000F000) + #define DDRDATA8CH0_CR_TXPERBITRANK3_Lane3_MAX (0x0000000F) + #define DDRDATA8CH0_CR_TXPERBITRANK3_Lane4_OFF (16) + #define DDRDATA8CH0_CR_TXPERBITRANK3_Lane4_WID ( 4) + #define DDRDATA8CH0_CR_TXPERBITRANK3_Lane4_MSK (0x000F0000) + #define DDRDATA8CH0_CR_TXPERBITRANK3_Lane4_MAX (0x0000000F) + #define DDRDATA8CH0_CR_TXPERBITRANK3_Lane5_OFF (20) + #define DDRDATA8CH0_CR_TXPERBITRANK3_Lane5_WID ( 4) + #define DDRDATA8CH0_CR_TXPERBITRANK3_Lane5_MSK (0x00F00000) + #define DDRDATA8CH0_CR_TXPERBITRANK3_Lane5_MAX (0x0000000F) + #define DDRDATA8CH0_CR_TXPERBITRANK3_Lane6_OFF (24) + #define DDRDATA8CH0_CR_TXPERBITRANK3_Lane6_WID ( 4) + #define DDRDATA8CH0_CR_TXPERBITRANK3_Lane6_MSK (0x0F000000) + #define DDRDATA8CH0_CR_TXPERBITRANK3_Lane6_MAX (0x0000000F) + #define DDRDATA8CH0_CR_TXPERBITRANK3_Lane7_OFF (28) + #define DDRDATA8CH0_CR_TXPERBITRANK3_Lane7_WID ( 4) + #define DDRDATA8CH0_CR_TXPERBITRANK3_Lane7_MSK (0xF0000000) + #define DDRDATA8CH0_CR_TXPERBITRANK3_Lane7_MAX (0x0000000F) + +#define DDRDATA8CH0_CR_RCOMPDATA0_REG (0x00001040) + #define DDRDATA8CH0_CR_RCOMPDATA0_RcompDrvUp_OFF ( 0) + #define DDRDATA8CH0_CR_RCOMPDATA0_RcompDrvUp_WID ( 6) + #define DDRDATA8CH0_CR_RCOMPDATA0_RcompDrvUp_MSK (0x0000003F) + #define DDRDATA8CH0_CR_RCOMPDATA0_RcompDrvUp_MAX (0x0000003F) + #define DDRDATA8CH0_CR_RCOMPDATA0_Spare0_OFF ( 6) + #define DDRDATA8CH0_CR_RCOMPDATA0_Spare0_WID ( 3) + #define DDRDATA8CH0_CR_RCOMPDATA0_Spare0_MSK (0x000001C0) + #define DDRDATA8CH0_CR_RCOMPDATA0_Spare0_MAX (0x00000007) + #define DDRDATA8CH0_CR_RCOMPDATA0_RcompDrvDown_OFF ( 9) + #define DDRDATA8CH0_CR_RCOMPDATA0_RcompDrvDown_WID ( 6) + #define DDRDATA8CH0_CR_RCOMPDATA0_RcompDrvDown_MSK (0x00007E00) + #define DDRDATA8CH0_CR_RCOMPDATA0_RcompDrvDown_MAX (0x0000003F) + #define DDRDATA8CH0_CR_RCOMPDATA0_VTComp_OFF (15) + #define DDRDATA8CH0_CR_RCOMPDATA0_VTComp_WID ( 5) + #define DDRDATA8CH0_CR_RCOMPDATA0_VTComp_MSK (0x000F8000) + #define DDRDATA8CH0_CR_RCOMPDATA0_VTComp_MAX (0x0000001F) + #define DDRDATA8CH0_CR_RCOMPDATA0_TcoComp_OFF (20) + #define DDRDATA8CH0_CR_RCOMPDATA0_TcoComp_WID ( 6) + #define DDRDATA8CH0_CR_RCOMPDATA0_TcoComp_MSK (0x03F00000) + #define DDRDATA8CH0_CR_RCOMPDATA0_TcoComp_MAX (0x0000003F) + #define DDRDATA8CH0_CR_RCOMPDATA0_SlewRateComp_OFF (26) + #define DDRDATA8CH0_CR_RCOMPDATA0_SlewRateComp_WID ( 5) + #define DDRDATA8CH0_CR_RCOMPDATA0_SlewRateComp_MSK (0x7C000000) + #define DDRDATA8CH0_CR_RCOMPDATA0_SlewRateComp_MAX (0x0000001F) + #define DDRDATA8CH0_CR_RCOMPDATA0_Spare2_OFF (31) + #define DDRDATA8CH0_CR_RCOMPDATA0_Spare2_WID ( 1) + #define DDRDATA8CH0_CR_RCOMPDATA0_Spare2_MSK (0x80000000) + #define DDRDATA8CH0_CR_RCOMPDATA0_Spare2_MAX (0x00000001) + +#define DDRDATA8CH0_CR_RCOMPDATA1_REG (0x00001044) + #define DDRDATA8CH0_CR_RCOMPDATA1_RcompOdtUp_OFF ( 0) + #define DDRDATA8CH0_CR_RCOMPDATA1_RcompOdtUp_WID ( 6) + #define DDRDATA8CH0_CR_RCOMPDATA1_RcompOdtUp_MSK (0x0000003F) + #define DDRDATA8CH0_CR_RCOMPDATA1_RcompOdtUp_MAX (0x0000003F) + #define DDRDATA8CH0_CR_RCOMPDATA1_Spare0_OFF ( 6) + #define DDRDATA8CH0_CR_RCOMPDATA1_Spare0_WID ( 3) + #define DDRDATA8CH0_CR_RCOMPDATA1_Spare0_MSK (0x000001C0) + #define DDRDATA8CH0_CR_RCOMPDATA1_Spare0_MAX (0x00000007) + #define DDRDATA8CH0_CR_RCOMPDATA1_RcompOdtDown_OFF ( 9) + #define DDRDATA8CH0_CR_RCOMPDATA1_RcompOdtDown_WID ( 6) + #define DDRDATA8CH0_CR_RCOMPDATA1_RcompOdtDown_MSK (0x00007E00) + #define DDRDATA8CH0_CR_RCOMPDATA1_RcompOdtDown_MAX (0x0000003F) + #define DDRDATA8CH0_CR_RCOMPDATA1_Spare1_OFF (15) + #define DDRDATA8CH0_CR_RCOMPDATA1_Spare1_WID ( 1) + #define DDRDATA8CH0_CR_RCOMPDATA1_Spare1_MSK (0x00008000) + #define DDRDATA8CH0_CR_RCOMPDATA1_Spare1_MAX (0x00000001) + #define DDRDATA8CH0_CR_RCOMPDATA1_PanicDrvDn_OFF (16) + #define DDRDATA8CH0_CR_RCOMPDATA1_PanicDrvDn_WID ( 6) + #define DDRDATA8CH0_CR_RCOMPDATA1_PanicDrvDn_MSK (0x003F0000) + #define DDRDATA8CH0_CR_RCOMPDATA1_PanicDrvDn_MAX (0x0000003F) + #define DDRDATA8CH0_CR_RCOMPDATA1_PanicDrvUp_OFF (22) + #define DDRDATA8CH0_CR_RCOMPDATA1_PanicDrvUp_WID ( 6) + #define DDRDATA8CH0_CR_RCOMPDATA1_PanicDrvUp_MSK (0x0FC00000) + #define DDRDATA8CH0_CR_RCOMPDATA1_PanicDrvUp_MAX (0x0000003F) + #define DDRDATA8CH0_CR_RCOMPDATA1_LevelShifterComp_OFF (28) + #define DDRDATA8CH0_CR_RCOMPDATA1_LevelShifterComp_WID ( 3) + #define DDRDATA8CH0_CR_RCOMPDATA1_LevelShifterComp_MSK (0x70000000) + #define DDRDATA8CH0_CR_RCOMPDATA1_LevelShifterComp_MAX (0x00000007) + #define DDRDATA8CH0_CR_RCOMPDATA1_Spare2_OFF (31) + #define DDRDATA8CH0_CR_RCOMPDATA1_Spare2_WID ( 1) + #define DDRDATA8CH0_CR_RCOMPDATA1_Spare2_MSK (0x80000000) + #define DDRDATA8CH0_CR_RCOMPDATA1_Spare2_MAX (0x00000001) + +#define DDRDATA8CH0_CR_TXXTALK_REG (0x00001048) + #define DDRDATA8CH0_CR_TXXTALK_Lane0_OFF ( 0) + #define DDRDATA8CH0_CR_TXXTALK_Lane0_WID ( 4) + #define DDRDATA8CH0_CR_TXXTALK_Lane0_MSK (0x0000000F) + #define DDRDATA8CH0_CR_TXXTALK_Lane0_MAX (0x0000000F) + #define DDRDATA8CH0_CR_TXXTALK_Lane1_OFF ( 4) + #define DDRDATA8CH0_CR_TXXTALK_Lane1_WID ( 4) + #define DDRDATA8CH0_CR_TXXTALK_Lane1_MSK (0x000000F0) + #define DDRDATA8CH0_CR_TXXTALK_Lane1_MAX (0x0000000F) + #define DDRDATA8CH0_CR_TXXTALK_Lane2_OFF ( 8) + #define DDRDATA8CH0_CR_TXXTALK_Lane2_WID ( 4) + #define DDRDATA8CH0_CR_TXXTALK_Lane2_MSK (0x00000F00) + #define DDRDATA8CH0_CR_TXXTALK_Lane2_MAX (0x0000000F) + #define DDRDATA8CH0_CR_TXXTALK_Lane3_OFF (12) + #define DDRDATA8CH0_CR_TXXTALK_Lane3_WID ( 4) + #define DDRDATA8CH0_CR_TXXTALK_Lane3_MSK (0x0000F000) + #define DDRDATA8CH0_CR_TXXTALK_Lane3_MAX (0x0000000F) + #define DDRDATA8CH0_CR_TXXTALK_Lane4_OFF (16) + #define DDRDATA8CH0_CR_TXXTALK_Lane4_WID ( 4) + #define DDRDATA8CH0_CR_TXXTALK_Lane4_MSK (0x000F0000) + #define DDRDATA8CH0_CR_TXXTALK_Lane4_MAX (0x0000000F) + #define DDRDATA8CH0_CR_TXXTALK_Lane5_OFF (20) + #define DDRDATA8CH0_CR_TXXTALK_Lane5_WID ( 4) + #define DDRDATA8CH0_CR_TXXTALK_Lane5_MSK (0x00F00000) + #define DDRDATA8CH0_CR_TXXTALK_Lane5_MAX (0x0000000F) + #define DDRDATA8CH0_CR_TXXTALK_Lane6_OFF (24) + #define DDRDATA8CH0_CR_TXXTALK_Lane6_WID ( 4) + #define DDRDATA8CH0_CR_TXXTALK_Lane6_MSK (0x0F000000) + #define DDRDATA8CH0_CR_TXXTALK_Lane6_MAX (0x0000000F) + #define DDRDATA8CH0_CR_TXXTALK_Lane7_OFF (28) + #define DDRDATA8CH0_CR_TXXTALK_Lane7_WID ( 4) + #define DDRDATA8CH0_CR_TXXTALK_Lane7_MSK (0xF0000000) + #define DDRDATA8CH0_CR_TXXTALK_Lane7_MAX (0x0000000F) + +#define DDRDATA8CH0_CR_RXOFFSETVDQ_REG (0x0000104C) + #define DDRDATA8CH0_CR_RXOFFSETVDQ_Lane0_OFF ( 0) + #define DDRDATA8CH0_CR_RXOFFSETVDQ_Lane0_WID ( 4) + #define DDRDATA8CH0_CR_RXOFFSETVDQ_Lane0_MSK (0x0000000F) + #define DDRDATA8CH0_CR_RXOFFSETVDQ_Lane0_MAX (0x0000000F) + #define DDRDATA8CH0_CR_RXOFFSETVDQ_Lane1_OFF ( 4) + #define DDRDATA8CH0_CR_RXOFFSETVDQ_Lane1_WID ( 4) + #define DDRDATA8CH0_CR_RXOFFSETVDQ_Lane1_MSK (0x000000F0) + #define DDRDATA8CH0_CR_RXOFFSETVDQ_Lane1_MAX (0x0000000F) + #define DDRDATA8CH0_CR_RXOFFSETVDQ_Lane2_OFF ( 8) + #define DDRDATA8CH0_CR_RXOFFSETVDQ_Lane2_WID ( 4) + #define DDRDATA8CH0_CR_RXOFFSETVDQ_Lane2_MSK (0x00000F00) + #define DDRDATA8CH0_CR_RXOFFSETVDQ_Lane2_MAX (0x0000000F) + #define DDRDATA8CH0_CR_RXOFFSETVDQ_Lane3_OFF (12) + #define DDRDATA8CH0_CR_RXOFFSETVDQ_Lane3_WID ( 4) + #define DDRDATA8CH0_CR_RXOFFSETVDQ_Lane3_MSK (0x0000F000) + #define DDRDATA8CH0_CR_RXOFFSETVDQ_Lane3_MAX (0x0000000F) + #define DDRDATA8CH0_CR_RXOFFSETVDQ_Lane4_OFF (16) + #define DDRDATA8CH0_CR_RXOFFSETVDQ_Lane4_WID ( 4) + #define DDRDATA8CH0_CR_RXOFFSETVDQ_Lane4_MSK (0x000F0000) + #define DDRDATA8CH0_CR_RXOFFSETVDQ_Lane4_MAX (0x0000000F) + #define DDRDATA8CH0_CR_RXOFFSETVDQ_Lane5_OFF (20) + #define DDRDATA8CH0_CR_RXOFFSETVDQ_Lane5_WID ( 4) + #define DDRDATA8CH0_CR_RXOFFSETVDQ_Lane5_MSK (0x00F00000) + #define DDRDATA8CH0_CR_RXOFFSETVDQ_Lane5_MAX (0x0000000F) + #define DDRDATA8CH0_CR_RXOFFSETVDQ_Lane6_OFF (24) + #define DDRDATA8CH0_CR_RXOFFSETVDQ_Lane6_WID ( 4) + #define DDRDATA8CH0_CR_RXOFFSETVDQ_Lane6_MSK (0x0F000000) + #define DDRDATA8CH0_CR_RXOFFSETVDQ_Lane6_MAX (0x0000000F) + #define DDRDATA8CH0_CR_RXOFFSETVDQ_Lane7_OFF (28) + #define DDRDATA8CH0_CR_RXOFFSETVDQ_Lane7_WID ( 4) + #define DDRDATA8CH0_CR_RXOFFSETVDQ_Lane7_MSK (0xF0000000) + #define DDRDATA8CH0_CR_RXOFFSETVDQ_Lane7_MAX (0x0000000F) + +#define DDRDATA8CH0_CR_DDRDATARESERVED_REG (0x00001050) + #define DDRDATA8CH0_CR_DDRDATARESERVED_Spare_OFF ( 0) + #define DDRDATA8CH0_CR_DDRDATARESERVED_Spare_WID (32) + #define DDRDATA8CH0_CR_DDRDATARESERVED_Spare_MSK (0xFFFFFFFF) + #define DDRDATA8CH0_CR_DDRDATARESERVED_Spare_MAX (0xFFFFFFFF) + +#define DDRDATA8CH0_CR_DATATRAINFEEDBACK_REG (0x00001054) + #define DDRDATA8CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_OFF ( 0) + #define DDRDATA8CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_WID ( 9) + #define DDRDATA8CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_MSK (0x000001FF) + #define DDRDATA8CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_MAX (0x000001FF) + #define DDRDATA8CH0_CR_DATATRAINFEEDBACK_Spare_OFF ( 9) + #define DDRDATA8CH0_CR_DATATRAINFEEDBACK_Spare_WID (23) + #define DDRDATA8CH0_CR_DATATRAINFEEDBACK_Spare_MSK (0xFFFFFE00) + #define DDRDATA8CH0_CR_DATATRAINFEEDBACK_Spare_MAX (0x007FFFFF) + +#define DDRDATA8CH0_CR_DLLPITESTANDADC_REG (0x00001058) + #define DDRDATA8CH0_CR_DLLPITESTANDADC_RunTest_OFF ( 0) + #define DDRDATA8CH0_CR_DLLPITESTANDADC_RunTest_WID ( 1) + #define DDRDATA8CH0_CR_DLLPITESTANDADC_RunTest_MSK (0x00000001) + #define DDRDATA8CH0_CR_DLLPITESTANDADC_RunTest_MAX (0x00000001) + #define DDRDATA8CH0_CR_DLLPITESTANDADC_RunTest_DEF (0x00000000) + #define DDRDATA8CH0_CR_DLLPITESTANDADC_Load_OFF ( 1) + #define DDRDATA8CH0_CR_DLLPITESTANDADC_Load_WID ( 1) + #define DDRDATA8CH0_CR_DLLPITESTANDADC_Load_MSK (0x00000002) + #define DDRDATA8CH0_CR_DLLPITESTANDADC_Load_MAX (0x00000001) + #define DDRDATA8CH0_CR_DLLPITESTANDADC_Load_DEF (0x00000000) + #define DDRDATA8CH0_CR_DLLPITESTANDADC_ModeHVM_OFF ( 2) + #define DDRDATA8CH0_CR_DLLPITESTANDADC_ModeHVM_WID ( 1) + #define DDRDATA8CH0_CR_DLLPITESTANDADC_ModeHVM_MSK (0x00000004) + #define DDRDATA8CH0_CR_DLLPITESTANDADC_ModeHVM_MAX (0x00000001) + #define DDRDATA8CH0_CR_DLLPITESTANDADC_ModeHVM_DEF (0x00000000) + #define DDRDATA8CH0_CR_DLLPITESTANDADC_ModeDV_OFF ( 3) + #define DDRDATA8CH0_CR_DLLPITESTANDADC_ModeDV_WID ( 1) + #define DDRDATA8CH0_CR_DLLPITESTANDADC_ModeDV_MSK (0x00000008) + #define DDRDATA8CH0_CR_DLLPITESTANDADC_ModeDV_MAX (0x00000001) + #define DDRDATA8CH0_CR_DLLPITESTANDADC_ModeDV_DEF (0x00000000) + #define DDRDATA8CH0_CR_DLLPITESTANDADC_ModeADC_OFF ( 4) + #define DDRDATA8CH0_CR_DLLPITESTANDADC_ModeADC_WID ( 1) + #define DDRDATA8CH0_CR_DLLPITESTANDADC_ModeADC_MSK (0x00000010) + #define DDRDATA8CH0_CR_DLLPITESTANDADC_ModeADC_MAX (0x00000001) + #define DDRDATA8CH0_CR_DLLPITESTANDADC_ModeADC_DEF (0x00000000) + #define DDRDATA8CH0_CR_DLLPITESTANDADC_LoadCount_OFF ( 5) + #define DDRDATA8CH0_CR_DLLPITESTANDADC_LoadCount_WID (10) + #define DDRDATA8CH0_CR_DLLPITESTANDADC_LoadCount_MSK (0x00007FE0) + #define DDRDATA8CH0_CR_DLLPITESTANDADC_LoadCount_MAX (0x000003FF) + #define DDRDATA8CH0_CR_DLLPITESTANDADC_CountStatus_OFF (15) + #define DDRDATA8CH0_CR_DLLPITESTANDADC_CountStatus_WID (10) + #define DDRDATA8CH0_CR_DLLPITESTANDADC_CountStatus_MSK (0x01FF8000) + #define DDRDATA8CH0_CR_DLLPITESTANDADC_CountStatus_MAX (0x000003FF) + #define DDRDATA8CH0_CR_DLLPITESTANDADC_CountStatus_DEF (0x00000000) + #define DDRDATA8CH0_CR_DLLPITESTANDADC_Spare_OFF (25) + #define DDRDATA8CH0_CR_DLLPITESTANDADC_Spare_WID ( 7) + #define DDRDATA8CH0_CR_DLLPITESTANDADC_Spare_MSK (0xFE000000) + #define DDRDATA8CH0_CR_DLLPITESTANDADC_Spare_MAX (0x0000007F) + +#define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_REG (0x0000105C) + #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_OFF ( 0) + #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_WID ( 6) + #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MSK (0x0000003F) + #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MAX (0x0000003F) + #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_DEF (0x00000000) + #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_OFF ( 6) + #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_WID ( 6) + #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MSK (0x00000FC0) + #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MAX (0x0000003F) + #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_DEF (0x00000000) + #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_OFF (12) + #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_WID ( 5) + #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MSK (0x0001F000) + #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MAX (0x0000001F) + #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_DEF (0x00000000) + #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_OFF (17) + #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_WID ( 5) + #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MSK (0x003E0000) + #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MAX (0x0000001F) + #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_DEF (0x00000000) + #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_OFF (22) + #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_WID ( 5) + #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_MSK (0x07C00000) + #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_MAX (0x0000001F) + #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_DEF (0x00000000) + #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_OFF (27) + #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_WID ( 5) + #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MSK (0xF8000000) + #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MAX (0x0000001F) + #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_DEF (0x00000000) + +#define DDRDATA8CH0_CR_DDRCRDATACONTROL1_REG (0x00001060) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_RefPi_OFF ( 0) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_RefPi_WID ( 4) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_RefPi_MSK (0x0000000F) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_RefPi_MAX (0x0000000F) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_RefPi_DEF (0x00000000) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_DllMask_OFF ( 4) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_DllMask_WID ( 2) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_DllMask_MSK (0x00000030) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_DllMask_MAX (0x00000003) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_DllMask_DEF (0x00000000) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_DllWeakLock_OFF ( 6) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_DllWeakLock_WID ( 1) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_DllWeakLock_MSK (0x00000040) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_DllWeakLock_MAX (0x00000001) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_DllWeakLock_DEF (0x00000000) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_OFF ( 7) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_WID ( 3) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MSK (0x00000380) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MAX (0x00000007) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_DEF (0x00000000) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_OFF (10) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_WID ( 3) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_MSK (0x00001C00) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_MAX (0x00000007) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_DEF (0x00000000) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_OdtDelay_OFF (13) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_OdtDelay_WID ( 4) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_OdtDelay_MSK (0x0001E000) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_OdtDelay_MAX (0x0000000F) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_OdtDelay_DEF (0x00000000) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_OdtDuration_OFF (17) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_OdtDuration_WID ( 3) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_OdtDuration_MSK (0x000E0000) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_OdtDuration_MAX (0x00000007) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_OdtDuration_DEF (0x00000000) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_OFF (20) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_WID ( 4) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_MSK (0x00F00000) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_MAX (0x0000000F) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_DEF (0x00000000) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_OFF (24) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_WID ( 3) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_MSK (0x07000000) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_MAX (0x00000007) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_DEF (0x00000000) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_OFF (27) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_WID ( 3) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_MSK (0x38000000) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_MAX (0x00000007) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_DEF (0x00000000) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_OFF (30) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_WID ( 1) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_MSK (0x40000000) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_MAX (0x00000001) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_DEF (0x00000000) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_Rsvd1_OFF (31) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_Rsvd1_WID ( 1) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_Rsvd1_MSK (0x80000000) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_Rsvd1_MAX (0x00000001) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_Rsvd1_DEF (0x00000000) + +#define DDRDATA8CH0_CR_DDRCRDATACONTROL2_REG (0x00001064) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_OFF ( 0) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_WID ( 5) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_MSK (0x0000001F) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_MAX (0x0000001F) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_DEF (0x00000000) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_OFF ( 5) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_WID ( 1) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_MSK (0x00000020) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_MAX (0x00000001) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_DEF (0x00000000) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_ForceRxOn_OFF ( 6) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_ForceRxOn_WID ( 1) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_ForceRxOn_MSK (0x00000040) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_ForceRxOn_MAX (0x00000001) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_ForceRxOn_DEF (0x00000000) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_LeakerComp_OFF ( 7) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_LeakerComp_WID ( 2) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_LeakerComp_MSK (0x00000180) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_LeakerComp_MAX (0x00000003) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_LeakerComp_DEF (0x00000000) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_OFF ( 9) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_WID ( 4) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_MSK (0x00001E00) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_MAX (0x0000000F) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_DEF (0x00000008) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_OFF (13) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_WID ( 5) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_MSK (0x0003E000) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_MAX (0x0000001F) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_DEF (0x00000011) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_OFF (18) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_WID ( 1) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_MSK (0x00040000) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_MAX (0x00000001) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_DEF (0x00000000) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_Spare_OFF (19) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_Spare_WID (13) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_Spare_MSK (0xFFF80000) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_Spare_MAX (0x00001FFF) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_Spare_DEF (0x00000000) + +#define DDRDATA8CH0_CR_DDRCRVSSHIORVREFCONTROL_REG (0x0000106C) + #define DDRDATA8CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_OFF ( 0) + #define DDRDATA8CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_WID (24) + #define DDRDATA8CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_MSK (0x00FFFFFF) + #define DDRDATA8CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_MAX (0x00FFFFFF) + #define DDRDATA8CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_DEF (0x00000000) + #define DDRDATA8CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_OFF (24) + #define DDRDATA8CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_WID ( 8) + #define DDRDATA8CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_MSK (0xFF000000) + #define DDRDATA8CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_MAX (0x000000FF) + #define DDRDATA8CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_DEF (0x00000000) + +#define DDRDATA8CH0_CR_DDRCRDATAOFFSETTRAIN_REG (0x00001070) + #define DDRDATA8CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_OFF ( 0) + #define DDRDATA8CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_WID ( 6) + #define DDRDATA8CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MSK (0x0000003F) + #define DDRDATA8CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MAX (0x0000003F) + #define DDRDATA8CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_DEF (0x00000000) + #define DDRDATA8CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_OFF ( 6) + #define DDRDATA8CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_WID ( 6) + #define DDRDATA8CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MSK (0x00000FC0) + #define DDRDATA8CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MAX (0x0000003F) + #define DDRDATA8CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_DEF (0x00000000) + #define DDRDATA8CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_OFF (12) + #define DDRDATA8CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_WID ( 6) + #define DDRDATA8CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MSK (0x0003F000) + #define DDRDATA8CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MAX (0x0000003F) + #define DDRDATA8CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_DEF (0x00000000) + #define DDRDATA8CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_OFF (18) + #define DDRDATA8CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_WID ( 6) + #define DDRDATA8CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MSK (0x00FC0000) + #define DDRDATA8CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MAX (0x0000003F) + #define DDRDATA8CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_DEF (0x00000000) + #define DDRDATA8CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_OFF (24) + #define DDRDATA8CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_WID ( 7) + #define DDRDATA8CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MSK (0x7F000000) + #define DDRDATA8CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MAX (0x0000007F) + #define DDRDATA8CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_DEF (0x00000000) + #define DDRDATA8CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_OFF (31) + #define DDRDATA8CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_WID ( 1) + #define DDRDATA8CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_MSK (0x80000000) + #define DDRDATA8CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_MAX (0x00000001) + #define DDRDATA8CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_DEF (0x00000000) + +#define DDRDATA8CH0_CR_DDRCRDATACONTROL0_REG (0x00001074) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_OFF ( 0) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_WID ( 1) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_MSK (0x00000001) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_MAX (0x00000001) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_DEF (0x00000000) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_OFF ( 1) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_WID ( 1) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_MSK (0x00000002) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_MAX (0x00000001) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_DEF (0x00000000) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_OFF ( 2) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_WID ( 1) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_MSK (0x00000004) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_MAX (0x00000001) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_DEF (0x00000000) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_OFF ( 3) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_WID ( 1) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MSK (0x00000008) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MAX (0x00000001) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_DEF (0x00000000) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_TxOn_OFF ( 4) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_TxOn_WID ( 1) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_TxOn_MSK (0x00000010) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_TxOn_MAX (0x00000001) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_TxOn_DEF (0x00000000) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RfOn_OFF ( 5) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RfOn_WID ( 1) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RfOn_MSK (0x00000020) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RfOn_MAX (0x00000001) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RfOn_DEF (0x00000000) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RxPiOn_OFF ( 6) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RxPiOn_WID ( 1) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RxPiOn_MSK (0x00000040) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RxPiOn_MAX (0x00000001) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RxPiOn_DEF (0x00000000) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_TxPiOn_OFF ( 7) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_TxPiOn_WID ( 1) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_TxPiOn_MSK (0x00000080) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_TxPiOn_MAX (0x00000001) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_TxPiOn_DEF (0x00000000) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_OFF ( 8) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_WID ( 1) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_MSK (0x00000100) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_MAX (0x00000001) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_DEF (0x00000000) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_OFF ( 9) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_WID ( 1) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MSK (0x00000200) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MAX (0x00000001) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_DEF (0x00000000) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_TxDisable_OFF (10) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_TxDisable_WID ( 1) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_TxDisable_MSK (0x00000400) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_TxDisable_MAX (0x00000001) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_TxDisable_DEF (0x00000000) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RxDisable_OFF (11) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RxDisable_WID ( 1) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RxDisable_MSK (0x00000800) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RxDisable_MAX (0x00000001) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RxDisable_DEF (0x00000000) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_TxLong_OFF (12) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_TxLong_WID ( 1) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_TxLong_MSK (0x00001000) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_TxLong_MAX (0x00000001) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_TxLong_DEF (0x00000000) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_OFF (13) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_WID ( 2) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_MSK (0x00006000) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_MAX (0x00000003) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_DEF (0x00000000) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RxReadPointer_OFF (15) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RxReadPointer_WID ( 3) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RxReadPointer_MSK (0x00038000) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RxReadPointer_MAX (0x00000007) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RxReadPointer_DEF (0x00000000) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_OFF (18) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_WID ( 1) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_MSK (0x00040000) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_MAX (0x00000001) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_DEF (0x00000000) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_OFF (19) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_WID ( 1) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_MSK (0x00080000) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_MAX (0x00000001) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_DEF (0x00000000) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_ReadRFRd_OFF (20) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_ReadRFRd_WID ( 1) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_ReadRFRd_MSK (0x00100000) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_ReadRFRd_MAX (0x00000001) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_ReadRFRd_DEF (0x00000000) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_ReadRFWr_OFF (21) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_ReadRFWr_WID ( 1) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_ReadRFWr_MSK (0x00200000) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_ReadRFWr_MAX (0x00000001) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_ReadRFWr_DEF (0x00000000) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_ReadRFRank_OFF (22) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_ReadRFRank_WID ( 2) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_ReadRFRank_MSK (0x00C00000) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_ReadRFRank_MAX (0x00000003) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_ReadRFRank_DEF (0x00000000) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_OFF (24) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_WID ( 1) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_MSK (0x01000000) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_MAX (0x00000001) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_DEF (0x00000000) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_OdtSampOff_OFF (25) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_OdtSampOff_WID ( 1) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_OdtSampOff_MSK (0x02000000) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_OdtSampOff_MAX (0x00000001) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_OdtSampOff_DEF (0x00000000) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_OFF (26) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_WID ( 1) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_MSK (0x04000000) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_MAX (0x00000001) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_DEF (0x00000000) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_OFF (27) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_WID ( 1) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MSK (0x08000000) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MAX (0x00000001) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_DEF (0x00000000) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_OFF (28) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_WID ( 1) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_MSK (0x10000000) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_MAX (0x00000001) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_DEF (0x00000000) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_OFF (29) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_WID ( 1) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_MSK (0x20000000) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_MAX (0x00000001) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_DEF (0x00000000) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_OFF (30) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_WID ( 1) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MSK (0x40000000) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MAX (0x00000001) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_DEF (0x00000000) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_OFF (31) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_WID ( 1) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_MSK (0x80000000) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_MAX (0x00000001) + #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_DEF (0x00000000) + +#define DDRDATA8CH0_CR_DDRCRVREFADJUST1_REG (0x00001078) + #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_OFF ( 0) + #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_WID ( 7) + #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_MSK (0x0000007F) + #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_MAX (0x0000007F) + #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_DEF (0x00000000) + #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_OFF ( 7) + #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_WID ( 7) + #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_MSK (0x00003F80) + #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_MAX (0x0000007F) + #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_DEF (0x00000000) + #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_OFF (14) + #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_WID ( 7) + #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_MSK (0x001FC000) + #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_MAX (0x0000007F) + #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_DEF (0x00000000) + #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_OFF (21) + #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_WID ( 1) + #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_MSK (0x00200000) + #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_MAX (0x00000001) + #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_DEF (0x00000000) + #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_OFF (22) + #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_WID ( 1) + #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_MSK (0x00400000) + #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_MAX (0x00000001) + #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_DEF (0x00000000) + #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_OFF (23) + #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_WID ( 1) + #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_MSK (0x00800000) + #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_MAX (0x00000001) + #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_DEF (0x00000000) + #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_OFF (24) + #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_WID ( 2) + #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_MSK (0x03000000) + #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_MAX (0x00000003) + #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_DEF (0x00000000) + #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_OFF (26) + #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_WID ( 1) + #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_MSK (0x04000000) + #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_MAX (0x00000001) + #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_DEF (0x00000000) + #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_Rsvd_OFF (27) + #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_Rsvd_WID ( 2) + #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_Rsvd_MSK (0x18000000) + #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_Rsvd_MAX (0x00000003) + #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_Rsvd_DEF (0x00000000) + #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_caSlowBW_OFF (29) + #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_caSlowBW_WID ( 1) + #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_caSlowBW_MSK (0x20000000) + #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_caSlowBW_MAX (0x00000001) + #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_caSlowBW_DEF (0x00000000) + #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_OFF (30) + #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_WID ( 1) + #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_MSK (0x40000000) + #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_MAX (0x00000001) + #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_DEF (0x00000000) + #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_OFF (31) + #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_WID ( 1) + #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_MSK (0x80000000) + #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_MAX (0x00000001) + #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_DEF (0x00000000) + +#define DDRDATA8CH1_CR_RXTRAINRANK0_REG (0x00001100) + #define DDRDATA8CH1_CR_RXTRAINRANK0_RxRcvEnPi_OFF ( 0) + #define DDRDATA8CH1_CR_RXTRAINRANK0_RxRcvEnPi_WID ( 9) + #define DDRDATA8CH1_CR_RXTRAINRANK0_RxRcvEnPi_MSK (0x000001FF) + #define DDRDATA8CH1_CR_RXTRAINRANK0_RxRcvEnPi_MAX (0x000001FF) + #define DDRDATA8CH1_CR_RXTRAINRANK0_RxDqsPPi_OFF ( 9) + #define DDRDATA8CH1_CR_RXTRAINRANK0_RxDqsPPi_WID ( 6) + #define DDRDATA8CH1_CR_RXTRAINRANK0_RxDqsPPi_MSK (0x00007E00) + #define DDRDATA8CH1_CR_RXTRAINRANK0_RxDqsPPi_MAX (0x0000003F) + #define DDRDATA8CH1_CR_RXTRAINRANK0_RxEq_OFF (15) + #define DDRDATA8CH1_CR_RXTRAINRANK0_RxEq_WID ( 5) + #define DDRDATA8CH1_CR_RXTRAINRANK0_RxEq_MSK (0x000F8000) + #define DDRDATA8CH1_CR_RXTRAINRANK0_RxEq_MAX (0x0000001F) + #define DDRDATA8CH1_CR_RXTRAINRANK0_RxDqsNPi_OFF (20) + #define DDRDATA8CH1_CR_RXTRAINRANK0_RxDqsNPi_WID ( 6) + #define DDRDATA8CH1_CR_RXTRAINRANK0_RxDqsNPi_MSK (0x03F00000) + #define DDRDATA8CH1_CR_RXTRAINRANK0_RxDqsNPi_MAX (0x0000003F) + #define DDRDATA8CH1_CR_RXTRAINRANK0_RxVref_OFF (26) + #define DDRDATA8CH1_CR_RXTRAINRANK0_RxVref_WID ( 6) + #define DDRDATA8CH1_CR_RXTRAINRANK0_RxVref_MSK (0xFC000000) + #define DDRDATA8CH1_CR_RXTRAINRANK0_RxVref_MAX (0x0000003F) + +#define DDRDATA8CH1_CR_RXTRAINRANK1_REG (0x00001104) + #define DDRDATA8CH1_CR_RXTRAINRANK1_RxRcvEnPi_OFF ( 0) + #define DDRDATA8CH1_CR_RXTRAINRANK1_RxRcvEnPi_WID ( 9) + #define DDRDATA8CH1_CR_RXTRAINRANK1_RxRcvEnPi_MSK (0x000001FF) + #define DDRDATA8CH1_CR_RXTRAINRANK1_RxRcvEnPi_MAX (0x000001FF) + #define DDRDATA8CH1_CR_RXTRAINRANK1_RxDqsPPi_OFF ( 9) + #define DDRDATA8CH1_CR_RXTRAINRANK1_RxDqsPPi_WID ( 6) + #define DDRDATA8CH1_CR_RXTRAINRANK1_RxDqsPPi_MSK (0x00007E00) + #define DDRDATA8CH1_CR_RXTRAINRANK1_RxDqsPPi_MAX (0x0000003F) + #define DDRDATA8CH1_CR_RXTRAINRANK1_RxEq_OFF (15) + #define DDRDATA8CH1_CR_RXTRAINRANK1_RxEq_WID ( 5) + #define DDRDATA8CH1_CR_RXTRAINRANK1_RxEq_MSK (0x000F8000) + #define DDRDATA8CH1_CR_RXTRAINRANK1_RxEq_MAX (0x0000001F) + #define DDRDATA8CH1_CR_RXTRAINRANK1_RxDqsNPi_OFF (20) + #define DDRDATA8CH1_CR_RXTRAINRANK1_RxDqsNPi_WID ( 6) + #define DDRDATA8CH1_CR_RXTRAINRANK1_RxDqsNPi_MSK (0x03F00000) + #define DDRDATA8CH1_CR_RXTRAINRANK1_RxDqsNPi_MAX (0x0000003F) + #define DDRDATA8CH1_CR_RXTRAINRANK1_RxVref_OFF (26) + #define DDRDATA8CH1_CR_RXTRAINRANK1_RxVref_WID ( 6) + #define DDRDATA8CH1_CR_RXTRAINRANK1_RxVref_MSK (0xFC000000) + #define DDRDATA8CH1_CR_RXTRAINRANK1_RxVref_MAX (0x0000003F) + +#define DDRDATA8CH1_CR_RXTRAINRANK2_REG (0x00001108) + #define DDRDATA8CH1_CR_RXTRAINRANK2_RxRcvEnPi_OFF ( 0) + #define DDRDATA8CH1_CR_RXTRAINRANK2_RxRcvEnPi_WID ( 9) + #define DDRDATA8CH1_CR_RXTRAINRANK2_RxRcvEnPi_MSK (0x000001FF) + #define DDRDATA8CH1_CR_RXTRAINRANK2_RxRcvEnPi_MAX (0x000001FF) + #define DDRDATA8CH1_CR_RXTRAINRANK2_RxDqsPPi_OFF ( 9) + #define DDRDATA8CH1_CR_RXTRAINRANK2_RxDqsPPi_WID ( 6) + #define DDRDATA8CH1_CR_RXTRAINRANK2_RxDqsPPi_MSK (0x00007E00) + #define DDRDATA8CH1_CR_RXTRAINRANK2_RxDqsPPi_MAX (0x0000003F) + #define DDRDATA8CH1_CR_RXTRAINRANK2_RxEq_OFF (15) + #define DDRDATA8CH1_CR_RXTRAINRANK2_RxEq_WID ( 5) + #define DDRDATA8CH1_CR_RXTRAINRANK2_RxEq_MSK (0x000F8000) + #define DDRDATA8CH1_CR_RXTRAINRANK2_RxEq_MAX (0x0000001F) + #define DDRDATA8CH1_CR_RXTRAINRANK2_RxDqsNPi_OFF (20) + #define DDRDATA8CH1_CR_RXTRAINRANK2_RxDqsNPi_WID ( 6) + #define DDRDATA8CH1_CR_RXTRAINRANK2_RxDqsNPi_MSK (0x03F00000) + #define DDRDATA8CH1_CR_RXTRAINRANK2_RxDqsNPi_MAX (0x0000003F) + #define DDRDATA8CH1_CR_RXTRAINRANK2_RxVref_OFF (26) + #define DDRDATA8CH1_CR_RXTRAINRANK2_RxVref_WID ( 6) + #define DDRDATA8CH1_CR_RXTRAINRANK2_RxVref_MSK (0xFC000000) + #define DDRDATA8CH1_CR_RXTRAINRANK2_RxVref_MAX (0x0000003F) + +#define DDRDATA8CH1_CR_RXTRAINRANK3_REG (0x0000110C) + #define DDRDATA8CH1_CR_RXTRAINRANK3_RxRcvEnPi_OFF ( 0) + #define DDRDATA8CH1_CR_RXTRAINRANK3_RxRcvEnPi_WID ( 9) + #define DDRDATA8CH1_CR_RXTRAINRANK3_RxRcvEnPi_MSK (0x000001FF) + #define DDRDATA8CH1_CR_RXTRAINRANK3_RxRcvEnPi_MAX (0x000001FF) + #define DDRDATA8CH1_CR_RXTRAINRANK3_RxDqsPPi_OFF ( 9) + #define DDRDATA8CH1_CR_RXTRAINRANK3_RxDqsPPi_WID ( 6) + #define DDRDATA8CH1_CR_RXTRAINRANK3_RxDqsPPi_MSK (0x00007E00) + #define DDRDATA8CH1_CR_RXTRAINRANK3_RxDqsPPi_MAX (0x0000003F) + #define DDRDATA8CH1_CR_RXTRAINRANK3_RxEq_OFF (15) + #define DDRDATA8CH1_CR_RXTRAINRANK3_RxEq_WID ( 5) + #define DDRDATA8CH1_CR_RXTRAINRANK3_RxEq_MSK (0x000F8000) + #define DDRDATA8CH1_CR_RXTRAINRANK3_RxEq_MAX (0x0000001F) + #define DDRDATA8CH1_CR_RXTRAINRANK3_RxDqsNPi_OFF (20) + #define DDRDATA8CH1_CR_RXTRAINRANK3_RxDqsNPi_WID ( 6) + #define DDRDATA8CH1_CR_RXTRAINRANK3_RxDqsNPi_MSK (0x03F00000) + #define DDRDATA8CH1_CR_RXTRAINRANK3_RxDqsNPi_MAX (0x0000003F) + #define DDRDATA8CH1_CR_RXTRAINRANK3_RxVref_OFF (26) + #define DDRDATA8CH1_CR_RXTRAINRANK3_RxVref_WID ( 6) + #define DDRDATA8CH1_CR_RXTRAINRANK3_RxVref_MSK (0xFC000000) + #define DDRDATA8CH1_CR_RXTRAINRANK3_RxVref_MAX (0x0000003F) + +#define DDRDATA8CH1_CR_RXPERBITRANK0_REG (0x00001110) + #define DDRDATA8CH1_CR_RXPERBITRANK0_Lane0_OFF ( 0) + #define DDRDATA8CH1_CR_RXPERBITRANK0_Lane0_WID ( 4) + #define DDRDATA8CH1_CR_RXPERBITRANK0_Lane0_MSK (0x0000000F) + #define DDRDATA8CH1_CR_RXPERBITRANK0_Lane0_MAX (0x0000000F) + #define DDRDATA8CH1_CR_RXPERBITRANK0_Lane1_OFF ( 4) + #define DDRDATA8CH1_CR_RXPERBITRANK0_Lane1_WID ( 4) + #define DDRDATA8CH1_CR_RXPERBITRANK0_Lane1_MSK (0x000000F0) + #define DDRDATA8CH1_CR_RXPERBITRANK0_Lane1_MAX (0x0000000F) + #define DDRDATA8CH1_CR_RXPERBITRANK0_Lane2_OFF ( 8) + #define DDRDATA8CH1_CR_RXPERBITRANK0_Lane2_WID ( 4) + #define DDRDATA8CH1_CR_RXPERBITRANK0_Lane2_MSK (0x00000F00) + #define DDRDATA8CH1_CR_RXPERBITRANK0_Lane2_MAX (0x0000000F) + #define DDRDATA8CH1_CR_RXPERBITRANK0_Lane3_OFF (12) + #define DDRDATA8CH1_CR_RXPERBITRANK0_Lane3_WID ( 4) + #define DDRDATA8CH1_CR_RXPERBITRANK0_Lane3_MSK (0x0000F000) + #define DDRDATA8CH1_CR_RXPERBITRANK0_Lane3_MAX (0x0000000F) + #define DDRDATA8CH1_CR_RXPERBITRANK0_Lane4_OFF (16) + #define DDRDATA8CH1_CR_RXPERBITRANK0_Lane4_WID ( 4) + #define DDRDATA8CH1_CR_RXPERBITRANK0_Lane4_MSK (0x000F0000) + #define DDRDATA8CH1_CR_RXPERBITRANK0_Lane4_MAX (0x0000000F) + #define DDRDATA8CH1_CR_RXPERBITRANK0_Lane5_OFF (20) + #define DDRDATA8CH1_CR_RXPERBITRANK0_Lane5_WID ( 4) + #define DDRDATA8CH1_CR_RXPERBITRANK0_Lane5_MSK (0x00F00000) + #define DDRDATA8CH1_CR_RXPERBITRANK0_Lane5_MAX (0x0000000F) + #define DDRDATA8CH1_CR_RXPERBITRANK0_Lane6_OFF (24) + #define DDRDATA8CH1_CR_RXPERBITRANK0_Lane6_WID ( 4) + #define DDRDATA8CH1_CR_RXPERBITRANK0_Lane6_MSK (0x0F000000) + #define DDRDATA8CH1_CR_RXPERBITRANK0_Lane6_MAX (0x0000000F) + #define DDRDATA8CH1_CR_RXPERBITRANK0_Lane7_OFF (28) + #define DDRDATA8CH1_CR_RXPERBITRANK0_Lane7_WID ( 4) + #define DDRDATA8CH1_CR_RXPERBITRANK0_Lane7_MSK (0xF0000000) + #define DDRDATA8CH1_CR_RXPERBITRANK0_Lane7_MAX (0x0000000F) + +#define DDRDATA8CH1_CR_RXPERBITRANK1_REG (0x00001114) + #define DDRDATA8CH1_CR_RXPERBITRANK1_Lane0_OFF ( 0) + #define DDRDATA8CH1_CR_RXPERBITRANK1_Lane0_WID ( 4) + #define DDRDATA8CH1_CR_RXPERBITRANK1_Lane0_MSK (0x0000000F) + #define DDRDATA8CH1_CR_RXPERBITRANK1_Lane0_MAX (0x0000000F) + #define DDRDATA8CH1_CR_RXPERBITRANK1_Lane1_OFF ( 4) + #define DDRDATA8CH1_CR_RXPERBITRANK1_Lane1_WID ( 4) + #define DDRDATA8CH1_CR_RXPERBITRANK1_Lane1_MSK (0x000000F0) + #define DDRDATA8CH1_CR_RXPERBITRANK1_Lane1_MAX (0x0000000F) + #define DDRDATA8CH1_CR_RXPERBITRANK1_Lane2_OFF ( 8) + #define DDRDATA8CH1_CR_RXPERBITRANK1_Lane2_WID ( 4) + #define DDRDATA8CH1_CR_RXPERBITRANK1_Lane2_MSK (0x00000F00) + #define DDRDATA8CH1_CR_RXPERBITRANK1_Lane2_MAX (0x0000000F) + #define DDRDATA8CH1_CR_RXPERBITRANK1_Lane3_OFF (12) + #define DDRDATA8CH1_CR_RXPERBITRANK1_Lane3_WID ( 4) + #define DDRDATA8CH1_CR_RXPERBITRANK1_Lane3_MSK (0x0000F000) + #define DDRDATA8CH1_CR_RXPERBITRANK1_Lane3_MAX (0x0000000F) + #define DDRDATA8CH1_CR_RXPERBITRANK1_Lane4_OFF (16) + #define DDRDATA8CH1_CR_RXPERBITRANK1_Lane4_WID ( 4) + #define DDRDATA8CH1_CR_RXPERBITRANK1_Lane4_MSK (0x000F0000) + #define DDRDATA8CH1_CR_RXPERBITRANK1_Lane4_MAX (0x0000000F) + #define DDRDATA8CH1_CR_RXPERBITRANK1_Lane5_OFF (20) + #define DDRDATA8CH1_CR_RXPERBITRANK1_Lane5_WID ( 4) + #define DDRDATA8CH1_CR_RXPERBITRANK1_Lane5_MSK (0x00F00000) + #define DDRDATA8CH1_CR_RXPERBITRANK1_Lane5_MAX (0x0000000F) + #define DDRDATA8CH1_CR_RXPERBITRANK1_Lane6_OFF (24) + #define DDRDATA8CH1_CR_RXPERBITRANK1_Lane6_WID ( 4) + #define DDRDATA8CH1_CR_RXPERBITRANK1_Lane6_MSK (0x0F000000) + #define DDRDATA8CH1_CR_RXPERBITRANK1_Lane6_MAX (0x0000000F) + #define DDRDATA8CH1_CR_RXPERBITRANK1_Lane7_OFF (28) + #define DDRDATA8CH1_CR_RXPERBITRANK1_Lane7_WID ( 4) + #define DDRDATA8CH1_CR_RXPERBITRANK1_Lane7_MSK (0xF0000000) + #define DDRDATA8CH1_CR_RXPERBITRANK1_Lane7_MAX (0x0000000F) + +#define DDRDATA8CH1_CR_RXPERBITRANK2_REG (0x00001118) + #define DDRDATA8CH1_CR_RXPERBITRANK2_Lane0_OFF ( 0) + #define DDRDATA8CH1_CR_RXPERBITRANK2_Lane0_WID ( 4) + #define DDRDATA8CH1_CR_RXPERBITRANK2_Lane0_MSK (0x0000000F) + #define DDRDATA8CH1_CR_RXPERBITRANK2_Lane0_MAX (0x0000000F) + #define DDRDATA8CH1_CR_RXPERBITRANK2_Lane1_OFF ( 4) + #define DDRDATA8CH1_CR_RXPERBITRANK2_Lane1_WID ( 4) + #define DDRDATA8CH1_CR_RXPERBITRANK2_Lane1_MSK (0x000000F0) + #define DDRDATA8CH1_CR_RXPERBITRANK2_Lane1_MAX (0x0000000F) + #define DDRDATA8CH1_CR_RXPERBITRANK2_Lane2_OFF ( 8) + #define DDRDATA8CH1_CR_RXPERBITRANK2_Lane2_WID ( 4) + #define DDRDATA8CH1_CR_RXPERBITRANK2_Lane2_MSK (0x00000F00) + #define DDRDATA8CH1_CR_RXPERBITRANK2_Lane2_MAX (0x0000000F) + #define DDRDATA8CH1_CR_RXPERBITRANK2_Lane3_OFF (12) + #define DDRDATA8CH1_CR_RXPERBITRANK2_Lane3_WID ( 4) + #define DDRDATA8CH1_CR_RXPERBITRANK2_Lane3_MSK (0x0000F000) + #define DDRDATA8CH1_CR_RXPERBITRANK2_Lane3_MAX (0x0000000F) + #define DDRDATA8CH1_CR_RXPERBITRANK2_Lane4_OFF (16) + #define DDRDATA8CH1_CR_RXPERBITRANK2_Lane4_WID ( 4) + #define DDRDATA8CH1_CR_RXPERBITRANK2_Lane4_MSK (0x000F0000) + #define DDRDATA8CH1_CR_RXPERBITRANK2_Lane4_MAX (0x0000000F) + #define DDRDATA8CH1_CR_RXPERBITRANK2_Lane5_OFF (20) + #define DDRDATA8CH1_CR_RXPERBITRANK2_Lane5_WID ( 4) + #define DDRDATA8CH1_CR_RXPERBITRANK2_Lane5_MSK (0x00F00000) + #define DDRDATA8CH1_CR_RXPERBITRANK2_Lane5_MAX (0x0000000F) + #define DDRDATA8CH1_CR_RXPERBITRANK2_Lane6_OFF (24) + #define DDRDATA8CH1_CR_RXPERBITRANK2_Lane6_WID ( 4) + #define DDRDATA8CH1_CR_RXPERBITRANK2_Lane6_MSK (0x0F000000) + #define DDRDATA8CH1_CR_RXPERBITRANK2_Lane6_MAX (0x0000000F) + #define DDRDATA8CH1_CR_RXPERBITRANK2_Lane7_OFF (28) + #define DDRDATA8CH1_CR_RXPERBITRANK2_Lane7_WID ( 4) + #define DDRDATA8CH1_CR_RXPERBITRANK2_Lane7_MSK (0xF0000000) + #define DDRDATA8CH1_CR_RXPERBITRANK2_Lane7_MAX (0x0000000F) + +#define DDRDATA8CH1_CR_RXPERBITRANK3_REG (0x0000111C) + #define DDRDATA8CH1_CR_RXPERBITRANK3_Lane0_OFF ( 0) + #define DDRDATA8CH1_CR_RXPERBITRANK3_Lane0_WID ( 4) + #define DDRDATA8CH1_CR_RXPERBITRANK3_Lane0_MSK (0x0000000F) + #define DDRDATA8CH1_CR_RXPERBITRANK3_Lane0_MAX (0x0000000F) + #define DDRDATA8CH1_CR_RXPERBITRANK3_Lane1_OFF ( 4) + #define DDRDATA8CH1_CR_RXPERBITRANK3_Lane1_WID ( 4) + #define DDRDATA8CH1_CR_RXPERBITRANK3_Lane1_MSK (0x000000F0) + #define DDRDATA8CH1_CR_RXPERBITRANK3_Lane1_MAX (0x0000000F) + #define DDRDATA8CH1_CR_RXPERBITRANK3_Lane2_OFF ( 8) + #define DDRDATA8CH1_CR_RXPERBITRANK3_Lane2_WID ( 4) + #define DDRDATA8CH1_CR_RXPERBITRANK3_Lane2_MSK (0x00000F00) + #define DDRDATA8CH1_CR_RXPERBITRANK3_Lane2_MAX (0x0000000F) + #define DDRDATA8CH1_CR_RXPERBITRANK3_Lane3_OFF (12) + #define DDRDATA8CH1_CR_RXPERBITRANK3_Lane3_WID ( 4) + #define DDRDATA8CH1_CR_RXPERBITRANK3_Lane3_MSK (0x0000F000) + #define DDRDATA8CH1_CR_RXPERBITRANK3_Lane3_MAX (0x0000000F) + #define DDRDATA8CH1_CR_RXPERBITRANK3_Lane4_OFF (16) + #define DDRDATA8CH1_CR_RXPERBITRANK3_Lane4_WID ( 4) + #define DDRDATA8CH1_CR_RXPERBITRANK3_Lane4_MSK (0x000F0000) + #define DDRDATA8CH1_CR_RXPERBITRANK3_Lane4_MAX (0x0000000F) + #define DDRDATA8CH1_CR_RXPERBITRANK3_Lane5_OFF (20) + #define DDRDATA8CH1_CR_RXPERBITRANK3_Lane5_WID ( 4) + #define DDRDATA8CH1_CR_RXPERBITRANK3_Lane5_MSK (0x00F00000) + #define DDRDATA8CH1_CR_RXPERBITRANK3_Lane5_MAX (0x0000000F) + #define DDRDATA8CH1_CR_RXPERBITRANK3_Lane6_OFF (24) + #define DDRDATA8CH1_CR_RXPERBITRANK3_Lane6_WID ( 4) + #define DDRDATA8CH1_CR_RXPERBITRANK3_Lane6_MSK (0x0F000000) + #define DDRDATA8CH1_CR_RXPERBITRANK3_Lane6_MAX (0x0000000F) + #define DDRDATA8CH1_CR_RXPERBITRANK3_Lane7_OFF (28) + #define DDRDATA8CH1_CR_RXPERBITRANK3_Lane7_WID ( 4) + #define DDRDATA8CH1_CR_RXPERBITRANK3_Lane7_MSK (0xF0000000) + #define DDRDATA8CH1_CR_RXPERBITRANK3_Lane7_MAX (0x0000000F) + +#define DDRDATA8CH1_CR_TXTRAINRANK0_REG (0x00001120) + #define DDRDATA8CH1_CR_TXTRAINRANK0_TxDqDelay_OFF ( 0) + #define DDRDATA8CH1_CR_TXTRAINRANK0_TxDqDelay_WID ( 9) + #define DDRDATA8CH1_CR_TXTRAINRANK0_TxDqDelay_MSK (0x000001FF) + #define DDRDATA8CH1_CR_TXTRAINRANK0_TxDqDelay_MAX (0x000001FF) + #define DDRDATA8CH1_CR_TXTRAINRANK0_TxDqsDelay_OFF ( 9) + #define DDRDATA8CH1_CR_TXTRAINRANK0_TxDqsDelay_WID ( 9) + #define DDRDATA8CH1_CR_TXTRAINRANK0_TxDqsDelay_MSK (0x0003FE00) + #define DDRDATA8CH1_CR_TXTRAINRANK0_TxDqsDelay_MAX (0x000001FF) + #define DDRDATA8CH1_CR_TXTRAINRANK0_Spare0_OFF (18) + #define DDRDATA8CH1_CR_TXTRAINRANK0_Spare0_WID ( 2) + #define DDRDATA8CH1_CR_TXTRAINRANK0_Spare0_MSK (0x000C0000) + #define DDRDATA8CH1_CR_TXTRAINRANK0_Spare0_MAX (0x00000003) + #define DDRDATA8CH1_CR_TXTRAINRANK0_TxEqualization_OFF (20) + #define DDRDATA8CH1_CR_TXTRAINRANK0_TxEqualization_WID ( 6) + #define DDRDATA8CH1_CR_TXTRAINRANK0_TxEqualization_MSK (0x03F00000) + #define DDRDATA8CH1_CR_TXTRAINRANK0_TxEqualization_MAX (0x0000003F) + #define DDRDATA8CH1_CR_TXTRAINRANK0_Spare1_OFF (26) + #define DDRDATA8CH1_CR_TXTRAINRANK0_Spare1_WID ( 6) + #define DDRDATA8CH1_CR_TXTRAINRANK0_Spare1_MSK (0xFC000000) + #define DDRDATA8CH1_CR_TXTRAINRANK0_Spare1_MAX (0x0000003F) + +#define DDRDATA8CH1_CR_TXTRAINRANK1_REG (0x00001124) + #define DDRDATA8CH1_CR_TXTRAINRANK1_TxDqDelay_OFF ( 0) + #define DDRDATA8CH1_CR_TXTRAINRANK1_TxDqDelay_WID ( 9) + #define DDRDATA8CH1_CR_TXTRAINRANK1_TxDqDelay_MSK (0x000001FF) + #define DDRDATA8CH1_CR_TXTRAINRANK1_TxDqDelay_MAX (0x000001FF) + #define DDRDATA8CH1_CR_TXTRAINRANK1_TxDqsDelay_OFF ( 9) + #define DDRDATA8CH1_CR_TXTRAINRANK1_TxDqsDelay_WID ( 9) + #define DDRDATA8CH1_CR_TXTRAINRANK1_TxDqsDelay_MSK (0x0003FE00) + #define DDRDATA8CH1_CR_TXTRAINRANK1_TxDqsDelay_MAX (0x000001FF) + #define DDRDATA8CH1_CR_TXTRAINRANK1_Spare0_OFF (18) + #define DDRDATA8CH1_CR_TXTRAINRANK1_Spare0_WID ( 2) + #define DDRDATA8CH1_CR_TXTRAINRANK1_Spare0_MSK (0x000C0000) + #define DDRDATA8CH1_CR_TXTRAINRANK1_Spare0_MAX (0x00000003) + #define DDRDATA8CH1_CR_TXTRAINRANK1_TxEqualization_OFF (20) + #define DDRDATA8CH1_CR_TXTRAINRANK1_TxEqualization_WID ( 6) + #define DDRDATA8CH1_CR_TXTRAINRANK1_TxEqualization_MSK (0x03F00000) + #define DDRDATA8CH1_CR_TXTRAINRANK1_TxEqualization_MAX (0x0000003F) + #define DDRDATA8CH1_CR_TXTRAINRANK1_Spare1_OFF (26) + #define DDRDATA8CH1_CR_TXTRAINRANK1_Spare1_WID ( 6) + #define DDRDATA8CH1_CR_TXTRAINRANK1_Spare1_MSK (0xFC000000) + #define DDRDATA8CH1_CR_TXTRAINRANK1_Spare1_MAX (0x0000003F) + +#define DDRDATA8CH1_CR_TXTRAINRANK2_REG (0x00001128) + #define DDRDATA8CH1_CR_TXTRAINRANK2_TxDqDelay_OFF ( 0) + #define DDRDATA8CH1_CR_TXTRAINRANK2_TxDqDelay_WID ( 9) + #define DDRDATA8CH1_CR_TXTRAINRANK2_TxDqDelay_MSK (0x000001FF) + #define DDRDATA8CH1_CR_TXTRAINRANK2_TxDqDelay_MAX (0x000001FF) + #define DDRDATA8CH1_CR_TXTRAINRANK2_TxDqsDelay_OFF ( 9) + #define DDRDATA8CH1_CR_TXTRAINRANK2_TxDqsDelay_WID ( 9) + #define DDRDATA8CH1_CR_TXTRAINRANK2_TxDqsDelay_MSK (0x0003FE00) + #define DDRDATA8CH1_CR_TXTRAINRANK2_TxDqsDelay_MAX (0x000001FF) + #define DDRDATA8CH1_CR_TXTRAINRANK2_Spare0_OFF (18) + #define DDRDATA8CH1_CR_TXTRAINRANK2_Spare0_WID ( 2) + #define DDRDATA8CH1_CR_TXTRAINRANK2_Spare0_MSK (0x000C0000) + #define DDRDATA8CH1_CR_TXTRAINRANK2_Spare0_MAX (0x00000003) + #define DDRDATA8CH1_CR_TXTRAINRANK2_TxEqualization_OFF (20) + #define DDRDATA8CH1_CR_TXTRAINRANK2_TxEqualization_WID ( 6) + #define DDRDATA8CH1_CR_TXTRAINRANK2_TxEqualization_MSK (0x03F00000) + #define DDRDATA8CH1_CR_TXTRAINRANK2_TxEqualization_MAX (0x0000003F) + #define DDRDATA8CH1_CR_TXTRAINRANK2_Spare1_OFF (26) + #define DDRDATA8CH1_CR_TXTRAINRANK2_Spare1_WID ( 6) + #define DDRDATA8CH1_CR_TXTRAINRANK2_Spare1_MSK (0xFC000000) + #define DDRDATA8CH1_CR_TXTRAINRANK2_Spare1_MAX (0x0000003F) + +#define DDRDATA8CH1_CR_TXTRAINRANK3_REG (0x0000112C) + #define DDRDATA8CH1_CR_TXTRAINRANK3_TxDqDelay_OFF ( 0) + #define DDRDATA8CH1_CR_TXTRAINRANK3_TxDqDelay_WID ( 9) + #define DDRDATA8CH1_CR_TXTRAINRANK3_TxDqDelay_MSK (0x000001FF) + #define DDRDATA8CH1_CR_TXTRAINRANK3_TxDqDelay_MAX (0x000001FF) + #define DDRDATA8CH1_CR_TXTRAINRANK3_TxDqsDelay_OFF ( 9) + #define DDRDATA8CH1_CR_TXTRAINRANK3_TxDqsDelay_WID ( 9) + #define DDRDATA8CH1_CR_TXTRAINRANK3_TxDqsDelay_MSK (0x0003FE00) + #define DDRDATA8CH1_CR_TXTRAINRANK3_TxDqsDelay_MAX (0x000001FF) + #define DDRDATA8CH1_CR_TXTRAINRANK3_Spare0_OFF (18) + #define DDRDATA8CH1_CR_TXTRAINRANK3_Spare0_WID ( 2) + #define DDRDATA8CH1_CR_TXTRAINRANK3_Spare0_MSK (0x000C0000) + #define DDRDATA8CH1_CR_TXTRAINRANK3_Spare0_MAX (0x00000003) + #define DDRDATA8CH1_CR_TXTRAINRANK3_TxEqualization_OFF (20) + #define DDRDATA8CH1_CR_TXTRAINRANK3_TxEqualization_WID ( 6) + #define DDRDATA8CH1_CR_TXTRAINRANK3_TxEqualization_MSK (0x03F00000) + #define DDRDATA8CH1_CR_TXTRAINRANK3_TxEqualization_MAX (0x0000003F) + #define DDRDATA8CH1_CR_TXTRAINRANK3_Spare1_OFF (26) + #define DDRDATA8CH1_CR_TXTRAINRANK3_Spare1_WID ( 6) + #define DDRDATA8CH1_CR_TXTRAINRANK3_Spare1_MSK (0xFC000000) + #define DDRDATA8CH1_CR_TXTRAINRANK3_Spare1_MAX (0x0000003F) + +#define DDRDATA8CH1_CR_TXPERBITRANK0_REG (0x00001130) + #define DDRDATA8CH1_CR_TXPERBITRANK0_Lane0_OFF ( 0) + #define DDRDATA8CH1_CR_TXPERBITRANK0_Lane0_WID ( 4) + #define DDRDATA8CH1_CR_TXPERBITRANK0_Lane0_MSK (0x0000000F) + #define DDRDATA8CH1_CR_TXPERBITRANK0_Lane0_MAX (0x0000000F) + #define DDRDATA8CH1_CR_TXPERBITRANK0_Lane1_OFF ( 4) + #define DDRDATA8CH1_CR_TXPERBITRANK0_Lane1_WID ( 4) + #define DDRDATA8CH1_CR_TXPERBITRANK0_Lane1_MSK (0x000000F0) + #define DDRDATA8CH1_CR_TXPERBITRANK0_Lane1_MAX (0x0000000F) + #define DDRDATA8CH1_CR_TXPERBITRANK0_Lane2_OFF ( 8) + #define DDRDATA8CH1_CR_TXPERBITRANK0_Lane2_WID ( 4) + #define DDRDATA8CH1_CR_TXPERBITRANK0_Lane2_MSK (0x00000F00) + #define DDRDATA8CH1_CR_TXPERBITRANK0_Lane2_MAX (0x0000000F) + #define DDRDATA8CH1_CR_TXPERBITRANK0_Lane3_OFF (12) + #define DDRDATA8CH1_CR_TXPERBITRANK0_Lane3_WID ( 4) + #define DDRDATA8CH1_CR_TXPERBITRANK0_Lane3_MSK (0x0000F000) + #define DDRDATA8CH1_CR_TXPERBITRANK0_Lane3_MAX (0x0000000F) + #define DDRDATA8CH1_CR_TXPERBITRANK0_Lane4_OFF (16) + #define DDRDATA8CH1_CR_TXPERBITRANK0_Lane4_WID ( 4) + #define DDRDATA8CH1_CR_TXPERBITRANK0_Lane4_MSK (0x000F0000) + #define DDRDATA8CH1_CR_TXPERBITRANK0_Lane4_MAX (0x0000000F) + #define DDRDATA8CH1_CR_TXPERBITRANK0_Lane5_OFF (20) + #define DDRDATA8CH1_CR_TXPERBITRANK0_Lane5_WID ( 4) + #define DDRDATA8CH1_CR_TXPERBITRANK0_Lane5_MSK (0x00F00000) + #define DDRDATA8CH1_CR_TXPERBITRANK0_Lane5_MAX (0x0000000F) + #define DDRDATA8CH1_CR_TXPERBITRANK0_Lane6_OFF (24) + #define DDRDATA8CH1_CR_TXPERBITRANK0_Lane6_WID ( 4) + #define DDRDATA8CH1_CR_TXPERBITRANK0_Lane6_MSK (0x0F000000) + #define DDRDATA8CH1_CR_TXPERBITRANK0_Lane6_MAX (0x0000000F) + #define DDRDATA8CH1_CR_TXPERBITRANK0_Lane7_OFF (28) + #define DDRDATA8CH1_CR_TXPERBITRANK0_Lane7_WID ( 4) + #define DDRDATA8CH1_CR_TXPERBITRANK0_Lane7_MSK (0xF0000000) + #define DDRDATA8CH1_CR_TXPERBITRANK0_Lane7_MAX (0x0000000F) + +#define DDRDATA8CH1_CR_TXPERBITRANK1_REG (0x00001134) + #define DDRDATA8CH1_CR_TXPERBITRANK1_Lane0_OFF ( 0) + #define DDRDATA8CH1_CR_TXPERBITRANK1_Lane0_WID ( 4) + #define DDRDATA8CH1_CR_TXPERBITRANK1_Lane0_MSK (0x0000000F) + #define DDRDATA8CH1_CR_TXPERBITRANK1_Lane0_MAX (0x0000000F) + #define DDRDATA8CH1_CR_TXPERBITRANK1_Lane1_OFF ( 4) + #define DDRDATA8CH1_CR_TXPERBITRANK1_Lane1_WID ( 4) + #define DDRDATA8CH1_CR_TXPERBITRANK1_Lane1_MSK (0x000000F0) + #define DDRDATA8CH1_CR_TXPERBITRANK1_Lane1_MAX (0x0000000F) + #define DDRDATA8CH1_CR_TXPERBITRANK1_Lane2_OFF ( 8) + #define DDRDATA8CH1_CR_TXPERBITRANK1_Lane2_WID ( 4) + #define DDRDATA8CH1_CR_TXPERBITRANK1_Lane2_MSK (0x00000F00) + #define DDRDATA8CH1_CR_TXPERBITRANK1_Lane2_MAX (0x0000000F) + #define DDRDATA8CH1_CR_TXPERBITRANK1_Lane3_OFF (12) + #define DDRDATA8CH1_CR_TXPERBITRANK1_Lane3_WID ( 4) + #define DDRDATA8CH1_CR_TXPERBITRANK1_Lane3_MSK (0x0000F000) + #define DDRDATA8CH1_CR_TXPERBITRANK1_Lane3_MAX (0x0000000F) + #define DDRDATA8CH1_CR_TXPERBITRANK1_Lane4_OFF (16) + #define DDRDATA8CH1_CR_TXPERBITRANK1_Lane4_WID ( 4) + #define DDRDATA8CH1_CR_TXPERBITRANK1_Lane4_MSK (0x000F0000) + #define DDRDATA8CH1_CR_TXPERBITRANK1_Lane4_MAX (0x0000000F) + #define DDRDATA8CH1_CR_TXPERBITRANK1_Lane5_OFF (20) + #define DDRDATA8CH1_CR_TXPERBITRANK1_Lane5_WID ( 4) + #define DDRDATA8CH1_CR_TXPERBITRANK1_Lane5_MSK (0x00F00000) + #define DDRDATA8CH1_CR_TXPERBITRANK1_Lane5_MAX (0x0000000F) + #define DDRDATA8CH1_CR_TXPERBITRANK1_Lane6_OFF (24) + #define DDRDATA8CH1_CR_TXPERBITRANK1_Lane6_WID ( 4) + #define DDRDATA8CH1_CR_TXPERBITRANK1_Lane6_MSK (0x0F000000) + #define DDRDATA8CH1_CR_TXPERBITRANK1_Lane6_MAX (0x0000000F) + #define DDRDATA8CH1_CR_TXPERBITRANK1_Lane7_OFF (28) + #define DDRDATA8CH1_CR_TXPERBITRANK1_Lane7_WID ( 4) + #define DDRDATA8CH1_CR_TXPERBITRANK1_Lane7_MSK (0xF0000000) + #define DDRDATA8CH1_CR_TXPERBITRANK1_Lane7_MAX (0x0000000F) + +#define DDRDATA8CH1_CR_TXPERBITRANK2_REG (0x00001138) + #define DDRDATA8CH1_CR_TXPERBITRANK2_Lane0_OFF ( 0) + #define DDRDATA8CH1_CR_TXPERBITRANK2_Lane0_WID ( 4) + #define DDRDATA8CH1_CR_TXPERBITRANK2_Lane0_MSK (0x0000000F) + #define DDRDATA8CH1_CR_TXPERBITRANK2_Lane0_MAX (0x0000000F) + #define DDRDATA8CH1_CR_TXPERBITRANK2_Lane1_OFF ( 4) + #define DDRDATA8CH1_CR_TXPERBITRANK2_Lane1_WID ( 4) + #define DDRDATA8CH1_CR_TXPERBITRANK2_Lane1_MSK (0x000000F0) + #define DDRDATA8CH1_CR_TXPERBITRANK2_Lane1_MAX (0x0000000F) + #define DDRDATA8CH1_CR_TXPERBITRANK2_Lane2_OFF ( 8) + #define DDRDATA8CH1_CR_TXPERBITRANK2_Lane2_WID ( 4) + #define DDRDATA8CH1_CR_TXPERBITRANK2_Lane2_MSK (0x00000F00) + #define DDRDATA8CH1_CR_TXPERBITRANK2_Lane2_MAX (0x0000000F) + #define DDRDATA8CH1_CR_TXPERBITRANK2_Lane3_OFF (12) + #define DDRDATA8CH1_CR_TXPERBITRANK2_Lane3_WID ( 4) + #define DDRDATA8CH1_CR_TXPERBITRANK2_Lane3_MSK (0x0000F000) + #define DDRDATA8CH1_CR_TXPERBITRANK2_Lane3_MAX (0x0000000F) + #define DDRDATA8CH1_CR_TXPERBITRANK2_Lane4_OFF (16) + #define DDRDATA8CH1_CR_TXPERBITRANK2_Lane4_WID ( 4) + #define DDRDATA8CH1_CR_TXPERBITRANK2_Lane4_MSK (0x000F0000) + #define DDRDATA8CH1_CR_TXPERBITRANK2_Lane4_MAX (0x0000000F) + #define DDRDATA8CH1_CR_TXPERBITRANK2_Lane5_OFF (20) + #define DDRDATA8CH1_CR_TXPERBITRANK2_Lane5_WID ( 4) + #define DDRDATA8CH1_CR_TXPERBITRANK2_Lane5_MSK (0x00F00000) + #define DDRDATA8CH1_CR_TXPERBITRANK2_Lane5_MAX (0x0000000F) + #define DDRDATA8CH1_CR_TXPERBITRANK2_Lane6_OFF (24) + #define DDRDATA8CH1_CR_TXPERBITRANK2_Lane6_WID ( 4) + #define DDRDATA8CH1_CR_TXPERBITRANK2_Lane6_MSK (0x0F000000) + #define DDRDATA8CH1_CR_TXPERBITRANK2_Lane6_MAX (0x0000000F) + #define DDRDATA8CH1_CR_TXPERBITRANK2_Lane7_OFF (28) + #define DDRDATA8CH1_CR_TXPERBITRANK2_Lane7_WID ( 4) + #define DDRDATA8CH1_CR_TXPERBITRANK2_Lane7_MSK (0xF0000000) + #define DDRDATA8CH1_CR_TXPERBITRANK2_Lane7_MAX (0x0000000F) + +#define DDRDATA8CH1_CR_TXPERBITRANK3_REG (0x0000113C) + #define DDRDATA8CH1_CR_TXPERBITRANK3_Lane0_OFF ( 0) + #define DDRDATA8CH1_CR_TXPERBITRANK3_Lane0_WID ( 4) + #define DDRDATA8CH1_CR_TXPERBITRANK3_Lane0_MSK (0x0000000F) + #define DDRDATA8CH1_CR_TXPERBITRANK3_Lane0_MAX (0x0000000F) + #define DDRDATA8CH1_CR_TXPERBITRANK3_Lane1_OFF ( 4) + #define DDRDATA8CH1_CR_TXPERBITRANK3_Lane1_WID ( 4) + #define DDRDATA8CH1_CR_TXPERBITRANK3_Lane1_MSK (0x000000F0) + #define DDRDATA8CH1_CR_TXPERBITRANK3_Lane1_MAX (0x0000000F) + #define DDRDATA8CH1_CR_TXPERBITRANK3_Lane2_OFF ( 8) + #define DDRDATA8CH1_CR_TXPERBITRANK3_Lane2_WID ( 4) + #define DDRDATA8CH1_CR_TXPERBITRANK3_Lane2_MSK (0x00000F00) + #define DDRDATA8CH1_CR_TXPERBITRANK3_Lane2_MAX (0x0000000F) + #define DDRDATA8CH1_CR_TXPERBITRANK3_Lane3_OFF (12) + #define DDRDATA8CH1_CR_TXPERBITRANK3_Lane3_WID ( 4) + #define DDRDATA8CH1_CR_TXPERBITRANK3_Lane3_MSK (0x0000F000) + #define DDRDATA8CH1_CR_TXPERBITRANK3_Lane3_MAX (0x0000000F) + #define DDRDATA8CH1_CR_TXPERBITRANK3_Lane4_OFF (16) + #define DDRDATA8CH1_CR_TXPERBITRANK3_Lane4_WID ( 4) + #define DDRDATA8CH1_CR_TXPERBITRANK3_Lane4_MSK (0x000F0000) + #define DDRDATA8CH1_CR_TXPERBITRANK3_Lane4_MAX (0x0000000F) + #define DDRDATA8CH1_CR_TXPERBITRANK3_Lane5_OFF (20) + #define DDRDATA8CH1_CR_TXPERBITRANK3_Lane5_WID ( 4) + #define DDRDATA8CH1_CR_TXPERBITRANK3_Lane5_MSK (0x00F00000) + #define DDRDATA8CH1_CR_TXPERBITRANK3_Lane5_MAX (0x0000000F) + #define DDRDATA8CH1_CR_TXPERBITRANK3_Lane6_OFF (24) + #define DDRDATA8CH1_CR_TXPERBITRANK3_Lane6_WID ( 4) + #define DDRDATA8CH1_CR_TXPERBITRANK3_Lane6_MSK (0x0F000000) + #define DDRDATA8CH1_CR_TXPERBITRANK3_Lane6_MAX (0x0000000F) + #define DDRDATA8CH1_CR_TXPERBITRANK3_Lane7_OFF (28) + #define DDRDATA8CH1_CR_TXPERBITRANK3_Lane7_WID ( 4) + #define DDRDATA8CH1_CR_TXPERBITRANK3_Lane7_MSK (0xF0000000) + #define DDRDATA8CH1_CR_TXPERBITRANK3_Lane7_MAX (0x0000000F) + +#define DDRDATA8CH1_CR_RCOMPDATA0_REG (0x00001140) + #define DDRDATA8CH1_CR_RCOMPDATA0_RcompDrvUp_OFF ( 0) + #define DDRDATA8CH1_CR_RCOMPDATA0_RcompDrvUp_WID ( 6) + #define DDRDATA8CH1_CR_RCOMPDATA0_RcompDrvUp_MSK (0x0000003F) + #define DDRDATA8CH1_CR_RCOMPDATA0_RcompDrvUp_MAX (0x0000003F) + #define DDRDATA8CH1_CR_RCOMPDATA0_Spare0_OFF ( 6) + #define DDRDATA8CH1_CR_RCOMPDATA0_Spare0_WID ( 3) + #define DDRDATA8CH1_CR_RCOMPDATA0_Spare0_MSK (0x000001C0) + #define DDRDATA8CH1_CR_RCOMPDATA0_Spare0_MAX (0x00000007) + #define DDRDATA8CH1_CR_RCOMPDATA0_RcompDrvDown_OFF ( 9) + #define DDRDATA8CH1_CR_RCOMPDATA0_RcompDrvDown_WID ( 6) + #define DDRDATA8CH1_CR_RCOMPDATA0_RcompDrvDown_MSK (0x00007E00) + #define DDRDATA8CH1_CR_RCOMPDATA0_RcompDrvDown_MAX (0x0000003F) + #define DDRDATA8CH1_CR_RCOMPDATA0_VTComp_OFF (15) + #define DDRDATA8CH1_CR_RCOMPDATA0_VTComp_WID ( 5) + #define DDRDATA8CH1_CR_RCOMPDATA0_VTComp_MSK (0x000F8000) + #define DDRDATA8CH1_CR_RCOMPDATA0_VTComp_MAX (0x0000001F) + #define DDRDATA8CH1_CR_RCOMPDATA0_TcoComp_OFF (20) + #define DDRDATA8CH1_CR_RCOMPDATA0_TcoComp_WID ( 6) + #define DDRDATA8CH1_CR_RCOMPDATA0_TcoComp_MSK (0x03F00000) + #define DDRDATA8CH1_CR_RCOMPDATA0_TcoComp_MAX (0x0000003F) + #define DDRDATA8CH1_CR_RCOMPDATA0_SlewRateComp_OFF (26) + #define DDRDATA8CH1_CR_RCOMPDATA0_SlewRateComp_WID ( 5) + #define DDRDATA8CH1_CR_RCOMPDATA0_SlewRateComp_MSK (0x7C000000) + #define DDRDATA8CH1_CR_RCOMPDATA0_SlewRateComp_MAX (0x0000001F) + #define DDRDATA8CH1_CR_RCOMPDATA0_Spare2_OFF (31) + #define DDRDATA8CH1_CR_RCOMPDATA0_Spare2_WID ( 1) + #define DDRDATA8CH1_CR_RCOMPDATA0_Spare2_MSK (0x80000000) + #define DDRDATA8CH1_CR_RCOMPDATA0_Spare2_MAX (0x00000001) + +#define DDRDATA8CH1_CR_RCOMPDATA1_REG (0x00001144) + #define DDRDATA8CH1_CR_RCOMPDATA1_RcompOdtUp_OFF ( 0) + #define DDRDATA8CH1_CR_RCOMPDATA1_RcompOdtUp_WID ( 6) + #define DDRDATA8CH1_CR_RCOMPDATA1_RcompOdtUp_MSK (0x0000003F) + #define DDRDATA8CH1_CR_RCOMPDATA1_RcompOdtUp_MAX (0x0000003F) + #define DDRDATA8CH1_CR_RCOMPDATA1_Spare0_OFF ( 6) + #define DDRDATA8CH1_CR_RCOMPDATA1_Spare0_WID ( 3) + #define DDRDATA8CH1_CR_RCOMPDATA1_Spare0_MSK (0x000001C0) + #define DDRDATA8CH1_CR_RCOMPDATA1_Spare0_MAX (0x00000007) + #define DDRDATA8CH1_CR_RCOMPDATA1_RcompOdtDown_OFF ( 9) + #define DDRDATA8CH1_CR_RCOMPDATA1_RcompOdtDown_WID ( 6) + #define DDRDATA8CH1_CR_RCOMPDATA1_RcompOdtDown_MSK (0x00007E00) + #define DDRDATA8CH1_CR_RCOMPDATA1_RcompOdtDown_MAX (0x0000003F) + #define DDRDATA8CH1_CR_RCOMPDATA1_Spare1_OFF (15) + #define DDRDATA8CH1_CR_RCOMPDATA1_Spare1_WID ( 1) + #define DDRDATA8CH1_CR_RCOMPDATA1_Spare1_MSK (0x00008000) + #define DDRDATA8CH1_CR_RCOMPDATA1_Spare1_MAX (0x00000001) + #define DDRDATA8CH1_CR_RCOMPDATA1_PanicDrvDn_OFF (16) + #define DDRDATA8CH1_CR_RCOMPDATA1_PanicDrvDn_WID ( 6) + #define DDRDATA8CH1_CR_RCOMPDATA1_PanicDrvDn_MSK (0x003F0000) + #define DDRDATA8CH1_CR_RCOMPDATA1_PanicDrvDn_MAX (0x0000003F) + #define DDRDATA8CH1_CR_RCOMPDATA1_PanicDrvUp_OFF (22) + #define DDRDATA8CH1_CR_RCOMPDATA1_PanicDrvUp_WID ( 6) + #define DDRDATA8CH1_CR_RCOMPDATA1_PanicDrvUp_MSK (0x0FC00000) + #define DDRDATA8CH1_CR_RCOMPDATA1_PanicDrvUp_MAX (0x0000003F) + #define DDRDATA8CH1_CR_RCOMPDATA1_LevelShifterComp_OFF (28) + #define DDRDATA8CH1_CR_RCOMPDATA1_LevelShifterComp_WID ( 3) + #define DDRDATA8CH1_CR_RCOMPDATA1_LevelShifterComp_MSK (0x70000000) + #define DDRDATA8CH1_CR_RCOMPDATA1_LevelShifterComp_MAX (0x00000007) + #define DDRDATA8CH1_CR_RCOMPDATA1_Spare2_OFF (31) + #define DDRDATA8CH1_CR_RCOMPDATA1_Spare2_WID ( 1) + #define DDRDATA8CH1_CR_RCOMPDATA1_Spare2_MSK (0x80000000) + #define DDRDATA8CH1_CR_RCOMPDATA1_Spare2_MAX (0x00000001) + +#define DDRDATA8CH1_CR_TXXTALK_REG (0x00001148) + #define DDRDATA8CH1_CR_TXXTALK_Lane0_OFF ( 0) + #define DDRDATA8CH1_CR_TXXTALK_Lane0_WID ( 4) + #define DDRDATA8CH1_CR_TXXTALK_Lane0_MSK (0x0000000F) + #define DDRDATA8CH1_CR_TXXTALK_Lane0_MAX (0x0000000F) + #define DDRDATA8CH1_CR_TXXTALK_Lane1_OFF ( 4) + #define DDRDATA8CH1_CR_TXXTALK_Lane1_WID ( 4) + #define DDRDATA8CH1_CR_TXXTALK_Lane1_MSK (0x000000F0) + #define DDRDATA8CH1_CR_TXXTALK_Lane1_MAX (0x0000000F) + #define DDRDATA8CH1_CR_TXXTALK_Lane2_OFF ( 8) + #define DDRDATA8CH1_CR_TXXTALK_Lane2_WID ( 4) + #define DDRDATA8CH1_CR_TXXTALK_Lane2_MSK (0x00000F00) + #define DDRDATA8CH1_CR_TXXTALK_Lane2_MAX (0x0000000F) + #define DDRDATA8CH1_CR_TXXTALK_Lane3_OFF (12) + #define DDRDATA8CH1_CR_TXXTALK_Lane3_WID ( 4) + #define DDRDATA8CH1_CR_TXXTALK_Lane3_MSK (0x0000F000) + #define DDRDATA8CH1_CR_TXXTALK_Lane3_MAX (0x0000000F) + #define DDRDATA8CH1_CR_TXXTALK_Lane4_OFF (16) + #define DDRDATA8CH1_CR_TXXTALK_Lane4_WID ( 4) + #define DDRDATA8CH1_CR_TXXTALK_Lane4_MSK (0x000F0000) + #define DDRDATA8CH1_CR_TXXTALK_Lane4_MAX (0x0000000F) + #define DDRDATA8CH1_CR_TXXTALK_Lane5_OFF (20) + #define DDRDATA8CH1_CR_TXXTALK_Lane5_WID ( 4) + #define DDRDATA8CH1_CR_TXXTALK_Lane5_MSK (0x00F00000) + #define DDRDATA8CH1_CR_TXXTALK_Lane5_MAX (0x0000000F) + #define DDRDATA8CH1_CR_TXXTALK_Lane6_OFF (24) + #define DDRDATA8CH1_CR_TXXTALK_Lane6_WID ( 4) + #define DDRDATA8CH1_CR_TXXTALK_Lane6_MSK (0x0F000000) + #define DDRDATA8CH1_CR_TXXTALK_Lane6_MAX (0x0000000F) + #define DDRDATA8CH1_CR_TXXTALK_Lane7_OFF (28) + #define DDRDATA8CH1_CR_TXXTALK_Lane7_WID ( 4) + #define DDRDATA8CH1_CR_TXXTALK_Lane7_MSK (0xF0000000) + #define DDRDATA8CH1_CR_TXXTALK_Lane7_MAX (0x0000000F) + +#define DDRDATA8CH1_CR_RXOFFSETVDQ_REG (0x0000114C) + #define DDRDATA8CH1_CR_RXOFFSETVDQ_Lane0_OFF ( 0) + #define DDRDATA8CH1_CR_RXOFFSETVDQ_Lane0_WID ( 4) + #define DDRDATA8CH1_CR_RXOFFSETVDQ_Lane0_MSK (0x0000000F) + #define DDRDATA8CH1_CR_RXOFFSETVDQ_Lane0_MAX (0x0000000F) + #define DDRDATA8CH1_CR_RXOFFSETVDQ_Lane1_OFF ( 4) + #define DDRDATA8CH1_CR_RXOFFSETVDQ_Lane1_WID ( 4) + #define DDRDATA8CH1_CR_RXOFFSETVDQ_Lane1_MSK (0x000000F0) + #define DDRDATA8CH1_CR_RXOFFSETVDQ_Lane1_MAX (0x0000000F) + #define DDRDATA8CH1_CR_RXOFFSETVDQ_Lane2_OFF ( 8) + #define DDRDATA8CH1_CR_RXOFFSETVDQ_Lane2_WID ( 4) + #define DDRDATA8CH1_CR_RXOFFSETVDQ_Lane2_MSK (0x00000F00) + #define DDRDATA8CH1_CR_RXOFFSETVDQ_Lane2_MAX (0x0000000F) + #define DDRDATA8CH1_CR_RXOFFSETVDQ_Lane3_OFF (12) + #define DDRDATA8CH1_CR_RXOFFSETVDQ_Lane3_WID ( 4) + #define DDRDATA8CH1_CR_RXOFFSETVDQ_Lane3_MSK (0x0000F000) + #define DDRDATA8CH1_CR_RXOFFSETVDQ_Lane3_MAX (0x0000000F) + #define DDRDATA8CH1_CR_RXOFFSETVDQ_Lane4_OFF (16) + #define DDRDATA8CH1_CR_RXOFFSETVDQ_Lane4_WID ( 4) + #define DDRDATA8CH1_CR_RXOFFSETVDQ_Lane4_MSK (0x000F0000) + #define DDRDATA8CH1_CR_RXOFFSETVDQ_Lane4_MAX (0x0000000F) + #define DDRDATA8CH1_CR_RXOFFSETVDQ_Lane5_OFF (20) + #define DDRDATA8CH1_CR_RXOFFSETVDQ_Lane5_WID ( 4) + #define DDRDATA8CH1_CR_RXOFFSETVDQ_Lane5_MSK (0x00F00000) + #define DDRDATA8CH1_CR_RXOFFSETVDQ_Lane5_MAX (0x0000000F) + #define DDRDATA8CH1_CR_RXOFFSETVDQ_Lane6_OFF (24) + #define DDRDATA8CH1_CR_RXOFFSETVDQ_Lane6_WID ( 4) + #define DDRDATA8CH1_CR_RXOFFSETVDQ_Lane6_MSK (0x0F000000) + #define DDRDATA8CH1_CR_RXOFFSETVDQ_Lane6_MAX (0x0000000F) + #define DDRDATA8CH1_CR_RXOFFSETVDQ_Lane7_OFF (28) + #define DDRDATA8CH1_CR_RXOFFSETVDQ_Lane7_WID ( 4) + #define DDRDATA8CH1_CR_RXOFFSETVDQ_Lane7_MSK (0xF0000000) + #define DDRDATA8CH1_CR_RXOFFSETVDQ_Lane7_MAX (0x0000000F) + +#define DDRDATA8CH1_CR_DDRDATARESERVED_REG (0x00001150) + #define DDRDATA8CH1_CR_DDRDATARESERVED_Spare_OFF ( 0) + #define DDRDATA8CH1_CR_DDRDATARESERVED_Spare_WID (32) + #define DDRDATA8CH1_CR_DDRDATARESERVED_Spare_MSK (0xFFFFFFFF) + #define DDRDATA8CH1_CR_DDRDATARESERVED_Spare_MAX (0xFFFFFFFF) + +#define DDRDATA8CH1_CR_DATATRAINFEEDBACK_REG (0x00001154) + #define DDRDATA8CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_OFF ( 0) + #define DDRDATA8CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_WID ( 9) + #define DDRDATA8CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_MSK (0x000001FF) + #define DDRDATA8CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_MAX (0x000001FF) + #define DDRDATA8CH1_CR_DATATRAINFEEDBACK_Spare_OFF ( 9) + #define DDRDATA8CH1_CR_DATATRAINFEEDBACK_Spare_WID (23) + #define DDRDATA8CH1_CR_DATATRAINFEEDBACK_Spare_MSK (0xFFFFFE00) + #define DDRDATA8CH1_CR_DATATRAINFEEDBACK_Spare_MAX (0x007FFFFF) + +#define DDRDATA8CH1_CR_DLLPITESTANDADC_REG (0x00001158) + #define DDRDATA8CH1_CR_DLLPITESTANDADC_RunTest_OFF ( 0) + #define DDRDATA8CH1_CR_DLLPITESTANDADC_RunTest_WID ( 1) + #define DDRDATA8CH1_CR_DLLPITESTANDADC_RunTest_MSK (0x00000001) + #define DDRDATA8CH1_CR_DLLPITESTANDADC_RunTest_MAX (0x00000001) + #define DDRDATA8CH1_CR_DLLPITESTANDADC_RunTest_DEF (0x00000000) + #define DDRDATA8CH1_CR_DLLPITESTANDADC_Load_OFF ( 1) + #define DDRDATA8CH1_CR_DLLPITESTANDADC_Load_WID ( 1) + #define DDRDATA8CH1_CR_DLLPITESTANDADC_Load_MSK (0x00000002) + #define DDRDATA8CH1_CR_DLLPITESTANDADC_Load_MAX (0x00000001) + #define DDRDATA8CH1_CR_DLLPITESTANDADC_Load_DEF (0x00000000) + #define DDRDATA8CH1_CR_DLLPITESTANDADC_ModeHVM_OFF ( 2) + #define DDRDATA8CH1_CR_DLLPITESTANDADC_ModeHVM_WID ( 1) + #define DDRDATA8CH1_CR_DLLPITESTANDADC_ModeHVM_MSK (0x00000004) + #define DDRDATA8CH1_CR_DLLPITESTANDADC_ModeHVM_MAX (0x00000001) + #define DDRDATA8CH1_CR_DLLPITESTANDADC_ModeHVM_DEF (0x00000000) + #define DDRDATA8CH1_CR_DLLPITESTANDADC_ModeDV_OFF ( 3) + #define DDRDATA8CH1_CR_DLLPITESTANDADC_ModeDV_WID ( 1) + #define DDRDATA8CH1_CR_DLLPITESTANDADC_ModeDV_MSK (0x00000008) + #define DDRDATA8CH1_CR_DLLPITESTANDADC_ModeDV_MAX (0x00000001) + #define DDRDATA8CH1_CR_DLLPITESTANDADC_ModeDV_DEF (0x00000000) + #define DDRDATA8CH1_CR_DLLPITESTANDADC_ModeADC_OFF ( 4) + #define DDRDATA8CH1_CR_DLLPITESTANDADC_ModeADC_WID ( 1) + #define DDRDATA8CH1_CR_DLLPITESTANDADC_ModeADC_MSK (0x00000010) + #define DDRDATA8CH1_CR_DLLPITESTANDADC_ModeADC_MAX (0x00000001) + #define DDRDATA8CH1_CR_DLLPITESTANDADC_ModeADC_DEF (0x00000000) + #define DDRDATA8CH1_CR_DLLPITESTANDADC_LoadCount_OFF ( 5) + #define DDRDATA8CH1_CR_DLLPITESTANDADC_LoadCount_WID (10) + #define DDRDATA8CH1_CR_DLLPITESTANDADC_LoadCount_MSK (0x00007FE0) + #define DDRDATA8CH1_CR_DLLPITESTANDADC_LoadCount_MAX (0x000003FF) + #define DDRDATA8CH1_CR_DLLPITESTANDADC_CountStatus_OFF (15) + #define DDRDATA8CH1_CR_DLLPITESTANDADC_CountStatus_WID (10) + #define DDRDATA8CH1_CR_DLLPITESTANDADC_CountStatus_MSK (0x01FF8000) + #define DDRDATA8CH1_CR_DLLPITESTANDADC_CountStatus_MAX (0x000003FF) + #define DDRDATA8CH1_CR_DLLPITESTANDADC_CountStatus_DEF (0x00000000) + #define DDRDATA8CH1_CR_DLLPITESTANDADC_Spare_OFF (25) + #define DDRDATA8CH1_CR_DLLPITESTANDADC_Spare_WID ( 7) + #define DDRDATA8CH1_CR_DLLPITESTANDADC_Spare_MSK (0xFE000000) + #define DDRDATA8CH1_CR_DLLPITESTANDADC_Spare_MAX (0x0000007F) + +#define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_REG (0x0000115C) + #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_OFF ( 0) + #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_WID ( 6) + #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MSK (0x0000003F) + #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MAX (0x0000003F) + #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_DEF (0x00000000) + #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_OFF ( 6) + #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_WID ( 6) + #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MSK (0x00000FC0) + #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MAX (0x0000003F) + #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_DEF (0x00000000) + #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_OFF (12) + #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_WID ( 5) + #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MSK (0x0001F000) + #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MAX (0x0000001F) + #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_DEF (0x00000000) + #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_OFF (17) + #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_WID ( 5) + #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MSK (0x003E0000) + #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MAX (0x0000001F) + #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_DEF (0x00000000) + #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_OFF (22) + #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_WID ( 5) + #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_MSK (0x07C00000) + #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_MAX (0x0000001F) + #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_DEF (0x00000000) + #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_OFF (27) + #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_WID ( 5) + #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MSK (0xF8000000) + #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MAX (0x0000001F) + #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_DEF (0x00000000) + +#define DDRDATA8CH1_CR_DDRCRDATACONTROL1_REG (0x00001160) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_RefPi_OFF ( 0) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_RefPi_WID ( 4) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_RefPi_MSK (0x0000000F) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_RefPi_MAX (0x0000000F) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_RefPi_DEF (0x00000000) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_DllMask_OFF ( 4) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_DllMask_WID ( 2) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_DllMask_MSK (0x00000030) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_DllMask_MAX (0x00000003) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_DllMask_DEF (0x00000000) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_DllWeakLock_OFF ( 6) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_DllWeakLock_WID ( 1) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_DllWeakLock_MSK (0x00000040) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_DllWeakLock_MAX (0x00000001) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_DllWeakLock_DEF (0x00000000) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_OFF ( 7) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_WID ( 3) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MSK (0x00000380) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MAX (0x00000007) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_DEF (0x00000000) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_OFF (10) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_WID ( 3) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_MSK (0x00001C00) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_MAX (0x00000007) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_DEF (0x00000000) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_OdtDelay_OFF (13) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_OdtDelay_WID ( 4) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_OdtDelay_MSK (0x0001E000) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_OdtDelay_MAX (0x0000000F) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_OdtDelay_DEF (0x00000000) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_OdtDuration_OFF (17) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_OdtDuration_WID ( 3) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_OdtDuration_MSK (0x000E0000) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_OdtDuration_MAX (0x00000007) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_OdtDuration_DEF (0x00000000) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_OFF (20) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_WID ( 4) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_MSK (0x00F00000) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_MAX (0x0000000F) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_DEF (0x00000000) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_OFF (24) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_WID ( 3) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_MSK (0x07000000) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_MAX (0x00000007) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_DEF (0x00000000) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_OFF (27) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_WID ( 3) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_MSK (0x38000000) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_MAX (0x00000007) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_DEF (0x00000000) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_OFF (30) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_WID ( 1) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_MSK (0x40000000) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_MAX (0x00000001) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_DEF (0x00000000) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_Rsvd1_OFF (31) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_Rsvd1_WID ( 1) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_Rsvd1_MSK (0x80000000) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_Rsvd1_MAX (0x00000001) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_Rsvd1_DEF (0x00000000) + +#define DDRDATA8CH1_CR_DDRCRDATACONTROL2_REG (0x00001164) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_OFF ( 0) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_WID ( 5) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_MSK (0x0000001F) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_MAX (0x0000001F) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_DEF (0x00000000) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_OFF ( 5) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_WID ( 1) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_MSK (0x00000020) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_MAX (0x00000001) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_DEF (0x00000000) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_ForceRxOn_OFF ( 6) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_ForceRxOn_WID ( 1) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_ForceRxOn_MSK (0x00000040) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_ForceRxOn_MAX (0x00000001) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_ForceRxOn_DEF (0x00000000) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_LeakerComp_OFF ( 7) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_LeakerComp_WID ( 2) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_LeakerComp_MSK (0x00000180) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_LeakerComp_MAX (0x00000003) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_LeakerComp_DEF (0x00000000) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_OFF ( 9) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_WID ( 4) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_MSK (0x00001E00) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_MAX (0x0000000F) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_DEF (0x00000008) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_OFF (13) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_WID ( 5) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_MSK (0x0003E000) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_MAX (0x0000001F) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_DEF (0x00000011) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_OFF (18) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_WID ( 1) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_MSK (0x00040000) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_MAX (0x00000001) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_DEF (0x00000000) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_Spare_OFF (19) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_Spare_WID (13) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_Spare_MSK (0xFFF80000) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_Spare_MAX (0x00001FFF) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_Spare_DEF (0x00000000) + +#define DDRDATA8CH1_CR_DDRCRVSSHIORVREFCONTROL_REG (0x0000116C) + #define DDRDATA8CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_OFF ( 0) + #define DDRDATA8CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_WID (24) + #define DDRDATA8CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_MSK (0x00FFFFFF) + #define DDRDATA8CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_MAX (0x00FFFFFF) + #define DDRDATA8CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_DEF (0x00000000) + #define DDRDATA8CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_OFF (24) + #define DDRDATA8CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_WID ( 8) + #define DDRDATA8CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_MSK (0xFF000000) + #define DDRDATA8CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_MAX (0x000000FF) + #define DDRDATA8CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_DEF (0x00000000) + +#define DDRDATA8CH1_CR_DDRCRDATAOFFSETTRAIN_REG (0x00001170) + #define DDRDATA8CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_OFF ( 0) + #define DDRDATA8CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_WID ( 6) + #define DDRDATA8CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MSK (0x0000003F) + #define DDRDATA8CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MAX (0x0000003F) + #define DDRDATA8CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_DEF (0x00000000) + #define DDRDATA8CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_OFF ( 6) + #define DDRDATA8CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_WID ( 6) + #define DDRDATA8CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MSK (0x00000FC0) + #define DDRDATA8CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MAX (0x0000003F) + #define DDRDATA8CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_DEF (0x00000000) + #define DDRDATA8CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_OFF (12) + #define DDRDATA8CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_WID ( 6) + #define DDRDATA8CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MSK (0x0003F000) + #define DDRDATA8CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MAX (0x0000003F) + #define DDRDATA8CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_DEF (0x00000000) + #define DDRDATA8CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_OFF (18) + #define DDRDATA8CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_WID ( 6) + #define DDRDATA8CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MSK (0x00FC0000) + #define DDRDATA8CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MAX (0x0000003F) + #define DDRDATA8CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_DEF (0x00000000) + #define DDRDATA8CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_OFF (24) + #define DDRDATA8CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_WID ( 7) + #define DDRDATA8CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MSK (0x7F000000) + #define DDRDATA8CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MAX (0x0000007F) + #define DDRDATA8CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_DEF (0x00000000) + #define DDRDATA8CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_OFF (31) + #define DDRDATA8CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_WID ( 1) + #define DDRDATA8CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_MSK (0x80000000) + #define DDRDATA8CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_MAX (0x00000001) + #define DDRDATA8CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_DEF (0x00000000) + +#define DDRDATA8CH1_CR_DDRCRDATACONTROL0_REG (0x00001174) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_OFF ( 0) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_WID ( 1) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_MSK (0x00000001) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_MAX (0x00000001) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_DEF (0x00000000) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_OFF ( 1) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_WID ( 1) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_MSK (0x00000002) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_MAX (0x00000001) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_DEF (0x00000000) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_OFF ( 2) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_WID ( 1) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_MSK (0x00000004) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_MAX (0x00000001) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_DEF (0x00000000) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_OFF ( 3) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_WID ( 1) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MSK (0x00000008) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MAX (0x00000001) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_DEF (0x00000000) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_TxOn_OFF ( 4) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_TxOn_WID ( 1) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_TxOn_MSK (0x00000010) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_TxOn_MAX (0x00000001) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_TxOn_DEF (0x00000000) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RfOn_OFF ( 5) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RfOn_WID ( 1) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RfOn_MSK (0x00000020) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RfOn_MAX (0x00000001) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RfOn_DEF (0x00000000) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RxPiOn_OFF ( 6) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RxPiOn_WID ( 1) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RxPiOn_MSK (0x00000040) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RxPiOn_MAX (0x00000001) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RxPiOn_DEF (0x00000000) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_TxPiOn_OFF ( 7) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_TxPiOn_WID ( 1) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_TxPiOn_MSK (0x00000080) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_TxPiOn_MAX (0x00000001) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_TxPiOn_DEF (0x00000000) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_OFF ( 8) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_WID ( 1) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_MSK (0x00000100) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_MAX (0x00000001) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_DEF (0x00000000) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_OFF ( 9) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_WID ( 1) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MSK (0x00000200) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MAX (0x00000001) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_DEF (0x00000000) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_TxDisable_OFF (10) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_TxDisable_WID ( 1) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_TxDisable_MSK (0x00000400) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_TxDisable_MAX (0x00000001) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_TxDisable_DEF (0x00000000) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RxDisable_OFF (11) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RxDisable_WID ( 1) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RxDisable_MSK (0x00000800) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RxDisable_MAX (0x00000001) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RxDisable_DEF (0x00000000) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_TxLong_OFF (12) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_TxLong_WID ( 1) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_TxLong_MSK (0x00001000) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_TxLong_MAX (0x00000001) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_TxLong_DEF (0x00000000) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_OFF (13) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_WID ( 2) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_MSK (0x00006000) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_MAX (0x00000003) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_DEF (0x00000000) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RxReadPointer_OFF (15) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RxReadPointer_WID ( 3) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RxReadPointer_MSK (0x00038000) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RxReadPointer_MAX (0x00000007) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RxReadPointer_DEF (0x00000000) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_OFF (18) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_WID ( 1) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_MSK (0x00040000) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_MAX (0x00000001) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_DEF (0x00000000) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_OFF (19) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_WID ( 1) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_MSK (0x00080000) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_MAX (0x00000001) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_DEF (0x00000000) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_ReadRFRd_OFF (20) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_ReadRFRd_WID ( 1) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_ReadRFRd_MSK (0x00100000) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_ReadRFRd_MAX (0x00000001) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_ReadRFRd_DEF (0x00000000) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_ReadRFWr_OFF (21) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_ReadRFWr_WID ( 1) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_ReadRFWr_MSK (0x00200000) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_ReadRFWr_MAX (0x00000001) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_ReadRFWr_DEF (0x00000000) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_ReadRFRank_OFF (22) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_ReadRFRank_WID ( 2) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_ReadRFRank_MSK (0x00C00000) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_ReadRFRank_MAX (0x00000003) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_ReadRFRank_DEF (0x00000000) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_OFF (24) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_WID ( 1) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_MSK (0x01000000) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_MAX (0x00000001) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_DEF (0x00000000) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_OdtSampOff_OFF (25) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_OdtSampOff_WID ( 1) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_OdtSampOff_MSK (0x02000000) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_OdtSampOff_MAX (0x00000001) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_OdtSampOff_DEF (0x00000000) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_OFF (26) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_WID ( 1) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_MSK (0x04000000) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_MAX (0x00000001) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_DEF (0x00000000) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_OFF (27) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_WID ( 1) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MSK (0x08000000) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MAX (0x00000001) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_DEF (0x00000000) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_OFF (28) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_WID ( 1) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_MSK (0x10000000) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_MAX (0x00000001) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_DEF (0x00000000) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_OFF (29) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_WID ( 1) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_MSK (0x20000000) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_MAX (0x00000001) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_DEF (0x00000000) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_OFF (30) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_WID ( 1) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MSK (0x40000000) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MAX (0x00000001) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_DEF (0x00000000) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_OFF (31) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_WID ( 1) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_MSK (0x80000000) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_MAX (0x00000001) + #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_DEF (0x00000000) + +#define DDRDATA8CH1_CR_DDRCRVREFADJUST1_REG (0x00001178) + #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_OFF ( 0) + #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_WID ( 7) + #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_MSK (0x0000007F) + #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_MAX (0x0000007F) + #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_DEF (0x00000000) + #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_OFF ( 7) + #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_WID ( 7) + #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_MSK (0x00003F80) + #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_MAX (0x0000007F) + #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_DEF (0x00000000) + #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_OFF (14) + #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_WID ( 7) + #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_MSK (0x001FC000) + #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_MAX (0x0000007F) + #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_DEF (0x00000000) + #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_OFF (21) + #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_WID ( 1) + #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_MSK (0x00200000) + #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_MAX (0x00000001) + #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_DEF (0x00000000) + #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_OFF (22) + #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_WID ( 1) + #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_MSK (0x00400000) + #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_MAX (0x00000001) + #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_DEF (0x00000000) + #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_OFF (23) + #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_WID ( 1) + #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_MSK (0x00800000) + #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_MAX (0x00000001) + #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_DEF (0x00000000) + #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_OFF (24) + #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_WID ( 2) + #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_MSK (0x03000000) + #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_MAX (0x00000003) + #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_DEF (0x00000000) + #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_OFF (26) + #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_WID ( 1) + #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_MSK (0x04000000) + #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_MAX (0x00000001) + #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_DEF (0x00000000) + #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_Rsvd_OFF (27) + #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_Rsvd_WID ( 2) + #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_Rsvd_MSK (0x18000000) + #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_Rsvd_MAX (0x00000003) + #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_Rsvd_DEF (0x00000000) + #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_caSlowBW_OFF (29) + #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_caSlowBW_WID ( 1) + #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_caSlowBW_MSK (0x20000000) + #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_caSlowBW_MAX (0x00000001) + #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_caSlowBW_DEF (0x00000000) + #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_OFF (30) + #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_WID ( 1) + #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_MSK (0x40000000) + #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_MAX (0x00000001) + #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_DEF (0x00000000) + #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_OFF (31) + #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_WID ( 1) + #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_MSK (0x80000000) + #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_MAX (0x00000001) + #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_DEF (0x00000000) + +#pragma pack(pop) +#endif // __McIoData_h__ diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcRegisters/McMain.h b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcRegisters/McMain.h new file mode 100644 index 0000000..fa1db62 --- /dev/null +++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcRegisters/McMain.h @@ -0,0 +1,19761 @@ +/** @file + This file was automatically generated. Modify at your own risk. + +@copyright + Copyright (c) 2010 - 2012 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +**/ +#ifndef __McMain_h__ +#define __McMain_h__ + +#pragma pack(push, 1) +#include "MrcTypes.h" + +typedef union { + struct { + U32 Global_Start_Test : 1; // Bits 0:0 + U32 Global_Stop_Test : 1; // Bits 1:1 + U32 Global_Clear_Errors : 1; // Bits 2:2 + U32 : 1; // Bits 3:3 + U32 Global_Stop_Test_On_Any_Error : 1; // Bits 4:4 + U32 : 27; // Bits 31:5 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_GLOBAL_CTL_MCMAIN_STRUCT; + +typedef union { + struct { + U32 Channel_Error_Status_0 : 1; // Bits 0:0 + U32 Channel_Error_Status_1 : 1; // Bits 1:1 + U32 : 14; // Bits 15:2 + U32 Channel_Test_Done_Status_0 : 1; // Bits 16:16 + U32 Channel_Test_Done_Status_1 : 1; // Bits 17:17 + U32 : 14; // Bits 31:18 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_GLOBAL_ERR_MCMAIN_STRUCT; + +typedef union { + struct { + U32 Number_of_Cachelines : 7; // Bits 6:0 + U32 Number_of_Cachelines_Scale : 1; // Bits 7:7 + U32 Subsequence_Wait : 10; // Bits 17:8 + U32 : 2; // Bits 19:18 + U32 Subsequence_Type : 4; // Bits 23:20 + U32 : 1; // Bits 24:24 + U32 Save_Current_Base_Address_To_Start : 1; // Bits 25:25 + U32 Reset_Current_Base_Address_To_Start : 1; // Bits 26:26 + U32 Data_and_ECC_Address_Inversion : 2; // Bits 28:27 + U32 : 1; // Bits 29:29 + U32 Invert_Data_and_ECC : 1; // Bits 30:30 + U32 Stop_Base_Subsequence_On_Wrap_Trigger : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_STRUCT_HSW_A0; + +typedef union { + struct { + U32 Number_of_Cachelines : 7; // Bits 6:0 + U32 Number_of_Cachelines_Scale : 1; // Bits 7:7 + U32 Subsequence_Wait : 10; // Bits 17:8 + U32 : 2; // Bits 19:18 + U32 Subsequence_Type : 4; // Bits 23:20 + U32 : 1; // Bits 24:24 + U32 Save_Current_Base_Address_To_Start : 1; // Bits 25:25 + U32 Reset_Current_Base_Address_To_Start : 1; // Bits 26:26 + U32 Data_and_ECC_Address_Inversion : 2; // Bits 28:27 + U32 : 1; // Bits 29:29 + U32 Invert_Data_and_ECC : 1; // Bits 30:30 + U32 Stop_Base_Subsequence_On_Wrap_Trigger : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_STRUCT_HSW_A0; + +typedef union { + struct { + U32 Number_of_Cachelines : 7; // Bits 6:0 + U32 Number_of_Cachelines_Scale : 1; // Bits 7:7 + U32 Subsequence_Wait : 10; // Bits 17:8 + U32 : 2; // Bits 19:18 + U32 Subsequence_Type : 4; // Bits 23:20 + U32 : 1; // Bits 24:24 + U32 Save_Current_Base_Address_To_Start : 1; // Bits 25:25 + U32 Reset_Current_Base_Address_To_Start : 1; // Bits 26:26 + U32 Data_and_ECC_Address_Inversion : 2; // Bits 28:27 + U32 : 1; // Bits 29:29 + U32 Invert_Data_and_ECC : 1; // Bits 30:30 + U32 Stop_Base_Subsequence_On_Wrap_Trigger : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_STRUCT_HSW_A0; + +typedef union { + struct { + U32 Number_of_Cachelines : 7; // Bits 6:0 + U32 Number_of_Cachelines_Scale : 1; // Bits 7:7 + U32 Subsequence_Wait : 10; // Bits 17:8 + U32 : 2; // Bits 19:18 + U32 Subsequence_Type : 4; // Bits 23:20 + U32 : 1; // Bits 24:24 + U32 Save_Current_Base_Address_To_Start : 1; // Bits 25:25 + U32 Reset_Current_Base_Address_To_Start : 1; // Bits 26:26 + U32 Data_and_ECC_Address_Inversion : 2; // Bits 28:27 + U32 : 1; // Bits 29:29 + U32 Invert_Data_and_ECC : 1; // Bits 30:30 + U32 Stop_Base_Subsequence_On_Wrap_Trigger : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_STRUCT_HSW_A0; + +typedef union { + struct { + U32 Number_of_Cachelines : 7; // Bits 6:0 + U32 Number_of_Cachelines_Scale : 1; // Bits 7:7 + U32 Subsequence_Wait : 10; // Bits 17:8 + U32 : 2; // Bits 19:18 + U32 Subsequence_Type : 4; // Bits 23:20 + U32 : 1; // Bits 24:24 + U32 Save_Current_Base_Address_To_Start : 1; // Bits 25:25 + U32 Reset_Current_Base_Address_To_Start : 1; // Bits 26:26 + U32 Data_and_ECC_Address_Inversion : 2; // Bits 28:27 + U32 : 1; // Bits 29:29 + U32 Invert_Data_and_ECC : 1; // Bits 30:30 + U32 Stop_Base_Subsequence_On_Wrap_Trigger : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_STRUCT_HSW_A0; + +typedef union { + struct { + U32 Number_of_Cachelines : 7; // Bits 6:0 + U32 Number_of_Cachelines_Scale : 1; // Bits 7:7 + U32 Subsequence_Wait : 10; // Bits 17:8 + U32 : 2; // Bits 19:18 + U32 Subsequence_Type : 4; // Bits 23:20 + U32 : 1; // Bits 24:24 + U32 Save_Current_Base_Address_To_Start : 1; // Bits 25:25 + U32 Reset_Current_Base_Address_To_Start : 1; // Bits 26:26 + U32 Data_and_ECC_Address_Inversion : 2; // Bits 28:27 + U32 : 1; // Bits 29:29 + U32 Invert_Data_and_ECC : 1; // Bits 30:30 + U32 Stop_Base_Subsequence_On_Wrap_Trigger : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_STRUCT_HSW_A0; + +typedef union { + struct { + U32 Number_of_Cachelines : 7; // Bits 6:0 + U32 Number_of_Cachelines_Scale : 1; // Bits 7:7 + U32 Subsequence_Wait : 10; // Bits 17:8 + U32 : 2; // Bits 19:18 + U32 Subsequence_Type : 4; // Bits 23:20 + U32 : 1; // Bits 24:24 + U32 Save_Current_Base_Address_To_Start : 1; // Bits 25:25 + U32 Reset_Current_Base_Address_To_Start : 1; // Bits 26:26 + U32 Data_and_ECC_Address_Inversion : 2; // Bits 28:27 + U32 : 1; // Bits 29:29 + U32 Invert_Data_and_ECC : 1; // Bits 30:30 + U32 Stop_Base_Subsequence_On_Wrap_Trigger : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_STRUCT_HSW_A0; + +typedef union { + struct { + U32 Number_of_Cachelines : 7; // Bits 6:0 + U32 Number_of_Cachelines_Scale : 1; // Bits 7:7 + U32 Subsequence_Wait : 10; // Bits 17:8 + U32 : 2; // Bits 19:18 + U32 Subsequence_Type : 4; // Bits 23:20 + U32 : 1; // Bits 24:24 + U32 Save_Current_Base_Address_To_Start : 1; // Bits 25:25 + U32 Reset_Current_Base_Address_To_Start : 1; // Bits 26:26 + U32 Data_and_ECC_Address_Inversion : 2; // Bits 28:27 + U32 : 1; // Bits 29:29 + U32 Invert_Data_and_ECC : 1; // Bits 30:30 + U32 Stop_Base_Subsequence_On_Wrap_Trigger : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_STRUCT_HSW_A0; + +typedef union { + struct { + U32 Number_of_Cachelines : 7; // Bits 6:0 + U32 Number_of_Cachelines_Scale : 1; // Bits 7:7 + U32 Subsequence_Wait : 8; // Bits 15:8 + U32 : 4; // Bits 19:16 + U32 Subsequence_Type : 4; // Bits 23:20 + U32 : 1; // Bits 24:24 + U32 Save_Current_Base_Address_To_Start : 1; // Bits 25:25 + U32 Reset_Current_Base_Address_To_Start : 1; // Bits 26:26 + U32 Data_and_ECC_Address_Inversion : 2; // Bits 28:27 + U32 : 1; // Bits 29:29 + U32 Invert_Data_and_ECC : 1; // Bits 30:30 + U32 Stop_Base_Subsequence_On_Wrap_Trigger : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_STRUCT_HSW_A0; + +typedef union { + struct { + U32 Number_of_Cachelines : 7; // Bits 6:0 + U32 Number_of_Cachelines_Scale : 1; // Bits 7:7 + U32 Subsequence_Wait : 8; // Bits 15:8 + U32 : 4; // Bits 19:16 + U32 Subsequence_Type : 4; // Bits 23:20 + U32 : 1; // Bits 24:24 + U32 Save_Current_Base_Address_To_Start : 1; // Bits 25:25 + U32 Reset_Current_Base_Address_To_Start : 1; // Bits 26:26 + U32 Data_and_ECC_Address_Inversion : 2; // Bits 28:27 + U32 : 1; // Bits 29:29 + U32 Invert_Data_and_ECC : 1; // Bits 30:30 + U32 Stop_Base_Subsequence_On_Wrap_Trigger : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_STRUCT_HSW_A0; + +typedef union { + struct { + U32 Number_of_Cachelines : 7; // Bits 6:0 + U32 Number_of_Cachelines_Scale : 1; // Bits 7:7 + U32 Subsequence_Wait : 8; // Bits 15:8 + U32 : 4; // Bits 19:16 + U32 Subsequence_Type : 4; // Bits 23:20 + U32 : 1; // Bits 24:24 + U32 Save_Current_Base_Address_To_Start : 1; // Bits 25:25 + U32 Reset_Current_Base_Address_To_Start : 1; // Bits 26:26 + U32 Data_and_ECC_Address_Inversion : 2; // Bits 28:27 + U32 : 1; // Bits 29:29 + U32 Invert_Data_and_ECC : 1; // Bits 30:30 + U32 Stop_Base_Subsequence_On_Wrap_Trigger : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_STRUCT_HSW_A0; + +typedef union { + struct { + U32 Number_of_Cachelines : 7; // Bits 6:0 + U32 Number_of_Cachelines_Scale : 1; // Bits 7:7 + U32 Subsequence_Wait : 8; // Bits 15:8 + U32 : 4; // Bits 19:16 + U32 Subsequence_Type : 4; // Bits 23:20 + U32 : 1; // Bits 24:24 + U32 Save_Current_Base_Address_To_Start : 1; // Bits 25:25 + U32 Reset_Current_Base_Address_To_Start : 1; // Bits 26:26 + U32 Data_and_ECC_Address_Inversion : 2; // Bits 28:27 + U32 : 1; // Bits 29:29 + U32 Invert_Data_and_ECC : 1; // Bits 30:30 + U32 Stop_Base_Subsequence_On_Wrap_Trigger : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_STRUCT_HSW_A0; + +typedef union { + struct { + U32 Number_of_Cachelines : 7; // Bits 6:0 + U32 Number_of_Cachelines_Scale : 1; // Bits 7:7 + U32 Subsequence_Wait : 8; // Bits 15:8 + U32 : 4; // Bits 19:16 + U32 Subsequence_Type : 4; // Bits 23:20 + U32 : 1; // Bits 24:24 + U32 Save_Current_Base_Address_To_Start : 1; // Bits 25:25 + U32 Reset_Current_Base_Address_To_Start : 1; // Bits 26:26 + U32 Data_and_ECC_Address_Inversion : 2; // Bits 28:27 + U32 : 1; // Bits 29:29 + U32 Invert_Data_and_ECC : 1; // Bits 30:30 + U32 Stop_Base_Subsequence_On_Wrap_Trigger : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_STRUCT_HSW_A0; + +typedef union { + struct { + U32 Number_of_Cachelines : 7; // Bits 6:0 + U32 Number_of_Cachelines_Scale : 1; // Bits 7:7 + U32 Subsequence_Wait : 8; // Bits 15:8 + U32 : 4; // Bits 19:16 + U32 Subsequence_Type : 4; // Bits 23:20 + U32 : 1; // Bits 24:24 + U32 Save_Current_Base_Address_To_Start : 1; // Bits 25:25 + U32 Reset_Current_Base_Address_To_Start : 1; // Bits 26:26 + U32 Data_and_ECC_Address_Inversion : 2; // Bits 28:27 + U32 : 1; // Bits 29:29 + U32 Invert_Data_and_ECC : 1; // Bits 30:30 + U32 Stop_Base_Subsequence_On_Wrap_Trigger : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_STRUCT_HSW_A0; + +typedef union { + struct { + U32 Number_of_Cachelines : 7; // Bits 6:0 + U32 Number_of_Cachelines_Scale : 1; // Bits 7:7 + U32 Subsequence_Wait : 8; // Bits 15:8 + U32 : 4; // Bits 19:16 + U32 Subsequence_Type : 4; // Bits 23:20 + U32 : 1; // Bits 24:24 + U32 Save_Current_Base_Address_To_Start : 1; // Bits 25:25 + U32 Reset_Current_Base_Address_To_Start : 1; // Bits 26:26 + U32 Data_and_ECC_Address_Inversion : 2; // Bits 28:27 + U32 : 1; // Bits 29:29 + U32 Invert_Data_and_ECC : 1; // Bits 30:30 + U32 Stop_Base_Subsequence_On_Wrap_Trigger : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_STRUCT_HSW_A0; + +typedef union { + struct { + U32 Number_of_Cachelines : 7; // Bits 6:0 + U32 Number_of_Cachelines_Scale : 1; // Bits 7:7 + U32 Subsequence_Wait : 8; // Bits 15:8 + U32 : 4; // Bits 19:16 + U32 Subsequence_Type : 4; // Bits 23:20 + U32 : 1; // Bits 24:24 + U32 Save_Current_Base_Address_To_Start : 1; // Bits 25:25 + U32 Reset_Current_Base_Address_To_Start : 1; // Bits 26:26 + U32 Data_and_ECC_Address_Inversion : 2; // Bits 28:27 + U32 : 1; // Bits 29:29 + U32 Invert_Data_and_ECC : 1; // Bits 30:30 + U32 Stop_Base_Subsequence_On_Wrap_Trigger : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_STRUCT_HSW_A0; + +typedef union { + struct { + U32 Number_of_Cachelines : 7; // Bits 6:0 + U32 Number_of_Cachelines_Scale : 1; // Bits 7:7 + U32 Subsequence_Wait : 14; // Bits 21:8 + U32 Subsequence_Type : 4; // Bits 25:22 + U32 Save_Current_Base_Address_To_Start : 1; // Bits 26:26 + U32 Reset_Current_Base_Address_To_Start : 1; // Bits 27:27 + U32 Data_and_ECC_Address_Inversion : 2; // Bits 29:28 + U32 Invert_Data_and_ECC : 1; // Bits 30:30 + U32 Stop_Base_Subsequence_On_Wrap_Trigger : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_STRUCT; + +typedef union { + struct { + U32 Number_of_Cachelines : 7; // Bits 6:0 + U32 Number_of_Cachelines_Scale : 1; // Bits 7:7 + U32 Subsequence_Wait : 14; // Bits 21:8 + U32 Subsequence_Type : 4; // Bits 25:22 + U32 Save_Current_Base_Address_To_Start : 1; // Bits 26:26 + U32 Reset_Current_Base_Address_To_Start : 1; // Bits 27:27 + U32 Data_and_ECC_Address_Inversion : 2; // Bits 29:28 + U32 Invert_Data_and_ECC : 1; // Bits 30:30 + U32 Stop_Base_Subsequence_On_Wrap_Trigger : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_STRUCT; + +typedef union { + struct { + U32 Number_of_Cachelines : 7; // Bits 6:0 + U32 Number_of_Cachelines_Scale : 1; // Bits 7:7 + U32 Subsequence_Wait : 14; // Bits 21:8 + U32 Subsequence_Type : 4; // Bits 25:22 + U32 Save_Current_Base_Address_To_Start : 1; // Bits 26:26 + U32 Reset_Current_Base_Address_To_Start : 1; // Bits 27:27 + U32 Data_and_ECC_Address_Inversion : 2; // Bits 29:28 + U32 Invert_Data_and_ECC : 1; // Bits 30:30 + U32 Stop_Base_Subsequence_On_Wrap_Trigger : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_STRUCT; + +typedef union { + struct { + U32 Number_of_Cachelines : 7; // Bits 6:0 + U32 Number_of_Cachelines_Scale : 1; // Bits 7:7 + U32 Subsequence_Wait : 14; // Bits 21:8 + U32 Subsequence_Type : 4; // Bits 25:22 + U32 Save_Current_Base_Address_To_Start : 1; // Bits 26:26 + U32 Reset_Current_Base_Address_To_Start : 1; // Bits 27:27 + U32 Data_and_ECC_Address_Inversion : 2; // Bits 29:28 + U32 Invert_Data_and_ECC : 1; // Bits 30:30 + U32 Stop_Base_Subsequence_On_Wrap_Trigger : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_STRUCT; + +typedef union { + struct { + U32 Number_of_Cachelines : 7; // Bits 6:0 + U32 Number_of_Cachelines_Scale : 1; // Bits 7:7 + U32 Subsequence_Wait : 14; // Bits 21:8 + U32 Subsequence_Type : 4; // Bits 25:22 + U32 Save_Current_Base_Address_To_Start : 1; // Bits 26:26 + U32 Reset_Current_Base_Address_To_Start : 1; // Bits 27:27 + U32 Data_and_ECC_Address_Inversion : 2; // Bits 29:28 + U32 Invert_Data_and_ECC : 1; // Bits 30:30 + U32 Stop_Base_Subsequence_On_Wrap_Trigger : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_STRUCT; + +typedef union { + struct { + U32 Number_of_Cachelines : 7; // Bits 6:0 + U32 Number_of_Cachelines_Scale : 1; // Bits 7:7 + U32 Subsequence_Wait : 14; // Bits 21:8 + U32 Subsequence_Type : 4; // Bits 25:22 + U32 Save_Current_Base_Address_To_Start : 1; // Bits 26:26 + U32 Reset_Current_Base_Address_To_Start : 1; // Bits 27:27 + U32 Data_and_ECC_Address_Inversion : 2; // Bits 29:28 + U32 Invert_Data_and_ECC : 1; // Bits 30:30 + U32 Stop_Base_Subsequence_On_Wrap_Trigger : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_STRUCT; + +typedef union { + struct { + U32 Number_of_Cachelines : 7; // Bits 6:0 + U32 Number_of_Cachelines_Scale : 1; // Bits 7:7 + U32 Subsequence_Wait : 14; // Bits 21:8 + U32 Subsequence_Type : 4; // Bits 25:22 + U32 Save_Current_Base_Address_To_Start : 1; // Bits 26:26 + U32 Reset_Current_Base_Address_To_Start : 1; // Bits 27:27 + U32 Data_and_ECC_Address_Inversion : 2; // Bits 29:28 + U32 Invert_Data_and_ECC : 1; // Bits 30:30 + U32 Stop_Base_Subsequence_On_Wrap_Trigger : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_STRUCT; + +typedef union { + struct { + U32 Number_of_Cachelines : 7; // Bits 6:0 + U32 Number_of_Cachelines_Scale : 1; // Bits 7:7 + U32 Subsequence_Wait : 14; // Bits 21:8 + U32 Subsequence_Type : 4; // Bits 25:22 + U32 Save_Current_Base_Address_To_Start : 1; // Bits 26:26 + U32 Reset_Current_Base_Address_To_Start : 1; // Bits 27:27 + U32 Data_and_ECC_Address_Inversion : 2; // Bits 29:28 + U32 Invert_Data_and_ECC : 1; // Bits 30:30 + U32 Stop_Base_Subsequence_On_Wrap_Trigger : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_STRUCT; + +typedef union { + struct { + U32 Number_of_Cachelines : 7; // Bits 6:0 + U32 Number_of_Cachelines_Scale : 1; // Bits 7:7 + U32 Subsequence_Wait : 14; // Bits 21:8 + U32 Subsequence_Type : 4; // Bits 25:22 + U32 Save_Current_Base_Address_To_Start : 1; // Bits 26:26 + U32 Reset_Current_Base_Address_To_Start : 1; // Bits 27:27 + U32 Data_and_ECC_Address_Inversion : 2; // Bits 29:28 + U32 Invert_Data_and_ECC : 1; // Bits 30:30 + U32 Stop_Base_Subsequence_On_Wrap_Trigger : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_STRUCT; + +typedef union { + struct { + U32 Number_of_Cachelines : 7; // Bits 6:0 + U32 Number_of_Cachelines_Scale : 1; // Bits 7:7 + U32 Subsequence_Wait : 14; // Bits 21:8 + U32 Subsequence_Type : 4; // Bits 25:22 + U32 Save_Current_Base_Address_To_Start : 1; // Bits 26:26 + U32 Reset_Current_Base_Address_To_Start : 1; // Bits 27:27 + U32 Data_and_ECC_Address_Inversion : 2; // Bits 29:28 + U32 Invert_Data_and_ECC : 1; // Bits 30:30 + U32 Stop_Base_Subsequence_On_Wrap_Trigger : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_STRUCT; + +typedef union { + struct { + U32 Number_of_Cachelines : 7; // Bits 6:0 + U32 Number_of_Cachelines_Scale : 1; // Bits 7:7 + U32 Subsequence_Wait : 14; // Bits 21:8 + U32 Subsequence_Type : 4; // Bits 25:22 + U32 Save_Current_Base_Address_To_Start : 1; // Bits 26:26 + U32 Reset_Current_Base_Address_To_Start : 1; // Bits 27:27 + U32 Data_and_ECC_Address_Inversion : 2; // Bits 29:28 + U32 Invert_Data_and_ECC : 1; // Bits 30:30 + U32 Stop_Base_Subsequence_On_Wrap_Trigger : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_STRUCT; + +typedef union { + struct { + U32 Number_of_Cachelines : 7; // Bits 6:0 + U32 Number_of_Cachelines_Scale : 1; // Bits 7:7 + U32 Subsequence_Wait : 14; // Bits 21:8 + U32 Subsequence_Type : 4; // Bits 25:22 + U32 Save_Current_Base_Address_To_Start : 1; // Bits 26:26 + U32 Reset_Current_Base_Address_To_Start : 1; // Bits 27:27 + U32 Data_and_ECC_Address_Inversion : 2; // Bits 29:28 + U32 Invert_Data_and_ECC : 1; // Bits 30:30 + U32 Stop_Base_Subsequence_On_Wrap_Trigger : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_STRUCT; + +typedef union { + struct { + U32 Number_of_Cachelines : 7; // Bits 6:0 + U32 Number_of_Cachelines_Scale : 1; // Bits 7:7 + U32 Subsequence_Wait : 14; // Bits 21:8 + U32 Subsequence_Type : 4; // Bits 25:22 + U32 Save_Current_Base_Address_To_Start : 1; // Bits 26:26 + U32 Reset_Current_Base_Address_To_Start : 1; // Bits 27:27 + U32 Data_and_ECC_Address_Inversion : 2; // Bits 29:28 + U32 Invert_Data_and_ECC : 1; // Bits 30:30 + U32 Stop_Base_Subsequence_On_Wrap_Trigger : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_STRUCT; + +typedef union { + struct { + U32 Number_of_Cachelines : 7; // Bits 6:0 + U32 Number_of_Cachelines_Scale : 1; // Bits 7:7 + U32 Subsequence_Wait : 14; // Bits 21:8 + U32 Subsequence_Type : 4; // Bits 25:22 + U32 Save_Current_Base_Address_To_Start : 1; // Bits 26:26 + U32 Reset_Current_Base_Address_To_Start : 1; // Bits 27:27 + U32 Data_and_ECC_Address_Inversion : 2; // Bits 29:28 + U32 Invert_Data_and_ECC : 1; // Bits 30:30 + U32 Stop_Base_Subsequence_On_Wrap_Trigger : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_STRUCT; + +typedef union { + struct { + U32 Number_of_Cachelines : 7; // Bits 6:0 + U32 Number_of_Cachelines_Scale : 1; // Bits 7:7 + U32 Subsequence_Wait : 14; // Bits 21:8 + U32 Subsequence_Type : 4; // Bits 25:22 + U32 Save_Current_Base_Address_To_Start : 1; // Bits 26:26 + U32 Reset_Current_Base_Address_To_Start : 1; // Bits 27:27 + U32 Data_and_ECC_Address_Inversion : 2; // Bits 29:28 + U32 Invert_Data_and_ECC : 1; // Bits 30:30 + U32 Stop_Base_Subsequence_On_Wrap_Trigger : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_STRUCT; + +typedef union { + struct { + U32 Number_of_Cachelines : 7; // Bits 6:0 + U32 Number_of_Cachelines_Scale : 1; // Bits 7:7 + U32 Subsequence_Wait : 14; // Bits 21:8 + U32 Subsequence_Type : 4; // Bits 25:22 + U32 Save_Current_Base_Address_To_Start : 1; // Bits 26:26 + U32 Reset_Current_Base_Address_To_Start : 1; // Bits 27:27 + U32 Data_and_ECC_Address_Inversion : 2; // Bits 29:28 + U32 Invert_Data_and_ECC : 1; // Bits 30:30 + U32 Stop_Base_Subsequence_On_Wrap_Trigger : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_STRUCT; + +typedef union { + struct { + U32 Offset_Address_Update_Rate : 5; // Bits 4:0 + U32 : 3; // Bits 7:5 + U32 Base_Subsequence_Repeat_Rate : 5; // Bits 12:8 + U32 : 2; // Bits 14:13 + U32 Column_Offset_Wrap_Trigger_Enable : 1; // Bits 15:15 + U32 Row_Offset_Wrap_Trigger_Enable : 1; // Bits 16:16 + U32 : 3; // Bits 19:17 + U32 Base_Subsequence_Type : 1; // Bits 20:20 + U32 CADB_Deselect_Enable : 1; // Bits 21:21 + U32 CADB_Select_Enable : 1; // Bits 22:22 + U32 CADB_Seeds_Save_Enable : 1; // Bits 23:23 + U32 Column_Increment_Order : 1; // Bits 24:24 + U32 : 1; // Bits 25:25 + U32 Column_Increment_Enable : 1; // Bits 26:26 + U32 Row_Increment_Order : 1; // Bits 27:27 + U32 : 1; // Bits 28:28 + U32 Row_Increment_Enable : 1; // Bits 29:29 + U32 Base_Invert_Data_and_ECC : 1; // Bits 30:30 + U32 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_STRUCT; + +typedef union { + struct { + U32 Offset_Address_Update_Rate : 5; // Bits 4:0 + U32 : 3; // Bits 7:5 + U32 Base_Subsequence_Repeat_Rate : 5; // Bits 12:8 + U32 : 2; // Bits 14:13 + U32 Column_Offset_Wrap_Trigger_Enable : 1; // Bits 15:15 + U32 Row_Offset_Wrap_Trigger_Enable : 1; // Bits 16:16 + U32 : 3; // Bits 19:17 + U32 Base_Subsequence_Type : 1; // Bits 20:20 + U32 CADB_Deselect_Enable : 1; // Bits 21:21 + U32 CADB_Select_Enable : 1; // Bits 22:22 + U32 CADB_Seeds_Save_Enable : 1; // Bits 23:23 + U32 Column_Increment_Order : 1; // Bits 24:24 + U32 : 1; // Bits 25:25 + U32 Column_Increment_Enable : 1; // Bits 26:26 + U32 Row_Increment_Order : 1; // Bits 27:27 + U32 : 1; // Bits 28:28 + U32 Row_Increment_Enable : 1; // Bits 29:29 + U32 Base_Invert_Data_and_ECC : 1; // Bits 30:30 + U32 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_STRUCT; + +typedef union { + struct { + U32 Offset_Address_Update_Rate : 5; // Bits 4:0 + U32 : 3; // Bits 7:5 + U32 Base_Subsequence_Repeat_Rate : 5; // Bits 12:8 + U32 : 2; // Bits 14:13 + U32 Column_Offset_Wrap_Trigger_Enable : 1; // Bits 15:15 + U32 Row_Offset_Wrap_Trigger_Enable : 1; // Bits 16:16 + U32 : 3; // Bits 19:17 + U32 Base_Subsequence_Type : 1; // Bits 20:20 + U32 CADB_Deselect_Enable : 1; // Bits 21:21 + U32 CADB_Select_Enable : 1; // Bits 22:22 + U32 CADB_Seeds_Save_Enable : 1; // Bits 23:23 + U32 Column_Increment_Order : 1; // Bits 24:24 + U32 : 1; // Bits 25:25 + U32 Column_Increment_Enable : 1; // Bits 26:26 + U32 Row_Increment_Order : 1; // Bits 27:27 + U32 : 1; // Bits 28:28 + U32 Row_Increment_Enable : 1; // Bits 29:29 + U32 Base_Invert_Data_and_ECC : 1; // Bits 30:30 + U32 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_STRUCT; + +typedef union { + struct { + U32 Offset_Address_Update_Rate : 5; // Bits 4:0 + U32 : 3; // Bits 7:5 + U32 Base_Subsequence_Repeat_Rate : 5; // Bits 12:8 + U32 : 2; // Bits 14:13 + U32 Column_Offset_Wrap_Trigger_Enable : 1; // Bits 15:15 + U32 Row_Offset_Wrap_Trigger_Enable : 1; // Bits 16:16 + U32 : 3; // Bits 19:17 + U32 Base_Subsequence_Type : 1; // Bits 20:20 + U32 CADB_Deselect_Enable : 1; // Bits 21:21 + U32 CADB_Select_Enable : 1; // Bits 22:22 + U32 CADB_Seeds_Save_Enable : 1; // Bits 23:23 + U32 Column_Increment_Order : 1; // Bits 24:24 + U32 : 1; // Bits 25:25 + U32 Column_Increment_Enable : 1; // Bits 26:26 + U32 Row_Increment_Order : 1; // Bits 27:27 + U32 : 1; // Bits 28:28 + U32 Row_Increment_Enable : 1; // Bits 29:29 + U32 Base_Invert_Data_and_ECC : 1; // Bits 30:30 + U32 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_STRUCT; + +typedef union { + struct { + U32 Offset_Address_Update_Rate : 5; // Bits 4:0 + U32 : 3; // Bits 7:5 + U32 Base_Subsequence_Repeat_Rate : 5; // Bits 12:8 + U32 : 2; // Bits 14:13 + U32 Column_Offset_Wrap_Trigger_Enable : 1; // Bits 15:15 + U32 Row_Offset_Wrap_Trigger_Enable : 1; // Bits 16:16 + U32 : 3; // Bits 19:17 + U32 Base_Subsequence_Type : 1; // Bits 20:20 + U32 CADB_Deselect_Enable : 1; // Bits 21:21 + U32 CADB_Select_Enable : 1; // Bits 22:22 + U32 CADB_Seeds_Save_Enable : 1; // Bits 23:23 + U32 Column_Increment_Order : 1; // Bits 24:24 + U32 : 1; // Bits 25:25 + U32 Column_Increment_Enable : 1; // Bits 26:26 + U32 Row_Increment_Order : 1; // Bits 27:27 + U32 : 1; // Bits 28:28 + U32 Row_Increment_Enable : 1; // Bits 29:29 + U32 Base_Invert_Data_and_ECC : 1; // Bits 30:30 + U32 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_STRUCT; + +typedef union { + struct { + U32 Offset_Address_Update_Rate : 5; // Bits 4:0 + U32 : 3; // Bits 7:5 + U32 Base_Subsequence_Repeat_Rate : 5; // Bits 12:8 + U32 : 2; // Bits 14:13 + U32 Column_Offset_Wrap_Trigger_Enable : 1; // Bits 15:15 + U32 Row_Offset_Wrap_Trigger_Enable : 1; // Bits 16:16 + U32 : 3; // Bits 19:17 + U32 Base_Subsequence_Type : 1; // Bits 20:20 + U32 CADB_Deselect_Enable : 1; // Bits 21:21 + U32 CADB_Select_Enable : 1; // Bits 22:22 + U32 CADB_Seeds_Save_Enable : 1; // Bits 23:23 + U32 Column_Increment_Order : 1; // Bits 24:24 + U32 : 1; // Bits 25:25 + U32 Column_Increment_Enable : 1; // Bits 26:26 + U32 Row_Increment_Order : 1; // Bits 27:27 + U32 : 1; // Bits 28:28 + U32 Row_Increment_Enable : 1; // Bits 29:29 + U32 Base_Invert_Data_and_ECC : 1; // Bits 30:30 + U32 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_STRUCT; + +typedef union { + struct { + U32 Offset_Address_Update_Rate : 5; // Bits 4:0 + U32 : 3; // Bits 7:5 + U32 Base_Subsequence_Repeat_Rate : 5; // Bits 12:8 + U32 : 2; // Bits 14:13 + U32 Column_Offset_Wrap_Trigger_Enable : 1; // Bits 15:15 + U32 Row_Offset_Wrap_Trigger_Enable : 1; // Bits 16:16 + U32 : 3; // Bits 19:17 + U32 Base_Subsequence_Type : 1; // Bits 20:20 + U32 CADB_Deselect_Enable : 1; // Bits 21:21 + U32 CADB_Select_Enable : 1; // Bits 22:22 + U32 CADB_Seeds_Save_Enable : 1; // Bits 23:23 + U32 Column_Increment_Order : 1; // Bits 24:24 + U32 : 1; // Bits 25:25 + U32 Column_Increment_Enable : 1; // Bits 26:26 + U32 Row_Increment_Order : 1; // Bits 27:27 + U32 : 1; // Bits 28:28 + U32 Row_Increment_Enable : 1; // Bits 29:29 + U32 Base_Invert_Data_and_ECC : 1; // Bits 30:30 + U32 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_STRUCT; + +typedef union { + struct { + U32 Offset_Address_Update_Rate : 5; // Bits 4:0 + U32 : 3; // Bits 7:5 + U32 Base_Subsequence_Repeat_Rate : 5; // Bits 12:8 + U32 : 2; // Bits 14:13 + U32 Column_Offset_Wrap_Trigger_Enable : 1; // Bits 15:15 + U32 Row_Offset_Wrap_Trigger_Enable : 1; // Bits 16:16 + U32 : 3; // Bits 19:17 + U32 Base_Subsequence_Type : 1; // Bits 20:20 + U32 CADB_Deselect_Enable : 1; // Bits 21:21 + U32 CADB_Select_Enable : 1; // Bits 22:22 + U32 CADB_Seeds_Save_Enable : 1; // Bits 23:23 + U32 Column_Increment_Order : 1; // Bits 24:24 + U32 : 1; // Bits 25:25 + U32 Column_Increment_Enable : 1; // Bits 26:26 + U32 Row_Increment_Order : 1; // Bits 27:27 + U32 : 1; // Bits 28:28 + U32 Row_Increment_Enable : 1; // Bits 29:29 + U32 Base_Invert_Data_and_ECC : 1; // Bits 30:30 + U32 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_STRUCT; + +typedef union { + struct { + U32 Offset_Address_Update_Rate : 5; // Bits 4:0 + U32 : 3; // Bits 7:5 + U32 Base_Subsequence_Repeat_Rate : 5; // Bits 12:8 + U32 : 2; // Bits 14:13 + U32 Column_Offset_Wrap_Trigger_Enable : 1; // Bits 15:15 + U32 Row_Offset_Wrap_Trigger_Enable : 1; // Bits 16:16 + U32 : 3; // Bits 19:17 + U32 Base_Subsequence_Type : 1; // Bits 20:20 + U32 CADB_Deselect_Enable : 1; // Bits 21:21 + U32 CADB_Select_Enable : 1; // Bits 22:22 + U32 CADB_Seeds_Save_Enable : 1; // Bits 23:23 + U32 Column_Increment_Order : 1; // Bits 24:24 + U32 : 1; // Bits 25:25 + U32 Column_Increment_Enable : 1; // Bits 26:26 + U32 Row_Increment_Order : 1; // Bits 27:27 + U32 : 1; // Bits 28:28 + U32 Row_Increment_Enable : 1; // Bits 29:29 + U32 Base_Invert_Data_and_ECC : 1; // Bits 30:30 + U32 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_STRUCT; + +typedef union { + struct { + U32 Offset_Address_Update_Rate : 5; // Bits 4:0 + U32 : 3; // Bits 7:5 + U32 Base_Subsequence_Repeat_Rate : 5; // Bits 12:8 + U32 : 2; // Bits 14:13 + U32 Column_Offset_Wrap_Trigger_Enable : 1; // Bits 15:15 + U32 Row_Offset_Wrap_Trigger_Enable : 1; // Bits 16:16 + U32 : 3; // Bits 19:17 + U32 Base_Subsequence_Type : 1; // Bits 20:20 + U32 CADB_Deselect_Enable : 1; // Bits 21:21 + U32 CADB_Select_Enable : 1; // Bits 22:22 + U32 CADB_Seeds_Save_Enable : 1; // Bits 23:23 + U32 Column_Increment_Order : 1; // Bits 24:24 + U32 : 1; // Bits 25:25 + U32 Column_Increment_Enable : 1; // Bits 26:26 + U32 Row_Increment_Order : 1; // Bits 27:27 + U32 : 1; // Bits 28:28 + U32 Row_Increment_Enable : 1; // Bits 29:29 + U32 Base_Invert_Data_and_ECC : 1; // Bits 30:30 + U32 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_STRUCT; + +typedef union { + struct { + U32 Offset_Address_Update_Rate : 5; // Bits 4:0 + U32 : 3; // Bits 7:5 + U32 Base_Subsequence_Repeat_Rate : 5; // Bits 12:8 + U32 : 2; // Bits 14:13 + U32 Column_Offset_Wrap_Trigger_Enable : 1; // Bits 15:15 + U32 Row_Offset_Wrap_Trigger_Enable : 1; // Bits 16:16 + U32 : 3; // Bits 19:17 + U32 Base_Subsequence_Type : 1; // Bits 20:20 + U32 CADB_Deselect_Enable : 1; // Bits 21:21 + U32 CADB_Select_Enable : 1; // Bits 22:22 + U32 CADB_Seeds_Save_Enable : 1; // Bits 23:23 + U32 Column_Increment_Order : 1; // Bits 24:24 + U32 : 1; // Bits 25:25 + U32 Column_Increment_Enable : 1; // Bits 26:26 + U32 Row_Increment_Order : 1; // Bits 27:27 + U32 : 1; // Bits 28:28 + U32 Row_Increment_Enable : 1; // Bits 29:29 + U32 Base_Invert_Data_and_ECC : 1; // Bits 30:30 + U32 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_STRUCT; + +typedef union { + struct { + U32 Offset_Address_Update_Rate : 5; // Bits 4:0 + U32 : 3; // Bits 7:5 + U32 Base_Subsequence_Repeat_Rate : 5; // Bits 12:8 + U32 : 2; // Bits 14:13 + U32 Column_Offset_Wrap_Trigger_Enable : 1; // Bits 15:15 + U32 Row_Offset_Wrap_Trigger_Enable : 1; // Bits 16:16 + U32 : 3; // Bits 19:17 + U32 Base_Subsequence_Type : 1; // Bits 20:20 + U32 CADB_Deselect_Enable : 1; // Bits 21:21 + U32 CADB_Select_Enable : 1; // Bits 22:22 + U32 CADB_Seeds_Save_Enable : 1; // Bits 23:23 + U32 Column_Increment_Order : 1; // Bits 24:24 + U32 : 1; // Bits 25:25 + U32 Column_Increment_Enable : 1; // Bits 26:26 + U32 Row_Increment_Order : 1; // Bits 27:27 + U32 : 1; // Bits 28:28 + U32 Row_Increment_Enable : 1; // Bits 29:29 + U32 Base_Invert_Data_and_ECC : 1; // Bits 30:30 + U32 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_STRUCT; + +typedef union { + struct { + U32 Offset_Address_Update_Rate : 5; // Bits 4:0 + U32 : 3; // Bits 7:5 + U32 Base_Subsequence_Repeat_Rate : 5; // Bits 12:8 + U32 : 2; // Bits 14:13 + U32 Column_Offset_Wrap_Trigger_Enable : 1; // Bits 15:15 + U32 Row_Offset_Wrap_Trigger_Enable : 1; // Bits 16:16 + U32 : 3; // Bits 19:17 + U32 Base_Subsequence_Type : 1; // Bits 20:20 + U32 CADB_Deselect_Enable : 1; // Bits 21:21 + U32 CADB_Select_Enable : 1; // Bits 22:22 + U32 CADB_Seeds_Save_Enable : 1; // Bits 23:23 + U32 Column_Increment_Order : 1; // Bits 24:24 + U32 : 1; // Bits 25:25 + U32 Column_Increment_Enable : 1; // Bits 26:26 + U32 Row_Increment_Order : 1; // Bits 27:27 + U32 : 1; // Bits 28:28 + U32 Row_Increment_Enable : 1; // Bits 29:29 + U32 Base_Invert_Data_and_ECC : 1; // Bits 30:30 + U32 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_STRUCT; + +typedef union { + struct { + U32 Offset_Address_Update_Rate : 5; // Bits 4:0 + U32 : 3; // Bits 7:5 + U32 Base_Subsequence_Repeat_Rate : 5; // Bits 12:8 + U32 : 2; // Bits 14:13 + U32 Column_Offset_Wrap_Trigger_Enable : 1; // Bits 15:15 + U32 Row_Offset_Wrap_Trigger_Enable : 1; // Bits 16:16 + U32 : 3; // Bits 19:17 + U32 Base_Subsequence_Type : 1; // Bits 20:20 + U32 CADB_Deselect_Enable : 1; // Bits 21:21 + U32 CADB_Select_Enable : 1; // Bits 22:22 + U32 CADB_Seeds_Save_Enable : 1; // Bits 23:23 + U32 Column_Increment_Order : 1; // Bits 24:24 + U32 : 1; // Bits 25:25 + U32 Column_Increment_Enable : 1; // Bits 26:26 + U32 Row_Increment_Order : 1; // Bits 27:27 + U32 : 1; // Bits 28:28 + U32 Row_Increment_Enable : 1; // Bits 29:29 + U32 Base_Invert_Data_and_ECC : 1; // Bits 30:30 + U32 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_STRUCT; + +typedef union { + struct { + U32 Offset_Address_Update_Rate : 5; // Bits 4:0 + U32 : 3; // Bits 7:5 + U32 Base_Subsequence_Repeat_Rate : 5; // Bits 12:8 + U32 : 2; // Bits 14:13 + U32 Column_Offset_Wrap_Trigger_Enable : 1; // Bits 15:15 + U32 Row_Offset_Wrap_Trigger_Enable : 1; // Bits 16:16 + U32 : 3; // Bits 19:17 + U32 Base_Subsequence_Type : 1; // Bits 20:20 + U32 CADB_Deselect_Enable : 1; // Bits 21:21 + U32 CADB_Select_Enable : 1; // Bits 22:22 + U32 CADB_Seeds_Save_Enable : 1; // Bits 23:23 + U32 Column_Increment_Order : 1; // Bits 24:24 + U32 : 1; // Bits 25:25 + U32 Column_Increment_Enable : 1; // Bits 26:26 + U32 Row_Increment_Order : 1; // Bits 27:27 + U32 : 1; // Bits 28:28 + U32 Row_Increment_Enable : 1; // Bits 29:29 + U32 Base_Invert_Data_and_ECC : 1; // Bits 30:30 + U32 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_STRUCT; + +typedef union { + struct { + U32 Offset_Address_Update_Rate : 5; // Bits 4:0 + U32 : 3; // Bits 7:5 + U32 Base_Subsequence_Repeat_Rate : 5; // Bits 12:8 + U32 : 2; // Bits 14:13 + U32 Column_Offset_Wrap_Trigger_Enable : 1; // Bits 15:15 + U32 Row_Offset_Wrap_Trigger_Enable : 1; // Bits 16:16 + U32 : 3; // Bits 19:17 + U32 Base_Subsequence_Type : 1; // Bits 20:20 + U32 CADB_Deselect_Enable : 1; // Bits 21:21 + U32 CADB_Select_Enable : 1; // Bits 22:22 + U32 CADB_Seeds_Save_Enable : 1; // Bits 23:23 + U32 Column_Increment_Order : 1; // Bits 24:24 + U32 : 1; // Bits 25:25 + U32 Column_Increment_Enable : 1; // Bits 26:26 + U32 Row_Increment_Order : 1; // Bits 27:27 + U32 : 1; // Bits 28:28 + U32 Row_Increment_Enable : 1; // Bits 29:29 + U32 Base_Invert_Data_and_ECC : 1; // Bits 30:30 + U32 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_STRUCT; + +typedef union { + struct { + U32 : 3; // Bits 2:0 + U32 Stop_Base_Sequence_On_Wrap_Trigger : 1; // Bits 3:3 + U32 : 1; // Bits 4:4 + U32 Address_Update_Rate_Mode : 1; // Bits 5:5 + U32 : 1; // Bits 6:6 + U32 Enable_Dummy_Reads : 1; // Bits 7:7 + U32 : 2; // Bits 9:8 + U32 Enable_Constant_Write_Strobe : 1; // Bits 10:10 + U32 Global_Control : 1; // Bits 11:11 + U32 Initialization_Mode : 2; // Bits 13:12 + U32 : 2; // Bits 15:14 + U32 Loopcount : 5; // Bits 20:16 ** Does not exist in C0 ** + U32 : 3; // Bits 23:21 + U32 Subsequence_Start_Pointer : 3; // Bits 26:24 + U32 : 1; // Bits 27:27 + U32 Subsequence_End_Pointer : 3; // Bits 30:28 + U32 : 1; // Bits 31:31 + U32 Start_Test_Delay : 10; // Bits 41:32 + U32 : 22; // Bits 63:42 + } Bits; + U64 Data; + U32 Data32[2]; + U16 Data16[4]; + U8 Data8[8]; +} MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_STRUCT; + +typedef union { + struct { + U32 : 3; // Bits 2:0 + U32 Stop_Base_Sequence_On_Wrap_Trigger : 1; // Bits 3:3 + U32 : 1; // Bits 4:4 + U32 Address_Update_Rate_Mode : 1; // Bits 5:5 + U32 : 1; // Bits 6:6 + U32 Enable_Dummy_Reads : 1; // Bits 7:7 + U32 : 2; // Bits 9:8 + U32 Enable_Constant_Write_Strobe : 1; // Bits 10:10 + U32 Global_Control : 1; // Bits 11:11 + U32 Initialization_Mode : 2; // Bits 13:12 + U32 : 2; // Bits 15:14 + U32 Loopcount : 5; // Bits 20:16 ** Does not exist in C0 ** + U32 : 3; // Bits 23:21 + U32 Subsequence_Start_Pointer : 3; // Bits 26:24 + U32 : 1; // Bits 27:27 + U32 Subsequence_End_Pointer : 3; // Bits 30:28 + U32 : 1; // Bits 31:31 + U32 Start_Test_Delay : 10; // Bits 41:32 + U32 : 22; // Bits 63:42 + } Bits; + U64 Data; + U32 Data32[2]; + U16 Data16[4]; + U8 Data8[8]; +} MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_STRUCT; + +typedef union { + struct { + U32 Local_Start_Test : 1; // Bits 0:0 + U32 Local_Stop_Test : 1; // Bits 1:1 + U32 Local_Clear_Errors : 1; // Bits 2:2 + U32 : 29; // Bits 31:3 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH_SEQ_CTL_MCMAIN_0_STRUCT; + +typedef union { + struct { + U32 Local_Start_Test : 1; // Bits 0:0 + U32 Local_Stop_Test : 1; // Bits 1:1 + U32 Local_Clear_Errors : 1; // Bits 2:2 + U32 : 29; // Bits 31:3 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH_SEQ_CTL_MCMAIN_1_STRUCT; + +typedef union { + struct { + U32 Current_Loopcount : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH_SEQ_LOOPCOUNT_STATUS_MCMAIN_0_STRUCT; + +typedef union { + struct { + U32 Current_Loopcount : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH_SEQ_LOOPCOUNT_STATUS_MCMAIN_1_STRUCT; + +typedef union { + struct { + U32 Current_Subsequence_Pointer : 3; // Bits 2:0 + U32 : 29; // Bits 31:3 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH_SEQ_SUBSEQ_PNTR_MCMAIN_0_STRUCT; + +typedef union { + struct { + U32 Current_Subsequence_Pointer : 3; // Bits 2:0 + U32 : 29; // Bits 31:3 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH_SEQ_SUBSEQ_PNTR_MCMAIN_1_STRUCT; + +typedef union { + struct { + U32 Current_Cacheline : 16; // Bits 15:0 + U32 : 16; // Bits 31:16 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH_SEQ_CACHELINE_STATUS_MCMAIN_0_STRUCT; + +typedef union { + struct { + U32 Current_Cacheline : 16; // Bits 15:0 + U32 : 16; // Bits 31:16 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH_SEQ_CACHELINE_STATUS_MCMAIN_1_STRUCT; + +typedef union { + struct { + U32 : 3; // Bits 2:0 + U32 Column_Address : 8; // Bits 10:3 + U32 : 13; // Bits 23:11 + U32 Row_Address : 16; // Bits 39:24 + U32 : 8; // Bits 47:40 + U32 Bank_Address : 3; // Bits 50:48 + U32 : 5; // Bits 55:51 + U32 Rank_Address : 3; // Bits 58:56 + U32 : 5; // Bits 63:59 + } Bits; + U64 Data; + U32 Data32[2]; + U16 Data16[4]; + U8 Data8[8]; +} MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_0_STRUCT; + +typedef union { + struct { + U32 : 3; // Bits 2:0 + U32 Column_Address : 8; // Bits 10:3 + U32 : 13; // Bits 23:11 + U32 Row_Address : 16; // Bits 39:24 + U32 : 8; // Bits 47:40 + U32 Bank_Address : 3; // Bits 50:48 + U32 : 5; // Bits 55:51 + U32 Rank_Address : 3; // Bits 58:56 + U32 : 5; // Bits 63:59 + } Bits; + U64 Data; + U32 Data32[2]; + U16 Data16[4]; + U8 Data8[8]; +} MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_1_STRUCT; + +typedef union { + struct { + U32 : 3; // Bits 2:0 + U32 Column_Address : 8; // Bits 10:3 + U32 : 13; // Bits 23:11 + U32 Row_Address : 16; // Bits 39:24 + U32 : 8; // Bits 47:40 + U32 Bank_Address : 3; // Bits 50:48 + U32 : 5; // Bits 55:51 + U32 Rank_Address : 3; // Bits 58:56 + U32 : 5; // Bits 63:59 + } Bits; + U64 Data; + U32 Data32[2]; + U16 Data16[4]; + U8 Data8[8]; +} MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_0_STRUCT; + +typedef union { + struct { + U32 : 3; // Bits 2:0 + U32 Column_Address : 8; // Bits 10:3 + U32 : 13; // Bits 23:11 + U32 Row_Address : 16; // Bits 39:24 + U32 : 8; // Bits 47:40 + U32 Bank_Address : 3; // Bits 50:48 + U32 : 5; // Bits 55:51 + U32 Rank_Address : 3; // Bits 58:56 + U32 : 5; // Bits 63:59 + } Bits; + U64 Data; + U32 Data32[2]; + U16 Data16[4]; + U8 Data8[8]; +} MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_1_STRUCT; + +typedef union { + struct { + U32 : 3; // Bits 2:0 + U32 Column_Address : 8; // Bits 10:3 + U32 : 13; // Bits 23:11 + U32 Row_Address : 16; // Bits 39:24 + U32 : 8; // Bits 47:40 + U32 Bank_Address : 3; // Bits 50:48 + U32 : 5; // Bits 55:51 + U32 Rank_Address : 3; // Bits 58:56 + U32 : 5; // Bits 63:59 + } Bits; + U64 Data; + U32 Data32[2]; + U16 Data16[4]; + U8 Data8[8]; +} MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_0_STRUCT; + +typedef union { + struct { + U32 : 3; // Bits 2:0 + U32 Column_Address : 8; // Bits 10:3 + U32 : 13; // Bits 23:11 + U32 Row_Address : 16; // Bits 39:24 + U32 : 8; // Bits 47:40 + U32 Bank_Address : 3; // Bits 50:48 + U32 : 5; // Bits 55:51 + U32 Rank_Address : 3; // Bits 58:56 + U32 : 5; // Bits 63:59 + } Bits; + U64 Data; + U32 Data32[2]; + U16 Data16[4]; + U8 Data8[8]; +} MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_1_STRUCT; + +typedef union { + struct { + U32 Base_Column_Address_Order : 2; // Bits 1:0 + U32 Base_Row_Address_Order : 2; // Bits 3:2 + U32 Base_Bank_Address_Order : 2; // Bits 5:4 + U32 Base_Rank_Address_Order : 2; // Bits 7:6 + U32 : 5; // Bits 12:8 + U32 Base_Address_Invert_Rate : 3; // Bits 15:13 + U32 : 4; // Bits 19:16 + U32 Column_Base_Address_Invert_Enable : 1; // Bits 20:20 + U32 Row_Base_Address_Invert_Enable : 1; // Bits 21:21 + U32 Bank_Base_Address_Invert_Enable : 1; // Bits 22:22 + U32 Rank_Base_Address_Invert_Enable : 1; // Bits 23:23 + U32 Column_Base_Wrap_Trigger_Enable : 1; // Bits 24:24 + U32 Row_Base_Wrap_Trigger_Enable : 1; // Bits 25:25 + U32 Bank_Base_Wrap_Trigger_Enable : 1; // Bits 26:26 + U32 Rank_Base_Wrap_Trigger_Enable : 1; // Bits 27:27 + U32 Column_Base_Wrap_Carry_Enable : 1; // Bits 28:28 + U32 Row_Base_Wrap_Carry_Enable : 1; // Bits 29:29 + U32 Bank_Base_Wrap_Carry_Enable : 1; // Bits 30:30 + U32 Rank_Base_Wrap_Carry_Enable : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_STRUCT; + +typedef union { + struct { + U32 Base_Column_Address_Order : 2; // Bits 1:0 + U32 Base_Row_Address_Order : 2; // Bits 3:2 + U32 Base_Bank_Address_Order : 2; // Bits 5:4 + U32 Base_Rank_Address_Order : 2; // Bits 7:6 + U32 : 5; // Bits 12:8 + U32 Base_Address_Invert_Rate : 3; // Bits 15:13 + U32 : 4; // Bits 19:16 + U32 Column_Base_Address_Invert_Enable : 1; // Bits 20:20 + U32 Row_Base_Address_Invert_Enable : 1; // Bits 21:21 + U32 Bank_Base_Address_Invert_Enable : 1; // Bits 22:22 + U32 Rank_Base_Address_Invert_Enable : 1; // Bits 23:23 + U32 Column_Base_Wrap_Trigger_Enable : 1; // Bits 24:24 + U32 Row_Base_Wrap_Trigger_Enable : 1; // Bits 25:25 + U32 Bank_Base_Wrap_Trigger_Enable : 1; // Bits 26:26 + U32 Rank_Base_Wrap_Trigger_Enable : 1; // Bits 27:27 + U32 Column_Base_Wrap_Carry_Enable : 1; // Bits 28:28 + U32 Row_Base_Wrap_Carry_Enable : 1; // Bits 29:29 + U32 Bank_Base_Wrap_Carry_Enable : 1; // Bits 30:30 + U32 Rank_Base_Wrap_Carry_Enable : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_STRUCT; + +typedef union { + struct { + U32 : 3; // Bits 2:0 + U32 Column_Base_Address_Increment : 8; // Bits 10:3 + U32 : 1; // Bits 11:11 + U32 Column_Base_Address_Update_Rate : 5; // Bits 16:12 + U32 : 2; // Bits 18:17 + U32 Column_Base_Address_Update_Scale : 1; // Bits 19:19 + U32 Row_Base_Address_Increment : 12; // Bits 31:20 + U32 Row_Base_Address_Update_Rate : 4; // Bits 35:32 + U32 : 1; // Bits 36:36 + U32 Row_Base_Address_Update_Scale : 1; // Bits 37:37 + U32 Bank_Base_Address_Increment : 3; // Bits 40:38 + U32 : 3; // Bits 43:41 + U32 Bank_Base_Address_Update_Rate : 5; // Bits 48:44 + U32 : 2; // Bits 50:49 + U32 Bank_Base_Address_Update_Scale : 1; // Bits 51:51 + U32 Rank_Base_Address_Increment : 3; // Bits 54:52 + U32 : 1; // Bits 55:55 + U32 Rank_Base_Address_Update_Rate : 5; // Bits 60:56 + U32 : 2; // Bits 62:61 + U32 Rank_Base_Address_Update_Scale : 1; // Bits 63:63 + } Bits; + U64 Data; + U32 Data32[2]; + U16 Data16[4]; + U8 Data8[8]; +} MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_STRUCT; + +typedef union { + struct { + U32 : 3; // Bits 2:0 + U32 Column_Base_Address_Increment : 8; // Bits 10:3 + U32 : 1; // Bits 11:11 + U32 Column_Base_Address_Update_Rate : 5; // Bits 16:12 + U32 : 2; // Bits 18:17 + U32 Column_Base_Address_Update_Scale : 1; // Bits 19:19 + U32 Row_Base_Address_Increment : 12; // Bits 31:20 + U32 Row_Base_Address_Update_Rate : 4; // Bits 35:32 + U32 : 1; // Bits 36:36 + U32 Row_Base_Address_Update_Scale : 1; // Bits 37:37 + U32 Bank_Base_Address_Increment : 3; // Bits 40:38 + U32 : 3; // Bits 43:41 + U32 Bank_Base_Address_Update_Rate : 5; // Bits 48:44 + U32 : 2; // Bits 50:49 + U32 Bank_Base_Address_Update_Scale : 1; // Bits 51:51 + U32 Rank_Base_Address_Increment : 3; // Bits 54:52 + U32 : 1; // Bits 55:55 + U32 Rank_Base_Address_Update_Rate : 5; // Bits 60:56 + U32 : 2; // Bits 62:61 + U32 Rank_Base_Address_Update_Scale : 1; // Bits 63:63 + } Bits; + U64 Data; + U32 Data32[2]; + U16 Data16[4]; + U8 Data8[8]; +} MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_STRUCT; + +typedef union { + struct { + U32 : 3; // Bits 2:0 + U32 Column_Address : 8; // Bits 10:3 + U32 : 13; // Bits 23:11 + U32 Row_Address : 16; // Bits 39:24 + U32 : 24; // Bits 63:40 + } Bits; + U64 Data; + U32 Data32[2]; + U16 Data16[4]; + U8 Data8[8]; +} MCDFXS_CR_REUT_CH_SEQ_OFFSET_ADDR_CURRENT_MCMAIN_0_STRUCT; + +typedef union { + struct { + U32 : 3; // Bits 2:0 + U32 Column_Address : 8; // Bits 10:3 + U32 : 13; // Bits 23:11 + U32 Row_Address : 16; // Bits 39:24 + U32 : 24; // Bits 63:40 + } Bits; + U64 Data; + U32 Data32[2]; + U16 Data16[4]; + U8 Data8[8]; +} MCDFXS_CR_REUT_CH_SEQ_OFFSET_ADDR_CURRENT_MCMAIN_1_STRUCT; + +typedef union { + struct { + U32 Logical_to_Physical_Rank0_Mapping : 2; // Bits 1:0 + U32 : 2; // Bits 3:2 + U32 Logical_to_Physical_Rank1_Mapping : 2; // Bits 5:4 + U32 : 2; // Bits 7:6 + U32 Logical_to_Physical_Rank2_Mapping : 2; // Bits 9:8 + U32 : 2; // Bits 11:10 + U32 Logical_to_Physical_Rank3_Mapping : 2; // Bits 13:12 + U32 : 2; // Bits 15:14 + U32 Logical_to_Physical_Rank4_Mapping : 2; // Bits 17:16 + U32 : 2; // Bits 19:18 + U32 Logical_to_Physical_Rank5_Mapping : 2; // Bits 21:20 + U32 : 2; // Bits 23:22 + U32 Logical_to_Physical_Rank6_Mapping : 2; // Bits 25:24 + U32 : 2; // Bits 27:26 + U32 Logical_to_Physical_Rank7_Mapping : 2; // Bits 29:28 + U32 : 2; // Bits 31:30 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_STRUCT; + +typedef union { + struct { + U32 Logical_to_Physical_Rank0_Mapping : 2; // Bits 1:0 + U32 : 2; // Bits 3:2 + U32 Logical_to_Physical_Rank1_Mapping : 2; // Bits 5:4 + U32 : 2; // Bits 7:6 + U32 Logical_to_Physical_Rank2_Mapping : 2; // Bits 9:8 + U32 : 2; // Bits 11:10 + U32 Logical_to_Physical_Rank3_Mapping : 2; // Bits 13:12 + U32 : 2; // Bits 15:14 + U32 Logical_to_Physical_Rank4_Mapping : 2; // Bits 17:16 + U32 : 2; // Bits 19:18 + U32 Logical_to_Physical_Rank5_Mapping : 2; // Bits 21:20 + U32 : 2; // Bits 23:22 + U32 Logical_to_Physical_Rank6_Mapping : 2; // Bits 25:24 + U32 : 2; // Bits 27:26 + U32 Logical_to_Physical_Rank7_Mapping : 2; // Bits 29:28 + U32 : 2; // Bits 31:30 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_1_STRUCT; + +typedef union { + struct { + U32 Logical_to_Physical_Row0_Swizzle : 4; // Bits 3:0 + U32 : 1; // Bits 4:4 + U32 Logical_to_Physical_Row1_Swizzle : 4; // Bits 8:5 + U32 : 1; // Bits 9:9 + U32 Logical_to_Physical_Row2_Swizzle : 4; // Bits 13:10 + U32 : 1; // Bits 14:14 + U32 Logical_to_Physical_Row3_Swizzle : 4; // Bits 18:15 + U32 : 1; // Bits 19:19 + U32 Logical_to_Physical_Row4_Swizzle : 4; // Bits 23:20 + U32 : 1; // Bits 24:24 + U32 Logical_to_Physical_Row5_Swizzle : 4; // Bits 28:25 + U32 : 3; // Bits 31:29 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_0_STRUCT; + +typedef union { + struct { + U32 Logical_to_Physical_Row0_Swizzle : 4; // Bits 3:0 + U32 : 1; // Bits 4:4 + U32 Logical_to_Physical_Row1_Swizzle : 4; // Bits 8:5 + U32 : 1; // Bits 9:9 + U32 Logical_to_Physical_Row2_Swizzle : 4; // Bits 13:10 + U32 : 1; // Bits 14:14 + U32 Logical_to_Physical_Row3_Swizzle : 4; // Bits 18:15 + U32 : 1; // Bits 19:19 + U32 Logical_to_Physical_Row4_Swizzle : 4; // Bits 23:20 + U32 : 1; // Bits 24:24 + U32 Logical_to_Physical_Row5_Swizzle : 4; // Bits 28:25 + U32 : 3; // Bits 31:29 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_1_STRUCT; + +typedef union { + struct { + U32 Logical_to_Physical_Row6_Swizzle : 4; // Bits 3:0 + U32 : 1; // Bits 4:4 + U32 Logical_to_Physical_Row7_Swizzle : 4; // Bits 8:5 + U32 : 1; // Bits 9:9 + U32 Logical_to_Physical_Row8_Swizzle : 4; // Bits 13:10 + U32 : 1; // Bits 14:14 + U32 Logical_to_Physical_Row9_Swizzle : 4; // Bits 18:15 + U32 : 1; // Bits 19:19 + U32 Logical_to_Physical_Row10_Swizzle : 4; // Bits 23:20 + U32 : 1; // Bits 24:24 + U32 Logical_to_Physical_Row11_Swizzle : 4; // Bits 28:25 + U32 : 1; // Bits 29:29 + U32 Logical_to_Physical_Row12_Swizzle : 4; // Bits 33:30 + U32 : 1; // Bits 34:34 + U32 Logical_to_Physical_Row13_Swizzle : 4; // Bits 38:35 + U32 : 1; // Bits 39:39 + U32 Logical_to_Physical_Row14_Swizzle : 4; // Bits 43:40 + U32 : 1; // Bits 44:44 + U32 Logical_to_Physical_Row15_Swizzle : 4; // Bits 48:45 + U32 : 15; // Bits 63:49 + } Bits; + U64 Data; + U32 Data32[2]; + U16 Data16[4]; + U8 Data8[8]; +} MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_STRUCT; + +typedef union { + struct { + U32 Logical_to_Physical_Row6_Swizzle : 4; // Bits 3:0 + U32 : 1; // Bits 4:4 + U32 Logical_to_Physical_Row7_Swizzle : 4; // Bits 8:5 + U32 : 1; // Bits 9:9 + U32 Logical_to_Physical_Row8_Swizzle : 4; // Bits 13:10 + U32 : 1; // Bits 14:14 + U32 Logical_to_Physical_Row9_Swizzle : 4; // Bits 18:15 + U32 : 1; // Bits 19:19 + U32 Logical_to_Physical_Row10_Swizzle : 4; // Bits 23:20 + U32 : 1; // Bits 24:24 + U32 Logical_to_Physical_Row11_Swizzle : 4; // Bits 28:25 + U32 : 1; // Bits 29:29 + U32 Logical_to_Physical_Row12_Swizzle : 4; // Bits 33:30 + U32 : 1; // Bits 34:34 + U32 Logical_to_Physical_Row13_Swizzle : 4; // Bits 38:35 + U32 : 1; // Bits 39:39 + U32 Logical_to_Physical_Row14_Swizzle : 4; // Bits 43:40 + U32 : 1; // Bits 44:44 + U32 Logical_to_Physical_Row15_Swizzle : 4; // Bits 48:45 + U32 : 15; // Bits 63:49 + } Bits; + U64 Data; + U32 Data32[2]; + U16 Data16[4]; + U8 Data8[8]; +} MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_STRUCT; + +typedef union { + struct { + U32 Dummy_Read_Row_Current_Address : 16; // Bits 15:0 + U32 : 8; // Bits 23:16 + U32 Dummy_Read_Bank_Current_Address : 3; // Bits 26:24 + U32 : 5; // Bits 31:27 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_ADDRESS_MCMAIN_0_STRUCT; + +typedef union { + struct { + U32 Dummy_Read_Row_Current_Address : 16; // Bits 15:0 + U32 : 8; // Bits 23:16 + U32 Dummy_Read_Bank_Current_Address : 3; // Bits 26:24 + U32 : 5; // Bits 31:27 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_ADDRESS_MCMAIN_1_STRUCT; + +typedef union { + struct { + U32 Dummy_Read_Bank_Mask : 8; // Bits 7:0 + U32 : 24; // Bits 31:8 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_MASK_MCMAIN_0_STRUCT; + +typedef union { + struct { + U32 Dummy_Read_Bank_Mask : 8; // Bits 7:0 + U32 : 24; // Bits 31:8 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_MASK_MCMAIN_1_STRUCT; + +typedef union { + struct { + U32 L_DummyRead_Select : 1; // Bits 0:0 + U32 Enable_Sweep_Frequency : 1; // Bits 1:1 + U32 : 6; // Bits 7:2 + U32 L_counter : 8; // Bits 15:8 + U32 M_counter : 8; // Bits 23:16 + U32 N_Counter : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_0_STRUCT; + +typedef union { + struct { + U32 L_DummyRead_Select : 1; // Bits 0:0 + U32 Enable_Sweep_Frequency : 1; // Bits 1:1 + U32 : 6; // Bits 7:2 + U32 L_counter : 8; // Bits 15:8 + U32 M_counter : 8; // Bits 23:16 + U32 N_Counter : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_1_STRUCT; + +typedef union { + struct { + U32 EN_CLK : 1; // Bits 0:0 + U32 L0_DATA_BYTE_SEL : 7; // Bits 7:1 + U32 L0_BYP_SEL : 1; // Bits 8:8 + U32 L1_DATA_BYTE_SEL : 7; // Bits 15:9 + U32 L1_BYP_SEL : 1; // Bits 16:16 + U32 : 15; // Bits 31:17 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_VISA_CTL_MCDFXS_MCMAIN_STRUCT; + +typedef union { + struct { + U32 Trigger_In_Global_Start : 1; // Bits 0:0 + U32 Trigger_Out_Global_Start : 1; // Bits 1:1 + U32 : 5; // Bits 6:2 + U32 Trigger_Out_On_Error_0 : 1; // Bits 7:7 + U32 Trigger_Out_On_Error_1 : 1; // Bits 8:8 + U32 : 6; // Bits 14:9 + U32 Trigger_Out_On_Channel_Test_Done_Status_0: 1; // Bits 15:15 + U32 Trigger_Out_On_Channel_Test_Done_Status_1: 1; // Bits 16:16 + U32 : 15; // Bits 31:17 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH_ERR_TRIGGER_CTL_MCMAIN_STRUCT; + +typedef union { + struct { + U32 Loopcount_Limit : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH_SEQ_LOOPCOUNT_LIMIT_MCMAIN_0_STRUCT; + +typedef union { + struct { + U32 Loopcount_Limit : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH_SEQ_LOOPCOUNT_LIMIT_MCMAIN_1_STRUCT; + +typedef union { + struct { + U32 tRCD : 5; // Bits 4:0 + U32 tRP : 5; // Bits 9:5 + U32 tRAS : 6; // Bits 15:10 + U32 tRDPRE : 4; // Bits 19:16 + U32 tWRPRE : 6; // Bits 25:20 + U32 tRRD : 4; // Bits 29:26 + U32 tRPab_ext : 2; // Bits 31:30 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_TC_BANK_STRUCT; + +typedef union { + struct { + U32 tCKE : 4; // Bits 3:0 + U32 tFAW : 8; // Bits 11:4 + U32 tRDRD : 3; // Bits 14:12 + U32 tRDRD_dr : 4; // Bits 18:15 + U32 tRDRD_dd : 4; // Bits 22:19 + U32 tRDPDEN : 5; // Bits 27:23 + U32 : 1; // Bits 28:28 + U32 CMD_3st : 1; // Bits 29:29 + U32 CMD_stretch : 2; // Bits 31:30 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_TC_BANK_RANK_A_STRUCT; + +typedef union { + struct { + U32 tWRRD : 6; // Bits 5:0 + U32 tWRRD_dr : 4; // Bits 9:6 + U32 tWRRD_dd : 4; // Bits 13:10 + U32 tWRWR : 3; // Bits 16:14 + U32 tWRWR_dr : 4; // Bits 20:17 + U32 tWRWR_dd : 4; // Bits 24:21 + U32 tWRPDEN : 6; // Bits 30:25 + U32 Dec_WRD : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_TC_BANK_RANK_B_STRUCT; + +typedef union { + struct { + U32 tXPDLL : 6; // Bits 5:0 + U32 tXP : 4; // Bits 9:6 + U32 TAONPD : 4; // Bits 13:10 + U32 tRDWR : 5; // Bits 18:14 + U32 tRDWR_dr : 5; // Bits 23:19 + U32 tRDWR_dd : 5; // Bits 28:24 + U32 : 3; // Bits 31:29 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_TC_BANK_RANK_C_STRUCT; + +typedef union { + struct { + U32 enable_cmd_rate_limit : 1; // Bits 0:0 + U32 cmd_rate_limit : 3; // Bits 3:1 + U32 reset_on_command : 4; // Bits 7:4 + U32 reset_delay : 4; // Bits 11:8 + U32 ck_to_cke_delay : 2; // Bits 13:12 + U32 spare : 17; // Bits 30:14 + U32 init_mrw_2n_cs : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_CMD_RATE_STRUCT; + +typedef union { + struct { + U32 tCL : 5; // Bits 4:0 + U32 tWCL : 5; // Bits 9:5 + U32 tCPDED : 2; // Bits 11:10 + U32 tPRPDEN : 2; // Bits 13:12 + U32 Odt_Read_Delay : 3; // Bits 16:14 + U32 Odt_Read_Duration : 2; // Bits 18:17 + U32 Odt_Write_Duration : 2; // Bits 20:19 + U32 : 11; // Bits 31:21 + } Bits; +#ifdef ULT_FLAG + struct { + U32 tCL : 5; // Bits 4:0 + U32 tWCL : 5; // Bits 9:5 + U32 tCPDED : 2; // Bits 11:10 + U32 tPRPDEN : 2; // Bits 13:12 + U32 Odt_Read_Delay : 3; // Bits 16:14 + U32 Odt_Read_Duration : 2; // Bits 18:17 + U32 Odt_Write_Duration : 3; // Bits 21:19 + U32 Odt_Write_Delay : 3; // Bits 24:22 + U32 Odt_Always_Rank0 : 1; // Bits 25:25 + U32 cmd_delay : 2; // Bits 27:26 + U32 : 4; // Bits 31:28 + } UltBits; +#endif //ULT_FLAG + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_TC_BANK_RANK_D_STRUCT; + +typedef union { + struct { + U32 dis_opp_cas : 1; // Bits 0:0 + U32 dis_opp_is_cas : 1; // Bits 1:1 + U32 dis_opp_ras : 1; // Bits 2:2 + U32 dis_opp_is_ras : 1; // Bits 3:3 + U32 dis_1c_byp : 1; // Bits 4:4 + U32 dis_2c_byp : 1; // Bits 5:5 + U32 dis_deprd_opt : 1; // Bits 6:6 + U32 dis_pt_it : 1; // Bits 7:7 + U32 dis_prcnt_ring : 1; // Bits 8:8 + U32 dis_prcnt_sa : 1; // Bits 9:9 + U32 dis_blkr_ph : 1; // Bits 10:10 + U32 dis_blkr_pe : 1; // Bits 11:11 + U32 dis_blkr_pm : 1; // Bits 12:12 + U32 dis_odt : 1; // Bits 13:13 + U32 OE_alw_off : 1; // Bits 14:14 + U32 : 1; // Bits 15:15 + U32 dis_aom : 1; // Bits 16:16 + U32 block_rpq : 1; // Bits 17:17 + U32 block_wpq : 1; // Bits 18:18 + U32 invert_align : 1; // Bits 19:19 + U32 dis_write_gap : 1; // Bits 20:20 + U32 dis_zq : 1; // Bits 21:21 + U32 dis_tt : 1; // Bits 22:22 + U32 dis_opp_ref : 1; // Bits 23:23 + U32 Long_ZQ : 1; // Bits 24:24 + U32 dis_srx_zq : 1; // Bits 25:25 + U32 Serialize_ZQ : 1; // Bits 26:26 + U32 ZQ_fast_exec : 1; // Bits 27:27 + U32 Dis_DriveNop : 1; // Bits 28:28 + U32 Pres_WDB_Ent : 1; // Bits 29:29 + U32 dis_clk_gate : 1; // Bits 30:30 + U32 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_SCHED_CBIT_STRUCT; + +typedef union { + struct { + U32 Lat_R0D0 : 6; // Bits 5:0 + U32 : 2; // Bits 7:6 + U32 Lat_R1D0 : 6; // Bits 13:8 + U32 : 2; // Bits 15:14 + U32 Lat_R0D1 : 6; // Bits 21:16 + U32 : 2; // Bits 23:22 + U32 Lat_R1D1 : 6; // Bits 29:24 + U32 : 2; // Bits 31:30 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_SC_ROUNDT_LAT_STRUCT; + +typedef union { + struct { + U32 IOLAT_R0D0 : 4; // Bits 3:0 + U32 IOLAT_R1D0 : 4; // Bits 7:4 + U32 IOLAT_R0D1 : 4; // Bits 11:8 + U32 IOLAT_R1D1 : 4; // Bits 15:12 + U32 RT_IOCOMP : 6; // Bits 21:16 + U32 : 8; // Bits 29:22 + U32 three_channels : 1; // Bits 30:30 + U32 DIS_RT_CLK_GATE : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_SC_IO_LATENCY_STRUCT; + +typedef union { + struct { + U32 DATA : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_ROUND_TRIP_DFT_DATA_STRUCT; + +typedef union { + struct { + U32 WDAR : 1; // Bits 0:0 + U32 safe_mask_sel : 3; // Bits 3:1 + U32 force_rcv_en : 1; // Bits 4:4 + U32 : 3; // Bits 7:5 + U32 DDR_QUAL : 2; // Bits 9:8 + U32 Qual_length : 2; // Bits 11:10 + U32 WDB_Block_En : 1; // Bits 12:12 + U32 RT_DFT_READ_PTR : 4; // Bits 16:13 + U32 RT_DFT_READ_ENABLE : 1; // Bits 17:17 + U32 RT_DFT_READ_SEL_ADDR : 1; // Bits 18:18 + U32 : 13; // Bits 31:19 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_DFT_MISC_STRUCT; + +typedef union { + struct { + U32 ECC : 8; // Bits 7:0 + U32 RRD_DFT_Mode : 2; // Bits 9:8 + U32 LFSR_Seed_Index : 5; // Bits 14:10 + U32 Inversion_Mode : 1; // Bits 15:15 + U32 : 16; // Bits 31:16 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_READ_RETURN_DFT_STRUCT; + +typedef union { + struct { + U32 dis_imph_error : 1; // Bits 0:0 + U32 : 7; // Bits 7:1 + U32 dis_async_odt : 1; // Bits 8:8 + U32 : 23; // Bits 31:9 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_SCHED_SECOND_CBIT_STRUCT; + +typedef union { + struct { + U32 Mux0_Control : 2; // Bits 1:0 + U32 : 1; // Bits 2:2 + U32 Mux1_Control : 2; // Bits 4:3 + U32 : 1; // Bits 5:5 + U32 Mux2_Control : 2; // Bits 7:6 + U32 : 6; // Bits 13:8 + U32 ECC_Replace_Byte_Control : 1; // Bits 14:14 + U32 ECC_Data_Source_Sel : 1; // Bits 15:15 + U32 Save_LFSR_Seed_Rate : 6; // Bits 21:16 + U32 : 2; // Bits 23:22 + U32 Reload_LFSR_Seed_Rate : 3; // Bits 26:24 + U32 : 5; // Bits 31:27 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_STRUCT; + +typedef union { + struct { + U32 WDB_Current_Read_Pointer : 6; // Bits 5:0 + U32 : 26; // Bits 31:6 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_RD_STATUS_STRUCT; + +typedef union { + struct { + U32 Pattern_Buffer : 24; // Bits 23:0 + U32 : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_0_STRUCT; + +typedef union { + struct { + U32 Pattern_Buffer : 24; // Bits 23:0 + U32 : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_1_STRUCT; + +typedef union { + struct { + U32 Pattern_Buffer : 24; // Bits 23:0 + U32 : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_2_STRUCT; + +typedef union { + struct { + U32 Pattern_Buffer : 24; // Bits 23:0 + U32 : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_0_STRUCT; + +typedef union { + struct { + U32 Pattern_Buffer : 24; // Bits 23:0 + U32 : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_1_STRUCT; + +typedef union { + struct { + U32 Pattern_Buffer : 24; // Bits 23:0 + U32 : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_2_STRUCT; + +typedef union { + struct { + U32 Pattern_Buffer : 24; // Bits 23:0 + U32 : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_0_STRUCT; + +typedef union { + struct { + U32 Pattern_Buffer : 24; // Bits 23:0 + U32 : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_1_STRUCT; + +typedef union { + struct { + U32 Pattern_Buffer : 24; // Bits 23:0 + U32 : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_2_STRUCT; + +typedef union { + struct { + U32 Pattern_Buffer : 24; // Bits 23:0 + U32 : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_0_STRUCT; + +typedef union { + struct { + U32 Pattern_Buffer : 24; // Bits 23:0 + U32 : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_1_STRUCT; + +typedef union { + struct { + U32 Pattern_Buffer : 24; // Bits 23:0 + U32 : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_2_STRUCT; + +typedef union { + struct { + U32 L_data_select : 1; // Bits 0:0 + U32 Enable_Sweep_Frequency : 1; // Bits 1:1 + U32 : 6; // Bits 7:2 + U32 L_counter : 8; // Bits 15:8 + U32 M_counter : 8; // Bits 23:16 + U32 N_counter : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_STRUCT; + +typedef union { + struct { + U32 ECC_Inv_or_DC_Enable : 8; // Bits 7:0 + U32 : 8; // Bits 15:8 + U32 Inv_or_DC_Shift_Rate : 4; // Bits 19:16 + U32 DC_Polarity_Control : 1; // Bits 20:20 + U32 : 9; // Bits 29:21 + U32 Inv_or_DC_Control : 1; // Bits 30:30 + U32 Inv_or_DC_Shift_Enable : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_REUT_CH_PAT_WDB_INV_STRUCT; + +typedef union { + struct { + U64 Data_Inv_or_DC_Enable : 64; // Bits 63:0 + } Bits; + U64 Data; + U32 Data32[2]; + U16 Data16[4]; + U8 Data8[8]; +} MCSCHEDS_CR_REUT_CH_PAT_WDB_DATA_INV_STRUCT; + +typedef union { + struct { + U32 Stop_on_Nth_Error : 6; // Bits 5:0 + U32 : 6; // Bits 11:6 + U32 Stop_On_Error_Control : 2; // Bits 13:12 + U32 : 2; // Bits 15:14 + U32 Selective_Error_Enable_Chunk : 8; // Bits 23:16 + U32 Selective_Error_Enable_Cacheline : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_REUT_CH_ERR_CTL_STRUCT; + +typedef union { + struct { + U32 ECC_Error_Mask : 8; // Bits 7:0 + U32 : 24; // Bits 31:8 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_REUT_CH_ERR_ECC_MASK_STRUCT; + +typedef union { + struct { + U32 Stretch_mode : 2; // Bits 1:0 + U32 : 2; // Bits 3:2 + U32 STF : 3; // Bits 6:4 + U32 : 25; // Bits 31:7 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_STM_CONFIG_STRUCT; + +typedef union { + struct { + U32 Priority_count_ring : 10; // Bits 9:0 + U32 : 6; // Bits 15:10 + U32 Priority_count_SA : 10; // Bits 25:16 + U32 : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_SC_PR_CNT_CONFIG_STRUCT; + +typedef union { + struct { + U32 PCIT : 8; // Bits 7:0 + U32 : 24; // Bits 31:8 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_SC_PCIT_STRUCT; + +typedef union { + struct { + U32 PDWN_idle_counter : 12; // Bits 11:0 + U32 PDWN_mode : 4; // Bits 15:12 + U32 : 16; // Bits 31:16 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_PM_PDWN_CONFIG_STRUCT; + +typedef union { + struct { + U32 Count : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_ECC_INJECT_COUNT_STRUCT; + +typedef union { + struct { + U32 ECC4ANA_fill : 8; // Bits 7:0 + U32 ECC4ANA_trigger : 2; // Bits 9:8 + U32 ECC4ANA_BS : 1; // Bits 10:10 + U32 ECC_Inject : 3; // Bits 13:11 + U32 ECC_correction_disable : 1; // Bits 14:14 + U32 ECC4ANA_Inject : 1; // Bits 15:15 + U32 DIS_MCA_LOG : 1; // Bits 16:16 + U32 DIS_PCH_EVENT : 1; // Bits 17:17 + U32 DIS_PCIE_POISON : 1; // Bits 18:18 + U32 : 13; // Bits 31:19 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_ECC_DFT_STRUCT; + +typedef union { + struct { + U32 Data : 18; // Bits 17:0 + U32 : 13; // Bits 30:18 + U32 VORANGE : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_VISA_CTL_MCSCHEDS_STRUCT; + +typedef union { + struct { + U32 Data : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_VISA_XBAR_MCSCHEDS_STRUCT; + +typedef union { + struct { + U32 CERRSTS : 1; // Bits 0:0 + U32 MERRSTS : 1; // Bits 1:1 + U32 : 14; // Bits 15:2 + U32 ERRSYND : 8; // Bits 23:16 + U32 ERRCHUNK : 3; // Bits 26:24 + U32 ERRRANK : 2; // Bits 28:27 + U32 ERRBANK : 3; // Bits 31:29 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_ECCERRLOG0_STRUCT; + +typedef union { + struct { + U32 ERRROW : 16; // Bits 15:0 + U32 ERRCOL : 16; // Bits 31:16 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_ECCERRLOG1_STRUCT; + +typedef union { + struct { + U32 D0R0 : 2; // Bits 1:0 + U32 D0R1 : 2; // Bits 3:2 + U32 D1R0 : 2; // Bits 5:4 + U32 D1R1 : 2; // Bits 7:6 + U32 : 24; // Bits 31:8 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_SC_WR_ADD_DELAY_STRUCT; + +typedef union { + struct { + U32 Dis_Opp_rd : 1; // Bits 0:0 + U32 ACT_Enable : 1; // Bits 1:1 + U32 PRE_Enable : 1; // Bits 2:2 + U32 MAX_RPQ_Cas : 4; // Bits 6:3 + U32 : 25; // Bits 31:7 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_WMM_READ_CONFIG_STRUCT; + +typedef union { + struct { + U64 Data_Error_Mask : 64; // Bits 63:0 + } Bits; + U64 Data; + U32 Data32[2]; + U16 Data16[4]; + U8 Data8[8]; +} MCSCHEDS_CR_REUT_CH_ERR_DATA_MASK_STRUCT; + +typedef union { + struct { + U64 Data_Error_Status : 64; // Bits 63:0 + } Bits; + U64 Data; + U32 Data32[2]; + U16 Data16[4]; + U8 Data8[8]; +} MCSCHEDS_CR_REUT_CH_ERR_DATA_STATUS_STRUCT; + +typedef union { + struct { + U32 ECC_Error_Status : 8; // Bits 7:0 + U32 Chunk_Error_Status : 8; // Bits 15:8 + U32 Rank_Error_Status : 4; // Bits 19:16 + U32 : 12; // Bits 31:20 + U32 Byte_Group_Error_Status : 9; // Bits 40:32 + U32 : 11; // Bits 51:41 + U32 WDB_Rd_Chunk_Num_Status : 3; // Bits 54:52 + U32 : 1; // Bits 55:55 + U32 Nth_Error : 6; // Bits 61:56 + U32 : 2; // Bits 63:62 + } Bits; + U64 Data; + U32 Data32[2]; + U16 Data16[4]; + U8 Data8[8]; +} MCSCHEDS_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_STRUCT; + +typedef union { + struct { + U32 Counter_Pointer : 7; // Bits 6:0 + U32 Counter_Control : 2; // Bits 8:7 + U32 : 23; // Bits 31:9 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_0_STRUCT; + +typedef union { + struct { + U32 Counter_Pointer : 7; // Bits 6:0 + U32 Counter_Control : 2; // Bits 8:7 + U32 : 23; // Bits 31:9 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_1_STRUCT; + +typedef union { + struct { + U32 Counter_Pointer : 7; // Bits 6:0 + U32 Counter_Control : 2; // Bits 8:7 + U32 : 23; // Bits 31:9 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_2_STRUCT; + +typedef union { + struct { + U32 Counter_Pointer : 7; // Bits 6:0 + U32 Counter_Control : 2; // Bits 8:7 + U32 : 23; // Bits 31:9 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_3_STRUCT; + +typedef union { + struct { + U32 Counter_Pointer : 7; // Bits 6:0 + U32 Counter_Control : 2; // Bits 8:7 + U32 : 23; // Bits 31:9 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_4_STRUCT; + +typedef union { + struct { + U32 Counter_Pointer : 7; // Bits 6:0 + U32 Counter_Control : 2; // Bits 8:7 + U32 : 23; // Bits 31:9 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_5_STRUCT; + +typedef union { + struct { + U32 Counter_Pointer : 7; // Bits 6:0 + U32 Counter_Control : 2; // Bits 8:7 + U32 : 23; // Bits 31:9 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_6_STRUCT; + +typedef union { + struct { + U32 Counter_Pointer : 7; // Bits 6:0 + U32 Counter_Control : 2; // Bits 8:7 + U32 : 23; // Bits 31:9 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_7_STRUCT; + +typedef union { + struct { + U32 Counter_Pointer : 7; // Bits 6:0 + U32 Counter_Control : 2; // Bits 8:7 + U32 : 23; // Bits 31:9 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_8_STRUCT; + +typedef union { + struct { + U32 Counter_Status : 23; // Bits 22:0 + U32 : 9; // Bits 31:23 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_0_STRUCT; + +typedef union { + struct { + U32 Counter_Status : 23; // Bits 22:0 + U32 : 9; // Bits 31:23 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_1_STRUCT; + +typedef union { + struct { + U32 Counter_Status : 23; // Bits 22:0 + U32 : 9; // Bits 31:23 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_2_STRUCT; + +typedef union { + struct { + U32 Counter_Status : 23; // Bits 22:0 + U32 : 9; // Bits 31:23 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_3_STRUCT; + +typedef union { + struct { + U32 Counter_Status : 23; // Bits 22:0 + U32 : 9; // Bits 31:23 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_4_STRUCT; + +typedef union { + struct { + U32 Counter_Status : 23; // Bits 22:0 + U32 : 9; // Bits 31:23 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_5_STRUCT; + +typedef union { + struct { + U32 Counter_Status : 23; // Bits 22:0 + U32 : 9; // Bits 31:23 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_6_STRUCT; + +typedef union { + struct { + U32 Counter_Status : 23; // Bits 22:0 + U32 : 9; // Bits 31:23 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_7_STRUCT; + +typedef union { + struct { + U32 Counter_Status : 23; // Bits 22:0 + U32 : 9; // Bits 31:23 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_8_STRUCT; + +typedef union { + struct { + U32 Counter_Overflow_Status : 9; // Bits 8:0 + U32 : 23; // Bits 31:9 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_REUT_CH_ERR_COUNTER_OVERFLOW_STATUS_STRUCT; + +typedef union { + struct { + U32 Column_Address : 10; // Bits 9:0 + U32 : 14; // Bits 23:10 + U32 Row_Address : 16; // Bits 39:24 + U32 : 8; // Bits 47:40 + U32 Bank_Address : 3; // Bits 50:48 + U32 : 5; // Bits 55:51 + U32 Rank_Address : 2; // Bits 57:56 + U32 : 6; // Bits 63:58 + } Bits; + U64 Data; + U32 Data32[2]; + U16 Data16[4]; + U8 Data8[8]; +} MCSCHEDS_CR_REUT_CH_ERROR_ADDR_STRUCT; + +typedef union { + struct { + U32 WDB_Current_Error_Pointer : 6; // Bits 5:0 + U32 : 26; // Bits 31:6 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_REUT_CH_ERR_WDB_CAPTURE_STATUS_STRUCT; + +typedef union { + struct { + U32 Enable_WDB_Error_Capture : 1; // Bits 0:0 + U32 : 7; // Bits 7:1 + U32 WDB_Starting_Error_Pointer : 6; // Bits 13:8 + U32 : 2; // Bits 15:14 + U32 WDB_Ending_Error_Pointer : 6; // Bits 21:16 + U32 : 10; // Bits 31:22 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_STRUCT; + +typedef union { + struct { + U32 CKE_Override : 4; // Bits 3:0 + U32 : 4; // Bits 7:4 + U32 CKE_En_Start_Test_Sync : 1; // Bits 8:8 + U32 : 7; // Bits 15:9 + U32 CKE_On : 4; // Bits 19:16 + U32 : 12; // Bits 31:20 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_REUT_CH_MISC_CKE_CTRL_STRUCT; + +typedef union { + struct { + U32 ODT_Override : 4; // Bits 3:0 + U32 : 12; // Bits 15:4 + U32 ODT_On : 4; // Bits 19:16 + U32 : 11; // Bits 30:20 + U32 MPR_Train_DDR_On : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_REUT_CH_MISC_ODT_CTRL_STRUCT; + +typedef union { + struct { + U32 Enable_CADB_on_Deselect : 1; // Bits 0:0 + U32 Enable_CADB_Always_On : 1; // Bits 1:1 + U32 CMD_Deselect_Start : 4; // Bits 5:2 + U32 CMD_Deselect_Stop : 4; // Bits 9:6 + U32 Lane_Deselect_Enable : 4; // Bits 13:10 + U32 CAS_Select_Enable : 2; // Bits 15:14 + U32 ACT_Select_Enable : 2; // Bits 17:16 + U32 PRE_Select_Enable : 2; // Bits 19:18 + U32 Save_Current_Seed : 4; // Bits 23:20 + U32 Reload_Starting_Seed : 4; // Bits 27:24 + U32 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_STRUCT; + +typedef union { + struct { + U32 MRS_Gap : 3; // Bits 2:0 + U32 : 5; // Bits 7:3 + U32 CADB_MRS_Start_Pointer : 3; // Bits 10:8 + U32 : 5; // Bits 15:11 + U32 CADB_MRS_End_Pointer : 3; // Bits 18:16 + U32 : 5; // Bits 23:19 + U32 CADB_MRS_Current_Pointer : 3; // Bits 26:24 + U32 : 5; // Bits 31:27 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_REUT_CH_PAT_CADB_MRS_STRUCT; + +typedef union { + struct { + U32 Mux0_Control : 2; // Bits 1:0 + U32 : 2; // Bits 3:2 + U32 Mux1_Control : 2; // Bits 5:4 + U32 : 2; // Bits 7:6 + U32 Mux2_Control : 2; // Bits 9:8 + U32 : 6; // Bits 15:10 + U32 Select_Mux0_Control : 2; // Bits 17:16 + U32 : 2; // Bits 19:18 + U32 Select_Mux1_Control : 2; // Bits 21:20 + U32 : 2; // Bits 23:22 + U32 Select_Mux2_Control : 2; // Bits 25:24 + U32 : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_CTRL_STRUCT; + +typedef union { + struct { + U32 Pattern_Buffer : 16; // Bits 15:0 + U32 : 16; // Bits 31:16 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_PB_0_STRUCT; + +typedef union { + struct { + U32 Pattern_Buffer : 16; // Bits 15:0 + U32 : 16; // Bits 31:16 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_PB_1_STRUCT; + +typedef union { + struct { + U32 Pattern_Buffer : 16; // Bits 15:0 + U32 : 16; // Bits 31:16 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_PB_2_STRUCT; + +typedef union { + struct { + U32 L_data_select : 1; // Bits 0:0 + U32 Enable_Sweep_Frequency : 1; // Bits 1:1 + U32 : 6; // Bits 7:2 + U32 L_counter : 8; // Bits 15:8 + U32 M_counter : 8; // Bits 23:16 + U32 N_counter : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_STRUCT; + +typedef union { + struct { + U32 CADB_Write_Pointer : 3; // Bits 2:0 + U32 : 29; // Bits 31:3 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_REUT_CH_PAT_CADB_WRITE_POINTER_STRUCT; + +typedef union { + struct { + U32 CADB_Data_Address : 16; // Bits 15:0 + U32 : 8; // Bits 23:16 + U32 CADB_Data_Bank : 3; // Bits 26:24 + U32 : 5; // Bits 31:27 + U32 CADB_Data_CS : 4; // Bits 35:32 + U32 : 4; // Bits 39:36 + U32 CADB_Data_Control : 3; // Bits 42:40 + U32 : 5; // Bits 47:43 + U32 CADB_Data_ODT : 4; // Bits 51:48 + U32 : 4; // Bits 55:52 + U32 CADB_Data_CKE : 4; // Bits 59:56 + U32 : 4; // Bits 63:60 + } Bits; + U64 Data; + U32 Data32[2]; + U16 Data16[4]; + U8 Data8[8]; +} MCSCHEDS_CR_REUT_CH_PAT_CADB_PROG_STRUCT; + +typedef union { + struct { + U32 Pattern_Buffer : 16; // Bits 15:0 + U32 : 16; // Bits 31:16 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_0_STRUCT; + +typedef union { + struct { + U32 Pattern_Buffer : 16; // Bits 15:0 + U32 : 16; // Bits 31:16 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_1_STRUCT; + +typedef union { + struct { + U32 Pattern_Buffer : 16; // Bits 15:0 + U32 : 16; // Bits 31:16 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_2_STRUCT; + +typedef union { + struct { + U32 WDB_Increment_Rate : 5; // Bits 4:0 + U32 WDB_Increment_Scale : 1; // Bits 5:5 + U32 : 2; // Bits 7:6 + U32 WDB_Start_Pointer : 6; // Bits 13:8 + U32 : 2; // Bits 15:14 + U32 WDB_End_Pointer : 6; // Bits 21:16 + U32 : 10; // Bits 31:22 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCMNTS_CR_REUT_CH_PAT_WDB_CL_CTRL_STRUCT; + +typedef union { + struct { + U32 Refresh_Rank_Mask : 4; // Bits 3:0 + U32 : 4; // Bits 7:4 + U32 RefZQ_En_Start_Test_Sync : 1; // Bits 8:8 + U32 : 22; // Bits 30:9 + U32 Panic_Refresh_Only : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCMNTS_CR_REUT_CH_MISC_REFRESH_CTRL_STRUCT; + +typedef union { + struct { + U32 ZQ_Rank_Mask : 4; // Bits 3:0 + U32 : 27; // Bits 30:4 + U32 Always_Do_ZQ : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCMNTS_CR_REUT_CH_MISC_ZQ_CTRL_STRUCT; + +#ifdef ULT_FLAG +typedef union { + struct { + U32 Rank_0_x32 : 1; // Bits 0:0 + U32 Rank_1_x32 : 1; // Bits 1:1 + U32 Rank_2_x32 : 1; // Bits 2:2 + U32 Rank_3_x32 : 1; // Bits 3:3 + U32 LPDDR2 : 1; // Bits 4:4 + U32 : 3; // Bits 7:5 + U32 MR4_PERIOD : 16; // Bits 23:8 + U32 : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCMNTS_CR_LPDDR_MR_PARAMS_STRUCT; + +typedef union { + struct { + U32 Address : 8; // Bits 7:0 + U32 Data : 8; // Bits 15:8 + U32 Rank : 2; // Bits 17:16 + U32 Write : 1; // Bits 18:18 + U32 Init_MRW : 1; // Bits 19:19 + U32 : 11; // Bits 30:20 + U32 Busy : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCMNTS_CR_LPDDR_MR_COMMAND_STRUCT; + +typedef union { + struct { + U32 Device_0 : 8; // Bits 7:0 + U32 Device_1 : 8; // Bits 15:8 + U32 Device_2 : 8; // Bits 23:16 + U32 Device_3 : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCMNTS_CR_LPDDR_MR_RESULT_STRUCT; + +typedef union { + struct { + U32 Rank_0 : 3; // Bits 2:0 + U32 : 5; // Bits 7:3 + U32 Rank_1 : 3; // Bits 10:8 + U32 : 5; // Bits 15:11 + U32 Rank_2 : 3; // Bits 18:16 + U32 : 5; // Bits 23:19 + U32 Rank_3 : 3; // Bits 26:24 + U32 : 5; // Bits 31:27 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCMNTS_CR_LPDDR_MR4_RANK_TEMPERATURE_STRUCT; + +typedef union { + struct { + U32 Bit_0 : 3; // Bits 2:0 + U32 : 1; // Bits 3:3 + U32 Bit_1 : 3; // Bits 6:4 + U32 : 1; // Bits 7:7 + U32 Bit_2 : 3; // Bits 10:8 + U32 : 1; // Bits 11:11 + U32 Bit_16 : 3; // Bits 14:12 + U32 : 1; // Bits 15:15 + U32 Bit_17 : 3; // Bits 18:16 + U32 : 1; // Bits 19:19 + U32 Bit_18 : 3; // Bits 22:20 + U32 : 1; // Bits 23:23 + U32 Byte_0 : 3; // Bits 26:24 + U32 : 1; // Bits 27:27 + U32 Byte_2 : 3; // Bits 30:28 + U32 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCMNTS_CR_DESWIZZLE_LOW_STRUCT; + +typedef union { + struct { + U32 Bit_32 : 3; // Bits 2:0 + U32 : 1; // Bits 3:3 + U32 Bit_33 : 3; // Bits 6:4 + U32 : 1; // Bits 7:7 + U32 Bit_34 : 3; // Bits 10:8 + U32 : 1; // Bits 11:11 + U32 Bit_48 : 3; // Bits 14:12 + U32 : 1; // Bits 15:15 + U32 Bit_49 : 3; // Bits 18:16 + U32 : 1; // Bits 19:19 + U32 Bit_50 : 3; // Bits 22:20 + U32 : 1; // Bits 23:23 + U32 Byte_4 : 3; // Bits 26:24 + U32 : 1; // Bits 27:27 + U32 Byte_6 : 3; // Bits 30:28 + U32 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCMNTS_CR_DESWIZZLE_HIGH_STRUCT; +#endif // ULT_FLAG + +typedef union { + struct { + U32 Ref_Interval : 11; // Bits 10:0 + U32 Ref_Stagger_En : 1; // Bits 11:11 + U32 Ref_Stagger_Mode : 1; // Bits 12:12 + U32 Disable_Stolen_Refresh : 1; // Bits 13:13 + U32 En_Ref_Type_Display : 1; // Bits 14:14 + U32 : 17; // Bits 31:15 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCMNTS_CR_MC_REFRESH_STAGGER_STRUCT; + +typedef union { + struct { + U32 ZQCS_period : 8; // Bits 7:0 + U32 tZQCS : 8; // Bits 15:8 + U32 : 16; // Bits 31:16 + } Bits; +#ifdef ULT_FLAG + struct { + U32 ZQCS_period : 10; // Bits 9:0 + U32 tZQCS : 10; // Bits 19:10 + U32 : 12; // Bits 31:20 + } UltBits; +#endif // ULT_FLAG + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCMNTS_CR_TC_ZQCAL_STRUCT; + +typedef union { + struct { + U32 OREF_RI : 8; // Bits 7:0 + U32 Refresh_HP_WM : 4; // Bits 11:8 + U32 Refresh_panic_wm : 4; // Bits 15:12 + U32 : 16; // Bits 31:16 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCMNTS_CR_TC_RFP_STRUCT; + +typedef union { + struct { + U32 tREFI : 16; // Bits 15:0 + U32 tRFC : 9; // Bits 24:16 + U32 tREFIx9 : 7; // Bits 31:25 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCMNTS_CR_TC_RFTP_STRUCT; + +typedef union { + struct { + U32 MR2_sh_low : 6; // Bits 5:0 + U32 SRT_avail : 2; // Bits 7:6 + U32 MR2_sh_high : 3; // Bits 10:8 + U32 : 3; // Bits 13:11 + U32 Addr_bit_swizzle : 2; // Bits 15:14 + U32 : 16; // Bits 31:16 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCMNTS_CR_TC_MR2_SHADDOW_STRUCT; + +typedef union { + struct { + U32 Rank_occupancy : 4; // Bits 3:0 + U32 : 28; // Bits 31:4 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCMNTS_CR_MC_INIT_STATE_STRUCT; + +typedef union { + struct { + U32 tXSDLL : 12; // Bits 11:0 + U32 tXS_offset : 4; // Bits 15:12 + U32 tZQOPER : 10; // Bits 25:16 + U32 : 2; // Bits 27:26 + U32 tMOD : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCMNTS_CR_TC_SRFTP_STRUCT; + +typedef union { + struct { + U32 VISAByteSel : 3; // Bits 2:0 + U32 : 29; // Bits 31:3 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCMNTS_CR_WDB_VISA_SEL_STRUCT; + +typedef union { + struct { + U32 FASTADDR : 12; // Bits 11:0 + U32 : 4; // Bits 15:12 + U32 ADDREN : 1; // Bits 16:16 + U32 SEQEN : 1; // Bits 17:17 + U32 POL0 : 1; // Bits 18:18 + U32 POL1 : 1; // Bits 19:19 + U32 CMDA : 4; // Bits 23:20 + U32 CMDB : 4; // Bits 27:24 + U32 CMDC : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCMNTS_CR_DCLK_LDAT_PDAT_STRUCT; + +typedef union { + struct { + U32 BANKSEL : 4; // Bits 3:0 + U32 : 1; // Bits 4:4 + U32 ARRAYSEL : 5; // Bits 9:5 + U32 CMP : 1; // Bits 10:10 + U32 REP : 1; // Bits 11:11 + U32 DWORD : 4; // Bits 15:12 + U32 MODE : 2; // Bits 17:16 + U32 MPMAP : 6; // Bits 23:18 + U32 MPBOFFSET : 4; // Bits 27:24 + U32 STAGE_EN : 1; // Bits 28:28 + U32 SHADOW : 2; // Bits 30:29 + U32 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCMNTS_CR_DCLK_LDAT_SDAT_STRUCT; + +typedef union { + struct { + U32 DATOUT : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCMNTS_CR_DCLK_LDAT_DATAOUT_STRUCT; + +typedef union { + struct { + U32 DATIN : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCMNTS_CR_DCLK_LDAT_DATAIN_0_STRUCT; + +typedef union { + struct { + U32 FASTADDR : 12; // Bits 11:0 + U32 : 4; // Bits 15:12 + U32 ADDREN : 1; // Bits 16:16 + U32 SEQEN : 1; // Bits 17:17 + U32 POL0 : 1; // Bits 18:18 + U32 POL1 : 1; // Bits 19:19 + U32 CMDA : 4; // Bits 23:20 + U32 CMDB : 4; // Bits 27:24 + U32 CMDC : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCMNTS_CR_QCLK_LDAT_PDAT_STRUCT; + +typedef union { + struct { + U32 BANKSEL : 4; // Bits 3:0 + U32 : 1; // Bits 4:4 + U32 ARRAYSEL : 5; // Bits 9:5 + U32 CMP : 1; // Bits 10:10 + U32 REP : 1; // Bits 11:11 + U32 DWORD : 4; // Bits 15:12 + U32 MODE : 2; // Bits 17:16 + U32 MPMAP : 6; // Bits 23:18 + U32 MPBOFFSET : 4; // Bits 27:24 + U32 STAGE_EN : 1; // Bits 28:28 + U32 SHADOW : 2; // Bits 30:29 + U32 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCMNTS_CR_QCLK_LDAT_SDAT_STRUCT; + +typedef union { + struct { + U32 DATOUT : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCMNTS_CR_QCLK_LDAT_DATAOUT_STRUCT; + +typedef union { + struct { + U32 DATIN : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCMNTS_CR_QCLK_LDAT_DATAIN_0_STRUCT; + +typedef union { + struct { + U32 DATIN : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCMNTS_CR_QCLK_LDAT_DATAIN_1_STRUCT; + +typedef union { + struct { + U32 RPQ_disable : 28; // Bits 27:0 + U32 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCMNTS_CR_QUEUE_ENTRY_DISABLE_RPQ_STRUCT; + +typedef union { + struct { + U32 WPQ_disable : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCMNTS_CR_QUEUE_ENTRY_DISABLE_WPQ_STRUCT; + +typedef union { + struct { + U32 DIMM0_IDLE_ENERGY : 6; // Bits 5:0 + U32 : 2; // Bits 7:6 + U32 DIMM1_IDLE_ENERGY : 6; // Bits 13:8 + U32 : 18; // Bits 31:14 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCMNTS_CR_PM_DIMM_IDLE_ENERGY_STRUCT; + +typedef union { + struct { + U32 DIMM0_PD_ENERGY : 6; // Bits 5:0 + U32 : 2; // Bits 7:6 + U32 DIMM1_PD_ENERGY : 6; // Bits 13:8 + U32 : 18; // Bits 31:14 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCMNTS_CR_PM_DIMM_PD_ENERGY_STRUCT; + +typedef union { + struct { + U32 DIMM0_ACT_ENERGY : 8; // Bits 7:0 + U32 DIMM1_ACT_ENERGY : 8; // Bits 15:8 + U32 : 16; // Bits 31:16 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCMNTS_CR_PM_DIMM_ACT_ENERGY_STRUCT; + +typedef union { + struct { + U32 DIMM0_RD_ENERGY : 8; // Bits 7:0 + U32 DIMM1_RD_ENERGY : 8; // Bits 15:8 + U32 : 16; // Bits 31:16 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCMNTS_CR_PM_DIMM_RD_ENERGY_STRUCT; + +typedef union { + struct { + U32 DIMM0_WR_ENERGY : 8; // Bits 7:0 + U32 DIMM1_WR_ENERGY : 8; // Bits 15:8 + U32 : 16; // Bits 31:16 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCMNTS_CR_PM_DIMM_WR_ENERGY_STRUCT; + +typedef union { + struct { + U32 CKE_MIN : 8; // Bits 7:0 + U32 CKE_MIN_DEFEATURE : 1; // Bits 8:8 + U32 : 23; // Bits 31:9 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCMNTS_CR_PM_THRT_CKE_MIN_STRUCT; + +typedef union { + struct { + U32 ODT : 4; // Bits 3:0 + U32 Web : 1; // Bits 4:4 + U32 CASb : 1; // Bits 5:5 + U32 RASb : 1; // Bits 6:6 + U32 CSb : 4; // Bits 10:7 + U32 CKE : 4; // Bits 14:11 + U32 MA : 16; // Bits 30:15 + U32 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCMNTS_CR_ODLAT_CMD_MATCH0_STRUCT; + +typedef union { + struct { + U32 ODT : 4; // Bits 3:0 + U32 Web : 1; // Bits 4:4 + U32 CASb : 1; // Bits 5:5 + U32 RASb : 1; // Bits 6:6 + U32 CSb : 4; // Bits 10:7 + U32 CKE : 4; // Bits 14:11 + U32 MA : 16; // Bits 30:15 + U32 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCMNTS_CR_ODLAT_CMD_MATCH1_STRUCT; + +typedef union { + struct { + U32 ODT : 4; // Bits 3:0 + U32 Web : 1; // Bits 4:4 + U32 CASb : 1; // Bits 5:5 + U32 RASb : 1; // Bits 6:6 + U32 CSb : 4; // Bits 10:7 + U32 CKE : 4; // Bits 14:11 + U32 MA : 16; // Bits 30:15 + U32 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCMNTS_CR_ODLAT_CMD_MATCH2_STRUCT; + +typedef union { + struct { + U32 ODT : 4; // Bits 3:0 + U32 Web : 1; // Bits 4:4 + U32 CASb : 1; // Bits 5:5 + U32 RASb : 1; // Bits 6:6 + U32 CSb : 4; // Bits 10:7 + U32 CKE : 4; // Bits 14:11 + U32 MA : 16; // Bits 30:15 + U32 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCMNTS_CR_ODLAT_CMD_MATCH3_STRUCT; + +typedef union { + struct { + U32 ODT : 4; // Bits 3:0 + U32 Web : 1; // Bits 4:4 + U32 CASb : 1; // Bits 5:5 + U32 RASb : 1; // Bits 6:6 + U32 CSb : 4; // Bits 10:7 + U32 CKE : 4; // Bits 14:11 + U32 MA : 16; // Bits 30:15 + U32 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCMNTS_CR_ODLAT_CMD_MASK0_STRUCT; + +typedef union { + struct { + U32 ODT : 4; // Bits 3:0 + U32 Web : 1; // Bits 4:4 + U32 CASb : 1; // Bits 5:5 + U32 RASb : 1; // Bits 6:6 + U32 CSb : 4; // Bits 10:7 + U32 CKE : 4; // Bits 14:11 + U32 MA : 16; // Bits 30:15 + U32 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCMNTS_CR_ODLAT_CMD_MASK1_STRUCT; + +typedef union { + struct { + U32 ODT : 4; // Bits 3:0 + U32 Web : 1; // Bits 4:4 + U32 CASb : 1; // Bits 5:5 + U32 RASb : 1; // Bits 6:6 + U32 CSb : 4; // Bits 10:7 + U32 CKE : 4; // Bits 14:11 + U32 MA : 16; // Bits 30:15 + U32 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCMNTS_CR_ODLAT_CMD_MASK2_STRUCT; + +typedef union { + struct { + U32 ODT : 4; // Bits 3:0 + U32 Web : 1; // Bits 4:4 + U32 CASb : 1; // Bits 5:5 + U32 RASb : 1; // Bits 6:6 + U32 CSb : 4; // Bits 10:7 + U32 CKE : 4; // Bits 14:11 + U32 MA : 16; // Bits 30:15 + U32 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCMNTS_CR_ODLAT_CMD_MASK3_STRUCT; + +typedef union { + struct { + U32 BankMatch0 : 3; // Bits 2:0 + U32 BankMatch1 : 3; // Bits 5:3 + U32 BankMatch2 : 3; // Bits 8:6 + U32 BankMatch3 : 3; // Bits 11:9 + U32 BankMask0 : 3; // Bits 14:12 + U32 BankMask1 : 3; // Bits 17:15 + U32 BankMask2 : 3; // Bits 20:18 + U32 BankMask3 : 3; // Bits 23:21 + U32 : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCMNTS_CR_ODLAT_CMD_BANK_STRUCT; + +typedef union { + struct { + U32 InputMatch : 4; // Bits 3:0 + U32 InputInvert : 4; // Bits 7:4 + U32 CountMatches : 1; // Bits 8:8 + U32 CounterThreshold : 15; // Bits 23:9 + U32 CounterAction : 2; // Bits 25:24 + U32 CounterNextState : 2; // Bits 27:26 + U32 MatchAction : 2; // Bits 29:28 + U32 MatchNextState : 2; // Bits 31:30 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCMNTS_CR_ODLAT_SEQ_LEVEL0_STRUCT; + +typedef union { + struct { + U32 InputMatch : 4; // Bits 3:0 + U32 InputInvert : 4; // Bits 7:4 + U32 CountMatches : 1; // Bits 8:8 + U32 CounterThreshold : 15; // Bits 23:9 + U32 CounterAction : 2; // Bits 25:24 + U32 CounterNextState : 2; // Bits 27:26 + U32 MatchAction : 2; // Bits 29:28 + U32 MatchNextState : 2; // Bits 31:30 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCMNTS_CR_ODLAT_SEQ_LEVEL1_STRUCT; + +typedef union { + struct { + U32 InputMatch : 4; // Bits 3:0 + U32 InputInvert : 4; // Bits 7:4 + U32 CountMatches : 1; // Bits 8:8 + U32 CounterThreshold : 15; // Bits 23:9 + U32 CounterAction : 2; // Bits 25:24 + U32 CounterNextState : 2; // Bits 27:26 + U32 MatchAction : 2; // Bits 29:28 + U32 MatchNextState : 2; // Bits 31:30 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCMNTS_CR_ODLAT_SEQ_LEVEL2_STRUCT; + +typedef union { + struct { + U32 InputMatch : 4; // Bits 3:0 + U32 InputInvert : 4; // Bits 7:4 + U32 CountMatches : 1; // Bits 8:8 + U32 CounterThreshold : 15; // Bits 23:9 + U32 CounterAction : 2; // Bits 25:24 + U32 CounterNextState : 2; // Bits 27:26 + U32 MatchAction : 2; // Bits 29:28 + U32 MatchNextState : 2; // Bits 31:30 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCMNTS_CR_ODLAT_SEQ_LEVEL3_STRUCT; + +typedef union { + struct { + U32 TriggerBlockEnable : 1; // Bits 0:0 + U32 GlobalCounterThreshold : 16; // Bits 16:1 + U32 : 15; // Bits 31:17 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCMNTS_CR_ODLAT_SEQ_GLOBAL_STRUCT; + +typedef union { + struct { + U32 WMM_Enter : 8; // Bits 7:0 + U32 WMM_Exit : 8; // Bits 15:8 + U32 WPQ_IS : 8; // Bits 23:16 + U32 Starve_count : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCMNTS_CR_SC_WDBWM_STRUCT; + +typedef union { + struct { + U32 Data : 18; // Bits 17:0 + U32 : 13; // Bits 30:18 + U32 VORANGE : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCMNTS_CR_VISA_CTL_MCMNTS_STRUCT; + +typedef union { + struct { + U32 CH_A : 2; // Bits 1:0 + U32 CH_B : 2; // Bits 3:2 + U32 CH_C : 2; // Bits 5:4 + U32 STKD_MODE : 1; // Bits 6:6 + U32 STKD_MODE_CH_BITS : 3; // Bits 9:7 + U32 LPDDR : 1; // Bits 10:10 + U32 : 21; // Bits 31:11 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDECS_CR_MAD_CHNL_MCMAIN_STRUCT; + +typedef union { + struct { + U32 DIMM_A_Size : 8; // Bits 7:0 + U32 DIMM_B_Size : 8; // Bits 15:8 + U32 DAS : 1; // Bits 16:16 + U32 DANOR : 1; // Bits 17:17 + U32 DBNOR : 1; // Bits 18:18 + U32 DAW : 1; // Bits 19:19 + U32 DBW : 1; // Bits 20:20 + U32 RI : 1; // Bits 21:21 + U32 Enh_Interleave : 1; // Bits 22:22 + U32 : 1; // Bits 23:23 + U32 ECC : 2; // Bits 25:24 + U32 HORI : 1; // Bits 26:26 + U32 HORIAddr : 3; // Bits 29:27 + U32 : 2; // Bits 31:30 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDECS_CR_MAD_DIMM_CH0_MCMAIN_STRUCT; + +typedef union { + struct { + U32 DIMM_A_Size : 8; // Bits 7:0 + U32 DIMM_B_Size : 8; // Bits 15:8 + U32 DAS : 1; // Bits 16:16 + U32 DANOR : 1; // Bits 17:17 + U32 DBNOR : 1; // Bits 18:18 + U32 DAW : 1; // Bits 19:19 + U32 DBW : 1; // Bits 20:20 + U32 RI : 1; // Bits 21:21 + U32 Enh_Interleave : 1; // Bits 22:22 + U32 : 1; // Bits 23:23 + U32 ECC : 2; // Bits 25:24 + U32 HORI : 1; // Bits 26:26 + U32 HORIAddr : 3; // Bits 29:27 + U32 : 2; // Bits 31:30 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDECS_CR_MAD_DIMM_CH1_MCMAIN_STRUCT; + +typedef union { + struct { + U32 DIMM_A_Size : 8; // Bits 7:0 + U32 DIMM_B_Size : 8; // Bits 15:8 + U32 DAS : 1; // Bits 16:16 + U32 DANOR : 1; // Bits 17:17 + U32 DBNOR : 1; // Bits 18:18 + U32 DAW : 1; // Bits 19:19 + U32 DBW : 1; // Bits 20:20 + U32 RI : 1; // Bits 21:21 + U32 Enh_Interleave : 1; // Bits 22:22 + U32 : 1; // Bits 23:23 + U32 ECC : 2; // Bits 25:24 + U32 HORI : 1; // Bits 26:26 + U32 HORIAddr : 3; // Bits 29:27 + U32 : 2; // Bits 31:30 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDECS_CR_MAD_DIMM_CH2_MCMAIN_STRUCT; + +typedef union { + struct { + U32 OneC : 8; // Bits 7:0 + U32 ThreeC : 8; // Bits 15:8 + U32 TwoBandC : 8; // Bits 23:16 + U32 BandC : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDECS_CR_MAD_ZR_MCMAIN_STRUCT; + +typedef union { + struct { + U32 spare : 23; // Bits 22:0 + U32 ovrd_pcu_sr_exit : 1; // Bits 23:23 + U32 isoch_stall_pattern : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDECS_CR_MCDECS_MISC_MCMAIN_STRUCT; + +typedef union { + struct { + U32 increase_rcomp : 1; // Bits 0:0 + U32 noa_on_ecc : 1; // Bits 1:1 + U32 noa_demux : 1; // Bits 2:2 + U32 noa_countctrl : 1; // Bits 3:3 + U32 : 4; // Bits 7:4 + U32 psmi_freeze_pwm_counters : 1; // Bits 8:8 + U32 : 6; // Bits 14:9 + U32 dis_lp_prefetch : 1; // Bits 15:15 + U32 : 13; // Bits 28:16 + U32 dis_reg_clk_gate : 1; // Bits 29:29 + U32 dis_msg_clk_gate : 1; // Bits 30:30 + U32 dis_clk_gate : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDECS_CR_MCDECS_CBIT_MCMAIN_STRUCT; + +typedef union { + struct { + U32 count : 4; // Bits 3:0 + U32 : 28; // Bits 31:4 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDECS_CR_SC_IS_CREDIT_MCMAIN_STRUCT; + +typedef union { + struct { + U32 Mask : 14; // Bits 13:0 + U32 : 7; // Bits 20:14 + U32 LSB_mask_bit : 2; // Bits 22:21 + U32 Enable : 1; // Bits 23:23 + U32 : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDECS_CR_CHANNEL_HASH_MCMAIN_STRUCT; + +typedef union { + struct { + U32 pu_mrc_done : 1; // Bits 0:0 + U32 ddr_reset : 1; // Bits 1:1 + U32 : 1; // Bits 2:2 + U32 refresh_enable : 1; // Bits 3:3 + U32 : 1; // Bits 4:4 + U32 mc_init_done_ack : 1; // Bits 5:5 + U32 : 1; // Bits 6:6 + U32 mrc_done : 1; // Bits 7:7 + U32 safe_sr : 1; // Bits 8:8 + U32 : 1; // Bits 9:9 + U32 HVM_Gate_DDR_Reset : 1; // Bits 10:10 + U32 : 11; // Bits 21:11 + U32 dclk_enable : 1; // Bits 22:22 + U32 reset_io : 1; // Bits 23:23 + U32 : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDECS_CR_MC_INIT_STATE_G_MCMAIN_STRUCT; + +typedef union { + struct { + U32 REVISION : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDECS_CR_MRC_REVISION_MCMAIN_STRUCT; + +typedef union { + struct { + U32 count : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDECS_CR_PWM_GT_REQCOUNT_MCMAIN_STRUCT; + +typedef union { + struct { + U32 count : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDECS_CR_PWM_IA_REQCOUNT_MCMAIN_STRUCT; + +typedef union { + struct { + U32 count : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDECS_CR_PWM_IO_REQCOUNT_MCMAIN_STRUCT; + +typedef union { + struct { + U32 count : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDECS_CR_PWM_RDDATA_COUNT_MCMAIN_STRUCT; + +typedef union { + struct { + U32 count : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDECS_CR_PWM_WRDATA_COUNT_MCMAIN_STRUCT; + +typedef union { + struct { + U32 count : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDECS_CR_PWM_COMMAND_COUNT_MCMAIN_STRUCT; + +typedef union { + struct { + U32 Idle_timer : 16; // Bits 15:0 + U32 SR_Enable : 1; // Bits 16:16 + U32 : 15; // Bits 31:17 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDECS_CR_PM_SREF_CONFIG_MCMAIN_STRUCT; + +typedef union { + struct { + U32 Ch_dir : 4; // Bits 3:0 + U32 : 4; // Bits 7:4 + U32 MCI_clk_div : 10; // Bits 17:8 + U32 : 14; // Bits 31:18 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDECS_CR_MCI_CONFIG_MCMAIN_STRUCT; + +typedef union { + struct { + U32 stall_until_drain : 1; // Bits 0:0 + U32 stall_input : 1; // Bits 1:1 + U32 : 2; // Bits 3:2 + U32 mc_drained : 1; // Bits 4:4 + U32 : 3; // Bits 7:5 + U32 sr_state : 2; // Bits 9:8 + U32 : 22; // Bits 31:10 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDECS_CR_STALL_DRAIN_MCMAIN_STRUCT; + +typedef union { + struct { + U32 RPQ_count : 5; // Bits 4:0 + U32 : 3; // Bits 7:5 + U32 WPQ_count : 7; // Bits 14:8 + U32 : 17; // Bits 31:15 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDECS_CR_QUEUE_CREDIT_C_MCMAIN_STRUCT; + +typedef union { + struct { + U32 count : 16; // Bits 15:0 + U32 First_Rcomp_done : 1; // Bits 16:16 + U32 : 15; // Bits 31:17 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDECS_CR_RCOMP_TIMER_MCMAIN_STRUCT; + +typedef union { + struct { + U32 Address : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDECS_CR_ECC_INJ_ADDR_COMPARE_MCMAIN_STRUCT; + +typedef union { + struct { + U32 Mask : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDECS_CR_ECC_INJ_ADDR_MASK_MCMAIN_STRUCT; + +typedef union { + struct { + U32 Data : 18; // Bits 17:0 + U32 : 13; // Bits 30:18 + U32 VORANGE : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDECS_CR_VISA_CTL_MCDECS_MCMAIN_STRUCT; + +typedef union { + struct { + U32 Data : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDECS_CR_VISA_XBAR_MCDECS_MCMAIN_STRUCT; + +typedef union { + struct { + U32 lock_addr_map : 1; // Bits 0:0 + U32 lock_mc_config : 1; // Bits 1:1 + U32 lock_iosav_init : 1; // Bits 2:2 + U32 lock_pwr_mngment : 1; // Bits 3:3 + U32 : 3; // Bits 6:4 + U32 lock_mc_dft : 1; // Bits 7:7 + U32 : 24; // Bits 31:8 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDECS_CR_MC_LOCK_MCMAIN_STRUCT; + +typedef union { + struct { + U32 tRCD : 5; // Bits 4:0 + U32 tRP : 5; // Bits 9:5 + U32 tRAS : 6; // Bits 15:10 + U32 tRDPRE : 4; // Bits 19:16 + U32 tWRPRE : 6; // Bits 25:20 + U32 tRRD : 4; // Bits 29:26 + U32 tRPab_ext : 2; // Bits 31:30 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_TC_BANK_STRUCT; + +typedef union { + struct { + U32 tCKE : 4; // Bits 3:0 + U32 tFAW : 8; // Bits 11:4 + U32 tRDRD : 3; // Bits 14:12 + U32 tRDRD_dr : 4; // Bits 18:15 + U32 tRDRD_dd : 4; // Bits 22:19 + U32 tRDPDEN : 5; // Bits 27:23 + U32 : 1; // Bits 28:28 + U32 CMD_3st : 1; // Bits 29:29 + U32 CMD_stretch : 2; // Bits 31:30 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_TC_BANK_RANK_A_STRUCT; + +typedef union { + struct { + U32 tWRRD : 6; // Bits 5:0 + U32 tWRRD_dr : 4; // Bits 9:6 + U32 tWRRD_dd : 4; // Bits 13:10 + U32 tWRWR : 3; // Bits 16:14 + U32 tWRWR_dr : 4; // Bits 20:17 + U32 tWRWR_dd : 4; // Bits 24:21 + U32 tWRPDEN : 6; // Bits 30:25 + U32 Dec_WRD : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_TC_BANK_RANK_B_STRUCT; + +typedef union { + struct { + U32 tXPDLL : 6; // Bits 5:0 + U32 tXP : 4; // Bits 9:6 + U32 TAONPD : 4; // Bits 13:10 + U32 tRDWR : 5; // Bits 18:14 + U32 tRDWR_dr : 5; // Bits 23:19 + U32 tRDWR_dd : 5; // Bits 28:24 + U32 : 3; // Bits 31:29 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_TC_BANK_RANK_C_STRUCT; + +typedef union { + struct { + U32 enable_cmd_rate_limit : 1; // Bits 0:0 + U32 cmd_rate_limit : 3; // Bits 3:1 + U32 reset_on_command : 4; // Bits 7:4 + U32 reset_delay : 4; // Bits 11:8 + U32 ck_to_cke_delay : 2; // Bits 13:12 + U32 spare : 17; // Bits 30:14 + U32 init_mrw_2n_cs : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_CMD_RATE_STRUCT; + +typedef union { + struct { + U32 tCL : 5; // Bits 4:0 + U32 tWCL : 5; // Bits 9:5 + U32 tCPDED : 2; // Bits 11:10 + U32 tPRPDEN : 2; // Bits 13:12 + U32 Odt_Read_Delay : 3; // Bits 16:14 + U32 Odt_Read_Duration : 2; // Bits 18:17 + U32 Odt_Write_Duration : 2; // Bits 20:19 + U32 : 11; // Bits 31:21 + } Bits; +#ifdef ULT_FLAG + struct { + U32 tCL : 5; // Bits 4:0 + U32 tWCL : 5; // Bits 9:5 + U32 tCPDED : 2; // Bits 11:10 + U32 tPRPDEN : 2; // Bits 13:12 + U32 Odt_Read_Delay : 3; // Bits 16:14 + U32 Odt_Read_Duration : 2; // Bits 18:17 + U32 Odt_Write_Duration : 3; // Bits 21:19 + U32 Odt_Write_Delay : 3; // Bits 24:22 + U32 Odt_Always_Rank0 : 1; // Bits 25:25 + U32 cmd_delay : 2; // Bits 27:26 + U32 : 4; // Bits 31:28 + } UltBits; +#endif // ULT_FLAG + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_TC_BANK_RANK_D_STRUCT; + +typedef union { + struct { + U32 dis_opp_cas : 1; // Bits 0:0 + U32 dis_opp_is_cas : 1; // Bits 1:1 + U32 dis_opp_ras : 1; // Bits 2:2 + U32 dis_opp_is_ras : 1; // Bits 3:3 + U32 dis_1c_byp : 1; // Bits 4:4 + U32 dis_2c_byp : 1; // Bits 5:5 + U32 dis_deprd_opt : 1; // Bits 6:6 + U32 dis_pt_it : 1; // Bits 7:7 + U32 dis_prcnt_ring : 1; // Bits 8:8 + U32 dis_prcnt_sa : 1; // Bits 9:9 + U32 dis_blkr_ph : 1; // Bits 10:10 + U32 dis_blkr_pe : 1; // Bits 11:11 + U32 dis_blkr_pm : 1; // Bits 12:12 + U32 dis_odt : 1; // Bits 13:13 + U32 OE_alw_off : 1; // Bits 14:14 + U32 : 1; // Bits 15:15 + U32 dis_aom : 1; // Bits 16:16 + U32 block_rpq : 1; // Bits 17:17 + U32 block_wpq : 1; // Bits 18:18 + U32 invert_align : 1; // Bits 19:19 + U32 dis_write_gap : 1; // Bits 20:20 + U32 dis_zq : 1; // Bits 21:21 + U32 dis_tt : 1; // Bits 22:22 + U32 dis_opp_ref : 1; // Bits 23:23 + U32 Long_ZQ : 1; // Bits 24:24 + U32 dis_srx_zq : 1; // Bits 25:25 + U32 Serialize_ZQ : 1; // Bits 26:26 + U32 ZQ_fast_exec : 1; // Bits 27:27 + U32 Dis_DriveNop : 1; // Bits 28:28 + U32 Pres_WDB_Ent : 1; // Bits 29:29 + U32 dis_clk_gate : 1; // Bits 30:30 + U32 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_SCHED_CBIT_STRUCT; + +typedef union { + struct { + U32 Lat_R0D0 : 6; // Bits 5:0 + U32 : 2; // Bits 7:6 + U32 Lat_R1D0 : 6; // Bits 13:8 + U32 : 2; // Bits 15:14 + U32 Lat_R0D1 : 6; // Bits 21:16 + U32 : 2; // Bits 23:22 + U32 Lat_R1D1 : 6; // Bits 29:24 + U32 : 2; // Bits 31:30 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_SC_ROUNDT_LAT_STRUCT; + +typedef union { + struct { + U32 IOLAT_R0D0 : 4; // Bits 3:0 + U32 IOLAT_R1D0 : 4; // Bits 7:4 + U32 IOLAT_R0D1 : 4; // Bits 11:8 + U32 IOLAT_R1D1 : 4; // Bits 15:12 + U32 RT_IOCOMP : 6; // Bits 21:16 + U32 : 8; // Bits 29:22 + U32 three_channels : 1; // Bits 30:30 + U32 DIS_RT_CLK_GATE : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_SC_IO_LATENCY_STRUCT; + +typedef union { + struct { + U32 DATA : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_ROUND_TRIP_DFT_DATA_STRUCT; + +typedef union { + struct { + U32 WDAR : 1; // Bits 0:0 + U32 safe_mask_sel : 3; // Bits 3:1 + U32 force_rcv_en : 1; // Bits 4:4 + U32 : 3; // Bits 7:5 + U32 DDR_QUAL : 2; // Bits 9:8 + U32 Qual_length : 2; // Bits 11:10 + U32 WDB_Block_En : 1; // Bits 12:12 + U32 RT_DFT_READ_PTR : 4; // Bits 16:13 + U32 RT_DFT_READ_ENABLE : 1; // Bits 17:17 + U32 RT_DFT_READ_SEL_ADDR : 1; // Bits 18:18 + U32 : 13; // Bits 31:19 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_DFT_MISC_STRUCT; + +typedef union { + struct { + U32 ECC : 8; // Bits 7:0 + U32 RRD_DFT_Mode : 2; // Bits 9:8 + U32 LFSR_Seed_Index : 5; // Bits 14:10 + U32 Inversion_Mode : 1; // Bits 15:15 + U32 : 16; // Bits 31:16 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_READ_RETURN_DFT_STRUCT; + +typedef union { + struct { + U32 dis_imph_error : 1; // Bits 0:0 + U32 : 7; // Bits 7:1 + U32 dis_async_odt : 1; // Bits 8:8 + U32 : 23; // Bits 31:9 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_SCHED_SECOND_CBIT_STRUCT; + +typedef union { + struct { + U32 Mux0_Control : 2; // Bits 1:0 + U32 : 1; // Bits 2:2 + U32 Mux1_Control : 2; // Bits 4:3 + U32 : 1; // Bits 5:5 + U32 Mux2_Control : 2; // Bits 7:6 + U32 : 6; // Bits 13:8 + U32 ECC_Replace_Byte_Control : 1; // Bits 14:14 + U32 ECC_Data_Source_Sel : 1; // Bits 15:15 + U32 Save_LFSR_Seed_Rate : 6; // Bits 21:16 + U32 : 2; // Bits 23:22 + U32 Reload_LFSR_Seed_Rate : 3; // Bits 26:24 + U32 : 5; // Bits 31:27 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_STRUCT; + +typedef union { + struct { + U32 WDB_Current_Read_Pointer : 6; // Bits 5:0 + U32 : 26; // Bits 31:6 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_RD_STATUS_STRUCT; + +typedef union { + struct { + U32 Pattern_Buffer : 24; // Bits 23:0 + U32 : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_0_STRUCT; + +typedef union { + struct { + U32 Pattern_Buffer : 24; // Bits 23:0 + U32 : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_1_STRUCT; + +typedef union { + struct { + U32 Pattern_Buffer : 24; // Bits 23:0 + U32 : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_2_STRUCT; + +typedef union { + struct { + U32 Pattern_Buffer : 24; // Bits 23:0 + U32 : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_0_STRUCT; + +typedef union { + struct { + U32 Pattern_Buffer : 24; // Bits 23:0 + U32 : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_1_STRUCT; + +typedef union { + struct { + U32 Pattern_Buffer : 24; // Bits 23:0 + U32 : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_2_STRUCT; + +typedef union { + struct { + U32 Pattern_Buffer : 24; // Bits 23:0 + U32 : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_0_STRUCT; + +typedef union { + struct { + U32 Pattern_Buffer : 24; // Bits 23:0 + U32 : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_1_STRUCT; + +typedef union { + struct { + U32 Pattern_Buffer : 24; // Bits 23:0 + U32 : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_2_STRUCT; + +typedef union { + struct { + U32 Pattern_Buffer : 24; // Bits 23:0 + U32 : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_0_STRUCT; + +typedef union { + struct { + U32 Pattern_Buffer : 24; // Bits 23:0 + U32 : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_1_STRUCT; + +typedef union { + struct { + U32 Pattern_Buffer : 24; // Bits 23:0 + U32 : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_2_STRUCT; + +typedef union { + struct { + U32 L_data_select : 1; // Bits 0:0 + U32 Enable_Sweep_Frequency : 1; // Bits 1:1 + U32 : 6; // Bits 7:2 + U32 L_counter : 8; // Bits 15:8 + U32 M_counter : 8; // Bits 23:16 + U32 N_counter : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_STRUCT; + +typedef union { + struct { + U32 ECC_Inv_or_DC_Enable : 8; // Bits 7:0 + U32 : 8; // Bits 15:8 + U32 Inv_or_DC_Shift_Rate : 4; // Bits 19:16 + U32 DC_Polarity_Control : 1; // Bits 20:20 + U32 : 9; // Bits 29:21 + U32 Inv_or_DC_Control : 1; // Bits 30:30 + U32 Inv_or_DC_Shift_Enable : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_REUT_CH_PAT_WDB_INV_STRUCT; + +typedef union { + struct { + U64 Data_Inv_or_DC_Enable : 64; // Bits 63:0 + } Bits; + U64 Data; + U32 Data32[2]; + U16 Data16[4]; + U8 Data8[8]; +} MCHBAR_CH0_CR_REUT_CH_PAT_WDB_DATA_INV_STRUCT; + +typedef union { + struct { + U32 Stop_on_Nth_Error : 6; // Bits 5:0 + U32 : 6; // Bits 11:6 + U32 Stop_On_Error_Control : 2; // Bits 13:12 + U32 : 2; // Bits 15:14 + U32 Selective_Error_Enable_Chunk : 8; // Bits 23:16 + U32 Selective_Error_Enable_Cacheline : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_REUT_CH_ERR_CTL_STRUCT; + +typedef union { + struct { + U32 ECC_Error_Mask : 8; // Bits 7:0 + U32 : 24; // Bits 31:8 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_REUT_CH_ERR_ECC_MASK_STRUCT; + +typedef union { + struct { + U32 Stretch_mode : 2; // Bits 1:0 + U32 : 2; // Bits 3:2 + U32 STF : 3; // Bits 6:4 + U32 : 25; // Bits 31:7 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_STM_CONFIG_STRUCT; + +typedef union { + struct { + U32 Priority_count_ring : 10; // Bits 9:0 + U32 : 6; // Bits 15:10 + U32 Priority_count_SA : 10; // Bits 25:16 + U32 : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_SC_PR_CNT_CONFIG_STRUCT; + +typedef union { + struct { + U32 PCIT : 8; // Bits 7:0 + U32 : 24; // Bits 31:8 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_SC_PCIT_STRUCT; + +typedef union { + struct { + U32 PDWN_idle_counter : 12; // Bits 11:0 + U32 PDWN_mode : 4; // Bits 15:12 + U32 : 16; // Bits 31:16 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_PM_PDWN_CONFIG_STRUCT; + +typedef union { + struct { + U32 Count : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_ECC_INJECT_COUNT_STRUCT; + +typedef union { + struct { + U32 ECC4ANA_fill : 8; // Bits 7:0 + U32 ECC4ANA_trigger : 2; // Bits 9:8 + U32 ECC4ANA_BS : 1; // Bits 10:10 + U32 ECC_Inject : 3; // Bits 13:11 + U32 ECC_correction_disable : 1; // Bits 14:14 + U32 ECC4ANA_Inject : 1; // Bits 15:15 + U32 DIS_MCA_LOG : 1; // Bits 16:16 + U32 DIS_PCH_EVENT : 1; // Bits 17:17 + U32 DIS_PCIE_POISON : 1; // Bits 18:18 + U32 : 13; // Bits 31:19 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_ECC_DFT_STRUCT; + +typedef union { + struct { + U32 Data : 18; // Bits 17:0 + U32 : 13; // Bits 30:18 + U32 VORANGE : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_VISA_CTL_MCSCHEDS_STRUCT; + +typedef union { + struct { + U32 Data : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_VISA_XBAR_MCSCHEDS_STRUCT; + +typedef union { + struct { + U32 CERRSTS : 1; // Bits 0:0 + U32 MERRSTS : 1; // Bits 1:1 + U32 : 14; // Bits 15:2 + U32 ERRSYND : 8; // Bits 23:16 + U32 ERRCHUNK : 3; // Bits 26:24 + U32 ERRRANK : 2; // Bits 28:27 + U32 ERRBANK : 3; // Bits 31:29 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_ECCERRLOG0_STRUCT; + +typedef union { + struct { + U32 ERRROW : 16; // Bits 15:0 + U32 ERRCOL : 16; // Bits 31:16 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_ECCERRLOG1_STRUCT; + +typedef union { + struct { + U32 D0R0 : 2; // Bits 1:0 + U32 D0R1 : 2; // Bits 3:2 + U32 D1R0 : 2; // Bits 5:4 + U32 D1R1 : 2; // Bits 7:6 + U32 : 24; // Bits 31:8 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_SC_WR_ADD_DELAY_STRUCT; + +typedef union { + struct { + U32 Dis_Opp_rd : 1; // Bits 0:0 + U32 ACT_Enable : 1; // Bits 1:1 + U32 PRE_Enable : 1; // Bits 2:2 + U32 MAX_RPQ_Cas : 4; // Bits 6:3 + U32 : 25; // Bits 31:7 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_WMM_READ_CONFIG_STRUCT; + +typedef union { + struct { + U64 Data_Error_Mask : 64; // Bits 63:0 + } Bits; + U64 Data; + U32 Data32[2]; + U16 Data16[4]; + U8 Data8[8]; +} MCHBAR_CH0_CR_REUT_CH_ERR_DATA_MASK_STRUCT; + +typedef union { + struct { + U64 Data_Error_Status : 64; // Bits 63:0 + } Bits; + U64 Data; + U32 Data32[2]; + U16 Data16[4]; + U8 Data8[8]; +} MCHBAR_CH0_CR_REUT_CH_ERR_DATA_STATUS_STRUCT; + +typedef union { + struct { + U32 ECC_Error_Status : 8; // Bits 7:0 + U32 Chunk_Error_Status : 8; // Bits 15:8 + U32 Rank_Error_Status : 4; // Bits 19:16 + U32 : 12; // Bits 31:20 + U32 Byte_Group_Error_Status : 9; // Bits 40:32 + U32 : 11; // Bits 51:41 + U32 WDB_Rd_Chunk_Num_Status : 3; // Bits 54:52 + U32 : 1; // Bits 55:55 + U32 Nth_Error : 6; // Bits 61:56 + U32 : 2; // Bits 63:62 + } Bits; + U64 Data; + U32 Data32[2]; + U16 Data16[4]; + U8 Data8[8]; +} MCHBAR_CH0_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_STRUCT; + +typedef union { + struct { + U32 Counter_Pointer : 7; // Bits 6:0 + U32 Counter_Control : 2; // Bits 8:7 + U32 : 23; // Bits 31:9 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_0_STRUCT; + +typedef union { + struct { + U32 Counter_Pointer : 7; // Bits 6:0 + U32 Counter_Control : 2; // Bits 8:7 + U32 : 23; // Bits 31:9 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_1_STRUCT; + +typedef union { + struct { + U32 Counter_Pointer : 7; // Bits 6:0 + U32 Counter_Control : 2; // Bits 8:7 + U32 : 23; // Bits 31:9 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_2_STRUCT; + +typedef union { + struct { + U32 Counter_Pointer : 7; // Bits 6:0 + U32 Counter_Control : 2; // Bits 8:7 + U32 : 23; // Bits 31:9 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_3_STRUCT; + +typedef union { + struct { + U32 Counter_Pointer : 7; // Bits 6:0 + U32 Counter_Control : 2; // Bits 8:7 + U32 : 23; // Bits 31:9 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_4_STRUCT; + +typedef union { + struct { + U32 Counter_Pointer : 7; // Bits 6:0 + U32 Counter_Control : 2; // Bits 8:7 + U32 : 23; // Bits 31:9 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_5_STRUCT; + +typedef union { + struct { + U32 Counter_Pointer : 7; // Bits 6:0 + U32 Counter_Control : 2; // Bits 8:7 + U32 : 23; // Bits 31:9 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_6_STRUCT; + +typedef union { + struct { + U32 Counter_Pointer : 7; // Bits 6:0 + U32 Counter_Control : 2; // Bits 8:7 + U32 : 23; // Bits 31:9 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_7_STRUCT; + +typedef union { + struct { + U32 Counter_Pointer : 7; // Bits 6:0 + U32 Counter_Control : 2; // Bits 8:7 + U32 : 23; // Bits 31:9 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_8_STRUCT; + +typedef union { + struct { + U32 Counter_Status : 23; // Bits 22:0 + U32 : 9; // Bits 31:23 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_0_STRUCT; + +typedef union { + struct { + U32 Counter_Status : 23; // Bits 22:0 + U32 : 9; // Bits 31:23 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_1_STRUCT; + +typedef union { + struct { + U32 Counter_Status : 23; // Bits 22:0 + U32 : 9; // Bits 31:23 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_2_STRUCT; + +typedef union { + struct { + U32 Counter_Status : 23; // Bits 22:0 + U32 : 9; // Bits 31:23 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_3_STRUCT; + +typedef union { + struct { + U32 Counter_Status : 23; // Bits 22:0 + U32 : 9; // Bits 31:23 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_4_STRUCT; + +typedef union { + struct { + U32 Counter_Status : 23; // Bits 22:0 + U32 : 9; // Bits 31:23 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_5_STRUCT; + +typedef union { + struct { + U32 Counter_Status : 23; // Bits 22:0 + U32 : 9; // Bits 31:23 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_6_STRUCT; + +typedef union { + struct { + U32 Counter_Status : 23; // Bits 22:0 + U32 : 9; // Bits 31:23 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_7_STRUCT; + +typedef union { + struct { + U32 Counter_Status : 23; // Bits 22:0 + U32 : 9; // Bits 31:23 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_8_STRUCT; + +typedef union { + struct { + U32 Counter_Overflow_Status : 9; // Bits 8:0 + U32 : 23; // Bits 31:9 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_OVERFLOW_STATUS_STRUCT; + +typedef union { + struct { + U32 Column_Address : 10; // Bits 9:0 + U32 : 14; // Bits 23:10 + U32 Row_Address : 16; // Bits 39:24 + U32 : 8; // Bits 47:40 + U32 Bank_Address : 3; // Bits 50:48 + U32 : 5; // Bits 55:51 + U32 Rank_Address : 2; // Bits 57:56 + U32 : 6; // Bits 63:58 + } Bits; + U64 Data; + U32 Data32[2]; + U16 Data16[4]; + U8 Data8[8]; +} MCHBAR_CH0_CR_REUT_CH_ERROR_ADDR_STRUCT; + +typedef union { + struct { + U32 WDB_Current_Error_Pointer : 6; // Bits 5:0 + U32 : 26; // Bits 31:6 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_REUT_CH_ERR_WDB_CAPTURE_STATUS_STRUCT; + +typedef union { + struct { + U32 Enable_WDB_Error_Capture : 1; // Bits 0:0 + U32 : 7; // Bits 7:1 + U32 WDB_Starting_Error_Pointer : 6; // Bits 13:8 + U32 : 2; // Bits 15:14 + U32 WDB_Ending_Error_Pointer : 6; // Bits 21:16 + U32 : 10; // Bits 31:22 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_STRUCT; + +typedef union { + struct { + U32 CKE_Override : 4; // Bits 3:0 + U32 : 4; // Bits 7:4 + U32 CKE_En_Start_Test_Sync : 1; // Bits 8:8 + U32 : 7; // Bits 15:9 + U32 CKE_On : 4; // Bits 19:16 + U32 : 12; // Bits 31:20 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_REUT_CH_MISC_CKE_CTRL_STRUCT; + +typedef union { + struct { + U32 ODT_Override : 4; // Bits 3:0 + U32 : 12; // Bits 15:4 + U32 ODT_On : 4; // Bits 19:16 + U32 : 11; // Bits 30:20 + U32 MPR_Train_DDR_On : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_REUT_CH_MISC_ODT_CTRL_STRUCT; + +typedef union { + struct { + U32 Enable_CADB_on_Deselect : 1; // Bits 0:0 + U32 Enable_CADB_Always_On : 1; // Bits 1:1 + U32 CMD_Deselect_Start : 4; // Bits 5:2 + U32 CMD_Deselect_Stop : 4; // Bits 9:6 + U32 Lane_Deselect_Enable : 4; // Bits 13:10 + U32 CAS_Select_Enable : 2; // Bits 15:14 + U32 ACT_Select_Enable : 2; // Bits 17:16 + U32 PRE_Select_Enable : 2; // Bits 19:18 + U32 Save_Current_Seed : 4; // Bits 23:20 + U32 Reload_Starting_Seed : 4; // Bits 27:24 + U32 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_STRUCT; + +typedef union { + struct { + U32 MRS_Gap : 3; // Bits 2:0 + U32 : 5; // Bits 7:3 + U32 CADB_MRS_Start_Pointer : 3; // Bits 10:8 + U32 : 5; // Bits 15:11 + U32 CADB_MRS_End_Pointer : 3; // Bits 18:16 + U32 : 5; // Bits 23:19 + U32 CADB_MRS_Current_Pointer : 3; // Bits 26:24 + U32 : 5; // Bits 31:27 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MRS_STRUCT; + +typedef union { + struct { + U32 Mux0_Control : 2; // Bits 1:0 + U32 : 2; // Bits 3:2 + U32 Mux1_Control : 2; // Bits 5:4 + U32 : 2; // Bits 7:6 + U32 Mux2_Control : 2; // Bits 9:8 + U32 : 6; // Bits 15:10 + U32 Select_Mux0_Control : 2; // Bits 17:16 + U32 : 2; // Bits 19:18 + U32 Select_Mux1_Control : 2; // Bits 21:20 + U32 : 2; // Bits 23:22 + U32 Select_Mux2_Control : 2; // Bits 25:24 + U32 : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_CTRL_STRUCT; + +typedef union { + struct { + U32 Pattern_Buffer : 16; // Bits 15:0 + U32 : 16; // Bits 31:16 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_PB_0_STRUCT; + +typedef union { + struct { + U32 Pattern_Buffer : 16; // Bits 15:0 + U32 : 16; // Bits 31:16 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_PB_1_STRUCT; + +typedef union { + struct { + U32 Pattern_Buffer : 16; // Bits 15:0 + U32 : 16; // Bits 31:16 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_PB_2_STRUCT; + +typedef union { + struct { + U32 L_data_select : 1; // Bits 0:0 + U32 Enable_Sweep_Frequency : 1; // Bits 1:1 + U32 : 6; // Bits 7:2 + U32 L_counter : 8; // Bits 15:8 + U32 M_counter : 8; // Bits 23:16 + U32 N_counter : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_STRUCT; + +typedef union { + struct { + U32 CADB_Write_Pointer : 3; // Bits 2:0 + U32 : 29; // Bits 31:3 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_REUT_CH_PAT_CADB_WRITE_POINTER_STRUCT; + +typedef union { + struct { + U32 CADB_Data_Address : 16; // Bits 15:0 + U32 : 8; // Bits 23:16 + U32 CADB_Data_Bank : 3; // Bits 26:24 + U32 : 5; // Bits 31:27 + U32 CADB_Data_CS : 4; // Bits 35:32 + U32 : 4; // Bits 39:36 + U32 CADB_Data_Control : 3; // Bits 42:40 + U32 : 5; // Bits 47:43 + U32 CADB_Data_ODT : 4; // Bits 51:48 + U32 : 4; // Bits 55:52 + U32 CADB_Data_CKE : 4; // Bits 59:56 + U32 : 4; // Bits 63:60 + } Bits; + U64 Data; + U32 Data32[2]; + U16 Data16[4]; + U8 Data8[8]; +} MCHBAR_CH0_CR_REUT_CH_PAT_CADB_PROG_STRUCT; + +typedef union { + struct { + U32 Pattern_Buffer : 16; // Bits 15:0 + U32 : 16; // Bits 31:16 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_0_STRUCT; + +typedef union { + struct { + U32 Pattern_Buffer : 16; // Bits 15:0 + U32 : 16; // Bits 31:16 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_1_STRUCT; + +typedef union { + struct { + U32 Pattern_Buffer : 16; // Bits 15:0 + U32 : 16; // Bits 31:16 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_2_STRUCT; + +typedef union { + struct { + U32 WDB_Increment_Rate : 5; // Bits 4:0 + U32 WDB_Increment_Scale : 1; // Bits 5:5 + U32 : 2; // Bits 7:6 + U32 WDB_Start_Pointer : 6; // Bits 13:8 + U32 : 2; // Bits 15:14 + U32 WDB_End_Pointer : 6; // Bits 21:16 + U32 : 10; // Bits 31:22 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_CTRL_STRUCT; + +typedef union { + struct { + U32 Refresh_Rank_Mask : 4; // Bits 3:0 + U32 : 4; // Bits 7:4 + U32 RefZQ_En_Start_Test_Sync : 1; // Bits 8:8 + U32 : 22; // Bits 30:9 + U32 Panic_Refresh_Only : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_REUT_CH_MISC_REFRESH_CTRL_STRUCT; + +typedef union { + struct { + U32 ZQ_Rank_Mask : 4; // Bits 3:0 + U32 : 27; // Bits 30:4 + U32 Always_Do_ZQ : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_REUT_CH_MISC_ZQ_CTRL_STRUCT; + +#ifdef ULT_FLAG +typedef union { + struct { + U32 Rank_0_x32 : 1; // Bits 0:0 + U32 Rank_1_x32 : 1; // Bits 1:1 + U32 Rank_2_x32 : 1; // Bits 2:2 + U32 Rank_3_x32 : 1; // Bits 3:3 + U32 LPDDR2 : 1; // Bits 4:4 + U32 : 3; // Bits 7:5 + U32 MR4_PERIOD : 16; // Bits 23:8 + U32 : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_LPDDR_MR_PARAMS_STRUCT; + +typedef union { + struct { + U32 Address : 8; // Bits 7:0 + U32 Data : 8; // Bits 15:8 + U32 Rank : 2; // Bits 17:16 + U32 Write : 1; // Bits 18:18 + U32 Init_MRW : 1; // Bits 19:19 + U32 : 11; // Bits 30:20 + U32 Busy : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_LPDDR_MR_COMMAND_STRUCT; + +typedef union { + struct { + U32 Device_0 : 8; // Bits 7:0 + U32 Device_1 : 8; // Bits 15:8 + U32 Device_2 : 8; // Bits 23:16 + U32 Device_3 : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_LPDDR_MR_RESULT_STRUCT; + +typedef union { + struct { + U32 Rank_0 : 3; // Bits 2:0 + U32 : 5; // Bits 7:3 + U32 Rank_1 : 3; // Bits 10:8 + U32 : 5; // Bits 15:11 + U32 Rank_2 : 3; // Bits 18:16 + U32 : 5; // Bits 23:19 + U32 Rank_3 : 3; // Bits 26:24 + U32 : 5; // Bits 31:27 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_LPDDR_MR4_RANK_TEMPERATURE_STRUCT; + +typedef union { + struct { + U32 Bit_0 : 3; // Bits 2:0 + U32 : 1; // Bits 3:3 + U32 Bit_1 : 3; // Bits 6:4 + U32 : 1; // Bits 7:7 + U32 Bit_2 : 3; // Bits 10:8 + U32 : 1; // Bits 11:11 + U32 Bit_16 : 3; // Bits 14:12 + U32 : 1; // Bits 15:15 + U32 Bit_17 : 3; // Bits 18:16 + U32 : 1; // Bits 19:19 + U32 Bit_18 : 3; // Bits 22:20 + U32 : 1; // Bits 23:23 + U32 Byte_0 : 3; // Bits 26:24 + U32 : 1; // Bits 27:27 + U32 Byte_2 : 3; // Bits 30:28 + U32 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_DESWIZZLE_LOW_STRUCT; + +typedef union { + struct { + U32 Bit_32 : 3; // Bits 2:0 + U32 : 1; // Bits 3:3 + U32 Bit_33 : 3; // Bits 6:4 + U32 : 1; // Bits 7:7 + U32 Bit_34 : 3; // Bits 10:8 + U32 : 1; // Bits 11:11 + U32 Bit_48 : 3; // Bits 14:12 + U32 : 1; // Bits 15:15 + U32 Bit_49 : 3; // Bits 18:16 + U32 : 1; // Bits 19:19 + U32 Bit_50 : 3; // Bits 22:20 + U32 : 1; // Bits 23:23 + U32 Byte_4 : 3; // Bits 26:24 + U32 : 1; // Bits 27:27 + U32 Byte_6 : 3; // Bits 30:28 + U32 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_DESWIZZLE_HIGH_STRUCT; +#endif // ULT_FLAG + +typedef union { + struct { + U32 Ref_Interval : 11; // Bits 10:0 + U32 Ref_Stagger_En : 1; // Bits 11:11 + U32 Ref_Stagger_Mode : 1; // Bits 12:12 + U32 Disable_Stolen_Refresh : 1; // Bits 13:13 + U32 En_Ref_Type_Display : 1; // Bits 14:14 + U32 : 17; // Bits 31:15 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_MC_REFRESH_STAGGER_STRUCT; + +typedef union { + struct { + U32 ZQCS_period : 8; // Bits 7:0 + U32 tZQCS : 8; // Bits 15:8 + U32 : 16; // Bits 31:16 + } Bits; +#ifdef ULT_FLAG + struct { + U32 ZQCS_period : 10; // Bits 9:0 + U32 tZQCS : 10; // Bits 19:10 + U32 : 12; // Bits 31:20 + } UltBits; +#endif // ULT_FLAG + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_TC_ZQCAL_STRUCT; + +typedef union { + struct { + U32 OREF_RI : 8; // Bits 7:0 + U32 Refresh_HP_WM : 4; // Bits 11:8 + U32 Refresh_panic_wm : 4; // Bits 15:12 + U32 : 16; // Bits 31:16 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_TC_RFP_STRUCT; + +typedef union { + struct { + U32 tREFI : 16; // Bits 15:0 + U32 tRFC : 9; // Bits 24:16 + U32 tREFIx9 : 7; // Bits 31:25 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_TC_RFTP_STRUCT; + +typedef union { + struct { + U32 MR2_sh_low : 6; // Bits 5:0 + U32 SRT_avail : 2; // Bits 7:6 + U32 MR2_sh_high : 3; // Bits 10:8 + U32 : 3; // Bits 13:11 + U32 Addr_bit_swizzle : 2; // Bits 15:14 + U32 : 16; // Bits 31:16 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_TC_MR2_SHADDOW_STRUCT; + +typedef union { + struct { + U32 Rank_occupancy : 4; // Bits 3:0 + U32 : 28; // Bits 31:4 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_MC_INIT_STATE_STRUCT; + +typedef union { + struct { + U32 tXSDLL : 12; // Bits 11:0 + U32 tXS_offset : 4; // Bits 15:12 + U32 tZQOPER : 10; // Bits 25:16 + U32 : 2; // Bits 27:26 + U32 tMOD : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_TC_SRFTP_STRUCT; + +typedef union { + struct { + U32 VISAByteSel : 3; // Bits 2:0 + U32 : 29; // Bits 31:3 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_WDB_VISA_SEL_STRUCT; + +typedef union { + struct { + U32 FASTADDR : 12; // Bits 11:0 + U32 : 4; // Bits 15:12 + U32 ADDREN : 1; // Bits 16:16 + U32 SEQEN : 1; // Bits 17:17 + U32 POL0 : 1; // Bits 18:18 + U32 POL1 : 1; // Bits 19:19 + U32 CMDA : 4; // Bits 23:20 + U32 CMDB : 4; // Bits 27:24 + U32 CMDC : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_DCLK_LDAT_PDAT_STRUCT; + +typedef union { + struct { + U32 BANKSEL : 4; // Bits 3:0 + U32 : 1; // Bits 4:4 + U32 ARRAYSEL : 5; // Bits 9:5 + U32 CMP : 1; // Bits 10:10 + U32 REP : 1; // Bits 11:11 + U32 DWORD : 4; // Bits 15:12 + U32 MODE : 2; // Bits 17:16 + U32 MPMAP : 6; // Bits 23:18 + U32 MPBOFFSET : 4; // Bits 27:24 + U32 STAGE_EN : 1; // Bits 28:28 + U32 SHADOW : 2; // Bits 30:29 + U32 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_DCLK_LDAT_SDAT_STRUCT; + +typedef union { + struct { + U32 DATOUT : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_DCLK_LDAT_DATAOUT_STRUCT; + +typedef union { + struct { + U32 DATIN : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_DCLK_LDAT_DATAIN_0_STRUCT; + +typedef union { + struct { + U32 FASTADDR : 12; // Bits 11:0 + U32 : 4; // Bits 15:12 + U32 ADDREN : 1; // Bits 16:16 + U32 SEQEN : 1; // Bits 17:17 + U32 POL0 : 1; // Bits 18:18 + U32 POL1 : 1; // Bits 19:19 + U32 CMDA : 4; // Bits 23:20 + U32 CMDB : 4; // Bits 27:24 + U32 CMDC : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_QCLK_LDAT_PDAT_STRUCT; + +typedef union { + struct { + U32 BANKSEL : 4; // Bits 3:0 + U32 : 1; // Bits 4:4 + U32 ARRAYSEL : 5; // Bits 9:5 + U32 CMP : 1; // Bits 10:10 + U32 REP : 1; // Bits 11:11 + U32 DWORD : 4; // Bits 15:12 + U32 MODE : 2; // Bits 17:16 + U32 MPMAP : 6; // Bits 23:18 + U32 MPBOFFSET : 4; // Bits 27:24 + U32 STAGE_EN : 1; // Bits 28:28 + U32 SHADOW : 2; // Bits 30:29 + U32 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_QCLK_LDAT_SDAT_STRUCT; + +typedef union { + struct { + U32 DATOUT : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_QCLK_LDAT_DATAOUT_STRUCT; + +typedef union { + struct { + U32 DATIN : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_QCLK_LDAT_DATAIN_0_STRUCT; + +typedef union { + struct { + U32 DATIN : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_QCLK_LDAT_DATAIN_1_STRUCT; + +typedef union { + struct { + U32 RPQ_disable : 28; // Bits 27:0 + U32 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_QUEUE_ENTRY_DISABLE_RPQ_STRUCT; + +typedef union { + struct { + U32 WPQ_disable : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_QUEUE_ENTRY_DISABLE_WPQ_STRUCT; + +typedef union { + struct { + U32 DIMM0_IDLE_ENERGY : 6; // Bits 5:0 + U32 : 2; // Bits 7:6 + U32 DIMM1_IDLE_ENERGY : 6; // Bits 13:8 + U32 : 18; // Bits 31:14 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_PM_DIMM_IDLE_ENERGY_STRUCT; + +typedef union { + struct { + U32 DIMM0_PD_ENERGY : 6; // Bits 5:0 + U32 : 2; // Bits 7:6 + U32 DIMM1_PD_ENERGY : 6; // Bits 13:8 + U32 : 18; // Bits 31:14 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_PM_DIMM_PD_ENERGY_STRUCT; + +typedef union { + struct { + U32 DIMM0_ACT_ENERGY : 8; // Bits 7:0 + U32 DIMM1_ACT_ENERGY : 8; // Bits 15:8 + U32 : 16; // Bits 31:16 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_PM_DIMM_ACT_ENERGY_STRUCT; + +typedef union { + struct { + U32 DIMM0_RD_ENERGY : 8; // Bits 7:0 + U32 DIMM1_RD_ENERGY : 8; // Bits 15:8 + U32 : 16; // Bits 31:16 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_PM_DIMM_RD_ENERGY_STRUCT; + +typedef union { + struct { + U32 DIMM0_WR_ENERGY : 8; // Bits 7:0 + U32 DIMM1_WR_ENERGY : 8; // Bits 15:8 + U32 : 16; // Bits 31:16 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_PM_DIMM_WR_ENERGY_STRUCT; + +typedef union { + struct { + U32 CKE_MIN : 8; // Bits 7:0 + U32 CKE_MIN_DEFEATURE : 1; // Bits 8:8 + U32 : 23; // Bits 31:9 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_PM_THRT_CKE_MIN_STRUCT; + +typedef union { + struct { + U32 ODT : 4; // Bits 3:0 + U32 Web : 1; // Bits 4:4 + U32 CASb : 1; // Bits 5:5 + U32 RASb : 1; // Bits 6:6 + U32 CSb : 4; // Bits 10:7 + U32 CKE : 4; // Bits 14:11 + U32 MA : 16; // Bits 30:15 + U32 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_ODLAT_CMD_MATCH0_STRUCT; + +typedef union { + struct { + U32 ODT : 4; // Bits 3:0 + U32 Web : 1; // Bits 4:4 + U32 CASb : 1; // Bits 5:5 + U32 RASb : 1; // Bits 6:6 + U32 CSb : 4; // Bits 10:7 + U32 CKE : 4; // Bits 14:11 + U32 MA : 16; // Bits 30:15 + U32 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_ODLAT_CMD_MATCH1_STRUCT; + +typedef union { + struct { + U32 ODT : 4; // Bits 3:0 + U32 Web : 1; // Bits 4:4 + U32 CASb : 1; // Bits 5:5 + U32 RASb : 1; // Bits 6:6 + U32 CSb : 4; // Bits 10:7 + U32 CKE : 4; // Bits 14:11 + U32 MA : 16; // Bits 30:15 + U32 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_ODLAT_CMD_MATCH2_STRUCT; + +typedef union { + struct { + U32 ODT : 4; // Bits 3:0 + U32 Web : 1; // Bits 4:4 + U32 CASb : 1; // Bits 5:5 + U32 RASb : 1; // Bits 6:6 + U32 CSb : 4; // Bits 10:7 + U32 CKE : 4; // Bits 14:11 + U32 MA : 16; // Bits 30:15 + U32 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_ODLAT_CMD_MATCH3_STRUCT; + +typedef union { + struct { + U32 ODT : 4; // Bits 3:0 + U32 Web : 1; // Bits 4:4 + U32 CASb : 1; // Bits 5:5 + U32 RASb : 1; // Bits 6:6 + U32 CSb : 4; // Bits 10:7 + U32 CKE : 4; // Bits 14:11 + U32 MA : 16; // Bits 30:15 + U32 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_ODLAT_CMD_MASK0_STRUCT; + +typedef union { + struct { + U32 ODT : 4; // Bits 3:0 + U32 Web : 1; // Bits 4:4 + U32 CASb : 1; // Bits 5:5 + U32 RASb : 1; // Bits 6:6 + U32 CSb : 4; // Bits 10:7 + U32 CKE : 4; // Bits 14:11 + U32 MA : 16; // Bits 30:15 + U32 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_ODLAT_CMD_MASK1_STRUCT; + +typedef union { + struct { + U32 ODT : 4; // Bits 3:0 + U32 Web : 1; // Bits 4:4 + U32 CASb : 1; // Bits 5:5 + U32 RASb : 1; // Bits 6:6 + U32 CSb : 4; // Bits 10:7 + U32 CKE : 4; // Bits 14:11 + U32 MA : 16; // Bits 30:15 + U32 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_ODLAT_CMD_MASK2_STRUCT; + +typedef union { + struct { + U32 ODT : 4; // Bits 3:0 + U32 Web : 1; // Bits 4:4 + U32 CASb : 1; // Bits 5:5 + U32 RASb : 1; // Bits 6:6 + U32 CSb : 4; // Bits 10:7 + U32 CKE : 4; // Bits 14:11 + U32 MA : 16; // Bits 30:15 + U32 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_ODLAT_CMD_MASK3_STRUCT; + +typedef union { + struct { + U32 BankMatch0 : 3; // Bits 2:0 + U32 BankMatch1 : 3; // Bits 5:3 + U32 BankMatch2 : 3; // Bits 8:6 + U32 BankMatch3 : 3; // Bits 11:9 + U32 BankMask0 : 3; // Bits 14:12 + U32 BankMask1 : 3; // Bits 17:15 + U32 BankMask2 : 3; // Bits 20:18 + U32 BankMask3 : 3; // Bits 23:21 + U32 : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_ODLAT_CMD_BANK_STRUCT; + +typedef union { + struct { + U32 InputMatch : 4; // Bits 3:0 + U32 InputInvert : 4; // Bits 7:4 + U32 CountMatches : 1; // Bits 8:8 + U32 CounterThreshold : 15; // Bits 23:9 + U32 CounterAction : 2; // Bits 25:24 + U32 CounterNextState : 2; // Bits 27:26 + U32 MatchAction : 2; // Bits 29:28 + U32 MatchNextState : 2; // Bits 31:30 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL0_STRUCT; + +typedef union { + struct { + U32 InputMatch : 4; // Bits 3:0 + U32 InputInvert : 4; // Bits 7:4 + U32 CountMatches : 1; // Bits 8:8 + U32 CounterThreshold : 15; // Bits 23:9 + U32 CounterAction : 2; // Bits 25:24 + U32 CounterNextState : 2; // Bits 27:26 + U32 MatchAction : 2; // Bits 29:28 + U32 MatchNextState : 2; // Bits 31:30 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL1_STRUCT; + +typedef union { + struct { + U32 InputMatch : 4; // Bits 3:0 + U32 InputInvert : 4; // Bits 7:4 + U32 CountMatches : 1; // Bits 8:8 + U32 CounterThreshold : 15; // Bits 23:9 + U32 CounterAction : 2; // Bits 25:24 + U32 CounterNextState : 2; // Bits 27:26 + U32 MatchAction : 2; // Bits 29:28 + U32 MatchNextState : 2; // Bits 31:30 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL2_STRUCT; + +typedef union { + struct { + U32 InputMatch : 4; // Bits 3:0 + U32 InputInvert : 4; // Bits 7:4 + U32 CountMatches : 1; // Bits 8:8 + U32 CounterThreshold : 15; // Bits 23:9 + U32 CounterAction : 2; // Bits 25:24 + U32 CounterNextState : 2; // Bits 27:26 + U32 MatchAction : 2; // Bits 29:28 + U32 MatchNextState : 2; // Bits 31:30 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL3_STRUCT; + +typedef union { + struct { + U32 TriggerBlockEnable : 1; // Bits 0:0 + U32 GlobalCounterThreshold : 16; // Bits 16:1 + U32 : 15; // Bits 31:17 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_ODLAT_SEQ_GLOBAL_STRUCT; + +typedef union { + struct { + U32 WMM_Enter : 8; // Bits 7:0 + U32 WMM_Exit : 8; // Bits 15:8 + U32 WPQ_IS : 8; // Bits 23:16 + U32 Starve_count : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_SC_WDBWM_STRUCT; + +typedef union { + struct { + U32 Data : 18; // Bits 17:0 + U32 : 13; // Bits 30:18 + U32 VORANGE : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_VISA_CTL_MCMNTS_STRUCT; + +typedef union { + struct { + U32 tRCD : 5; // Bits 4:0 + U32 tRP : 5; // Bits 9:5 + U32 tRAS : 6; // Bits 15:10 + U32 tRDPRE : 4; // Bits 19:16 + U32 tWRPRE : 6; // Bits 25:20 + U32 tRRD : 4; // Bits 29:26 + U32 tRPab_ext : 2; // Bits 31:30 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_TC_BANK_STRUCT; + +typedef union { + struct { + U32 tCKE : 4; // Bits 3:0 + U32 tFAW : 8; // Bits 11:4 + U32 tRDRD : 3; // Bits 14:12 + U32 tRDRD_dr : 4; // Bits 18:15 + U32 tRDRD_dd : 4; // Bits 22:19 + U32 tRDPDEN : 5; // Bits 27:23 + U32 : 1; // Bits 28:28 + U32 CMD_3st : 1; // Bits 29:29 + U32 CMD_stretch : 2; // Bits 31:30 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_TC_BANK_RANK_A_STRUCT; + +typedef union { + struct { + U32 tWRRD : 6; // Bits 5:0 + U32 tWRRD_dr : 4; // Bits 9:6 + U32 tWRRD_dd : 4; // Bits 13:10 + U32 tWRWR : 3; // Bits 16:14 + U32 tWRWR_dr : 4; // Bits 20:17 + U32 tWRWR_dd : 4; // Bits 24:21 + U32 tWRPDEN : 6; // Bits 30:25 + U32 Dec_WRD : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_TC_BANK_RANK_B_STRUCT; + +typedef union { + struct { + U32 tXPDLL : 6; // Bits 5:0 + U32 tXP : 4; // Bits 9:6 + U32 TAONPD : 4; // Bits 13:10 + U32 tRDWR : 5; // Bits 18:14 + U32 tRDWR_dr : 5; // Bits 23:19 + U32 tRDWR_dd : 5; // Bits 28:24 + U32 : 3; // Bits 31:29 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_TC_BANK_RANK_C_STRUCT; + +typedef union { + struct { + U32 enable_cmd_rate_limit : 1; // Bits 0:0 + U32 cmd_rate_limit : 3; // Bits 3:1 + U32 reset_on_command : 4; // Bits 7:4 + U32 reset_delay : 4; // Bits 11:8 + U32 ck_to_cke_delay : 2; // Bits 13:12 + U32 spare : 17; // Bits 30:14 + U32 init_mrw_2n_cs : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_CMD_RATE_STRUCT; + +typedef union { + struct { + U32 tCL : 5; // Bits 4:0 + U32 tWCL : 5; // Bits 9:5 + U32 tCPDED : 2; // Bits 11:10 + U32 tPRPDEN : 2; // Bits 13:12 + U32 Odt_Read_Delay : 3; // Bits 16:14 + U32 Odt_Read_Duration : 2; // Bits 18:17 + U32 Odt_Write_Duration : 2; // Bits 20:19 + U32 : 11; // Bits 31:21 + } Bits; +#ifdef ULT_FLAG + struct { + U32 tCL : 5; // Bits 4:0 + U32 tWCL : 5; // Bits 9:5 + U32 tCPDED : 2; // Bits 11:10 + U32 tPRPDEN : 2; // Bits 13:12 + U32 Odt_Read_Delay : 3; // Bits 16:14 + U32 Odt_Read_Duration : 2; // Bits 18:17 + U32 Odt_Write_Duration : 3; // Bits 21:19 + U32 Odt_Write_Delay : 3; // Bits 24:22 + U32 Odt_Always_Rank0 : 1; // Bits 25:25 + U32 cmd_delay : 2; // Bits 27:26 + U32 : 4; // Bits 31:28 + } UltBits; +#endif // ULT_FLAG + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_TC_BANK_RANK_D_STRUCT; + +typedef union { + struct { + U32 dis_opp_cas : 1; // Bits 0:0 + U32 dis_opp_is_cas : 1; // Bits 1:1 + U32 dis_opp_ras : 1; // Bits 2:2 + U32 dis_opp_is_ras : 1; // Bits 3:3 + U32 dis_1c_byp : 1; // Bits 4:4 + U32 dis_2c_byp : 1; // Bits 5:5 + U32 dis_deprd_opt : 1; // Bits 6:6 + U32 dis_pt_it : 1; // Bits 7:7 + U32 dis_prcnt_ring : 1; // Bits 8:8 + U32 dis_prcnt_sa : 1; // Bits 9:9 + U32 dis_blkr_ph : 1; // Bits 10:10 + U32 dis_blkr_pe : 1; // Bits 11:11 + U32 dis_blkr_pm : 1; // Bits 12:12 + U32 dis_odt : 1; // Bits 13:13 + U32 OE_alw_off : 1; // Bits 14:14 + U32 : 1; // Bits 15:15 + U32 dis_aom : 1; // Bits 16:16 + U32 block_rpq : 1; // Bits 17:17 + U32 block_wpq : 1; // Bits 18:18 + U32 invert_align : 1; // Bits 19:19 + U32 dis_write_gap : 1; // Bits 20:20 + U32 dis_zq : 1; // Bits 21:21 + U32 dis_tt : 1; // Bits 22:22 + U32 dis_opp_ref : 1; // Bits 23:23 + U32 Long_ZQ : 1; // Bits 24:24 + U32 dis_srx_zq : 1; // Bits 25:25 + U32 Serialize_ZQ : 1; // Bits 26:26 + U32 ZQ_fast_exec : 1; // Bits 27:27 + U32 Dis_DriveNop : 1; // Bits 28:28 + U32 Pres_WDB_Ent : 1; // Bits 29:29 + U32 dis_clk_gate : 1; // Bits 30:30 + U32 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_SCHED_CBIT_STRUCT; + +typedef union { + struct { + U32 Lat_R0D0 : 6; // Bits 5:0 + U32 : 2; // Bits 7:6 + U32 Lat_R1D0 : 6; // Bits 13:8 + U32 : 2; // Bits 15:14 + U32 Lat_R0D1 : 6; // Bits 21:16 + U32 : 2; // Bits 23:22 + U32 Lat_R1D1 : 6; // Bits 29:24 + U32 : 2; // Bits 31:30 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_SC_ROUNDT_LAT_STRUCT; + +typedef union { + struct { + U32 IOLAT_R0D0 : 4; // Bits 3:0 + U32 IOLAT_R1D0 : 4; // Bits 7:4 + U32 IOLAT_R0D1 : 4; // Bits 11:8 + U32 IOLAT_R1D1 : 4; // Bits 15:12 + U32 RT_IOCOMP : 6; // Bits 21:16 + U32 : 8; // Bits 29:22 + U32 three_channels : 1; // Bits 30:30 + U32 DIS_RT_CLK_GATE : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_SC_IO_LATENCY_STRUCT; + +typedef union { + struct { + U32 DATA : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_ROUND_TRIP_DFT_DATA_STRUCT; + +typedef union { + struct { + U32 WDAR : 1; // Bits 0:0 + U32 safe_mask_sel : 3; // Bits 3:1 + U32 force_rcv_en : 1; // Bits 4:4 + U32 : 3; // Bits 7:5 + U32 DDR_QUAL : 2; // Bits 9:8 + U32 Qual_length : 2; // Bits 11:10 + U32 WDB_Block_En : 1; // Bits 12:12 + U32 RT_DFT_READ_PTR : 4; // Bits 16:13 + U32 RT_DFT_READ_ENABLE : 1; // Bits 17:17 + U32 RT_DFT_READ_SEL_ADDR : 1; // Bits 18:18 + U32 : 13; // Bits 31:19 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_DFT_MISC_STRUCT; + +typedef union { + struct { + U32 ECC : 8; // Bits 7:0 + U32 RRD_DFT_Mode : 2; // Bits 9:8 + U32 LFSR_Seed_Index : 5; // Bits 14:10 + U32 Inversion_Mode : 1; // Bits 15:15 + U32 : 16; // Bits 31:16 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_READ_RETURN_DFT_STRUCT; + +typedef union { + struct { + U32 dis_imph_error : 1; // Bits 0:0 + U32 : 7; // Bits 7:1 + U32 dis_async_odt : 1; // Bits 8:8 + U32 : 23; // Bits 31:9 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_SCHED_SECOND_CBIT_STRUCT; + +typedef union { + struct { + U32 Mux0_Control : 2; // Bits 1:0 + U32 : 1; // Bits 2:2 + U32 Mux1_Control : 2; // Bits 4:3 + U32 : 1; // Bits 5:5 + U32 Mux2_Control : 2; // Bits 7:6 + U32 : 6; // Bits 13:8 + U32 ECC_Replace_Byte_Control : 1; // Bits 14:14 + U32 ECC_Data_Source_Sel : 1; // Bits 15:15 + U32 Save_LFSR_Seed_Rate : 6; // Bits 21:16 + U32 : 2; // Bits 23:22 + U32 Reload_LFSR_Seed_Rate : 3; // Bits 26:24 + U32 : 5; // Bits 31:27 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_STRUCT; + +typedef union { + struct { + U32 WDB_Current_Read_Pointer : 6; // Bits 5:0 + U32 : 26; // Bits 31:6 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_RD_STATUS_STRUCT; + +typedef union { + struct { + U32 Pattern_Buffer : 24; // Bits 23:0 + U32 : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_0_STRUCT; + +typedef union { + struct { + U32 Pattern_Buffer : 24; // Bits 23:0 + U32 : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_1_STRUCT; + +typedef union { + struct { + U32 Pattern_Buffer : 24; // Bits 23:0 + U32 : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_2_STRUCT; + +typedef union { + struct { + U32 Pattern_Buffer : 24; // Bits 23:0 + U32 : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_0_STRUCT; + +typedef union { + struct { + U32 Pattern_Buffer : 24; // Bits 23:0 + U32 : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_1_STRUCT; + +typedef union { + struct { + U32 Pattern_Buffer : 24; // Bits 23:0 + U32 : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_2_STRUCT; + +typedef union { + struct { + U32 Pattern_Buffer : 24; // Bits 23:0 + U32 : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_0_STRUCT; + +typedef union { + struct { + U32 Pattern_Buffer : 24; // Bits 23:0 + U32 : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_1_STRUCT; + +typedef union { + struct { + U32 Pattern_Buffer : 24; // Bits 23:0 + U32 : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_2_STRUCT; + +typedef union { + struct { + U32 Pattern_Buffer : 24; // Bits 23:0 + U32 : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_0_STRUCT; + +typedef union { + struct { + U32 Pattern_Buffer : 24; // Bits 23:0 + U32 : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_1_STRUCT; + +typedef union { + struct { + U32 Pattern_Buffer : 24; // Bits 23:0 + U32 : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_2_STRUCT; + +typedef union { + struct { + U32 L_data_select : 1; // Bits 0:0 + U32 Enable_Sweep_Frequency : 1; // Bits 1:1 + U32 : 6; // Bits 7:2 + U32 L_counter : 8; // Bits 15:8 + U32 M_counter : 8; // Bits 23:16 + U32 N_counter : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_STRUCT; + +typedef union { + struct { + U32 ECC_Inv_or_DC_Enable : 8; // Bits 7:0 + U32 : 8; // Bits 15:8 + U32 Inv_or_DC_Shift_Rate : 4; // Bits 19:16 + U32 DC_Polarity_Control : 1; // Bits 20:20 + U32 : 9; // Bits 29:21 + U32 Inv_or_DC_Control : 1; // Bits 30:30 + U32 Inv_or_DC_Shift_Enable : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_REUT_CH_PAT_WDB_INV_STRUCT; + +typedef union { + struct { + U64 Data_Inv_or_DC_Enable : 64; // Bits 63:0 + } Bits; + U64 Data; + U32 Data32[2]; + U16 Data16[4]; + U8 Data8[8]; +} MCHBAR_CH1_CR_REUT_CH_PAT_WDB_DATA_INV_STRUCT; + +typedef union { + struct { + U32 Stop_on_Nth_Error : 6; // Bits 5:0 + U32 : 6; // Bits 11:6 + U32 Stop_On_Error_Control : 2; // Bits 13:12 + U32 : 2; // Bits 15:14 + U32 Selective_Error_Enable_Chunk : 8; // Bits 23:16 + U32 Selective_Error_Enable_Cacheline : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_REUT_CH_ERR_CTL_STRUCT; + +typedef union { + struct { + U32 ECC_Error_Mask : 8; // Bits 7:0 + U32 : 24; // Bits 31:8 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_REUT_CH_ERR_ECC_MASK_STRUCT; + +typedef union { + struct { + U32 Stretch_mode : 2; // Bits 1:0 + U32 : 2; // Bits 3:2 + U32 STF : 3; // Bits 6:4 + U32 : 25; // Bits 31:7 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_STM_CONFIG_STRUCT; + +typedef union { + struct { + U32 Priority_count_ring : 10; // Bits 9:0 + U32 : 6; // Bits 15:10 + U32 Priority_count_SA : 10; // Bits 25:16 + U32 : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_SC_PR_CNT_CONFIG_STRUCT; + +typedef union { + struct { + U32 PCIT : 8; // Bits 7:0 + U32 : 24; // Bits 31:8 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_SC_PCIT_STRUCT; + +typedef union { + struct { + U32 PDWN_idle_counter : 12; // Bits 11:0 + U32 PDWN_mode : 4; // Bits 15:12 + U32 : 16; // Bits 31:16 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_PM_PDWN_CONFIG_STRUCT; + +typedef union { + struct { + U32 Count : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_ECC_INJECT_COUNT_STRUCT; + +typedef union { + struct { + U32 ECC4ANA_fill : 8; // Bits 7:0 + U32 ECC4ANA_trigger : 2; // Bits 9:8 + U32 ECC4ANA_BS : 1; // Bits 10:10 + U32 ECC_Inject : 3; // Bits 13:11 + U32 ECC_correction_disable : 1; // Bits 14:14 + U32 ECC4ANA_Inject : 1; // Bits 15:15 + U32 DIS_MCA_LOG : 1; // Bits 16:16 + U32 DIS_PCH_EVENT : 1; // Bits 17:17 + U32 DIS_PCIE_POISON : 1; // Bits 18:18 + U32 : 13; // Bits 31:19 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_ECC_DFT_STRUCT; + +typedef union { + struct { + U32 Data : 18; // Bits 17:0 + U32 : 13; // Bits 30:18 + U32 VORANGE : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_VISA_CTL_MCSCHEDS_STRUCT; + +typedef union { + struct { + U32 Data : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_VISA_XBAR_MCSCHEDS_STRUCT; + +typedef union { + struct { + U32 CERRSTS : 1; // Bits 0:0 + U32 MERRSTS : 1; // Bits 1:1 + U32 : 14; // Bits 15:2 + U32 ERRSYND : 8; // Bits 23:16 + U32 ERRCHUNK : 3; // Bits 26:24 + U32 ERRRANK : 2; // Bits 28:27 + U32 ERRBANK : 3; // Bits 31:29 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_ECCERRLOG0_STRUCT; + +typedef union { + struct { + U32 ERRROW : 16; // Bits 15:0 + U32 ERRCOL : 16; // Bits 31:16 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_ECCERRLOG1_STRUCT; + +typedef union { + struct { + U32 D0R0 : 2; // Bits 1:0 + U32 D0R1 : 2; // Bits 3:2 + U32 D1R0 : 2; // Bits 5:4 + U32 D1R1 : 2; // Bits 7:6 + U32 : 24; // Bits 31:8 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_SC_WR_ADD_DELAY_STRUCT; + +typedef union { + struct { + U32 Dis_Opp_rd : 1; // Bits 0:0 + U32 ACT_Enable : 1; // Bits 1:1 + U32 PRE_Enable : 1; // Bits 2:2 + U32 MAX_RPQ_Cas : 4; // Bits 6:3 + U32 : 25; // Bits 31:7 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_WMM_READ_CONFIG_STRUCT; + +typedef union { + struct { + U64 Data_Error_Mask : 64; // Bits 63:0 + } Bits; + U64 Data; + U32 Data32[2]; + U16 Data16[4]; + U8 Data8[8]; +} MCHBAR_CH1_CR_REUT_CH_ERR_DATA_MASK_STRUCT; + +typedef union { + struct { + U64 Data_Error_Status : 64; // Bits 63:0 + } Bits; + U64 Data; + U32 Data32[2]; + U16 Data16[4]; + U8 Data8[8]; +} MCHBAR_CH1_CR_REUT_CH_ERR_DATA_STATUS_STRUCT; + +typedef union { + struct { + U32 ECC_Error_Status : 8; // Bits 7:0 + U32 Chunk_Error_Status : 8; // Bits 15:8 + U32 Rank_Error_Status : 4; // Bits 19:16 + U32 : 12; // Bits 31:20 + U32 Byte_Group_Error_Status : 9; // Bits 40:32 + U32 : 11; // Bits 51:41 + U32 WDB_Rd_Chunk_Num_Status : 3; // Bits 54:52 + U32 : 1; // Bits 55:55 + U32 Nth_Error : 6; // Bits 61:56 + U32 : 2; // Bits 63:62 + } Bits; + U64 Data; + U32 Data32[2]; + U16 Data16[4]; + U8 Data8[8]; +} MCHBAR_CH1_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_STRUCT; + +typedef union { + struct { + U32 Counter_Pointer : 7; // Bits 6:0 + U32 Counter_Control : 2; // Bits 8:7 + U32 : 23; // Bits 31:9 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_0_STRUCT; + +typedef union { + struct { + U32 Counter_Pointer : 7; // Bits 6:0 + U32 Counter_Control : 2; // Bits 8:7 + U32 : 23; // Bits 31:9 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_1_STRUCT; + +typedef union { + struct { + U32 Counter_Pointer : 7; // Bits 6:0 + U32 Counter_Control : 2; // Bits 8:7 + U32 : 23; // Bits 31:9 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_2_STRUCT; + +typedef union { + struct { + U32 Counter_Pointer : 7; // Bits 6:0 + U32 Counter_Control : 2; // Bits 8:7 + U32 : 23; // Bits 31:9 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_3_STRUCT; + +typedef union { + struct { + U32 Counter_Pointer : 7; // Bits 6:0 + U32 Counter_Control : 2; // Bits 8:7 + U32 : 23; // Bits 31:9 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_4_STRUCT; + +typedef union { + struct { + U32 Counter_Pointer : 7; // Bits 6:0 + U32 Counter_Control : 2; // Bits 8:7 + U32 : 23; // Bits 31:9 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_5_STRUCT; + +typedef union { + struct { + U32 Counter_Pointer : 7; // Bits 6:0 + U32 Counter_Control : 2; // Bits 8:7 + U32 : 23; // Bits 31:9 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_6_STRUCT; + +typedef union { + struct { + U32 Counter_Pointer : 7; // Bits 6:0 + U32 Counter_Control : 2; // Bits 8:7 + U32 : 23; // Bits 31:9 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_7_STRUCT; + +typedef union { + struct { + U32 Counter_Pointer : 7; // Bits 6:0 + U32 Counter_Control : 2; // Bits 8:7 + U32 : 23; // Bits 31:9 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_8_STRUCT; + +typedef union { + struct { + U32 Counter_Status : 23; // Bits 22:0 + U32 : 9; // Bits 31:23 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_0_STRUCT; + +typedef union { + struct { + U32 Counter_Status : 23; // Bits 22:0 + U32 : 9; // Bits 31:23 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_1_STRUCT; + +typedef union { + struct { + U32 Counter_Status : 23; // Bits 22:0 + U32 : 9; // Bits 31:23 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_2_STRUCT; + +typedef union { + struct { + U32 Counter_Status : 23; // Bits 22:0 + U32 : 9; // Bits 31:23 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_3_STRUCT; + +typedef union { + struct { + U32 Counter_Status : 23; // Bits 22:0 + U32 : 9; // Bits 31:23 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_4_STRUCT; + +typedef union { + struct { + U32 Counter_Status : 23; // Bits 22:0 + U32 : 9; // Bits 31:23 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_5_STRUCT; + +typedef union { + struct { + U32 Counter_Status : 23; // Bits 22:0 + U32 : 9; // Bits 31:23 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_6_STRUCT; + +typedef union { + struct { + U32 Counter_Status : 23; // Bits 22:0 + U32 : 9; // Bits 31:23 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_7_STRUCT; + +typedef union { + struct { + U32 Counter_Status : 23; // Bits 22:0 + U32 : 9; // Bits 31:23 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_8_STRUCT; + +typedef union { + struct { + U32 Counter_Overflow_Status : 9; // Bits 8:0 + U32 : 23; // Bits 31:9 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_OVERFLOW_STATUS_STRUCT; + +typedef union { + struct { + U32 Column_Address : 10; // Bits 9:0 + U32 : 14; // Bits 23:10 + U32 Row_Address : 16; // Bits 39:24 + U32 : 8; // Bits 47:40 + U32 Bank_Address : 3; // Bits 50:48 + U32 : 5; // Bits 55:51 + U32 Rank_Address : 2; // Bits 57:56 + U32 : 6; // Bits 63:58 + } Bits; + U64 Data; + U32 Data32[2]; + U16 Data16[4]; + U8 Data8[8]; +} MCHBAR_CH1_CR_REUT_CH_ERROR_ADDR_STRUCT; + +typedef union { + struct { + U32 WDB_Current_Error_Pointer : 6; // Bits 5:0 + U32 : 26; // Bits 31:6 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_REUT_CH_ERR_WDB_CAPTURE_STATUS_STRUCT; + +typedef union { + struct { + U32 Enable_WDB_Error_Capture : 1; // Bits 0:0 + U32 : 7; // Bits 7:1 + U32 WDB_Starting_Error_Pointer : 6; // Bits 13:8 + U32 : 2; // Bits 15:14 + U32 WDB_Ending_Error_Pointer : 6; // Bits 21:16 + U32 : 10; // Bits 31:22 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_STRUCT; + +typedef union { + struct { + U32 CKE_Override : 4; // Bits 3:0 + U32 : 4; // Bits 7:4 + U32 CKE_En_Start_Test_Sync : 1; // Bits 8:8 + U32 : 7; // Bits 15:9 + U32 CKE_On : 4; // Bits 19:16 + U32 : 12; // Bits 31:20 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_REUT_CH_MISC_CKE_CTRL_STRUCT; + +typedef union { + struct { + U32 ODT_Override : 4; // Bits 3:0 + U32 : 12; // Bits 15:4 + U32 ODT_On : 4; // Bits 19:16 + U32 : 11; // Bits 30:20 + U32 MPR_Train_DDR_On : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_REUT_CH_MISC_ODT_CTRL_STRUCT; + +typedef union { + struct { + U32 Enable_CADB_on_Deselect : 1; // Bits 0:0 + U32 Enable_CADB_Always_On : 1; // Bits 1:1 + U32 CMD_Deselect_Start : 4; // Bits 5:2 + U32 CMD_Deselect_Stop : 4; // Bits 9:6 + U32 Lane_Deselect_Enable : 4; // Bits 13:10 + U32 CAS_Select_Enable : 2; // Bits 15:14 + U32 ACT_Select_Enable : 2; // Bits 17:16 + U32 PRE_Select_Enable : 2; // Bits 19:18 + U32 Save_Current_Seed : 4; // Bits 23:20 + U32 Reload_Starting_Seed : 4; // Bits 27:24 + U32 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_STRUCT; + +typedef union { + struct { + U32 MRS_Gap : 3; // Bits 2:0 + U32 : 5; // Bits 7:3 + U32 CADB_MRS_Start_Pointer : 3; // Bits 10:8 + U32 : 5; // Bits 15:11 + U32 CADB_MRS_End_Pointer : 3; // Bits 18:16 + U32 : 5; // Bits 23:19 + U32 CADB_MRS_Current_Pointer : 3; // Bits 26:24 + U32 : 5; // Bits 31:27 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MRS_STRUCT; + +typedef union { + struct { + U32 Mux0_Control : 2; // Bits 1:0 + U32 : 2; // Bits 3:2 + U32 Mux1_Control : 2; // Bits 5:4 + U32 : 2; // Bits 7:6 + U32 Mux2_Control : 2; // Bits 9:8 + U32 : 6; // Bits 15:10 + U32 Select_Mux0_Control : 2; // Bits 17:16 + U32 : 2; // Bits 19:18 + U32 Select_Mux1_Control : 2; // Bits 21:20 + U32 : 2; // Bits 23:22 + U32 Select_Mux2_Control : 2; // Bits 25:24 + U32 : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_CTRL_STRUCT; + +typedef union { + struct { + U32 Pattern_Buffer : 16; // Bits 15:0 + U32 : 16; // Bits 31:16 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_PB_0_STRUCT; + +typedef union { + struct { + U32 Pattern_Buffer : 16; // Bits 15:0 + U32 : 16; // Bits 31:16 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_PB_1_STRUCT; + +typedef union { + struct { + U32 Pattern_Buffer : 16; // Bits 15:0 + U32 : 16; // Bits 31:16 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_PB_2_STRUCT; + +typedef union { + struct { + U32 L_data_select : 1; // Bits 0:0 + U32 Enable_Sweep_Frequency : 1; // Bits 1:1 + U32 : 6; // Bits 7:2 + U32 L_counter : 8; // Bits 15:8 + U32 M_counter : 8; // Bits 23:16 + U32 N_counter : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_STRUCT; + +typedef union { + struct { + U32 CADB_Write_Pointer : 3; // Bits 2:0 + U32 : 29; // Bits 31:3 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_REUT_CH_PAT_CADB_WRITE_POINTER_STRUCT; + +typedef union { + struct { + U32 CADB_Data_Address : 16; // Bits 15:0 + U32 : 8; // Bits 23:16 + U32 CADB_Data_Bank : 3; // Bits 26:24 + U32 : 5; // Bits 31:27 + U32 CADB_Data_CS : 4; // Bits 35:32 + U32 : 4; // Bits 39:36 + U32 CADB_Data_Control : 3; // Bits 42:40 + U32 : 5; // Bits 47:43 + U32 CADB_Data_ODT : 4; // Bits 51:48 + U32 : 4; // Bits 55:52 + U32 CADB_Data_CKE : 4; // Bits 59:56 + U32 : 4; // Bits 63:60 + } Bits; + U64 Data; + U32 Data32[2]; + U16 Data16[4]; + U8 Data8[8]; +} MCHBAR_CH1_CR_REUT_CH_PAT_CADB_PROG_STRUCT; + +typedef union { + struct { + U32 Pattern_Buffer : 16; // Bits 15:0 + U32 : 16; // Bits 31:16 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_0_STRUCT; + +typedef union { + struct { + U32 Pattern_Buffer : 16; // Bits 15:0 + U32 : 16; // Bits 31:16 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_1_STRUCT; + +typedef union { + struct { + U32 Pattern_Buffer : 16; // Bits 15:0 + U32 : 16; // Bits 31:16 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_2_STRUCT; + +typedef union { + struct { + U32 WDB_Increment_Rate : 5; // Bits 4:0 + U32 WDB_Increment_Scale : 1; // Bits 5:5 + U32 : 2; // Bits 7:6 + U32 WDB_Start_Pointer : 6; // Bits 13:8 + U32 : 2; // Bits 15:14 + U32 WDB_End_Pointer : 6; // Bits 21:16 + U32 : 10; // Bits 31:22 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_CTRL_STRUCT; + +typedef union { + struct { + U32 Refresh_Rank_Mask : 4; // Bits 3:0 + U32 : 4; // Bits 7:4 + U32 RefZQ_En_Start_Test_Sync : 1; // Bits 8:8 + U32 : 22; // Bits 30:9 + U32 Panic_Refresh_Only : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_REUT_CH_MISC_REFRESH_CTRL_STRUCT; + +typedef union { + struct { + U32 ZQ_Rank_Mask : 4; // Bits 3:0 + U32 : 27; // Bits 30:4 + U32 Always_Do_ZQ : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_REUT_CH_MISC_ZQ_CTRL_STRUCT; + +#ifdef ULT_FLAG +typedef union { + struct { + U32 Rank_0_x32 : 1; // Bits 0:0 + U32 Rank_1_x32 : 1; // Bits 1:1 + U32 Rank_2_x32 : 1; // Bits 2:2 + U32 Rank_3_x32 : 1; // Bits 3:3 + U32 LPDDR2 : 1; // Bits 4:4 + U32 : 3; // Bits 7:5 + U32 MR4_PERIOD : 16; // Bits 23:8 + U32 : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_LPDDR_MR_PARAMS_STRUCT; + +typedef union { + struct { + U32 Address : 8; // Bits 7:0 + U32 Data : 8; // Bits 15:8 + U32 Rank : 2; // Bits 17:16 + U32 Write : 1; // Bits 18:18 + U32 Init_MRW : 1; // Bits 19:19 + U32 : 11; // Bits 30:20 + U32 Busy : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_LPDDR_MR_COMMAND_STRUCT; + +typedef union { + struct { + U32 Device_0 : 8; // Bits 7:0 + U32 Device_1 : 8; // Bits 15:8 + U32 Device_2 : 8; // Bits 23:16 + U32 Device_3 : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_LPDDR_MR_RESULT_STRUCT; + +typedef union { + struct { + U32 Rank_0 : 3; // Bits 2:0 + U32 : 5; // Bits 7:3 + U32 Rank_1 : 3; // Bits 10:8 + U32 : 5; // Bits 15:11 + U32 Rank_2 : 3; // Bits 18:16 + U32 : 5; // Bits 23:19 + U32 Rank_3 : 3; // Bits 26:24 + U32 : 5; // Bits 31:27 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_LPDDR_MR4_RANK_TEMPERATURE_STRUCT; + +typedef union { + struct { + U32 Bit_0 : 3; // Bits 2:0 + U32 : 1; // Bits 3:3 + U32 Bit_1 : 3; // Bits 6:4 + U32 : 1; // Bits 7:7 + U32 Bit_2 : 3; // Bits 10:8 + U32 : 1; // Bits 11:11 + U32 Bit_16 : 3; // Bits 14:12 + U32 : 1; // Bits 15:15 + U32 Bit_17 : 3; // Bits 18:16 + U32 : 1; // Bits 19:19 + U32 Bit_18 : 3; // Bits 22:20 + U32 : 1; // Bits 23:23 + U32 Byte_0 : 3; // Bits 26:24 + U32 : 1; // Bits 27:27 + U32 Byte_2 : 3; // Bits 30:28 + U32 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_DESWIZZLE_LOW_STRUCT; + +typedef union { + struct { + U32 Bit_32 : 3; // Bits 2:0 + U32 : 1; // Bits 3:3 + U32 Bit_33 : 3; // Bits 6:4 + U32 : 1; // Bits 7:7 + U32 Bit_34 : 3; // Bits 10:8 + U32 : 1; // Bits 11:11 + U32 Bit_48 : 3; // Bits 14:12 + U32 : 1; // Bits 15:15 + U32 Bit_49 : 3; // Bits 18:16 + U32 : 1; // Bits 19:19 + U32 Bit_50 : 3; // Bits 22:20 + U32 : 1; // Bits 23:23 + U32 Byte_4 : 3; // Bits 26:24 + U32 : 1; // Bits 27:27 + U32 Byte_6 : 3; // Bits 30:28 + U32 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_DESWIZZLE_HIGH_STRUCT; +#endif // ULT_FLAG + +typedef union { + struct { + U32 Ref_Interval : 11; // Bits 10:0 + U32 Ref_Stagger_En : 1; // Bits 11:11 + U32 Ref_Stagger_Mode : 1; // Bits 12:12 + U32 Disable_Stolen_Refresh : 1; // Bits 13:13 + U32 En_Ref_Type_Display : 1; // Bits 14:14 + U32 : 17; // Bits 31:15 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_MC_REFRESH_STAGGER_STRUCT; + +typedef union { + struct { + U32 ZQCS_period : 8; // Bits 7:0 + U32 tZQCS : 8; // Bits 15:8 + U32 : 16; // Bits 31:16 + } Bits; +#ifdef ULT_FLAG + struct { + U32 ZQCS_period : 10; // Bits 9:0 + U32 tZQCS : 10; // Bits 19:10 + U32 : 12; // Bits 31:20 + } UltBits; +#endif //ULT_FLAG + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_TC_ZQCAL_STRUCT; + +typedef union { + struct { + U32 OREF_RI : 8; // Bits 7:0 + U32 Refresh_HP_WM : 4; // Bits 11:8 + U32 Refresh_panic_wm : 4; // Bits 15:12 + U32 : 16; // Bits 31:16 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_TC_RFP_STRUCT; + +typedef union { + struct { + U32 tREFI : 16; // Bits 15:0 + U32 tRFC : 9; // Bits 24:16 + U32 tREFIx9 : 7; // Bits 31:25 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_TC_RFTP_STRUCT; + +typedef union { + struct { + U32 MR2_sh_low : 6; // Bits 5:0 + U32 SRT_avail : 2; // Bits 7:6 + U32 MR2_sh_high : 3; // Bits 10:8 + U32 : 3; // Bits 13:11 + U32 Addr_bit_swizzle : 2; // Bits 15:14 + U32 : 16; // Bits 31:16 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_TC_MR2_SHADDOW_STRUCT; + +typedef union { + struct { + U32 Rank_occupancy : 4; // Bits 3:0 + U32 : 28; // Bits 31:4 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_MC_INIT_STATE_STRUCT; + +typedef union { + struct { + U32 tXSDLL : 12; // Bits 11:0 + U32 tXS_offset : 4; // Bits 15:12 + U32 tZQOPER : 10; // Bits 25:16 + U32 : 2; // Bits 27:26 + U32 tMOD : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_TC_SRFTP_STRUCT; + +typedef union { + struct { + U32 VISAByteSel : 3; // Bits 2:0 + U32 : 29; // Bits 31:3 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_WDB_VISA_SEL_STRUCT; + +typedef union { + struct { + U32 FASTADDR : 12; // Bits 11:0 + U32 : 4; // Bits 15:12 + U32 ADDREN : 1; // Bits 16:16 + U32 SEQEN : 1; // Bits 17:17 + U32 POL0 : 1; // Bits 18:18 + U32 POL1 : 1; // Bits 19:19 + U32 CMDA : 4; // Bits 23:20 + U32 CMDB : 4; // Bits 27:24 + U32 CMDC : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_DCLK_LDAT_PDAT_STRUCT; + +typedef union { + struct { + U32 BANKSEL : 4; // Bits 3:0 + U32 : 1; // Bits 4:4 + U32 ARRAYSEL : 5; // Bits 9:5 + U32 CMP : 1; // Bits 10:10 + U32 REP : 1; // Bits 11:11 + U32 DWORD : 4; // Bits 15:12 + U32 MODE : 2; // Bits 17:16 + U32 MPMAP : 6; // Bits 23:18 + U32 MPBOFFSET : 4; // Bits 27:24 + U32 STAGE_EN : 1; // Bits 28:28 + U32 SHADOW : 2; // Bits 30:29 + U32 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_DCLK_LDAT_SDAT_STRUCT; + +typedef union { + struct { + U32 DATOUT : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_DCLK_LDAT_DATAOUT_STRUCT; + +typedef union { + struct { + U32 DATIN : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_DCLK_LDAT_DATAIN_0_STRUCT; + +typedef union { + struct { + U32 FASTADDR : 12; // Bits 11:0 + U32 : 4; // Bits 15:12 + U32 ADDREN : 1; // Bits 16:16 + U32 SEQEN : 1; // Bits 17:17 + U32 POL0 : 1; // Bits 18:18 + U32 POL1 : 1; // Bits 19:19 + U32 CMDA : 4; // Bits 23:20 + U32 CMDB : 4; // Bits 27:24 + U32 CMDC : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_QCLK_LDAT_PDAT_STRUCT; + +typedef union { + struct { + U32 BANKSEL : 4; // Bits 3:0 + U32 : 1; // Bits 4:4 + U32 ARRAYSEL : 5; // Bits 9:5 + U32 CMP : 1; // Bits 10:10 + U32 REP : 1; // Bits 11:11 + U32 DWORD : 4; // Bits 15:12 + U32 MODE : 2; // Bits 17:16 + U32 MPMAP : 6; // Bits 23:18 + U32 MPBOFFSET : 4; // Bits 27:24 + U32 STAGE_EN : 1; // Bits 28:28 + U32 SHADOW : 2; // Bits 30:29 + U32 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_QCLK_LDAT_SDAT_STRUCT; + +typedef union { + struct { + U32 DATOUT : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_QCLK_LDAT_DATAOUT_STRUCT; + +typedef union { + struct { + U32 DATIN : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_QCLK_LDAT_DATAIN_0_STRUCT; + +typedef union { + struct { + U32 DATIN : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_QCLK_LDAT_DATAIN_1_STRUCT; + +typedef union { + struct { + U32 RPQ_disable : 28; // Bits 27:0 + U32 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_QUEUE_ENTRY_DISABLE_RPQ_STRUCT; + +typedef union { + struct { + U32 WPQ_disable : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_QUEUE_ENTRY_DISABLE_WPQ_STRUCT; + +typedef union { + struct { + U32 DIMM0_IDLE_ENERGY : 6; // Bits 5:0 + U32 : 2; // Bits 7:6 + U32 DIMM1_IDLE_ENERGY : 6; // Bits 13:8 + U32 : 18; // Bits 31:14 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_PM_DIMM_IDLE_ENERGY_STRUCT; + +typedef union { + struct { + U32 DIMM0_PD_ENERGY : 6; // Bits 5:0 + U32 : 2; // Bits 7:6 + U32 DIMM1_PD_ENERGY : 6; // Bits 13:8 + U32 : 18; // Bits 31:14 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_PM_DIMM_PD_ENERGY_STRUCT; + +typedef union { + struct { + U32 DIMM0_ACT_ENERGY : 8; // Bits 7:0 + U32 DIMM1_ACT_ENERGY : 8; // Bits 15:8 + U32 : 16; // Bits 31:16 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_PM_DIMM_ACT_ENERGY_STRUCT; + +typedef union { + struct { + U32 DIMM0_RD_ENERGY : 8; // Bits 7:0 + U32 DIMM1_RD_ENERGY : 8; // Bits 15:8 + U32 : 16; // Bits 31:16 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_PM_DIMM_RD_ENERGY_STRUCT; + +typedef union { + struct { + U32 DIMM0_WR_ENERGY : 8; // Bits 7:0 + U32 DIMM1_WR_ENERGY : 8; // Bits 15:8 + U32 : 16; // Bits 31:16 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_PM_DIMM_WR_ENERGY_STRUCT; + +typedef union { + struct { + U32 CKE_MIN : 8; // Bits 7:0 + U32 CKE_MIN_DEFEATURE : 1; // Bits 8:8 + U32 : 23; // Bits 31:9 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_PM_THRT_CKE_MIN_STRUCT; + +typedef union { + struct { + U32 ODT : 4; // Bits 3:0 + U32 Web : 1; // Bits 4:4 + U32 CASb : 1; // Bits 5:5 + U32 RASb : 1; // Bits 6:6 + U32 CSb : 4; // Bits 10:7 + U32 CKE : 4; // Bits 14:11 + U32 MA : 16; // Bits 30:15 + U32 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_ODLAT_CMD_MATCH0_STRUCT; + +typedef union { + struct { + U32 ODT : 4; // Bits 3:0 + U32 Web : 1; // Bits 4:4 + U32 CASb : 1; // Bits 5:5 + U32 RASb : 1; // Bits 6:6 + U32 CSb : 4; // Bits 10:7 + U32 CKE : 4; // Bits 14:11 + U32 MA : 16; // Bits 30:15 + U32 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_ODLAT_CMD_MATCH1_STRUCT; + +typedef union { + struct { + U32 ODT : 4; // Bits 3:0 + U32 Web : 1; // Bits 4:4 + U32 CASb : 1; // Bits 5:5 + U32 RASb : 1; // Bits 6:6 + U32 CSb : 4; // Bits 10:7 + U32 CKE : 4; // Bits 14:11 + U32 MA : 16; // Bits 30:15 + U32 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_ODLAT_CMD_MATCH2_STRUCT; + +typedef union { + struct { + U32 ODT : 4; // Bits 3:0 + U32 Web : 1; // Bits 4:4 + U32 CASb : 1; // Bits 5:5 + U32 RASb : 1; // Bits 6:6 + U32 CSb : 4; // Bits 10:7 + U32 CKE : 4; // Bits 14:11 + U32 MA : 16; // Bits 30:15 + U32 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_ODLAT_CMD_MATCH3_STRUCT; + +typedef union { + struct { + U32 ODT : 4; // Bits 3:0 + U32 Web : 1; // Bits 4:4 + U32 CASb : 1; // Bits 5:5 + U32 RASb : 1; // Bits 6:6 + U32 CSb : 4; // Bits 10:7 + U32 CKE : 4; // Bits 14:11 + U32 MA : 16; // Bits 30:15 + U32 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_ODLAT_CMD_MASK0_STRUCT; + +typedef union { + struct { + U32 ODT : 4; // Bits 3:0 + U32 Web : 1; // Bits 4:4 + U32 CASb : 1; // Bits 5:5 + U32 RASb : 1; // Bits 6:6 + U32 CSb : 4; // Bits 10:7 + U32 CKE : 4; // Bits 14:11 + U32 MA : 16; // Bits 30:15 + U32 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_ODLAT_CMD_MASK1_STRUCT; + +typedef union { + struct { + U32 ODT : 4; // Bits 3:0 + U32 Web : 1; // Bits 4:4 + U32 CASb : 1; // Bits 5:5 + U32 RASb : 1; // Bits 6:6 + U32 CSb : 4; // Bits 10:7 + U32 CKE : 4; // Bits 14:11 + U32 MA : 16; // Bits 30:15 + U32 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_ODLAT_CMD_MASK2_STRUCT; + +typedef union { + struct { + U32 ODT : 4; // Bits 3:0 + U32 Web : 1; // Bits 4:4 + U32 CASb : 1; // Bits 5:5 + U32 RASb : 1; // Bits 6:6 + U32 CSb : 4; // Bits 10:7 + U32 CKE : 4; // Bits 14:11 + U32 MA : 16; // Bits 30:15 + U32 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_ODLAT_CMD_MASK3_STRUCT; + +typedef union { + struct { + U32 BankMatch0 : 3; // Bits 2:0 + U32 BankMatch1 : 3; // Bits 5:3 + U32 BankMatch2 : 3; // Bits 8:6 + U32 BankMatch3 : 3; // Bits 11:9 + U32 BankMask0 : 3; // Bits 14:12 + U32 BankMask1 : 3; // Bits 17:15 + U32 BankMask2 : 3; // Bits 20:18 + U32 BankMask3 : 3; // Bits 23:21 + U32 : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_ODLAT_CMD_BANK_STRUCT; + +typedef union { + struct { + U32 InputMatch : 4; // Bits 3:0 + U32 InputInvert : 4; // Bits 7:4 + U32 CountMatches : 1; // Bits 8:8 + U32 CounterThreshold : 15; // Bits 23:9 + U32 CounterAction : 2; // Bits 25:24 + U32 CounterNextState : 2; // Bits 27:26 + U32 MatchAction : 2; // Bits 29:28 + U32 MatchNextState : 2; // Bits 31:30 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL0_STRUCT; + +typedef union { + struct { + U32 InputMatch : 4; // Bits 3:0 + U32 InputInvert : 4; // Bits 7:4 + U32 CountMatches : 1; // Bits 8:8 + U32 CounterThreshold : 15; // Bits 23:9 + U32 CounterAction : 2; // Bits 25:24 + U32 CounterNextState : 2; // Bits 27:26 + U32 MatchAction : 2; // Bits 29:28 + U32 MatchNextState : 2; // Bits 31:30 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL1_STRUCT; + +typedef union { + struct { + U32 InputMatch : 4; // Bits 3:0 + U32 InputInvert : 4; // Bits 7:4 + U32 CountMatches : 1; // Bits 8:8 + U32 CounterThreshold : 15; // Bits 23:9 + U32 CounterAction : 2; // Bits 25:24 + U32 CounterNextState : 2; // Bits 27:26 + U32 MatchAction : 2; // Bits 29:28 + U32 MatchNextState : 2; // Bits 31:30 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL2_STRUCT; + +typedef union { + struct { + U32 InputMatch : 4; // Bits 3:0 + U32 InputInvert : 4; // Bits 7:4 + U32 CountMatches : 1; // Bits 8:8 + U32 CounterThreshold : 15; // Bits 23:9 + U32 CounterAction : 2; // Bits 25:24 + U32 CounterNextState : 2; // Bits 27:26 + U32 MatchAction : 2; // Bits 29:28 + U32 MatchNextState : 2; // Bits 31:30 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL3_STRUCT; + +typedef union { + struct { + U32 TriggerBlockEnable : 1; // Bits 0:0 + U32 GlobalCounterThreshold : 16; // Bits 16:1 + U32 : 15; // Bits 31:17 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_ODLAT_SEQ_GLOBAL_STRUCT; + +typedef union { + struct { + U32 WMM_Enter : 8; // Bits 7:0 + U32 WMM_Exit : 8; // Bits 15:8 + U32 WPQ_IS : 8; // Bits 23:16 + U32 Starve_count : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_SC_WDBWM_STRUCT; + +typedef union { + struct { + U32 Data : 18; // Bits 17:0 + U32 : 13; // Bits 30:18 + U32 VORANGE : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_VISA_CTL_MCMNTS_STRUCT; + +#define MCDFXS_CR_REUT_GLOBAL_CTL_MCMAIN_REG (0x00004800) + #define MCDFXS_CR_REUT_GLOBAL_CTL_MCMAIN_Global_Start_Test_OFF ( 0) + #define MCDFXS_CR_REUT_GLOBAL_CTL_MCMAIN_Global_Start_Test_WID ( 1) + #define MCDFXS_CR_REUT_GLOBAL_CTL_MCMAIN_Global_Start_Test_MSK (0x00000001) + #define MCDFXS_CR_REUT_GLOBAL_CTL_MCMAIN_Global_Start_Test_MAX (0x00000001) + #define MCDFXS_CR_REUT_GLOBAL_CTL_MCMAIN_Global_Start_Test_DEF (0x00000000) + #define MCDFXS_CR_REUT_GLOBAL_CTL_MCMAIN_Global_Stop_Test_OFF ( 1) + #define MCDFXS_CR_REUT_GLOBAL_CTL_MCMAIN_Global_Stop_Test_WID ( 1) + #define MCDFXS_CR_REUT_GLOBAL_CTL_MCMAIN_Global_Stop_Test_MSK (0x00000002) + #define MCDFXS_CR_REUT_GLOBAL_CTL_MCMAIN_Global_Stop_Test_MAX (0x00000001) + #define MCDFXS_CR_REUT_GLOBAL_CTL_MCMAIN_Global_Stop_Test_DEF (0x00000000) + #define MCDFXS_CR_REUT_GLOBAL_CTL_MCMAIN_Global_Clear_Errors_OFF ( 2) + #define MCDFXS_CR_REUT_GLOBAL_CTL_MCMAIN_Global_Clear_Errors_WID ( 1) + #define MCDFXS_CR_REUT_GLOBAL_CTL_MCMAIN_Global_Clear_Errors_MSK (0x00000004) + #define MCDFXS_CR_REUT_GLOBAL_CTL_MCMAIN_Global_Clear_Errors_MAX (0x00000001) + #define MCDFXS_CR_REUT_GLOBAL_CTL_MCMAIN_Global_Clear_Errors_DEF (0x00000000) + #define MCDFXS_CR_REUT_GLOBAL_CTL_MCMAIN_Global_Stop_Test_On_Any_Error_OFF ( 4) + #define MCDFXS_CR_REUT_GLOBAL_CTL_MCMAIN_Global_Stop_Test_On_Any_Error_WID ( 1) + #define MCDFXS_CR_REUT_GLOBAL_CTL_MCMAIN_Global_Stop_Test_On_Any_Error_MSK (0x00000010) + #define MCDFXS_CR_REUT_GLOBAL_CTL_MCMAIN_Global_Stop_Test_On_Any_Error_MAX (0x00000001) + #define MCDFXS_CR_REUT_GLOBAL_CTL_MCMAIN_Global_Stop_Test_On_Any_Error_DEF (0x00000000) + +#define MCDFXS_CR_REUT_GLOBAL_ERR_MCMAIN_REG (0x00004804) + #define MCDFXS_CR_REUT_GLOBAL_ERR_MCMAIN_Channel_Error_Status_0_OFF ( 0) + #define MCDFXS_CR_REUT_GLOBAL_ERR_MCMAIN_Channel_Error_Status_0_WID ( 1) + #define MCDFXS_CR_REUT_GLOBAL_ERR_MCMAIN_Channel_Error_Status_0_MSK (0x00000001) + #define MCDFXS_CR_REUT_GLOBAL_ERR_MCMAIN_Channel_Error_Status_0_MAX (0x00000001) + #define MCDFXS_CR_REUT_GLOBAL_ERR_MCMAIN_Channel_Error_Status_0_DEF (0x00000000) + #define MCDFXS_CR_REUT_GLOBAL_ERR_MCMAIN_Channel_Error_Status_1_OFF ( 1) + #define MCDFXS_CR_REUT_GLOBAL_ERR_MCMAIN_Channel_Error_Status_1_WID ( 1) + #define MCDFXS_CR_REUT_GLOBAL_ERR_MCMAIN_Channel_Error_Status_1_MSK (0x00000002) + #define MCDFXS_CR_REUT_GLOBAL_ERR_MCMAIN_Channel_Error_Status_1_MAX (0x00000001) + #define MCDFXS_CR_REUT_GLOBAL_ERR_MCMAIN_Channel_Error_Status_1_DEF (0x00000000) + #define MCDFXS_CR_REUT_GLOBAL_ERR_MCMAIN_Channel_Test_Done_Status_0_OFF (16) + #define MCDFXS_CR_REUT_GLOBAL_ERR_MCMAIN_Channel_Test_Done_Status_0_WID ( 1) + #define MCDFXS_CR_REUT_GLOBAL_ERR_MCMAIN_Channel_Test_Done_Status_0_MSK (0x00010000) + #define MCDFXS_CR_REUT_GLOBAL_ERR_MCMAIN_Channel_Test_Done_Status_0_MAX (0x00000001) + #define MCDFXS_CR_REUT_GLOBAL_ERR_MCMAIN_Channel_Test_Done_Status_0_DEF (0x00000001) + #define MCDFXS_CR_REUT_GLOBAL_ERR_MCMAIN_Channel_Test_Done_Status_1_OFF (17) + #define MCDFXS_CR_REUT_GLOBAL_ERR_MCMAIN_Channel_Test_Done_Status_1_WID ( 1) + #define MCDFXS_CR_REUT_GLOBAL_ERR_MCMAIN_Channel_Test_Done_Status_1_MSK (0x00020000) + #define MCDFXS_CR_REUT_GLOBAL_ERR_MCMAIN_Channel_Test_Done_Status_1_MAX (0x00000001) + #define MCDFXS_CR_REUT_GLOBAL_ERR_MCMAIN_Channel_Test_Done_Status_1_DEF (0x00000001) + +#define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_REG (0x00004808) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Number_of_Cachelines_OFF ( 0) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Number_of_Cachelines_WID ( 7) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Number_of_Cachelines_MSK (0x0000007F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Number_of_Cachelines_MAX (0x0000007F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Number_of_Cachelines_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Number_of_Cachelines_Scale_OFF ( 7) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Number_of_Cachelines_Scale_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Number_of_Cachelines_Scale_MSK (0x00000080) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Number_of_Cachelines_Scale_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Number_of_Cachelines_Scale_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Subsequence_Wait_OFF ( 8) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Subsequence_Wait_WID (10) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Subsequence_Wait_MSK (0x0003FF00) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Subsequence_Wait_MAX (0x000003FF) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Subsequence_Wait_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Subsequence_Type_OFF (20) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Subsequence_Type_WID ( 4) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Subsequence_Type_MSK (0x00F00000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Subsequence_Type_MAX (0x0000000F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Subsequence_Type_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Save_Current_Base_Address_To_Start_OFF (25) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Save_Current_Base_Address_To_Start_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Save_Current_Base_Address_To_Start_MSK (0x02000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Save_Current_Base_Address_To_Start_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Save_Current_Base_Address_To_Start_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Reset_Current_Base_Address_To_Start_OFF (26) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Reset_Current_Base_Address_To_Start_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Reset_Current_Base_Address_To_Start_MSK (0x04000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Reset_Current_Base_Address_To_Start_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Reset_Current_Base_Address_To_Start_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Data_and_ECC_Address_Inversion_OFF (27) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Data_and_ECC_Address_Inversion_WID ( 2) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Data_and_ECC_Address_Inversion_MSK (0x18000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Data_and_ECC_Address_Inversion_MAX (0x00000003) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Data_and_ECC_Address_Inversion_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Invert_Data_and_ECC_OFF (30) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Invert_Data_and_ECC_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Invert_Data_and_ECC_MSK (0x40000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Invert_Data_and_ECC_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Invert_Data_and_ECC_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_OFF (31) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_MSK (0x80000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_DEF (0x00000000) + + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Number_of_Cachelines_OFF ( 0) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Number_of_Cachelines_WID ( 7) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Number_of_Cachelines_MSK (0x0000007F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Number_of_Cachelines_MAX (0x0000007F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Number_of_Cachelines_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Number_of_Cachelines_Scale_OFF ( 7) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Number_of_Cachelines_Scale_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Number_of_Cachelines_Scale_MSK (0x00000080) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Number_of_Cachelines_Scale_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Number_of_Cachelines_Scale_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Subsequence_Wait_OFF ( 8) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Subsequence_Wait_WID (14) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Subsequence_Wait_MSK (0x003FFF00) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Subsequence_Wait_MAX (0x00003FFF) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Subsequence_Wait_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Subsequence_Type_OFF (22) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Subsequence_Type_WID ( 4) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Subsequence_Type_MSK (0x03C00000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Subsequence_Type_MAX (0x0000000F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Subsequence_Type_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Save_Current_Base_Address_To_Start_OFF (26) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Save_Current_Base_Address_To_Start_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Save_Current_Base_Address_To_Start_MSK (0x04000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Save_Current_Base_Address_To_Start_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Save_Current_Base_Address_To_Start_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Reset_Current_Base_Address_To_Start_OFF (27) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Reset_Current_Base_Address_To_Start_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Reset_Current_Base_Address_To_Start_MSK (0x08000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Reset_Current_Base_Address_To_Start_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Reset_Current_Base_Address_To_Start_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Data_and_ECC_Address_Inversion_OFF (28) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Data_and_ECC_Address_Inversion_WID ( 2) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Data_and_ECC_Address_Inversion_MSK (0x30000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Data_and_ECC_Address_Inversion_MAX (0x00000003) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Data_and_ECC_Address_Inversion_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Invert_Data_and_ECC_OFF (30) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Invert_Data_and_ECC_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Invert_Data_and_ECC_MSK (0x40000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Invert_Data_and_ECC_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Invert_Data_and_ECC_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Stop_Base_Subsequence_On_Wrap_Trigger_OFF (31) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Stop_Base_Subsequence_On_Wrap_Trigger_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Stop_Base_Subsequence_On_Wrap_Trigger_MSK (0x80000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Stop_Base_Subsequence_On_Wrap_Trigger_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Stop_Base_Subsequence_On_Wrap_Trigger_DEF (0x00000000) + +#define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_REG (0x0000480C) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Number_of_Cachelines_OFF ( 0) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Number_of_Cachelines_WID ( 7) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Number_of_Cachelines_MSK (0x0000007F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Number_of_Cachelines_MAX (0x0000007F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Number_of_Cachelines_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Number_of_Cachelines_Scale_OFF ( 7) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Number_of_Cachelines_Scale_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Number_of_Cachelines_Scale_MSK (0x00000080) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Number_of_Cachelines_Scale_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Number_of_Cachelines_Scale_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Subsequence_Wait_OFF ( 8) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Subsequence_Wait_WID (10) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Subsequence_Wait_MSK (0x0003FF00) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Subsequence_Wait_MAX (0x000003FF) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Subsequence_Wait_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Subsequence_Type_OFF (20) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Subsequence_Type_WID ( 4) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Subsequence_Type_MSK (0x00F00000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Subsequence_Type_MAX (0x0000000F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Subsequence_Type_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Save_Current_Base_Address_To_Start_OFF (25) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Save_Current_Base_Address_To_Start_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Save_Current_Base_Address_To_Start_MSK (0x02000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Save_Current_Base_Address_To_Start_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Save_Current_Base_Address_To_Start_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Reset_Current_Base_Address_To_Start_OFF (26) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Reset_Current_Base_Address_To_Start_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Reset_Current_Base_Address_To_Start_MSK (0x04000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Reset_Current_Base_Address_To_Start_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Reset_Current_Base_Address_To_Start_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Data_and_ECC_Address_Inversion_OFF (27) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Data_and_ECC_Address_Inversion_WID ( 2) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Data_and_ECC_Address_Inversion_MSK (0x18000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Data_and_ECC_Address_Inversion_MAX (0x00000003) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Data_and_ECC_Address_Inversion_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Invert_Data_and_ECC_OFF (30) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Invert_Data_and_ECC_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Invert_Data_and_ECC_MSK (0x40000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Invert_Data_and_ECC_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Invert_Data_and_ECC_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_OFF (31) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_MSK (0x80000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_DEF (0x00000000) + + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Number_of_Cachelines_OFF ( 0) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Number_of_Cachelines_WID ( 7) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Number_of_Cachelines_MSK (0x0000007F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Number_of_Cachelines_MAX (0x0000007F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Number_of_Cachelines_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Number_of_Cachelines_Scale_OFF ( 7) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Number_of_Cachelines_Scale_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Number_of_Cachelines_Scale_MSK (0x00000080) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Number_of_Cachelines_Scale_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Number_of_Cachelines_Scale_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Subsequence_Wait_OFF ( 8) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Subsequence_Wait_WID (14) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Subsequence_Wait_MSK (0x003FFF00) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Subsequence_Wait_MAX (0x00003FFF) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Subsequence_Wait_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Subsequence_Type_OFF (22) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Subsequence_Type_WID ( 4) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Subsequence_Type_MSK (0x03C00000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Subsequence_Type_MAX (0x0000000F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Subsequence_Type_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Save_Current_Base_Address_To_Start_OFF (26) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Save_Current_Base_Address_To_Start_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Save_Current_Base_Address_To_Start_MSK (0x04000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Save_Current_Base_Address_To_Start_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Save_Current_Base_Address_To_Start_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Reset_Current_Base_Address_To_Start_OFF (27) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Reset_Current_Base_Address_To_Start_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Reset_Current_Base_Address_To_Start_MSK (0x08000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Reset_Current_Base_Address_To_Start_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Reset_Current_Base_Address_To_Start_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Data_and_ECC_Address_Inversion_OFF (28) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Data_and_ECC_Address_Inversion_WID ( 2) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Data_and_ECC_Address_Inversion_MSK (0x30000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Data_and_ECC_Address_Inversion_MAX (0x00000003) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Data_and_ECC_Address_Inversion_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Invert_Data_and_ECC_OFF (30) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Invert_Data_and_ECC_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Invert_Data_and_ECC_MSK (0x40000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Invert_Data_and_ECC_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Invert_Data_and_ECC_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Stop_Base_Subsequence_On_Wrap_Trigger_OFF (31) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Stop_Base_Subsequence_On_Wrap_Trigger_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Stop_Base_Subsequence_On_Wrap_Trigger_MSK (0x80000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Stop_Base_Subsequence_On_Wrap_Trigger_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Stop_Base_Subsequence_On_Wrap_Trigger_DEF (0x00000000) + +#define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_REG (0x00004810) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Number_of_Cachelines_OFF ( 0) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Number_of_Cachelines_WID ( 7) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Number_of_Cachelines_MSK (0x0000007F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Number_of_Cachelines_MAX (0x0000007F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Number_of_Cachelines_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Number_of_Cachelines_Scale_OFF ( 7) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Number_of_Cachelines_Scale_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Number_of_Cachelines_Scale_MSK (0x00000080) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Number_of_Cachelines_Scale_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Number_of_Cachelines_Scale_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Subsequence_Wait_OFF ( 8) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Subsequence_Wait_WID (10) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Subsequence_Wait_MSK (0x0003FF00) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Subsequence_Wait_MAX (0x000003FF) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Subsequence_Wait_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Subsequence_Type_OFF (20) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Subsequence_Type_WID ( 4) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Subsequence_Type_MSK (0x00F00000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Subsequence_Type_MAX (0x0000000F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Subsequence_Type_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Save_Current_Base_Address_To_Start_OFF (25) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Save_Current_Base_Address_To_Start_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Save_Current_Base_Address_To_Start_MSK (0x02000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Save_Current_Base_Address_To_Start_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Save_Current_Base_Address_To_Start_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Reset_Current_Base_Address_To_Start_OFF (26) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Reset_Current_Base_Address_To_Start_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Reset_Current_Base_Address_To_Start_MSK (0x04000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Reset_Current_Base_Address_To_Start_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Reset_Current_Base_Address_To_Start_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Data_and_ECC_Address_Inversion_OFF (27) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Data_and_ECC_Address_Inversion_WID ( 2) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Data_and_ECC_Address_Inversion_MSK (0x18000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Data_and_ECC_Address_Inversion_MAX (0x00000003) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Data_and_ECC_Address_Inversion_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Invert_Data_and_ECC_OFF (30) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Invert_Data_and_ECC_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Invert_Data_and_ECC_MSK (0x40000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Invert_Data_and_ECC_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Invert_Data_and_ECC_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_OFF (31) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_MSK (0x80000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_DEF (0x00000000) + + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Number_of_Cachelines_OFF ( 0) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Number_of_Cachelines_WID ( 7) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Number_of_Cachelines_MSK (0x0000007F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Number_of_Cachelines_MAX (0x0000007F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Number_of_Cachelines_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Number_of_Cachelines_Scale_OFF ( 7) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Number_of_Cachelines_Scale_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Number_of_Cachelines_Scale_MSK (0x00000080) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Number_of_Cachelines_Scale_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Number_of_Cachelines_Scale_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Subsequence_Wait_OFF ( 8) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Subsequence_Wait_WID (14) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Subsequence_Wait_MSK (0x003FFF00) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Subsequence_Wait_MAX (0x00003FFF) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Subsequence_Wait_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Subsequence_Type_OFF (22) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Subsequence_Type_WID ( 4) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Subsequence_Type_MSK (0x03C00000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Subsequence_Type_MAX (0x0000000F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Subsequence_Type_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Save_Current_Base_Address_To_Start_OFF (26) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Save_Current_Base_Address_To_Start_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Save_Current_Base_Address_To_Start_MSK (0x04000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Save_Current_Base_Address_To_Start_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Save_Current_Base_Address_To_Start_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Reset_Current_Base_Address_To_Start_OFF (27) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Reset_Current_Base_Address_To_Start_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Reset_Current_Base_Address_To_Start_MSK (0x08000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Reset_Current_Base_Address_To_Start_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Reset_Current_Base_Address_To_Start_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Data_and_ECC_Address_Inversion_OFF (28) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Data_and_ECC_Address_Inversion_WID ( 2) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Data_and_ECC_Address_Inversion_MSK (0x30000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Data_and_ECC_Address_Inversion_MAX (0x00000003) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Data_and_ECC_Address_Inversion_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Invert_Data_and_ECC_OFF (30) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Invert_Data_and_ECC_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Invert_Data_and_ECC_MSK (0x40000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Invert_Data_and_ECC_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Invert_Data_and_ECC_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Stop_Base_Subsequence_On_Wrap_Trigger_OFF (31) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Stop_Base_Subsequence_On_Wrap_Trigger_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Stop_Base_Subsequence_On_Wrap_Trigger_MSK (0x80000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Stop_Base_Subsequence_On_Wrap_Trigger_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Stop_Base_Subsequence_On_Wrap_Trigger_DEF (0x00000000) + +#define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_REG (0x00004814) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Number_of_Cachelines_OFF ( 0) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Number_of_Cachelines_WID ( 7) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Number_of_Cachelines_MSK (0x0000007F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Number_of_Cachelines_MAX (0x0000007F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Number_of_Cachelines_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Number_of_Cachelines_Scale_OFF ( 7) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Number_of_Cachelines_Scale_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Number_of_Cachelines_Scale_MSK (0x00000080) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Number_of_Cachelines_Scale_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Number_of_Cachelines_Scale_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Subsequence_Wait_OFF ( 8) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Subsequence_Wait_WID (10) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Subsequence_Wait_MSK (0x0003FF00) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Subsequence_Wait_MAX (0x000003FF) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Subsequence_Wait_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Subsequence_Type_OFF (20) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Subsequence_Type_WID ( 4) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Subsequence_Type_MSK (0x00F00000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Subsequence_Type_MAX (0x0000000F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Subsequence_Type_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Save_Current_Base_Address_To_Start_OFF (25) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Save_Current_Base_Address_To_Start_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Save_Current_Base_Address_To_Start_MSK (0x02000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Save_Current_Base_Address_To_Start_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Save_Current_Base_Address_To_Start_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Reset_Current_Base_Address_To_Start_OFF (26) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Reset_Current_Base_Address_To_Start_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Reset_Current_Base_Address_To_Start_MSK (0x04000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Reset_Current_Base_Address_To_Start_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Reset_Current_Base_Address_To_Start_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Data_and_ECC_Address_Inversion_OFF (27) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Data_and_ECC_Address_Inversion_WID ( 2) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Data_and_ECC_Address_Inversion_MSK (0x18000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Data_and_ECC_Address_Inversion_MAX (0x00000003) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Data_and_ECC_Address_Inversion_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Invert_Data_and_ECC_OFF (30) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Invert_Data_and_ECC_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Invert_Data_and_ECC_MSK (0x40000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Invert_Data_and_ECC_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Invert_Data_and_ECC_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_OFF (31) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_MSK (0x80000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_DEF (0x00000000) + + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Number_of_Cachelines_OFF ( 0) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Number_of_Cachelines_WID ( 7) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Number_of_Cachelines_MSK (0x0000007F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Number_of_Cachelines_MAX (0x0000007F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Number_of_Cachelines_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Number_of_Cachelines_Scale_OFF ( 7) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Number_of_Cachelines_Scale_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Number_of_Cachelines_Scale_MSK (0x00000080) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Number_of_Cachelines_Scale_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Number_of_Cachelines_Scale_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Subsequence_Wait_OFF ( 8) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Subsequence_Wait_WID (14) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Subsequence_Wait_MSK (0x003FFF00) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Subsequence_Wait_MAX (0x00003FFF) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Subsequence_Wait_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Subsequence_Type_OFF (22) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Subsequence_Type_WID ( 4) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Subsequence_Type_MSK (0x03C00000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Subsequence_Type_MAX (0x0000000F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Subsequence_Type_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Save_Current_Base_Address_To_Start_OFF (26) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Save_Current_Base_Address_To_Start_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Save_Current_Base_Address_To_Start_MSK (0x04000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Save_Current_Base_Address_To_Start_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Save_Current_Base_Address_To_Start_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Reset_Current_Base_Address_To_Start_OFF (27) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Reset_Current_Base_Address_To_Start_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Reset_Current_Base_Address_To_Start_MSK (0x08000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Reset_Current_Base_Address_To_Start_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Reset_Current_Base_Address_To_Start_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Data_and_ECC_Address_Inversion_OFF (28) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Data_and_ECC_Address_Inversion_WID ( 2) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Data_and_ECC_Address_Inversion_MSK (0x30000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Data_and_ECC_Address_Inversion_MAX (0x00000003) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Data_and_ECC_Address_Inversion_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Invert_Data_and_ECC_OFF (30) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Invert_Data_and_ECC_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Invert_Data_and_ECC_MSK (0x40000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Invert_Data_and_ECC_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Invert_Data_and_ECC_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Stop_Base_Subsequence_On_Wrap_Trigger_OFF (31) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Stop_Base_Subsequence_On_Wrap_Trigger_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Stop_Base_Subsequence_On_Wrap_Trigger_MSK (0x80000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Stop_Base_Subsequence_On_Wrap_Trigger_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Stop_Base_Subsequence_On_Wrap_Trigger_DEF (0x00000000) + +#define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_REG (0x00004818) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Number_of_Cachelines_OFF ( 0) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Number_of_Cachelines_WID ( 7) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Number_of_Cachelines_MSK (0x0000007F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Number_of_Cachelines_MAX (0x0000007F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Number_of_Cachelines_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Number_of_Cachelines_Scale_OFF ( 7) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Number_of_Cachelines_Scale_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Number_of_Cachelines_Scale_MSK (0x00000080) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Number_of_Cachelines_Scale_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Number_of_Cachelines_Scale_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Subsequence_Wait_OFF ( 8) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Subsequence_Wait_WID (10) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Subsequence_Wait_MSK (0x0003FF00) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Subsequence_Wait_MAX (0x000003FF) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Subsequence_Wait_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Subsequence_Type_OFF (20) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Subsequence_Type_WID ( 4) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Subsequence_Type_MSK (0x00F00000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Subsequence_Type_MAX (0x0000000F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Subsequence_Type_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Save_Current_Base_Address_To_Start_OFF (25) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Save_Current_Base_Address_To_Start_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Save_Current_Base_Address_To_Start_MSK (0x02000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Save_Current_Base_Address_To_Start_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Save_Current_Base_Address_To_Start_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Reset_Current_Base_Address_To_Start_OFF (26) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Reset_Current_Base_Address_To_Start_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Reset_Current_Base_Address_To_Start_MSK (0x04000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Reset_Current_Base_Address_To_Start_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Reset_Current_Base_Address_To_Start_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Data_and_ECC_Address_Inversion_OFF (27) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Data_and_ECC_Address_Inversion_WID ( 2) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Data_and_ECC_Address_Inversion_MSK (0x18000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Data_and_ECC_Address_Inversion_MAX (0x00000003) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Data_and_ECC_Address_Inversion_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Invert_Data_and_ECC_OFF (30) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Invert_Data_and_ECC_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Invert_Data_and_ECC_MSK (0x40000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Invert_Data_and_ECC_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Invert_Data_and_ECC_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_OFF (31) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_MSK (0x80000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_DEF (0x00000000) + + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Number_of_Cachelines_OFF ( 0) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Number_of_Cachelines_WID ( 7) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Number_of_Cachelines_MSK (0x0000007F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Number_of_Cachelines_MAX (0x0000007F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Number_of_Cachelines_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Number_of_Cachelines_Scale_OFF ( 7) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Number_of_Cachelines_Scale_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Number_of_Cachelines_Scale_MSK (0x00000080) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Number_of_Cachelines_Scale_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Number_of_Cachelines_Scale_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Subsequence_Wait_OFF ( 8) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Subsequence_Wait_WID (14) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Subsequence_Wait_MSK (0x003FFF00) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Subsequence_Wait_MAX (0x00003FFF) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Subsequence_Wait_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Subsequence_Type_OFF (22) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Subsequence_Type_WID ( 4) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Subsequence_Type_MSK (0x03C00000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Subsequence_Type_MAX (0x0000000F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Subsequence_Type_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Save_Current_Base_Address_To_Start_OFF (26) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Save_Current_Base_Address_To_Start_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Save_Current_Base_Address_To_Start_MSK (0x04000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Save_Current_Base_Address_To_Start_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Save_Current_Base_Address_To_Start_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Reset_Current_Base_Address_To_Start_OFF (27) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Reset_Current_Base_Address_To_Start_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Reset_Current_Base_Address_To_Start_MSK (0x08000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Reset_Current_Base_Address_To_Start_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Reset_Current_Base_Address_To_Start_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Data_and_ECC_Address_Inversion_OFF (28) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Data_and_ECC_Address_Inversion_WID ( 2) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Data_and_ECC_Address_Inversion_MSK (0x30000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Data_and_ECC_Address_Inversion_MAX (0x00000003) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Data_and_ECC_Address_Inversion_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Invert_Data_and_ECC_OFF (30) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Invert_Data_and_ECC_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Invert_Data_and_ECC_MSK (0x40000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Invert_Data_and_ECC_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Invert_Data_and_ECC_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Stop_Base_Subsequence_On_Wrap_Trigger_OFF (31) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Stop_Base_Subsequence_On_Wrap_Trigger_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Stop_Base_Subsequence_On_Wrap_Trigger_MSK (0x80000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Stop_Base_Subsequence_On_Wrap_Trigger_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Stop_Base_Subsequence_On_Wrap_Trigger_DEF (0x00000000) + +#define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_REG (0x0000481C) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Number_of_Cachelines_OFF ( 0) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Number_of_Cachelines_WID ( 7) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Number_of_Cachelines_MSK (0x0000007F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Number_of_Cachelines_MAX (0x0000007F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Number_of_Cachelines_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Number_of_Cachelines_Scale_OFF ( 7) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Number_of_Cachelines_Scale_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Number_of_Cachelines_Scale_MSK (0x00000080) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Number_of_Cachelines_Scale_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Number_of_Cachelines_Scale_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Subsequence_Wait_OFF ( 8) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Subsequence_Wait_WID (10) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Subsequence_Wait_MSK (0x0003FF00) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Subsequence_Wait_MAX (0x000003FF) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Subsequence_Wait_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Subsequence_Type_OFF (20) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Subsequence_Type_WID ( 4) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Subsequence_Type_MSK (0x00F00000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Subsequence_Type_MAX (0x0000000F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Subsequence_Type_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Save_Current_Base_Address_To_Start_OFF (25) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Save_Current_Base_Address_To_Start_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Save_Current_Base_Address_To_Start_MSK (0x02000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Save_Current_Base_Address_To_Start_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Save_Current_Base_Address_To_Start_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Reset_Current_Base_Address_To_Start_OFF (26) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Reset_Current_Base_Address_To_Start_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Reset_Current_Base_Address_To_Start_MSK (0x04000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Reset_Current_Base_Address_To_Start_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Reset_Current_Base_Address_To_Start_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Data_and_ECC_Address_Inversion_OFF (27) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Data_and_ECC_Address_Inversion_WID ( 2) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Data_and_ECC_Address_Inversion_MSK (0x18000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Data_and_ECC_Address_Inversion_MAX (0x00000003) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Data_and_ECC_Address_Inversion_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Invert_Data_and_ECC_OFF (30) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Invert_Data_and_ECC_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Invert_Data_and_ECC_MSK (0x40000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Invert_Data_and_ECC_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Invert_Data_and_ECC_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_OFF (31) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_MSK (0x80000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_DEF (0x00000000) + + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Number_of_Cachelines_OFF ( 0) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Number_of_Cachelines_WID ( 7) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Number_of_Cachelines_MSK (0x0000007F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Number_of_Cachelines_MAX (0x0000007F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Number_of_Cachelines_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Number_of_Cachelines_Scale_OFF ( 7) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Number_of_Cachelines_Scale_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Number_of_Cachelines_Scale_MSK (0x00000080) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Number_of_Cachelines_Scale_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Number_of_Cachelines_Scale_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Subsequence_Wait_OFF ( 8) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Subsequence_Wait_WID (14) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Subsequence_Wait_MSK (0x003FFF00) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Subsequence_Wait_MAX (0x00003FFF) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Subsequence_Wait_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Subsequence_Type_OFF (22) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Subsequence_Type_WID ( 4) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Subsequence_Type_MSK (0x03C00000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Subsequence_Type_MAX (0x0000000F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Subsequence_Type_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Save_Current_Base_Address_To_Start_OFF (26) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Save_Current_Base_Address_To_Start_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Save_Current_Base_Address_To_Start_MSK (0x04000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Save_Current_Base_Address_To_Start_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Save_Current_Base_Address_To_Start_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Reset_Current_Base_Address_To_Start_OFF (27) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Reset_Current_Base_Address_To_Start_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Reset_Current_Base_Address_To_Start_MSK (0x08000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Reset_Current_Base_Address_To_Start_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Reset_Current_Base_Address_To_Start_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Data_and_ECC_Address_Inversion_OFF (28) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Data_and_ECC_Address_Inversion_WID ( 2) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Data_and_ECC_Address_Inversion_MSK (0x30000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Data_and_ECC_Address_Inversion_MAX (0x00000003) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Data_and_ECC_Address_Inversion_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Invert_Data_and_ECC_OFF (30) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Invert_Data_and_ECC_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Invert_Data_and_ECC_MSK (0x40000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Invert_Data_and_ECC_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Invert_Data_and_ECC_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Stop_Base_Subsequence_On_Wrap_Trigger_OFF (31) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Stop_Base_Subsequence_On_Wrap_Trigger_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Stop_Base_Subsequence_On_Wrap_Trigger_MSK (0x80000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Stop_Base_Subsequence_On_Wrap_Trigger_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Stop_Base_Subsequence_On_Wrap_Trigger_DEF (0x00000000) + +#define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_REG (0x00004820) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Number_of_Cachelines_OFF ( 0) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Number_of_Cachelines_WID ( 7) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Number_of_Cachelines_MSK (0x0000007F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Number_of_Cachelines_MAX (0x0000007F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Number_of_Cachelines_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Number_of_Cachelines_Scale_OFF ( 7) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Number_of_Cachelines_Scale_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Number_of_Cachelines_Scale_MSK (0x00000080) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Number_of_Cachelines_Scale_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Number_of_Cachelines_Scale_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Subsequence_Wait_OFF ( 8) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Subsequence_Wait_WID (10) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Subsequence_Wait_MSK (0x0003FF00) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Subsequence_Wait_MAX (0x000003FF) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Subsequence_Wait_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Subsequence_Type_OFF (20) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Subsequence_Type_WID ( 4) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Subsequence_Type_MSK (0x00F00000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Subsequence_Type_MAX (0x0000000F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Subsequence_Type_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Save_Current_Base_Address_To_Start_OFF (25) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Save_Current_Base_Address_To_Start_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Save_Current_Base_Address_To_Start_MSK (0x02000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Save_Current_Base_Address_To_Start_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Save_Current_Base_Address_To_Start_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Reset_Current_Base_Address_To_Start_OFF (26) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Reset_Current_Base_Address_To_Start_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Reset_Current_Base_Address_To_Start_MSK (0x04000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Reset_Current_Base_Address_To_Start_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Reset_Current_Base_Address_To_Start_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Data_and_ECC_Address_Inversion_OFF (27) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Data_and_ECC_Address_Inversion_WID ( 2) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Data_and_ECC_Address_Inversion_MSK (0x18000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Data_and_ECC_Address_Inversion_MAX (0x00000003) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Data_and_ECC_Address_Inversion_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Invert_Data_and_ECC_OFF (30) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Invert_Data_and_ECC_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Invert_Data_and_ECC_MSK (0x40000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Invert_Data_and_ECC_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Invert_Data_and_ECC_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_OFF (31) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_MSK (0x80000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_DEF (0x00000000) + + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Number_of_Cachelines_OFF ( 0) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Number_of_Cachelines_WID ( 7) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Number_of_Cachelines_MSK (0x0000007F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Number_of_Cachelines_MAX (0x0000007F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Number_of_Cachelines_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Number_of_Cachelines_Scale_OFF ( 7) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Number_of_Cachelines_Scale_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Number_of_Cachelines_Scale_MSK (0x00000080) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Number_of_Cachelines_Scale_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Number_of_Cachelines_Scale_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Subsequence_Wait_OFF ( 8) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Subsequence_Wait_WID (14) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Subsequence_Wait_MSK (0x003FFF00) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Subsequence_Wait_MAX (0x00003FFF) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Subsequence_Wait_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Subsequence_Type_OFF (22) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Subsequence_Type_WID ( 4) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Subsequence_Type_MSK (0x03C00000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Subsequence_Type_MAX (0x0000000F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Subsequence_Type_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Save_Current_Base_Address_To_Start_OFF (26) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Save_Current_Base_Address_To_Start_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Save_Current_Base_Address_To_Start_MSK (0x04000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Save_Current_Base_Address_To_Start_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Save_Current_Base_Address_To_Start_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Reset_Current_Base_Address_To_Start_OFF (27) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Reset_Current_Base_Address_To_Start_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Reset_Current_Base_Address_To_Start_MSK (0x08000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Reset_Current_Base_Address_To_Start_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Reset_Current_Base_Address_To_Start_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Data_and_ECC_Address_Inversion_OFF (28) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Data_and_ECC_Address_Inversion_WID ( 2) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Data_and_ECC_Address_Inversion_MSK (0x30000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Data_and_ECC_Address_Inversion_MAX (0x00000003) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Data_and_ECC_Address_Inversion_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Invert_Data_and_ECC_OFF (30) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Invert_Data_and_ECC_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Invert_Data_and_ECC_MSK (0x40000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Invert_Data_and_ECC_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Invert_Data_and_ECC_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Stop_Base_Subsequence_On_Wrap_Trigger_OFF (31) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Stop_Base_Subsequence_On_Wrap_Trigger_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Stop_Base_Subsequence_On_Wrap_Trigger_MSK (0x80000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Stop_Base_Subsequence_On_Wrap_Trigger_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Stop_Base_Subsequence_On_Wrap_Trigger_DEF (0x00000000) + +#define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_REG (0x00004824) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Number_of_Cachelines_OFF ( 0) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Number_of_Cachelines_WID ( 7) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Number_of_Cachelines_MSK (0x0000007F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Number_of_Cachelines_MAX (0x0000007F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Number_of_Cachelines_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Number_of_Cachelines_Scale_OFF ( 7) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Number_of_Cachelines_Scale_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Number_of_Cachelines_Scale_MSK (0x00000080) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Number_of_Cachelines_Scale_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Number_of_Cachelines_Scale_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Subsequence_Wait_OFF ( 8) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Subsequence_Wait_WID (10) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Subsequence_Wait_MSK (0x0003FF00) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Subsequence_Wait_MAX (0x000003FF) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Subsequence_Wait_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Subsequence_Type_OFF (20) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Subsequence_Type_WID ( 4) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Subsequence_Type_MSK (0x00F00000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Subsequence_Type_MAX (0x0000000F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Subsequence_Type_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Save_Current_Base_Address_To_Start_OFF (25) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Save_Current_Base_Address_To_Start_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Save_Current_Base_Address_To_Start_MSK (0x02000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Save_Current_Base_Address_To_Start_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Save_Current_Base_Address_To_Start_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Reset_Current_Base_Address_To_Start_OFF (26) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Reset_Current_Base_Address_To_Start_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Reset_Current_Base_Address_To_Start_MSK (0x04000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Reset_Current_Base_Address_To_Start_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Reset_Current_Base_Address_To_Start_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Data_and_ECC_Address_Inversion_OFF (27) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Data_and_ECC_Address_Inversion_WID ( 2) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Data_and_ECC_Address_Inversion_MSK (0x18000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Data_and_ECC_Address_Inversion_MAX (0x00000003) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Data_and_ECC_Address_Inversion_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Invert_Data_and_ECC_OFF (30) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Invert_Data_and_ECC_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Invert_Data_and_ECC_MSK (0x40000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Invert_Data_and_ECC_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Invert_Data_and_ECC_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_OFF (31) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_MSK (0x80000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_DEF (0x00000000) + + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Number_of_Cachelines_OFF ( 0) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Number_of_Cachelines_WID ( 7) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Number_of_Cachelines_MSK (0x0000007F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Number_of_Cachelines_MAX (0x0000007F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Number_of_Cachelines_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Number_of_Cachelines_Scale_OFF ( 7) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Number_of_Cachelines_Scale_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Number_of_Cachelines_Scale_MSK (0x00000080) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Number_of_Cachelines_Scale_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Number_of_Cachelines_Scale_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Subsequence_Wait_OFF ( 8) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Subsequence_Wait_WID (14) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Subsequence_Wait_MSK (0x003FFF00) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Subsequence_Wait_MAX (0x00003FFF) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Subsequence_Wait_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Subsequence_Type_OFF (22) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Subsequence_Type_WID ( 4) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Subsequence_Type_MSK (0x03C00000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Subsequence_Type_MAX (0x0000000F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Subsequence_Type_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Save_Current_Base_Address_To_Start_OFF (26) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Save_Current_Base_Address_To_Start_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Save_Current_Base_Address_To_Start_MSK (0x04000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Save_Current_Base_Address_To_Start_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Save_Current_Base_Address_To_Start_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Reset_Current_Base_Address_To_Start_OFF (27) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Reset_Current_Base_Address_To_Start_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Reset_Current_Base_Address_To_Start_MSK (0x08000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Reset_Current_Base_Address_To_Start_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Reset_Current_Base_Address_To_Start_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Data_and_ECC_Address_Inversion_OFF (28) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Data_and_ECC_Address_Inversion_WID ( 2) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Data_and_ECC_Address_Inversion_MSK (0x30000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Data_and_ECC_Address_Inversion_MAX (0x00000003) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Data_and_ECC_Address_Inversion_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Invert_Data_and_ECC_OFF (30) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Invert_Data_and_ECC_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Invert_Data_and_ECC_MSK (0x40000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Invert_Data_and_ECC_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Invert_Data_and_ECC_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Stop_Base_Subsequence_On_Wrap_Trigger_OFF (31) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Stop_Base_Subsequence_On_Wrap_Trigger_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Stop_Base_Subsequence_On_Wrap_Trigger_MSK (0x80000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Stop_Base_Subsequence_On_Wrap_Trigger_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Stop_Base_Subsequence_On_Wrap_Trigger_DEF (0x00000000) + +#define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_REG (0x00004830) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Number_of_Cachelines_OFF ( 0) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Number_of_Cachelines_WID ( 7) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Number_of_Cachelines_MSK (0x0000007F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Number_of_Cachelines_MAX (0x0000007F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Number_of_Cachelines_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Number_of_Cachelines_Scale_OFF ( 7) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Number_of_Cachelines_Scale_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Number_of_Cachelines_Scale_MSK (0x00000080) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Number_of_Cachelines_Scale_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Number_of_Cachelines_Scale_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Subsequence_Wait_OFF ( 8) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Subsequence_Wait_WID ( 8) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Subsequence_Wait_MSK (0x0000FF00) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Subsequence_Wait_MAX (0x000000FF) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Subsequence_Wait_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Subsequence_Type_OFF (20) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Subsequence_Type_WID ( 4) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Subsequence_Type_MSK (0x00F00000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Subsequence_Type_MAX (0x0000000F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Subsequence_Type_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Save_Current_Base_Address_To_Start_OFF (25) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Save_Current_Base_Address_To_Start_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Save_Current_Base_Address_To_Start_MSK (0x02000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Save_Current_Base_Address_To_Start_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Save_Current_Base_Address_To_Start_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Reset_Current_Base_Address_To_Start_OFF (26) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Reset_Current_Base_Address_To_Start_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Reset_Current_Base_Address_To_Start_MSK (0x04000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Reset_Current_Base_Address_To_Start_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Reset_Current_Base_Address_To_Start_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Data_and_ECC_Address_Inversion_OFF (27) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Data_and_ECC_Address_Inversion_WID ( 2) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Data_and_ECC_Address_Inversion_MSK (0x18000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Data_and_ECC_Address_Inversion_MAX (0x00000003) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Data_and_ECC_Address_Inversion_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Invert_Data_and_ECC_OFF (30) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Invert_Data_and_ECC_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Invert_Data_and_ECC_MSK (0x40000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Invert_Data_and_ECC_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Invert_Data_and_ECC_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_OFF (31) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_MSK (0x80000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_DEF (0x00000000) + + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Number_of_Cachelines_OFF ( 0) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Number_of_Cachelines_WID ( 7) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Number_of_Cachelines_MSK (0x0000007F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Number_of_Cachelines_MAX (0x0000007F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Number_of_Cachelines_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Number_of_Cachelines_Scale_OFF ( 7) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Number_of_Cachelines_Scale_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Number_of_Cachelines_Scale_MSK (0x00000080) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Number_of_Cachelines_Scale_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Number_of_Cachelines_Scale_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Subsequence_Wait_OFF ( 8) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Subsequence_Wait_WID (14) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Subsequence_Wait_MSK (0x003FFF00) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Subsequence_Wait_MAX (0x00003FFF) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Subsequence_Wait_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Subsequence_Type_OFF (22) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Subsequence_Type_WID ( 4) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Subsequence_Type_MSK (0x03C00000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Subsequence_Type_MAX (0x0000000F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Subsequence_Type_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Save_Current_Base_Address_To_Start_OFF (26) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Save_Current_Base_Address_To_Start_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Save_Current_Base_Address_To_Start_MSK (0x04000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Save_Current_Base_Address_To_Start_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Save_Current_Base_Address_To_Start_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Reset_Current_Base_Address_To_Start_OFF (27) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Reset_Current_Base_Address_To_Start_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Reset_Current_Base_Address_To_Start_MSK (0x08000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Reset_Current_Base_Address_To_Start_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Reset_Current_Base_Address_To_Start_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Data_and_ECC_Address_Inversion_OFF (28) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Data_and_ECC_Address_Inversion_WID ( 2) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Data_and_ECC_Address_Inversion_MSK (0x30000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Data_and_ECC_Address_Inversion_MAX (0x00000003) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Data_and_ECC_Address_Inversion_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Invert_Data_and_ECC_OFF (30) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Invert_Data_and_ECC_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Invert_Data_and_ECC_MSK (0x40000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Invert_Data_and_ECC_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Invert_Data_and_ECC_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Stop_Base_Subsequence_On_Wrap_Trigger_OFF (31) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Stop_Base_Subsequence_On_Wrap_Trigger_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Stop_Base_Subsequence_On_Wrap_Trigger_MSK (0x80000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Stop_Base_Subsequence_On_Wrap_Trigger_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Stop_Base_Subsequence_On_Wrap_Trigger_DEF (0x00000000) + +#define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_REG (0x00004834) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Number_of_Cachelines_OFF ( 0) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Number_of_Cachelines_WID ( 7) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Number_of_Cachelines_MSK (0x0000007F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Number_of_Cachelines_MAX (0x0000007F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Number_of_Cachelines_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Number_of_Cachelines_Scale_OFF ( 7) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Number_of_Cachelines_Scale_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Number_of_Cachelines_Scale_MSK (0x00000080) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Number_of_Cachelines_Scale_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Number_of_Cachelines_Scale_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Subsequence_Wait_OFF ( 8) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Subsequence_Wait_WID ( 8) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Subsequence_Wait_MSK (0x0000FF00) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Subsequence_Wait_MAX (0x000000FF) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Subsequence_Wait_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Subsequence_Type_OFF (20) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Subsequence_Type_WID ( 4) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Subsequence_Type_MSK (0x00F00000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Subsequence_Type_MAX (0x0000000F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Subsequence_Type_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Save_Current_Base_Address_To_Start_OFF (25) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Save_Current_Base_Address_To_Start_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Save_Current_Base_Address_To_Start_MSK (0x02000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Save_Current_Base_Address_To_Start_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Save_Current_Base_Address_To_Start_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Reset_Current_Base_Address_To_Start_OFF (26) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Reset_Current_Base_Address_To_Start_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Reset_Current_Base_Address_To_Start_MSK (0x04000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Reset_Current_Base_Address_To_Start_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Reset_Current_Base_Address_To_Start_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Data_and_ECC_Address_Inversion_OFF (27) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Data_and_ECC_Address_Inversion_WID ( 2) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Data_and_ECC_Address_Inversion_MSK (0x18000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Data_and_ECC_Address_Inversion_MAX (0x00000003) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Data_and_ECC_Address_Inversion_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Invert_Data_and_ECC_OFF (30) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Invert_Data_and_ECC_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Invert_Data_and_ECC_MSK (0x40000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Invert_Data_and_ECC_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Invert_Data_and_ECC_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_OFF (31) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_MSK (0x80000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_DEF (0x00000000) + + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Number_of_Cachelines_OFF ( 0) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Number_of_Cachelines_WID ( 7) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Number_of_Cachelines_MSK (0x0000007F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Number_of_Cachelines_MAX (0x0000007F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Number_of_Cachelines_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Number_of_Cachelines_Scale_OFF ( 7) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Number_of_Cachelines_Scale_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Number_of_Cachelines_Scale_MSK (0x00000080) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Number_of_Cachelines_Scale_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Number_of_Cachelines_Scale_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Subsequence_Wait_OFF ( 8) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Subsequence_Wait_WID (14) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Subsequence_Wait_MSK (0x003FFF00) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Subsequence_Wait_MAX (0x00003FFF) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Subsequence_Wait_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Subsequence_Type_OFF (22) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Subsequence_Type_WID ( 4) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Subsequence_Type_MSK (0x03C00000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Subsequence_Type_MAX (0x0000000F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Subsequence_Type_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Save_Current_Base_Address_To_Start_OFF (26) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Save_Current_Base_Address_To_Start_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Save_Current_Base_Address_To_Start_MSK (0x04000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Save_Current_Base_Address_To_Start_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Save_Current_Base_Address_To_Start_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Reset_Current_Base_Address_To_Start_OFF (27) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Reset_Current_Base_Address_To_Start_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Reset_Current_Base_Address_To_Start_MSK (0x08000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Reset_Current_Base_Address_To_Start_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Reset_Current_Base_Address_To_Start_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Data_and_ECC_Address_Inversion_OFF (28) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Data_and_ECC_Address_Inversion_WID ( 2) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Data_and_ECC_Address_Inversion_MSK (0x30000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Data_and_ECC_Address_Inversion_MAX (0x00000003) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Data_and_ECC_Address_Inversion_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Invert_Data_and_ECC_OFF (30) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Invert_Data_and_ECC_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Invert_Data_and_ECC_MSK (0x40000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Invert_Data_and_ECC_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Invert_Data_and_ECC_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Stop_Base_Subsequence_On_Wrap_Trigger_OFF (31) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Stop_Base_Subsequence_On_Wrap_Trigger_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Stop_Base_Subsequence_On_Wrap_Trigger_MSK (0x80000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Stop_Base_Subsequence_On_Wrap_Trigger_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Stop_Base_Subsequence_On_Wrap_Trigger_DEF (0x00000000) + +#define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_REG (0x00004838) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Number_of_Cachelines_OFF ( 0) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Number_of_Cachelines_WID ( 7) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Number_of_Cachelines_MSK (0x0000007F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Number_of_Cachelines_MAX (0x0000007F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Number_of_Cachelines_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Number_of_Cachelines_Scale_OFF ( 7) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Number_of_Cachelines_Scale_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Number_of_Cachelines_Scale_MSK (0x00000080) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Number_of_Cachelines_Scale_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Number_of_Cachelines_Scale_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Subsequence_Wait_OFF ( 8) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Subsequence_Wait_WID ( 8) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Subsequence_Wait_MSK (0x0000FF00) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Subsequence_Wait_MAX (0x000000FF) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Subsequence_Wait_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Subsequence_Type_OFF (20) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Subsequence_Type_WID ( 4) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Subsequence_Type_MSK (0x00F00000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Subsequence_Type_MAX (0x0000000F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Subsequence_Type_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Save_Current_Base_Address_To_Start_OFF (25) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Save_Current_Base_Address_To_Start_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Save_Current_Base_Address_To_Start_MSK (0x02000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Save_Current_Base_Address_To_Start_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Save_Current_Base_Address_To_Start_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Reset_Current_Base_Address_To_Start_OFF (26) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Reset_Current_Base_Address_To_Start_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Reset_Current_Base_Address_To_Start_MSK (0x04000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Reset_Current_Base_Address_To_Start_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Reset_Current_Base_Address_To_Start_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Data_and_ECC_Address_Inversion_OFF (27) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Data_and_ECC_Address_Inversion_WID ( 2) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Data_and_ECC_Address_Inversion_MSK (0x18000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Data_and_ECC_Address_Inversion_MAX (0x00000003) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Data_and_ECC_Address_Inversion_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Invert_Data_and_ECC_OFF (30) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Invert_Data_and_ECC_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Invert_Data_and_ECC_MSK (0x40000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Invert_Data_and_ECC_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Invert_Data_and_ECC_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_OFF (31) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_MSK (0x80000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Stop_Base_Subsequence_On_Wrap_Trigger_DEF (0x00000000) + + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Number_of_Cachelines_OFF ( 0) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Number_of_Cachelines_WID ( 7) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Number_of_Cachelines_MSK (0x0000007F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Number_of_Cachelines_MAX (0x0000007F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Number_of_Cachelines_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Number_of_Cachelines_Scale_OFF ( 7) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Number_of_Cachelines_Scale_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Number_of_Cachelines_Scale_MSK (0x00000080) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Number_of_Cachelines_Scale_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Number_of_Cachelines_Scale_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Subsequence_Wait_OFF ( 8) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Subsequence_Wait_WID (14) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Subsequence_Wait_MSK (0x003FFF00) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Subsequence_Wait_MAX (0x00003FFF) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Subsequence_Wait_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Subsequence_Type_OFF (22) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Subsequence_Type_WID ( 4) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Subsequence_Type_MSK (0x03C00000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Subsequence_Type_MAX (0x0000000F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Subsequence_Type_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Save_Current_Base_Address_To_Start_OFF (26) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Save_Current_Base_Address_To_Start_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Save_Current_Base_Address_To_Start_MSK (0x04000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Save_Current_Base_Address_To_Start_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Save_Current_Base_Address_To_Start_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Reset_Current_Base_Address_To_Start_OFF (27) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Reset_Current_Base_Address_To_Start_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Reset_Current_Base_Address_To_Start_MSK (0x08000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Reset_Current_Base_Address_To_Start_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Reset_Current_Base_Address_To_Start_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Data_and_ECC_Address_Inversion_OFF (28) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Data_and_ECC_Address_Inversion_WID ( 2) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Data_and_ECC_Address_Inversion_MSK (0x30000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Data_and_ECC_Address_Inversion_MAX (0x00000003) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Data_and_ECC_Address_Inversion_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Invert_Data_and_ECC_OFF (30) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Invert_Data_and_ECC_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Invert_Data_and_ECC_MSK (0x40000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Invert_Data_and_ECC_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Invert_Data_and_ECC_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Stop_Base_Subsequence_On_Wrap_Trigger_OFF (31) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Stop_Base_Subsequence_On_Wrap_Trigger_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Stop_Base_Subsequence_On_Wrap_Trigger_MSK (0x80000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Stop_Base_Subsequence_On_Wrap_Trigger_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Stop_Base_Subsequence_On_Wrap_Trigger_DEF (0x00000000) + +#define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_REG (0x0000483C) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Number_of_Cachelines_OFF ( 0) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Number_of_Cachelines_WID ( 7) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Number_of_Cachelines_MSK (0x0000007F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Number_of_Cachelines_MAX (0x0000007F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Number_of_Cachelines_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Number_of_Cachelines_Scale_OFF ( 7) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Number_of_Cachelines_Scale_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Number_of_Cachelines_Scale_MSK (0x00000080) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Number_of_Cachelines_Scale_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Number_of_Cachelines_Scale_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Subsequence_Wait_OFF ( 8) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Subsequence_Wait_WID ( 8) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Subsequence_Wait_MSK (0x0000FF00) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Subsequence_Wait_MAX (0x000000FF) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Subsequence_Wait_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Subsequence_Type_OFF (20) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Subsequence_Type_WID ( 4) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Subsequence_Type_MSK (0x00F00000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Subsequence_Type_MAX (0x0000000F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Subsequence_Type_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Save_Current_Base_Address_To_Start_OFF (25) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Save_Current_Base_Address_To_Start_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Save_Current_Base_Address_To_Start_MSK (0x02000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Save_Current_Base_Address_To_Start_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Save_Current_Base_Address_To_Start_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Reset_Current_Base_Address_To_Start_OFF (26) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Reset_Current_Base_Address_To_Start_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Reset_Current_Base_Address_To_Start_MSK (0x04000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Reset_Current_Base_Address_To_Start_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Reset_Current_Base_Address_To_Start_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Data_and_ECC_Address_Inversion_OFF (27) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Data_and_ECC_Address_Inversion_WID ( 2) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Data_and_ECC_Address_Inversion_MSK (0x18000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Data_and_ECC_Address_Inversion_MAX (0x00000003) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Data_and_ECC_Address_Inversion_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Invert_Data_and_ECC_OFF (30) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Invert_Data_and_ECC_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Invert_Data_and_ECC_MSK (0x40000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Invert_Data_and_ECC_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Invert_Data_and_ECC_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_OFF (31) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_MSK (0x80000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_DEF (0x00000000) + + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Number_of_Cachelines_OFF ( 0) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Number_of_Cachelines_WID ( 7) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Number_of_Cachelines_MSK (0x0000007F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Number_of_Cachelines_MAX (0x0000007F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Number_of_Cachelines_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Number_of_Cachelines_Scale_OFF ( 7) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Number_of_Cachelines_Scale_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Number_of_Cachelines_Scale_MSK (0x00000080) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Number_of_Cachelines_Scale_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Number_of_Cachelines_Scale_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Subsequence_Wait_OFF ( 8) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Subsequence_Wait_WID (14) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Subsequence_Wait_MSK (0x003FFF00) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Subsequence_Wait_MAX (0x00003FFF) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Subsequence_Wait_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Subsequence_Type_OFF (22) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Subsequence_Type_WID ( 4) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Subsequence_Type_MSK (0x03C00000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Subsequence_Type_MAX (0x0000000F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Subsequence_Type_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Save_Current_Base_Address_To_Start_OFF (26) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Save_Current_Base_Address_To_Start_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Save_Current_Base_Address_To_Start_MSK (0x04000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Save_Current_Base_Address_To_Start_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Save_Current_Base_Address_To_Start_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Reset_Current_Base_Address_To_Start_OFF (27) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Reset_Current_Base_Address_To_Start_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Reset_Current_Base_Address_To_Start_MSK (0x08000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Reset_Current_Base_Address_To_Start_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Reset_Current_Base_Address_To_Start_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Data_and_ECC_Address_Inversion_OFF (28) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Data_and_ECC_Address_Inversion_WID ( 2) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Data_and_ECC_Address_Inversion_MSK (0x30000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Data_and_ECC_Address_Inversion_MAX (0x00000003) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Data_and_ECC_Address_Inversion_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Invert_Data_and_ECC_OFF (30) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Invert_Data_and_ECC_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Invert_Data_and_ECC_MSK (0x40000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Invert_Data_and_ECC_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Invert_Data_and_ECC_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Stop_Base_Subsequence_On_Wrap_Trigger_OFF (31) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Stop_Base_Subsequence_On_Wrap_Trigger_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Stop_Base_Subsequence_On_Wrap_Trigger_MSK (0x80000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Stop_Base_Subsequence_On_Wrap_Trigger_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Stop_Base_Subsequence_On_Wrap_Trigger_DEF (0x00000000) + +#define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_REG (0x00004840) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Number_of_Cachelines_OFF ( 0) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Number_of_Cachelines_WID ( 7) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Number_of_Cachelines_MSK (0x0000007F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Number_of_Cachelines_MAX (0x0000007F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Number_of_Cachelines_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Number_of_Cachelines_Scale_OFF ( 7) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Number_of_Cachelines_Scale_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Number_of_Cachelines_Scale_MSK (0x00000080) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Number_of_Cachelines_Scale_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Number_of_Cachelines_Scale_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Subsequence_Wait_OFF ( 8) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Subsequence_Wait_WID ( 8) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Subsequence_Wait_MSK (0x0000FF00) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Subsequence_Wait_MAX (0x000000FF) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Subsequence_Wait_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Subsequence_Type_OFF (20) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Subsequence_Type_WID ( 4) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Subsequence_Type_MSK (0x00F00000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Subsequence_Type_MAX (0x0000000F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Subsequence_Type_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Save_Current_Base_Address_To_Start_OFF (25) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Save_Current_Base_Address_To_Start_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Save_Current_Base_Address_To_Start_MSK (0x02000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Save_Current_Base_Address_To_Start_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Save_Current_Base_Address_To_Start_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Reset_Current_Base_Address_To_Start_OFF (26) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Reset_Current_Base_Address_To_Start_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Reset_Current_Base_Address_To_Start_MSK (0x04000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Reset_Current_Base_Address_To_Start_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Reset_Current_Base_Address_To_Start_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Data_and_ECC_Address_Inversion_OFF (27) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Data_and_ECC_Address_Inversion_WID ( 2) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Data_and_ECC_Address_Inversion_MSK (0x18000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Data_and_ECC_Address_Inversion_MAX (0x00000003) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Data_and_ECC_Address_Inversion_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Invert_Data_and_ECC_OFF (30) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Invert_Data_and_ECC_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Invert_Data_and_ECC_MSK (0x40000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Invert_Data_and_ECC_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Invert_Data_and_ECC_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_OFF (31) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_MSK (0x80000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_DEF (0x00000000) + + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Number_of_Cachelines_OFF ( 0) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Number_of_Cachelines_WID ( 7) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Number_of_Cachelines_MSK (0x0000007F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Number_of_Cachelines_MAX (0x0000007F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Number_of_Cachelines_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Number_of_Cachelines_Scale_OFF ( 7) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Number_of_Cachelines_Scale_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Number_of_Cachelines_Scale_MSK (0x00000080) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Number_of_Cachelines_Scale_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Number_of_Cachelines_Scale_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Subsequence_Wait_OFF ( 8) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Subsequence_Wait_WID (14) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Subsequence_Wait_MSK (0x003FFF00) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Subsequence_Wait_MAX (0x00003FFF) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Subsequence_Wait_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Subsequence_Type_OFF (22) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Subsequence_Type_WID ( 4) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Subsequence_Type_MSK (0x03C00000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Subsequence_Type_MAX (0x0000000F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Subsequence_Type_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Save_Current_Base_Address_To_Start_OFF (26) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Save_Current_Base_Address_To_Start_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Save_Current_Base_Address_To_Start_MSK (0x04000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Save_Current_Base_Address_To_Start_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Save_Current_Base_Address_To_Start_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Reset_Current_Base_Address_To_Start_OFF (27) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Reset_Current_Base_Address_To_Start_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Reset_Current_Base_Address_To_Start_MSK (0x08000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Reset_Current_Base_Address_To_Start_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Reset_Current_Base_Address_To_Start_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Data_and_ECC_Address_Inversion_OFF (28) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Data_and_ECC_Address_Inversion_WID ( 2) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Data_and_ECC_Address_Inversion_MSK (0x30000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Data_and_ECC_Address_Inversion_MAX (0x00000003) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Data_and_ECC_Address_Inversion_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Invert_Data_and_ECC_OFF (30) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Invert_Data_and_ECC_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Invert_Data_and_ECC_MSK (0x40000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Invert_Data_and_ECC_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Invert_Data_and_ECC_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Stop_Base_Subsequence_On_Wrap_Trigger_OFF (31) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Stop_Base_Subsequence_On_Wrap_Trigger_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Stop_Base_Subsequence_On_Wrap_Trigger_MSK (0x80000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Stop_Base_Subsequence_On_Wrap_Trigger_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Stop_Base_Subsequence_On_Wrap_Trigger_DEF (0x00000000) + +#define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_REG (0x00004844) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Number_of_Cachelines_OFF ( 0) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Number_of_Cachelines_WID ( 7) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Number_of_Cachelines_MSK (0x0000007F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Number_of_Cachelines_MAX (0x0000007F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Number_of_Cachelines_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Number_of_Cachelines_Scale_OFF ( 7) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Number_of_Cachelines_Scale_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Number_of_Cachelines_Scale_MSK (0x00000080) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Number_of_Cachelines_Scale_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Number_of_Cachelines_Scale_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Subsequence_Wait_OFF ( 8) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Subsequence_Wait_WID ( 8) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Subsequence_Wait_MSK (0x0000FF00) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Subsequence_Wait_MAX (0x000000FF) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Subsequence_Wait_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Subsequence_Type_OFF (20) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Subsequence_Type_WID ( 4) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Subsequence_Type_MSK (0x00F00000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Subsequence_Type_MAX (0x0000000F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Subsequence_Type_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Save_Current_Base_Address_To_Start_OFF (25) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Save_Current_Base_Address_To_Start_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Save_Current_Base_Address_To_Start_MSK (0x02000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Save_Current_Base_Address_To_Start_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Save_Current_Base_Address_To_Start_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Reset_Current_Base_Address_To_Start_OFF (26) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Reset_Current_Base_Address_To_Start_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Reset_Current_Base_Address_To_Start_MSK (0x04000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Reset_Current_Base_Address_To_Start_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Reset_Current_Base_Address_To_Start_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Data_and_ECC_Address_Inversion_OFF (27) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Data_and_ECC_Address_Inversion_WID ( 2) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Data_and_ECC_Address_Inversion_MSK (0x18000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Data_and_ECC_Address_Inversion_MAX (0x00000003) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Data_and_ECC_Address_Inversion_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Invert_Data_and_ECC_OFF (30) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Invert_Data_and_ECC_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Invert_Data_and_ECC_MSK (0x40000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Invert_Data_and_ECC_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Invert_Data_and_ECC_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_OFF (31) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_MSK (0x80000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_DEF (0x00000000) + + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Number_of_Cachelines_OFF ( 0) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Number_of_Cachelines_WID ( 7) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Number_of_Cachelines_MSK (0x0000007F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Number_of_Cachelines_MAX (0x0000007F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Number_of_Cachelines_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Number_of_Cachelines_Scale_OFF ( 7) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Number_of_Cachelines_Scale_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Number_of_Cachelines_Scale_MSK (0x00000080) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Number_of_Cachelines_Scale_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Number_of_Cachelines_Scale_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Subsequence_Wait_OFF ( 8) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Subsequence_Wait_WID (14) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Subsequence_Wait_MSK (0x003FFF00) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Subsequence_Wait_MAX (0x00003FFF) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Subsequence_Wait_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Subsequence_Type_OFF (22) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Subsequence_Type_WID ( 4) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Subsequence_Type_MSK (0x03C00000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Subsequence_Type_MAX (0x0000000F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Subsequence_Type_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Save_Current_Base_Address_To_Start_OFF (26) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Save_Current_Base_Address_To_Start_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Save_Current_Base_Address_To_Start_MSK (0x04000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Save_Current_Base_Address_To_Start_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Save_Current_Base_Address_To_Start_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Reset_Current_Base_Address_To_Start_OFF (27) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Reset_Current_Base_Address_To_Start_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Reset_Current_Base_Address_To_Start_MSK (0x08000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Reset_Current_Base_Address_To_Start_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Reset_Current_Base_Address_To_Start_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Data_and_ECC_Address_Inversion_OFF (28) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Data_and_ECC_Address_Inversion_WID ( 2) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Data_and_ECC_Address_Inversion_MSK (0x30000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Data_and_ECC_Address_Inversion_MAX (0x00000003) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Data_and_ECC_Address_Inversion_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Invert_Data_and_ECC_OFF (30) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Invert_Data_and_ECC_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Invert_Data_and_ECC_MSK (0x40000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Invert_Data_and_ECC_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Invert_Data_and_ECC_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Stop_Base_Subsequence_On_Wrap_Trigger_OFF (31) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Stop_Base_Subsequence_On_Wrap_Trigger_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Stop_Base_Subsequence_On_Wrap_Trigger_MSK (0x80000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Stop_Base_Subsequence_On_Wrap_Trigger_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Stop_Base_Subsequence_On_Wrap_Trigger_DEF (0x00000000) + +#define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_REG (0x00004848) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Number_of_Cachelines_OFF ( 0) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Number_of_Cachelines_WID ( 7) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Number_of_Cachelines_MSK (0x0000007F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Number_of_Cachelines_MAX (0x0000007F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Number_of_Cachelines_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Number_of_Cachelines_Scale_OFF ( 7) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Number_of_Cachelines_Scale_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Number_of_Cachelines_Scale_MSK (0x00000080) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Number_of_Cachelines_Scale_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Number_of_Cachelines_Scale_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Subsequence_Wait_OFF ( 8) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Subsequence_Wait_WID ( 8) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Subsequence_Wait_MSK (0x0000FF00) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Subsequence_Wait_MAX (0x000000FF) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Subsequence_Wait_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Subsequence_Type_OFF (20) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Subsequence_Type_WID ( 4) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Subsequence_Type_MSK (0x00F00000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Subsequence_Type_MAX (0x0000000F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Subsequence_Type_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Save_Current_Base_Address_To_Start_OFF (25) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Save_Current_Base_Address_To_Start_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Save_Current_Base_Address_To_Start_MSK (0x02000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Save_Current_Base_Address_To_Start_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Save_Current_Base_Address_To_Start_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Reset_Current_Base_Address_To_Start_OFF (26) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Reset_Current_Base_Address_To_Start_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Reset_Current_Base_Address_To_Start_MSK (0x04000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Reset_Current_Base_Address_To_Start_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Reset_Current_Base_Address_To_Start_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Data_and_ECC_Address_Inversion_OFF (27) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Data_and_ECC_Address_Inversion_WID ( 2) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Data_and_ECC_Address_Inversion_MSK (0x18000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Data_and_ECC_Address_Inversion_MAX (0x00000003) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Data_and_ECC_Address_Inversion_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Invert_Data_and_ECC_OFF (30) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Invert_Data_and_ECC_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Invert_Data_and_ECC_MSK (0x40000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Invert_Data_and_ECC_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Invert_Data_and_ECC_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_OFF (31) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_MSK (0x80000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_DEF (0x00000000) + + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Number_of_Cachelines_OFF ( 0) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Number_of_Cachelines_WID ( 7) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Number_of_Cachelines_MSK (0x0000007F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Number_of_Cachelines_MAX (0x0000007F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Number_of_Cachelines_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Number_of_Cachelines_Scale_OFF ( 7) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Number_of_Cachelines_Scale_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Number_of_Cachelines_Scale_MSK (0x00000080) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Number_of_Cachelines_Scale_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Number_of_Cachelines_Scale_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Subsequence_Wait_OFF ( 8) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Subsequence_Wait_WID (14) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Subsequence_Wait_MSK (0x003FFF00) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Subsequence_Wait_MAX (0x00003FFF) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Subsequence_Wait_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Subsequence_Type_OFF (22) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Subsequence_Type_WID ( 4) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Subsequence_Type_MSK (0x03C00000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Subsequence_Type_MAX (0x0000000F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Subsequence_Type_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Save_Current_Base_Address_To_Start_OFF (26) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Save_Current_Base_Address_To_Start_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Save_Current_Base_Address_To_Start_MSK (0x04000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Save_Current_Base_Address_To_Start_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Save_Current_Base_Address_To_Start_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Reset_Current_Base_Address_To_Start_OFF (27) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Reset_Current_Base_Address_To_Start_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Reset_Current_Base_Address_To_Start_MSK (0x08000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Reset_Current_Base_Address_To_Start_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Reset_Current_Base_Address_To_Start_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Data_and_ECC_Address_Inversion_OFF (28) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Data_and_ECC_Address_Inversion_WID ( 2) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Data_and_ECC_Address_Inversion_MSK (0x30000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Data_and_ECC_Address_Inversion_MAX (0x00000003) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Data_and_ECC_Address_Inversion_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Invert_Data_and_ECC_OFF (30) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Invert_Data_and_ECC_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Invert_Data_and_ECC_MSK (0x40000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Invert_Data_and_ECC_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Invert_Data_and_ECC_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Stop_Base_Subsequence_On_Wrap_Trigger_OFF (31) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Stop_Base_Subsequence_On_Wrap_Trigger_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Stop_Base_Subsequence_On_Wrap_Trigger_MSK (0x80000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Stop_Base_Subsequence_On_Wrap_Trigger_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Stop_Base_Subsequence_On_Wrap_Trigger_DEF (0x00000000) + +#define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_REG (0x0000484C) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Number_of_Cachelines_OFF ( 0) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Number_of_Cachelines_WID ( 7) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Number_of_Cachelines_MSK (0x0000007F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Number_of_Cachelines_MAX (0x0000007F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Number_of_Cachelines_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Number_of_Cachelines_Scale_OFF ( 7) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Number_of_Cachelines_Scale_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Number_of_Cachelines_Scale_MSK (0x00000080) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Number_of_Cachelines_Scale_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Number_of_Cachelines_Scale_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Subsequence_Wait_OFF ( 8) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Subsequence_Wait_WID ( 8) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Subsequence_Wait_MSK (0x0000FF00) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Subsequence_Wait_MAX (0x000000FF) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Subsequence_Wait_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Subsequence_Type_OFF (20) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Subsequence_Type_WID ( 4) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Subsequence_Type_MSK (0x00F00000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Subsequence_Type_MAX (0x0000000F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Subsequence_Type_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Save_Current_Base_Address_To_Start_OFF (25) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Save_Current_Base_Address_To_Start_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Save_Current_Base_Address_To_Start_MSK (0x02000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Save_Current_Base_Address_To_Start_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Save_Current_Base_Address_To_Start_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Reset_Current_Base_Address_To_Start_OFF (26) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Reset_Current_Base_Address_To_Start_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Reset_Current_Base_Address_To_Start_MSK (0x04000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Reset_Current_Base_Address_To_Start_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Reset_Current_Base_Address_To_Start_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Data_and_ECC_Address_Inversion_OFF (27) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Data_and_ECC_Address_Inversion_WID ( 2) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Data_and_ECC_Address_Inversion_MSK (0x18000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Data_and_ECC_Address_Inversion_MAX (0x00000003) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Data_and_ECC_Address_Inversion_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Invert_Data_and_ECC_OFF (30) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Invert_Data_and_ECC_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Invert_Data_and_ECC_MSK (0x40000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Invert_Data_and_ECC_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Invert_Data_and_ECC_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_OFF (31) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_MSK (0x80000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_DEF (0x00000000) + + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Number_of_Cachelines_OFF ( 0) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Number_of_Cachelines_WID ( 7) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Number_of_Cachelines_MSK (0x0000007F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Number_of_Cachelines_MAX (0x0000007F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Number_of_Cachelines_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Number_of_Cachelines_Scale_OFF ( 7) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Number_of_Cachelines_Scale_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Number_of_Cachelines_Scale_MSK (0x00000080) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Number_of_Cachelines_Scale_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Number_of_Cachelines_Scale_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Subsequence_Wait_OFF ( 8) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Subsequence_Wait_WID (14) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Subsequence_Wait_MSK (0x003FFF00) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Subsequence_Wait_MAX (0x00003FFF) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Subsequence_Wait_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Subsequence_Type_OFF (22) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Subsequence_Type_WID ( 4) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Subsequence_Type_MSK (0x03C00000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Subsequence_Type_MAX (0x0000000F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Subsequence_Type_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Save_Current_Base_Address_To_Start_OFF (26) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Save_Current_Base_Address_To_Start_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Save_Current_Base_Address_To_Start_MSK (0x04000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Save_Current_Base_Address_To_Start_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Save_Current_Base_Address_To_Start_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Reset_Current_Base_Address_To_Start_OFF (27) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Reset_Current_Base_Address_To_Start_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Reset_Current_Base_Address_To_Start_MSK (0x08000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Reset_Current_Base_Address_To_Start_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Reset_Current_Base_Address_To_Start_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Data_and_ECC_Address_Inversion_OFF (28) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Data_and_ECC_Address_Inversion_WID ( 2) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Data_and_ECC_Address_Inversion_MSK (0x30000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Data_and_ECC_Address_Inversion_MAX (0x00000003) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Data_and_ECC_Address_Inversion_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Invert_Data_and_ECC_OFF (30) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Invert_Data_and_ECC_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Invert_Data_and_ECC_MSK (0x40000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Invert_Data_and_ECC_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Invert_Data_and_ECC_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Stop_Base_Subsequence_On_Wrap_Trigger_OFF (31) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Stop_Base_Subsequence_On_Wrap_Trigger_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Stop_Base_Subsequence_On_Wrap_Trigger_MSK (0x80000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Stop_Base_Subsequence_On_Wrap_Trigger_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Stop_Base_Subsequence_On_Wrap_Trigger_DEF (0x00000000) + +#define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_REG (0x00004858) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Offset_Address_Update_Rate_OFF ( 0) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Offset_Address_Update_Rate_WID ( 5) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Offset_Address_Update_Rate_MSK (0x0000001F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Offset_Address_Update_Rate_MAX (0x0000001F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Offset_Address_Update_Rate_DEF (0x00000002) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Base_Subsequence_Repeat_Rate_OFF ( 8) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Base_Subsequence_Repeat_Rate_WID ( 5) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Base_Subsequence_Repeat_Rate_MSK (0x00001F00) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Base_Subsequence_Repeat_Rate_MAX (0x0000001F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Base_Subsequence_Repeat_Rate_DEF (0x00000002) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Column_Offset_Wrap_Trigger_Enable_OFF (15) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Column_Offset_Wrap_Trigger_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Column_Offset_Wrap_Trigger_Enable_MSK (0x00008000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Column_Offset_Wrap_Trigger_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Column_Offset_Wrap_Trigger_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Row_Offset_Wrap_Trigger_Enable_OFF (16) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Row_Offset_Wrap_Trigger_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Row_Offset_Wrap_Trigger_Enable_MSK (0x00010000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Row_Offset_Wrap_Trigger_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Row_Offset_Wrap_Trigger_Enable_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Base_Subsequence_Type_OFF (20) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Base_Subsequence_Type_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Base_Subsequence_Type_MSK (0x00100000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Base_Subsequence_Type_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Base_Subsequence_Type_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_CADB_Deselect_Enable_OFF (21) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_CADB_Deselect_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_CADB_Deselect_Enable_MSK (0x00200000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_CADB_Deselect_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_CADB_Deselect_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_CADB_Select_Enable_OFF (22) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_CADB_Select_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_CADB_Select_Enable_MSK (0x00400000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_CADB_Select_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_CADB_Select_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_CADB_Seeds_Save_Enable_OFF (23) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_CADB_Seeds_Save_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_CADB_Seeds_Save_Enable_MSK (0x00800000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_CADB_Seeds_Save_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_CADB_Seeds_Save_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Column_Increment_Order_OFF (24) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Column_Increment_Order_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Column_Increment_Order_MSK (0x01000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Column_Increment_Order_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Column_Increment_Order_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Column_Increment_Enable_OFF (26) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Column_Increment_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Column_Increment_Enable_MSK (0x04000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Column_Increment_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Column_Increment_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Row_Increment_Order_OFF (27) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Row_Increment_Order_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Row_Increment_Order_MSK (0x08000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Row_Increment_Order_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Row_Increment_Order_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Row_Increment_Enable_OFF (29) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Row_Increment_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Row_Increment_Enable_MSK (0x20000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Row_Increment_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Row_Increment_Enable_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Base_Invert_Data_and_ECC_OFF (30) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Base_Invert_Data_and_ECC_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Base_Invert_Data_and_ECC_MSK (0x40000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Base_Invert_Data_and_ECC_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Base_Invert_Data_and_ECC_DEF (0x00000000) + +#define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_REG (0x0000485C) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Offset_Address_Update_Rate_OFF ( 0) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Offset_Address_Update_Rate_WID ( 5) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Offset_Address_Update_Rate_MSK (0x0000001F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Offset_Address_Update_Rate_MAX (0x0000001F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Offset_Address_Update_Rate_DEF (0x00000002) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Base_Subsequence_Repeat_Rate_OFF ( 8) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Base_Subsequence_Repeat_Rate_WID ( 5) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Base_Subsequence_Repeat_Rate_MSK (0x00001F00) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Base_Subsequence_Repeat_Rate_MAX (0x0000001F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Base_Subsequence_Repeat_Rate_DEF (0x00000002) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Column_Offset_Wrap_Trigger_Enable_OFF (15) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Column_Offset_Wrap_Trigger_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Column_Offset_Wrap_Trigger_Enable_MSK (0x00008000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Column_Offset_Wrap_Trigger_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Column_Offset_Wrap_Trigger_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Row_Offset_Wrap_Trigger_Enable_OFF (16) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Row_Offset_Wrap_Trigger_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Row_Offset_Wrap_Trigger_Enable_MSK (0x00010000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Row_Offset_Wrap_Trigger_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Row_Offset_Wrap_Trigger_Enable_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Base_Subsequence_Type_OFF (20) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Base_Subsequence_Type_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Base_Subsequence_Type_MSK (0x00100000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Base_Subsequence_Type_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Base_Subsequence_Type_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_CADB_Deselect_Enable_OFF (21) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_CADB_Deselect_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_CADB_Deselect_Enable_MSK (0x00200000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_CADB_Deselect_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_CADB_Deselect_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_CADB_Select_Enable_OFF (22) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_CADB_Select_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_CADB_Select_Enable_MSK (0x00400000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_CADB_Select_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_CADB_Select_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_CADB_Seeds_Save_Enable_OFF (23) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_CADB_Seeds_Save_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_CADB_Seeds_Save_Enable_MSK (0x00800000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_CADB_Seeds_Save_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_CADB_Seeds_Save_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Column_Increment_Order_OFF (24) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Column_Increment_Order_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Column_Increment_Order_MSK (0x01000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Column_Increment_Order_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Column_Increment_Order_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Column_Increment_Enable_OFF (26) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Column_Increment_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Column_Increment_Enable_MSK (0x04000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Column_Increment_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Column_Increment_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Row_Increment_Order_OFF (27) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Row_Increment_Order_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Row_Increment_Order_MSK (0x08000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Row_Increment_Order_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Row_Increment_Order_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Row_Increment_Enable_OFF (29) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Row_Increment_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Row_Increment_Enable_MSK (0x20000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Row_Increment_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Row_Increment_Enable_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Base_Invert_Data_and_ECC_OFF (30) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Base_Invert_Data_and_ECC_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Base_Invert_Data_and_ECC_MSK (0x40000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Base_Invert_Data_and_ECC_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Base_Invert_Data_and_ECC_DEF (0x00000000) + +#define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_REG (0x00004860) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Offset_Address_Update_Rate_OFF ( 0) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Offset_Address_Update_Rate_WID ( 5) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Offset_Address_Update_Rate_MSK (0x0000001F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Offset_Address_Update_Rate_MAX (0x0000001F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Offset_Address_Update_Rate_DEF (0x00000002) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Base_Subsequence_Repeat_Rate_OFF ( 8) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Base_Subsequence_Repeat_Rate_WID ( 5) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Base_Subsequence_Repeat_Rate_MSK (0x00001F00) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Base_Subsequence_Repeat_Rate_MAX (0x0000001F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Base_Subsequence_Repeat_Rate_DEF (0x00000002) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Column_Offset_Wrap_Trigger_Enable_OFF (15) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Column_Offset_Wrap_Trigger_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Column_Offset_Wrap_Trigger_Enable_MSK (0x00008000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Column_Offset_Wrap_Trigger_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Column_Offset_Wrap_Trigger_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Row_Offset_Wrap_Trigger_Enable_OFF (16) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Row_Offset_Wrap_Trigger_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Row_Offset_Wrap_Trigger_Enable_MSK (0x00010000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Row_Offset_Wrap_Trigger_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Row_Offset_Wrap_Trigger_Enable_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Base_Subsequence_Type_OFF (20) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Base_Subsequence_Type_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Base_Subsequence_Type_MSK (0x00100000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Base_Subsequence_Type_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Base_Subsequence_Type_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_CADB_Deselect_Enable_OFF (21) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_CADB_Deselect_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_CADB_Deselect_Enable_MSK (0x00200000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_CADB_Deselect_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_CADB_Deselect_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_CADB_Select_Enable_OFF (22) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_CADB_Select_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_CADB_Select_Enable_MSK (0x00400000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_CADB_Select_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_CADB_Select_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_CADB_Seeds_Save_Enable_OFF (23) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_CADB_Seeds_Save_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_CADB_Seeds_Save_Enable_MSK (0x00800000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_CADB_Seeds_Save_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_CADB_Seeds_Save_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Column_Increment_Order_OFF (24) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Column_Increment_Order_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Column_Increment_Order_MSK (0x01000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Column_Increment_Order_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Column_Increment_Order_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Column_Increment_Enable_OFF (26) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Column_Increment_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Column_Increment_Enable_MSK (0x04000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Column_Increment_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Column_Increment_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Row_Increment_Order_OFF (27) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Row_Increment_Order_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Row_Increment_Order_MSK (0x08000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Row_Increment_Order_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Row_Increment_Order_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Row_Increment_Enable_OFF (29) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Row_Increment_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Row_Increment_Enable_MSK (0x20000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Row_Increment_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Row_Increment_Enable_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Base_Invert_Data_and_ECC_OFF (30) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Base_Invert_Data_and_ECC_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Base_Invert_Data_and_ECC_MSK (0x40000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Base_Invert_Data_and_ECC_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Base_Invert_Data_and_ECC_DEF (0x00000000) + +#define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_REG (0x00004864) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Offset_Address_Update_Rate_OFF ( 0) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Offset_Address_Update_Rate_WID ( 5) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Offset_Address_Update_Rate_MSK (0x0000001F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Offset_Address_Update_Rate_MAX (0x0000001F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Offset_Address_Update_Rate_DEF (0x00000002) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Base_Subsequence_Repeat_Rate_OFF ( 8) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Base_Subsequence_Repeat_Rate_WID ( 5) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Base_Subsequence_Repeat_Rate_MSK (0x00001F00) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Base_Subsequence_Repeat_Rate_MAX (0x0000001F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Base_Subsequence_Repeat_Rate_DEF (0x00000002) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Column_Offset_Wrap_Trigger_Enable_OFF (15) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Column_Offset_Wrap_Trigger_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Column_Offset_Wrap_Trigger_Enable_MSK (0x00008000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Column_Offset_Wrap_Trigger_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Column_Offset_Wrap_Trigger_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Row_Offset_Wrap_Trigger_Enable_OFF (16) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Row_Offset_Wrap_Trigger_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Row_Offset_Wrap_Trigger_Enable_MSK (0x00010000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Row_Offset_Wrap_Trigger_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Row_Offset_Wrap_Trigger_Enable_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Base_Subsequence_Type_OFF (20) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Base_Subsequence_Type_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Base_Subsequence_Type_MSK (0x00100000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Base_Subsequence_Type_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Base_Subsequence_Type_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_CADB_Deselect_Enable_OFF (21) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_CADB_Deselect_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_CADB_Deselect_Enable_MSK (0x00200000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_CADB_Deselect_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_CADB_Deselect_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_CADB_Select_Enable_OFF (22) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_CADB_Select_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_CADB_Select_Enable_MSK (0x00400000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_CADB_Select_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_CADB_Select_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_CADB_Seeds_Save_Enable_OFF (23) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_CADB_Seeds_Save_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_CADB_Seeds_Save_Enable_MSK (0x00800000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_CADB_Seeds_Save_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_CADB_Seeds_Save_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Column_Increment_Order_OFF (24) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Column_Increment_Order_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Column_Increment_Order_MSK (0x01000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Column_Increment_Order_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Column_Increment_Order_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Column_Increment_Enable_OFF (26) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Column_Increment_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Column_Increment_Enable_MSK (0x04000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Column_Increment_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Column_Increment_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Row_Increment_Order_OFF (27) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Row_Increment_Order_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Row_Increment_Order_MSK (0x08000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Row_Increment_Order_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Row_Increment_Order_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Row_Increment_Enable_OFF (29) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Row_Increment_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Row_Increment_Enable_MSK (0x20000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Row_Increment_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Row_Increment_Enable_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Base_Invert_Data_and_ECC_OFF (30) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Base_Invert_Data_and_ECC_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Base_Invert_Data_and_ECC_MSK (0x40000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Base_Invert_Data_and_ECC_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Base_Invert_Data_and_ECC_DEF (0x00000000) + +#define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_REG (0x00004868) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Offset_Address_Update_Rate_OFF ( 0) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Offset_Address_Update_Rate_WID ( 5) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Offset_Address_Update_Rate_MSK (0x0000001F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Offset_Address_Update_Rate_MAX (0x0000001F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Offset_Address_Update_Rate_DEF (0x00000002) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Base_Subsequence_Repeat_Rate_OFF ( 8) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Base_Subsequence_Repeat_Rate_WID ( 5) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Base_Subsequence_Repeat_Rate_MSK (0x00001F00) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Base_Subsequence_Repeat_Rate_MAX (0x0000001F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Base_Subsequence_Repeat_Rate_DEF (0x00000002) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Column_Offset_Wrap_Trigger_Enable_OFF (15) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Column_Offset_Wrap_Trigger_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Column_Offset_Wrap_Trigger_Enable_MSK (0x00008000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Column_Offset_Wrap_Trigger_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Column_Offset_Wrap_Trigger_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Row_Offset_Wrap_Trigger_Enable_OFF (16) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Row_Offset_Wrap_Trigger_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Row_Offset_Wrap_Trigger_Enable_MSK (0x00010000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Row_Offset_Wrap_Trigger_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Row_Offset_Wrap_Trigger_Enable_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Base_Subsequence_Type_OFF (20) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Base_Subsequence_Type_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Base_Subsequence_Type_MSK (0x00100000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Base_Subsequence_Type_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Base_Subsequence_Type_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_CADB_Deselect_Enable_OFF (21) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_CADB_Deselect_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_CADB_Deselect_Enable_MSK (0x00200000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_CADB_Deselect_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_CADB_Deselect_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_CADB_Select_Enable_OFF (22) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_CADB_Select_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_CADB_Select_Enable_MSK (0x00400000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_CADB_Select_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_CADB_Select_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_CADB_Seeds_Save_Enable_OFF (23) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_CADB_Seeds_Save_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_CADB_Seeds_Save_Enable_MSK (0x00800000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_CADB_Seeds_Save_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_CADB_Seeds_Save_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Column_Increment_Order_OFF (24) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Column_Increment_Order_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Column_Increment_Order_MSK (0x01000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Column_Increment_Order_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Column_Increment_Order_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Column_Increment_Enable_OFF (26) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Column_Increment_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Column_Increment_Enable_MSK (0x04000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Column_Increment_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Column_Increment_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Row_Increment_Order_OFF (27) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Row_Increment_Order_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Row_Increment_Order_MSK (0x08000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Row_Increment_Order_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Row_Increment_Order_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Row_Increment_Enable_OFF (29) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Row_Increment_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Row_Increment_Enable_MSK (0x20000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Row_Increment_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Row_Increment_Enable_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Base_Invert_Data_and_ECC_OFF (30) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Base_Invert_Data_and_ECC_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Base_Invert_Data_and_ECC_MSK (0x40000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Base_Invert_Data_and_ECC_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Base_Invert_Data_and_ECC_DEF (0x00000000) + +#define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_REG (0x0000486C) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Offset_Address_Update_Rate_OFF ( 0) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Offset_Address_Update_Rate_WID ( 5) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Offset_Address_Update_Rate_MSK (0x0000001F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Offset_Address_Update_Rate_MAX (0x0000001F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Offset_Address_Update_Rate_DEF (0x00000002) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Base_Subsequence_Repeat_Rate_OFF ( 8) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Base_Subsequence_Repeat_Rate_WID ( 5) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Base_Subsequence_Repeat_Rate_MSK (0x00001F00) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Base_Subsequence_Repeat_Rate_MAX (0x0000001F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Base_Subsequence_Repeat_Rate_DEF (0x00000002) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Column_Offset_Wrap_Trigger_Enable_OFF (15) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Column_Offset_Wrap_Trigger_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Column_Offset_Wrap_Trigger_Enable_MSK (0x00008000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Column_Offset_Wrap_Trigger_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Column_Offset_Wrap_Trigger_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Row_Offset_Wrap_Trigger_Enable_OFF (16) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Row_Offset_Wrap_Trigger_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Row_Offset_Wrap_Trigger_Enable_MSK (0x00010000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Row_Offset_Wrap_Trigger_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Row_Offset_Wrap_Trigger_Enable_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Base_Subsequence_Type_OFF (20) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Base_Subsequence_Type_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Base_Subsequence_Type_MSK (0x00100000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Base_Subsequence_Type_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Base_Subsequence_Type_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_CADB_Deselect_Enable_OFF (21) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_CADB_Deselect_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_CADB_Deselect_Enable_MSK (0x00200000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_CADB_Deselect_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_CADB_Deselect_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_CADB_Select_Enable_OFF (22) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_CADB_Select_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_CADB_Select_Enable_MSK (0x00400000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_CADB_Select_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_CADB_Select_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_CADB_Seeds_Save_Enable_OFF (23) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_CADB_Seeds_Save_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_CADB_Seeds_Save_Enable_MSK (0x00800000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_CADB_Seeds_Save_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_CADB_Seeds_Save_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Column_Increment_Order_OFF (24) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Column_Increment_Order_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Column_Increment_Order_MSK (0x01000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Column_Increment_Order_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Column_Increment_Order_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Column_Increment_Enable_OFF (26) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Column_Increment_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Column_Increment_Enable_MSK (0x04000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Column_Increment_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Column_Increment_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Row_Increment_Order_OFF (27) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Row_Increment_Order_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Row_Increment_Order_MSK (0x08000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Row_Increment_Order_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Row_Increment_Order_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Row_Increment_Enable_OFF (29) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Row_Increment_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Row_Increment_Enable_MSK (0x20000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Row_Increment_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Row_Increment_Enable_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Base_Invert_Data_and_ECC_OFF (30) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Base_Invert_Data_and_ECC_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Base_Invert_Data_and_ECC_MSK (0x40000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Base_Invert_Data_and_ECC_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Base_Invert_Data_and_ECC_DEF (0x00000000) + +#define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_REG (0x00004870) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Offset_Address_Update_Rate_OFF ( 0) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Offset_Address_Update_Rate_WID ( 5) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Offset_Address_Update_Rate_MSK (0x0000001F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Offset_Address_Update_Rate_MAX (0x0000001F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Offset_Address_Update_Rate_DEF (0x00000002) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Base_Subsequence_Repeat_Rate_OFF ( 8) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Base_Subsequence_Repeat_Rate_WID ( 5) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Base_Subsequence_Repeat_Rate_MSK (0x00001F00) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Base_Subsequence_Repeat_Rate_MAX (0x0000001F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Base_Subsequence_Repeat_Rate_DEF (0x00000002) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Column_Offset_Wrap_Trigger_Enable_OFF (15) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Column_Offset_Wrap_Trigger_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Column_Offset_Wrap_Trigger_Enable_MSK (0x00008000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Column_Offset_Wrap_Trigger_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Column_Offset_Wrap_Trigger_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Row_Offset_Wrap_Trigger_Enable_OFF (16) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Row_Offset_Wrap_Trigger_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Row_Offset_Wrap_Trigger_Enable_MSK (0x00010000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Row_Offset_Wrap_Trigger_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Row_Offset_Wrap_Trigger_Enable_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Base_Subsequence_Type_OFF (20) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Base_Subsequence_Type_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Base_Subsequence_Type_MSK (0x00100000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Base_Subsequence_Type_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Base_Subsequence_Type_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_CADB_Deselect_Enable_OFF (21) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_CADB_Deselect_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_CADB_Deselect_Enable_MSK (0x00200000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_CADB_Deselect_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_CADB_Deselect_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_CADB_Select_Enable_OFF (22) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_CADB_Select_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_CADB_Select_Enable_MSK (0x00400000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_CADB_Select_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_CADB_Select_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_CADB_Seeds_Save_Enable_OFF (23) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_CADB_Seeds_Save_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_CADB_Seeds_Save_Enable_MSK (0x00800000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_CADB_Seeds_Save_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_CADB_Seeds_Save_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Column_Increment_Order_OFF (24) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Column_Increment_Order_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Column_Increment_Order_MSK (0x01000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Column_Increment_Order_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Column_Increment_Order_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Column_Increment_Enable_OFF (26) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Column_Increment_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Column_Increment_Enable_MSK (0x04000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Column_Increment_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Column_Increment_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Row_Increment_Order_OFF (27) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Row_Increment_Order_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Row_Increment_Order_MSK (0x08000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Row_Increment_Order_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Row_Increment_Order_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Row_Increment_Enable_OFF (29) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Row_Increment_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Row_Increment_Enable_MSK (0x20000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Row_Increment_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Row_Increment_Enable_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Base_Invert_Data_and_ECC_OFF (30) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Base_Invert_Data_and_ECC_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Base_Invert_Data_and_ECC_MSK (0x40000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Base_Invert_Data_and_ECC_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Base_Invert_Data_and_ECC_DEF (0x00000000) + +#define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_REG (0x00004874) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Offset_Address_Update_Rate_OFF ( 0) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Offset_Address_Update_Rate_WID ( 5) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Offset_Address_Update_Rate_MSK (0x0000001F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Offset_Address_Update_Rate_MAX (0x0000001F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Offset_Address_Update_Rate_DEF (0x00000002) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Base_Subsequence_Repeat_Rate_OFF ( 8) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Base_Subsequence_Repeat_Rate_WID ( 5) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Base_Subsequence_Repeat_Rate_MSK (0x00001F00) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Base_Subsequence_Repeat_Rate_MAX (0x0000001F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Base_Subsequence_Repeat_Rate_DEF (0x00000002) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Column_Offset_Wrap_Trigger_Enable_OFF (15) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Column_Offset_Wrap_Trigger_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Column_Offset_Wrap_Trigger_Enable_MSK (0x00008000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Column_Offset_Wrap_Trigger_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Column_Offset_Wrap_Trigger_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Row_Offset_Wrap_Trigger_Enable_OFF (16) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Row_Offset_Wrap_Trigger_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Row_Offset_Wrap_Trigger_Enable_MSK (0x00010000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Row_Offset_Wrap_Trigger_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Row_Offset_Wrap_Trigger_Enable_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Base_Subsequence_Type_OFF (20) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Base_Subsequence_Type_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Base_Subsequence_Type_MSK (0x00100000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Base_Subsequence_Type_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Base_Subsequence_Type_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_CADB_Deselect_Enable_OFF (21) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_CADB_Deselect_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_CADB_Deselect_Enable_MSK (0x00200000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_CADB_Deselect_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_CADB_Deselect_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_CADB_Select_Enable_OFF (22) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_CADB_Select_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_CADB_Select_Enable_MSK (0x00400000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_CADB_Select_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_CADB_Select_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_CADB_Seeds_Save_Enable_OFF (23) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_CADB_Seeds_Save_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_CADB_Seeds_Save_Enable_MSK (0x00800000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_CADB_Seeds_Save_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_CADB_Seeds_Save_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Column_Increment_Order_OFF (24) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Column_Increment_Order_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Column_Increment_Order_MSK (0x01000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Column_Increment_Order_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Column_Increment_Order_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Column_Increment_Enable_OFF (26) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Column_Increment_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Column_Increment_Enable_MSK (0x04000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Column_Increment_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Column_Increment_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Row_Increment_Order_OFF (27) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Row_Increment_Order_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Row_Increment_Order_MSK (0x08000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Row_Increment_Order_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Row_Increment_Order_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Row_Increment_Enable_OFF (29) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Row_Increment_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Row_Increment_Enable_MSK (0x20000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Row_Increment_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Row_Increment_Enable_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Base_Invert_Data_and_ECC_OFF (30) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Base_Invert_Data_and_ECC_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Base_Invert_Data_and_ECC_MSK (0x40000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Base_Invert_Data_and_ECC_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Base_Invert_Data_and_ECC_DEF (0x00000000) + +#define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_REG (0x00004880) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Offset_Address_Update_Rate_OFF ( 0) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Offset_Address_Update_Rate_WID ( 5) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Offset_Address_Update_Rate_MSK (0x0000001F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Offset_Address_Update_Rate_MAX (0x0000001F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Offset_Address_Update_Rate_DEF (0x00000002) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Base_Subsequence_Repeat_Rate_OFF ( 8) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Base_Subsequence_Repeat_Rate_WID ( 5) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Base_Subsequence_Repeat_Rate_MSK (0x00001F00) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Base_Subsequence_Repeat_Rate_MAX (0x0000001F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Base_Subsequence_Repeat_Rate_DEF (0x00000002) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Column_Offset_Wrap_Trigger_Enable_OFF (15) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Column_Offset_Wrap_Trigger_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Column_Offset_Wrap_Trigger_Enable_MSK (0x00008000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Column_Offset_Wrap_Trigger_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Column_Offset_Wrap_Trigger_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Row_Offset_Wrap_Trigger_Enable_OFF (16) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Row_Offset_Wrap_Trigger_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Row_Offset_Wrap_Trigger_Enable_MSK (0x00010000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Row_Offset_Wrap_Trigger_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Row_Offset_Wrap_Trigger_Enable_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Base_Subsequence_Type_OFF (20) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Base_Subsequence_Type_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Base_Subsequence_Type_MSK (0x00100000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Base_Subsequence_Type_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Base_Subsequence_Type_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_CADB_Deselect_Enable_OFF (21) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_CADB_Deselect_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_CADB_Deselect_Enable_MSK (0x00200000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_CADB_Deselect_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_CADB_Deselect_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_CADB_Select_Enable_OFF (22) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_CADB_Select_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_CADB_Select_Enable_MSK (0x00400000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_CADB_Select_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_CADB_Select_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_CADB_Seeds_Save_Enable_OFF (23) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_CADB_Seeds_Save_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_CADB_Seeds_Save_Enable_MSK (0x00800000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_CADB_Seeds_Save_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_CADB_Seeds_Save_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Column_Increment_Order_OFF (24) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Column_Increment_Order_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Column_Increment_Order_MSK (0x01000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Column_Increment_Order_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Column_Increment_Order_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Column_Increment_Enable_OFF (26) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Column_Increment_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Column_Increment_Enable_MSK (0x04000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Column_Increment_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Column_Increment_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Row_Increment_Order_OFF (27) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Row_Increment_Order_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Row_Increment_Order_MSK (0x08000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Row_Increment_Order_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Row_Increment_Order_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Row_Increment_Enable_OFF (29) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Row_Increment_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Row_Increment_Enable_MSK (0x20000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Row_Increment_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Row_Increment_Enable_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Base_Invert_Data_and_ECC_OFF (30) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Base_Invert_Data_and_ECC_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Base_Invert_Data_and_ECC_MSK (0x40000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Base_Invert_Data_and_ECC_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Base_Invert_Data_and_ECC_DEF (0x00000000) + +#define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_REG (0x00004884) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Offset_Address_Update_Rate_OFF ( 0) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Offset_Address_Update_Rate_WID ( 5) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Offset_Address_Update_Rate_MSK (0x0000001F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Offset_Address_Update_Rate_MAX (0x0000001F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Offset_Address_Update_Rate_DEF (0x00000002) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Base_Subsequence_Repeat_Rate_OFF ( 8) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Base_Subsequence_Repeat_Rate_WID ( 5) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Base_Subsequence_Repeat_Rate_MSK (0x00001F00) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Base_Subsequence_Repeat_Rate_MAX (0x0000001F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Base_Subsequence_Repeat_Rate_DEF (0x00000002) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Column_Offset_Wrap_Trigger_Enable_OFF (15) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Column_Offset_Wrap_Trigger_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Column_Offset_Wrap_Trigger_Enable_MSK (0x00008000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Column_Offset_Wrap_Trigger_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Column_Offset_Wrap_Trigger_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Row_Offset_Wrap_Trigger_Enable_OFF (16) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Row_Offset_Wrap_Trigger_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Row_Offset_Wrap_Trigger_Enable_MSK (0x00010000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Row_Offset_Wrap_Trigger_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Row_Offset_Wrap_Trigger_Enable_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Base_Subsequence_Type_OFF (20) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Base_Subsequence_Type_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Base_Subsequence_Type_MSK (0x00100000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Base_Subsequence_Type_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Base_Subsequence_Type_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_CADB_Deselect_Enable_OFF (21) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_CADB_Deselect_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_CADB_Deselect_Enable_MSK (0x00200000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_CADB_Deselect_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_CADB_Deselect_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_CADB_Select_Enable_OFF (22) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_CADB_Select_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_CADB_Select_Enable_MSK (0x00400000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_CADB_Select_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_CADB_Select_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_CADB_Seeds_Save_Enable_OFF (23) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_CADB_Seeds_Save_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_CADB_Seeds_Save_Enable_MSK (0x00800000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_CADB_Seeds_Save_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_CADB_Seeds_Save_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Column_Increment_Order_OFF (24) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Column_Increment_Order_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Column_Increment_Order_MSK (0x01000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Column_Increment_Order_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Column_Increment_Order_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Column_Increment_Enable_OFF (26) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Column_Increment_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Column_Increment_Enable_MSK (0x04000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Column_Increment_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Column_Increment_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Row_Increment_Order_OFF (27) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Row_Increment_Order_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Row_Increment_Order_MSK (0x08000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Row_Increment_Order_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Row_Increment_Order_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Row_Increment_Enable_OFF (29) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Row_Increment_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Row_Increment_Enable_MSK (0x20000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Row_Increment_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Row_Increment_Enable_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Base_Invert_Data_and_ECC_OFF (30) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Base_Invert_Data_and_ECC_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Base_Invert_Data_and_ECC_MSK (0x40000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Base_Invert_Data_and_ECC_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Base_Invert_Data_and_ECC_DEF (0x00000000) + +#define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_REG (0x00004888) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Offset_Address_Update_Rate_OFF ( 0) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Offset_Address_Update_Rate_WID ( 5) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Offset_Address_Update_Rate_MSK (0x0000001F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Offset_Address_Update_Rate_MAX (0x0000001F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Offset_Address_Update_Rate_DEF (0x00000002) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Base_Subsequence_Repeat_Rate_OFF ( 8) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Base_Subsequence_Repeat_Rate_WID ( 5) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Base_Subsequence_Repeat_Rate_MSK (0x00001F00) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Base_Subsequence_Repeat_Rate_MAX (0x0000001F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Base_Subsequence_Repeat_Rate_DEF (0x00000002) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Column_Offset_Wrap_Trigger_Enable_OFF (15) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Column_Offset_Wrap_Trigger_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Column_Offset_Wrap_Trigger_Enable_MSK (0x00008000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Column_Offset_Wrap_Trigger_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Column_Offset_Wrap_Trigger_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Row_Offset_Wrap_Trigger_Enable_OFF (16) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Row_Offset_Wrap_Trigger_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Row_Offset_Wrap_Trigger_Enable_MSK (0x00010000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Row_Offset_Wrap_Trigger_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Row_Offset_Wrap_Trigger_Enable_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Base_Subsequence_Type_OFF (20) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Base_Subsequence_Type_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Base_Subsequence_Type_MSK (0x00100000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Base_Subsequence_Type_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Base_Subsequence_Type_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_CADB_Deselect_Enable_OFF (21) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_CADB_Deselect_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_CADB_Deselect_Enable_MSK (0x00200000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_CADB_Deselect_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_CADB_Deselect_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_CADB_Select_Enable_OFF (22) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_CADB_Select_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_CADB_Select_Enable_MSK (0x00400000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_CADB_Select_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_CADB_Select_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_CADB_Seeds_Save_Enable_OFF (23) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_CADB_Seeds_Save_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_CADB_Seeds_Save_Enable_MSK (0x00800000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_CADB_Seeds_Save_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_CADB_Seeds_Save_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Column_Increment_Order_OFF (24) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Column_Increment_Order_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Column_Increment_Order_MSK (0x01000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Column_Increment_Order_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Column_Increment_Order_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Column_Increment_Enable_OFF (26) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Column_Increment_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Column_Increment_Enable_MSK (0x04000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Column_Increment_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Column_Increment_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Row_Increment_Order_OFF (27) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Row_Increment_Order_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Row_Increment_Order_MSK (0x08000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Row_Increment_Order_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Row_Increment_Order_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Row_Increment_Enable_OFF (29) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Row_Increment_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Row_Increment_Enable_MSK (0x20000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Row_Increment_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Row_Increment_Enable_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Base_Invert_Data_and_ECC_OFF (30) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Base_Invert_Data_and_ECC_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Base_Invert_Data_and_ECC_MSK (0x40000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Base_Invert_Data_and_ECC_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Base_Invert_Data_and_ECC_DEF (0x00000000) + +#define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_REG (0x0000488C) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Offset_Address_Update_Rate_OFF ( 0) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Offset_Address_Update_Rate_WID ( 5) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Offset_Address_Update_Rate_MSK (0x0000001F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Offset_Address_Update_Rate_MAX (0x0000001F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Offset_Address_Update_Rate_DEF (0x00000002) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Base_Subsequence_Repeat_Rate_OFF ( 8) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Base_Subsequence_Repeat_Rate_WID ( 5) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Base_Subsequence_Repeat_Rate_MSK (0x00001F00) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Base_Subsequence_Repeat_Rate_MAX (0x0000001F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Base_Subsequence_Repeat_Rate_DEF (0x00000002) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Column_Offset_Wrap_Trigger_Enable_OFF (15) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Column_Offset_Wrap_Trigger_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Column_Offset_Wrap_Trigger_Enable_MSK (0x00008000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Column_Offset_Wrap_Trigger_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Column_Offset_Wrap_Trigger_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Row_Offset_Wrap_Trigger_Enable_OFF (16) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Row_Offset_Wrap_Trigger_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Row_Offset_Wrap_Trigger_Enable_MSK (0x00010000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Row_Offset_Wrap_Trigger_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Row_Offset_Wrap_Trigger_Enable_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Base_Subsequence_Type_OFF (20) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Base_Subsequence_Type_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Base_Subsequence_Type_MSK (0x00100000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Base_Subsequence_Type_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Base_Subsequence_Type_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_CADB_Deselect_Enable_OFF (21) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_CADB_Deselect_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_CADB_Deselect_Enable_MSK (0x00200000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_CADB_Deselect_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_CADB_Deselect_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_CADB_Select_Enable_OFF (22) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_CADB_Select_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_CADB_Select_Enable_MSK (0x00400000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_CADB_Select_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_CADB_Select_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_CADB_Seeds_Save_Enable_OFF (23) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_CADB_Seeds_Save_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_CADB_Seeds_Save_Enable_MSK (0x00800000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_CADB_Seeds_Save_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_CADB_Seeds_Save_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Column_Increment_Order_OFF (24) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Column_Increment_Order_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Column_Increment_Order_MSK (0x01000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Column_Increment_Order_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Column_Increment_Order_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Column_Increment_Enable_OFF (26) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Column_Increment_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Column_Increment_Enable_MSK (0x04000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Column_Increment_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Column_Increment_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Row_Increment_Order_OFF (27) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Row_Increment_Order_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Row_Increment_Order_MSK (0x08000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Row_Increment_Order_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Row_Increment_Order_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Row_Increment_Enable_OFF (29) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Row_Increment_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Row_Increment_Enable_MSK (0x20000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Row_Increment_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Row_Increment_Enable_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Base_Invert_Data_and_ECC_OFF (30) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Base_Invert_Data_and_ECC_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Base_Invert_Data_and_ECC_MSK (0x40000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Base_Invert_Data_and_ECC_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Base_Invert_Data_and_ECC_DEF (0x00000000) + +#define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_REG (0x00004890) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Offset_Address_Update_Rate_OFF ( 0) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Offset_Address_Update_Rate_WID ( 5) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Offset_Address_Update_Rate_MSK (0x0000001F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Offset_Address_Update_Rate_MAX (0x0000001F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Offset_Address_Update_Rate_DEF (0x00000002) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Base_Subsequence_Repeat_Rate_OFF ( 8) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Base_Subsequence_Repeat_Rate_WID ( 5) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Base_Subsequence_Repeat_Rate_MSK (0x00001F00) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Base_Subsequence_Repeat_Rate_MAX (0x0000001F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Base_Subsequence_Repeat_Rate_DEF (0x00000002) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Column_Offset_Wrap_Trigger_Enable_OFF (15) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Column_Offset_Wrap_Trigger_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Column_Offset_Wrap_Trigger_Enable_MSK (0x00008000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Column_Offset_Wrap_Trigger_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Column_Offset_Wrap_Trigger_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Row_Offset_Wrap_Trigger_Enable_OFF (16) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Row_Offset_Wrap_Trigger_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Row_Offset_Wrap_Trigger_Enable_MSK (0x00010000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Row_Offset_Wrap_Trigger_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Row_Offset_Wrap_Trigger_Enable_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Base_Subsequence_Type_OFF (20) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Base_Subsequence_Type_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Base_Subsequence_Type_MSK (0x00100000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Base_Subsequence_Type_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Base_Subsequence_Type_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_CADB_Deselect_Enable_OFF (21) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_CADB_Deselect_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_CADB_Deselect_Enable_MSK (0x00200000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_CADB_Deselect_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_CADB_Deselect_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_CADB_Select_Enable_OFF (22) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_CADB_Select_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_CADB_Select_Enable_MSK (0x00400000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_CADB_Select_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_CADB_Select_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_CADB_Seeds_Save_Enable_OFF (23) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_CADB_Seeds_Save_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_CADB_Seeds_Save_Enable_MSK (0x00800000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_CADB_Seeds_Save_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_CADB_Seeds_Save_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Column_Increment_Order_OFF (24) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Column_Increment_Order_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Column_Increment_Order_MSK (0x01000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Column_Increment_Order_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Column_Increment_Order_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Column_Increment_Enable_OFF (26) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Column_Increment_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Column_Increment_Enable_MSK (0x04000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Column_Increment_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Column_Increment_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Row_Increment_Order_OFF (27) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Row_Increment_Order_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Row_Increment_Order_MSK (0x08000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Row_Increment_Order_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Row_Increment_Order_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Row_Increment_Enable_OFF (29) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Row_Increment_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Row_Increment_Enable_MSK (0x20000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Row_Increment_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Row_Increment_Enable_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Base_Invert_Data_and_ECC_OFF (30) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Base_Invert_Data_and_ECC_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Base_Invert_Data_and_ECC_MSK (0x40000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Base_Invert_Data_and_ECC_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Base_Invert_Data_and_ECC_DEF (0x00000000) + +#define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_REG (0x00004894) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Offset_Address_Update_Rate_OFF ( 0) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Offset_Address_Update_Rate_WID ( 5) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Offset_Address_Update_Rate_MSK (0x0000001F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Offset_Address_Update_Rate_MAX (0x0000001F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Offset_Address_Update_Rate_DEF (0x00000002) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Base_Subsequence_Repeat_Rate_OFF ( 8) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Base_Subsequence_Repeat_Rate_WID ( 5) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Base_Subsequence_Repeat_Rate_MSK (0x00001F00) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Base_Subsequence_Repeat_Rate_MAX (0x0000001F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Base_Subsequence_Repeat_Rate_DEF (0x00000002) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Column_Offset_Wrap_Trigger_Enable_OFF (15) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Column_Offset_Wrap_Trigger_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Column_Offset_Wrap_Trigger_Enable_MSK (0x00008000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Column_Offset_Wrap_Trigger_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Column_Offset_Wrap_Trigger_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Row_Offset_Wrap_Trigger_Enable_OFF (16) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Row_Offset_Wrap_Trigger_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Row_Offset_Wrap_Trigger_Enable_MSK (0x00010000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Row_Offset_Wrap_Trigger_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Row_Offset_Wrap_Trigger_Enable_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Base_Subsequence_Type_OFF (20) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Base_Subsequence_Type_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Base_Subsequence_Type_MSK (0x00100000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Base_Subsequence_Type_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Base_Subsequence_Type_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_CADB_Deselect_Enable_OFF (21) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_CADB_Deselect_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_CADB_Deselect_Enable_MSK (0x00200000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_CADB_Deselect_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_CADB_Deselect_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_CADB_Select_Enable_OFF (22) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_CADB_Select_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_CADB_Select_Enable_MSK (0x00400000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_CADB_Select_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_CADB_Select_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_CADB_Seeds_Save_Enable_OFF (23) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_CADB_Seeds_Save_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_CADB_Seeds_Save_Enable_MSK (0x00800000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_CADB_Seeds_Save_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_CADB_Seeds_Save_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Column_Increment_Order_OFF (24) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Column_Increment_Order_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Column_Increment_Order_MSK (0x01000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Column_Increment_Order_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Column_Increment_Order_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Column_Increment_Enable_OFF (26) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Column_Increment_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Column_Increment_Enable_MSK (0x04000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Column_Increment_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Column_Increment_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Row_Increment_Order_OFF (27) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Row_Increment_Order_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Row_Increment_Order_MSK (0x08000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Row_Increment_Order_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Row_Increment_Order_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Row_Increment_Enable_OFF (29) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Row_Increment_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Row_Increment_Enable_MSK (0x20000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Row_Increment_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Row_Increment_Enable_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Base_Invert_Data_and_ECC_OFF (30) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Base_Invert_Data_and_ECC_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Base_Invert_Data_and_ECC_MSK (0x40000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Base_Invert_Data_and_ECC_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Base_Invert_Data_and_ECC_DEF (0x00000000) + +#define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_REG (0x00004898) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Offset_Address_Update_Rate_OFF ( 0) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Offset_Address_Update_Rate_WID ( 5) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Offset_Address_Update_Rate_MSK (0x0000001F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Offset_Address_Update_Rate_MAX (0x0000001F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Offset_Address_Update_Rate_DEF (0x00000002) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Base_Subsequence_Repeat_Rate_OFF ( 8) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Base_Subsequence_Repeat_Rate_WID ( 5) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Base_Subsequence_Repeat_Rate_MSK (0x00001F00) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Base_Subsequence_Repeat_Rate_MAX (0x0000001F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Base_Subsequence_Repeat_Rate_DEF (0x00000002) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Column_Offset_Wrap_Trigger_Enable_OFF (15) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Column_Offset_Wrap_Trigger_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Column_Offset_Wrap_Trigger_Enable_MSK (0x00008000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Column_Offset_Wrap_Trigger_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Column_Offset_Wrap_Trigger_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Row_Offset_Wrap_Trigger_Enable_OFF (16) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Row_Offset_Wrap_Trigger_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Row_Offset_Wrap_Trigger_Enable_MSK (0x00010000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Row_Offset_Wrap_Trigger_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Row_Offset_Wrap_Trigger_Enable_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Base_Subsequence_Type_OFF (20) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Base_Subsequence_Type_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Base_Subsequence_Type_MSK (0x00100000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Base_Subsequence_Type_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Base_Subsequence_Type_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_CADB_Deselect_Enable_OFF (21) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_CADB_Deselect_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_CADB_Deselect_Enable_MSK (0x00200000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_CADB_Deselect_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_CADB_Deselect_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_CADB_Select_Enable_OFF (22) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_CADB_Select_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_CADB_Select_Enable_MSK (0x00400000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_CADB_Select_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_CADB_Select_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_CADB_Seeds_Save_Enable_OFF (23) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_CADB_Seeds_Save_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_CADB_Seeds_Save_Enable_MSK (0x00800000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_CADB_Seeds_Save_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_CADB_Seeds_Save_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Column_Increment_Order_OFF (24) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Column_Increment_Order_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Column_Increment_Order_MSK (0x01000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Column_Increment_Order_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Column_Increment_Order_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Column_Increment_Enable_OFF (26) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Column_Increment_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Column_Increment_Enable_MSK (0x04000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Column_Increment_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Column_Increment_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Row_Increment_Order_OFF (27) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Row_Increment_Order_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Row_Increment_Order_MSK (0x08000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Row_Increment_Order_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Row_Increment_Order_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Row_Increment_Enable_OFF (29) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Row_Increment_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Row_Increment_Enable_MSK (0x20000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Row_Increment_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Row_Increment_Enable_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Base_Invert_Data_and_ECC_OFF (30) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Base_Invert_Data_and_ECC_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Base_Invert_Data_and_ECC_MSK (0x40000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Base_Invert_Data_and_ECC_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Base_Invert_Data_and_ECC_DEF (0x00000000) + +#define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_REG (0x0000489C) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Offset_Address_Update_Rate_OFF ( 0) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Offset_Address_Update_Rate_WID ( 5) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Offset_Address_Update_Rate_MSK (0x0000001F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Offset_Address_Update_Rate_MAX (0x0000001F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Offset_Address_Update_Rate_DEF (0x00000002) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Base_Subsequence_Repeat_Rate_OFF ( 8) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Base_Subsequence_Repeat_Rate_WID ( 5) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Base_Subsequence_Repeat_Rate_MSK (0x00001F00) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Base_Subsequence_Repeat_Rate_MAX (0x0000001F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Base_Subsequence_Repeat_Rate_DEF (0x00000002) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Column_Offset_Wrap_Trigger_Enable_OFF (15) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Column_Offset_Wrap_Trigger_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Column_Offset_Wrap_Trigger_Enable_MSK (0x00008000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Column_Offset_Wrap_Trigger_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Column_Offset_Wrap_Trigger_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Row_Offset_Wrap_Trigger_Enable_OFF (16) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Row_Offset_Wrap_Trigger_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Row_Offset_Wrap_Trigger_Enable_MSK (0x00010000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Row_Offset_Wrap_Trigger_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Row_Offset_Wrap_Trigger_Enable_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Base_Subsequence_Type_OFF (20) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Base_Subsequence_Type_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Base_Subsequence_Type_MSK (0x00100000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Base_Subsequence_Type_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Base_Subsequence_Type_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_CADB_Deselect_Enable_OFF (21) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_CADB_Deselect_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_CADB_Deselect_Enable_MSK (0x00200000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_CADB_Deselect_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_CADB_Deselect_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_CADB_Select_Enable_OFF (22) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_CADB_Select_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_CADB_Select_Enable_MSK (0x00400000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_CADB_Select_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_CADB_Select_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_CADB_Seeds_Save_Enable_OFF (23) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_CADB_Seeds_Save_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_CADB_Seeds_Save_Enable_MSK (0x00800000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_CADB_Seeds_Save_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_CADB_Seeds_Save_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Column_Increment_Order_OFF (24) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Column_Increment_Order_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Column_Increment_Order_MSK (0x01000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Column_Increment_Order_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Column_Increment_Order_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Column_Increment_Enable_OFF (26) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Column_Increment_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Column_Increment_Enable_MSK (0x04000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Column_Increment_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Column_Increment_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Row_Increment_Order_OFF (27) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Row_Increment_Order_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Row_Increment_Order_MSK (0x08000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Row_Increment_Order_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Row_Increment_Order_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Row_Increment_Enable_OFF (29) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Row_Increment_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Row_Increment_Enable_MSK (0x20000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Row_Increment_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Row_Increment_Enable_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Base_Invert_Data_and_ECC_OFF (30) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Base_Invert_Data_and_ECC_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Base_Invert_Data_and_ECC_MSK (0x40000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Base_Invert_Data_and_ECC_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Base_Invert_Data_and_ECC_DEF (0x00000000) + +#define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_REG (0x000048A8) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Stop_Base_Sequence_On_Wrap_Trigger_OFF ( 3) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Stop_Base_Sequence_On_Wrap_Trigger_WID ( 1) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Stop_Base_Sequence_On_Wrap_Trigger_MSK (0x00000008) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Stop_Base_Sequence_On_Wrap_Trigger_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Stop_Base_Sequence_On_Wrap_Trigger_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Address_Update_Rate_Mode_OFF ( 5) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Address_Update_Rate_Mode_WID ( 1) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Address_Update_Rate_Mode_MSK (0x00000020) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Address_Update_Rate_Mode_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Address_Update_Rate_Mode_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Enable_Dummy_Reads_OFF ( 7) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Enable_Dummy_Reads_WID ( 1) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Enable_Dummy_Reads_MSK (0x00000080) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Enable_Dummy_Reads_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Enable_Dummy_Reads_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Enable_Constant_Write_Strobe_OFF (10) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Enable_Constant_Write_Strobe_WID ( 1) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Enable_Constant_Write_Strobe_MSK (0x00000400) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Enable_Constant_Write_Strobe_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Enable_Constant_Write_Strobe_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Global_Control_OFF (11) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Global_Control_WID ( 1) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Global_Control_MSK (0x00000800) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Global_Control_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Global_Control_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Initialization_Mode_OFF (12) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Initialization_Mode_WID ( 2) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Initialization_Mode_MSK (0x00003000) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Initialization_Mode_MAX (0x00000003) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Initialization_Mode_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Loopcount_OFF (16) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Loopcount_WID ( 5) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Loopcount_MSK (0x001F0000) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Loopcount_MAX (0x0000001F) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Loopcount_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Subsequence_Start_Pointer_OFF (24) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Subsequence_Start_Pointer_WID ( 3) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Subsequence_Start_Pointer_MSK (0x07000000) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Subsequence_Start_Pointer_MAX (0x00000007) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Subsequence_Start_Pointer_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Subsequence_End_Pointer_OFF (28) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Subsequence_End_Pointer_WID ( 3) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Subsequence_End_Pointer_MSK (0x70000000) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Subsequence_End_Pointer_MAX (0x00000007) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Subsequence_End_Pointer_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Start_Test_Delay_OFF (32) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Start_Test_Delay_WID (10) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Start_Test_Delay_MSK (0x3FF00000000) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Start_Test_Delay_MAX (0x000003FF) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Start_Test_Delay_DEF (0x00000000) + +#define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_REG (0x000048B0) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Stop_Base_Sequence_On_Wrap_Trigger_OFF ( 3) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Stop_Base_Sequence_On_Wrap_Trigger_WID ( 1) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Stop_Base_Sequence_On_Wrap_Trigger_MSK (0x00000008) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Stop_Base_Sequence_On_Wrap_Trigger_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Stop_Base_Sequence_On_Wrap_Trigger_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Address_Update_Rate_Mode_OFF ( 5) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Address_Update_Rate_Mode_WID ( 1) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Address_Update_Rate_Mode_MSK (0x00000020) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Address_Update_Rate_Mode_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Address_Update_Rate_Mode_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Enable_Dummy_Reads_OFF ( 7) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Enable_Dummy_Reads_WID ( 1) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Enable_Dummy_Reads_MSK (0x00000080) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Enable_Dummy_Reads_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Enable_Dummy_Reads_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Enable_Constant_Write_Strobe_OFF (10) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Enable_Constant_Write_Strobe_WID ( 1) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Enable_Constant_Write_Strobe_MSK (0x00000400) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Enable_Constant_Write_Strobe_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Enable_Constant_Write_Strobe_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Global_Control_OFF (11) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Global_Control_WID ( 1) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Global_Control_MSK (0x00000800) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Global_Control_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Global_Control_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Initialization_Mode_OFF (12) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Initialization_Mode_WID ( 2) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Initialization_Mode_MSK (0x00003000) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Initialization_Mode_MAX (0x00000003) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Initialization_Mode_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Loopcount_OFF (16) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Loopcount_WID ( 5) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Loopcount_MSK (0x001F0000) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Loopcount_MAX (0x0000001F) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Loopcount_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Subsequence_Start_Pointer_OFF (24) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Subsequence_Start_Pointer_WID ( 3) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Subsequence_Start_Pointer_MSK (0x07000000) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Subsequence_Start_Pointer_MAX (0x00000007) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Subsequence_Start_Pointer_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Subsequence_End_Pointer_OFF (28) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Subsequence_End_Pointer_WID ( 3) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Subsequence_End_Pointer_MSK (0x70000000) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Subsequence_End_Pointer_MAX (0x00000007) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Subsequence_End_Pointer_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Start_Test_Delay_OFF (32) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Start_Test_Delay_WID (10) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Start_Test_Delay_MSK (0x3FF00000000) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Start_Test_Delay_MAX (0x000003FF) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Start_Test_Delay_DEF (0x00000000) + +#define MCDFXS_CR_REUT_CH_SEQ_CTL_MCMAIN_0_REG (0x000048B8) + #define MCDFXS_CR_REUT_CH_SEQ_CTL_MCMAIN_0_Local_Start_Test_OFF ( 0) + #define MCDFXS_CR_REUT_CH_SEQ_CTL_MCMAIN_0_Local_Start_Test_WID ( 1) + #define MCDFXS_CR_REUT_CH_SEQ_CTL_MCMAIN_0_Local_Start_Test_MSK (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_CTL_MCMAIN_0_Local_Start_Test_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_CTL_MCMAIN_0_Local_Start_Test_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_CTL_MCMAIN_0_Local_Stop_Test_OFF ( 1) + #define MCDFXS_CR_REUT_CH_SEQ_CTL_MCMAIN_0_Local_Stop_Test_WID ( 1) + #define MCDFXS_CR_REUT_CH_SEQ_CTL_MCMAIN_0_Local_Stop_Test_MSK (0x00000002) + #define MCDFXS_CR_REUT_CH_SEQ_CTL_MCMAIN_0_Local_Stop_Test_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_CTL_MCMAIN_0_Local_Stop_Test_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_CTL_MCMAIN_0_Local_Clear_Errors_OFF ( 2) + #define MCDFXS_CR_REUT_CH_SEQ_CTL_MCMAIN_0_Local_Clear_Errors_WID ( 1) + #define MCDFXS_CR_REUT_CH_SEQ_CTL_MCMAIN_0_Local_Clear_Errors_MSK (0x00000004) + #define MCDFXS_CR_REUT_CH_SEQ_CTL_MCMAIN_0_Local_Clear_Errors_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_CTL_MCMAIN_0_Local_Clear_Errors_DEF (0x00000000) + +#define MCDFXS_CR_REUT_CH_SEQ_CTL_MCMAIN_1_REG (0x000048BC) + #define MCDFXS_CR_REUT_CH_SEQ_CTL_MCMAIN_1_Local_Start_Test_OFF ( 0) + #define MCDFXS_CR_REUT_CH_SEQ_CTL_MCMAIN_1_Local_Start_Test_WID ( 1) + #define MCDFXS_CR_REUT_CH_SEQ_CTL_MCMAIN_1_Local_Start_Test_MSK (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_CTL_MCMAIN_1_Local_Start_Test_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_CTL_MCMAIN_1_Local_Start_Test_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_CTL_MCMAIN_1_Local_Stop_Test_OFF ( 1) + #define MCDFXS_CR_REUT_CH_SEQ_CTL_MCMAIN_1_Local_Stop_Test_WID ( 1) + #define MCDFXS_CR_REUT_CH_SEQ_CTL_MCMAIN_1_Local_Stop_Test_MSK (0x00000002) + #define MCDFXS_CR_REUT_CH_SEQ_CTL_MCMAIN_1_Local_Stop_Test_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_CTL_MCMAIN_1_Local_Stop_Test_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_CTL_MCMAIN_1_Local_Clear_Errors_OFF ( 2) + #define MCDFXS_CR_REUT_CH_SEQ_CTL_MCMAIN_1_Local_Clear_Errors_WID ( 1) + #define MCDFXS_CR_REUT_CH_SEQ_CTL_MCMAIN_1_Local_Clear_Errors_MSK (0x00000004) + #define MCDFXS_CR_REUT_CH_SEQ_CTL_MCMAIN_1_Local_Clear_Errors_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_CTL_MCMAIN_1_Local_Clear_Errors_DEF (0x00000000) + +#define MCDFXS_CR_REUT_CH_SEQ_LOOPCOUNT_STATUS_MCMAIN_0_REG (0x000048C0) + #define MCDFXS_CR_REUT_CH_SEQ_LOOPCOUNT_STATUS_MCMAIN_0_Current_Loopcount_OFF ( 0) + #define MCDFXS_CR_REUT_CH_SEQ_LOOPCOUNT_STATUS_MCMAIN_0_Current_Loopcount_WID (32) + #define MCDFXS_CR_REUT_CH_SEQ_LOOPCOUNT_STATUS_MCMAIN_0_Current_Loopcount_MSK (0xFFFFFFFF) + #define MCDFXS_CR_REUT_CH_SEQ_LOOPCOUNT_STATUS_MCMAIN_0_Current_Loopcount_MAX (0xFFFFFFFF) + #define MCDFXS_CR_REUT_CH_SEQ_LOOPCOUNT_STATUS_MCMAIN_0_Current_Loopcount_DEF (0x00000000) + +#define MCDFXS_CR_REUT_CH_SEQ_LOOPCOUNT_STATUS_MCMAIN_1_REG (0x000048C4) + #define MCDFXS_CR_REUT_CH_SEQ_LOOPCOUNT_STATUS_MCMAIN_1_Current_Loopcount_OFF ( 0) + #define MCDFXS_CR_REUT_CH_SEQ_LOOPCOUNT_STATUS_MCMAIN_1_Current_Loopcount_WID (32) + #define MCDFXS_CR_REUT_CH_SEQ_LOOPCOUNT_STATUS_MCMAIN_1_Current_Loopcount_MSK (0xFFFFFFFF) + #define MCDFXS_CR_REUT_CH_SEQ_LOOPCOUNT_STATUS_MCMAIN_1_Current_Loopcount_MAX (0xFFFFFFFF) + #define MCDFXS_CR_REUT_CH_SEQ_LOOPCOUNT_STATUS_MCMAIN_1_Current_Loopcount_DEF (0x00000000) + +#define MCDFXS_CR_REUT_CH_SEQ_SUBSEQ_PNTR_MCMAIN_0_REG (0x000048C8) + #define MCDFXS_CR_REUT_CH_SEQ_SUBSEQ_PNTR_MCMAIN_0_Current_Subsequence_Pointer_OFF ( 0) + #define MCDFXS_CR_REUT_CH_SEQ_SUBSEQ_PNTR_MCMAIN_0_Current_Subsequence_Pointer_WID ( 3) + #define MCDFXS_CR_REUT_CH_SEQ_SUBSEQ_PNTR_MCMAIN_0_Current_Subsequence_Pointer_MSK (0x00000007) + #define MCDFXS_CR_REUT_CH_SEQ_SUBSEQ_PNTR_MCMAIN_0_Current_Subsequence_Pointer_MAX (0x00000007) + #define MCDFXS_CR_REUT_CH_SEQ_SUBSEQ_PNTR_MCMAIN_0_Current_Subsequence_Pointer_DEF (0x00000000) + +#define MCDFXS_CR_REUT_CH_SEQ_SUBSEQ_PNTR_MCMAIN_1_REG (0x000048CC) + #define MCDFXS_CR_REUT_CH_SEQ_SUBSEQ_PNTR_MCMAIN_1_Current_Subsequence_Pointer_OFF ( 0) + #define MCDFXS_CR_REUT_CH_SEQ_SUBSEQ_PNTR_MCMAIN_1_Current_Subsequence_Pointer_WID ( 3) + #define MCDFXS_CR_REUT_CH_SEQ_SUBSEQ_PNTR_MCMAIN_1_Current_Subsequence_Pointer_MSK (0x00000007) + #define MCDFXS_CR_REUT_CH_SEQ_SUBSEQ_PNTR_MCMAIN_1_Current_Subsequence_Pointer_MAX (0x00000007) + #define MCDFXS_CR_REUT_CH_SEQ_SUBSEQ_PNTR_MCMAIN_1_Current_Subsequence_Pointer_DEF (0x00000000) + +#define MCDFXS_CR_REUT_CH_SEQ_CACHELINE_STATUS_MCMAIN_0_REG (0x000048D0) + #define MCDFXS_CR_REUT_CH_SEQ_CACHELINE_STATUS_MCMAIN_0_Current_Cacheline_OFF ( 0) + #define MCDFXS_CR_REUT_CH_SEQ_CACHELINE_STATUS_MCMAIN_0_Current_Cacheline_WID (16) + #define MCDFXS_CR_REUT_CH_SEQ_CACHELINE_STATUS_MCMAIN_0_Current_Cacheline_MSK (0x0000FFFF) + #define MCDFXS_CR_REUT_CH_SEQ_CACHELINE_STATUS_MCMAIN_0_Current_Cacheline_MAX (0x0000FFFF) + #define MCDFXS_CR_REUT_CH_SEQ_CACHELINE_STATUS_MCMAIN_0_Current_Cacheline_DEF (0x00000000) + +#define MCDFXS_CR_REUT_CH_SEQ_CACHELINE_STATUS_MCMAIN_1_REG (0x000048D4) + #define MCDFXS_CR_REUT_CH_SEQ_CACHELINE_STATUS_MCMAIN_1_Current_Cacheline_OFF ( 0) + #define MCDFXS_CR_REUT_CH_SEQ_CACHELINE_STATUS_MCMAIN_1_Current_Cacheline_WID (16) + #define MCDFXS_CR_REUT_CH_SEQ_CACHELINE_STATUS_MCMAIN_1_Current_Cacheline_MSK (0x0000FFFF) + #define MCDFXS_CR_REUT_CH_SEQ_CACHELINE_STATUS_MCMAIN_1_Current_Cacheline_MAX (0x0000FFFF) + #define MCDFXS_CR_REUT_CH_SEQ_CACHELINE_STATUS_MCMAIN_1_Current_Cacheline_DEF (0x00000000) + +#define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_0_REG (0x000048D8) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_0_Column_Address_OFF (3) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_0_Column_Address_WID_A0 (7) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_0_Column_Address_MSK_A0 (0x000003F8) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_0_Column_Address_MAX_A0 (0x0000007F) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_0_Column_Address_WID (8) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_0_Column_Address_MSK (0x000007F8) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_0_Column_Address_MAX (0x000000FF) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_0_Column_Address_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_0_Row_Address_OFF (24) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_0_Row_Address_WID (16) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_0_Row_Address_MSK (0xFFFF000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_0_Row_Address_MAX (0x0000FFFF) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_0_Row_Address_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_0_Bank_Address_OFF (48) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_0_Bank_Address_WID (3) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_0_Bank_Address_MSK (0x7000000000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_0_Bank_Address_MAX (0x00000007) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_0_Bank_Address_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_0_Rank_Address_OFF (56) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_0_Rank_Address_WID (3) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_0_Rank_Address_MSK (0x700000000000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_0_Rank_Address_MAX (0x00000007) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_0_Rank_Address_DEF (0x00000000) + +#define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_1_REG (0x000048E0) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_1_Column_Address_OFF (3) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_1_Column_Address_WID_A0 (7) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_1_Column_Address_MSK_A0 (0x000003F8) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_1_Column_Address_MAX_A0 (0x0000007F) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_1_Column_Address_WID (8) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_1_Column_Address_MSK (0x000007F8) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_1_Column_Address_MAX (0x000000FF) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_1_Column_Address_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_1_Row_Address_OFF (24) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_1_Row_Address_WID (16) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_1_Row_Address_MSK (0xFFFF000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_1_Row_Address_MAX (0x0000FFFF) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_1_Row_Address_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_1_Bank_Address_OFF (48) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_1_Bank_Address_WID (3) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_1_Bank_Address_MSK (0x7000000000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_1_Bank_Address_MAX (0x00000007) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_1_Bank_Address_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_1_Rank_Address_OFF (56) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_1_Rank_Address_WID (3) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_1_Rank_Address_MSK (0x700000000000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_1_Rank_Address_MAX (0x00000007) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_1_Rank_Address_DEF (0x00000000) + +#define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_0_REG (0x000048E8) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_0_Column_Address_OFF (3) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_0_Column_Address_WID_A0 (7) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_0_Column_Address_MSK_A0 (0x000003F8) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_0_Column_Address_MAX_A0 (0x0000007F) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_0_Column_Address_DEF_A0 (0x0000007F) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_0_Column_Address_WID (8) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_0_Column_Address_MSK (0x000007F8) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_0_Column_Address_MAX (0x000000FF) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_0_Column_Address_DEF (0x000000FF) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_0_Row_Address_OFF (24) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_0_Row_Address_WID (16) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_0_Row_Address_MSK (0xFFFF000000ULL) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_0_Row_Address_MAX (0x0000FFFF) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_0_Row_Address_DEF (0x0000FFFF) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_0_Bank_Address_OFF (48) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_0_Bank_Address_WID (3) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_0_Bank_Address_MSK (0x7000000000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_0_Bank_Address_MAX (0x00000007) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_0_Bank_Address_DEF (0x00000007) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_0_Rank_Address_OFF (56) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_0_Rank_Address_WID (3) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_0_Rank_Address_MSK (0x700000000000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_0_Rank_Address_MAX (0x00000007) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_0_Rank_Address_DEF (0x00000007) + +#define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_1_REG (0x000048F0) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_1_Column_Address_OFF (3) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_1_Column_Address_WID_A0 (7) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_1_Column_Address_MSK_A0 (0x000003F8) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_1_Column_Address_MAX_A0 (0x0000007F) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_1_Column_Address_DEF_A0 (0x0000007F) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_1_Column_Address_WID (8) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_1_Column_Address_MSK (0x000007F8) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_1_Column_Address_MAX (0x000000FF) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_1_Column_Address_DEF (0x000000FF) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_1_Row_Address_OFF (24) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_1_Row_Address_WID (16) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_1_Row_Address_MSK (0xFFFF000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_1_Row_Address_MAX (0x0000FFFF) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_1_Row_Address_DEF (0x0000FFFF) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_1_Bank_Address_OFF (48) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_1_Bank_Address_WID (3) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_1_Bank_Address_MSK (0x7000000000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_1_Bank_Address_MAX (0x00000007) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_1_Bank_Address_DEF (0x00000007) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_1_Rank_Address_OFF (56) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_1_Rank_Address_WID (3) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_1_Rank_Address_MSK (0x700000000000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_1_Rank_Address_MAX (0x00000007) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_1_Rank_Address_DEF (0x00000007) + +#define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_0_REG (0x000048F8) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_0_Column_Address_OFF (3) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_0_Column_Address_WID_A0 (7) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_0_Column_Address_MSK_A0 (0x000003F8) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_0_Column_Address_MAX_A0 (0x0000007F) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_0_Column_Address_WID (8) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_0_Column_Address_MSK (0x000007F8) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_0_Column_Address_MAX (0x000000FF) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_0_Column_Address_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_0_Row_Address_OFF (24) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_0_Row_Address_WID (16) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_0_Row_Address_MSK (0xFFFF000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_0_Row_Address_MAX (0x0000FFFF) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_0_Row_Address_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_0_Bank_Address_OFF (48) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_0_Bank_Address_WID (3) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_0_Bank_Address_MSK (0x7000000000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_0_Bank_Address_MAX (0x00000007) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_0_Bank_Address_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_0_Rank_Address_OFF (56) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_0_Rank_Address_WID (3) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_0_Rank_Address_MSK (0x700000000000000ULL) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_0_Rank_Address_MAX (0x00000007) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_0_Rank_Address_DEF (0x00000000) + +#define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_1_REG (0x00004900) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_1_Column_Address_OFF (3) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_1_Column_Address_WID_A0 (7) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_1_Column_Address_MSK_A0 (0x000003F8) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_1_Column_Address_MAX_A0 (0x0000007F) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_1_Column_Address_WID (8) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_1_Column_Address_MSK (0x000007F8) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_1_Column_Address_MAX (0x000000FF) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_1_Column_Address_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_1_Row_Address_OFF (24) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_1_Row_Address_WID (16) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_1_Row_Address_MSK (0xFFFF000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_1_Row_Address_MAX (0x0000FFFF) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_1_Row_Address_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_1_Bank_Address_OFF (48) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_1_Bank_Address_WID (3) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_1_Bank_Address_MSK (0x7000000000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_1_Bank_Address_MAX (0x00000007) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_1_Bank_Address_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_1_Rank_Address_OFF (56) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_1_Rank_Address_WID (3) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_1_Rank_Address_MSK (0x700000000000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_1_Rank_Address_MAX (0x00000007) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_1_Rank_Address_DEF (0x00000000) + +#define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_REG (0x00004908) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Base_Column_Address_Order_OFF ( 0) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Base_Column_Address_Order_WID ( 2) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Base_Column_Address_Order_MSK (0x00000003) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Base_Column_Address_Order_MAX (0x00000003) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Base_Column_Address_Order_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Base_Row_Address_Order_OFF ( 2) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Base_Row_Address_Order_WID ( 2) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Base_Row_Address_Order_MSK (0x0000000C) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Base_Row_Address_Order_MAX (0x00000003) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Base_Row_Address_Order_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Base_Bank_Address_Order_OFF ( 4) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Base_Bank_Address_Order_WID ( 2) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Base_Bank_Address_Order_MSK (0x00000030) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Base_Bank_Address_Order_MAX (0x00000003) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Base_Bank_Address_Order_DEF (0x00000002) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Base_Rank_Address_Order_OFF ( 6) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Base_Rank_Address_Order_WID ( 2) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Base_Rank_Address_Order_MSK (0x000000C0) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Base_Rank_Address_Order_MAX (0x00000003) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Base_Rank_Address_Order_DEF (0x00000003) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Base_Address_Invert_Rate_OFF (13) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Base_Address_Invert_Rate_WID ( 3) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Base_Address_Invert_Rate_MSK (0x0000E000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Base_Address_Invert_Rate_MAX (0x00000007) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Base_Address_Invert_Rate_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Column_Base_Address_Invert_Enable_OFF (20) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Column_Base_Address_Invert_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Column_Base_Address_Invert_Enable_MSK (0x00100000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Column_Base_Address_Invert_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Column_Base_Address_Invert_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Row_Base_Address_Invert_Enable_OFF (21) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Row_Base_Address_Invert_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Row_Base_Address_Invert_Enable_MSK (0x00200000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Row_Base_Address_Invert_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Row_Base_Address_Invert_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Bank_Base_Address_Invert_Enable_OFF (22) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Bank_Base_Address_Invert_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Bank_Base_Address_Invert_Enable_MSK (0x00400000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Bank_Base_Address_Invert_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Bank_Base_Address_Invert_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Rank_Base_Address_Invert_Enable_OFF (23) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Rank_Base_Address_Invert_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Rank_Base_Address_Invert_Enable_MSK (0x00800000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Rank_Base_Address_Invert_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Rank_Base_Address_Invert_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Column_Base_Wrap_Trigger_Enable_OFF (24) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Column_Base_Wrap_Trigger_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Column_Base_Wrap_Trigger_Enable_MSK (0x01000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Column_Base_Wrap_Trigger_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Column_Base_Wrap_Trigger_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Row_Base_Wrap_Trigger_Enable_OFF (25) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Row_Base_Wrap_Trigger_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Row_Base_Wrap_Trigger_Enable_MSK (0x02000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Row_Base_Wrap_Trigger_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Row_Base_Wrap_Trigger_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Bank_Base_Wrap_Trigger_Enable_OFF (26) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Bank_Base_Wrap_Trigger_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Bank_Base_Wrap_Trigger_Enable_MSK (0x04000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Bank_Base_Wrap_Trigger_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Bank_Base_Wrap_Trigger_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Rank_Base_Wrap_Trigger_Enable_OFF (27) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Rank_Base_Wrap_Trigger_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Rank_Base_Wrap_Trigger_Enable_MSK (0x08000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Rank_Base_Wrap_Trigger_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Rank_Base_Wrap_Trigger_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Column_Base_Wrap_Carry_Enable_OFF (28) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Column_Base_Wrap_Carry_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Column_Base_Wrap_Carry_Enable_MSK (0x10000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Column_Base_Wrap_Carry_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Column_Base_Wrap_Carry_Enable_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Row_Base_Wrap_Carry_Enable_OFF (29) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Row_Base_Wrap_Carry_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Row_Base_Wrap_Carry_Enable_MSK (0x20000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Row_Base_Wrap_Carry_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Row_Base_Wrap_Carry_Enable_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Bank_Base_Wrap_Carry_Enable_OFF (30) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Bank_Base_Wrap_Carry_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Bank_Base_Wrap_Carry_Enable_MSK (0x40000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Bank_Base_Wrap_Carry_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Bank_Base_Wrap_Carry_Enable_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Rank_Base_Wrap_Carry_Enable_OFF (31) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Rank_Base_Wrap_Carry_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Rank_Base_Wrap_Carry_Enable_MSK (0x80000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Rank_Base_Wrap_Carry_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Rank_Base_Wrap_Carry_Enable_DEF (0x00000001) + +#define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_REG (0x0000490C) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Base_Column_Address_Order_OFF ( 0) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Base_Column_Address_Order_WID ( 2) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Base_Column_Address_Order_MSK (0x00000003) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Base_Column_Address_Order_MAX (0x00000003) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Base_Column_Address_Order_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Base_Row_Address_Order_OFF ( 2) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Base_Row_Address_Order_WID ( 2) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Base_Row_Address_Order_MSK (0x0000000C) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Base_Row_Address_Order_MAX (0x00000003) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Base_Row_Address_Order_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Base_Bank_Address_Order_OFF ( 4) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Base_Bank_Address_Order_WID ( 2) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Base_Bank_Address_Order_MSK (0x00000030) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Base_Bank_Address_Order_MAX (0x00000003) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Base_Bank_Address_Order_DEF (0x00000002) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Base_Rank_Address_Order_OFF ( 6) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Base_Rank_Address_Order_WID ( 2) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Base_Rank_Address_Order_MSK (0x000000C0) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Base_Rank_Address_Order_MAX (0x00000003) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Base_Rank_Address_Order_DEF (0x00000003) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Base_Address_Invert_Rate_OFF (13) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Base_Address_Invert_Rate_WID ( 3) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Base_Address_Invert_Rate_MSK (0x0000E000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Base_Address_Invert_Rate_MAX (0x00000007) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Base_Address_Invert_Rate_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Column_Base_Address_Invert_Enable_OFF (20) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Column_Base_Address_Invert_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Column_Base_Address_Invert_Enable_MSK (0x00100000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Column_Base_Address_Invert_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Column_Base_Address_Invert_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Row_Base_Address_Invert_Enable_OFF (21) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Row_Base_Address_Invert_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Row_Base_Address_Invert_Enable_MSK (0x00200000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Row_Base_Address_Invert_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Row_Base_Address_Invert_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Bank_Base_Address_Invert_Enable_OFF (22) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Bank_Base_Address_Invert_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Bank_Base_Address_Invert_Enable_MSK (0x00400000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Bank_Base_Address_Invert_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Bank_Base_Address_Invert_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Rank_Base_Address_Invert_Enable_OFF (23) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Rank_Base_Address_Invert_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Rank_Base_Address_Invert_Enable_MSK (0x00800000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Rank_Base_Address_Invert_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Rank_Base_Address_Invert_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Column_Base_Wrap_Trigger_Enable_OFF (24) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Column_Base_Wrap_Trigger_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Column_Base_Wrap_Trigger_Enable_MSK (0x01000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Column_Base_Wrap_Trigger_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Column_Base_Wrap_Trigger_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Row_Base_Wrap_Trigger_Enable_OFF (25) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Row_Base_Wrap_Trigger_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Row_Base_Wrap_Trigger_Enable_MSK (0x02000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Row_Base_Wrap_Trigger_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Row_Base_Wrap_Trigger_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Bank_Base_Wrap_Trigger_Enable_OFF (26) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Bank_Base_Wrap_Trigger_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Bank_Base_Wrap_Trigger_Enable_MSK (0x04000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Bank_Base_Wrap_Trigger_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Bank_Base_Wrap_Trigger_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Rank_Base_Wrap_Trigger_Enable_OFF (27) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Rank_Base_Wrap_Trigger_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Rank_Base_Wrap_Trigger_Enable_MSK (0x08000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Rank_Base_Wrap_Trigger_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Rank_Base_Wrap_Trigger_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Column_Base_Wrap_Carry_Enable_OFF (28) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Column_Base_Wrap_Carry_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Column_Base_Wrap_Carry_Enable_MSK (0x10000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Column_Base_Wrap_Carry_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Column_Base_Wrap_Carry_Enable_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Row_Base_Wrap_Carry_Enable_OFF (29) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Row_Base_Wrap_Carry_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Row_Base_Wrap_Carry_Enable_MSK (0x20000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Row_Base_Wrap_Carry_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Row_Base_Wrap_Carry_Enable_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Bank_Base_Wrap_Carry_Enable_OFF (30) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Bank_Base_Wrap_Carry_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Bank_Base_Wrap_Carry_Enable_MSK (0x40000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Bank_Base_Wrap_Carry_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Bank_Base_Wrap_Carry_Enable_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Rank_Base_Wrap_Carry_Enable_OFF (31) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Rank_Base_Wrap_Carry_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Rank_Base_Wrap_Carry_Enable_MSK (0x80000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Rank_Base_Wrap_Carry_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Rank_Base_Wrap_Carry_Enable_DEF (0x00000001) + +#define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_REG (0x00004910) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Column_Base_Address_Increment_OFF (3) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Column_Base_Address_Increment_WID_A0 (7) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Column_Base_Address_Increment_MSK_A0 (0x000003F8) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Column_Base_Address_Increment_MAX_A0 (0x0000007F) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Column_Base_Address_Increment_WID (8) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Column_Base_Address_Increment_MSK (0x000007F8) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Column_Base_Address_Increment_MAX (0x000000FF) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Column_Base_Address_Increment_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Column_Base_Address_Update_Rate_OFF (12) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Column_Base_Address_Update_Rate_WID (5) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Column_Base_Address_Update_Rate_MSK (0x0001F000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Column_Base_Address_Update_Rate_MAX (0x0000001F) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Column_Base_Address_Update_Rate_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Column_Base_Address_Update_Scale_OFF (19) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Column_Base_Address_Update_Scale_WID (1) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Column_Base_Address_Update_Scale_MSK (0x00080000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Column_Base_Address_Update_Scale_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Column_Base_Address_Update_Scale_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Row_Base_Address_Increment_OFF (20) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Row_Base_Address_Increment_WID (12) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Row_Base_Address_Increment_MSK (0xFFF00000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Row_Base_Address_Increment_MAX (0x00000FFF) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Row_Base_Address_Increment_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Row_Base_Address_Update_Rate_OFF (32) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Row_Base_Address_Update_Rate_WID (4) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Row_Base_Address_Update_Rate_MSK (0xF00000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Row_Base_Address_Update_Rate_MAX (0x0000000F) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Row_Base_Address_Update_Rate_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Row_Base_Address_Update_Scale_OFF (37) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Row_Base_Address_Update_Scale_WID (1) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Row_Base_Address_Update_Scale_MSK (0x2000000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Row_Base_Address_Update_Scale_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Row_Base_Address_Update_Scale_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Bank_Base_Address_Increment_OFF (38) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Bank_Base_Address_Increment_WID (3) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Bank_Base_Address_Increment_MSK (0x1C000000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Bank_Base_Address_Increment_MAX (0x00000007) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Bank_Base_Address_Increment_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Bank_Base_Address_Update_Rate_OFF (44) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Bank_Base_Address_Update_Rate_WID (5) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Bank_Base_Address_Update_Rate_MSK (0x1F00000000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Bank_Base_Address_Update_Rate_MAX (0x0000001F) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Bank_Base_Address_Update_Rate_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Bank_Base_Address_Update_Scale_OFF (51) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Bank_Base_Address_Update_Scale_WID (1) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Bank_Base_Address_Update_Scale_MSK (0x8000000000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Bank_Base_Address_Update_Scale_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Bank_Base_Address_Update_Scale_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Rank_Base_Address_Increment_OFF (52) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Rank_Base_Address_Increment_WID (3) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Rank_Base_Address_Increment_MSK (0x70000000000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Rank_Base_Address_Increment_MAX (0x00000007) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Rank_Base_Address_Increment_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Rank_Base_Address_Update_Rate_OFF (56) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Rank_Base_Address_Update_Rate_WID (5) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Rank_Base_Address_Update_Rate_MSK (0x1F00000000000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Rank_Base_Address_Update_Rate_MAX (0x0000001F) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Rank_Base_Address_Update_Rate_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Rank_Base_Address_Update_Scale_OFF (63) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Rank_Base_Address_Update_Scale_WID (1) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Rank_Base_Address_Update_Scale_MSK (0x8000000000000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Rank_Base_Address_Update_Scale_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Rank_Base_Address_Update_Scale_DEF (0x00000000) + +#define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_REG (0x00004918) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Column_Base_Address_Increment_OFF (3) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Column_Base_Address_Increment_WID_A0 (7) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Column_Base_Address_Increment_MSK_A0 (0x000003F8) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Column_Base_Address_Increment_MAX_A0 (0x0000007F) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Column_Base_Address_Increment_WID (8) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Column_Base_Address_Increment_MSK (0x000007F8) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Column_Base_Address_Increment_MAX (0x000000FF) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Column_Base_Address_Increment_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Column_Base_Address_Update_Rate_OFF (12) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Column_Base_Address_Update_Rate_WID (5) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Column_Base_Address_Update_Rate_MSK (0x0001F000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Column_Base_Address_Update_Rate_MAX (0x0000001F) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Column_Base_Address_Update_Rate_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Column_Base_Address_Update_Scale_OFF (19) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Column_Base_Address_Update_Scale_WID (1) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Column_Base_Address_Update_Scale_MSK (0x00080000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Column_Base_Address_Update_Scale_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Column_Base_Address_Update_Scale_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Row_Base_Address_Increment_OFF (20) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Row_Base_Address_Increment_WID (12) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Row_Base_Address_Increment_MSK (0xFFF00000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Row_Base_Address_Increment_MAX (0x00000FFF) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Row_Base_Address_Increment_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Row_Base_Address_Update_Rate_OFF (32) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Row_Base_Address_Update_Rate_WID (4) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Row_Base_Address_Update_Rate_MSK (0xF00000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Row_Base_Address_Update_Rate_MAX (0x0000000F) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Row_Base_Address_Update_Rate_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Row_Base_Address_Update_Scale_OFF (37) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Row_Base_Address_Update_Scale_WID (1) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Row_Base_Address_Update_Scale_MSK (0x2000000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Row_Base_Address_Update_Scale_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Row_Base_Address_Update_Scale_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Bank_Base_Address_Increment_OFF (38) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Bank_Base_Address_Increment_WID (3) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Bank_Base_Address_Increment_MSK (0x1C000000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Bank_Base_Address_Increment_MAX (0x00000007) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Bank_Base_Address_Increment_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Bank_Base_Address_Update_Rate_OFF (44) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Bank_Base_Address_Update_Rate_WID (5) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Bank_Base_Address_Update_Rate_MSK (0x1F00000000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Bank_Base_Address_Update_Rate_MAX (0x0000001F) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Bank_Base_Address_Update_Rate_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Bank_Base_Address_Update_Scale_OFF (51) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Bank_Base_Address_Update_Scale_WID (1) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Bank_Base_Address_Update_Scale_MSK (0x8000000000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Bank_Base_Address_Update_Scale_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Bank_Base_Address_Update_Scale_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Rank_Base_Address_Increment_OFF (52) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Rank_Base_Address_Increment_WID (3) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Rank_Base_Address_Increment_MSK (0x70000000000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Rank_Base_Address_Increment_MAX (0x00000007) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Rank_Base_Address_Increment_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Rank_Base_Address_Update_Rate_OFF (56) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Rank_Base_Address_Update_Rate_WID (5) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Rank_Base_Address_Update_Rate_MSK (0x1F00000000000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Rank_Base_Address_Update_Rate_MAX (0x0000001F) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Rank_Base_Address_Update_Rate_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Rank_Base_Address_Update_Scale_OFF (63) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Rank_Base_Address_Update_Scale_WID (1) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Rank_Base_Address_Update_Scale_MSK (0x8000000000000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Rank_Base_Address_Update_Scale_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Rank_Base_Address_Update_Scale_DEF (0x00000000) + +#define MCDFXS_CR_REUT_CH_SEQ_OFFSET_ADDR_CURRENT_MCMAIN_0_REG (0x00004920) + #define MCDFXS_CR_REUT_CH_SEQ_OFFSET_ADDR_CURRENT_MCMAIN_0_Column_Address_OFF (3) + #define MCDFXS_CR_REUT_CH_SEQ_OFFSET_ADDR_CURRENT_MCMAIN_0_Column_Address_WID_A0 (7) + #define MCDFXS_CR_REUT_CH_SEQ_OFFSET_ADDR_CURRENT_MCMAIN_0_Column_Address_MSK_A0 (0x000003F8) + #define MCDFXS_CR_REUT_CH_SEQ_OFFSET_ADDR_CURRENT_MCMAIN_0_Column_Address_MAX_A0 (0x0000007F) + #define MCDFXS_CR_REUT_CH_SEQ_OFFSET_ADDR_CURRENT_MCMAIN_0_Column_Address_WID (8) + #define MCDFXS_CR_REUT_CH_SEQ_OFFSET_ADDR_CURRENT_MCMAIN_0_Column_Address_MSK (0x000007F8) + #define MCDFXS_CR_REUT_CH_SEQ_OFFSET_ADDR_CURRENT_MCMAIN_0_Column_Address_MAX (0x000000FF) + #define MCDFXS_CR_REUT_CH_SEQ_OFFSET_ADDR_CURRENT_MCMAIN_0_Column_Address_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_OFFSET_ADDR_CURRENT_MCMAIN_0_Row_Address_OFF (24) + #define MCDFXS_CR_REUT_CH_SEQ_OFFSET_ADDR_CURRENT_MCMAIN_0_Row_Address_WID (16) + #define MCDFXS_CR_REUT_CH_SEQ_OFFSET_ADDR_CURRENT_MCMAIN_0_Row_Address_MSK (0xFFFF000000) + #define MCDFXS_CR_REUT_CH_SEQ_OFFSET_ADDR_CURRENT_MCMAIN_0_Row_Address_MAX (0x0000FFFF) + #define MCDFXS_CR_REUT_CH_SEQ_OFFSET_ADDR_CURRENT_MCMAIN_0_Row_Address_DEF (0x00000000) + +#define MCDFXS_CR_REUT_CH_SEQ_OFFSET_ADDR_CURRENT_MCMAIN_1_REG (0x00004928) + #define MCDFXS_CR_REUT_CH_SEQ_OFFSET_ADDR_CURRENT_MCMAIN_1_Column_Address_OFF (3) + #define MCDFXS_CR_REUT_CH_SEQ_OFFSET_ADDR_CURRENT_MCMAIN_1_Column_Address_WID_A0 (7) + #define MCDFXS_CR_REUT_CH_SEQ_OFFSET_ADDR_CURRENT_MCMAIN_1_Column_Address_MSK_A0 (0x000003F8) + #define MCDFXS_CR_REUT_CH_SEQ_OFFSET_ADDR_CURRENT_MCMAIN_1_Column_Address_MAX_A0 (0x0000007F) + #define MCDFXS_CR_REUT_CH_SEQ_OFFSET_ADDR_CURRENT_MCMAIN_1_Column_Address_WID (8) + #define MCDFXS_CR_REUT_CH_SEQ_OFFSET_ADDR_CURRENT_MCMAIN_1_Column_Address_MSK (0x000007F8) + #define MCDFXS_CR_REUT_CH_SEQ_OFFSET_ADDR_CURRENT_MCMAIN_1_Column_Address_MAX (0x000000FF) + #define MCDFXS_CR_REUT_CH_SEQ_OFFSET_ADDR_CURRENT_MCMAIN_1_Column_Address_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_OFFSET_ADDR_CURRENT_MCMAIN_1_Row_Address_OFF (24) + #define MCDFXS_CR_REUT_CH_SEQ_OFFSET_ADDR_CURRENT_MCMAIN_1_Row_Address_WID (16) + #define MCDFXS_CR_REUT_CH_SEQ_OFFSET_ADDR_CURRENT_MCMAIN_1_Row_Address_MSK (0xFFFF000000) + #define MCDFXS_CR_REUT_CH_SEQ_OFFSET_ADDR_CURRENT_MCMAIN_1_Row_Address_MAX (0x0000FFFF) + #define MCDFXS_CR_REUT_CH_SEQ_OFFSET_ADDR_CURRENT_MCMAIN_1_Row_Address_DEF (0x00000000) + +#define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_REG (0x00004930) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_Logical_to_Physical_Rank0_Mapping_OFF ( 0) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_Logical_to_Physical_Rank0_Mapping_WID ( 2) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_Logical_to_Physical_Rank0_Mapping_MSK (0x00000003) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_Logical_to_Physical_Rank0_Mapping_MAX (0x00000003) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_Logical_to_Physical_Rank0_Mapping_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_Logical_to_Physical_Rank1_Mapping_OFF ( 4) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_Logical_to_Physical_Rank1_Mapping_WID ( 2) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_Logical_to_Physical_Rank1_Mapping_MSK (0x00000030) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_Logical_to_Physical_Rank1_Mapping_MAX (0x00000003) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_Logical_to_Physical_Rank1_Mapping_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_Logical_to_Physical_Rank2_Mapping_OFF ( 8) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_Logical_to_Physical_Rank2_Mapping_WID ( 2) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_Logical_to_Physical_Rank2_Mapping_MSK (0x00000300) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_Logical_to_Physical_Rank2_Mapping_MAX (0x00000003) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_Logical_to_Physical_Rank2_Mapping_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_Logical_to_Physical_Rank3_Mapping_OFF (12) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_Logical_to_Physical_Rank3_Mapping_WID ( 2) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_Logical_to_Physical_Rank3_Mapping_MSK (0x00003000) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_Logical_to_Physical_Rank3_Mapping_MAX (0x00000003) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_Logical_to_Physical_Rank3_Mapping_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_Logical_to_Physical_Rank4_Mapping_OFF (16) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_Logical_to_Physical_Rank4_Mapping_WID ( 2) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_Logical_to_Physical_Rank4_Mapping_MSK (0x00030000) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_Logical_to_Physical_Rank4_Mapping_MAX (0x00000003) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_Logical_to_Physical_Rank4_Mapping_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_Logical_to_Physical_Rank5_Mapping_OFF (20) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_Logical_to_Physical_Rank5_Mapping_WID ( 2) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_Logical_to_Physical_Rank5_Mapping_MSK (0x00300000) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_Logical_to_Physical_Rank5_Mapping_MAX (0x00000003) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_Logical_to_Physical_Rank5_Mapping_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_Logical_to_Physical_Rank6_Mapping_OFF (24) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_Logical_to_Physical_Rank6_Mapping_WID ( 2) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_Logical_to_Physical_Rank6_Mapping_MSK (0x03000000) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_Logical_to_Physical_Rank6_Mapping_MAX (0x00000003) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_Logical_to_Physical_Rank6_Mapping_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_Logical_to_Physical_Rank7_Mapping_OFF (28) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_Logical_to_Physical_Rank7_Mapping_WID ( 2) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_Logical_to_Physical_Rank7_Mapping_MSK (0x30000000) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_Logical_to_Physical_Rank7_Mapping_MAX (0x00000003) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_Logical_to_Physical_Rank7_Mapping_DEF (0x00000000) + +#define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_1_REG (0x00004934) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_1_Logical_to_Physical_Rank0_Mapping_OFF ( 0) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_1_Logical_to_Physical_Rank0_Mapping_WID ( 2) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_1_Logical_to_Physical_Rank0_Mapping_MSK (0x00000003) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_1_Logical_to_Physical_Rank0_Mapping_MAX (0x00000003) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_1_Logical_to_Physical_Rank0_Mapping_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_1_Logical_to_Physical_Rank1_Mapping_OFF ( 4) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_1_Logical_to_Physical_Rank1_Mapping_WID ( 2) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_1_Logical_to_Physical_Rank1_Mapping_MSK (0x00000030) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_1_Logical_to_Physical_Rank1_Mapping_MAX (0x00000003) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_1_Logical_to_Physical_Rank1_Mapping_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_1_Logical_to_Physical_Rank2_Mapping_OFF ( 8) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_1_Logical_to_Physical_Rank2_Mapping_WID ( 2) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_1_Logical_to_Physical_Rank2_Mapping_MSK (0x00000300) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_1_Logical_to_Physical_Rank2_Mapping_MAX (0x00000003) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_1_Logical_to_Physical_Rank2_Mapping_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_1_Logical_to_Physical_Rank3_Mapping_OFF (12) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_1_Logical_to_Physical_Rank3_Mapping_WID ( 2) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_1_Logical_to_Physical_Rank3_Mapping_MSK (0x00003000) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_1_Logical_to_Physical_Rank3_Mapping_MAX (0x00000003) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_1_Logical_to_Physical_Rank3_Mapping_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_1_Logical_to_Physical_Rank4_Mapping_OFF (16) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_1_Logical_to_Physical_Rank4_Mapping_WID ( 2) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_1_Logical_to_Physical_Rank4_Mapping_MSK (0x00030000) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_1_Logical_to_Physical_Rank4_Mapping_MAX (0x00000003) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_1_Logical_to_Physical_Rank4_Mapping_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_1_Logical_to_Physical_Rank5_Mapping_OFF (20) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_1_Logical_to_Physical_Rank5_Mapping_WID ( 2) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_1_Logical_to_Physical_Rank5_Mapping_MSK (0x00300000) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_1_Logical_to_Physical_Rank5_Mapping_MAX (0x00000003) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_1_Logical_to_Physical_Rank5_Mapping_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_1_Logical_to_Physical_Rank6_Mapping_OFF (24) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_1_Logical_to_Physical_Rank6_Mapping_WID ( 2) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_1_Logical_to_Physical_Rank6_Mapping_MSK (0x03000000) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_1_Logical_to_Physical_Rank6_Mapping_MAX (0x00000003) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_1_Logical_to_Physical_Rank6_Mapping_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_1_Logical_to_Physical_Rank7_Mapping_OFF (28) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_1_Logical_to_Physical_Rank7_Mapping_WID ( 2) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_1_Logical_to_Physical_Rank7_Mapping_MSK (0x30000000) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_1_Logical_to_Physical_Rank7_Mapping_MAX (0x00000003) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_1_Logical_to_Physical_Rank7_Mapping_DEF (0x00000000) + +#define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_0_REG (0x00004938) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_0_Logical_to_Physical_Row0_Swizzle_OFF ( 0) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_0_Logical_to_Physical_Row0_Swizzle_WID ( 4) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_0_Logical_to_Physical_Row0_Swizzle_MSK (0x0000000F) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_0_Logical_to_Physical_Row0_Swizzle_MAX (0x0000000F) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_0_Logical_to_Physical_Row0_Swizzle_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_0_Logical_to_Physical_Row1_Swizzle_OFF ( 5) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_0_Logical_to_Physical_Row1_Swizzle_WID ( 4) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_0_Logical_to_Physical_Row1_Swizzle_MSK (0x000001E0) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_0_Logical_to_Physical_Row1_Swizzle_MAX (0x0000000F) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_0_Logical_to_Physical_Row1_Swizzle_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_0_Logical_to_Physical_Row2_Swizzle_OFF (10) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_0_Logical_to_Physical_Row2_Swizzle_WID ( 4) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_0_Logical_to_Physical_Row2_Swizzle_MSK (0x00003C00) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_0_Logical_to_Physical_Row2_Swizzle_MAX (0x0000000F) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_0_Logical_to_Physical_Row2_Swizzle_DEF (0x00000002) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_0_Logical_to_Physical_Row3_Swizzle_OFF (15) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_0_Logical_to_Physical_Row3_Swizzle_WID ( 4) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_0_Logical_to_Physical_Row3_Swizzle_MSK (0x00078000) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_0_Logical_to_Physical_Row3_Swizzle_MAX (0x0000000F) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_0_Logical_to_Physical_Row3_Swizzle_DEF (0x00000003) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_0_Logical_to_Physical_Row4_Swizzle_OFF (20) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_0_Logical_to_Physical_Row4_Swizzle_WID ( 4) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_0_Logical_to_Physical_Row4_Swizzle_MSK (0x00F00000) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_0_Logical_to_Physical_Row4_Swizzle_MAX (0x0000000F) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_0_Logical_to_Physical_Row4_Swizzle_DEF (0x00000004) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_0_Logical_to_Physical_Row5_Swizzle_OFF (25) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_0_Logical_to_Physical_Row5_Swizzle_WID ( 4) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_0_Logical_to_Physical_Row5_Swizzle_MSK (0x1E000000) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_0_Logical_to_Physical_Row5_Swizzle_MAX (0x0000000F) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_0_Logical_to_Physical_Row5_Swizzle_DEF (0x00000005) + +#define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_1_REG (0x0000493C) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_1_Logical_to_Physical_Row0_Swizzle_OFF ( 0) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_1_Logical_to_Physical_Row0_Swizzle_WID ( 4) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_1_Logical_to_Physical_Row0_Swizzle_MSK (0x0000000F) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_1_Logical_to_Physical_Row0_Swizzle_MAX (0x0000000F) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_1_Logical_to_Physical_Row0_Swizzle_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_1_Logical_to_Physical_Row1_Swizzle_OFF ( 5) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_1_Logical_to_Physical_Row1_Swizzle_WID ( 4) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_1_Logical_to_Physical_Row1_Swizzle_MSK (0x000001E0) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_1_Logical_to_Physical_Row1_Swizzle_MAX (0x0000000F) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_1_Logical_to_Physical_Row1_Swizzle_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_1_Logical_to_Physical_Row2_Swizzle_OFF (10) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_1_Logical_to_Physical_Row2_Swizzle_WID ( 4) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_1_Logical_to_Physical_Row2_Swizzle_MSK (0x00003C00) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_1_Logical_to_Physical_Row2_Swizzle_MAX (0x0000000F) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_1_Logical_to_Physical_Row2_Swizzle_DEF (0x00000002) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_1_Logical_to_Physical_Row3_Swizzle_OFF (15) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_1_Logical_to_Physical_Row3_Swizzle_WID ( 4) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_1_Logical_to_Physical_Row3_Swizzle_MSK (0x00078000) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_1_Logical_to_Physical_Row3_Swizzle_MAX (0x0000000F) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_1_Logical_to_Physical_Row3_Swizzle_DEF (0x00000003) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_1_Logical_to_Physical_Row4_Swizzle_OFF (20) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_1_Logical_to_Physical_Row4_Swizzle_WID ( 4) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_1_Logical_to_Physical_Row4_Swizzle_MSK (0x00F00000) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_1_Logical_to_Physical_Row4_Swizzle_MAX (0x0000000F) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_1_Logical_to_Physical_Row4_Swizzle_DEF (0x00000004) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_1_Logical_to_Physical_Row5_Swizzle_OFF (25) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_1_Logical_to_Physical_Row5_Swizzle_WID ( 4) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_1_Logical_to_Physical_Row5_Swizzle_MSK (0x1E000000) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_1_Logical_to_Physical_Row5_Swizzle_MAX (0x0000000F) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_1_Logical_to_Physical_Row5_Swizzle_DEF (0x00000005) + +#define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_REG (0x00004940) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row6_Swizzle_OFF ( 0) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row6_Swizzle_WID ( 4) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row6_Swizzle_MSK (0x0000000F) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row6_Swizzle_MAX (0x0000000F) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row6_Swizzle_DEF (0x00000006) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row7_Swizzle_OFF ( 5) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row7_Swizzle_WID ( 4) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row7_Swizzle_MSK (0x000001E0) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row7_Swizzle_MAX (0x0000000F) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row7_Swizzle_DEF (0x00000007) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row8_Swizzle_OFF (10) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row8_Swizzle_WID ( 4) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row8_Swizzle_MSK (0x00003C00) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row8_Swizzle_MAX (0x0000000F) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row8_Swizzle_DEF (0x00000008) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row9_Swizzle_OFF (15) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row9_Swizzle_WID ( 4) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row9_Swizzle_MSK (0x00078000) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row9_Swizzle_MAX (0x0000000F) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row9_Swizzle_DEF (0x00000009) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row10_Swizzle_OFF (20) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row10_Swizzle_WID ( 4) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row10_Swizzle_MSK (0x00F00000) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row10_Swizzle_MAX (0x0000000F) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row10_Swizzle_DEF (0x0000000A) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row11_Swizzle_OFF (25) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row11_Swizzle_WID ( 4) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row11_Swizzle_MSK (0x1E000000) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row11_Swizzle_MAX (0x0000000F) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row11_Swizzle_DEF (0x0000000B) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row12_Swizzle_OFF (30) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row12_Swizzle_WID ( 4) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row12_Swizzle_MSK (0x3C0000000) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row12_Swizzle_MAX (0x0000000F) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row12_Swizzle_DEF (0x0000000C) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row13_Swizzle_OFF (35) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row13_Swizzle_WID ( 4) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row13_Swizzle_MSK (0x7800000000) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row13_Swizzle_MAX (0x0000000F) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row13_Swizzle_DEF (0x0000000D) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row14_Swizzle_OFF (40) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row14_Swizzle_WID ( 4) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row14_Swizzle_MSK (0xF0000000000) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row14_Swizzle_MAX (0x0000000F) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row14_Swizzle_DEF (0x0000000E) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row15_Swizzle_OFF (45) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row15_Swizzle_WID ( 4) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row15_Swizzle_MSK (0x1E00000000000) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row15_Swizzle_MAX (0x0000000F) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row15_Swizzle_DEF (0x0000000F) + +#define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_REG (0x00004948) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row6_Swizzle_OFF ( 0) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row6_Swizzle_WID ( 4) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row6_Swizzle_MSK (0x0000000F) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row6_Swizzle_MAX (0x0000000F) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row6_Swizzle_DEF (0x00000006) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row7_Swizzle_OFF ( 5) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row7_Swizzle_WID ( 4) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row7_Swizzle_MSK (0x000001E0) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row7_Swizzle_MAX (0x0000000F) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row7_Swizzle_DEF (0x00000007) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row8_Swizzle_OFF (10) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row8_Swizzle_WID ( 4) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row8_Swizzle_MSK (0x00003C00) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row8_Swizzle_MAX (0x0000000F) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row8_Swizzle_DEF (0x00000008) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row9_Swizzle_OFF (15) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row9_Swizzle_WID ( 4) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row9_Swizzle_MSK (0x00078000) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row9_Swizzle_MAX (0x0000000F) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row9_Swizzle_DEF (0x00000009) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row10_Swizzle_OFF (20) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row10_Swizzle_WID ( 4) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row10_Swizzle_MSK (0x00F00000) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row10_Swizzle_MAX (0x0000000F) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row10_Swizzle_DEF (0x0000000A) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row11_Swizzle_OFF (25) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row11_Swizzle_WID ( 4) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row11_Swizzle_MSK (0x1E000000) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row11_Swizzle_MAX (0x0000000F) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row11_Swizzle_DEF (0x0000000B) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row12_Swizzle_OFF (30) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row12_Swizzle_WID ( 4) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row12_Swizzle_MSK (0x3C0000000) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row12_Swizzle_MAX (0x0000000F) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row12_Swizzle_DEF (0x0000000C) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row13_Swizzle_OFF (35) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row13_Swizzle_WID ( 4) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row13_Swizzle_MSK (0x7800000000) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row13_Swizzle_MAX (0x0000000F) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row13_Swizzle_DEF (0x0000000D) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row14_Swizzle_OFF (40) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row14_Swizzle_WID ( 4) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row14_Swizzle_MSK (0xF0000000000) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row14_Swizzle_MAX (0x0000000F) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row14_Swizzle_DEF (0x0000000E) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row15_Swizzle_OFF (45) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row15_Swizzle_WID ( 4) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row15_Swizzle_MSK (0x1E00000000000) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row15_Swizzle_MAX (0x0000000F) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row15_Swizzle_DEF (0x0000000F) + +#define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_ADDRESS_MCMAIN_0_REG (0x00004950) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_ADDRESS_MCMAIN_0_Dummy_Read_Row_Current_Address_OFF ( 0) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_ADDRESS_MCMAIN_0_Dummy_Read_Row_Current_Address_WID (16) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_ADDRESS_MCMAIN_0_Dummy_Read_Row_Current_Address_MSK (0x0000FFFF) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_ADDRESS_MCMAIN_0_Dummy_Read_Row_Current_Address_MAX (0x0000FFFF) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_ADDRESS_MCMAIN_0_Dummy_Read_Row_Current_Address_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_ADDRESS_MCMAIN_0_Dummy_Read_Bank_Current_Address_OFF (24) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_ADDRESS_MCMAIN_0_Dummy_Read_Bank_Current_Address_WID ( 3) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_ADDRESS_MCMAIN_0_Dummy_Read_Bank_Current_Address_MSK (0x07000000) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_ADDRESS_MCMAIN_0_Dummy_Read_Bank_Current_Address_MAX (0x00000007) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_ADDRESS_MCMAIN_0_Dummy_Read_Bank_Current_Address_DEF (0x00000000) + +#define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_ADDRESS_MCMAIN_1_REG (0x00004954) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_ADDRESS_MCMAIN_1_Dummy_Read_Row_Current_Address_OFF ( 0) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_ADDRESS_MCMAIN_1_Dummy_Read_Row_Current_Address_WID (16) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_ADDRESS_MCMAIN_1_Dummy_Read_Row_Current_Address_MSK (0x0000FFFF) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_ADDRESS_MCMAIN_1_Dummy_Read_Row_Current_Address_MAX (0x0000FFFF) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_ADDRESS_MCMAIN_1_Dummy_Read_Row_Current_Address_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_ADDRESS_MCMAIN_1_Dummy_Read_Bank_Current_Address_OFF (24) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_ADDRESS_MCMAIN_1_Dummy_Read_Bank_Current_Address_WID ( 3) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_ADDRESS_MCMAIN_1_Dummy_Read_Bank_Current_Address_MSK (0x07000000) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_ADDRESS_MCMAIN_1_Dummy_Read_Bank_Current_Address_MAX (0x00000007) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_ADDRESS_MCMAIN_1_Dummy_Read_Bank_Current_Address_DEF (0x00000000) + +#define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_MASK_MCMAIN_0_REG (0x00004958) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_MASK_MCMAIN_0_Dummy_Read_Bank_Mask_OFF ( 0) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_MASK_MCMAIN_0_Dummy_Read_Bank_Mask_WID ( 8) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_MASK_MCMAIN_0_Dummy_Read_Bank_Mask_MSK (0x000000FF) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_MASK_MCMAIN_0_Dummy_Read_Bank_Mask_MAX (0x000000FF) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_MASK_MCMAIN_0_Dummy_Read_Bank_Mask_DEF (0x00000000) + +#define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_MASK_MCMAIN_1_REG (0x0000495C) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_MASK_MCMAIN_1_Dummy_Read_Bank_Mask_OFF ( 0) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_MASK_MCMAIN_1_Dummy_Read_Bank_Mask_WID ( 8) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_MASK_MCMAIN_1_Dummy_Read_Bank_Mask_MSK (0x000000FF) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_MASK_MCMAIN_1_Dummy_Read_Bank_Mask_MAX (0x000000FF) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_MASK_MCMAIN_1_Dummy_Read_Bank_Mask_DEF (0x00000000) + +#define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_0_REG (0x00004960) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_0_L_DummyRead_Select_OFF ( 0) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_0_L_DummyRead_Select_WID ( 1) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_0_L_DummyRead_Select_MSK (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_0_L_DummyRead_Select_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_0_L_DummyRead_Select_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_0_Enable_Sweep_Frequency_OFF ( 1) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_0_Enable_Sweep_Frequency_WID ( 1) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_0_Enable_Sweep_Frequency_MSK (0x00000002) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_0_Enable_Sweep_Frequency_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_0_Enable_Sweep_Frequency_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_0_L_counter_OFF ( 8) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_0_L_counter_WID ( 8) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_0_L_counter_MSK (0x0000FF00) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_0_L_counter_MAX (0x000000FF) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_0_L_counter_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_0_M_counter_OFF (16) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_0_M_counter_WID ( 8) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_0_M_counter_MSK (0x00FF0000) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_0_M_counter_MAX (0x000000FF) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_0_M_counter_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_0_N_Counter_OFF (24) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_0_N_Counter_WID ( 8) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_0_N_Counter_MSK (0xFF000000) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_0_N_Counter_MAX (0x000000FF) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_0_N_Counter_DEF (0x00000001) + +#define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_1_REG (0x00004964) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_1_L_DummyRead_Select_OFF ( 0) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_1_L_DummyRead_Select_WID ( 1) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_1_L_DummyRead_Select_MSK (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_1_L_DummyRead_Select_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_1_L_DummyRead_Select_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_1_Enable_Sweep_Frequency_OFF ( 1) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_1_Enable_Sweep_Frequency_WID ( 1) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_1_Enable_Sweep_Frequency_MSK (0x00000002) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_1_Enable_Sweep_Frequency_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_1_Enable_Sweep_Frequency_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_1_L_counter_OFF ( 8) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_1_L_counter_WID ( 8) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_1_L_counter_MSK (0x0000FF00) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_1_L_counter_MAX (0x000000FF) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_1_L_counter_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_1_M_counter_OFF (16) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_1_M_counter_WID ( 8) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_1_M_counter_MSK (0x00FF0000) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_1_M_counter_MAX (0x000000FF) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_1_M_counter_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_1_N_Counter_OFF (24) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_1_N_Counter_WID ( 8) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_1_N_Counter_MSK (0xFF000000) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_1_N_Counter_MAX (0x000000FF) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_1_N_Counter_DEF (0x00000001) + +#define MCDFXS_CR_VISA_CTL_MCDFXS_MCMAIN_REG (0x00004968) + #define MCDFXS_CR_VISA_CTL_MCDFXS_MCMAIN_EN_CLK_OFF ( 0) + #define MCDFXS_CR_VISA_CTL_MCDFXS_MCMAIN_EN_CLK_WID ( 1) + #define MCDFXS_CR_VISA_CTL_MCDFXS_MCMAIN_EN_CLK_MSK (0x00000001) + #define MCDFXS_CR_VISA_CTL_MCDFXS_MCMAIN_EN_CLK_MAX (0x00000001) + #define MCDFXS_CR_VISA_CTL_MCDFXS_MCMAIN_EN_CLK_DEF (0x00000000) + #define MCDFXS_CR_VISA_CTL_MCDFXS_MCMAIN_L0_DATA_BYTE_SEL_OFF ( 1) + #define MCDFXS_CR_VISA_CTL_MCDFXS_MCMAIN_L0_DATA_BYTE_SEL_WID ( 7) + #define MCDFXS_CR_VISA_CTL_MCDFXS_MCMAIN_L0_DATA_BYTE_SEL_MSK (0x000000FE) + #define MCDFXS_CR_VISA_CTL_MCDFXS_MCMAIN_L0_DATA_BYTE_SEL_MAX (0x0000007F) + #define MCDFXS_CR_VISA_CTL_MCDFXS_MCMAIN_L0_DATA_BYTE_SEL_DEF (0x00000000) + #define MCDFXS_CR_VISA_CTL_MCDFXS_MCMAIN_L0_BYP_SEL_OFF ( 8) + #define MCDFXS_CR_VISA_CTL_MCDFXS_MCMAIN_L0_BYP_SEL_WID ( 1) + #define MCDFXS_CR_VISA_CTL_MCDFXS_MCMAIN_L0_BYP_SEL_MSK (0x00000100) + #define MCDFXS_CR_VISA_CTL_MCDFXS_MCMAIN_L0_BYP_SEL_MAX (0x00000001) + #define MCDFXS_CR_VISA_CTL_MCDFXS_MCMAIN_L0_BYP_SEL_DEF (0x00000000) + #define MCDFXS_CR_VISA_CTL_MCDFXS_MCMAIN_L1_DATA_BYTE_SEL_OFF ( 9) + #define MCDFXS_CR_VISA_CTL_MCDFXS_MCMAIN_L1_DATA_BYTE_SEL_WID ( 7) + #define MCDFXS_CR_VISA_CTL_MCDFXS_MCMAIN_L1_DATA_BYTE_SEL_MSK (0x0000FE00) + #define MCDFXS_CR_VISA_CTL_MCDFXS_MCMAIN_L1_DATA_BYTE_SEL_MAX (0x0000007F) + #define MCDFXS_CR_VISA_CTL_MCDFXS_MCMAIN_L1_DATA_BYTE_SEL_DEF (0x00000000) + #define MCDFXS_CR_VISA_CTL_MCDFXS_MCMAIN_L1_BYP_SEL_OFF (16) + #define MCDFXS_CR_VISA_CTL_MCDFXS_MCMAIN_L1_BYP_SEL_WID ( 1) + #define MCDFXS_CR_VISA_CTL_MCDFXS_MCMAIN_L1_BYP_SEL_MSK (0x00010000) + #define MCDFXS_CR_VISA_CTL_MCDFXS_MCMAIN_L1_BYP_SEL_MAX (0x00000001) + #define MCDFXS_CR_VISA_CTL_MCDFXS_MCMAIN_L1_BYP_SEL_DEF (0x00000000) + +#define MCDFXS_CR_REUT_CH_ERR_TRIGGER_CTL_MCMAIN_REG (0x0000496C) + #define MCDFXS_CR_REUT_CH_ERR_TRIGGER_CTL_MCMAIN_Trigger_In_Global_Start_OFF ( 0) + #define MCDFXS_CR_REUT_CH_ERR_TRIGGER_CTL_MCMAIN_Trigger_In_Global_Start_WID ( 1) + #define MCDFXS_CR_REUT_CH_ERR_TRIGGER_CTL_MCMAIN_Trigger_In_Global_Start_MSK (0x00000001) + #define MCDFXS_CR_REUT_CH_ERR_TRIGGER_CTL_MCMAIN_Trigger_In_Global_Start_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH_ERR_TRIGGER_CTL_MCMAIN_Trigger_In_Global_Start_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_ERR_TRIGGER_CTL_MCMAIN_Trigger_Out_Global_Start_OFF ( 1) + #define MCDFXS_CR_REUT_CH_ERR_TRIGGER_CTL_MCMAIN_Trigger_Out_Global_Start_WID ( 1) + #define MCDFXS_CR_REUT_CH_ERR_TRIGGER_CTL_MCMAIN_Trigger_Out_Global_Start_MSK (0x00000002) + #define MCDFXS_CR_REUT_CH_ERR_TRIGGER_CTL_MCMAIN_Trigger_Out_Global_Start_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH_ERR_TRIGGER_CTL_MCMAIN_Trigger_Out_Global_Start_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_ERR_TRIGGER_CTL_MCMAIN_Trigger_Out_On_Error_0_OFF ( 7) + #define MCDFXS_CR_REUT_CH_ERR_TRIGGER_CTL_MCMAIN_Trigger_Out_On_Error_0_WID ( 1) + #define MCDFXS_CR_REUT_CH_ERR_TRIGGER_CTL_MCMAIN_Trigger_Out_On_Error_0_MSK (0x00000080) + #define MCDFXS_CR_REUT_CH_ERR_TRIGGER_CTL_MCMAIN_Trigger_Out_On_Error_0_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH_ERR_TRIGGER_CTL_MCMAIN_Trigger_Out_On_Error_0_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_ERR_TRIGGER_CTL_MCMAIN_Trigger_Out_On_Error_1_OFF ( 8) + #define MCDFXS_CR_REUT_CH_ERR_TRIGGER_CTL_MCMAIN_Trigger_Out_On_Error_1_WID ( 1) + #define MCDFXS_CR_REUT_CH_ERR_TRIGGER_CTL_MCMAIN_Trigger_Out_On_Error_1_MSK (0x00000100) + #define MCDFXS_CR_REUT_CH_ERR_TRIGGER_CTL_MCMAIN_Trigger_Out_On_Error_1_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH_ERR_TRIGGER_CTL_MCMAIN_Trigger_Out_On_Error_1_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_ERR_TRIGGER_CTL_MCMAIN_Trigger_Out_On_Channel_Test_Done_Status_0_OFF (15) + #define MCDFXS_CR_REUT_CH_ERR_TRIGGER_CTL_MCMAIN_Trigger_Out_On_Channel_Test_Done_Status_0_WID ( 1) + #define MCDFXS_CR_REUT_CH_ERR_TRIGGER_CTL_MCMAIN_Trigger_Out_On_Channel_Test_Done_Status_0_MSK (0x00008000) + #define MCDFXS_CR_REUT_CH_ERR_TRIGGER_CTL_MCMAIN_Trigger_Out_On_Channel_Test_Done_Status_0_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH_ERR_TRIGGER_CTL_MCMAIN_Trigger_Out_On_Channel_Test_Done_Status_0_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_ERR_TRIGGER_CTL_MCMAIN_Trigger_Out_On_Channel_Test_Done_Status_1_OFF (16) + #define MCDFXS_CR_REUT_CH_ERR_TRIGGER_CTL_MCMAIN_Trigger_Out_On_Channel_Test_Done_Status_1_WID ( 1) + #define MCDFXS_CR_REUT_CH_ERR_TRIGGER_CTL_MCMAIN_Trigger_Out_On_Channel_Test_Done_Status_1_MSK (0x00010000) + #define MCDFXS_CR_REUT_CH_ERR_TRIGGER_CTL_MCMAIN_Trigger_Out_On_Channel_Test_Done_Status_1_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH_ERR_TRIGGER_CTL_MCMAIN_Trigger_Out_On_Channel_Test_Done_Status_1_DEF (0x00000000) + +#define MCDFXS_CR_REUT_CH_SEQ_LOOPCOUNT_LIMIT_MCMAIN_0_REG (0x00004980) + #define MCDFXS_CR_REUT_CH_SEQ_LOOPCOUNT_LIMIT_MCMAIN_0_Loopcount_Limit_OFF (0) + #define MCDFXS_CR_REUT_CH_SEQ_LOOPCOUNT_LIMIT_MCMAIN_0_Loopcount_Limit_WID (32) + #define MCDFXS_CR_REUT_CH_SEQ_LOOPCOUNT_LIMIT_MCMAIN_0_Loopcount_Limit_MSK (0xFFFFFFFF) + #define MCDFXS_CR_REUT_CH_SEQ_LOOPCOUNT_LIMIT_MCMAIN_0_Loopcount_Limit_MAX (0xFFFFFFFF) + #define MCDFXS_CR_REUT_CH_SEQ_LOOPCOUNT_LIMIT_MCMAIN_0_Loopcount_Limit_DEF (0x00000000) + +#define MCDFXS_CR_REUT_CH_SEQ_LOOPCOUNT_LIMIT_MCMAIN_1_REG (0x00004984) + #define MCDFXS_CR_REUT_CH_SEQ_LOOPCOUNT_LIMIT_MCMAIN_1_Loopcount_Limit_OFF (0) + #define MCDFXS_CR_REUT_CH_SEQ_LOOPCOUNT_LIMIT_MCMAIN_1_Loopcount_Limit_WID (32) + #define MCDFXS_CR_REUT_CH_SEQ_LOOPCOUNT_LIMIT_MCMAIN_1_Loopcount_Limit_MSK (0xFFFFFFFF) + #define MCDFXS_CR_REUT_CH_SEQ_LOOPCOUNT_LIMIT_MCMAIN_1_Loopcount_Limit_MAX (0xFFFFFFFF) + #define MCDFXS_CR_REUT_CH_SEQ_LOOPCOUNT_LIMIT_MCMAIN_1_Loopcount_Limit_DEF (0x00000000) + +#define MCSCHEDS_CR_TC_BANK_REG (0x00004C00) + #define MCSCHEDS_CR_TC_BANK_tRCD_OFF ( 0) + #define MCSCHEDS_CR_TC_BANK_tRCD_WID ( 5) + #define MCSCHEDS_CR_TC_BANK_tRCD_MSK (0x0000001F) + #define MCSCHEDS_CR_TC_BANK_tRCD_MAX (0x0000001F) + #define MCSCHEDS_CR_TC_BANK_tRCD_DEF (0x00000006) + #define MCSCHEDS_CR_TC_BANK_tRP_OFF ( 5) + #define MCSCHEDS_CR_TC_BANK_tRP_WID ( 5) + #define MCSCHEDS_CR_TC_BANK_tRP_MSK (0x000003E0) + #define MCSCHEDS_CR_TC_BANK_tRP_MAX (0x0000001F) + #define MCSCHEDS_CR_TC_BANK_tRP_DEF (0x00000006) + #define MCSCHEDS_CR_TC_BANK_tRAS_OFF (10) + #define MCSCHEDS_CR_TC_BANK_tRAS_WID ( 6) + #define MCSCHEDS_CR_TC_BANK_tRAS_MSK (0x0000FC00) + #define MCSCHEDS_CR_TC_BANK_tRAS_MAX (0x0000003F) + #define MCSCHEDS_CR_TC_BANK_tRAS_DEF (0x00000014) + #define MCSCHEDS_CR_TC_BANK_tRDPRE_OFF (16) + #define MCSCHEDS_CR_TC_BANK_tRDPRE_WID ( 4) + #define MCSCHEDS_CR_TC_BANK_tRDPRE_MSK (0x000F0000) + #define MCSCHEDS_CR_TC_BANK_tRDPRE_MAX (0x0000000F) + #define MCSCHEDS_CR_TC_BANK_tRDPRE_DEF (0x00000004) + #define MCSCHEDS_CR_TC_BANK_tWRPRE_OFF (20) + #define MCSCHEDS_CR_TC_BANK_tWRPRE_WID ( 6) + #define MCSCHEDS_CR_TC_BANK_tWRPRE_MSK (0x03F00000) + #define MCSCHEDS_CR_TC_BANK_tWRPRE_MAX (0x0000003F) + #define MCSCHEDS_CR_TC_BANK_tWRPRE_DEF (0x00000004) + #define MCSCHEDS_CR_TC_BANK_tRRD_OFF (26) + #define MCSCHEDS_CR_TC_BANK_tRRD_WID ( 4) + #define MCSCHEDS_CR_TC_BANK_tRRD_MSK (0x3C000000) + #define MCSCHEDS_CR_TC_BANK_tRRD_MAX (0x0000000F) + #define MCSCHEDS_CR_TC_BANK_tRRD_DEF (0x00000004) + #define MCSCHEDS_CR_TC_BANK_tRPab_ext_OFF (30) + #define MCSCHEDS_CR_TC_BANK_tRPab_ext_WID ( 2) + #define MCSCHEDS_CR_TC_BANK_tRPab_ext_MSK (0xC0000000) + #define MCSCHEDS_CR_TC_BANK_tRPab_ext_MAX (0x00000003) + #define MCSCHEDS_CR_TC_BANK_tRPab_ext_DEF (0x00000000) + +#define MCSCHEDS_CR_TC_BANK_RANK_A_REG (0x00004C04) + #define MCSCHEDS_CR_TC_BANK_RANK_A_tCKE_OFF ( 0) + #define MCSCHEDS_CR_TC_BANK_RANK_A_tCKE_WID ( 4) + #define MCSCHEDS_CR_TC_BANK_RANK_A_tCKE_MSK (0x0000000F) + #define MCSCHEDS_CR_TC_BANK_RANK_A_tCKE_MAX (0x0000000F) + #define MCSCHEDS_CR_TC_BANK_RANK_A_tCKE_DEF (0x00000003) + #define MCSCHEDS_CR_TC_BANK_RANK_A_tFAW_OFF ( 4) + #define MCSCHEDS_CR_TC_BANK_RANK_A_tFAW_WID ( 8) + #define MCSCHEDS_CR_TC_BANK_RANK_A_tFAW_MSK (0x00000FF0) + #define MCSCHEDS_CR_TC_BANK_RANK_A_tFAW_MAX (0x000000FF) + #define MCSCHEDS_CR_TC_BANK_RANK_A_tFAW_DEF (0x00000010) + #define MCSCHEDS_CR_TC_BANK_RANK_A_tRDRD_OFF (12) + #define MCSCHEDS_CR_TC_BANK_RANK_A_tRDRD_WID ( 3) + #define MCSCHEDS_CR_TC_BANK_RANK_A_tRDRD_MSK (0x00007000) + #define MCSCHEDS_CR_TC_BANK_RANK_A_tRDRD_MAX (0x00000007) + #define MCSCHEDS_CR_TC_BANK_RANK_A_tRDRD_DEF (0x00000004) + #define MCSCHEDS_CR_TC_BANK_RANK_A_tRDRD_dr_OFF (15) + #define MCSCHEDS_CR_TC_BANK_RANK_A_tRDRD_dr_WID ( 4) + #define MCSCHEDS_CR_TC_BANK_RANK_A_tRDRD_dr_MSK (0x00078000) + #define MCSCHEDS_CR_TC_BANK_RANK_A_tRDRD_dr_MAX (0x0000000F) + #define MCSCHEDS_CR_TC_BANK_RANK_A_tRDRD_dr_DEF (0x00000004) + #define MCSCHEDS_CR_TC_BANK_RANK_A_tRDRD_dd_OFF (19) + #define MCSCHEDS_CR_TC_BANK_RANK_A_tRDRD_dd_WID ( 4) + #define MCSCHEDS_CR_TC_BANK_RANK_A_tRDRD_dd_MSK (0x00780000) + #define MCSCHEDS_CR_TC_BANK_RANK_A_tRDRD_dd_MAX (0x0000000F) + #define MCSCHEDS_CR_TC_BANK_RANK_A_tRDRD_dd_DEF (0x00000004) + #define MCSCHEDS_CR_TC_BANK_RANK_A_tRDPDEN_OFF (23) + #define MCSCHEDS_CR_TC_BANK_RANK_A_tRDPDEN_WID ( 5) + #define MCSCHEDS_CR_TC_BANK_RANK_A_tRDPDEN_MSK (0x0F800000) + #define MCSCHEDS_CR_TC_BANK_RANK_A_tRDPDEN_MAX (0x0000001F) + #define MCSCHEDS_CR_TC_BANK_RANK_A_tRDPDEN_DEF (0x00000004) + #define MCSCHEDS_CR_TC_BANK_RANK_A_CMD_3st_OFF (29) + #define MCSCHEDS_CR_TC_BANK_RANK_A_CMD_3st_WID ( 1) + #define MCSCHEDS_CR_TC_BANK_RANK_A_CMD_3st_MSK (0x20000000) + #define MCSCHEDS_CR_TC_BANK_RANK_A_CMD_3st_MAX (0x00000001) + #define MCSCHEDS_CR_TC_BANK_RANK_A_CMD_3st_DEF (0x00000000) + #define MCSCHEDS_CR_TC_BANK_RANK_A_CMD_stretch_OFF (30) + #define MCSCHEDS_CR_TC_BANK_RANK_A_CMD_stretch_WID ( 2) + #define MCSCHEDS_CR_TC_BANK_RANK_A_CMD_stretch_MSK (0xC0000000) + #define MCSCHEDS_CR_TC_BANK_RANK_A_CMD_stretch_MAX (0x00000003) + #define MCSCHEDS_CR_TC_BANK_RANK_A_CMD_stretch_DEF (0x00000002) + +#define MCSCHEDS_CR_TC_BANK_RANK_B_REG (0x00004C08) + #define MCSCHEDS_CR_TC_BANK_RANK_B_tWRRD_OFF ( 0) + #define MCSCHEDS_CR_TC_BANK_RANK_B_tWRRD_WID ( 6) + #define MCSCHEDS_CR_TC_BANK_RANK_B_tWRRD_MSK (0x0000003F) + #define MCSCHEDS_CR_TC_BANK_RANK_B_tWRRD_MAX (0x0000003F) + #define MCSCHEDS_CR_TC_BANK_RANK_B_tWRRD_DEF (0x00000005) + #define MCSCHEDS_CR_TC_BANK_RANK_B_tWRRD_dr_OFF ( 6) + #define MCSCHEDS_CR_TC_BANK_RANK_B_tWRRD_dr_WID ( 4) + #define MCSCHEDS_CR_TC_BANK_RANK_B_tWRRD_dr_MSK (0x000003C0) + #define MCSCHEDS_CR_TC_BANK_RANK_B_tWRRD_dr_MAX (0x0000000F) + #define MCSCHEDS_CR_TC_BANK_RANK_B_tWRRD_dr_DEF (0x00000005) + #define MCSCHEDS_CR_TC_BANK_RANK_B_tWRRD_dd_OFF (10) + #define MCSCHEDS_CR_TC_BANK_RANK_B_tWRRD_dd_WID ( 4) + #define MCSCHEDS_CR_TC_BANK_RANK_B_tWRRD_dd_MSK (0x00003C00) + #define MCSCHEDS_CR_TC_BANK_RANK_B_tWRRD_dd_MAX (0x0000000F) + #define MCSCHEDS_CR_TC_BANK_RANK_B_tWRRD_dd_DEF (0x00000005) + #define MCSCHEDS_CR_TC_BANK_RANK_B_tWRWR_OFF (14) + #define MCSCHEDS_CR_TC_BANK_RANK_B_tWRWR_WID ( 3) + #define MCSCHEDS_CR_TC_BANK_RANK_B_tWRWR_MSK (0x0001C000) + #define MCSCHEDS_CR_TC_BANK_RANK_B_tWRWR_MAX (0x00000007) + #define MCSCHEDS_CR_TC_BANK_RANK_B_tWRWR_DEF (0x00000005) + #define MCSCHEDS_CR_TC_BANK_RANK_B_tWRWR_dr_OFF (17) + #define MCSCHEDS_CR_TC_BANK_RANK_B_tWRWR_dr_WID ( 4) + #define MCSCHEDS_CR_TC_BANK_RANK_B_tWRWR_dr_MSK (0x001E0000) + #define MCSCHEDS_CR_TC_BANK_RANK_B_tWRWR_dr_MAX (0x0000000F) + #define MCSCHEDS_CR_TC_BANK_RANK_B_tWRWR_dr_DEF (0x00000005) + #define MCSCHEDS_CR_TC_BANK_RANK_B_tWRWR_dd_OFF (21) + #define MCSCHEDS_CR_TC_BANK_RANK_B_tWRWR_dd_WID ( 4) + #define MCSCHEDS_CR_TC_BANK_RANK_B_tWRWR_dd_MSK (0x01E00000) + #define MCSCHEDS_CR_TC_BANK_RANK_B_tWRWR_dd_MAX (0x0000000F) + #define MCSCHEDS_CR_TC_BANK_RANK_B_tWRWR_dd_DEF (0x00000005) + #define MCSCHEDS_CR_TC_BANK_RANK_B_tWRPDEN_OFF (25) + #define MCSCHEDS_CR_TC_BANK_RANK_B_tWRPDEN_WID ( 6) + #define MCSCHEDS_CR_TC_BANK_RANK_B_tWRPDEN_MSK (0x7E000000) + #define MCSCHEDS_CR_TC_BANK_RANK_B_tWRPDEN_MAX (0x0000003F) + #define MCSCHEDS_CR_TC_BANK_RANK_B_tWRPDEN_DEF (0x00000005) + #define MCSCHEDS_CR_TC_BANK_RANK_B_Dec_WRD_OFF (31) + #define MCSCHEDS_CR_TC_BANK_RANK_B_Dec_WRD_WID ( 1) + #define MCSCHEDS_CR_TC_BANK_RANK_B_Dec_WRD_MSK (0x80000000) + #define MCSCHEDS_CR_TC_BANK_RANK_B_Dec_WRD_MAX (0x00000001) + #define MCSCHEDS_CR_TC_BANK_RANK_B_Dec_WRD_DEF (0x00000000) + +#define MCSCHEDS_CR_TC_BANK_RANK_C_REG (0x00004C0C) + #define MCSCHEDS_CR_TC_BANK_RANK_C_tXPDLL_OFF ( 0) + #define MCSCHEDS_CR_TC_BANK_RANK_C_tXPDLL_WID ( 6) + #define MCSCHEDS_CR_TC_BANK_RANK_C_tXPDLL_MSK (0x0000003F) + #define MCSCHEDS_CR_TC_BANK_RANK_C_tXPDLL_MAX (0x0000003F) + #define MCSCHEDS_CR_TC_BANK_RANK_C_tXPDLL_DEF (0x0000000A) + #define MCSCHEDS_CR_TC_BANK_RANK_C_tXP_OFF ( 6) + #define MCSCHEDS_CR_TC_BANK_RANK_C_tXP_WID ( 4) + #define MCSCHEDS_CR_TC_BANK_RANK_C_tXP_MSK (0x000003C0) + #define MCSCHEDS_CR_TC_BANK_RANK_C_tXP_MAX (0x0000000F) + #define MCSCHEDS_CR_TC_BANK_RANK_C_tXP_DEF (0x00000003) + #define MCSCHEDS_CR_TC_BANK_RANK_C_TAONPD_OFF (10) + #define MCSCHEDS_CR_TC_BANK_RANK_C_TAONPD_WID ( 4) + #define MCSCHEDS_CR_TC_BANK_RANK_C_TAONPD_MSK (0x00003C00) + #define MCSCHEDS_CR_TC_BANK_RANK_C_TAONPD_MAX (0x0000000F) + #define MCSCHEDS_CR_TC_BANK_RANK_C_TAONPD_DEF (0x00000009) + #define MCSCHEDS_CR_TC_BANK_RANK_C_tRDWR_OFF (14) + #define MCSCHEDS_CR_TC_BANK_RANK_C_tRDWR_WID ( 5) + #define MCSCHEDS_CR_TC_BANK_RANK_C_tRDWR_MSK (0x0007C000) + #define MCSCHEDS_CR_TC_BANK_RANK_C_tRDWR_MAX (0x0000001F) + #define MCSCHEDS_CR_TC_BANK_RANK_C_tRDWR_DEF (0x00000005) + #define MCSCHEDS_CR_TC_BANK_RANK_C_tRDWR_dr_OFF (19) + #define MCSCHEDS_CR_TC_BANK_RANK_C_tRDWR_dr_WID ( 5) + #define MCSCHEDS_CR_TC_BANK_RANK_C_tRDWR_dr_MSK (0x00F80000) + #define MCSCHEDS_CR_TC_BANK_RANK_C_tRDWR_dr_MAX (0x0000001F) + #define MCSCHEDS_CR_TC_BANK_RANK_C_tRDWR_dr_DEF (0x00000005) + #define MCSCHEDS_CR_TC_BANK_RANK_C_tRDWR_dd_OFF (24) + #define MCSCHEDS_CR_TC_BANK_RANK_C_tRDWR_dd_WID ( 5) + #define MCSCHEDS_CR_TC_BANK_RANK_C_tRDWR_dd_MSK (0x1F000000) + #define MCSCHEDS_CR_TC_BANK_RANK_C_tRDWR_dd_MAX (0x0000001F) + #define MCSCHEDS_CR_TC_BANK_RANK_C_tRDWR_dd_DEF (0x00000005) + +#define MCSCHEDS_CR_CMD_RATE_REG (0x00004C10) + #define MCSCHEDS_CR_CMD_RATE_enable_cmd_rate_limit_OFF ( 0) + #define MCSCHEDS_CR_CMD_RATE_enable_cmd_rate_limit_WID ( 1) + #define MCSCHEDS_CR_CMD_RATE_enable_cmd_rate_limit_MSK (0x00000001) + #define MCSCHEDS_CR_CMD_RATE_enable_cmd_rate_limit_MAX (0x00000001) + #define MCSCHEDS_CR_CMD_RATE_enable_cmd_rate_limit_DEF (0x00000000) + #define MCSCHEDS_CR_CMD_RATE_cmd_rate_limit_OFF ( 1) + #define MCSCHEDS_CR_CMD_RATE_cmd_rate_limit_WID ( 3) + #define MCSCHEDS_CR_CMD_RATE_cmd_rate_limit_MSK (0x0000000E) + #define MCSCHEDS_CR_CMD_RATE_cmd_rate_limit_MAX (0x00000007) + #define MCSCHEDS_CR_CMD_RATE_cmd_rate_limit_DEF (0x00000004) + #define MCSCHEDS_CR_CMD_RATE_reset_on_command_OFF ( 4) + #define MCSCHEDS_CR_CMD_RATE_reset_on_command_WID ( 4) + #define MCSCHEDS_CR_CMD_RATE_reset_on_command_MSK (0x000000F0) + #define MCSCHEDS_CR_CMD_RATE_reset_on_command_MAX (0x0000000F) + #define MCSCHEDS_CR_CMD_RATE_reset_on_command_DEF (0x00000000) + #define MCSCHEDS_CR_CMD_RATE_reset_delay_OFF ( 8) + #define MCSCHEDS_CR_CMD_RATE_reset_delay_WID ( 4) + #define MCSCHEDS_CR_CMD_RATE_reset_delay_MSK (0x00000F00) + #define MCSCHEDS_CR_CMD_RATE_reset_delay_MAX (0x0000000F) + #define MCSCHEDS_CR_CMD_RATE_reset_delay_DEF (0x00000000) + #define MCSCHEDS_CR_CMD_RATE_ck_to_cke_delay_OFF (12) + #define MCSCHEDS_CR_CMD_RATE_ck_to_cke_delay_WID ( 2) + #define MCSCHEDS_CR_CMD_RATE_ck_to_cke_delay_MSK (0x00003000) + #define MCSCHEDS_CR_CMD_RATE_ck_to_cke_delay_MAX (0x00000003) + #define MCSCHEDS_CR_CMD_RATE_ck_to_cke_delay_DEF (0x00000001) + #define MCSCHEDS_CR_CMD_RATE_spare_OFF (14) + #define MCSCHEDS_CR_CMD_RATE_spare_WID (17) + #define MCSCHEDS_CR_CMD_RATE_spare_MSK (0x7FFFC000) + #define MCSCHEDS_CR_CMD_RATE_spare_MAX (0x0001FFFF) + #define MCSCHEDS_CR_CMD_RATE_spare_DEF (0x00000000) + #define MCSCHEDS_CR_CMD_RATE_init_mrw_2n_cs_OFF (31) + #define MCSCHEDS_CR_CMD_RATE_init_mrw_2n_cs_WID ( 1) + #define MCSCHEDS_CR_CMD_RATE_init_mrw_2n_cs_MSK (0x80000000) + #define MCSCHEDS_CR_CMD_RATE_init_mrw_2n_cs_MAX (0x00000001) + #define MCSCHEDS_CR_CMD_RATE_init_mrw_2n_cs_DEF (0x00000000) + +#define MCSCHEDS_CR_TC_BANK_RANK_D_REG (0x00004C14) + #define MCSCHEDS_CR_TC_BANK_RANK_D_tCL_OFF ( 0) + #define MCSCHEDS_CR_TC_BANK_RANK_D_tCL_WID ( 5) + #define MCSCHEDS_CR_TC_BANK_RANK_D_tCL_MSK (0x0000001F) + #define MCSCHEDS_CR_TC_BANK_RANK_D_tCL_MAX (0x0000001F) + #define MCSCHEDS_CR_TC_BANK_RANK_D_tCL_DEF (0x00000006) + #define MCSCHEDS_CR_TC_BANK_RANK_D_tWCL_OFF ( 5) + #define MCSCHEDS_CR_TC_BANK_RANK_D_tWCL_WID ( 5) + #define MCSCHEDS_CR_TC_BANK_RANK_D_tWCL_MSK (0x000003E0) + #define MCSCHEDS_CR_TC_BANK_RANK_D_tWCL_MAX (0x0000001F) + #define MCSCHEDS_CR_TC_BANK_RANK_D_tWCL_DEF (0x00000006) + #define MCSCHEDS_CR_TC_BANK_RANK_D_tCPDED_OFF (10) + #define MCSCHEDS_CR_TC_BANK_RANK_D_tCPDED_WID ( 2) + #define MCSCHEDS_CR_TC_BANK_RANK_D_tCPDED_MSK (0x00000C00) + #define MCSCHEDS_CR_TC_BANK_RANK_D_tCPDED_MAX (0x00000003) + #define MCSCHEDS_CR_TC_BANK_RANK_D_tCPDED_DEF (0x00000001) + #define MCSCHEDS_CR_TC_BANK_RANK_D_tPRPDEN_OFF (12) + #define MCSCHEDS_CR_TC_BANK_RANK_D_tPRPDEN_WID ( 2) + #define MCSCHEDS_CR_TC_BANK_RANK_D_tPRPDEN_MSK (0x00003000) + #define MCSCHEDS_CR_TC_BANK_RANK_D_tPRPDEN_MAX (0x00000003) + #define MCSCHEDS_CR_TC_BANK_RANK_D_tPRPDEN_DEF (0x00000001) + #define MCSCHEDS_CR_TC_BANK_RANK_D_Odt_Read_Delay_OFF (14) + #define MCSCHEDS_CR_TC_BANK_RANK_D_Odt_Read_Delay_WID ( 3) + #define MCSCHEDS_CR_TC_BANK_RANK_D_Odt_Read_Delay_MSK (0x0001C000) + #define MCSCHEDS_CR_TC_BANK_RANK_D_Odt_Read_Delay_MAX (0x00000007) + #define MCSCHEDS_CR_TC_BANK_RANK_D_Odt_Read_Delay_DEF (0x00000000) + #define MCSCHEDS_CR_TC_BANK_RANK_D_Odt_Read_Duration_OFF (17) + #define MCSCHEDS_CR_TC_BANK_RANK_D_Odt_Read_Duration_WID ( 2) + #define MCSCHEDS_CR_TC_BANK_RANK_D_Odt_Read_Duration_MSK (0x00060000) + #define MCSCHEDS_CR_TC_BANK_RANK_D_Odt_Read_Duration_MAX (0x00000003) + #define MCSCHEDS_CR_TC_BANK_RANK_D_Odt_Read_Duration_DEF (0x00000000) + #define MCSCHEDS_CR_TC_BANK_RANK_D_Odt_Write_Duration_OFF (19) + #define MCSCHEDS_CR_TC_BANK_RANK_D_Odt_Write_Duration_WID ( 2) + #define MCSCHEDS_CR_TC_BANK_RANK_D_Odt_Write_Duration_MSK (0x00180000) + #define MCSCHEDS_CR_TC_BANK_RANK_D_Odt_Write_Duration_MAX (0x00000003) + #define MCSCHEDS_CR_TC_BANK_RANK_D_Odt_Write_Duration_DEF (0x00000000) + #define MCSCHEDS_CR_TC_BANK_RANK_D_Odt_Write_Duration_Ult_OFF (19) + #define MCSCHEDS_CR_TC_BANK_RANK_D_Odt_Write_Duration_Ult_WID ( 3) + #define MCSCHEDS_CR_TC_BANK_RANK_D_Odt_Write_Duration_Ult_MSK (0x00380000) + #define MCSCHEDS_CR_TC_BANK_RANK_D_Odt_Write_Duration_Ult_MAX (0x00000007) + #define MCSCHEDS_CR_TC_BANK_RANK_D_Odt_Write_Duration_Ult_DEF (0x00000000) + #define MCSCHEDS_CR_TC_BANK_RANK_D_Odt_Write_Delay_Ult_OFF (22) + #define MCSCHEDS_CR_TC_BANK_RANK_D_Odt_Write_Delay_Ult_WID ( 3) + #define MCSCHEDS_CR_TC_BANK_RANK_D_Odt_Write_Delay_Ult_MSK (0x01C00000) + #define MCSCHEDS_CR_TC_BANK_RANK_D_Odt_Write_Delay_Ult_MAX (0x00000007) + #define MCSCHEDS_CR_TC_BANK_RANK_D_Odt_Write_Delay_Ult_DEF (0x00000000) + #define MCSCHEDS_CR_TC_BANK_RANK_D_Odt_Always_Rank0_Ult_OFF (25) + #define MCSCHEDS_CR_TC_BANK_RANK_D_Odt_Always_Rank0_Ult_WID ( 1) + #define MCSCHEDS_CR_TC_BANK_RANK_D_Odt_Always_Rank0_Ult_MSK (0x02000000) + #define MCSCHEDS_CR_TC_BANK_RANK_D_Odt_Always_Rank0_Ult_MAX (0x00000001) + #define MCSCHEDS_CR_TC_BANK_RANK_D_Odt_Always_Rank0_Ult_DEF (0x00000000) + #define MCSCHEDS_CR_TC_BANK_RANK_D_cmd_delay_Ult_OFF (26) + #define MCSCHEDS_CR_TC_BANK_RANK_D_cmd_delay_Ult_WID ( 2) + #define MCSCHEDS_CR_TC_BANK_RANK_D_cmd_delay_Ult_MSK (0x0C000000) + #define MCSCHEDS_CR_TC_BANK_RANK_D_cmd_delay_Ult_MAX (0x00000003) + #define MCSCHEDS_CR_TC_BANK_RANK_D_cmd_delay_Ult_DEF (0x00000000) + +#define MCSCHEDS_CR_SCHED_CBIT_REG (0x00004C20) + #define MCSCHEDS_CR_SCHED_CBIT_dis_opp_cas_OFF ( 0) + #define MCSCHEDS_CR_SCHED_CBIT_dis_opp_cas_WID ( 1) + #define MCSCHEDS_CR_SCHED_CBIT_dis_opp_cas_MSK (0x00000001) + #define MCSCHEDS_CR_SCHED_CBIT_dis_opp_cas_MAX (0x00000001) + #define MCSCHEDS_CR_SCHED_CBIT_dis_opp_cas_DEF (0x00000001) + #define MCSCHEDS_CR_SCHED_CBIT_dis_opp_is_cas_OFF ( 1) + #define MCSCHEDS_CR_SCHED_CBIT_dis_opp_is_cas_WID ( 1) + #define MCSCHEDS_CR_SCHED_CBIT_dis_opp_is_cas_MSK (0x00000002) + #define MCSCHEDS_CR_SCHED_CBIT_dis_opp_is_cas_MAX (0x00000001) + #define MCSCHEDS_CR_SCHED_CBIT_dis_opp_is_cas_DEF (0x00000000) + #define MCSCHEDS_CR_SCHED_CBIT_dis_opp_ras_OFF ( 2) + #define MCSCHEDS_CR_SCHED_CBIT_dis_opp_ras_WID ( 1) + #define MCSCHEDS_CR_SCHED_CBIT_dis_opp_ras_MSK (0x00000004) + #define MCSCHEDS_CR_SCHED_CBIT_dis_opp_ras_MAX (0x00000001) + #define MCSCHEDS_CR_SCHED_CBIT_dis_opp_ras_DEF (0x00000001) + #define MCSCHEDS_CR_SCHED_CBIT_dis_opp_is_ras_OFF ( 3) + #define MCSCHEDS_CR_SCHED_CBIT_dis_opp_is_ras_WID ( 1) + #define MCSCHEDS_CR_SCHED_CBIT_dis_opp_is_ras_MSK (0x00000008) + #define MCSCHEDS_CR_SCHED_CBIT_dis_opp_is_ras_MAX (0x00000001) + #define MCSCHEDS_CR_SCHED_CBIT_dis_opp_is_ras_DEF (0x00000000) + #define MCSCHEDS_CR_SCHED_CBIT_dis_1c_byp_OFF ( 4) + #define MCSCHEDS_CR_SCHED_CBIT_dis_1c_byp_WID ( 1) + #define MCSCHEDS_CR_SCHED_CBIT_dis_1c_byp_MSK (0x00000010) + #define MCSCHEDS_CR_SCHED_CBIT_dis_1c_byp_MAX (0x00000001) + #define MCSCHEDS_CR_SCHED_CBIT_dis_1c_byp_DEF (0x00000001) + #define MCSCHEDS_CR_SCHED_CBIT_dis_2c_byp_OFF ( 5) + #define MCSCHEDS_CR_SCHED_CBIT_dis_2c_byp_WID ( 1) + #define MCSCHEDS_CR_SCHED_CBIT_dis_2c_byp_MSK (0x00000020) + #define MCSCHEDS_CR_SCHED_CBIT_dis_2c_byp_MAX (0x00000001) + #define MCSCHEDS_CR_SCHED_CBIT_dis_2c_byp_DEF (0x00000000) + #define MCSCHEDS_CR_SCHED_CBIT_dis_deprd_opt_OFF ( 6) + #define MCSCHEDS_CR_SCHED_CBIT_dis_deprd_opt_WID ( 1) + #define MCSCHEDS_CR_SCHED_CBIT_dis_deprd_opt_MSK (0x00000040) + #define MCSCHEDS_CR_SCHED_CBIT_dis_deprd_opt_MAX (0x00000001) + #define MCSCHEDS_CR_SCHED_CBIT_dis_deprd_opt_DEF (0x00000000) + #define MCSCHEDS_CR_SCHED_CBIT_dis_pt_it_OFF ( 7) + #define MCSCHEDS_CR_SCHED_CBIT_dis_pt_it_WID ( 1) + #define MCSCHEDS_CR_SCHED_CBIT_dis_pt_it_MSK (0x00000080) + #define MCSCHEDS_CR_SCHED_CBIT_dis_pt_it_MAX (0x00000001) + #define MCSCHEDS_CR_SCHED_CBIT_dis_pt_it_DEF (0x00000000) + #define MCSCHEDS_CR_SCHED_CBIT_dis_prcnt_ring_OFF ( 8) + #define MCSCHEDS_CR_SCHED_CBIT_dis_prcnt_ring_WID ( 1) + #define MCSCHEDS_CR_SCHED_CBIT_dis_prcnt_ring_MSK (0x00000100) + #define MCSCHEDS_CR_SCHED_CBIT_dis_prcnt_ring_MAX (0x00000001) + #define MCSCHEDS_CR_SCHED_CBIT_dis_prcnt_ring_DEF (0x00000000) + #define MCSCHEDS_CR_SCHED_CBIT_dis_prcnt_sa_OFF ( 9) + #define MCSCHEDS_CR_SCHED_CBIT_dis_prcnt_sa_WID ( 1) + #define MCSCHEDS_CR_SCHED_CBIT_dis_prcnt_sa_MSK (0x00000200) + #define MCSCHEDS_CR_SCHED_CBIT_dis_prcnt_sa_MAX (0x00000001) + #define MCSCHEDS_CR_SCHED_CBIT_dis_prcnt_sa_DEF (0x00000000) + #define MCSCHEDS_CR_SCHED_CBIT_dis_blkr_ph_OFF (10) + #define MCSCHEDS_CR_SCHED_CBIT_dis_blkr_ph_WID ( 1) + #define MCSCHEDS_CR_SCHED_CBIT_dis_blkr_ph_MSK (0x00000400) + #define MCSCHEDS_CR_SCHED_CBIT_dis_blkr_ph_MAX (0x00000001) + #define MCSCHEDS_CR_SCHED_CBIT_dis_blkr_ph_DEF (0x00000000) + #define MCSCHEDS_CR_SCHED_CBIT_dis_blkr_pe_OFF (11) + #define MCSCHEDS_CR_SCHED_CBIT_dis_blkr_pe_WID ( 1) + #define MCSCHEDS_CR_SCHED_CBIT_dis_blkr_pe_MSK (0x00000800) + #define MCSCHEDS_CR_SCHED_CBIT_dis_blkr_pe_MAX (0x00000001) + #define MCSCHEDS_CR_SCHED_CBIT_dis_blkr_pe_DEF (0x00000000) + #define MCSCHEDS_CR_SCHED_CBIT_dis_blkr_pm_OFF (12) + #define MCSCHEDS_CR_SCHED_CBIT_dis_blkr_pm_WID ( 1) + #define MCSCHEDS_CR_SCHED_CBIT_dis_blkr_pm_MSK (0x00001000) + #define MCSCHEDS_CR_SCHED_CBIT_dis_blkr_pm_MAX (0x00000001) + #define MCSCHEDS_CR_SCHED_CBIT_dis_blkr_pm_DEF (0x00000000) + #define MCSCHEDS_CR_SCHED_CBIT_dis_odt_OFF (13) + #define MCSCHEDS_CR_SCHED_CBIT_dis_odt_WID ( 1) + #define MCSCHEDS_CR_SCHED_CBIT_dis_odt_MSK (0x00002000) + #define MCSCHEDS_CR_SCHED_CBIT_dis_odt_MAX (0x00000001) + #define MCSCHEDS_CR_SCHED_CBIT_dis_odt_DEF (0x00000000) + #define MCSCHEDS_CR_SCHED_CBIT_OE_alw_off_OFF (14) + #define MCSCHEDS_CR_SCHED_CBIT_OE_alw_off_WID ( 1) + #define MCSCHEDS_CR_SCHED_CBIT_OE_alw_off_MSK (0x00004000) + #define MCSCHEDS_CR_SCHED_CBIT_OE_alw_off_MAX (0x00000001) + #define MCSCHEDS_CR_SCHED_CBIT_OE_alw_off_DEF (0x00000000) + #define MCSCHEDS_CR_SCHED_CBIT_dis_aom_OFF (16) + #define MCSCHEDS_CR_SCHED_CBIT_dis_aom_WID ( 1) + #define MCSCHEDS_CR_SCHED_CBIT_dis_aom_MSK (0x00010000) + #define MCSCHEDS_CR_SCHED_CBIT_dis_aom_MAX (0x00000001) + #define MCSCHEDS_CR_SCHED_CBIT_dis_aom_DEF (0x00000000) + #define MCSCHEDS_CR_SCHED_CBIT_block_rpq_OFF (17) + #define MCSCHEDS_CR_SCHED_CBIT_block_rpq_WID ( 1) + #define MCSCHEDS_CR_SCHED_CBIT_block_rpq_MSK (0x00020000) + #define MCSCHEDS_CR_SCHED_CBIT_block_rpq_MAX (0x00000001) + #define MCSCHEDS_CR_SCHED_CBIT_block_rpq_DEF (0x00000000) + #define MCSCHEDS_CR_SCHED_CBIT_block_wpq_OFF (18) + #define MCSCHEDS_CR_SCHED_CBIT_block_wpq_WID ( 1) + #define MCSCHEDS_CR_SCHED_CBIT_block_wpq_MSK (0x00040000) + #define MCSCHEDS_CR_SCHED_CBIT_block_wpq_MAX (0x00000001) + #define MCSCHEDS_CR_SCHED_CBIT_block_wpq_DEF (0x00000000) + #define MCSCHEDS_CR_SCHED_CBIT_invert_align_OFF (19) + #define MCSCHEDS_CR_SCHED_CBIT_invert_align_WID ( 1) + #define MCSCHEDS_CR_SCHED_CBIT_invert_align_MSK (0x00080000) + #define MCSCHEDS_CR_SCHED_CBIT_invert_align_MAX (0x00000001) + #define MCSCHEDS_CR_SCHED_CBIT_invert_align_DEF (0x00000000) + #define MCSCHEDS_CR_SCHED_CBIT_dis_write_gap_OFF (20) + #define MCSCHEDS_CR_SCHED_CBIT_dis_write_gap_WID ( 1) + #define MCSCHEDS_CR_SCHED_CBIT_dis_write_gap_MSK (0x00100000) + #define MCSCHEDS_CR_SCHED_CBIT_dis_write_gap_MAX (0x00000001) + #define MCSCHEDS_CR_SCHED_CBIT_dis_write_gap_DEF (0x00000001) + #define MCSCHEDS_CR_SCHED_CBIT_dis_zq_OFF (21) + #define MCSCHEDS_CR_SCHED_CBIT_dis_zq_WID ( 1) + #define MCSCHEDS_CR_SCHED_CBIT_dis_zq_MSK (0x00200000) + #define MCSCHEDS_CR_SCHED_CBIT_dis_zq_MAX (0x00000001) + #define MCSCHEDS_CR_SCHED_CBIT_dis_zq_DEF (0x00000000) + #define MCSCHEDS_CR_SCHED_CBIT_dis_tt_OFF (22) + #define MCSCHEDS_CR_SCHED_CBIT_dis_tt_WID ( 1) + #define MCSCHEDS_CR_SCHED_CBIT_dis_tt_MSK (0x00400000) + #define MCSCHEDS_CR_SCHED_CBIT_dis_tt_MAX (0x00000001) + #define MCSCHEDS_CR_SCHED_CBIT_dis_tt_DEF (0x00000000) + #define MCSCHEDS_CR_SCHED_CBIT_dis_opp_ref_OFF (23) + #define MCSCHEDS_CR_SCHED_CBIT_dis_opp_ref_WID ( 1) + #define MCSCHEDS_CR_SCHED_CBIT_dis_opp_ref_MSK (0x00800000) + #define MCSCHEDS_CR_SCHED_CBIT_dis_opp_ref_MAX (0x00000001) + #define MCSCHEDS_CR_SCHED_CBIT_dis_opp_ref_DEF (0x00000000) + #define MCSCHEDS_CR_SCHED_CBIT_Long_ZQ_OFF (24) + #define MCSCHEDS_CR_SCHED_CBIT_Long_ZQ_WID ( 1) + #define MCSCHEDS_CR_SCHED_CBIT_Long_ZQ_MSK (0x01000000) + #define MCSCHEDS_CR_SCHED_CBIT_Long_ZQ_MAX (0x00000001) + #define MCSCHEDS_CR_SCHED_CBIT_Long_ZQ_DEF (0x00000000) + #define MCSCHEDS_CR_SCHED_CBIT_dis_srx_zq_OFF (25) + #define MCSCHEDS_CR_SCHED_CBIT_dis_srx_zq_WID ( 1) + #define MCSCHEDS_CR_SCHED_CBIT_dis_srx_zq_MSK (0x02000000) + #define MCSCHEDS_CR_SCHED_CBIT_dis_srx_zq_MAX (0x00000001) + #define MCSCHEDS_CR_SCHED_CBIT_dis_srx_zq_DEF (0x00000000) + #define MCSCHEDS_CR_SCHED_CBIT_Serialize_ZQ_OFF (26) + #define MCSCHEDS_CR_SCHED_CBIT_Serialize_ZQ_WID ( 1) + #define MCSCHEDS_CR_SCHED_CBIT_Serialize_ZQ_MSK (0x04000000) + #define MCSCHEDS_CR_SCHED_CBIT_Serialize_ZQ_MAX (0x00000001) + #define MCSCHEDS_CR_SCHED_CBIT_Serialize_ZQ_DEF (0x00000000) + #define MCSCHEDS_CR_SCHED_CBIT_ZQ_fast_exec_OFF (27) + #define MCSCHEDS_CR_SCHED_CBIT_ZQ_fast_exec_WID ( 1) + #define MCSCHEDS_CR_SCHED_CBIT_ZQ_fast_exec_MSK (0x08000000) + #define MCSCHEDS_CR_SCHED_CBIT_ZQ_fast_exec_MAX (0x00000001) + #define MCSCHEDS_CR_SCHED_CBIT_ZQ_fast_exec_DEF (0x00000000) + #define MCSCHEDS_CR_SCHED_CBIT_Dis_DriveNop_OFF (28) + #define MCSCHEDS_CR_SCHED_CBIT_Dis_DriveNop_WID ( 1) + #define MCSCHEDS_CR_SCHED_CBIT_Dis_DriveNop_MSK (0x10000000) + #define MCSCHEDS_CR_SCHED_CBIT_Dis_DriveNop_MAX (0x00000001) + #define MCSCHEDS_CR_SCHED_CBIT_Dis_DriveNop_DEF (0x00000000) + #define MCSCHEDS_CR_SCHED_CBIT_Pres_WDB_Ent_OFF (29) + #define MCSCHEDS_CR_SCHED_CBIT_Pres_WDB_Ent_WID ( 1) + #define MCSCHEDS_CR_SCHED_CBIT_Pres_WDB_Ent_MSK (0x20000000) + #define MCSCHEDS_CR_SCHED_CBIT_Pres_WDB_Ent_MAX (0x00000001) + #define MCSCHEDS_CR_SCHED_CBIT_Pres_WDB_Ent_DEF (0x00000000) + #define MCSCHEDS_CR_SCHED_CBIT_dis_clk_gate_OFF (30) + #define MCSCHEDS_CR_SCHED_CBIT_dis_clk_gate_WID ( 1) + #define MCSCHEDS_CR_SCHED_CBIT_dis_clk_gate_MSK (0x40000000) + #define MCSCHEDS_CR_SCHED_CBIT_dis_clk_gate_MAX (0x00000001) + #define MCSCHEDS_CR_SCHED_CBIT_dis_clk_gate_DEF (0x00000000) + +#define MCSCHEDS_CR_SC_ROUNDT_LAT_REG (0x00004C24) + #define MCSCHEDS_CR_SC_ROUNDT_LAT_Lat_R0D0_OFF ( 0) + #define MCSCHEDS_CR_SC_ROUNDT_LAT_Lat_R0D0_WID ( 6) + #define MCSCHEDS_CR_SC_ROUNDT_LAT_Lat_R0D0_MSK (0x0000003F) + #define MCSCHEDS_CR_SC_ROUNDT_LAT_Lat_R0D0_MAX (0x0000003F) + #define MCSCHEDS_CR_SC_ROUNDT_LAT_Lat_R0D0_DEF (0x00000020) + #define MCSCHEDS_CR_SC_ROUNDT_LAT_Lat_R1D0_OFF ( 8) + #define MCSCHEDS_CR_SC_ROUNDT_LAT_Lat_R1D0_WID ( 6) + #define MCSCHEDS_CR_SC_ROUNDT_LAT_Lat_R1D0_MSK (0x00003F00) + #define MCSCHEDS_CR_SC_ROUNDT_LAT_Lat_R1D0_MAX (0x0000003F) + #define MCSCHEDS_CR_SC_ROUNDT_LAT_Lat_R1D0_DEF (0x00000020) + #define MCSCHEDS_CR_SC_ROUNDT_LAT_Lat_R0D1_OFF (16) + #define MCSCHEDS_CR_SC_ROUNDT_LAT_Lat_R0D1_WID ( 6) + #define MCSCHEDS_CR_SC_ROUNDT_LAT_Lat_R0D1_MSK (0x003F0000) + #define MCSCHEDS_CR_SC_ROUNDT_LAT_Lat_R0D1_MAX (0x0000003F) + #define MCSCHEDS_CR_SC_ROUNDT_LAT_Lat_R0D1_DEF (0x00000020) + #define MCSCHEDS_CR_SC_ROUNDT_LAT_Lat_R1D1_OFF (24) + #define MCSCHEDS_CR_SC_ROUNDT_LAT_Lat_R1D1_WID ( 6) + #define MCSCHEDS_CR_SC_ROUNDT_LAT_Lat_R1D1_MSK (0x3F000000) + #define MCSCHEDS_CR_SC_ROUNDT_LAT_Lat_R1D1_MAX (0x0000003F) + #define MCSCHEDS_CR_SC_ROUNDT_LAT_Lat_R1D1_DEF (0x00000020) + +#define MCSCHEDS_CR_SC_IO_LATENCY_REG (0x00004C28) + #define MCSCHEDS_CR_SC_IO_LATENCY_IOLAT_R0D0_OFF ( 0) + #define MCSCHEDS_CR_SC_IO_LATENCY_IOLAT_R0D0_WID ( 4) + #define MCSCHEDS_CR_SC_IO_LATENCY_IOLAT_R0D0_MSK (0x0000000F) + #define MCSCHEDS_CR_SC_IO_LATENCY_IOLAT_R0D0_MAX (0x0000000F) + #define MCSCHEDS_CR_SC_IO_LATENCY_IOLAT_R0D0_DEF (0x00000000) + #define MCSCHEDS_CR_SC_IO_LATENCY_IOLAT_R1D0_OFF ( 4) + #define MCSCHEDS_CR_SC_IO_LATENCY_IOLAT_R1D0_WID ( 4) + #define MCSCHEDS_CR_SC_IO_LATENCY_IOLAT_R1D0_MSK (0x000000F0) + #define MCSCHEDS_CR_SC_IO_LATENCY_IOLAT_R1D0_MAX (0x0000000F) + #define MCSCHEDS_CR_SC_IO_LATENCY_IOLAT_R1D0_DEF (0x00000000) + #define MCSCHEDS_CR_SC_IO_LATENCY_IOLAT_R0D1_OFF ( 8) + #define MCSCHEDS_CR_SC_IO_LATENCY_IOLAT_R0D1_WID ( 4) + #define MCSCHEDS_CR_SC_IO_LATENCY_IOLAT_R0D1_MSK (0x00000F00) + #define MCSCHEDS_CR_SC_IO_LATENCY_IOLAT_R0D1_MAX (0x0000000F) + #define MCSCHEDS_CR_SC_IO_LATENCY_IOLAT_R0D1_DEF (0x00000000) + #define MCSCHEDS_CR_SC_IO_LATENCY_IOLAT_R1D1_OFF (12) + #define MCSCHEDS_CR_SC_IO_LATENCY_IOLAT_R1D1_WID ( 4) + #define MCSCHEDS_CR_SC_IO_LATENCY_IOLAT_R1D1_MSK (0x0000F000) + #define MCSCHEDS_CR_SC_IO_LATENCY_IOLAT_R1D1_MAX (0x0000000F) + #define MCSCHEDS_CR_SC_IO_LATENCY_IOLAT_R1D1_DEF (0x00000000) + #define MCSCHEDS_CR_SC_IO_LATENCY_RT_IOCOMP_OFF (16) + #define MCSCHEDS_CR_SC_IO_LATENCY_RT_IOCOMP_WID ( 6) + #define MCSCHEDS_CR_SC_IO_LATENCY_RT_IOCOMP_MSK (0x003F0000) + #define MCSCHEDS_CR_SC_IO_LATENCY_RT_IOCOMP_MAX (0x0000003F) + #define MCSCHEDS_CR_SC_IO_LATENCY_RT_IOCOMP_DEF (0x0000000E) + #define MCSCHEDS_CR_SC_IO_LATENCY_three_channels_OFF (30) + #define MCSCHEDS_CR_SC_IO_LATENCY_three_channels_WID ( 1) + #define MCSCHEDS_CR_SC_IO_LATENCY_three_channels_MSK (0x40000000) + #define MCSCHEDS_CR_SC_IO_LATENCY_three_channels_MAX (0x00000001) + #define MCSCHEDS_CR_SC_IO_LATENCY_three_channels_DEF (0x00000000) + #define MCSCHEDS_CR_SC_IO_LATENCY_DIS_RT_CLK_GATE_OFF (31) + #define MCSCHEDS_CR_SC_IO_LATENCY_DIS_RT_CLK_GATE_WID ( 1) + #define MCSCHEDS_CR_SC_IO_LATENCY_DIS_RT_CLK_GATE_MSK (0x80000000) + #define MCSCHEDS_CR_SC_IO_LATENCY_DIS_RT_CLK_GATE_MAX (0x00000001) + #define MCSCHEDS_CR_SC_IO_LATENCY_DIS_RT_CLK_GATE_DEF (0x00000000) + +#define MCSCHEDS_CR_ROUND_TRIP_DFT_DATA_REG (0x00004C2C) + #define MCSCHEDS_CR_ROUND_TRIP_DFT_DATA_DATA_OFF ( 0) + #define MCSCHEDS_CR_ROUND_TRIP_DFT_DATA_DATA_WID (32) + #define MCSCHEDS_CR_ROUND_TRIP_DFT_DATA_DATA_MSK (0xFFFFFFFF) + #define MCSCHEDS_CR_ROUND_TRIP_DFT_DATA_DATA_MAX (0xFFFFFFFF) + #define MCSCHEDS_CR_ROUND_TRIP_DFT_DATA_DATA_DEF (0x00000000) + +#define MCSCHEDS_CR_DFT_MISC_REG (0x00004C30) + #define MCSCHEDS_CR_DFT_MISC_WDAR_OFF ( 0) + #define MCSCHEDS_CR_DFT_MISC_WDAR_WID ( 1) + #define MCSCHEDS_CR_DFT_MISC_WDAR_MSK (0x00000001) + #define MCSCHEDS_CR_DFT_MISC_WDAR_MAX (0x00000001) + #define MCSCHEDS_CR_DFT_MISC_WDAR_DEF (0x00000000) + #define MCSCHEDS_CR_DFT_MISC_safe_mask_sel_OFF ( 1) + #define MCSCHEDS_CR_DFT_MISC_safe_mask_sel_WID ( 3) + #define MCSCHEDS_CR_DFT_MISC_safe_mask_sel_MSK (0x0000000E) + #define MCSCHEDS_CR_DFT_MISC_safe_mask_sel_MAX (0x00000007) + #define MCSCHEDS_CR_DFT_MISC_safe_mask_sel_DEF (0x00000000) + #define MCSCHEDS_CR_DFT_MISC_force_rcv_en_OFF ( 4) + #define MCSCHEDS_CR_DFT_MISC_force_rcv_en_WID ( 1) + #define MCSCHEDS_CR_DFT_MISC_force_rcv_en_MSK (0x00000010) + #define MCSCHEDS_CR_DFT_MISC_force_rcv_en_MAX (0x00000001) + #define MCSCHEDS_CR_DFT_MISC_force_rcv_en_DEF (0x00000000) + #define MCSCHEDS_CR_DFT_MISC_DDR_QUAL_OFF ( 8) + #define MCSCHEDS_CR_DFT_MISC_DDR_QUAL_WID ( 2) + #define MCSCHEDS_CR_DFT_MISC_DDR_QUAL_MSK (0x00000300) + #define MCSCHEDS_CR_DFT_MISC_DDR_QUAL_MAX (0x00000003) + #define MCSCHEDS_CR_DFT_MISC_DDR_QUAL_DEF (0x00000000) + #define MCSCHEDS_CR_DFT_MISC_Qual_length_OFF (10) + #define MCSCHEDS_CR_DFT_MISC_Qual_length_WID ( 2) + #define MCSCHEDS_CR_DFT_MISC_Qual_length_MSK (0x00000C00) + #define MCSCHEDS_CR_DFT_MISC_Qual_length_MAX (0x00000003) + #define MCSCHEDS_CR_DFT_MISC_Qual_length_DEF (0x00000000) + #define MCSCHEDS_CR_DFT_MISC_WDB_Block_En_OFF (12) + #define MCSCHEDS_CR_DFT_MISC_WDB_Block_En_WID ( 1) + #define MCSCHEDS_CR_DFT_MISC_WDB_Block_En_MSK (0x00001000) + #define MCSCHEDS_CR_DFT_MISC_WDB_Block_En_MAX (0x00000001) + #define MCSCHEDS_CR_DFT_MISC_WDB_Block_En_DEF (0x00000000) + #define MCSCHEDS_CR_DFT_MISC_RT_DFT_READ_PTR_OFF (13) + #define MCSCHEDS_CR_DFT_MISC_RT_DFT_READ_PTR_WID ( 4) + #define MCSCHEDS_CR_DFT_MISC_RT_DFT_READ_PTR_MSK (0x0001E000) + #define MCSCHEDS_CR_DFT_MISC_RT_DFT_READ_PTR_MAX (0x0000000F) + #define MCSCHEDS_CR_DFT_MISC_RT_DFT_READ_PTR_DEF (0x00000000) + #define MCSCHEDS_CR_DFT_MISC_RT_DFT_READ_ENABLE_OFF (17) + #define MCSCHEDS_CR_DFT_MISC_RT_DFT_READ_ENABLE_WID ( 1) + #define MCSCHEDS_CR_DFT_MISC_RT_DFT_READ_ENABLE_MSK (0x00020000) + #define MCSCHEDS_CR_DFT_MISC_RT_DFT_READ_ENABLE_MAX (0x00000001) + #define MCSCHEDS_CR_DFT_MISC_RT_DFT_READ_ENABLE_DEF (0x00000000) + #define MCSCHEDS_CR_DFT_MISC_RT_DFT_READ_SEL_ADDR_OFF (18) + #define MCSCHEDS_CR_DFT_MISC_RT_DFT_READ_SEL_ADDR_WID ( 1) + #define MCSCHEDS_CR_DFT_MISC_RT_DFT_READ_SEL_ADDR_MSK (0x00040000) + #define MCSCHEDS_CR_DFT_MISC_RT_DFT_READ_SEL_ADDR_MAX (0x00000001) + #define MCSCHEDS_CR_DFT_MISC_RT_DFT_READ_SEL_ADDR_DEF (0x00000000) + +#define MCSCHEDS_CR_READ_RETURN_DFT_REG (0x00004C34) + #define MCSCHEDS_CR_READ_RETURN_DFT_ECC_OFF ( 0) + #define MCSCHEDS_CR_READ_RETURN_DFT_ECC_WID ( 8) + #define MCSCHEDS_CR_READ_RETURN_DFT_ECC_MSK (0x000000FF) + #define MCSCHEDS_CR_READ_RETURN_DFT_ECC_MAX (0x000000FF) + #define MCSCHEDS_CR_READ_RETURN_DFT_ECC_DEF (0x00000000) + #define MCSCHEDS_CR_READ_RETURN_DFT_RRD_DFT_Mode_OFF ( 8) + #define MCSCHEDS_CR_READ_RETURN_DFT_RRD_DFT_Mode_WID ( 2) + #define MCSCHEDS_CR_READ_RETURN_DFT_RRD_DFT_Mode_MSK (0x00000300) + #define MCSCHEDS_CR_READ_RETURN_DFT_RRD_DFT_Mode_MAX (0x00000003) + #define MCSCHEDS_CR_READ_RETURN_DFT_RRD_DFT_Mode_DEF (0x00000000) + #define MCSCHEDS_CR_READ_RETURN_DFT_LFSR_Seed_Index_OFF (10) + #define MCSCHEDS_CR_READ_RETURN_DFT_LFSR_Seed_Index_WID ( 5) + #define MCSCHEDS_CR_READ_RETURN_DFT_LFSR_Seed_Index_MSK (0x00007C00) + #define MCSCHEDS_CR_READ_RETURN_DFT_LFSR_Seed_Index_MAX (0x0000001F) + #define MCSCHEDS_CR_READ_RETURN_DFT_LFSR_Seed_Index_DEF (0x00000000) + #define MCSCHEDS_CR_READ_RETURN_DFT_Inversion_Mode_OFF (15) + #define MCSCHEDS_CR_READ_RETURN_DFT_Inversion_Mode_WID ( 1) + #define MCSCHEDS_CR_READ_RETURN_DFT_Inversion_Mode_MSK (0x00008000) + #define MCSCHEDS_CR_READ_RETURN_DFT_Inversion_Mode_MAX (0x00000001) + #define MCSCHEDS_CR_READ_RETURN_DFT_Inversion_Mode_DEF (0x00000000) + +#define MCSCHEDS_CR_SCHED_SECOND_CBIT_REG (0x00004C38) + #define MCSCHEDS_CR_SCHED_SECOND_CBIT_dis_imph_error_OFF ( 0) + #define MCSCHEDS_CR_SCHED_SECOND_CBIT_dis_imph_error_WID ( 1) + #define MCSCHEDS_CR_SCHED_SECOND_CBIT_dis_imph_error_MSK (0x00000001) + #define MCSCHEDS_CR_SCHED_SECOND_CBIT_dis_imph_error_MAX (0x00000001) + #define MCSCHEDS_CR_SCHED_SECOND_CBIT_dis_imph_error_DEF (0x00000000) + #define MCSCHEDS_CR_SCHED_SECOND_CBIT_dis_async_odt_OFF ( 8) + #define MCSCHEDS_CR_SCHED_SECOND_CBIT_dis_async_odt_WID ( 1) + #define MCSCHEDS_CR_SCHED_SECOND_CBIT_dis_async_odt_MSK (0x00000100) + #define MCSCHEDS_CR_SCHED_SECOND_CBIT_dis_async_odt_MAX (0x00000001) + #define MCSCHEDS_CR_SCHED_SECOND_CBIT_dis_async_odt_DEF (0x00000000) + +#define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_REG (0x00004C40) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux0_Control_OFF ( 0) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux0_Control_WID ( 2) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux0_Control_MSK (0x00000003) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux0_Control_MAX (0x00000003) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux0_Control_DEF (0x00000001) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux1_Control_OFF ( 3) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux1_Control_WID ( 2) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux1_Control_MSK (0x00000018) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux1_Control_MAX (0x00000003) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux1_Control_DEF (0x00000001) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux2_Control_OFF ( 6) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux2_Control_WID ( 2) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux2_Control_MSK (0x000000C0) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux2_Control_MAX (0x00000003) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux2_Control_DEF (0x00000001) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_ECC_Replace_Byte_Control_OFF (14) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_ECC_Replace_Byte_Control_WID ( 1) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_ECC_Replace_Byte_Control_MSK (0x00004000) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_ECC_Replace_Byte_Control_MAX (0x00000001) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_ECC_Replace_Byte_Control_DEF (0x00000001) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_ECC_Data_Source_Sel_OFF (15) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_ECC_Data_Source_Sel_WID ( 1) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_ECC_Data_Source_Sel_MSK (0x00008000) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_ECC_Data_Source_Sel_MAX (0x00000001) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_ECC_Data_Source_Sel_DEF (0x00000001) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Save_LFSR_Seed_Rate_OFF (16) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Save_LFSR_Seed_Rate_WID ( 6) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Save_LFSR_Seed_Rate_MSK (0x003F0000) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Save_LFSR_Seed_Rate_MAX (0x0000003F) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Save_LFSR_Seed_Rate_DEF (0x00000000) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Reload_LFSR_Seed_Rate_OFF (24) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Reload_LFSR_Seed_Rate_WID ( 3) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Reload_LFSR_Seed_Rate_MSK (0x07000000) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Reload_LFSR_Seed_Rate_MAX (0x00000007) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Reload_LFSR_Seed_Rate_DEF (0x00000000) + +#define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_RD_STATUS_REG (0x00004C44) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_RD_STATUS_WDB_Current_Read_Pointer_OFF ( 0) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_RD_STATUS_WDB_Current_Read_Pointer_WID ( 6) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_RD_STATUS_WDB_Current_Read_Pointer_MSK (0x0000003F) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_RD_STATUS_WDB_Current_Read_Pointer_MAX (0x0000003F) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_RD_STATUS_WDB_Current_Read_Pointer_DEF (0x00000000) + +#define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_0_REG (0x00004C48) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_0_Pattern_Buffer_OFF ( 0) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_0_Pattern_Buffer_WID (24) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_0_Pattern_Buffer_MSK (0x00FFFFFF) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_0_Pattern_Buffer_MAX (0x00FFFFFF) + +#define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_1_REG (0x00004C4C) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_1_Pattern_Buffer_OFF ( 0) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_1_Pattern_Buffer_WID (24) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_1_Pattern_Buffer_MSK (0x00FFFFFF) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_1_Pattern_Buffer_MAX (0x00FFFFFF) + +#define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_2_REG (0x00004C50) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_2_Pattern_Buffer_OFF ( 0) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_2_Pattern_Buffer_WID (24) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_2_Pattern_Buffer_MSK (0x00FFFFFF) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_2_Pattern_Buffer_MAX (0x00FFFFFF) + +#define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_0_REG (0x00004C54) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_0_Pattern_Buffer_OFF ( 0) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_0_Pattern_Buffer_WID (24) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_0_Pattern_Buffer_MSK (0x00FFFFFF) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_0_Pattern_Buffer_MAX (0x00FFFFFF) + +#define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_1_REG (0x00004C58) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_1_Pattern_Buffer_OFF ( 0) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_1_Pattern_Buffer_WID (24) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_1_Pattern_Buffer_MSK (0x00FFFFFF) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_1_Pattern_Buffer_MAX (0x00FFFFFF) + +#define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_2_REG (0x00004C5C) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_2_Pattern_Buffer_OFF ( 0) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_2_Pattern_Buffer_WID (24) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_2_Pattern_Buffer_MSK (0x00FFFFFF) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_2_Pattern_Buffer_MAX (0x00FFFFFF) + +#define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_0_REG (0x00004C60) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_0_Pattern_Buffer_OFF ( 0) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_0_Pattern_Buffer_WID (24) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_0_Pattern_Buffer_MSK (0x00FFFFFF) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_0_Pattern_Buffer_MAX (0x00FFFFFF) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_0_Pattern_Buffer_DEF (0x00000000) + +#define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_1_REG (0x00004C64) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_1_Pattern_Buffer_OFF ( 0) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_1_Pattern_Buffer_WID (24) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_1_Pattern_Buffer_MSK (0x00FFFFFF) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_1_Pattern_Buffer_MAX (0x00FFFFFF) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_1_Pattern_Buffer_DEF (0x00000000) + +#define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_2_REG (0x00004C68) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_2_Pattern_Buffer_OFF ( 0) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_2_Pattern_Buffer_WID (24) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_2_Pattern_Buffer_MSK (0x00FFFFFF) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_2_Pattern_Buffer_MAX (0x00FFFFFF) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_2_Pattern_Buffer_DEF (0x00000000) + +#define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_0_REG (0x00004C6C) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_0_Pattern_Buffer_OFF ( 0) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_0_Pattern_Buffer_WID (24) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_0_Pattern_Buffer_MSK (0x00FFFFFF) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_0_Pattern_Buffer_MAX (0x00FFFFFF) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_0_Pattern_Buffer_DEF (0x00000000) + +#define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_1_REG (0x00004C70) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_1_Pattern_Buffer_OFF ( 0) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_1_Pattern_Buffer_WID (24) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_1_Pattern_Buffer_MSK (0x00FFFFFF) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_1_Pattern_Buffer_MAX (0x00FFFFFF) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_1_Pattern_Buffer_DEF (0x00000000) + +#define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_2_REG (0x00004C74) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_2_Pattern_Buffer_OFF ( 0) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_2_Pattern_Buffer_WID (24) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_2_Pattern_Buffer_MSK (0x00FFFFFF) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_2_Pattern_Buffer_MAX (0x00FFFFFF) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_2_Pattern_Buffer_DEF (0x00000000) + +#define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_REG (0x00004C78) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_L_data_select_OFF ( 0) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_L_data_select_WID ( 1) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_L_data_select_MSK (0x00000001) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_L_data_select_MAX (0x00000001) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_L_data_select_DEF (0x00000000) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_Enable_Sweep_Frequency_OFF ( 1) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_Enable_Sweep_Frequency_WID ( 1) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_Enable_Sweep_Frequency_MSK (0x00000002) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_Enable_Sweep_Frequency_MAX (0x00000001) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_Enable_Sweep_Frequency_DEF (0x00000000) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_L_counter_OFF ( 8) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_L_counter_WID ( 8) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_L_counter_MSK (0x0000FF00) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_L_counter_MAX (0x000000FF) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_L_counter_DEF (0x00000001) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_M_counter_OFF (16) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_M_counter_WID ( 8) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_M_counter_MSK (0x00FF0000) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_M_counter_MAX (0x000000FF) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_M_counter_DEF (0x00000001) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_N_counter_OFF (24) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_N_counter_WID ( 8) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_N_counter_MSK (0xFF000000) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_N_counter_MAX (0x000000FF) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_N_counter_DEF (0x00000001) + +#define MCSCHEDS_CR_REUT_CH_PAT_WDB_INV_REG (0x00004C84) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_INV_ECC_Inv_or_DC_Enable_OFF ( 0) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_INV_ECC_Inv_or_DC_Enable_WID ( 8) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_INV_ECC_Inv_or_DC_Enable_MSK (0x000000FF) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_INV_ECC_Inv_or_DC_Enable_MAX (0x000000FF) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_INV_ECC_Inv_or_DC_Enable_DEF (0x00000000) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Shift_Rate_OFF (16) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Shift_Rate_WID ( 4) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Shift_Rate_MSK (0x000F0000) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Shift_Rate_MAX (0x0000000F) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Shift_Rate_DEF (0x00000000) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_INV_DC_Polarity_Control_OFF (20) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_INV_DC_Polarity_Control_WID ( 1) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_INV_DC_Polarity_Control_MSK (0x00100000) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_INV_DC_Polarity_Control_MAX (0x00000001) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_INV_DC_Polarity_Control_DEF (0x00000000) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Control_OFF (30) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Control_WID ( 1) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Control_MSK (0x40000000) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Control_MAX (0x00000001) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Control_DEF (0x00000000) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Shift_Enable_OFF (31) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Shift_Enable_WID ( 1) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Shift_Enable_MSK (0x80000000) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Shift_Enable_MAX (0x00000001) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Shift_Enable_DEF (0x00000000) + +#define MCSCHEDS_CR_REUT_CH_PAT_WDB_DATA_INV_REG (0x00004C90) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_DATA_INV_Data_Inv_or_DC_Enable_OFF ( 0) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_DATA_INV_Data_Inv_or_DC_Enable_WID (64) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_DATA_INV_Data_Inv_or_DC_Enable_MSK (0xFFFFFFFFFFFFFFFF) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_DATA_INV_Data_Inv_or_DC_Enable_MAX (0xFFFFFFFFFFFFFFFF) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_DATA_INV_Data_Inv_or_DC_Enable_DEF (0x00000000) + +#define MCSCHEDS_CR_REUT_CH_ERR_CTL_REG (0x00004C98) + #define MCSCHEDS_CR_REUT_CH_ERR_CTL_Stop_on_Nth_Error_OFF ( 0) + #define MCSCHEDS_CR_REUT_CH_ERR_CTL_Stop_on_Nth_Error_WID ( 6) + #define MCSCHEDS_CR_REUT_CH_ERR_CTL_Stop_on_Nth_Error_MSK (0x0000003F) + #define MCSCHEDS_CR_REUT_CH_ERR_CTL_Stop_on_Nth_Error_MAX (0x0000003F) + #define MCSCHEDS_CR_REUT_CH_ERR_CTL_Stop_on_Nth_Error_DEF (0x00000001) + #define MCSCHEDS_CR_REUT_CH_ERR_CTL_Stop_On_Error_Control_OFF (12) + #define MCSCHEDS_CR_REUT_CH_ERR_CTL_Stop_On_Error_Control_WID ( 2) + #define MCSCHEDS_CR_REUT_CH_ERR_CTL_Stop_On_Error_Control_MSK (0x00003000) + #define MCSCHEDS_CR_REUT_CH_ERR_CTL_Stop_On_Error_Control_MAX (0x00000003) + #define MCSCHEDS_CR_REUT_CH_ERR_CTL_Stop_On_Error_Control_DEF (0x00000000) + #define MCSCHEDS_CR_REUT_CH_ERR_CTL_Selective_Error_Enable_Chunk_OFF (16) + #define MCSCHEDS_CR_REUT_CH_ERR_CTL_Selective_Error_Enable_Chunk_WID ( 8) + #define MCSCHEDS_CR_REUT_CH_ERR_CTL_Selective_Error_Enable_Chunk_MSK (0x00FF0000) + #define MCSCHEDS_CR_REUT_CH_ERR_CTL_Selective_Error_Enable_Chunk_MAX (0x000000FF) + #define MCSCHEDS_CR_REUT_CH_ERR_CTL_Selective_Error_Enable_Chunk_DEF (0x000000FF) + #define MCSCHEDS_CR_REUT_CH_ERR_CTL_Selective_Error_Enable_Cacheline_OFF (24) + #define MCSCHEDS_CR_REUT_CH_ERR_CTL_Selective_Error_Enable_Cacheline_WID ( 8) + #define MCSCHEDS_CR_REUT_CH_ERR_CTL_Selective_Error_Enable_Cacheline_MSK (0xFF000000) + #define MCSCHEDS_CR_REUT_CH_ERR_CTL_Selective_Error_Enable_Cacheline_MAX (0x000000FF) + #define MCSCHEDS_CR_REUT_CH_ERR_CTL_Selective_Error_Enable_Cacheline_DEF (0x000000FF) + +#define MCSCHEDS_CR_REUT_CH_ERR_ECC_MASK_REG (0x00004C9C) + #define MCSCHEDS_CR_REUT_CH_ERR_ECC_MASK_ECC_Error_Mask_OFF ( 0) + #define MCSCHEDS_CR_REUT_CH_ERR_ECC_MASK_ECC_Error_Mask_WID ( 8) + #define MCSCHEDS_CR_REUT_CH_ERR_ECC_MASK_ECC_Error_Mask_MSK (0x000000FF) + #define MCSCHEDS_CR_REUT_CH_ERR_ECC_MASK_ECC_Error_Mask_MAX (0x000000FF) + #define MCSCHEDS_CR_REUT_CH_ERR_ECC_MASK_ECC_Error_Mask_DEF (0x00000000) + +#define MCSCHEDS_CR_STM_CONFIG_REG (0x00004CA4) + #define MCSCHEDS_CR_STM_CONFIG_Stretch_mode_OFF ( 0) + #define MCSCHEDS_CR_STM_CONFIG_Stretch_mode_WID ( 2) + #define MCSCHEDS_CR_STM_CONFIG_Stretch_mode_MSK (0x00000003) + #define MCSCHEDS_CR_STM_CONFIG_Stretch_mode_MAX (0x00000003) + #define MCSCHEDS_CR_STM_CONFIG_Stretch_mode_DEF (0x00000000) + #define MCSCHEDS_CR_STM_CONFIG_STF_OFF ( 4) + #define MCSCHEDS_CR_STM_CONFIG_STF_WID ( 3) + #define MCSCHEDS_CR_STM_CONFIG_STF_MSK (0x00000070) + #define MCSCHEDS_CR_STM_CONFIG_STF_MAX (0x00000007) + #define MCSCHEDS_CR_STM_CONFIG_STF_DEF (0x00000000) + +#define MCSCHEDS_CR_SC_PR_CNT_CONFIG_REG (0x00004CA8) + #define MCSCHEDS_CR_SC_PR_CNT_CONFIG_Priority_count_ring_OFF ( 0) + #define MCSCHEDS_CR_SC_PR_CNT_CONFIG_Priority_count_ring_WID (10) + #define MCSCHEDS_CR_SC_PR_CNT_CONFIG_Priority_count_ring_MSK (0x000003FF) + #define MCSCHEDS_CR_SC_PR_CNT_CONFIG_Priority_count_ring_MAX (0x000003FF) + #define MCSCHEDS_CR_SC_PR_CNT_CONFIG_Priority_count_ring_DEF (0x00000040) + #define MCSCHEDS_CR_SC_PR_CNT_CONFIG_Priority_count_SA_OFF (16) + #define MCSCHEDS_CR_SC_PR_CNT_CONFIG_Priority_count_SA_WID (10) + #define MCSCHEDS_CR_SC_PR_CNT_CONFIG_Priority_count_SA_MSK (0x03FF0000) + #define MCSCHEDS_CR_SC_PR_CNT_CONFIG_Priority_count_SA_MAX (0x000003FF) + #define MCSCHEDS_CR_SC_PR_CNT_CONFIG_Priority_count_SA_DEF (0x00000100) + +#define MCSCHEDS_CR_SC_PCIT_REG (0x00004CAC) + #define MCSCHEDS_CR_SC_PCIT_PCIT_OFF ( 0) + #define MCSCHEDS_CR_SC_PCIT_PCIT_WID ( 8) + #define MCSCHEDS_CR_SC_PCIT_PCIT_MSK (0x000000FF) + #define MCSCHEDS_CR_SC_PCIT_PCIT_MAX (0x000000FF) + #define MCSCHEDS_CR_SC_PCIT_PCIT_DEF (0x00000040) + +#define MCSCHEDS_CR_PM_PDWN_CONFIG_REG (0x00004CB0) + #define MCSCHEDS_CR_PM_PDWN_CONFIG_PDWN_idle_counter_OFF ( 0) + #define MCSCHEDS_CR_PM_PDWN_CONFIG_PDWN_idle_counter_WID (12) + #define MCSCHEDS_CR_PM_PDWN_CONFIG_PDWN_idle_counter_MSK (0x00000FFF) + #define MCSCHEDS_CR_PM_PDWN_CONFIG_PDWN_idle_counter_MAX (0x00000FFF) + #define MCSCHEDS_CR_PM_PDWN_CONFIG_PDWN_idle_counter_DEF (0x00000000) + #define MCSCHEDS_CR_PM_PDWN_CONFIG_PDWN_mode_OFF (12) + #define MCSCHEDS_CR_PM_PDWN_CONFIG_PDWN_mode_WID ( 4) + #define MCSCHEDS_CR_PM_PDWN_CONFIG_PDWN_mode_MSK (0x0000F000) + #define MCSCHEDS_CR_PM_PDWN_CONFIG_PDWN_mode_MAX (0x0000000F) + #define MCSCHEDS_CR_PM_PDWN_CONFIG_PDWN_mode_DEF (0x00000000) + +#define MCSCHEDS_CR_ECC_INJECT_COUNT_REG (0x00004CB4) + #define MCSCHEDS_CR_ECC_INJECT_COUNT_Count_OFF ( 0) + #define MCSCHEDS_CR_ECC_INJECT_COUNT_Count_WID (32) + #define MCSCHEDS_CR_ECC_INJECT_COUNT_Count_MSK (0xFFFFFFFF) + #define MCSCHEDS_CR_ECC_INJECT_COUNT_Count_MAX (0xFFFFFFFF) + #define MCSCHEDS_CR_ECC_INJECT_COUNT_Count_DEF (0xFFFFFFFF) + +#define MCSCHEDS_CR_ECC_DFT_REG (0x00004CB8) + #define MCSCHEDS_CR_ECC_DFT_ECC4ANA_fill_OFF ( 0) + #define MCSCHEDS_CR_ECC_DFT_ECC4ANA_fill_WID ( 8) + #define MCSCHEDS_CR_ECC_DFT_ECC4ANA_fill_MSK (0x000000FF) + #define MCSCHEDS_CR_ECC_DFT_ECC4ANA_fill_MAX (0x000000FF) + #define MCSCHEDS_CR_ECC_DFT_ECC4ANA_fill_DEF (0x00000000) + #define MCSCHEDS_CR_ECC_DFT_ECC4ANA_trigger_OFF ( 8) + #define MCSCHEDS_CR_ECC_DFT_ECC4ANA_trigger_WID ( 2) + #define MCSCHEDS_CR_ECC_DFT_ECC4ANA_trigger_MSK (0x00000300) + #define MCSCHEDS_CR_ECC_DFT_ECC4ANA_trigger_MAX (0x00000003) + #define MCSCHEDS_CR_ECC_DFT_ECC4ANA_trigger_DEF (0x00000000) + #define MCSCHEDS_CR_ECC_DFT_ECC4ANA_BS_OFF (10) + #define MCSCHEDS_CR_ECC_DFT_ECC4ANA_BS_WID ( 1) + #define MCSCHEDS_CR_ECC_DFT_ECC4ANA_BS_MSK (0x00000400) + #define MCSCHEDS_CR_ECC_DFT_ECC4ANA_BS_MAX (0x00000001) + #define MCSCHEDS_CR_ECC_DFT_ECC4ANA_BS_DEF (0x00000000) + #define MCSCHEDS_CR_ECC_DFT_ECC_Inject_OFF (11) + #define MCSCHEDS_CR_ECC_DFT_ECC_Inject_WID ( 3) + #define MCSCHEDS_CR_ECC_DFT_ECC_Inject_MSK (0x00003800) + #define MCSCHEDS_CR_ECC_DFT_ECC_Inject_MAX (0x00000007) + #define MCSCHEDS_CR_ECC_DFT_ECC_Inject_DEF (0x00000000) + #define MCSCHEDS_CR_ECC_DFT_ECC_correction_disable_OFF (14) + #define MCSCHEDS_CR_ECC_DFT_ECC_correction_disable_WID ( 1) + #define MCSCHEDS_CR_ECC_DFT_ECC_correction_disable_MSK (0x00004000) + #define MCSCHEDS_CR_ECC_DFT_ECC_correction_disable_MAX (0x00000001) + #define MCSCHEDS_CR_ECC_DFT_ECC_correction_disable_DEF (0x00000000) + #define MCSCHEDS_CR_ECC_DFT_ECC4ANA_Inject_OFF (15) + #define MCSCHEDS_CR_ECC_DFT_ECC4ANA_Inject_WID ( 1) + #define MCSCHEDS_CR_ECC_DFT_ECC4ANA_Inject_MSK (0x00008000) + #define MCSCHEDS_CR_ECC_DFT_ECC4ANA_Inject_MAX (0x00000001) + #define MCSCHEDS_CR_ECC_DFT_ECC4ANA_Inject_DEF (0x00000000) + #define MCSCHEDS_CR_ECC_DFT_DIS_MCA_LOG_OFF (16) + #define MCSCHEDS_CR_ECC_DFT_DIS_MCA_LOG_WID ( 1) + #define MCSCHEDS_CR_ECC_DFT_DIS_MCA_LOG_MSK (0x00010000) + #define MCSCHEDS_CR_ECC_DFT_DIS_MCA_LOG_MAX (0x00000001) + #define MCSCHEDS_CR_ECC_DFT_DIS_MCA_LOG_DEF (0x00000000) + #define MCSCHEDS_CR_ECC_DFT_DIS_PCH_EVENT_OFF (17) + #define MCSCHEDS_CR_ECC_DFT_DIS_PCH_EVENT_WID ( 1) + #define MCSCHEDS_CR_ECC_DFT_DIS_PCH_EVENT_MSK (0x00020000) + #define MCSCHEDS_CR_ECC_DFT_DIS_PCH_EVENT_MAX (0x00000001) + #define MCSCHEDS_CR_ECC_DFT_DIS_PCH_EVENT_DEF (0x00000000) + #define MCSCHEDS_CR_ECC_DFT_DIS_PCIE_POISON_OFF (18) + #define MCSCHEDS_CR_ECC_DFT_DIS_PCIE_POISON_WID ( 1) + #define MCSCHEDS_CR_ECC_DFT_DIS_PCIE_POISON_MSK (0x00040000) + #define MCSCHEDS_CR_ECC_DFT_DIS_PCIE_POISON_MAX (0x00000001) + #define MCSCHEDS_CR_ECC_DFT_DIS_PCIE_POISON_DEF (0x00000000) + +#define MCSCHEDS_CR_VISA_CTL_MCSCHEDS_REG (0x00004CC0) + #define MCSCHEDS_CR_VISA_CTL_MCSCHEDS_Data_OFF ( 0) + #define MCSCHEDS_CR_VISA_CTL_MCSCHEDS_Data_WID (18) + #define MCSCHEDS_CR_VISA_CTL_MCSCHEDS_Data_MSK (0x0003FFFF) + #define MCSCHEDS_CR_VISA_CTL_MCSCHEDS_Data_MAX (0x0003FFFF) + #define MCSCHEDS_CR_VISA_CTL_MCSCHEDS_Data_DEF (0x00000000) + #define MCSCHEDS_CR_VISA_CTL_MCSCHEDS_VORANGE_OFF (31) + #define MCSCHEDS_CR_VISA_CTL_MCSCHEDS_VORANGE_WID ( 1) + #define MCSCHEDS_CR_VISA_CTL_MCSCHEDS_VORANGE_MSK (0x80000000) + #define MCSCHEDS_CR_VISA_CTL_MCSCHEDS_VORANGE_MAX (0x00000001) + #define MCSCHEDS_CR_VISA_CTL_MCSCHEDS_VORANGE_DEF (0x00000000) + +#define MCSCHEDS_CR_VISA_XBAR_MCSCHEDS_REG (0x00004CC4) + #define MCSCHEDS_CR_VISA_XBAR_MCSCHEDS_Data_OFF ( 0) + #define MCSCHEDS_CR_VISA_XBAR_MCSCHEDS_Data_WID (32) + #define MCSCHEDS_CR_VISA_XBAR_MCSCHEDS_Data_MSK (0xFFFFFFFF) + #define MCSCHEDS_CR_VISA_XBAR_MCSCHEDS_Data_MAX (0xFFFFFFFF) + #define MCSCHEDS_CR_VISA_XBAR_MCSCHEDS_Data_DEF (0x76543210) + +#define MCSCHEDS_CR_ECCERRLOG0_REG (0x00004CC8) + #define MCSCHEDS_CR_ECCERRLOG0_CERRSTS_OFF ( 0) + #define MCSCHEDS_CR_ECCERRLOG0_CERRSTS_WID ( 1) + #define MCSCHEDS_CR_ECCERRLOG0_CERRSTS_MSK (0x00000001) + #define MCSCHEDS_CR_ECCERRLOG0_CERRSTS_MAX (0x00000001) + #define MCSCHEDS_CR_ECCERRLOG0_CERRSTS_DEF (0x00000000) + #define MCSCHEDS_CR_ECCERRLOG0_MERRSTS_OFF ( 1) + #define MCSCHEDS_CR_ECCERRLOG0_MERRSTS_WID ( 1) + #define MCSCHEDS_CR_ECCERRLOG0_MERRSTS_MSK (0x00000002) + #define MCSCHEDS_CR_ECCERRLOG0_MERRSTS_MAX (0x00000001) + #define MCSCHEDS_CR_ECCERRLOG0_MERRSTS_DEF (0x00000000) + #define MCSCHEDS_CR_ECCERRLOG0_ERRSYND_OFF (16) + #define MCSCHEDS_CR_ECCERRLOG0_ERRSYND_WID ( 8) + #define MCSCHEDS_CR_ECCERRLOG0_ERRSYND_MSK (0x00FF0000) + #define MCSCHEDS_CR_ECCERRLOG0_ERRSYND_MAX (0x000000FF) + #define MCSCHEDS_CR_ECCERRLOG0_ERRSYND_DEF (0x00000000) + #define MCSCHEDS_CR_ECCERRLOG0_ERRCHUNK_OFF (24) + #define MCSCHEDS_CR_ECCERRLOG0_ERRCHUNK_WID ( 3) + #define MCSCHEDS_CR_ECCERRLOG0_ERRCHUNK_MSK (0x07000000) + #define MCSCHEDS_CR_ECCERRLOG0_ERRCHUNK_MAX (0x00000007) + #define MCSCHEDS_CR_ECCERRLOG0_ERRCHUNK_DEF (0x00000000) + #define MCSCHEDS_CR_ECCERRLOG0_ERRRANK_OFF (27) + #define MCSCHEDS_CR_ECCERRLOG0_ERRRANK_WID ( 2) + #define MCSCHEDS_CR_ECCERRLOG0_ERRRANK_MSK (0x18000000) + #define MCSCHEDS_CR_ECCERRLOG0_ERRRANK_MAX (0x00000003) + #define MCSCHEDS_CR_ECCERRLOG0_ERRRANK_DEF (0x00000000) + #define MCSCHEDS_CR_ECCERRLOG0_ERRBANK_OFF (29) + #define MCSCHEDS_CR_ECCERRLOG0_ERRBANK_WID ( 3) + #define MCSCHEDS_CR_ECCERRLOG0_ERRBANK_MSK (0xE0000000) + #define MCSCHEDS_CR_ECCERRLOG0_ERRBANK_MAX (0x00000007) + #define MCSCHEDS_CR_ECCERRLOG0_ERRBANK_DEF (0x00000000) + +#define MCSCHEDS_CR_ECCERRLOG1_REG (0x00004CCC) + #define MCSCHEDS_CR_ECCERRLOG1_ERRROW_OFF ( 0) + #define MCSCHEDS_CR_ECCERRLOG1_ERRROW_WID (16) + #define MCSCHEDS_CR_ECCERRLOG1_ERRROW_MSK (0x0000FFFF) + #define MCSCHEDS_CR_ECCERRLOG1_ERRROW_MAX (0x0000FFFF) + #define MCSCHEDS_CR_ECCERRLOG1_ERRROW_DEF (0x00000000) + #define MCSCHEDS_CR_ECCERRLOG1_ERRCOL_OFF (16) + #define MCSCHEDS_CR_ECCERRLOG1_ERRCOL_WID (16) + #define MCSCHEDS_CR_ECCERRLOG1_ERRCOL_MSK (0xFFFF0000) + #define MCSCHEDS_CR_ECCERRLOG1_ERRCOL_MAX (0x0000FFFF) + #define MCSCHEDS_CR_ECCERRLOG1_ERRCOL_DEF (0x00000000) + +#define MCSCHEDS_CR_SC_WR_ADD_DELAY_REG (0x00004CD0) + #define MCSCHEDS_CR_SC_WR_ADD_DELAY_D0R0_OFF ( 0) + #define MCSCHEDS_CR_SC_WR_ADD_DELAY_D0R0_WID ( 2) + #define MCSCHEDS_CR_SC_WR_ADD_DELAY_D0R0_MSK (0x00000003) + #define MCSCHEDS_CR_SC_WR_ADD_DELAY_D0R0_MAX (0x00000003) + #define MCSCHEDS_CR_SC_WR_ADD_DELAY_D0R0_DEF (0x00000000) + #define MCSCHEDS_CR_SC_WR_ADD_DELAY_D0R1_OFF ( 2) + #define MCSCHEDS_CR_SC_WR_ADD_DELAY_D0R1_WID ( 2) + #define MCSCHEDS_CR_SC_WR_ADD_DELAY_D0R1_MSK (0x0000000C) + #define MCSCHEDS_CR_SC_WR_ADD_DELAY_D0R1_MAX (0x00000003) + #define MCSCHEDS_CR_SC_WR_ADD_DELAY_D0R1_DEF (0x00000000) + #define MCSCHEDS_CR_SC_WR_ADD_DELAY_D1R0_OFF ( 4) + #define MCSCHEDS_CR_SC_WR_ADD_DELAY_D1R0_WID ( 2) + #define MCSCHEDS_CR_SC_WR_ADD_DELAY_D1R0_MSK (0x00000030) + #define MCSCHEDS_CR_SC_WR_ADD_DELAY_D1R0_MAX (0x00000003) + #define MCSCHEDS_CR_SC_WR_ADD_DELAY_D1R0_DEF (0x00000000) + #define MCSCHEDS_CR_SC_WR_ADD_DELAY_D1R1_OFF ( 6) + #define MCSCHEDS_CR_SC_WR_ADD_DELAY_D1R1_WID ( 2) + #define MCSCHEDS_CR_SC_WR_ADD_DELAY_D1R1_MSK (0x000000C0) + #define MCSCHEDS_CR_SC_WR_ADD_DELAY_D1R1_MAX (0x00000003) + #define MCSCHEDS_CR_SC_WR_ADD_DELAY_D1R1_DEF (0x00000000) + +#define MCSCHEDS_CR_WMM_READ_CONFIG_REG (0x00004CD4) + #define MCSCHEDS_CR_WMM_READ_CONFIG_Dis_Opp_rd_OFF ( 0) + #define MCSCHEDS_CR_WMM_READ_CONFIG_Dis_Opp_rd_WID ( 1) + #define MCSCHEDS_CR_WMM_READ_CONFIG_Dis_Opp_rd_MSK (0x00000001) + #define MCSCHEDS_CR_WMM_READ_CONFIG_Dis_Opp_rd_MAX (0x00000001) + #define MCSCHEDS_CR_WMM_READ_CONFIG_Dis_Opp_rd_DEF (0x00000000) + #define MCSCHEDS_CR_WMM_READ_CONFIG_ACT_Enable_OFF ( 1) + #define MCSCHEDS_CR_WMM_READ_CONFIG_ACT_Enable_WID ( 1) + #define MCSCHEDS_CR_WMM_READ_CONFIG_ACT_Enable_MSK (0x00000002) + #define MCSCHEDS_CR_WMM_READ_CONFIG_ACT_Enable_MAX (0x00000001) + #define MCSCHEDS_CR_WMM_READ_CONFIG_ACT_Enable_DEF (0x00000001) + #define MCSCHEDS_CR_WMM_READ_CONFIG_PRE_Enable_OFF ( 2) + #define MCSCHEDS_CR_WMM_READ_CONFIG_PRE_Enable_WID ( 1) + #define MCSCHEDS_CR_WMM_READ_CONFIG_PRE_Enable_MSK (0x00000004) + #define MCSCHEDS_CR_WMM_READ_CONFIG_PRE_Enable_MAX (0x00000001) + #define MCSCHEDS_CR_WMM_READ_CONFIG_PRE_Enable_DEF (0x00000001) + #define MCSCHEDS_CR_WMM_READ_CONFIG_MAX_RPQ_Cas_OFF ( 3) + #define MCSCHEDS_CR_WMM_READ_CONFIG_MAX_RPQ_Cas_WID ( 4) + #define MCSCHEDS_CR_WMM_READ_CONFIG_MAX_RPQ_Cas_MSK (0x00000078) + #define MCSCHEDS_CR_WMM_READ_CONFIG_MAX_RPQ_Cas_MAX (0x0000000F) + #define MCSCHEDS_CR_WMM_READ_CONFIG_MAX_RPQ_Cas_DEF (0x00000008) + +#define MCSCHEDS_CR_REUT_CH_ERR_DATA_MASK_REG (0x00004CD8) + #define MCSCHEDS_CR_REUT_CH_ERR_DATA_MASK_Data_Error_Mask_OFF ( 0) + #define MCSCHEDS_CR_REUT_CH_ERR_DATA_MASK_Data_Error_Mask_WID (64) + #define MCSCHEDS_CR_REUT_CH_ERR_DATA_MASK_Data_Error_Mask_MSK (0xFFFFFFFFFFFFFFFF) + #define MCSCHEDS_CR_REUT_CH_ERR_DATA_MASK_Data_Error_Mask_MAX (0xFFFFFFFFFFFFFFFF) + #define MCSCHEDS_CR_REUT_CH_ERR_DATA_MASK_Data_Error_Mask_DEF (0x00000000) + +#define MCSCHEDS_CR_REUT_CH_ERR_DATA_STATUS_REG (0x00004CE0) + #define MCSCHEDS_CR_REUT_CH_ERR_DATA_STATUS_Data_Error_Status_OFF ( 0) + #define MCSCHEDS_CR_REUT_CH_ERR_DATA_STATUS_Data_Error_Status_WID (64) + #define MCSCHEDS_CR_REUT_CH_ERR_DATA_STATUS_Data_Error_Status_MSK (0xFFFFFFFFFFFFFFFF) + #define MCSCHEDS_CR_REUT_CH_ERR_DATA_STATUS_Data_Error_Status_MAX (0xFFFFFFFFFFFFFFFF) + #define MCSCHEDS_CR_REUT_CH_ERR_DATA_STATUS_Data_Error_Status_DEF (0x00000000) + +#define MCSCHEDS_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_REG (0x00004CE8) + #define MCSCHEDS_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_ECC_Error_Status_OFF ( 0) + #define MCSCHEDS_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_ECC_Error_Status_WID ( 8) + #define MCSCHEDS_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_ECC_Error_Status_MSK (0x000000FF) + #define MCSCHEDS_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_ECC_Error_Status_MAX (0x000000FF) + #define MCSCHEDS_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_ECC_Error_Status_DEF (0x00000000) + #define MCSCHEDS_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Chunk_Error_Status_OFF ( 8) + #define MCSCHEDS_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Chunk_Error_Status_WID ( 8) + #define MCSCHEDS_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Chunk_Error_Status_MSK (0x0000FF00) + #define MCSCHEDS_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Chunk_Error_Status_MAX (0x000000FF) + #define MCSCHEDS_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Chunk_Error_Status_DEF (0x00000000) + #define MCSCHEDS_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Rank_Error_Status_OFF (16) + #define MCSCHEDS_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Rank_Error_Status_WID ( 4) + #define MCSCHEDS_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Rank_Error_Status_MSK (0x000F0000) + #define MCSCHEDS_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Rank_Error_Status_MAX (0x0000000F) + #define MCSCHEDS_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Rank_Error_Status_DEF (0x00000000) + #define MCSCHEDS_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Byte_Group_Error_Status_OFF (32) + #define MCSCHEDS_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Byte_Group_Error_Status_WID ( 9) + #define MCSCHEDS_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Byte_Group_Error_Status_MSK (0x1FF00000000) + #define MCSCHEDS_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Byte_Group_Error_Status_MAX (0x000001FF) + #define MCSCHEDS_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Byte_Group_Error_Status_DEF (0x00000000) + #define MCSCHEDS_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_WDB_Rd_Chunk_Num_Status_OFF (52) + #define MCSCHEDS_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_WDB_Rd_Chunk_Num_Status_WID ( 3) + #define MCSCHEDS_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_WDB_Rd_Chunk_Num_Status_MSK (0x70000000000000) + #define MCSCHEDS_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_WDB_Rd_Chunk_Num_Status_MAX (0x00000007) + #define MCSCHEDS_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_WDB_Rd_Chunk_Num_Status_DEF (0x00000000) + #define MCSCHEDS_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Nth_Error_OFF (56) + #define MCSCHEDS_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Nth_Error_WID ( 6) + #define MCSCHEDS_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Nth_Error_MSK (0x3F00000000000000) + #define MCSCHEDS_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Nth_Error_MAX (0x0000003F) + #define MCSCHEDS_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Nth_Error_DEF (0x00000000) + +#define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_0_REG (0x00004CF0) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_0_Counter_Pointer_OFF ( 0) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_0_Counter_Pointer_WID ( 7) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_0_Counter_Pointer_MSK (0x0000007F) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_0_Counter_Pointer_MAX (0x0000007F) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_0_Counter_Pointer_DEF (0x0000007F) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_0_Counter_Control_OFF ( 7) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_0_Counter_Control_WID ( 2) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_0_Counter_Control_MSK (0x00000180) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_0_Counter_Control_MAX (0x00000003) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_0_Counter_Control_DEF (0x00000000) + +#define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_1_REG (0x00004CF4) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_1_Counter_Pointer_OFF ( 0) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_1_Counter_Pointer_WID ( 7) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_1_Counter_Pointer_MSK (0x0000007F) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_1_Counter_Pointer_MAX (0x0000007F) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_1_Counter_Pointer_DEF (0x0000007F) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_1_Counter_Control_OFF ( 7) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_1_Counter_Control_WID ( 2) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_1_Counter_Control_MSK (0x00000180) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_1_Counter_Control_MAX (0x00000003) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_1_Counter_Control_DEF (0x00000000) + +#define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_2_REG (0x00004CF8) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_2_Counter_Pointer_OFF ( 0) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_2_Counter_Pointer_WID ( 7) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_2_Counter_Pointer_MSK (0x0000007F) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_2_Counter_Pointer_MAX (0x0000007F) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_2_Counter_Pointer_DEF (0x0000007F) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_2_Counter_Control_OFF ( 7) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_2_Counter_Control_WID ( 2) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_2_Counter_Control_MSK (0x00000180) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_2_Counter_Control_MAX (0x00000003) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_2_Counter_Control_DEF (0x00000000) + +#define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_3_REG (0x00004CFC) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_3_Counter_Pointer_OFF ( 0) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_3_Counter_Pointer_WID ( 7) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_3_Counter_Pointer_MSK (0x0000007F) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_3_Counter_Pointer_MAX (0x0000007F) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_3_Counter_Pointer_DEF (0x0000007F) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_3_Counter_Control_OFF ( 7) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_3_Counter_Control_WID ( 2) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_3_Counter_Control_MSK (0x00000180) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_3_Counter_Control_MAX (0x00000003) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_3_Counter_Control_DEF (0x00000000) + +#define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_4_REG (0x00004D00) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_4_Counter_Pointer_OFF ( 0) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_4_Counter_Pointer_WID ( 7) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_4_Counter_Pointer_MSK (0x0000007F) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_4_Counter_Pointer_MAX (0x0000007F) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_4_Counter_Pointer_DEF (0x0000007F) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_4_Counter_Control_OFF ( 7) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_4_Counter_Control_WID ( 2) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_4_Counter_Control_MSK (0x00000180) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_4_Counter_Control_MAX (0x00000003) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_4_Counter_Control_DEF (0x00000000) + +#define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_5_REG (0x00004D04) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_5_Counter_Pointer_OFF ( 0) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_5_Counter_Pointer_WID ( 7) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_5_Counter_Pointer_MSK (0x0000007F) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_5_Counter_Pointer_MAX (0x0000007F) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_5_Counter_Pointer_DEF (0x0000007F) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_5_Counter_Control_OFF ( 7) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_5_Counter_Control_WID ( 2) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_5_Counter_Control_MSK (0x00000180) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_5_Counter_Control_MAX (0x00000003) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_5_Counter_Control_DEF (0x00000000) + +#define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_6_REG (0x00004D08) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_6_Counter_Pointer_OFF ( 0) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_6_Counter_Pointer_WID ( 7) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_6_Counter_Pointer_MSK (0x0000007F) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_6_Counter_Pointer_MAX (0x0000007F) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_6_Counter_Pointer_DEF (0x0000007F) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_6_Counter_Control_OFF ( 7) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_6_Counter_Control_WID ( 2) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_6_Counter_Control_MSK (0x00000180) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_6_Counter_Control_MAX (0x00000003) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_6_Counter_Control_DEF (0x00000000) + +#define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_7_REG (0x00004D0C) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_7_Counter_Pointer_OFF ( 0) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_7_Counter_Pointer_WID ( 7) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_7_Counter_Pointer_MSK (0x0000007F) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_7_Counter_Pointer_MAX (0x0000007F) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_7_Counter_Pointer_DEF (0x0000007F) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_7_Counter_Control_OFF ( 7) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_7_Counter_Control_WID ( 2) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_7_Counter_Control_MSK (0x00000180) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_7_Counter_Control_MAX (0x00000003) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_7_Counter_Control_DEF (0x00000000) + +#define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_8_REG (0x00004D10) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_8_Counter_Pointer_OFF ( 0) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_8_Counter_Pointer_WID ( 7) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_8_Counter_Pointer_MSK (0x0000007F) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_8_Counter_Pointer_MAX (0x0000007F) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_8_Counter_Pointer_DEF (0x0000007F) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_8_Counter_Control_OFF ( 7) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_8_Counter_Control_WID ( 2) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_8_Counter_Control_MSK (0x00000180) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_8_Counter_Control_MAX (0x00000003) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_8_Counter_Control_DEF (0x00000000) + +#define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_0_REG (0x00004D14) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_0_Counter_Status_OFF ( 0) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_0_Counter_Status_WID (23) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_0_Counter_Status_MSK (0x007FFFFF) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_0_Counter_Status_MAX (0x007FFFFF) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_0_Counter_Status_DEF (0x00000000) + +#define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_1_REG (0x00004D18) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_1_Counter_Status_OFF ( 0) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_1_Counter_Status_WID (23) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_1_Counter_Status_MSK (0x007FFFFF) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_1_Counter_Status_MAX (0x007FFFFF) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_1_Counter_Status_DEF (0x00000000) + +#define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_2_REG (0x00004D1C) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_2_Counter_Status_OFF ( 0) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_2_Counter_Status_WID (23) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_2_Counter_Status_MSK (0x007FFFFF) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_2_Counter_Status_MAX (0x007FFFFF) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_2_Counter_Status_DEF (0x00000000) + +#define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_3_REG (0x00004D20) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_3_Counter_Status_OFF ( 0) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_3_Counter_Status_WID (23) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_3_Counter_Status_MSK (0x007FFFFF) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_3_Counter_Status_MAX (0x007FFFFF) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_3_Counter_Status_DEF (0x00000000) + +#define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_4_REG (0x00004D24) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_4_Counter_Status_OFF ( 0) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_4_Counter_Status_WID (23) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_4_Counter_Status_MSK (0x007FFFFF) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_4_Counter_Status_MAX (0x007FFFFF) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_4_Counter_Status_DEF (0x00000000) + +#define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_5_REG (0x00004D28) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_5_Counter_Status_OFF ( 0) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_5_Counter_Status_WID (23) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_5_Counter_Status_MSK (0x007FFFFF) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_5_Counter_Status_MAX (0x007FFFFF) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_5_Counter_Status_DEF (0x00000000) + +#define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_6_REG (0x00004D2C) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_6_Counter_Status_OFF ( 0) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_6_Counter_Status_WID (23) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_6_Counter_Status_MSK (0x007FFFFF) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_6_Counter_Status_MAX (0x007FFFFF) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_6_Counter_Status_DEF (0x00000000) + +#define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_7_REG (0x00004D30) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_7_Counter_Status_OFF ( 0) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_7_Counter_Status_WID (23) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_7_Counter_Status_MSK (0x007FFFFF) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_7_Counter_Status_MAX (0x007FFFFF) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_7_Counter_Status_DEF (0x00000000) + +#define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_8_REG (0x00004D34) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_8_Counter_Status_OFF ( 0) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_8_Counter_Status_WID (23) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_8_Counter_Status_MSK (0x007FFFFF) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_8_Counter_Status_MAX (0x007FFFFF) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_8_Counter_Status_DEF (0x00000000) + +#define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_OVERFLOW_STATUS_REG (0x00004D38) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_OVERFLOW_STATUS_Counter_Overflow_Status_OFF ( 0) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_OVERFLOW_STATUS_Counter_Overflow_Status_WID ( 9) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_OVERFLOW_STATUS_Counter_Overflow_Status_MSK (0x000001FF) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_OVERFLOW_STATUS_Counter_Overflow_Status_MAX (0x000001FF) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_OVERFLOW_STATUS_Counter_Overflow_Status_DEF (0x00000000) + +#define MCSCHEDS_CR_REUT_CH_ERROR_ADDR_REG (0x00004D80) + #define MCSCHEDS_CR_REUT_CH_ERROR_ADDR_Column_Address_OFF ( 0) + #define MCSCHEDS_CR_REUT_CH_ERROR_ADDR_Column_Address_WID (10) + #define MCSCHEDS_CR_REUT_CH_ERROR_ADDR_Column_Address_MSK (0x000003FF) + #define MCSCHEDS_CR_REUT_CH_ERROR_ADDR_Column_Address_MAX (0x000003FF) + #define MCSCHEDS_CR_REUT_CH_ERROR_ADDR_Column_Address_DEF (0x00000000) + #define MCSCHEDS_CR_REUT_CH_ERROR_ADDR_Row_Address_OFF (24) + #define MCSCHEDS_CR_REUT_CH_ERROR_ADDR_Row_Address_WID (16) + #define MCSCHEDS_CR_REUT_CH_ERROR_ADDR_Row_Address_MSK (0xFFFF000000) + #define MCSCHEDS_CR_REUT_CH_ERROR_ADDR_Row_Address_MAX (0x0000FFFF) + #define MCSCHEDS_CR_REUT_CH_ERROR_ADDR_Row_Address_DEF (0x00000000) + #define MCSCHEDS_CR_REUT_CH_ERROR_ADDR_Bank_Address_OFF (48) + #define MCSCHEDS_CR_REUT_CH_ERROR_ADDR_Bank_Address_WID ( 3) + #define MCSCHEDS_CR_REUT_CH_ERROR_ADDR_Bank_Address_MSK (0x7000000000000) + #define MCSCHEDS_CR_REUT_CH_ERROR_ADDR_Bank_Address_MAX (0x00000007) + #define MCSCHEDS_CR_REUT_CH_ERROR_ADDR_Bank_Address_DEF (0x00000000) + #define MCSCHEDS_CR_REUT_CH_ERROR_ADDR_Rank_Address_OFF (56) + #define MCSCHEDS_CR_REUT_CH_ERROR_ADDR_Rank_Address_WID ( 2) + #define MCSCHEDS_CR_REUT_CH_ERROR_ADDR_Rank_Address_MSK (0x300000000000000) + #define MCSCHEDS_CR_REUT_CH_ERROR_ADDR_Rank_Address_MAX (0x00000003) + #define MCSCHEDS_CR_REUT_CH_ERROR_ADDR_Rank_Address_DEF (0x00000000) + +#define MCSCHEDS_CR_REUT_CH_ERR_WDB_CAPTURE_STATUS_REG (0x00004D88) + #define MCSCHEDS_CR_REUT_CH_ERR_WDB_CAPTURE_STATUS_WDB_Current_Error_Pointer_OFF ( 0) + #define MCSCHEDS_CR_REUT_CH_ERR_WDB_CAPTURE_STATUS_WDB_Current_Error_Pointer_WID ( 6) + #define MCSCHEDS_CR_REUT_CH_ERR_WDB_CAPTURE_STATUS_WDB_Current_Error_Pointer_MSK (0x0000003F) + #define MCSCHEDS_CR_REUT_CH_ERR_WDB_CAPTURE_STATUS_WDB_Current_Error_Pointer_MAX (0x0000003F) + #define MCSCHEDS_CR_REUT_CH_ERR_WDB_CAPTURE_STATUS_WDB_Current_Error_Pointer_DEF (0x00000000) + +#define MCSCHEDS_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_REG (0x00004D8C) + #define MCSCHEDS_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_Enable_WDB_Error_Capture_OFF ( 0) + #define MCSCHEDS_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_Enable_WDB_Error_Capture_WID ( 1) + #define MCSCHEDS_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_Enable_WDB_Error_Capture_MSK (0x00000001) + #define MCSCHEDS_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_Enable_WDB_Error_Capture_MAX (0x00000001) + #define MCSCHEDS_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_Enable_WDB_Error_Capture_DEF (0x00000000) + #define MCSCHEDS_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_WDB_Starting_Error_Pointer_OFF ( 8) + #define MCSCHEDS_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_WDB_Starting_Error_Pointer_WID ( 6) + #define MCSCHEDS_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_WDB_Starting_Error_Pointer_MSK (0x00003F00) + #define MCSCHEDS_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_WDB_Starting_Error_Pointer_MAX (0x0000003F) + #define MCSCHEDS_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_WDB_Starting_Error_Pointer_DEF (0x00000000) + #define MCSCHEDS_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_WDB_Ending_Error_Pointer_OFF (16) + #define MCSCHEDS_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_WDB_Ending_Error_Pointer_WID ( 6) + #define MCSCHEDS_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_WDB_Ending_Error_Pointer_MSK (0x003F0000) + #define MCSCHEDS_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_WDB_Ending_Error_Pointer_MAX (0x0000003F) + #define MCSCHEDS_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_WDB_Ending_Error_Pointer_DEF (0x00000000) + +#define MCSCHEDS_CR_REUT_CH_MISC_CKE_CTRL_REG (0x00004D90) + #define MCSCHEDS_CR_REUT_CH_MISC_CKE_CTRL_CKE_Override_OFF ( 0) + #define MCSCHEDS_CR_REUT_CH_MISC_CKE_CTRL_CKE_Override_WID ( 4) + #define MCSCHEDS_CR_REUT_CH_MISC_CKE_CTRL_CKE_Override_MSK (0x0000000F) + #define MCSCHEDS_CR_REUT_CH_MISC_CKE_CTRL_CKE_Override_MAX (0x0000000F) + #define MCSCHEDS_CR_REUT_CH_MISC_CKE_CTRL_CKE_Override_DEF (0x0000000F) + #define MCSCHEDS_CR_REUT_CH_MISC_CKE_CTRL_CKE_En_Start_Test_Sync_OFF ( 8) + #define MCSCHEDS_CR_REUT_CH_MISC_CKE_CTRL_CKE_En_Start_Test_Sync_WID ( 1) + #define MCSCHEDS_CR_REUT_CH_MISC_CKE_CTRL_CKE_En_Start_Test_Sync_MSK (0x00000100) + #define MCSCHEDS_CR_REUT_CH_MISC_CKE_CTRL_CKE_En_Start_Test_Sync_MAX (0x00000001) + #define MCSCHEDS_CR_REUT_CH_MISC_CKE_CTRL_CKE_En_Start_Test_Sync_DEF (0x00000000) + #define MCSCHEDS_CR_REUT_CH_MISC_CKE_CTRL_CKE_On_OFF (16) + #define MCSCHEDS_CR_REUT_CH_MISC_CKE_CTRL_CKE_On_WID ( 4) + #define MCSCHEDS_CR_REUT_CH_MISC_CKE_CTRL_CKE_On_MSK (0x000F0000) + #define MCSCHEDS_CR_REUT_CH_MISC_CKE_CTRL_CKE_On_MAX (0x0000000F) + #define MCSCHEDS_CR_REUT_CH_MISC_CKE_CTRL_CKE_On_DEF (0x00000000) + +#define MCSCHEDS_CR_REUT_CH_MISC_ODT_CTRL_REG (0x00004D94) + #define MCSCHEDS_CR_REUT_CH_MISC_ODT_CTRL_ODT_Override_OFF ( 0) + #define MCSCHEDS_CR_REUT_CH_MISC_ODT_CTRL_ODT_Override_WID ( 4) + #define MCSCHEDS_CR_REUT_CH_MISC_ODT_CTRL_ODT_Override_MSK (0x0000000F) + #define MCSCHEDS_CR_REUT_CH_MISC_ODT_CTRL_ODT_Override_MAX (0x0000000F) + #define MCSCHEDS_CR_REUT_CH_MISC_ODT_CTRL_ODT_Override_DEF (0x0000000F) + #define MCSCHEDS_CR_REUT_CH_MISC_ODT_CTRL_ODT_On_OFF (16) + #define MCSCHEDS_CR_REUT_CH_MISC_ODT_CTRL_ODT_On_WID ( 4) + #define MCSCHEDS_CR_REUT_CH_MISC_ODT_CTRL_ODT_On_MSK (0x000F0000) + #define MCSCHEDS_CR_REUT_CH_MISC_ODT_CTRL_ODT_On_MAX (0x0000000F) + #define MCSCHEDS_CR_REUT_CH_MISC_ODT_CTRL_ODT_On_DEF (0x00000000) + #define MCSCHEDS_CR_REUT_CH_MISC_ODT_CTRL_MPR_Train_DDR_On_OFF (31) + #define MCSCHEDS_CR_REUT_CH_MISC_ODT_CTRL_MPR_Train_DDR_On_WID ( 1) + #define MCSCHEDS_CR_REUT_CH_MISC_ODT_CTRL_MPR_Train_DDR_On_MSK (0x80000000) + #define MCSCHEDS_CR_REUT_CH_MISC_ODT_CTRL_MPR_Train_DDR_On_MAX (0x00000001) + #define MCSCHEDS_CR_REUT_CH_MISC_ODT_CTRL_MPR_Train_DDR_On_DEF (0x00000000) + +#define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_REG (0x00004D98) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_Enable_CADB_on_Deselect_OFF ( 0) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_Enable_CADB_on_Deselect_WID ( 1) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_Enable_CADB_on_Deselect_MSK (0x00000001) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_Enable_CADB_on_Deselect_MAX (0x00000001) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_Enable_CADB_on_Deselect_DEF (0x00000000) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_Enable_CADB_Always_On_OFF ( 1) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_Enable_CADB_Always_On_WID ( 1) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_Enable_CADB_Always_On_MSK (0x00000002) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_Enable_CADB_Always_On_MAX (0x00000001) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_Enable_CADB_Always_On_DEF (0x00000000) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_CMD_Deselect_Start_OFF ( 2) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_CMD_Deselect_Start_WID ( 4) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_CMD_Deselect_Start_MSK (0x0000003C) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_CMD_Deselect_Start_MAX (0x0000000F) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_CMD_Deselect_Start_DEF (0x00000000) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_CMD_Deselect_Stop_OFF ( 6) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_CMD_Deselect_Stop_WID ( 4) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_CMD_Deselect_Stop_MSK (0x000003C0) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_CMD_Deselect_Stop_MAX (0x0000000F) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_CMD_Deselect_Stop_DEF (0x00000000) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_Lane_Deselect_Enable_OFF ( 10) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_Lane_Deselect_Enable_WID ( 4) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_Lane_Deselect_Enable_MSK (0x00003C00) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_Lane_Deselect_Enable_MAX (0x0000000F) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_Lane_Deselect_Enable_DEF (0x00000000) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_CAS_Select_Enable_OFF ( 14) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_CAS_Select_Enable_WID ( 2) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_CAS_Select_Enable_MSK (0x0000C000) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_CAS_Select_Enable_MAX (0x00000003) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_CAS_Select_Enable_DEF (0x00000000) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_ACT_Select_Enable_OFF ( 16) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_ACT_Select_Enable_WID ( 2) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_ACT_Select_Enable_MSK (0x00030000) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_ACT_Select_Enable_MAX (0x00000003) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_ACT_Select_Enable_DEF (0x00000000) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_PRE_Select_Enable_OFF ( 18) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_PRE_Select_Enable_WID ( 2) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_PRE_Select_Enable_MSK (0x000C0000) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_PRE_Select_Enable_MAX (0x00000003) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_PRE_Select_Enable_DEF (0x00000000) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_Save_Current_Seed_OFF ( 20) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_Save_Current_Seed_WID ( 4) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_Save_Current_Seed_MSK (0x00F00000) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_Save_Current_Seed_MAX (0x0000000F) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_Save_Current_Seed_DEF (0x00000000) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_Reload_Starting_Seed_OFF ( 24) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_Reload_Starting_Seed_WID ( 4) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_Reload_Starting_Seed_MSK (0x0F000000) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_Reload_Starting_Seed_MAX (0x0000000F) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_Reload_Starting_Seed_DEF (0x00000000) + +#define MCSCHEDS_CR_REUT_CH_PAT_CADB_MRS_REG (0x00004D9C) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MRS_MRS_Gap_OFF ( 0) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MRS_MRS_Gap_WID ( 3) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MRS_MRS_Gap_MSK (0x00000007) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MRS_MRS_Gap_MAX (0x00000007) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MRS_MRS_Gap_DEF (0x00000002) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_Start_Pointer_OFF ( 8) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_Start_Pointer_WID ( 3) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_Start_Pointer_MSK (0x00000700) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_Start_Pointer_MAX (0x00000007) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_Start_Pointer_DEF (0x00000000) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_End_Pointer_OFF (16) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_End_Pointer_WID ( 3) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_End_Pointer_MSK (0x00070000) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_End_Pointer_MAX (0x00000007) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_End_Pointer_DEF (0x00000007) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_Current_Pointer_OFF (24) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_Current_Pointer_WID ( 3) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_Current_Pointer_MSK (0x07000000) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_Current_Pointer_MAX (0x00000007) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_Current_Pointer_DEF (0x00000000) + +#define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_CTRL_REG (0x00004DA0) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux0_Control_OFF ( 0) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux0_Control_WID ( 2) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux0_Control_MSK (0x00000003) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux0_Control_MAX (0x00000003) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux0_Control_DEF (0x00000001) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux1_Control_OFF ( 4) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux1_Control_WID ( 2) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux1_Control_MSK (0x00000030) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux1_Control_MAX (0x00000003) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux1_Control_DEF (0x00000001) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux2_Control_OFF ( 8) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux2_Control_WID ( 2) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux2_Control_MSK (0x00000300) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux2_Control_MAX (0x00000003) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux2_Control_DEF (0x00000001) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux0_Control_OFF ( 16) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux0_Control_WID ( 2) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux0_Control_MSK (0x00030000) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux0_Control_MAX (0x00000003) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux0_Control_DEF (0x00000001) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux1_Control_OFF ( 20) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux1_Control_WID ( 2) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux1_Control_MSK (0x00300000) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux1_Control_MAX (0x00000003) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux1_Control_DEF (0x00000001) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux2_Control_OFF ( 24) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux2_Control_WID ( 2) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux2_Control_MSK (0x03000000) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux2_Control_MAX (0x00000003) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux2_Control_DEF (0x00000001) + +#define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_PB_0_REG (0x00004DA4) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_PB_0_Pattern_Buffer_OFF ( 0) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_PB_0_Pattern_Buffer_WID (16) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_PB_0_Pattern_Buffer_MSK (0x0000FFFF) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_PB_0_Pattern_Buffer_MAX (0x0000FFFF) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_PB_0_Pattern_Buffer_DEF (0x00000000) + +#define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_PB_1_REG (0x00004DA8) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_PB_1_Pattern_Buffer_OFF ( 0) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_PB_1_Pattern_Buffer_WID (16) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_PB_1_Pattern_Buffer_MSK (0x0000FFFF) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_PB_1_Pattern_Buffer_MAX (0x0000FFFF) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_PB_1_Pattern_Buffer_DEF (0x00000000) + +#define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_PB_2_REG (0x00004DAC) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_PB_2_Pattern_Buffer_OFF ( 0) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_PB_2_Pattern_Buffer_WID (16) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_PB_2_Pattern_Buffer_MSK (0x0000FFFF) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_PB_2_Pattern_Buffer_MAX (0x0000FFFF) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_PB_2_Pattern_Buffer_DEF (0x00000000) + +#define MCSCHEDS_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_REG (0x00004DB0) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_L_data_select_OFF ( 0) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_L_data_select_WID ( 1) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_L_data_select_MSK (0x00000001) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_L_data_select_MAX (0x00000001) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_L_data_select_DEF (0x00000000) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_Enable_Sweep_Frequency_OFF ( 1) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_Enable_Sweep_Frequency_WID ( 1) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_Enable_Sweep_Frequency_MSK (0x00000002) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_Enable_Sweep_Frequency_MAX (0x00000001) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_Enable_Sweep_Frequency_DEF (0x00000000) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_L_counter_OFF ( 8) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_L_counter_WID ( 8) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_L_counter_MSK (0x0000FF00) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_L_counter_MAX (0x000000FF) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_L_counter_DEF (0x00000001) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_M_counter_OFF (16) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_M_counter_WID ( 8) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_M_counter_MSK (0x00FF0000) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_M_counter_MAX (0x000000FF) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_M_counter_DEF (0x00000001) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_N_counter_OFF (24) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_N_counter_WID ( 8) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_N_counter_MSK (0xFF000000) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_N_counter_MAX (0x000000FF) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_N_counter_DEF (0x00000001) + +#define MCSCHEDS_CR_REUT_CH_PAT_CADB_WRITE_POINTER_REG (0x00004DBC) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_WRITE_POINTER_CADB_Write_Pointer_OFF ( 0) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_WRITE_POINTER_CADB_Write_Pointer_WID ( 3) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_WRITE_POINTER_CADB_Write_Pointer_MSK (0x00000007) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_WRITE_POINTER_CADB_Write_Pointer_MAX (0x00000007) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_WRITE_POINTER_CADB_Write_Pointer_DEF (0x00000000) + +#define MCSCHEDS_CR_REUT_CH_PAT_CADB_PROG_REG (0x00004DC0) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Address_OFF ( 0) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Address_WID (16) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Address_MSK (0x0000FFFF) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Address_MAX (0x0000FFFF) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Address_DEF (0x00000000) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Bank_OFF (24) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Bank_WID ( 3) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Bank_MSK (0x07000000) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Bank_MAX (0x00000007) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Bank_DEF (0x00000000) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_CS_OFF (32) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_CS_WID ( 4) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_CS_MSK (0xF00000000) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_CS_MAX (0x0000000F) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_CS_DEF (0x00000000) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Control_OFF (40) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Control_WID ( 3) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Control_MSK (0x70000000000) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Control_MAX (0x00000007) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Control_DEF (0x00000000) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_ODT_OFF (48) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_ODT_WID ( 4) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_ODT_MSK (0xF000000000000) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_ODT_MAX (0x0000000F) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_ODT_DEF (0x00000000) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_CKE_OFF (56) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_CKE_WID ( 4) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_CKE_MSK (0xF00000000000000) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_CKE_MAX (0x0000000F) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_CKE_DEF (0x00000000) + +#define MCSCHEDS_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_0_REG (0x00004DC8) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_0_Pattern_Buffer_OFF ( 0) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_0_Pattern_Buffer_WID (16) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_0_Pattern_Buffer_MSK (0x0000FFFF) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_0_Pattern_Buffer_MAX (0x0000FFFF) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_0_Pattern_Buffer_DEF (0x00000000) + +#define MCSCHEDS_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_1_REG (0x00004DCC) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_1_Pattern_Buffer_OFF ( 0) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_1_Pattern_Buffer_WID (16) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_1_Pattern_Buffer_MSK (0x0000FFFF) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_1_Pattern_Buffer_MAX (0x0000FFFF) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_1_Pattern_Buffer_DEF (0x00000000) + +#define MCSCHEDS_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_2_REG (0x00004DD0) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_2_Pattern_Buffer_OFF ( 0) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_2_Pattern_Buffer_WID (16) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_2_Pattern_Buffer_MSK (0x0000FFFF) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_2_Pattern_Buffer_MAX (0x0000FFFF) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_2_Pattern_Buffer_DEF (0x00000000) + +#define MCMNTS_CR_REUT_CH_PAT_WDB_CL_CTRL_REG (0x00004E00) + #define MCMNTS_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Increment_Rate_OFF ( 0) + #define MCMNTS_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Increment_Rate_WID ( 5) + #define MCMNTS_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Increment_Rate_MSK (0x0000001F) + #define MCMNTS_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Increment_Rate_MAX (0x0000001F) + #define MCMNTS_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Increment_Rate_DEF (0x00000000) + #define MCMNTS_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Increment_Scale_OFF ( 5) + #define MCMNTS_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Increment_Scale_WID ( 1) + #define MCMNTS_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Increment_Scale_MSK (0x00000020) + #define MCMNTS_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Increment_Scale_MAX (0x00000001) + #define MCMNTS_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Increment_Scale_DEF (0x00000000) + #define MCMNTS_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Start_Pointer_OFF ( 8) + #define MCMNTS_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Start_Pointer_WID ( 6) + #define MCMNTS_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Start_Pointer_MSK (0x00003F00) + #define MCMNTS_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Start_Pointer_MAX (0x0000003F) + #define MCMNTS_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Start_Pointer_DEF (0x00000000) + #define MCMNTS_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_End_Pointer_OFF (16) + #define MCMNTS_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_End_Pointer_WID ( 6) + #define MCMNTS_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_End_Pointer_MSK (0x003F0000) + #define MCMNTS_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_End_Pointer_MAX (0x0000003F) + #define MCMNTS_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_End_Pointer_DEF (0x0000003F) + +#define MCMNTS_CR_REUT_CH_MISC_REFRESH_CTRL_REG (0x00004E04) + #define MCMNTS_CR_REUT_CH_MISC_REFRESH_CTRL_Refresh_Rank_Mask_OFF ( 0) + #define MCMNTS_CR_REUT_CH_MISC_REFRESH_CTRL_Refresh_Rank_Mask_WID ( 4) + #define MCMNTS_CR_REUT_CH_MISC_REFRESH_CTRL_Refresh_Rank_Mask_MSK (0x0000000F) + #define MCMNTS_CR_REUT_CH_MISC_REFRESH_CTRL_Refresh_Rank_Mask_MAX (0x0000000F) + #define MCMNTS_CR_REUT_CH_MISC_REFRESH_CTRL_Refresh_Rank_Mask_DEF (0x00000000) + #define MCMNTS_CR_REUT_CH_MISC_REFRESH_CTRL_RefZQ_En_Start_Test_Sync_OFF ( 8) + #define MCMNTS_CR_REUT_CH_MISC_REFRESH_CTRL_RefZQ_En_Start_Test_Sync_WID ( 1) + #define MCMNTS_CR_REUT_CH_MISC_REFRESH_CTRL_RefZQ_En_Start_Test_Sync_MSK (0x00000100) + #define MCMNTS_CR_REUT_CH_MISC_REFRESH_CTRL_RefZQ_En_Start_Test_Sync_MAX (0x00000001) + #define MCMNTS_CR_REUT_CH_MISC_REFRESH_CTRL_RefZQ_En_Start_Test_Sync_DEF (0x00000000) + #define MCMNTS_CR_REUT_CH_MISC_REFRESH_CTRL_Panic_Refresh_Only_OFF (31) + #define MCMNTS_CR_REUT_CH_MISC_REFRESH_CTRL_Panic_Refresh_Only_WID ( 1) + #define MCMNTS_CR_REUT_CH_MISC_REFRESH_CTRL_Panic_Refresh_Only_MSK (0x80000000) + #define MCMNTS_CR_REUT_CH_MISC_REFRESH_CTRL_Panic_Refresh_Only_MAX (0x00000001) + #define MCMNTS_CR_REUT_CH_MISC_REFRESH_CTRL_Panic_Refresh_Only_DEF (0x00000000) + +#define MCMNTS_CR_REUT_CH_MISC_ZQ_CTRL_REG (0x00004E08) + #define MCMNTS_CR_REUT_CH_MISC_ZQ_CTRL_ZQ_Rank_Mask_OFF ( 0) + #define MCMNTS_CR_REUT_CH_MISC_ZQ_CTRL_ZQ_Rank_Mask_WID ( 4) + #define MCMNTS_CR_REUT_CH_MISC_ZQ_CTRL_ZQ_Rank_Mask_MSK (0x0000000F) + #define MCMNTS_CR_REUT_CH_MISC_ZQ_CTRL_ZQ_Rank_Mask_MAX (0x0000000F) + #define MCMNTS_CR_REUT_CH_MISC_ZQ_CTRL_ZQ_Rank_Mask_DEF (0x00000000) + #define MCMNTS_CR_REUT_CH_MISC_ZQ_CTRL_Always_Do_ZQ_OFF (31) + #define MCMNTS_CR_REUT_CH_MISC_ZQ_CTRL_Always_Do_ZQ_WID ( 1) + #define MCMNTS_CR_REUT_CH_MISC_ZQ_CTRL_Always_Do_ZQ_MSK (0x80000000) + #define MCMNTS_CR_REUT_CH_MISC_ZQ_CTRL_Always_Do_ZQ_MAX (0x00000001) + #define MCMNTS_CR_REUT_CH_MISC_ZQ_CTRL_Always_Do_ZQ_DEF (0x00000000) + +#define MCMNTS_CR_LPDDR_MR_PARAMS_REG (0x00004E10) + #define MCMNTS_CR_LPDDR_MR_PARAMS_Rank_0_x32_OFF ( 0) + #define MCMNTS_CR_LPDDR_MR_PARAMS_Rank_0_x32_WID ( 1) + #define MCMNTS_CR_LPDDR_MR_PARAMS_Rank_0_x32_MSK (0x00000001) + #define MCMNTS_CR_LPDDR_MR_PARAMS_Rank_0_x32_MAX (0x00000001) + #define MCMNTS_CR_LPDDR_MR_PARAMS_Rank_0_x32_DEF (0x00000000) + #define MCMNTS_CR_LPDDR_MR_PARAMS_Rank_1_x32_OFF ( 1) + #define MCMNTS_CR_LPDDR_MR_PARAMS_Rank_1_x32_WID ( 1) + #define MCMNTS_CR_LPDDR_MR_PARAMS_Rank_1_x32_MSK (0x00000002) + #define MCMNTS_CR_LPDDR_MR_PARAMS_Rank_1_x32_MAX (0x00000001) + #define MCMNTS_CR_LPDDR_MR_PARAMS_Rank_1_x32_DEF (0x00000000) + #define MCMNTS_CR_LPDDR_MR_PARAMS_Rank_2_x32_OFF ( 2) + #define MCMNTS_CR_LPDDR_MR_PARAMS_Rank_2_x32_WID ( 1) + #define MCMNTS_CR_LPDDR_MR_PARAMS_Rank_2_x32_MSK (0x00000004) + #define MCMNTS_CR_LPDDR_MR_PARAMS_Rank_2_x32_MAX (0x00000001) + #define MCMNTS_CR_LPDDR_MR_PARAMS_Rank_2_x32_DEF (0x00000000) + #define MCMNTS_CR_LPDDR_MR_PARAMS_Rank_3_x32_OFF ( 3) + #define MCMNTS_CR_LPDDR_MR_PARAMS_Rank_3_x32_WID ( 1) + #define MCMNTS_CR_LPDDR_MR_PARAMS_Rank_3_x32_MSK (0x00000008) + #define MCMNTS_CR_LPDDR_MR_PARAMS_Rank_3_x32_MAX (0x00000001) + #define MCMNTS_CR_LPDDR_MR_PARAMS_Rank_3_x32_DEF (0x00000000) + #define MCMNTS_CR_LPDDR_MR_PARAMS_LPDDR2_OFF ( 4) + #define MCMNTS_CR_LPDDR_MR_PARAMS_LPDDR2_WID ( 1) + #define MCMNTS_CR_LPDDR_MR_PARAMS_LPDDR2_MSK (0x00000010) + #define MCMNTS_CR_LPDDR_MR_PARAMS_LPDDR2_MAX (0x00000001) + #define MCMNTS_CR_LPDDR_MR_PARAMS_LPDDR2_DEF (0x00000000) + #define MCMNTS_CR_LPDDR_MR_PARAMS_MR4_PERIOD_OFF ( 8) + #define MCMNTS_CR_LPDDR_MR_PARAMS_MR4_PERIOD_WID (16) + #define MCMNTS_CR_LPDDR_MR_PARAMS_MR4_PERIOD_MSK (0x00FFFF00) + #define MCMNTS_CR_LPDDR_MR_PARAMS_MR4_PERIOD_MAX (0x0000FFFF) + #define MCMNTS_CR_LPDDR_MR_PARAMS_MR4_PERIOD_DEF (0x00000000) + +#define MCMNTS_CR_LPDDR_MR_COMMAND_REG (0x00004E14) + #define MCMNTS_CR_LPDDR_MR_COMMAND_Address_OFF ( 0) + #define MCMNTS_CR_LPDDR_MR_COMMAND_Address_WID ( 8) + #define MCMNTS_CR_LPDDR_MR_COMMAND_Address_MSK (0x000000FF) + #define MCMNTS_CR_LPDDR_MR_COMMAND_Address_MAX (0x000000FF) + #define MCMNTS_CR_LPDDR_MR_COMMAND_Address_DEF (0x00000000) + #define MCMNTS_CR_LPDDR_MR_COMMAND_Data_OFF ( 8) + #define MCMNTS_CR_LPDDR_MR_COMMAND_Data_WID ( 8) + #define MCMNTS_CR_LPDDR_MR_COMMAND_Data_MSK (0x0000FF00) + #define MCMNTS_CR_LPDDR_MR_COMMAND_Data_MAX (0x000000FF) + #define MCMNTS_CR_LPDDR_MR_COMMAND_Data_DEF (0x00000000) + #define MCMNTS_CR_LPDDR_MR_COMMAND_Rank_OFF (16) + #define MCMNTS_CR_LPDDR_MR_COMMAND_Rank_WID ( 2) + #define MCMNTS_CR_LPDDR_MR_COMMAND_Rank_MSK (0x00030000) + #define MCMNTS_CR_LPDDR_MR_COMMAND_Rank_MAX (0x00000003) + #define MCMNTS_CR_LPDDR_MR_COMMAND_Rank_DEF (0x00000000) + #define MCMNTS_CR_LPDDR_MR_COMMAND_Write_OFF (18) + #define MCMNTS_CR_LPDDR_MR_COMMAND_Write_WID ( 1) + #define MCMNTS_CR_LPDDR_MR_COMMAND_Write_MSK (0x00040000) + #define MCMNTS_CR_LPDDR_MR_COMMAND_Write_MAX (0x00000001) + #define MCMNTS_CR_LPDDR_MR_COMMAND_Write_DEF (0x00000000) + #define MCMNTS_CR_LPDDR_MR_COMMAND_Init_MRW_OFF (19) + #define MCMNTS_CR_LPDDR_MR_COMMAND_Init_MRW_WID ( 1) + #define MCMNTS_CR_LPDDR_MR_COMMAND_Init_MRW_MSK (0x00080000) + #define MCMNTS_CR_LPDDR_MR_COMMAND_Init_MRW_MAX (0x00000001) + #define MCMNTS_CR_LPDDR_MR_COMMAND_Init_MRW_DEF (0x00000000) + #define MCMNTS_CR_LPDDR_MR_COMMAND_Busy_OFF (31) + #define MCMNTS_CR_LPDDR_MR_COMMAND_Busy_WID ( 1) + #define MCMNTS_CR_LPDDR_MR_COMMAND_Busy_MSK (0x80000000) + #define MCMNTS_CR_LPDDR_MR_COMMAND_Busy_MAX (0x00000001) + #define MCMNTS_CR_LPDDR_MR_COMMAND_Busy_DEF (0x00000000) + +#define MCMNTS_CR_LPDDR_MR_RESULT_REG (0x00004E18) + #define MCMNTS_CR_LPDDR_MR_RESULT_Device_0_OFF ( 0) + #define MCMNTS_CR_LPDDR_MR_RESULT_Device_0_WID ( 8) + #define MCMNTS_CR_LPDDR_MR_RESULT_Device_0_MSK (0x000000FF) + #define MCMNTS_CR_LPDDR_MR_RESULT_Device_0_MAX (0x000000FF) + #define MCMNTS_CR_LPDDR_MR_RESULT_Device_0_DEF (0x00000000) + #define MCMNTS_CR_LPDDR_MR_RESULT_Device_1_OFF ( 8) + #define MCMNTS_CR_LPDDR_MR_RESULT_Device_1_WID ( 8) + #define MCMNTS_CR_LPDDR_MR_RESULT_Device_1_MSK (0x0000FF00) + #define MCMNTS_CR_LPDDR_MR_RESULT_Device_1_MAX (0x000000FF) + #define MCMNTS_CR_LPDDR_MR_RESULT_Device_1_DEF (0x00000000) + #define MCMNTS_CR_LPDDR_MR_RESULT_Device_2_OFF (16) + #define MCMNTS_CR_LPDDR_MR_RESULT_Device_2_WID ( 8) + #define MCMNTS_CR_LPDDR_MR_RESULT_Device_2_MSK (0x00FF0000) + #define MCMNTS_CR_LPDDR_MR_RESULT_Device_2_MAX (0x000000FF) + #define MCMNTS_CR_LPDDR_MR_RESULT_Device_2_DEF (0x00000000) + #define MCMNTS_CR_LPDDR_MR_RESULT_Device_3_OFF (24) + #define MCMNTS_CR_LPDDR_MR_RESULT_Device_3_WID ( 8) + #define MCMNTS_CR_LPDDR_MR_RESULT_Device_3_MSK (0xFF000000) + #define MCMNTS_CR_LPDDR_MR_RESULT_Device_3_MAX (0x000000FF) + #define MCMNTS_CR_LPDDR_MR_RESULT_Device_3_DEF (0x00000000) + +#define MCMNTS_CR_LPDDR_MR4_RANK_TEMPERATURE_REG (0x00004E1C) + #define MCMNTS_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_0_OFF ( 0) + #define MCMNTS_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_0_WID ( 3) + #define MCMNTS_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_0_MSK (0x00000007) + #define MCMNTS_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_0_MAX (0x00000007) + #define MCMNTS_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_0_DEF (0x00000003) + #define MCMNTS_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_1_OFF ( 8) + #define MCMNTS_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_1_WID ( 3) + #define MCMNTS_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_1_MSK (0x00000700) + #define MCMNTS_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_1_MAX (0x00000007) + #define MCMNTS_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_1_DEF (0x00000003) + #define MCMNTS_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_2_OFF (16) + #define MCMNTS_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_2_WID ( 3) + #define MCMNTS_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_2_MSK (0x00070000) + #define MCMNTS_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_2_MAX (0x00000007) + #define MCMNTS_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_2_DEF (0x00000003) + #define MCMNTS_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_3_OFF (24) + #define MCMNTS_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_3_WID ( 3) + #define MCMNTS_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_3_MSK (0x07000000) + #define MCMNTS_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_3_MAX (0x00000007) + #define MCMNTS_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_3_DEF (0x00000003) + +#define MCMNTS_CR_DESWIZZLE_LOW_REG (0x00004E20) + #define MCMNTS_CR_DESWIZZLE_LOW_Bit_0_OFF ( 0) + #define MCMNTS_CR_DESWIZZLE_LOW_Bit_0_WID ( 3) + #define MCMNTS_CR_DESWIZZLE_LOW_Bit_0_MSK (0x00000007) + #define MCMNTS_CR_DESWIZZLE_LOW_Bit_0_MAX (0x00000007) + #define MCMNTS_CR_DESWIZZLE_LOW_Bit_0_DEF (0x00000000) + #define MCMNTS_CR_DESWIZZLE_LOW_Bit_1_OFF ( 4) + #define MCMNTS_CR_DESWIZZLE_LOW_Bit_1_WID ( 3) + #define MCMNTS_CR_DESWIZZLE_LOW_Bit_1_MSK (0x00000070) + #define MCMNTS_CR_DESWIZZLE_LOW_Bit_1_MAX (0x00000007) + #define MCMNTS_CR_DESWIZZLE_LOW_Bit_1_DEF (0x00000001) + #define MCMNTS_CR_DESWIZZLE_LOW_Bit_2_OFF ( 8) + #define MCMNTS_CR_DESWIZZLE_LOW_Bit_2_WID ( 3) + #define MCMNTS_CR_DESWIZZLE_LOW_Bit_2_MSK (0x00000700) + #define MCMNTS_CR_DESWIZZLE_LOW_Bit_2_MAX (0x00000007) + #define MCMNTS_CR_DESWIZZLE_LOW_Bit_2_DEF (0x00000002) + #define MCMNTS_CR_DESWIZZLE_LOW_Bit_16_OFF (12) + #define MCMNTS_CR_DESWIZZLE_LOW_Bit_16_WID ( 3) + #define MCMNTS_CR_DESWIZZLE_LOW_Bit_16_MSK (0x00007000) + #define MCMNTS_CR_DESWIZZLE_LOW_Bit_16_MAX (0x00000007) + #define MCMNTS_CR_DESWIZZLE_LOW_Bit_16_DEF (0x00000000) + #define MCMNTS_CR_DESWIZZLE_LOW_Bit_17_OFF (16) + #define MCMNTS_CR_DESWIZZLE_LOW_Bit_17_WID ( 3) + #define MCMNTS_CR_DESWIZZLE_LOW_Bit_17_MSK (0x00070000) + #define MCMNTS_CR_DESWIZZLE_LOW_Bit_17_MAX (0x00000007) + #define MCMNTS_CR_DESWIZZLE_LOW_Bit_17_DEF (0x00000001) + #define MCMNTS_CR_DESWIZZLE_LOW_Bit_18_OFF (20) + #define MCMNTS_CR_DESWIZZLE_LOW_Bit_18_WID ( 3) + #define MCMNTS_CR_DESWIZZLE_LOW_Bit_18_MSK (0x00700000) + #define MCMNTS_CR_DESWIZZLE_LOW_Bit_18_MAX (0x00000007) + #define MCMNTS_CR_DESWIZZLE_LOW_Bit_18_DEF (0x00000002) + #define MCMNTS_CR_DESWIZZLE_LOW_Byte_0_OFF (24) + #define MCMNTS_CR_DESWIZZLE_LOW_Byte_0_WID ( 3) + #define MCMNTS_CR_DESWIZZLE_LOW_Byte_0_MSK (0x07000000) + #define MCMNTS_CR_DESWIZZLE_LOW_Byte_0_MAX (0x00000007) + #define MCMNTS_CR_DESWIZZLE_LOW_Byte_0_DEF (0x00000000) + #define MCMNTS_CR_DESWIZZLE_LOW_Byte_2_OFF (28) + #define MCMNTS_CR_DESWIZZLE_LOW_Byte_2_WID ( 3) + #define MCMNTS_CR_DESWIZZLE_LOW_Byte_2_MSK (0x70000000) + #define MCMNTS_CR_DESWIZZLE_LOW_Byte_2_MAX (0x00000007) + #define MCMNTS_CR_DESWIZZLE_LOW_Byte_2_DEF (0x00000002) + +#define MCMNTS_CR_DESWIZZLE_HIGH_REG (0x00004E24) + #define MCMNTS_CR_DESWIZZLE_HIGH_Bit_32_OFF ( 0) + #define MCMNTS_CR_DESWIZZLE_HIGH_Bit_32_WID ( 3) + #define MCMNTS_CR_DESWIZZLE_HIGH_Bit_32_MSK (0x00000007) + #define MCMNTS_CR_DESWIZZLE_HIGH_Bit_32_MAX (0x00000007) + #define MCMNTS_CR_DESWIZZLE_HIGH_Bit_32_DEF (0x00000000) + #define MCMNTS_CR_DESWIZZLE_HIGH_Bit_33_OFF ( 4) + #define MCMNTS_CR_DESWIZZLE_HIGH_Bit_33_WID ( 3) + #define MCMNTS_CR_DESWIZZLE_HIGH_Bit_33_MSK (0x00000070) + #define MCMNTS_CR_DESWIZZLE_HIGH_Bit_33_MAX (0x00000007) + #define MCMNTS_CR_DESWIZZLE_HIGH_Bit_33_DEF (0x00000001) + #define MCMNTS_CR_DESWIZZLE_HIGH_Bit_34_OFF ( 8) + #define MCMNTS_CR_DESWIZZLE_HIGH_Bit_34_WID ( 3) + #define MCMNTS_CR_DESWIZZLE_HIGH_Bit_34_MSK (0x00000700) + #define MCMNTS_CR_DESWIZZLE_HIGH_Bit_34_MAX (0x00000007) + #define MCMNTS_CR_DESWIZZLE_HIGH_Bit_34_DEF (0x00000002) + #define MCMNTS_CR_DESWIZZLE_HIGH_Bit_48_OFF (12) + #define MCMNTS_CR_DESWIZZLE_HIGH_Bit_48_WID ( 3) + #define MCMNTS_CR_DESWIZZLE_HIGH_Bit_48_MSK (0x00007000) + #define MCMNTS_CR_DESWIZZLE_HIGH_Bit_48_MAX (0x00000007) + #define MCMNTS_CR_DESWIZZLE_HIGH_Bit_48_DEF (0x00000000) + #define MCMNTS_CR_DESWIZZLE_HIGH_Bit_49_OFF (16) + #define MCMNTS_CR_DESWIZZLE_HIGH_Bit_49_WID ( 3) + #define MCMNTS_CR_DESWIZZLE_HIGH_Bit_49_MSK (0x00070000) + #define MCMNTS_CR_DESWIZZLE_HIGH_Bit_49_MAX (0x00000007) + #define MCMNTS_CR_DESWIZZLE_HIGH_Bit_49_DEF (0x00000001) + #define MCMNTS_CR_DESWIZZLE_HIGH_Bit_50_OFF (20) + #define MCMNTS_CR_DESWIZZLE_HIGH_Bit_50_WID ( 3) + #define MCMNTS_CR_DESWIZZLE_HIGH_Bit_50_MSK (0x00700000) + #define MCMNTS_CR_DESWIZZLE_HIGH_Bit_50_MAX (0x00000007) + #define MCMNTS_CR_DESWIZZLE_HIGH_Bit_50_DEF (0x00000002) + #define MCMNTS_CR_DESWIZZLE_HIGH_Byte_4_OFF (24) + #define MCMNTS_CR_DESWIZZLE_HIGH_Byte_4_WID ( 3) + #define MCMNTS_CR_DESWIZZLE_HIGH_Byte_4_MSK (0x07000000) + #define MCMNTS_CR_DESWIZZLE_HIGH_Byte_4_MAX (0x00000007) + #define MCMNTS_CR_DESWIZZLE_HIGH_Byte_4_DEF (0x00000004) + #define MCMNTS_CR_DESWIZZLE_HIGH_Byte_6_OFF (28) + #define MCMNTS_CR_DESWIZZLE_HIGH_Byte_6_WID ( 3) + #define MCMNTS_CR_DESWIZZLE_HIGH_Byte_6_MSK (0x70000000) + #define MCMNTS_CR_DESWIZZLE_HIGH_Byte_6_MAX (0x00000007) + #define MCMNTS_CR_DESWIZZLE_HIGH_Byte_6_DEF (0x00000006) + +#define MCMNTS_CR_MC_REFRESH_STAGGER_REG (0x00004E8C) + #define MCMNTS_CR_MC_REFRESH_STAGGER_Ref_Interval_OFF ( 0) + #define MCMNTS_CR_MC_REFRESH_STAGGER_Ref_Interval_WID (11) + #define MCMNTS_CR_MC_REFRESH_STAGGER_Ref_Interval_MSK (0x000007FF) + #define MCMNTS_CR_MC_REFRESH_STAGGER_Ref_Interval_MAX (0x000007FF) + #define MCMNTS_CR_MC_REFRESH_STAGGER_Ref_Interval_DEF (0x00000000) + #define MCMNTS_CR_MC_REFRESH_STAGGER_Ref_Stagger_En_OFF (11) + #define MCMNTS_CR_MC_REFRESH_STAGGER_Ref_Stagger_En_WID ( 1) + #define MCMNTS_CR_MC_REFRESH_STAGGER_Ref_Stagger_En_MSK (0x00000800) + #define MCMNTS_CR_MC_REFRESH_STAGGER_Ref_Stagger_En_MAX (0x00000001) + #define MCMNTS_CR_MC_REFRESH_STAGGER_Ref_Stagger_En_DEF (0x00000000) + #define MCMNTS_CR_MC_REFRESH_STAGGER_Ref_Stagger_Mode_OFF (12) + #define MCMNTS_CR_MC_REFRESH_STAGGER_Ref_Stagger_Mode_WID ( 1) + #define MCMNTS_CR_MC_REFRESH_STAGGER_Ref_Stagger_Mode_MSK (0x00001000) + #define MCMNTS_CR_MC_REFRESH_STAGGER_Ref_Stagger_Mode_MAX (0x00000001) + #define MCMNTS_CR_MC_REFRESH_STAGGER_Ref_Stagger_Mode_DEF (0x00000000) + #define MCMNTS_CR_MC_REFRESH_STAGGER_Disable_Stolen_Refresh_OFF (13) + #define MCMNTS_CR_MC_REFRESH_STAGGER_Disable_Stolen_Refresh_WID ( 1) + #define MCMNTS_CR_MC_REFRESH_STAGGER_Disable_Stolen_Refresh_MSK (0x00002000) + #define MCMNTS_CR_MC_REFRESH_STAGGER_Disable_Stolen_Refresh_MAX (0x00000001) + #define MCMNTS_CR_MC_REFRESH_STAGGER_Disable_Stolen_Refresh_DEF (0x00000000) + #define MCMNTS_CR_MC_REFRESH_STAGGER_En_Ref_Type_Display_OFF (14) + #define MCMNTS_CR_MC_REFRESH_STAGGER_En_Ref_Type_Display_WID ( 1) + #define MCMNTS_CR_MC_REFRESH_STAGGER_En_Ref_Type_Display_MSK (0x00004000) + #define MCMNTS_CR_MC_REFRESH_STAGGER_En_Ref_Type_Display_MAX (0x00000001) + #define MCMNTS_CR_MC_REFRESH_STAGGER_En_Ref_Type_Display_DEF (0x00000000) + +#define MCMNTS_CR_TC_ZQCAL_REG (0x00004E90) + #define MCMNTS_CR_TC_ZQCAL_ZQCS_period_OFF ( 0) + #define MCMNTS_CR_TC_ZQCAL_ZQCS_period_WID ( 8) + #define MCMNTS_CR_TC_ZQCAL_ZQCS_period_MSK (0x000000FF) + #define MCMNTS_CR_TC_ZQCAL_ZQCS_period_MAX (0x000000FF) + #define MCMNTS_CR_TC_ZQCAL_ZQCS_period_DEF (0x00000080) + #define MCMNTS_CR_TC_ZQCAL_tZQCS_OFF ( 8) + #define MCMNTS_CR_TC_ZQCAL_tZQCS_WID ( 8) + #define MCMNTS_CR_TC_ZQCAL_tZQCS_MSK (0x0000FF00) + #define MCMNTS_CR_TC_ZQCAL_tZQCS_MAX (0x000000FF) + #define MCMNTS_CR_TC_ZQCAL_tZQCS_DEF (0x00000040) + #define MCMNTS_CR_TC_ZQCAL_ZQCS_period_Ult_OFF ( 0) + #define MCMNTS_CR_TC_ZQCAL_ZQCS_period_Ult_WID (10) + #define MCMNTS_CR_TC_ZQCAL_ZQCS_period_Ult_MSK (0x000003FF) + #define MCMNTS_CR_TC_ZQCAL_ZQCS_period_Ult_MAX (0x000003FF) + #define MCMNTS_CR_TC_ZQCAL_ZQCS_period_Ult_DEF (0x00000080) + #define MCMNTS_CR_TC_ZQCAL_tZQCS_Ult_OFF (10) + #define MCMNTS_CR_TC_ZQCAL_tZQCS_Ult_WID (10) + #define MCMNTS_CR_TC_ZQCAL_tZQCS_Ult_MSK (0x000FFC00) + #define MCMNTS_CR_TC_ZQCAL_tZQCS_Ult_MAX (0x000003FF) + #define MCMNTS_CR_TC_ZQCAL_tZQCS_Ult_DEF (0x00000040) + +#define MCMNTS_CR_TC_RFP_REG (0x00004E94) + #define MCMNTS_CR_TC_RFP_OREF_RI_OFF ( 0) + #define MCMNTS_CR_TC_RFP_OREF_RI_WID ( 8) + #define MCMNTS_CR_TC_RFP_OREF_RI_MSK (0x000000FF) + #define MCMNTS_CR_TC_RFP_OREF_RI_MAX (0x000000FF) + #define MCMNTS_CR_TC_RFP_OREF_RI_DEF (0x0000000F) + #define MCMNTS_CR_TC_RFP_Refresh_HP_WM_OFF ( 8) + #define MCMNTS_CR_TC_RFP_Refresh_HP_WM_WID ( 4) + #define MCMNTS_CR_TC_RFP_Refresh_HP_WM_MSK (0x00000F00) + #define MCMNTS_CR_TC_RFP_Refresh_HP_WM_MAX (0x0000000F) + #define MCMNTS_CR_TC_RFP_Refresh_HP_WM_DEF (0x00000008) + #define MCMNTS_CR_TC_RFP_Refresh_panic_wm_OFF (12) + #define MCMNTS_CR_TC_RFP_Refresh_panic_wm_WID ( 4) + #define MCMNTS_CR_TC_RFP_Refresh_panic_wm_MSK (0x0000F000) + #define MCMNTS_CR_TC_RFP_Refresh_panic_wm_MAX (0x0000000F) + #define MCMNTS_CR_TC_RFP_Refresh_panic_wm_DEF (0x00000009) + +#define MCMNTS_CR_TC_RFTP_REG (0x00004E98) + #define MCMNTS_CR_TC_RFTP_tREFI_OFF ( 0) + #define MCMNTS_CR_TC_RFTP_tREFI_WID (16) + #define MCMNTS_CR_TC_RFTP_tREFI_MSK (0x0000FFFF) + #define MCMNTS_CR_TC_RFTP_tREFI_MAX (0x0000FFFF) + #define MCMNTS_CR_TC_RFTP_tREFI_DEF (0x00001004) + #define MCMNTS_CR_TC_RFTP_tRFC_OFF (16) + #define MCMNTS_CR_TC_RFTP_tRFC_WID ( 9) + #define MCMNTS_CR_TC_RFTP_tRFC_MSK (0x01FF0000) + #define MCMNTS_CR_TC_RFTP_tRFC_MAX (0x000001FF) + #define MCMNTS_CR_TC_RFTP_tRFC_DEF (0x000000B4) + #define MCMNTS_CR_TC_RFTP_tREFIx9_OFF (25) + #define MCMNTS_CR_TC_RFTP_tREFIx9_WID ( 7) + #define MCMNTS_CR_TC_RFTP_tREFIx9_MSK (0xFE000000) + #define MCMNTS_CR_TC_RFTP_tREFIx9_MAX (0x0000007F) + #define MCMNTS_CR_TC_RFTP_tREFIx9_DEF (0x00000023) + +#define MCMNTS_CR_TC_MR2_SHADDOW_REG (0x00004E9C) + #define MCMNTS_CR_TC_MR2_SHADDOW_MR2_sh_low_OFF ( 0) + #define MCMNTS_CR_TC_MR2_SHADDOW_MR2_sh_low_WID ( 6) + #define MCMNTS_CR_TC_MR2_SHADDOW_MR2_sh_low_MSK (0x0000003F) + #define MCMNTS_CR_TC_MR2_SHADDOW_MR2_sh_low_MAX (0x0000003F) + #define MCMNTS_CR_TC_MR2_SHADDOW_MR2_sh_low_DEF (0x00000000) + #define MCMNTS_CR_TC_MR2_SHADDOW_SRT_avail_OFF ( 6) + #define MCMNTS_CR_TC_MR2_SHADDOW_SRT_avail_WID ( 2) + #define MCMNTS_CR_TC_MR2_SHADDOW_SRT_avail_MSK (0x000000C0) + #define MCMNTS_CR_TC_MR2_SHADDOW_SRT_avail_MAX (0x00000003) + #define MCMNTS_CR_TC_MR2_SHADDOW_SRT_avail_DEF (0x00000000) + #define MCMNTS_CR_TC_MR2_SHADDOW_MR2_sh_high_OFF ( 8) + #define MCMNTS_CR_TC_MR2_SHADDOW_MR2_sh_high_WID ( 3) + #define MCMNTS_CR_TC_MR2_SHADDOW_MR2_sh_high_MSK (0x00000700) + #define MCMNTS_CR_TC_MR2_SHADDOW_MR2_sh_high_MAX (0x00000007) + #define MCMNTS_CR_TC_MR2_SHADDOW_MR2_sh_high_DEF (0x00000000) + #define MCMNTS_CR_TC_MR2_SHADDOW_Addr_bit_swizzle_OFF (14) + #define MCMNTS_CR_TC_MR2_SHADDOW_Addr_bit_swizzle_WID ( 2) + #define MCMNTS_CR_TC_MR2_SHADDOW_Addr_bit_swizzle_MSK (0x0000C000) + #define MCMNTS_CR_TC_MR2_SHADDOW_Addr_bit_swizzle_MAX (0x00000003) + #define MCMNTS_CR_TC_MR2_SHADDOW_Addr_bit_swizzle_DEF (0x00000000) + +#define MCMNTS_CR_MC_INIT_STATE_REG (0x00004EA0) + #define MCMNTS_CR_MC_INIT_STATE_Rank_occupancy_OFF ( 0) + #define MCMNTS_CR_MC_INIT_STATE_Rank_occupancy_WID ( 4) + #define MCMNTS_CR_MC_INIT_STATE_Rank_occupancy_MSK (0x0000000F) + #define MCMNTS_CR_MC_INIT_STATE_Rank_occupancy_MAX (0x0000000F) + #define MCMNTS_CR_MC_INIT_STATE_Rank_occupancy_DEF (0x0000000F) + +#define MCMNTS_CR_TC_SRFTP_REG (0x00004EA4) + #define MCMNTS_CR_TC_SRFTP_tXSDLL_OFF ( 0) + #define MCMNTS_CR_TC_SRFTP_tXSDLL_WID (12) + #define MCMNTS_CR_TC_SRFTP_tXSDLL_MSK (0x00000FFF) + #define MCMNTS_CR_TC_SRFTP_tXSDLL_MAX (0x00000FFF) + #define MCMNTS_CR_TC_SRFTP_tXSDLL_DEF (0x00000200) + #define MCMNTS_CR_TC_SRFTP_tXS_offset_OFF (12) + #define MCMNTS_CR_TC_SRFTP_tXS_offset_WID ( 4) + #define MCMNTS_CR_TC_SRFTP_tXS_offset_MSK (0x0000F000) + #define MCMNTS_CR_TC_SRFTP_tXS_offset_MAX (0x0000000F) + #define MCMNTS_CR_TC_SRFTP_tXS_offset_DEF (0x0000000B) + #define MCMNTS_CR_TC_SRFTP_tZQOPER_OFF (16) + #define MCMNTS_CR_TC_SRFTP_tZQOPER_WID (10) + #define MCMNTS_CR_TC_SRFTP_tZQOPER_MSK (0x03FF0000) + #define MCMNTS_CR_TC_SRFTP_tZQOPER_MAX (0x000003FF) + #define MCMNTS_CR_TC_SRFTP_tZQOPER_DEF (0x00000100) + #define MCMNTS_CR_TC_SRFTP_tMOD_OFF (28) + #define MCMNTS_CR_TC_SRFTP_tMOD_WID ( 4) + #define MCMNTS_CR_TC_SRFTP_tMOD_MSK (0xF0000000) + #define MCMNTS_CR_TC_SRFTP_tMOD_MAX (0x0000000F) + #define MCMNTS_CR_TC_SRFTP_tMOD_DEF (0x00000000) + +#define MCMNTS_CR_WDB_VISA_SEL_REG (0x00004EA8) + #define MCMNTS_CR_WDB_VISA_SEL_VISAByteSel_OFF ( 0) + #define MCMNTS_CR_WDB_VISA_SEL_VISAByteSel_WID ( 3) + #define MCMNTS_CR_WDB_VISA_SEL_VISAByteSel_MSK (0x00000007) + #define MCMNTS_CR_WDB_VISA_SEL_VISAByteSel_MAX (0x00000007) + #define MCMNTS_CR_WDB_VISA_SEL_VISAByteSel_DEF (0x00000000) + +#define MCMNTS_CR_DCLK_LDAT_PDAT_REG (0x00004EC0) + #define MCMNTS_CR_DCLK_LDAT_PDAT_FASTADDR_OFF ( 0) + #define MCMNTS_CR_DCLK_LDAT_PDAT_FASTADDR_WID (12) + #define MCMNTS_CR_DCLK_LDAT_PDAT_FASTADDR_MSK (0x00000FFF) + #define MCMNTS_CR_DCLK_LDAT_PDAT_FASTADDR_MAX (0x00000FFF) + #define MCMNTS_CR_DCLK_LDAT_PDAT_FASTADDR_DEF (0x00000000) + #define MCMNTS_CR_DCLK_LDAT_PDAT_ADDREN_OFF (16) + #define MCMNTS_CR_DCLK_LDAT_PDAT_ADDREN_WID ( 1) + #define MCMNTS_CR_DCLK_LDAT_PDAT_ADDREN_MSK (0x00010000) + #define MCMNTS_CR_DCLK_LDAT_PDAT_ADDREN_MAX (0x00000001) + #define MCMNTS_CR_DCLK_LDAT_PDAT_ADDREN_DEF (0x00000000) + #define MCMNTS_CR_DCLK_LDAT_PDAT_SEQEN_OFF (17) + #define MCMNTS_CR_DCLK_LDAT_PDAT_SEQEN_WID ( 1) + #define MCMNTS_CR_DCLK_LDAT_PDAT_SEQEN_MSK (0x00020000) + #define MCMNTS_CR_DCLK_LDAT_PDAT_SEQEN_MAX (0x00000001) + #define MCMNTS_CR_DCLK_LDAT_PDAT_SEQEN_DEF (0x00000000) + #define MCMNTS_CR_DCLK_LDAT_PDAT_POL0_OFF (18) + #define MCMNTS_CR_DCLK_LDAT_PDAT_POL0_WID ( 1) + #define MCMNTS_CR_DCLK_LDAT_PDAT_POL0_MSK (0x00040000) + #define MCMNTS_CR_DCLK_LDAT_PDAT_POL0_MAX (0x00000001) + #define MCMNTS_CR_DCLK_LDAT_PDAT_POL0_DEF (0x00000000) + #define MCMNTS_CR_DCLK_LDAT_PDAT_POL1_OFF (19) + #define MCMNTS_CR_DCLK_LDAT_PDAT_POL1_WID ( 1) + #define MCMNTS_CR_DCLK_LDAT_PDAT_POL1_MSK (0x00080000) + #define MCMNTS_CR_DCLK_LDAT_PDAT_POL1_MAX (0x00000001) + #define MCMNTS_CR_DCLK_LDAT_PDAT_POL1_DEF (0x00000000) + #define MCMNTS_CR_DCLK_LDAT_PDAT_CMDA_OFF (20) + #define MCMNTS_CR_DCLK_LDAT_PDAT_CMDA_WID ( 4) + #define MCMNTS_CR_DCLK_LDAT_PDAT_CMDA_MSK (0x00F00000) + #define MCMNTS_CR_DCLK_LDAT_PDAT_CMDA_MAX (0x0000000F) + #define MCMNTS_CR_DCLK_LDAT_PDAT_CMDA_DEF (0x00000000) + #define MCMNTS_CR_DCLK_LDAT_PDAT_CMDB_OFF (24) + #define MCMNTS_CR_DCLK_LDAT_PDAT_CMDB_WID ( 4) + #define MCMNTS_CR_DCLK_LDAT_PDAT_CMDB_MSK (0x0F000000) + #define MCMNTS_CR_DCLK_LDAT_PDAT_CMDB_MAX (0x0000000F) + #define MCMNTS_CR_DCLK_LDAT_PDAT_CMDB_DEF (0x00000000) + #define MCMNTS_CR_DCLK_LDAT_PDAT_CMDC_OFF (28) + #define MCMNTS_CR_DCLK_LDAT_PDAT_CMDC_WID ( 4) + #define MCMNTS_CR_DCLK_LDAT_PDAT_CMDC_MSK (0xF0000000) + #define MCMNTS_CR_DCLK_LDAT_PDAT_CMDC_MAX (0x0000000F) + #define MCMNTS_CR_DCLK_LDAT_PDAT_CMDC_DEF (0x00000000) + +#define MCMNTS_CR_DCLK_LDAT_SDAT_REG (0x00004EC4) + #define MCMNTS_CR_DCLK_LDAT_SDAT_BANKSEL_OFF ( 0) + #define MCMNTS_CR_DCLK_LDAT_SDAT_BANKSEL_WID ( 4) + #define MCMNTS_CR_DCLK_LDAT_SDAT_BANKSEL_MSK (0x0000000F) + #define MCMNTS_CR_DCLK_LDAT_SDAT_BANKSEL_MAX (0x0000000F) + #define MCMNTS_CR_DCLK_LDAT_SDAT_BANKSEL_DEF (0x00000000) + #define MCMNTS_CR_DCLK_LDAT_SDAT_ARRAYSEL_OFF ( 5) + #define MCMNTS_CR_DCLK_LDAT_SDAT_ARRAYSEL_WID ( 5) + #define MCMNTS_CR_DCLK_LDAT_SDAT_ARRAYSEL_MSK (0x000003E0) + #define MCMNTS_CR_DCLK_LDAT_SDAT_ARRAYSEL_MAX (0x0000001F) + #define MCMNTS_CR_DCLK_LDAT_SDAT_ARRAYSEL_DEF (0x00000000) + #define MCMNTS_CR_DCLK_LDAT_SDAT_CMP_OFF (10) + #define MCMNTS_CR_DCLK_LDAT_SDAT_CMP_WID ( 1) + #define MCMNTS_CR_DCLK_LDAT_SDAT_CMP_MSK (0x00000400) + #define MCMNTS_CR_DCLK_LDAT_SDAT_CMP_MAX (0x00000001) + #define MCMNTS_CR_DCLK_LDAT_SDAT_CMP_DEF (0x00000000) + #define MCMNTS_CR_DCLK_LDAT_SDAT_REP_OFF (11) + #define MCMNTS_CR_DCLK_LDAT_SDAT_REP_WID ( 1) + #define MCMNTS_CR_DCLK_LDAT_SDAT_REP_MSK (0x00000800) + #define MCMNTS_CR_DCLK_LDAT_SDAT_REP_MAX (0x00000001) + #define MCMNTS_CR_DCLK_LDAT_SDAT_REP_DEF (0x00000000) + #define MCMNTS_CR_DCLK_LDAT_SDAT_DWORD_OFF (12) + #define MCMNTS_CR_DCLK_LDAT_SDAT_DWORD_WID ( 4) + #define MCMNTS_CR_DCLK_LDAT_SDAT_DWORD_MSK (0x0000F000) + #define MCMNTS_CR_DCLK_LDAT_SDAT_DWORD_MAX (0x0000000F) + #define MCMNTS_CR_DCLK_LDAT_SDAT_DWORD_DEF (0x00000000) + #define MCMNTS_CR_DCLK_LDAT_SDAT_MODE_OFF (16) + #define MCMNTS_CR_DCLK_LDAT_SDAT_MODE_WID ( 2) + #define MCMNTS_CR_DCLK_LDAT_SDAT_MODE_MSK (0x00030000) + #define MCMNTS_CR_DCLK_LDAT_SDAT_MODE_MAX (0x00000003) + #define MCMNTS_CR_DCLK_LDAT_SDAT_MODE_DEF (0x00000000) + #define MCMNTS_CR_DCLK_LDAT_SDAT_MPMAP_OFF (18) + #define MCMNTS_CR_DCLK_LDAT_SDAT_MPMAP_WID ( 6) + #define MCMNTS_CR_DCLK_LDAT_SDAT_MPMAP_MSK (0x00FC0000) + #define MCMNTS_CR_DCLK_LDAT_SDAT_MPMAP_MAX (0x0000003F) + #define MCMNTS_CR_DCLK_LDAT_SDAT_MPMAP_DEF (0x00000000) + #define MCMNTS_CR_DCLK_LDAT_SDAT_MPBOFFSET_OFF (24) + #define MCMNTS_CR_DCLK_LDAT_SDAT_MPBOFFSET_WID ( 4) + #define MCMNTS_CR_DCLK_LDAT_SDAT_MPBOFFSET_MSK (0x0F000000) + #define MCMNTS_CR_DCLK_LDAT_SDAT_MPBOFFSET_MAX (0x0000000F) + #define MCMNTS_CR_DCLK_LDAT_SDAT_MPBOFFSET_DEF (0x00000000) + #define MCMNTS_CR_DCLK_LDAT_SDAT_STAGE_EN_OFF (28) + #define MCMNTS_CR_DCLK_LDAT_SDAT_STAGE_EN_WID ( 1) + #define MCMNTS_CR_DCLK_LDAT_SDAT_STAGE_EN_MSK (0x10000000) + #define MCMNTS_CR_DCLK_LDAT_SDAT_STAGE_EN_MAX (0x00000001) + #define MCMNTS_CR_DCLK_LDAT_SDAT_STAGE_EN_DEF (0x00000000) + #define MCMNTS_CR_DCLK_LDAT_SDAT_SHADOW_OFF (29) + #define MCMNTS_CR_DCLK_LDAT_SDAT_SHADOW_WID ( 2) + #define MCMNTS_CR_DCLK_LDAT_SDAT_SHADOW_MSK (0x60000000) + #define MCMNTS_CR_DCLK_LDAT_SDAT_SHADOW_MAX (0x00000003) + #define MCMNTS_CR_DCLK_LDAT_SDAT_SHADOW_DEF (0x00000000) + +#define MCMNTS_CR_DCLK_LDAT_DATAOUT_REG (0x00004EC8) + #define MCMNTS_CR_DCLK_LDAT_DATAOUT_DATOUT_OFF ( 0) + #define MCMNTS_CR_DCLK_LDAT_DATAOUT_DATOUT_WID (32) + #define MCMNTS_CR_DCLK_LDAT_DATAOUT_DATOUT_MSK (0xFFFFFFFF) + #define MCMNTS_CR_DCLK_LDAT_DATAOUT_DATOUT_MAX (0xFFFFFFFF) + #define MCMNTS_CR_DCLK_LDAT_DATAOUT_DATOUT_DEF (0x00000000) + +#define MCMNTS_CR_DCLK_LDAT_DATAIN_0_REG (0x00004ECC) + #define MCMNTS_CR_DCLK_LDAT_DATAIN_0_DATIN_OFF ( 0) + #define MCMNTS_CR_DCLK_LDAT_DATAIN_0_DATIN_WID (32) + #define MCMNTS_CR_DCLK_LDAT_DATAIN_0_DATIN_MSK (0xFFFFFFFF) + #define MCMNTS_CR_DCLK_LDAT_DATAIN_0_DATIN_MAX (0xFFFFFFFF) + #define MCMNTS_CR_DCLK_LDAT_DATAIN_0_DATIN_DEF (0x00000000) + +#define MCMNTS_CR_QCLK_LDAT_PDAT_REG (0x00004ED0) + #define MCMNTS_CR_QCLK_LDAT_PDAT_FASTADDR_OFF ( 0) + #define MCMNTS_CR_QCLK_LDAT_PDAT_FASTADDR_WID (12) + #define MCMNTS_CR_QCLK_LDAT_PDAT_FASTADDR_MSK (0x00000FFF) + #define MCMNTS_CR_QCLK_LDAT_PDAT_FASTADDR_MAX (0x00000FFF) + #define MCMNTS_CR_QCLK_LDAT_PDAT_FASTADDR_DEF (0x00000000) + #define MCMNTS_CR_QCLK_LDAT_PDAT_ADDREN_OFF (16) + #define MCMNTS_CR_QCLK_LDAT_PDAT_ADDREN_WID ( 1) + #define MCMNTS_CR_QCLK_LDAT_PDAT_ADDREN_MSK (0x00010000) + #define MCMNTS_CR_QCLK_LDAT_PDAT_ADDREN_MAX (0x00000001) + #define MCMNTS_CR_QCLK_LDAT_PDAT_ADDREN_DEF (0x00000000) + #define MCMNTS_CR_QCLK_LDAT_PDAT_SEQEN_OFF (17) + #define MCMNTS_CR_QCLK_LDAT_PDAT_SEQEN_WID ( 1) + #define MCMNTS_CR_QCLK_LDAT_PDAT_SEQEN_MSK (0x00020000) + #define MCMNTS_CR_QCLK_LDAT_PDAT_SEQEN_MAX (0x00000001) + #define MCMNTS_CR_QCLK_LDAT_PDAT_SEQEN_DEF (0x00000000) + #define MCMNTS_CR_QCLK_LDAT_PDAT_POL0_OFF (18) + #define MCMNTS_CR_QCLK_LDAT_PDAT_POL0_WID ( 1) + #define MCMNTS_CR_QCLK_LDAT_PDAT_POL0_MSK (0x00040000) + #define MCMNTS_CR_QCLK_LDAT_PDAT_POL0_MAX (0x00000001) + #define MCMNTS_CR_QCLK_LDAT_PDAT_POL0_DEF (0x00000000) + #define MCMNTS_CR_QCLK_LDAT_PDAT_POL1_OFF (19) + #define MCMNTS_CR_QCLK_LDAT_PDAT_POL1_WID ( 1) + #define MCMNTS_CR_QCLK_LDAT_PDAT_POL1_MSK (0x00080000) + #define MCMNTS_CR_QCLK_LDAT_PDAT_POL1_MAX (0x00000001) + #define MCMNTS_CR_QCLK_LDAT_PDAT_POL1_DEF (0x00000000) + #define MCMNTS_CR_QCLK_LDAT_PDAT_CMDA_OFF (20) + #define MCMNTS_CR_QCLK_LDAT_PDAT_CMDA_WID ( 4) + #define MCMNTS_CR_QCLK_LDAT_PDAT_CMDA_MSK (0x00F00000) + #define MCMNTS_CR_QCLK_LDAT_PDAT_CMDA_MAX (0x0000000F) + #define MCMNTS_CR_QCLK_LDAT_PDAT_CMDA_DEF (0x00000000) + #define MCMNTS_CR_QCLK_LDAT_PDAT_CMDB_OFF (24) + #define MCMNTS_CR_QCLK_LDAT_PDAT_CMDB_WID ( 4) + #define MCMNTS_CR_QCLK_LDAT_PDAT_CMDB_MSK (0x0F000000) + #define MCMNTS_CR_QCLK_LDAT_PDAT_CMDB_MAX (0x0000000F) + #define MCMNTS_CR_QCLK_LDAT_PDAT_CMDB_DEF (0x00000000) + #define MCMNTS_CR_QCLK_LDAT_PDAT_CMDC_OFF (28) + #define MCMNTS_CR_QCLK_LDAT_PDAT_CMDC_WID ( 4) + #define MCMNTS_CR_QCLK_LDAT_PDAT_CMDC_MSK (0xF0000000) + #define MCMNTS_CR_QCLK_LDAT_PDAT_CMDC_MAX (0x0000000F) + #define MCMNTS_CR_QCLK_LDAT_PDAT_CMDC_DEF (0x00000000) + +#define MCMNTS_CR_QCLK_LDAT_SDAT_REG (0x00004ED4) + #define MCMNTS_CR_QCLK_LDAT_SDAT_BANKSEL_OFF ( 0) + #define MCMNTS_CR_QCLK_LDAT_SDAT_BANKSEL_WID ( 4) + #define MCMNTS_CR_QCLK_LDAT_SDAT_BANKSEL_MSK (0x0000000F) + #define MCMNTS_CR_QCLK_LDAT_SDAT_BANKSEL_MAX (0x0000000F) + #define MCMNTS_CR_QCLK_LDAT_SDAT_BANKSEL_DEF (0x00000000) + #define MCMNTS_CR_QCLK_LDAT_SDAT_ARRAYSEL_OFF ( 5) + #define MCMNTS_CR_QCLK_LDAT_SDAT_ARRAYSEL_WID ( 5) + #define MCMNTS_CR_QCLK_LDAT_SDAT_ARRAYSEL_MSK (0x000003E0) + #define MCMNTS_CR_QCLK_LDAT_SDAT_ARRAYSEL_MAX (0x0000001F) + #define MCMNTS_CR_QCLK_LDAT_SDAT_ARRAYSEL_DEF (0x00000000) + #define MCMNTS_CR_QCLK_LDAT_SDAT_CMP_OFF (10) + #define MCMNTS_CR_QCLK_LDAT_SDAT_CMP_WID ( 1) + #define MCMNTS_CR_QCLK_LDAT_SDAT_CMP_MSK (0x00000400) + #define MCMNTS_CR_QCLK_LDAT_SDAT_CMP_MAX (0x00000001) + #define MCMNTS_CR_QCLK_LDAT_SDAT_CMP_DEF (0x00000000) + #define MCMNTS_CR_QCLK_LDAT_SDAT_REP_OFF (11) + #define MCMNTS_CR_QCLK_LDAT_SDAT_REP_WID ( 1) + #define MCMNTS_CR_QCLK_LDAT_SDAT_REP_MSK (0x00000800) + #define MCMNTS_CR_QCLK_LDAT_SDAT_REP_MAX (0x00000001) + #define MCMNTS_CR_QCLK_LDAT_SDAT_REP_DEF (0x00000000) + #define MCMNTS_CR_QCLK_LDAT_SDAT_DWORD_OFF (12) + #define MCMNTS_CR_QCLK_LDAT_SDAT_DWORD_WID ( 4) + #define MCMNTS_CR_QCLK_LDAT_SDAT_DWORD_MSK (0x0000F000) + #define MCMNTS_CR_QCLK_LDAT_SDAT_DWORD_MAX (0x0000000F) + #define MCMNTS_CR_QCLK_LDAT_SDAT_DWORD_DEF (0x00000000) + #define MCMNTS_CR_QCLK_LDAT_SDAT_MODE_OFF (16) + #define MCMNTS_CR_QCLK_LDAT_SDAT_MODE_WID ( 2) + #define MCMNTS_CR_QCLK_LDAT_SDAT_MODE_MSK (0x00030000) + #define MCMNTS_CR_QCLK_LDAT_SDAT_MODE_MAX (0x00000003) + #define MCMNTS_CR_QCLK_LDAT_SDAT_MODE_DEF (0x00000000) + #define MCMNTS_CR_QCLK_LDAT_SDAT_MPMAP_OFF (18) + #define MCMNTS_CR_QCLK_LDAT_SDAT_MPMAP_WID ( 6) + #define MCMNTS_CR_QCLK_LDAT_SDAT_MPMAP_MSK (0x00FC0000) + #define MCMNTS_CR_QCLK_LDAT_SDAT_MPMAP_MAX (0x0000003F) + #define MCMNTS_CR_QCLK_LDAT_SDAT_MPMAP_DEF (0x00000000) + #define MCMNTS_CR_QCLK_LDAT_SDAT_MPBOFFSET_OFF (24) + #define MCMNTS_CR_QCLK_LDAT_SDAT_MPBOFFSET_WID ( 4) + #define MCMNTS_CR_QCLK_LDAT_SDAT_MPBOFFSET_MSK (0x0F000000) + #define MCMNTS_CR_QCLK_LDAT_SDAT_MPBOFFSET_MAX (0x0000000F) + #define MCMNTS_CR_QCLK_LDAT_SDAT_MPBOFFSET_DEF (0x00000000) + #define MCMNTS_CR_QCLK_LDAT_SDAT_STAGE_EN_OFF (28) + #define MCMNTS_CR_QCLK_LDAT_SDAT_STAGE_EN_WID ( 1) + #define MCMNTS_CR_QCLK_LDAT_SDAT_STAGE_EN_MSK (0x10000000) + #define MCMNTS_CR_QCLK_LDAT_SDAT_STAGE_EN_MAX (0x00000001) + #define MCMNTS_CR_QCLK_LDAT_SDAT_STAGE_EN_DEF (0x00000000) + #define MCMNTS_CR_QCLK_LDAT_SDAT_SHADOW_OFF (29) + #define MCMNTS_CR_QCLK_LDAT_SDAT_SHADOW_WID ( 2) + #define MCMNTS_CR_QCLK_LDAT_SDAT_SHADOW_MSK (0x60000000) + #define MCMNTS_CR_QCLK_LDAT_SDAT_SHADOW_MAX (0x00000003) + #define MCMNTS_CR_QCLK_LDAT_SDAT_SHADOW_DEF (0x00000000) + +#define MCMNTS_CR_QCLK_LDAT_DATAOUT_REG (0x00004ED8) + #define MCMNTS_CR_QCLK_LDAT_DATAOUT_DATOUT_OFF ( 0) + #define MCMNTS_CR_QCLK_LDAT_DATAOUT_DATOUT_WID (32) + #define MCMNTS_CR_QCLK_LDAT_DATAOUT_DATOUT_MSK (0xFFFFFFFF) + #define MCMNTS_CR_QCLK_LDAT_DATAOUT_DATOUT_MAX (0xFFFFFFFF) + #define MCMNTS_CR_QCLK_LDAT_DATAOUT_DATOUT_DEF (0x00000000) + +#define MCMNTS_CR_QCLK_LDAT_DATAIN_0_REG (0x00004EDC) + #define MCMNTS_CR_QCLK_LDAT_DATAIN_0_DATIN_OFF ( 0) + #define MCMNTS_CR_QCLK_LDAT_DATAIN_0_DATIN_WID (32) + #define MCMNTS_CR_QCLK_LDAT_DATAIN_0_DATIN_MSK (0xFFFFFFFF) + #define MCMNTS_CR_QCLK_LDAT_DATAIN_0_DATIN_MAX (0xFFFFFFFF) + #define MCMNTS_CR_QCLK_LDAT_DATAIN_0_DATIN_DEF (0x00000000) + +#define MCMNTS_CR_QCLK_LDAT_DATAIN_1_REG (0x00004EE0) + #define MCMNTS_CR_QCLK_LDAT_DATAIN_1_DATIN_OFF ( 0) + #define MCMNTS_CR_QCLK_LDAT_DATAIN_1_DATIN_WID (32) + #define MCMNTS_CR_QCLK_LDAT_DATAIN_1_DATIN_MSK (0xFFFFFFFF) + #define MCMNTS_CR_QCLK_LDAT_DATAIN_1_DATIN_MAX (0xFFFFFFFF) + #define MCMNTS_CR_QCLK_LDAT_DATAIN_1_DATIN_DEF (0x00000000) + +#define MCMNTS_CR_QUEUE_ENTRY_DISABLE_RPQ_REG (0x00004EE4) + #define MCMNTS_CR_QUEUE_ENTRY_DISABLE_RPQ_RPQ_disable_OFF ( 0) + #define MCMNTS_CR_QUEUE_ENTRY_DISABLE_RPQ_RPQ_disable_WID (28) + #define MCMNTS_CR_QUEUE_ENTRY_DISABLE_RPQ_RPQ_disable_MSK (0x0FFFFFFF) + #define MCMNTS_CR_QUEUE_ENTRY_DISABLE_RPQ_RPQ_disable_MAX (0x0FFFFFFF) + #define MCMNTS_CR_QUEUE_ENTRY_DISABLE_RPQ_RPQ_disable_DEF (0x00000000) + +#define MCMNTS_CR_QUEUE_ENTRY_DISABLE_WPQ_REG (0x00004EE8) + #define MCMNTS_CR_QUEUE_ENTRY_DISABLE_WPQ_WPQ_disable_OFF ( 0) + #define MCMNTS_CR_QUEUE_ENTRY_DISABLE_WPQ_WPQ_disable_WID (32) + #define MCMNTS_CR_QUEUE_ENTRY_DISABLE_WPQ_WPQ_disable_MSK (0xFFFFFFFF) + #define MCMNTS_CR_QUEUE_ENTRY_DISABLE_WPQ_WPQ_disable_MAX (0xFFFFFFFF) + #define MCMNTS_CR_QUEUE_ENTRY_DISABLE_WPQ_WPQ_disable_DEF (0x00000000) + +#define MCMNTS_CR_PM_DIMM_IDLE_ENERGY_REG (0x00004EEC) + #define MCMNTS_CR_PM_DIMM_IDLE_ENERGY_DIMM0_IDLE_ENERGY_OFF ( 0) + #define MCMNTS_CR_PM_DIMM_IDLE_ENERGY_DIMM0_IDLE_ENERGY_WID ( 6) + #define MCMNTS_CR_PM_DIMM_IDLE_ENERGY_DIMM0_IDLE_ENERGY_MSK (0x0000003F) + #define MCMNTS_CR_PM_DIMM_IDLE_ENERGY_DIMM0_IDLE_ENERGY_MAX (0x0000003F) + #define MCMNTS_CR_PM_DIMM_IDLE_ENERGY_DIMM0_IDLE_ENERGY_DEF (0x00000000) + #define MCMNTS_CR_PM_DIMM_IDLE_ENERGY_DIMM1_IDLE_ENERGY_OFF ( 8) + #define MCMNTS_CR_PM_DIMM_IDLE_ENERGY_DIMM1_IDLE_ENERGY_WID ( 6) + #define MCMNTS_CR_PM_DIMM_IDLE_ENERGY_DIMM1_IDLE_ENERGY_MSK (0x00003F00) + #define MCMNTS_CR_PM_DIMM_IDLE_ENERGY_DIMM1_IDLE_ENERGY_MAX (0x0000003F) + #define MCMNTS_CR_PM_DIMM_IDLE_ENERGY_DIMM1_IDLE_ENERGY_DEF (0x00000000) + +#define MCMNTS_CR_PM_DIMM_PD_ENERGY_REG (0x00004EF0) + #define MCMNTS_CR_PM_DIMM_PD_ENERGY_DIMM0_PD_ENERGY_OFF ( 0) + #define MCMNTS_CR_PM_DIMM_PD_ENERGY_DIMM0_PD_ENERGY_WID ( 6) + #define MCMNTS_CR_PM_DIMM_PD_ENERGY_DIMM0_PD_ENERGY_MSK (0x0000003F) + #define MCMNTS_CR_PM_DIMM_PD_ENERGY_DIMM0_PD_ENERGY_MAX (0x0000003F) + #define MCMNTS_CR_PM_DIMM_PD_ENERGY_DIMM0_PD_ENERGY_DEF (0x00000000) + #define MCMNTS_CR_PM_DIMM_PD_ENERGY_DIMM1_PD_ENERGY_OFF ( 8) + #define MCMNTS_CR_PM_DIMM_PD_ENERGY_DIMM1_PD_ENERGY_WID ( 6) + #define MCMNTS_CR_PM_DIMM_PD_ENERGY_DIMM1_PD_ENERGY_MSK (0x00003F00) + #define MCMNTS_CR_PM_DIMM_PD_ENERGY_DIMM1_PD_ENERGY_MAX (0x0000003F) + #define MCMNTS_CR_PM_DIMM_PD_ENERGY_DIMM1_PD_ENERGY_DEF (0x00000000) + +#define MCMNTS_CR_PM_DIMM_ACT_ENERGY_REG (0x00004EF4) + #define MCMNTS_CR_PM_DIMM_ACT_ENERGY_DIMM0_ACT_ENERGY_OFF ( 0) + #define MCMNTS_CR_PM_DIMM_ACT_ENERGY_DIMM0_ACT_ENERGY_WID ( 8) + #define MCMNTS_CR_PM_DIMM_ACT_ENERGY_DIMM0_ACT_ENERGY_MSK (0x000000FF) + #define MCMNTS_CR_PM_DIMM_ACT_ENERGY_DIMM0_ACT_ENERGY_MAX (0x000000FF) + #define MCMNTS_CR_PM_DIMM_ACT_ENERGY_DIMM0_ACT_ENERGY_DEF (0x00000000) + #define MCMNTS_CR_PM_DIMM_ACT_ENERGY_DIMM1_ACT_ENERGY_OFF ( 8) + #define MCMNTS_CR_PM_DIMM_ACT_ENERGY_DIMM1_ACT_ENERGY_WID ( 8) + #define MCMNTS_CR_PM_DIMM_ACT_ENERGY_DIMM1_ACT_ENERGY_MSK (0x0000FF00) + #define MCMNTS_CR_PM_DIMM_ACT_ENERGY_DIMM1_ACT_ENERGY_MAX (0x000000FF) + #define MCMNTS_CR_PM_DIMM_ACT_ENERGY_DIMM1_ACT_ENERGY_DEF (0x00000000) + +#define MCMNTS_CR_PM_DIMM_RD_ENERGY_REG (0x00004EF8) + #define MCMNTS_CR_PM_DIMM_RD_ENERGY_DIMM0_RD_ENERGY_OFF ( 0) + #define MCMNTS_CR_PM_DIMM_RD_ENERGY_DIMM0_RD_ENERGY_WID ( 8) + #define MCMNTS_CR_PM_DIMM_RD_ENERGY_DIMM0_RD_ENERGY_MSK (0x000000FF) + #define MCMNTS_CR_PM_DIMM_RD_ENERGY_DIMM0_RD_ENERGY_MAX (0x000000FF) + #define MCMNTS_CR_PM_DIMM_RD_ENERGY_DIMM0_RD_ENERGY_DEF (0x00000000) + #define MCMNTS_CR_PM_DIMM_RD_ENERGY_DIMM1_RD_ENERGY_OFF ( 8) + #define MCMNTS_CR_PM_DIMM_RD_ENERGY_DIMM1_RD_ENERGY_WID ( 8) + #define MCMNTS_CR_PM_DIMM_RD_ENERGY_DIMM1_RD_ENERGY_MSK (0x0000FF00) + #define MCMNTS_CR_PM_DIMM_RD_ENERGY_DIMM1_RD_ENERGY_MAX (0x000000FF) + #define MCMNTS_CR_PM_DIMM_RD_ENERGY_DIMM1_RD_ENERGY_DEF (0x00000000) + +#define MCMNTS_CR_PM_DIMM_WR_ENERGY_REG (0x00004EFC) + #define MCMNTS_CR_PM_DIMM_WR_ENERGY_DIMM0_WR_ENERGY_OFF ( 0) + #define MCMNTS_CR_PM_DIMM_WR_ENERGY_DIMM0_WR_ENERGY_WID ( 8) + #define MCMNTS_CR_PM_DIMM_WR_ENERGY_DIMM0_WR_ENERGY_MSK (0x000000FF) + #define MCMNTS_CR_PM_DIMM_WR_ENERGY_DIMM0_WR_ENERGY_MAX (0x000000FF) + #define MCMNTS_CR_PM_DIMM_WR_ENERGY_DIMM0_WR_ENERGY_DEF (0x00000000) + #define MCMNTS_CR_PM_DIMM_WR_ENERGY_DIMM1_WR_ENERGY_OFF ( 8) + #define MCMNTS_CR_PM_DIMM_WR_ENERGY_DIMM1_WR_ENERGY_WID ( 8) + #define MCMNTS_CR_PM_DIMM_WR_ENERGY_DIMM1_WR_ENERGY_MSK (0x0000FF00) + #define MCMNTS_CR_PM_DIMM_WR_ENERGY_DIMM1_WR_ENERGY_MAX (0x000000FF) + #define MCMNTS_CR_PM_DIMM_WR_ENERGY_DIMM1_WR_ENERGY_DEF (0x00000000) + +#define MCMNTS_CR_PM_THRT_CKE_MIN_REG (0x00004F28) + #define MCMNTS_CR_PM_THRT_CKE_MIN_CKE_MIN_OFF ( 0) + #define MCMNTS_CR_PM_THRT_CKE_MIN_CKE_MIN_WID ( 8) + #define MCMNTS_CR_PM_THRT_CKE_MIN_CKE_MIN_MSK (0x000000FF) + #define MCMNTS_CR_PM_THRT_CKE_MIN_CKE_MIN_MAX (0x000000FF) + #define MCMNTS_CR_PM_THRT_CKE_MIN_CKE_MIN_DEF (0x00000000) + #define MCMNTS_CR_PM_THRT_CKE_MIN_CKE_MIN_DEFEATURE_OFF ( 8) + #define MCMNTS_CR_PM_THRT_CKE_MIN_CKE_MIN_DEFEATURE_WID ( 1) + #define MCMNTS_CR_PM_THRT_CKE_MIN_CKE_MIN_DEFEATURE_MSK (0x00000100) + #define MCMNTS_CR_PM_THRT_CKE_MIN_CKE_MIN_DEFEATURE_MAX (0x00000001) + #define MCMNTS_CR_PM_THRT_CKE_MIN_CKE_MIN_DEFEATURE_DEF (0x00000000) + +#define MCMNTS_CR_ODLAT_CMD_MATCH0_REG (0x00004F40) + #define MCMNTS_CR_ODLAT_CMD_MATCH0_ODT_OFF ( 0) + #define MCMNTS_CR_ODLAT_CMD_MATCH0_ODT_WID ( 4) + #define MCMNTS_CR_ODLAT_CMD_MATCH0_ODT_MSK (0x0000000F) + #define MCMNTS_CR_ODLAT_CMD_MATCH0_ODT_MAX (0x0000000F) + #define MCMNTS_CR_ODLAT_CMD_MATCH0_ODT_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_CMD_MATCH0_Web_OFF ( 4) + #define MCMNTS_CR_ODLAT_CMD_MATCH0_Web_WID ( 1) + #define MCMNTS_CR_ODLAT_CMD_MATCH0_Web_MSK (0x00000010) + #define MCMNTS_CR_ODLAT_CMD_MATCH0_Web_MAX (0x00000001) + #define MCMNTS_CR_ODLAT_CMD_MATCH0_Web_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_CMD_MATCH0_CASb_OFF ( 5) + #define MCMNTS_CR_ODLAT_CMD_MATCH0_CASb_WID ( 1) + #define MCMNTS_CR_ODLAT_CMD_MATCH0_CASb_MSK (0x00000020) + #define MCMNTS_CR_ODLAT_CMD_MATCH0_CASb_MAX (0x00000001) + #define MCMNTS_CR_ODLAT_CMD_MATCH0_CASb_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_CMD_MATCH0_RASb_OFF ( 6) + #define MCMNTS_CR_ODLAT_CMD_MATCH0_RASb_WID ( 1) + #define MCMNTS_CR_ODLAT_CMD_MATCH0_RASb_MSK (0x00000040) + #define MCMNTS_CR_ODLAT_CMD_MATCH0_RASb_MAX (0x00000001) + #define MCMNTS_CR_ODLAT_CMD_MATCH0_RASb_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_CMD_MATCH0_CSb_OFF ( 7) + #define MCMNTS_CR_ODLAT_CMD_MATCH0_CSb_WID ( 4) + #define MCMNTS_CR_ODLAT_CMD_MATCH0_CSb_MSK (0x00000780) + #define MCMNTS_CR_ODLAT_CMD_MATCH0_CSb_MAX (0x0000000F) + #define MCMNTS_CR_ODLAT_CMD_MATCH0_CSb_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_CMD_MATCH0_CKE_OFF (11) + #define MCMNTS_CR_ODLAT_CMD_MATCH0_CKE_WID ( 4) + #define MCMNTS_CR_ODLAT_CMD_MATCH0_CKE_MSK (0x00007800) + #define MCMNTS_CR_ODLAT_CMD_MATCH0_CKE_MAX (0x0000000F) + #define MCMNTS_CR_ODLAT_CMD_MATCH0_CKE_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_CMD_MATCH0_MA_OFF (15) + #define MCMNTS_CR_ODLAT_CMD_MATCH0_MA_WID (16) + #define MCMNTS_CR_ODLAT_CMD_MATCH0_MA_MSK (0x7FFF8000) + #define MCMNTS_CR_ODLAT_CMD_MATCH0_MA_MAX (0x0000FFFF) + #define MCMNTS_CR_ODLAT_CMD_MATCH0_MA_DEF (0x00000000) + +#define MCMNTS_CR_ODLAT_CMD_MATCH1_REG (0x00004F44) + #define MCMNTS_CR_ODLAT_CMD_MATCH1_ODT_OFF ( 0) + #define MCMNTS_CR_ODLAT_CMD_MATCH1_ODT_WID ( 4) + #define MCMNTS_CR_ODLAT_CMD_MATCH1_ODT_MSK (0x0000000F) + #define MCMNTS_CR_ODLAT_CMD_MATCH1_ODT_MAX (0x0000000F) + #define MCMNTS_CR_ODLAT_CMD_MATCH1_ODT_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_CMD_MATCH1_Web_OFF ( 4) + #define MCMNTS_CR_ODLAT_CMD_MATCH1_Web_WID ( 1) + #define MCMNTS_CR_ODLAT_CMD_MATCH1_Web_MSK (0x00000010) + #define MCMNTS_CR_ODLAT_CMD_MATCH1_Web_MAX (0x00000001) + #define MCMNTS_CR_ODLAT_CMD_MATCH1_Web_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_CMD_MATCH1_CASb_OFF ( 5) + #define MCMNTS_CR_ODLAT_CMD_MATCH1_CASb_WID ( 1) + #define MCMNTS_CR_ODLAT_CMD_MATCH1_CASb_MSK (0x00000020) + #define MCMNTS_CR_ODLAT_CMD_MATCH1_CASb_MAX (0x00000001) + #define MCMNTS_CR_ODLAT_CMD_MATCH1_CASb_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_CMD_MATCH1_RASb_OFF ( 6) + #define MCMNTS_CR_ODLAT_CMD_MATCH1_RASb_WID ( 1) + #define MCMNTS_CR_ODLAT_CMD_MATCH1_RASb_MSK (0x00000040) + #define MCMNTS_CR_ODLAT_CMD_MATCH1_RASb_MAX (0x00000001) + #define MCMNTS_CR_ODLAT_CMD_MATCH1_RASb_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_CMD_MATCH1_CSb_OFF ( 7) + #define MCMNTS_CR_ODLAT_CMD_MATCH1_CSb_WID ( 4) + #define MCMNTS_CR_ODLAT_CMD_MATCH1_CSb_MSK (0x00000780) + #define MCMNTS_CR_ODLAT_CMD_MATCH1_CSb_MAX (0x0000000F) + #define MCMNTS_CR_ODLAT_CMD_MATCH1_CSb_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_CMD_MATCH1_CKE_OFF (11) + #define MCMNTS_CR_ODLAT_CMD_MATCH1_CKE_WID ( 4) + #define MCMNTS_CR_ODLAT_CMD_MATCH1_CKE_MSK (0x00007800) + #define MCMNTS_CR_ODLAT_CMD_MATCH1_CKE_MAX (0x0000000F) + #define MCMNTS_CR_ODLAT_CMD_MATCH1_CKE_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_CMD_MATCH1_MA_OFF (15) + #define MCMNTS_CR_ODLAT_CMD_MATCH1_MA_WID (16) + #define MCMNTS_CR_ODLAT_CMD_MATCH1_MA_MSK (0x7FFF8000) + #define MCMNTS_CR_ODLAT_CMD_MATCH1_MA_MAX (0x0000FFFF) + #define MCMNTS_CR_ODLAT_CMD_MATCH1_MA_DEF (0x00000000) + +#define MCMNTS_CR_ODLAT_CMD_MATCH2_REG (0x00004F48) + #define MCMNTS_CR_ODLAT_CMD_MATCH2_ODT_OFF ( 0) + #define MCMNTS_CR_ODLAT_CMD_MATCH2_ODT_WID ( 4) + #define MCMNTS_CR_ODLAT_CMD_MATCH2_ODT_MSK (0x0000000F) + #define MCMNTS_CR_ODLAT_CMD_MATCH2_ODT_MAX (0x0000000F) + #define MCMNTS_CR_ODLAT_CMD_MATCH2_ODT_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_CMD_MATCH2_Web_OFF ( 4) + #define MCMNTS_CR_ODLAT_CMD_MATCH2_Web_WID ( 1) + #define MCMNTS_CR_ODLAT_CMD_MATCH2_Web_MSK (0x00000010) + #define MCMNTS_CR_ODLAT_CMD_MATCH2_Web_MAX (0x00000001) + #define MCMNTS_CR_ODLAT_CMD_MATCH2_Web_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_CMD_MATCH2_CASb_OFF ( 5) + #define MCMNTS_CR_ODLAT_CMD_MATCH2_CASb_WID ( 1) + #define MCMNTS_CR_ODLAT_CMD_MATCH2_CASb_MSK (0x00000020) + #define MCMNTS_CR_ODLAT_CMD_MATCH2_CASb_MAX (0x00000001) + #define MCMNTS_CR_ODLAT_CMD_MATCH2_CASb_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_CMD_MATCH2_RASb_OFF ( 6) + #define MCMNTS_CR_ODLAT_CMD_MATCH2_RASb_WID ( 1) + #define MCMNTS_CR_ODLAT_CMD_MATCH2_RASb_MSK (0x00000040) + #define MCMNTS_CR_ODLAT_CMD_MATCH2_RASb_MAX (0x00000001) + #define MCMNTS_CR_ODLAT_CMD_MATCH2_RASb_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_CMD_MATCH2_CSb_OFF ( 7) + #define MCMNTS_CR_ODLAT_CMD_MATCH2_CSb_WID ( 4) + #define MCMNTS_CR_ODLAT_CMD_MATCH2_CSb_MSK (0x00000780) + #define MCMNTS_CR_ODLAT_CMD_MATCH2_CSb_MAX (0x0000000F) + #define MCMNTS_CR_ODLAT_CMD_MATCH2_CSb_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_CMD_MATCH2_CKE_OFF (11) + #define MCMNTS_CR_ODLAT_CMD_MATCH2_CKE_WID ( 4) + #define MCMNTS_CR_ODLAT_CMD_MATCH2_CKE_MSK (0x00007800) + #define MCMNTS_CR_ODLAT_CMD_MATCH2_CKE_MAX (0x0000000F) + #define MCMNTS_CR_ODLAT_CMD_MATCH2_CKE_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_CMD_MATCH2_MA_OFF (15) + #define MCMNTS_CR_ODLAT_CMD_MATCH2_MA_WID (16) + #define MCMNTS_CR_ODLAT_CMD_MATCH2_MA_MSK (0x7FFF8000) + #define MCMNTS_CR_ODLAT_CMD_MATCH2_MA_MAX (0x0000FFFF) + #define MCMNTS_CR_ODLAT_CMD_MATCH2_MA_DEF (0x00000000) + +#define MCMNTS_CR_ODLAT_CMD_MATCH3_REG (0x00004F4C) + #define MCMNTS_CR_ODLAT_CMD_MATCH3_ODT_OFF ( 0) + #define MCMNTS_CR_ODLAT_CMD_MATCH3_ODT_WID ( 4) + #define MCMNTS_CR_ODLAT_CMD_MATCH3_ODT_MSK (0x0000000F) + #define MCMNTS_CR_ODLAT_CMD_MATCH3_ODT_MAX (0x0000000F) + #define MCMNTS_CR_ODLAT_CMD_MATCH3_ODT_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_CMD_MATCH3_Web_OFF ( 4) + #define MCMNTS_CR_ODLAT_CMD_MATCH3_Web_WID ( 1) + #define MCMNTS_CR_ODLAT_CMD_MATCH3_Web_MSK (0x00000010) + #define MCMNTS_CR_ODLAT_CMD_MATCH3_Web_MAX (0x00000001) + #define MCMNTS_CR_ODLAT_CMD_MATCH3_Web_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_CMD_MATCH3_CASb_OFF ( 5) + #define MCMNTS_CR_ODLAT_CMD_MATCH3_CASb_WID ( 1) + #define MCMNTS_CR_ODLAT_CMD_MATCH3_CASb_MSK (0x00000020) + #define MCMNTS_CR_ODLAT_CMD_MATCH3_CASb_MAX (0x00000001) + #define MCMNTS_CR_ODLAT_CMD_MATCH3_CASb_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_CMD_MATCH3_RASb_OFF ( 6) + #define MCMNTS_CR_ODLAT_CMD_MATCH3_RASb_WID ( 1) + #define MCMNTS_CR_ODLAT_CMD_MATCH3_RASb_MSK (0x00000040) + #define MCMNTS_CR_ODLAT_CMD_MATCH3_RASb_MAX (0x00000001) + #define MCMNTS_CR_ODLAT_CMD_MATCH3_RASb_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_CMD_MATCH3_CSb_OFF ( 7) + #define MCMNTS_CR_ODLAT_CMD_MATCH3_CSb_WID ( 4) + #define MCMNTS_CR_ODLAT_CMD_MATCH3_CSb_MSK (0x00000780) + #define MCMNTS_CR_ODLAT_CMD_MATCH3_CSb_MAX (0x0000000F) + #define MCMNTS_CR_ODLAT_CMD_MATCH3_CSb_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_CMD_MATCH3_CKE_OFF (11) + #define MCMNTS_CR_ODLAT_CMD_MATCH3_CKE_WID ( 4) + #define MCMNTS_CR_ODLAT_CMD_MATCH3_CKE_MSK (0x00007800) + #define MCMNTS_CR_ODLAT_CMD_MATCH3_CKE_MAX (0x0000000F) + #define MCMNTS_CR_ODLAT_CMD_MATCH3_CKE_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_CMD_MATCH3_MA_OFF (15) + #define MCMNTS_CR_ODLAT_CMD_MATCH3_MA_WID (16) + #define MCMNTS_CR_ODLAT_CMD_MATCH3_MA_MSK (0x7FFF8000) + #define MCMNTS_CR_ODLAT_CMD_MATCH3_MA_MAX (0x0000FFFF) + #define MCMNTS_CR_ODLAT_CMD_MATCH3_MA_DEF (0x00000000) + +#define MCMNTS_CR_ODLAT_CMD_MASK0_REG (0x00004F50) + #define MCMNTS_CR_ODLAT_CMD_MASK0_ODT_OFF ( 0) + #define MCMNTS_CR_ODLAT_CMD_MASK0_ODT_WID ( 4) + #define MCMNTS_CR_ODLAT_CMD_MASK0_ODT_MSK (0x0000000F) + #define MCMNTS_CR_ODLAT_CMD_MASK0_ODT_MAX (0x0000000F) + #define MCMNTS_CR_ODLAT_CMD_MASK0_ODT_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_CMD_MASK0_Web_OFF ( 4) + #define MCMNTS_CR_ODLAT_CMD_MASK0_Web_WID ( 1) + #define MCMNTS_CR_ODLAT_CMD_MASK0_Web_MSK (0x00000010) + #define MCMNTS_CR_ODLAT_CMD_MASK0_Web_MAX (0x00000001) + #define MCMNTS_CR_ODLAT_CMD_MASK0_Web_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_CMD_MASK0_CASb_OFF ( 5) + #define MCMNTS_CR_ODLAT_CMD_MASK0_CASb_WID ( 1) + #define MCMNTS_CR_ODLAT_CMD_MASK0_CASb_MSK (0x00000020) + #define MCMNTS_CR_ODLAT_CMD_MASK0_CASb_MAX (0x00000001) + #define MCMNTS_CR_ODLAT_CMD_MASK0_CASb_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_CMD_MASK0_RASb_OFF ( 6) + #define MCMNTS_CR_ODLAT_CMD_MASK0_RASb_WID ( 1) + #define MCMNTS_CR_ODLAT_CMD_MASK0_RASb_MSK (0x00000040) + #define MCMNTS_CR_ODLAT_CMD_MASK0_RASb_MAX (0x00000001) + #define MCMNTS_CR_ODLAT_CMD_MASK0_RASb_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_CMD_MASK0_CSb_OFF ( 7) + #define MCMNTS_CR_ODLAT_CMD_MASK0_CSb_WID ( 4) + #define MCMNTS_CR_ODLAT_CMD_MASK0_CSb_MSK (0x00000780) + #define MCMNTS_CR_ODLAT_CMD_MASK0_CSb_MAX (0x0000000F) + #define MCMNTS_CR_ODLAT_CMD_MASK0_CSb_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_CMD_MASK0_CKE_OFF (11) + #define MCMNTS_CR_ODLAT_CMD_MASK0_CKE_WID ( 4) + #define MCMNTS_CR_ODLAT_CMD_MASK0_CKE_MSK (0x00007800) + #define MCMNTS_CR_ODLAT_CMD_MASK0_CKE_MAX (0x0000000F) + #define MCMNTS_CR_ODLAT_CMD_MASK0_CKE_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_CMD_MASK0_MA_OFF (15) + #define MCMNTS_CR_ODLAT_CMD_MASK0_MA_WID (16) + #define MCMNTS_CR_ODLAT_CMD_MASK0_MA_MSK (0x7FFF8000) + #define MCMNTS_CR_ODLAT_CMD_MASK0_MA_MAX (0x0000FFFF) + #define MCMNTS_CR_ODLAT_CMD_MASK0_MA_DEF (0x00000000) + +#define MCMNTS_CR_ODLAT_CMD_MASK1_REG (0x00004F54) + #define MCMNTS_CR_ODLAT_CMD_MASK1_ODT_OFF ( 0) + #define MCMNTS_CR_ODLAT_CMD_MASK1_ODT_WID ( 4) + #define MCMNTS_CR_ODLAT_CMD_MASK1_ODT_MSK (0x0000000F) + #define MCMNTS_CR_ODLAT_CMD_MASK1_ODT_MAX (0x0000000F) + #define MCMNTS_CR_ODLAT_CMD_MASK1_ODT_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_CMD_MASK1_Web_OFF ( 4) + #define MCMNTS_CR_ODLAT_CMD_MASK1_Web_WID ( 1) + #define MCMNTS_CR_ODLAT_CMD_MASK1_Web_MSK (0x00000010) + #define MCMNTS_CR_ODLAT_CMD_MASK1_Web_MAX (0x00000001) + #define MCMNTS_CR_ODLAT_CMD_MASK1_Web_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_CMD_MASK1_CASb_OFF ( 5) + #define MCMNTS_CR_ODLAT_CMD_MASK1_CASb_WID ( 1) + #define MCMNTS_CR_ODLAT_CMD_MASK1_CASb_MSK (0x00000020) + #define MCMNTS_CR_ODLAT_CMD_MASK1_CASb_MAX (0x00000001) + #define MCMNTS_CR_ODLAT_CMD_MASK1_CASb_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_CMD_MASK1_RASb_OFF ( 6) + #define MCMNTS_CR_ODLAT_CMD_MASK1_RASb_WID ( 1) + #define MCMNTS_CR_ODLAT_CMD_MASK1_RASb_MSK (0x00000040) + #define MCMNTS_CR_ODLAT_CMD_MASK1_RASb_MAX (0x00000001) + #define MCMNTS_CR_ODLAT_CMD_MASK1_RASb_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_CMD_MASK1_CSb_OFF ( 7) + #define MCMNTS_CR_ODLAT_CMD_MASK1_CSb_WID ( 4) + #define MCMNTS_CR_ODLAT_CMD_MASK1_CSb_MSK (0x00000780) + #define MCMNTS_CR_ODLAT_CMD_MASK1_CSb_MAX (0x0000000F) + #define MCMNTS_CR_ODLAT_CMD_MASK1_CSb_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_CMD_MASK1_CKE_OFF (11) + #define MCMNTS_CR_ODLAT_CMD_MASK1_CKE_WID ( 4) + #define MCMNTS_CR_ODLAT_CMD_MASK1_CKE_MSK (0x00007800) + #define MCMNTS_CR_ODLAT_CMD_MASK1_CKE_MAX (0x0000000F) + #define MCMNTS_CR_ODLAT_CMD_MASK1_CKE_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_CMD_MASK1_MA_OFF (15) + #define MCMNTS_CR_ODLAT_CMD_MASK1_MA_WID (16) + #define MCMNTS_CR_ODLAT_CMD_MASK1_MA_MSK (0x7FFF8000) + #define MCMNTS_CR_ODLAT_CMD_MASK1_MA_MAX (0x0000FFFF) + #define MCMNTS_CR_ODLAT_CMD_MASK1_MA_DEF (0x00000000) + +#define MCMNTS_CR_ODLAT_CMD_MASK2_REG (0x00004F58) + #define MCMNTS_CR_ODLAT_CMD_MASK2_ODT_OFF ( 0) + #define MCMNTS_CR_ODLAT_CMD_MASK2_ODT_WID ( 4) + #define MCMNTS_CR_ODLAT_CMD_MASK2_ODT_MSK (0x0000000F) + #define MCMNTS_CR_ODLAT_CMD_MASK2_ODT_MAX (0x0000000F) + #define MCMNTS_CR_ODLAT_CMD_MASK2_ODT_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_CMD_MASK2_Web_OFF ( 4) + #define MCMNTS_CR_ODLAT_CMD_MASK2_Web_WID ( 1) + #define MCMNTS_CR_ODLAT_CMD_MASK2_Web_MSK (0x00000010) + #define MCMNTS_CR_ODLAT_CMD_MASK2_Web_MAX (0x00000001) + #define MCMNTS_CR_ODLAT_CMD_MASK2_Web_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_CMD_MASK2_CASb_OFF ( 5) + #define MCMNTS_CR_ODLAT_CMD_MASK2_CASb_WID ( 1) + #define MCMNTS_CR_ODLAT_CMD_MASK2_CASb_MSK (0x00000020) + #define MCMNTS_CR_ODLAT_CMD_MASK2_CASb_MAX (0x00000001) + #define MCMNTS_CR_ODLAT_CMD_MASK2_CASb_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_CMD_MASK2_RASb_OFF ( 6) + #define MCMNTS_CR_ODLAT_CMD_MASK2_RASb_WID ( 1) + #define MCMNTS_CR_ODLAT_CMD_MASK2_RASb_MSK (0x00000040) + #define MCMNTS_CR_ODLAT_CMD_MASK2_RASb_MAX (0x00000001) + #define MCMNTS_CR_ODLAT_CMD_MASK2_RASb_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_CMD_MASK2_CSb_OFF ( 7) + #define MCMNTS_CR_ODLAT_CMD_MASK2_CSb_WID ( 4) + #define MCMNTS_CR_ODLAT_CMD_MASK2_CSb_MSK (0x00000780) + #define MCMNTS_CR_ODLAT_CMD_MASK2_CSb_MAX (0x0000000F) + #define MCMNTS_CR_ODLAT_CMD_MASK2_CSb_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_CMD_MASK2_CKE_OFF (11) + #define MCMNTS_CR_ODLAT_CMD_MASK2_CKE_WID ( 4) + #define MCMNTS_CR_ODLAT_CMD_MASK2_CKE_MSK (0x00007800) + #define MCMNTS_CR_ODLAT_CMD_MASK2_CKE_MAX (0x0000000F) + #define MCMNTS_CR_ODLAT_CMD_MASK2_CKE_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_CMD_MASK2_MA_OFF (15) + #define MCMNTS_CR_ODLAT_CMD_MASK2_MA_WID (16) + #define MCMNTS_CR_ODLAT_CMD_MASK2_MA_MSK (0x7FFF8000) + #define MCMNTS_CR_ODLAT_CMD_MASK2_MA_MAX (0x0000FFFF) + #define MCMNTS_CR_ODLAT_CMD_MASK2_MA_DEF (0x00000000) + +#define MCMNTS_CR_ODLAT_CMD_MASK3_REG (0x00004F5C) + #define MCMNTS_CR_ODLAT_CMD_MASK3_ODT_OFF ( 0) + #define MCMNTS_CR_ODLAT_CMD_MASK3_ODT_WID ( 4) + #define MCMNTS_CR_ODLAT_CMD_MASK3_ODT_MSK (0x0000000F) + #define MCMNTS_CR_ODLAT_CMD_MASK3_ODT_MAX (0x0000000F) + #define MCMNTS_CR_ODLAT_CMD_MASK3_ODT_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_CMD_MASK3_Web_OFF ( 4) + #define MCMNTS_CR_ODLAT_CMD_MASK3_Web_WID ( 1) + #define MCMNTS_CR_ODLAT_CMD_MASK3_Web_MSK (0x00000010) + #define MCMNTS_CR_ODLAT_CMD_MASK3_Web_MAX (0x00000001) + #define MCMNTS_CR_ODLAT_CMD_MASK3_Web_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_CMD_MASK3_CASb_OFF ( 5) + #define MCMNTS_CR_ODLAT_CMD_MASK3_CASb_WID ( 1) + #define MCMNTS_CR_ODLAT_CMD_MASK3_CASb_MSK (0x00000020) + #define MCMNTS_CR_ODLAT_CMD_MASK3_CASb_MAX (0x00000001) + #define MCMNTS_CR_ODLAT_CMD_MASK3_CASb_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_CMD_MASK3_RASb_OFF ( 6) + #define MCMNTS_CR_ODLAT_CMD_MASK3_RASb_WID ( 1) + #define MCMNTS_CR_ODLAT_CMD_MASK3_RASb_MSK (0x00000040) + #define MCMNTS_CR_ODLAT_CMD_MASK3_RASb_MAX (0x00000001) + #define MCMNTS_CR_ODLAT_CMD_MASK3_RASb_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_CMD_MASK3_CSb_OFF ( 7) + #define MCMNTS_CR_ODLAT_CMD_MASK3_CSb_WID ( 4) + #define MCMNTS_CR_ODLAT_CMD_MASK3_CSb_MSK (0x00000780) + #define MCMNTS_CR_ODLAT_CMD_MASK3_CSb_MAX (0x0000000F) + #define MCMNTS_CR_ODLAT_CMD_MASK3_CSb_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_CMD_MASK3_CKE_OFF (11) + #define MCMNTS_CR_ODLAT_CMD_MASK3_CKE_WID ( 4) + #define MCMNTS_CR_ODLAT_CMD_MASK3_CKE_MSK (0x00007800) + #define MCMNTS_CR_ODLAT_CMD_MASK3_CKE_MAX (0x0000000F) + #define MCMNTS_CR_ODLAT_CMD_MASK3_CKE_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_CMD_MASK3_MA_OFF (15) + #define MCMNTS_CR_ODLAT_CMD_MASK3_MA_WID (16) + #define MCMNTS_CR_ODLAT_CMD_MASK3_MA_MSK (0x7FFF8000) + #define MCMNTS_CR_ODLAT_CMD_MASK3_MA_MAX (0x0000FFFF) + #define MCMNTS_CR_ODLAT_CMD_MASK3_MA_DEF (0x00000000) + +#define MCMNTS_CR_ODLAT_CMD_BANK_REG (0x00004F60) + #define MCMNTS_CR_ODLAT_CMD_BANK_BankMatch0_OFF ( 0) + #define MCMNTS_CR_ODLAT_CMD_BANK_BankMatch0_WID ( 3) + #define MCMNTS_CR_ODLAT_CMD_BANK_BankMatch0_MSK (0x00000007) + #define MCMNTS_CR_ODLAT_CMD_BANK_BankMatch0_MAX (0x00000007) + #define MCMNTS_CR_ODLAT_CMD_BANK_BankMatch0_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_CMD_BANK_BankMatch1_OFF ( 3) + #define MCMNTS_CR_ODLAT_CMD_BANK_BankMatch1_WID ( 3) + #define MCMNTS_CR_ODLAT_CMD_BANK_BankMatch1_MSK (0x00000038) + #define MCMNTS_CR_ODLAT_CMD_BANK_BankMatch1_MAX (0x00000007) + #define MCMNTS_CR_ODLAT_CMD_BANK_BankMatch1_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_CMD_BANK_BankMatch2_OFF ( 6) + #define MCMNTS_CR_ODLAT_CMD_BANK_BankMatch2_WID ( 3) + #define MCMNTS_CR_ODLAT_CMD_BANK_BankMatch2_MSK (0x000001C0) + #define MCMNTS_CR_ODLAT_CMD_BANK_BankMatch2_MAX (0x00000007) + #define MCMNTS_CR_ODLAT_CMD_BANK_BankMatch2_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_CMD_BANK_BankMatch3_OFF ( 9) + #define MCMNTS_CR_ODLAT_CMD_BANK_BankMatch3_WID ( 3) + #define MCMNTS_CR_ODLAT_CMD_BANK_BankMatch3_MSK (0x00000E00) + #define MCMNTS_CR_ODLAT_CMD_BANK_BankMatch3_MAX (0x00000007) + #define MCMNTS_CR_ODLAT_CMD_BANK_BankMatch3_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_CMD_BANK_BankMask0_OFF (12) + #define MCMNTS_CR_ODLAT_CMD_BANK_BankMask0_WID ( 3) + #define MCMNTS_CR_ODLAT_CMD_BANK_BankMask0_MSK (0x00007000) + #define MCMNTS_CR_ODLAT_CMD_BANK_BankMask0_MAX (0x00000007) + #define MCMNTS_CR_ODLAT_CMD_BANK_BankMask0_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_CMD_BANK_BankMask1_OFF (15) + #define MCMNTS_CR_ODLAT_CMD_BANK_BankMask1_WID ( 3) + #define MCMNTS_CR_ODLAT_CMD_BANK_BankMask1_MSK (0x00038000) + #define MCMNTS_CR_ODLAT_CMD_BANK_BankMask1_MAX (0x00000007) + #define MCMNTS_CR_ODLAT_CMD_BANK_BankMask1_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_CMD_BANK_BankMask2_OFF (18) + #define MCMNTS_CR_ODLAT_CMD_BANK_BankMask2_WID ( 3) + #define MCMNTS_CR_ODLAT_CMD_BANK_BankMask2_MSK (0x001C0000) + #define MCMNTS_CR_ODLAT_CMD_BANK_BankMask2_MAX (0x00000007) + #define MCMNTS_CR_ODLAT_CMD_BANK_BankMask2_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_CMD_BANK_BankMask3_OFF (21) + #define MCMNTS_CR_ODLAT_CMD_BANK_BankMask3_WID ( 3) + #define MCMNTS_CR_ODLAT_CMD_BANK_BankMask3_MSK (0x00E00000) + #define MCMNTS_CR_ODLAT_CMD_BANK_BankMask3_MAX (0x00000007) + #define MCMNTS_CR_ODLAT_CMD_BANK_BankMask3_DEF (0x00000000) + +#define MCMNTS_CR_ODLAT_SEQ_LEVEL0_REG (0x00004F64) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL0_InputMatch_OFF ( 0) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL0_InputMatch_WID ( 4) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL0_InputMatch_MSK (0x0000000F) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL0_InputMatch_MAX (0x0000000F) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL0_InputMatch_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL0_InputInvert_OFF ( 4) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL0_InputInvert_WID ( 4) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL0_InputInvert_MSK (0x000000F0) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL0_InputInvert_MAX (0x0000000F) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL0_InputInvert_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL0_CountMatches_OFF ( 8) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL0_CountMatches_WID ( 1) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL0_CountMatches_MSK (0x00000100) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL0_CountMatches_MAX (0x00000001) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL0_CountMatches_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL0_CounterThreshold_OFF ( 9) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL0_CounterThreshold_WID (15) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL0_CounterThreshold_MSK (0x00FFFE00) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL0_CounterThreshold_MAX (0x00007FFF) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL0_CounterThreshold_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL0_CounterAction_OFF (24) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL0_CounterAction_WID ( 2) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL0_CounterAction_MSK (0x03000000) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL0_CounterAction_MAX (0x00000003) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL0_CounterAction_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL0_CounterNextState_OFF (26) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL0_CounterNextState_WID ( 2) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL0_CounterNextState_MSK (0x0C000000) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL0_CounterNextState_MAX (0x00000003) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL0_CounterNextState_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL0_MatchAction_OFF (28) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL0_MatchAction_WID ( 2) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL0_MatchAction_MSK (0x30000000) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL0_MatchAction_MAX (0x00000003) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL0_MatchAction_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL0_MatchNextState_OFF (30) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL0_MatchNextState_WID ( 2) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL0_MatchNextState_MSK (0xC0000000) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL0_MatchNextState_MAX (0x00000003) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL0_MatchNextState_DEF (0x00000000) + +#define MCMNTS_CR_ODLAT_SEQ_LEVEL1_REG (0x00004F68) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL1_InputMatch_OFF ( 0) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL1_InputMatch_WID ( 4) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL1_InputMatch_MSK (0x0000000F) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL1_InputMatch_MAX (0x0000000F) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL1_InputMatch_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL1_InputInvert_OFF ( 4) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL1_InputInvert_WID ( 4) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL1_InputInvert_MSK (0x000000F0) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL1_InputInvert_MAX (0x0000000F) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL1_InputInvert_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL1_CountMatches_OFF ( 8) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL1_CountMatches_WID ( 1) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL1_CountMatches_MSK (0x00000100) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL1_CountMatches_MAX (0x00000001) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL1_CountMatches_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL1_CounterThreshold_OFF ( 9) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL1_CounterThreshold_WID (15) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL1_CounterThreshold_MSK (0x00FFFE00) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL1_CounterThreshold_MAX (0x00007FFF) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL1_CounterThreshold_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL1_CounterAction_OFF (24) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL1_CounterAction_WID ( 2) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL1_CounterAction_MSK (0x03000000) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL1_CounterAction_MAX (0x00000003) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL1_CounterAction_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL1_CounterNextState_OFF (26) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL1_CounterNextState_WID ( 2) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL1_CounterNextState_MSK (0x0C000000) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL1_CounterNextState_MAX (0x00000003) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL1_CounterNextState_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL1_MatchAction_OFF (28) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL1_MatchAction_WID ( 2) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL1_MatchAction_MSK (0x30000000) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL1_MatchAction_MAX (0x00000003) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL1_MatchAction_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL1_MatchNextState_OFF (30) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL1_MatchNextState_WID ( 2) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL1_MatchNextState_MSK (0xC0000000) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL1_MatchNextState_MAX (0x00000003) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL1_MatchNextState_DEF (0x00000000) + +#define MCMNTS_CR_ODLAT_SEQ_LEVEL2_REG (0x00004F6C) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL2_InputMatch_OFF ( 0) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL2_InputMatch_WID ( 4) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL2_InputMatch_MSK (0x0000000F) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL2_InputMatch_MAX (0x0000000F) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL2_InputMatch_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL2_InputInvert_OFF ( 4) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL2_InputInvert_WID ( 4) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL2_InputInvert_MSK (0x000000F0) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL2_InputInvert_MAX (0x0000000F) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL2_InputInvert_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL2_CountMatches_OFF ( 8) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL2_CountMatches_WID ( 1) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL2_CountMatches_MSK (0x00000100) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL2_CountMatches_MAX (0x00000001) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL2_CountMatches_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL2_CounterThreshold_OFF ( 9) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL2_CounterThreshold_WID (15) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL2_CounterThreshold_MSK (0x00FFFE00) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL2_CounterThreshold_MAX (0x00007FFF) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL2_CounterThreshold_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL2_CounterAction_OFF (24) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL2_CounterAction_WID ( 2) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL2_CounterAction_MSK (0x03000000) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL2_CounterAction_MAX (0x00000003) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL2_CounterAction_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL2_CounterNextState_OFF (26) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL2_CounterNextState_WID ( 2) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL2_CounterNextState_MSK (0x0C000000) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL2_CounterNextState_MAX (0x00000003) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL2_CounterNextState_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL2_MatchAction_OFF (28) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL2_MatchAction_WID ( 2) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL2_MatchAction_MSK (0x30000000) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL2_MatchAction_MAX (0x00000003) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL2_MatchAction_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL2_MatchNextState_OFF (30) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL2_MatchNextState_WID ( 2) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL2_MatchNextState_MSK (0xC0000000) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL2_MatchNextState_MAX (0x00000003) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL2_MatchNextState_DEF (0x00000000) + +#define MCMNTS_CR_ODLAT_SEQ_LEVEL3_REG (0x00004F70) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL3_InputMatch_OFF ( 0) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL3_InputMatch_WID ( 4) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL3_InputMatch_MSK (0x0000000F) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL3_InputMatch_MAX (0x0000000F) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL3_InputMatch_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL3_InputInvert_OFF ( 4) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL3_InputInvert_WID ( 4) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL3_InputInvert_MSK (0x000000F0) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL3_InputInvert_MAX (0x0000000F) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL3_InputInvert_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL3_CountMatches_OFF ( 8) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL3_CountMatches_WID ( 1) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL3_CountMatches_MSK (0x00000100) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL3_CountMatches_MAX (0x00000001) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL3_CountMatches_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL3_CounterThreshold_OFF ( 9) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL3_CounterThreshold_WID (15) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL3_CounterThreshold_MSK (0x00FFFE00) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL3_CounterThreshold_MAX (0x00007FFF) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL3_CounterThreshold_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL3_CounterAction_OFF (24) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL3_CounterAction_WID ( 2) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL3_CounterAction_MSK (0x03000000) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL3_CounterAction_MAX (0x00000003) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL3_CounterAction_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL3_CounterNextState_OFF (26) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL3_CounterNextState_WID ( 2) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL3_CounterNextState_MSK (0x0C000000) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL3_CounterNextState_MAX (0x00000003) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL3_CounterNextState_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL3_MatchAction_OFF (28) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL3_MatchAction_WID ( 2) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL3_MatchAction_MSK (0x30000000) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL3_MatchAction_MAX (0x00000003) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL3_MatchAction_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL3_MatchNextState_OFF (30) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL3_MatchNextState_WID ( 2) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL3_MatchNextState_MSK (0xC0000000) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL3_MatchNextState_MAX (0x00000003) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL3_MatchNextState_DEF (0x00000000) + +#define MCMNTS_CR_ODLAT_SEQ_GLOBAL_REG (0x00004F74) + #define MCMNTS_CR_ODLAT_SEQ_GLOBAL_TriggerBlockEnable_OFF ( 0) + #define MCMNTS_CR_ODLAT_SEQ_GLOBAL_TriggerBlockEnable_WID ( 1) + #define MCMNTS_CR_ODLAT_SEQ_GLOBAL_TriggerBlockEnable_MSK (0x00000001) + #define MCMNTS_CR_ODLAT_SEQ_GLOBAL_TriggerBlockEnable_MAX (0x00000001) + #define MCMNTS_CR_ODLAT_SEQ_GLOBAL_TriggerBlockEnable_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_SEQ_GLOBAL_GlobalCounterThreshold_OFF ( 1) + #define MCMNTS_CR_ODLAT_SEQ_GLOBAL_GlobalCounterThreshold_WID (16) + #define MCMNTS_CR_ODLAT_SEQ_GLOBAL_GlobalCounterThreshold_MSK (0x0001FFFE) + #define MCMNTS_CR_ODLAT_SEQ_GLOBAL_GlobalCounterThreshold_MAX (0x0000FFFF) + #define MCMNTS_CR_ODLAT_SEQ_GLOBAL_GlobalCounterThreshold_DEF (0x00000000) + +#define MCMNTS_CR_SC_WDBWM_REG (0x00004F8C) + #define MCMNTS_CR_SC_WDBWM_WMM_Enter_OFF ( 0) + #define MCMNTS_CR_SC_WDBWM_WMM_Enter_WID ( 8) + #define MCMNTS_CR_SC_WDBWM_WMM_Enter_MSK (0x000000FF) + #define MCMNTS_CR_SC_WDBWM_WMM_Enter_MAX (0x000000FF) + #define MCMNTS_CR_SC_WDBWM_WMM_Enter_DEF (0x00000038) + #define MCMNTS_CR_SC_WDBWM_WMM_Exit_OFF ( 8) + #define MCMNTS_CR_SC_WDBWM_WMM_Exit_WID ( 8) + #define MCMNTS_CR_SC_WDBWM_WMM_Exit_MSK (0x0000FF00) + #define MCMNTS_CR_SC_WDBWM_WMM_Exit_MAX (0x000000FF) + #define MCMNTS_CR_SC_WDBWM_WMM_Exit_DEF (0x00000030) + #define MCMNTS_CR_SC_WDBWM_WPQ_IS_OFF (16) + #define MCMNTS_CR_SC_WDBWM_WPQ_IS_WID ( 8) + #define MCMNTS_CR_SC_WDBWM_WPQ_IS_MSK (0x00FF0000) + #define MCMNTS_CR_SC_WDBWM_WPQ_IS_MAX (0x000000FF) + #define MCMNTS_CR_SC_WDBWM_WPQ_IS_DEF (0x0000003C) + #define MCMNTS_CR_SC_WDBWM_Starve_count_OFF (24) + #define MCMNTS_CR_SC_WDBWM_Starve_count_WID ( 8) + #define MCMNTS_CR_SC_WDBWM_Starve_count_MSK (0xFF000000) + #define MCMNTS_CR_SC_WDBWM_Starve_count_MAX (0x000000FF) + #define MCMNTS_CR_SC_WDBWM_Starve_count_DEF (0x000000FF) + +#define MCMNTS_CR_VISA_CTL_MCMNTS_REG (0x00004F90) + #define MCMNTS_CR_VISA_CTL_MCMNTS_Data_OFF ( 0) + #define MCMNTS_CR_VISA_CTL_MCMNTS_Data_WID (18) + #define MCMNTS_CR_VISA_CTL_MCMNTS_Data_MSK (0x0003FFFF) + #define MCMNTS_CR_VISA_CTL_MCMNTS_Data_MAX (0x0003FFFF) + #define MCMNTS_CR_VISA_CTL_MCMNTS_Data_DEF (0x00000000) + #define MCMNTS_CR_VISA_CTL_MCMNTS_VORANGE_OFF (31) + #define MCMNTS_CR_VISA_CTL_MCMNTS_VORANGE_WID ( 1) + #define MCMNTS_CR_VISA_CTL_MCMNTS_VORANGE_MSK (0x80000000) + #define MCMNTS_CR_VISA_CTL_MCMNTS_VORANGE_MAX (0x00000001) + #define MCMNTS_CR_VISA_CTL_MCMNTS_VORANGE_DEF (0x00000000) + +#define MCDECS_CR_MAD_CHNL_MCMAIN_REG (0x00005000) + #define MCDECS_CR_MAD_CHNL_MCMAIN_CH_A_OFF ( 0) + #define MCDECS_CR_MAD_CHNL_MCMAIN_CH_A_WID ( 2) + #define MCDECS_CR_MAD_CHNL_MCMAIN_CH_A_MSK (0x00000003) + #define MCDECS_CR_MAD_CHNL_MCMAIN_CH_A_MAX (0x00000003) + #define MCDECS_CR_MAD_CHNL_MCMAIN_CH_A_DEF (0x00000000) + #define MCDECS_CR_MAD_CHNL_MCMAIN_CH_B_OFF ( 2) + #define MCDECS_CR_MAD_CHNL_MCMAIN_CH_B_WID ( 2) + #define MCDECS_CR_MAD_CHNL_MCMAIN_CH_B_MSK (0x0000000C) + #define MCDECS_CR_MAD_CHNL_MCMAIN_CH_B_MAX (0x00000003) + #define MCDECS_CR_MAD_CHNL_MCMAIN_CH_B_DEF (0x00000001) + #define MCDECS_CR_MAD_CHNL_MCMAIN_CH_C_OFF ( 4) + #define MCDECS_CR_MAD_CHNL_MCMAIN_CH_C_WID ( 2) + #define MCDECS_CR_MAD_CHNL_MCMAIN_CH_C_MSK (0x00000030) + #define MCDECS_CR_MAD_CHNL_MCMAIN_CH_C_MAX (0x00000003) + #define MCDECS_CR_MAD_CHNL_MCMAIN_CH_C_DEF (0x00000002) + #define MCDECS_CR_MAD_CHNL_MCMAIN_STKD_MODE_OFF ( 6) + #define MCDECS_CR_MAD_CHNL_MCMAIN_STKD_MODE_WID ( 1) + #define MCDECS_CR_MAD_CHNL_MCMAIN_STKD_MODE_MSK (0x00000040) + #define MCDECS_CR_MAD_CHNL_MCMAIN_STKD_MODE_MAX (0x00000001) + #define MCDECS_CR_MAD_CHNL_MCMAIN_STKD_MODE_DEF (0x00000000) + #define MCDECS_CR_MAD_CHNL_MCMAIN_STKD_MODE_CH_BITS_OFF ( 7) + #define MCDECS_CR_MAD_CHNL_MCMAIN_STKD_MODE_CH_BITS_WID ( 3) + #define MCDECS_CR_MAD_CHNL_MCMAIN_STKD_MODE_CH_BITS_MSK (0x00000380) + #define MCDECS_CR_MAD_CHNL_MCMAIN_STKD_MODE_CH_BITS_MAX (0x00000007) + #define MCDECS_CR_MAD_CHNL_MCMAIN_STKD_MODE_CH_BITS_DEF (0x00000000) + #define MCDECS_CR_MAD_CHNL_MCMAIN_LPDDR_OFF (10) + #define MCDECS_CR_MAD_CHNL_MCMAIN_LPDDR_WID ( 1) + #define MCDECS_CR_MAD_CHNL_MCMAIN_LPDDR_MSK (0x00000400) + #define MCDECS_CR_MAD_CHNL_MCMAIN_LPDDR_MAX (0x00000001) + #define MCDECS_CR_MAD_CHNL_MCMAIN_LPDDR_DEF (0x00000000) + +#define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_REG (0x00005004) + #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_DIMM_A_Size_OFF ( 0) + #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_DIMM_A_Size_WID ( 8) + #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_DIMM_A_Size_MSK (0x000000FF) + #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_DIMM_A_Size_MAX (0x000000FF) + #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_DIMM_A_Size_DEF (0x00000000) + #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_DIMM_B_Size_OFF ( 8) + #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_DIMM_B_Size_WID ( 8) + #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_DIMM_B_Size_MSK (0x0000FF00) + #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_DIMM_B_Size_MAX (0x000000FF) + #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_DIMM_B_Size_DEF (0x00000000) + #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_DAS_OFF (16) + #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_DAS_WID ( 1) + #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_DAS_MSK (0x00010000) + #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_DAS_MAX (0x00000001) + #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_DAS_DEF (0x00000000) + #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_DANOR_OFF (17) + #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_DANOR_WID ( 1) + #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_DANOR_MSK (0x00020000) + #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_DANOR_MAX (0x00000001) + #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_DANOR_DEF (0x00000000) + #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_DBNOR_OFF (18) + #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_DBNOR_WID ( 1) + #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_DBNOR_MSK (0x00040000) + #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_DBNOR_MAX (0x00000001) + #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_DBNOR_DEF (0x00000000) + #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_DAW_OFF (19) + #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_DAW_WID ( 1) + #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_DAW_MSK (0x00080000) + #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_DAW_MAX (0x00000001) + #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_DAW_DEF (0x00000000) + #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_DBW_OFF (20) + #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_DBW_WID ( 1) + #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_DBW_MSK (0x00100000) + #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_DBW_MAX (0x00000001) + #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_DBW_DEF (0x00000000) + #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_RI_OFF (21) + #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_RI_WID ( 1) + #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_RI_MSK (0x00200000) + #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_RI_MAX (0x00000001) + #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_RI_DEF (0x00000001) + #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_Enh_Interleave_OFF (22) + #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_Enh_Interleave_WID ( 1) + #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_Enh_Interleave_MSK (0x00400000) + #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_Enh_Interleave_MAX (0x00000001) + #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_Enh_Interleave_DEF (0x00000001) + #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_ECC_OFF (24) + #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_ECC_WID ( 2) + #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_ECC_MSK (0x03000000) + #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_ECC_MAX (0x00000003) + #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_ECC_DEF (0x00000000) + #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_HORI_OFF (26) + #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_HORI_WID ( 1) + #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_HORI_MSK (0x04000000) + #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_HORI_MAX (0x00000001) + #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_HORI_DEF (0x00000000) + #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_HORIAddr_OFF (27) + #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_HORIAddr_WID ( 3) + #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_HORIAddr_MSK (0x38000000) + #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_HORIAddr_MAX (0x00000007) + #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_HORIAddr_DEF (0x00000000) + +#define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_REG (0x00005008) + #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_DIMM_A_Size_OFF ( 0) + #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_DIMM_A_Size_WID ( 8) + #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_DIMM_A_Size_MSK (0x000000FF) + #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_DIMM_A_Size_MAX (0x000000FF) + #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_DIMM_A_Size_DEF (0x00000000) + #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_DIMM_B_Size_OFF ( 8) + #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_DIMM_B_Size_WID ( 8) + #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_DIMM_B_Size_MSK (0x0000FF00) + #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_DIMM_B_Size_MAX (0x000000FF) + #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_DIMM_B_Size_DEF (0x00000000) + #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_DAS_OFF (16) + #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_DAS_WID ( 1) + #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_DAS_MSK (0x00010000) + #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_DAS_MAX (0x00000001) + #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_DAS_DEF (0x00000000) + #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_DANOR_OFF (17) + #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_DANOR_WID ( 1) + #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_DANOR_MSK (0x00020000) + #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_DANOR_MAX (0x00000001) + #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_DANOR_DEF (0x00000000) + #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_DBNOR_OFF (18) + #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_DBNOR_WID ( 1) + #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_DBNOR_MSK (0x00040000) + #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_DBNOR_MAX (0x00000001) + #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_DBNOR_DEF (0x00000000) + #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_DAW_OFF (19) + #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_DAW_WID ( 1) + #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_DAW_MSK (0x00080000) + #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_DAW_MAX (0x00000001) + #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_DAW_DEF (0x00000000) + #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_DBW_OFF (20) + #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_DBW_WID ( 1) + #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_DBW_MSK (0x00100000) + #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_DBW_MAX (0x00000001) + #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_DBW_DEF (0x00000000) + #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_RI_OFF (21) + #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_RI_WID ( 1) + #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_RI_MSK (0x00200000) + #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_RI_MAX (0x00000001) + #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_RI_DEF (0x00000001) + #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_Enh_Interleave_OFF (22) + #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_Enh_Interleave_WID ( 1) + #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_Enh_Interleave_MSK (0x00400000) + #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_Enh_Interleave_MAX (0x00000001) + #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_Enh_Interleave_DEF (0x00000001) + #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_ECC_OFF (24) + #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_ECC_WID ( 2) + #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_ECC_MSK (0x03000000) + #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_ECC_MAX (0x00000003) + #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_ECC_DEF (0x00000000) + #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_HORI_OFF (26) + #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_HORI_WID ( 1) + #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_HORI_MSK (0x04000000) + #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_HORI_MAX (0x00000001) + #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_HORI_DEF (0x00000000) + #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_HORIAddr_OFF (27) + #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_HORIAddr_WID ( 3) + #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_HORIAddr_MSK (0x38000000) + #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_HORIAddr_MAX (0x00000007) + #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_HORIAddr_DEF (0x00000000) + +#define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_REG (0x0000500C) + #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_DIMM_A_Size_OFF ( 0) + #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_DIMM_A_Size_WID ( 8) + #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_DIMM_A_Size_MSK (0x000000FF) + #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_DIMM_A_Size_MAX (0x000000FF) + #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_DIMM_A_Size_DEF (0x00000000) + #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_DIMM_B_Size_OFF ( 8) + #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_DIMM_B_Size_WID ( 8) + #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_DIMM_B_Size_MSK (0x0000FF00) + #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_DIMM_B_Size_MAX (0x000000FF) + #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_DIMM_B_Size_DEF (0x00000000) + #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_DAS_OFF (16) + #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_DAS_WID ( 1) + #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_DAS_MSK (0x00010000) + #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_DAS_MAX (0x00000001) + #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_DAS_DEF (0x00000000) + #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_DANOR_OFF (17) + #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_DANOR_WID ( 1) + #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_DANOR_MSK (0x00020000) + #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_DANOR_MAX (0x00000001) + #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_DANOR_DEF (0x00000000) + #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_DBNOR_OFF (18) + #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_DBNOR_WID ( 1) + #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_DBNOR_MSK (0x00040000) + #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_DBNOR_MAX (0x00000001) + #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_DBNOR_DEF (0x00000000) + #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_DAW_OFF (19) + #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_DAW_WID ( 1) + #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_DAW_MSK (0x00080000) + #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_DAW_MAX (0x00000001) + #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_DAW_DEF (0x00000000) + #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_DBW_OFF (20) + #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_DBW_WID ( 1) + #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_DBW_MSK (0x00100000) + #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_DBW_MAX (0x00000001) + #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_DBW_DEF (0x00000000) + #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_RI_OFF (21) + #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_RI_WID ( 1) + #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_RI_MSK (0x00200000) + #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_RI_MAX (0x00000001) + #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_RI_DEF (0x00000001) + #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_Enh_Interleave_OFF (22) + #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_Enh_Interleave_WID ( 1) + #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_Enh_Interleave_MSK (0x00400000) + #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_Enh_Interleave_MAX (0x00000001) + #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_Enh_Interleave_DEF (0x00000001) + #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_ECC_OFF (24) + #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_ECC_WID ( 2) + #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_ECC_MSK (0x03000000) + #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_ECC_MAX (0x00000003) + #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_ECC_DEF (0x00000000) + #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_HORI_OFF (26) + #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_HORI_WID ( 1) + #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_HORI_MSK (0x04000000) + #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_HORI_MAX (0x00000001) + #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_HORI_DEF (0x00000000) + #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_HORIAddr_OFF (27) + #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_HORIAddr_WID ( 3) + #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_HORIAddr_MSK (0x38000000) + #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_HORIAddr_MAX (0x00000007) + #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_HORIAddr_DEF (0x00000000) + +#define MCDECS_CR_MAD_ZR_MCMAIN_REG (0x00005014) + #define MCDECS_CR_MAD_ZR_MCMAIN_OneC_OFF ( 0) + #define MCDECS_CR_MAD_ZR_MCMAIN_OneC_WID ( 8) + #define MCDECS_CR_MAD_ZR_MCMAIN_OneC_MSK (0x000000FF) + #define MCDECS_CR_MAD_ZR_MCMAIN_OneC_MAX (0x000000FF) + #define MCDECS_CR_MAD_ZR_MCMAIN_OneC_DEF (0x00000000) + #define MCDECS_CR_MAD_ZR_MCMAIN_ThreeC_OFF ( 8) + #define MCDECS_CR_MAD_ZR_MCMAIN_ThreeC_WID ( 8) + #define MCDECS_CR_MAD_ZR_MCMAIN_ThreeC_MSK (0x0000FF00) + #define MCDECS_CR_MAD_ZR_MCMAIN_ThreeC_MAX (0x000000FF) + #define MCDECS_CR_MAD_ZR_MCMAIN_ThreeC_DEF (0x00000000) + #define MCDECS_CR_MAD_ZR_MCMAIN_TwoBandC_OFF (16) + #define MCDECS_CR_MAD_ZR_MCMAIN_TwoBandC_WID ( 8) + #define MCDECS_CR_MAD_ZR_MCMAIN_TwoBandC_MSK (0x00FF0000) + #define MCDECS_CR_MAD_ZR_MCMAIN_TwoBandC_MAX (0x000000FF) + #define MCDECS_CR_MAD_ZR_MCMAIN_TwoBandC_DEF (0x00000000) + #define MCDECS_CR_MAD_ZR_MCMAIN_BandC_OFF (24) + #define MCDECS_CR_MAD_ZR_MCMAIN_BandC_WID ( 8) + #define MCDECS_CR_MAD_ZR_MCMAIN_BandC_MSK (0xFF000000) + #define MCDECS_CR_MAD_ZR_MCMAIN_BandC_MAX (0x000000FF) + #define MCDECS_CR_MAD_ZR_MCMAIN_BandC_DEF (0x00000000) + +#define MCDECS_CR_MCDECS_MISC_MCMAIN_REG (0x00005018) + #define MCDECS_CR_MCDECS_MISC_MCMAIN_spare_OFF ( 0) + #define MCDECS_CR_MCDECS_MISC_MCMAIN_spare_WID (23) + #define MCDECS_CR_MCDECS_MISC_MCMAIN_spare_MSK (0x007FFFFF) + #define MCDECS_CR_MCDECS_MISC_MCMAIN_spare_MAX (0x007FFFFF) + #define MCDECS_CR_MCDECS_MISC_MCMAIN_spare_DEF (0x00000000) + #define MCDECS_CR_MCDECS_MISC_MCMAIN_ovrd_pcu_sr_exit_OFF (23) + #define MCDECS_CR_MCDECS_MISC_MCMAIN_ovrd_pcu_sr_exit_WID ( 1) + #define MCDECS_CR_MCDECS_MISC_MCMAIN_ovrd_pcu_sr_exit_MSK (0x00800000) + #define MCDECS_CR_MCDECS_MISC_MCMAIN_ovrd_pcu_sr_exit_MAX (0x00000001) + #define MCDECS_CR_MCDECS_MISC_MCMAIN_ovrd_pcu_sr_exit_DEF (0x00000000) + #define MCDECS_CR_MCDECS_MISC_MCMAIN_isoch_stall_pattern_OFF (24) + #define MCDECS_CR_MCDECS_MISC_MCMAIN_isoch_stall_pattern_WID ( 8) + #define MCDECS_CR_MCDECS_MISC_MCMAIN_isoch_stall_pattern_MSK (0xFF000000) + #define MCDECS_CR_MCDECS_MISC_MCMAIN_isoch_stall_pattern_MAX (0x000000FF) + #define MCDECS_CR_MCDECS_MISC_MCMAIN_isoch_stall_pattern_DEF (0x00000000) + +#define MCDECS_CR_MCDECS_CBIT_MCMAIN_REG (0x0000501C) + #define MCDECS_CR_MCDECS_CBIT_MCMAIN_increase_rcomp_OFF ( 0) + #define MCDECS_CR_MCDECS_CBIT_MCMAIN_increase_rcomp_WID ( 1) + #define MCDECS_CR_MCDECS_CBIT_MCMAIN_increase_rcomp_MSK (0x00000001) + #define MCDECS_CR_MCDECS_CBIT_MCMAIN_increase_rcomp_MAX (0x00000001) + #define MCDECS_CR_MCDECS_CBIT_MCMAIN_increase_rcomp_DEF (0x00000000) + #define MCDECS_CR_MCDECS_CBIT_MCMAIN_noa_on_ecc_OFF ( 1) + #define MCDECS_CR_MCDECS_CBIT_MCMAIN_noa_on_ecc_WID ( 1) + #define MCDECS_CR_MCDECS_CBIT_MCMAIN_noa_on_ecc_MSK (0x00000002) + #define MCDECS_CR_MCDECS_CBIT_MCMAIN_noa_on_ecc_MAX (0x00000001) + #define MCDECS_CR_MCDECS_CBIT_MCMAIN_noa_on_ecc_DEF (0x00000000) + #define MCDECS_CR_MCDECS_CBIT_MCMAIN_noa_demux_OFF ( 2) + #define MCDECS_CR_MCDECS_CBIT_MCMAIN_noa_demux_WID ( 1) + #define MCDECS_CR_MCDECS_CBIT_MCMAIN_noa_demux_MSK (0x00000004) + #define MCDECS_CR_MCDECS_CBIT_MCMAIN_noa_demux_MAX (0x00000001) + #define MCDECS_CR_MCDECS_CBIT_MCMAIN_noa_demux_DEF (0x00000000) + #define MCDECS_CR_MCDECS_CBIT_MCMAIN_noa_countctrl_OFF ( 3) + #define MCDECS_CR_MCDECS_CBIT_MCMAIN_noa_countctrl_WID ( 1) + #define MCDECS_CR_MCDECS_CBIT_MCMAIN_noa_countctrl_MSK (0x00000008) + #define MCDECS_CR_MCDECS_CBIT_MCMAIN_noa_countctrl_MAX (0x00000001) + #define MCDECS_CR_MCDECS_CBIT_MCMAIN_noa_countctrl_DEF (0x00000000) + #define MCDECS_CR_MCDECS_CBIT_MCMAIN_psmi_freeze_pwm_counters_OFF ( 8) + #define MCDECS_CR_MCDECS_CBIT_MCMAIN_psmi_freeze_pwm_counters_WID ( 1) + #define MCDECS_CR_MCDECS_CBIT_MCMAIN_psmi_freeze_pwm_counters_MSK (0x00000100) + #define MCDECS_CR_MCDECS_CBIT_MCMAIN_psmi_freeze_pwm_counters_MAX (0x00000001) + #define MCDECS_CR_MCDECS_CBIT_MCMAIN_psmi_freeze_pwm_counters_DEF (0x00000000) + #define MCDECS_CR_MCDECS_CBIT_MCMAIN_dis_lp_prefetch_OFF (15) + #define MCDECS_CR_MCDECS_CBIT_MCMAIN_dis_lp_prefetch_WID ( 1) + #define MCDECS_CR_MCDECS_CBIT_MCMAIN_dis_lp_prefetch_MSK (0x00008000) + #define MCDECS_CR_MCDECS_CBIT_MCMAIN_dis_lp_prefetch_MAX (0x00000001) + #define MCDECS_CR_MCDECS_CBIT_MCMAIN_dis_lp_prefetch_DEF (0x00000000) + #define MCDECS_CR_MCDECS_CBIT_MCMAIN_dis_reg_clk_gate_OFF (29) + #define MCDECS_CR_MCDECS_CBIT_MCMAIN_dis_reg_clk_gate_WID ( 1) + #define MCDECS_CR_MCDECS_CBIT_MCMAIN_dis_reg_clk_gate_MSK (0x20000000) + #define MCDECS_CR_MCDECS_CBIT_MCMAIN_dis_reg_clk_gate_MAX (0x00000001) + #define MCDECS_CR_MCDECS_CBIT_MCMAIN_dis_reg_clk_gate_DEF (0x00000000) + #define MCDECS_CR_MCDECS_CBIT_MCMAIN_dis_msg_clk_gate_OFF (30) + #define MCDECS_CR_MCDECS_CBIT_MCMAIN_dis_msg_clk_gate_WID ( 1) + #define MCDECS_CR_MCDECS_CBIT_MCMAIN_dis_msg_clk_gate_MSK (0x40000000) + #define MCDECS_CR_MCDECS_CBIT_MCMAIN_dis_msg_clk_gate_MAX (0x00000001) + #define MCDECS_CR_MCDECS_CBIT_MCMAIN_dis_msg_clk_gate_DEF (0x00000001) + #define MCDECS_CR_MCDECS_CBIT_MCMAIN_dis_clk_gate_OFF (31) + #define MCDECS_CR_MCDECS_CBIT_MCMAIN_dis_clk_gate_WID ( 1) + #define MCDECS_CR_MCDECS_CBIT_MCMAIN_dis_clk_gate_MSK (0x80000000) + #define MCDECS_CR_MCDECS_CBIT_MCMAIN_dis_clk_gate_MAX (0x00000001) + #define MCDECS_CR_MCDECS_CBIT_MCMAIN_dis_clk_gate_DEF (0x00000000) + +#define MCDECS_CR_SC_IS_CREDIT_MCMAIN_REG (0x00005020) + #define MCDECS_CR_SC_IS_CREDIT_MCMAIN_count_OFF ( 0) + #define MCDECS_CR_SC_IS_CREDIT_MCMAIN_count_WID ( 4) + #define MCDECS_CR_SC_IS_CREDIT_MCMAIN_count_MSK (0x0000000F) + #define MCDECS_CR_SC_IS_CREDIT_MCMAIN_count_MAX (0x0000000F) + #define MCDECS_CR_SC_IS_CREDIT_MCMAIN_count_DEF (0x00000008) + +#define MCDECS_CR_CHANNEL_HASH_MCMAIN_REG (0x00005024) + #define MCDECS_CR_CHANNEL_HASH_MCMAIN_Mask_OFF ( 0) + #define MCDECS_CR_CHANNEL_HASH_MCMAIN_Mask_WID (14) + #define MCDECS_CR_CHANNEL_HASH_MCMAIN_Mask_MSK (0x00003FFF) + #define MCDECS_CR_CHANNEL_HASH_MCMAIN_Mask_MAX (0x00003FFF) + #define MCDECS_CR_CHANNEL_HASH_MCMAIN_Mask_DEF (0x00000000) + #define MCDECS_CR_CHANNEL_HASH_MCMAIN_LSB_mask_bit_OFF (21) + #define MCDECS_CR_CHANNEL_HASH_MCMAIN_LSB_mask_bit_WID ( 2) + #define MCDECS_CR_CHANNEL_HASH_MCMAIN_LSB_mask_bit_MSK (0x00600000) + #define MCDECS_CR_CHANNEL_HASH_MCMAIN_LSB_mask_bit_MAX (0x00000003) + #define MCDECS_CR_CHANNEL_HASH_MCMAIN_LSB_mask_bit_DEF (0x00000000) + #define MCDECS_CR_CHANNEL_HASH_MCMAIN_Enable_OFF (23) + #define MCDECS_CR_CHANNEL_HASH_MCMAIN_Enable_WID ( 1) + #define MCDECS_CR_CHANNEL_HASH_MCMAIN_Enable_MSK (0x00800000) + #define MCDECS_CR_CHANNEL_HASH_MCMAIN_Enable_MAX (0x00000001) + #define MCDECS_CR_CHANNEL_HASH_MCMAIN_Enable_DEF (0x00000000) + +#define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_REG (0x00005030) + #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_pu_mrc_done_OFF ( 0) + #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_pu_mrc_done_WID ( 1) + #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_pu_mrc_done_MSK (0x00000001) + #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_pu_mrc_done_MAX (0x00000001) + #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_pu_mrc_done_DEF (0x00000000) + #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_ddr_reset_OFF ( 1) + #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_ddr_reset_WID ( 1) + #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_ddr_reset_MSK (0x00000002) + #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_ddr_reset_MAX (0x00000001) + #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_ddr_reset_DEF (0x00000001) + #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_refresh_enable_OFF ( 3) + #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_refresh_enable_WID ( 1) + #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_refresh_enable_MSK (0x00000008) + #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_refresh_enable_MAX (0x00000001) + #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_refresh_enable_DEF (0x00000000) + #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_mc_init_done_ack_OFF ( 5) + #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_mc_init_done_ack_WID ( 1) + #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_mc_init_done_ack_MSK (0x00000020) + #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_mc_init_done_ack_MAX (0x00000001) + #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_mc_init_done_ack_DEF (0x00000000) + #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_mrc_done_OFF ( 7) + #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_mrc_done_WID ( 1) + #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_mrc_done_MSK (0x00000080) + #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_mrc_done_MAX (0x00000001) + #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_mrc_done_DEF (0x00000000) + #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_safe_sr_OFF ( 8) + #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_safe_sr_WID ( 1) + #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_safe_sr_MSK (0x00000100) + #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_safe_sr_MAX (0x00000001) + #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_safe_sr_DEF (0x00000001) + #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_HVM_Gate_DDR_Reset_OFF (10) + #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_HVM_Gate_DDR_Reset_WID ( 1) + #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_HVM_Gate_DDR_Reset_MSK (0x00000400) + #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_HVM_Gate_DDR_Reset_MAX (0x00000001) + #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_HVM_Gate_DDR_Reset_DEF (0x00000000) + #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_dclk_enable_OFF (22) + #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_dclk_enable_WID ( 1) + #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_dclk_enable_MSK (0x00400000) + #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_dclk_enable_MAX (0x00000001) + #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_dclk_enable_DEF (0x00000000) + #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_reset_io_OFF (23) + #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_reset_io_WID ( 1) + #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_reset_io_MSK (0x00800000) + #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_reset_io_MAX (0x00000001) + #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_reset_io_DEF (0x00000000) + +#define MCDECS_CR_MRC_REVISION_MCMAIN_REG (0x00005034) + #define MCDECS_CR_MRC_REVISION_MCMAIN_REVISION_OFF ( 0) + #define MCDECS_CR_MRC_REVISION_MCMAIN_REVISION_WID (32) + #define MCDECS_CR_MRC_REVISION_MCMAIN_REVISION_MSK (0xFFFFFFFF) + #define MCDECS_CR_MRC_REVISION_MCMAIN_REVISION_MAX (0xFFFFFFFF) + #define MCDECS_CR_MRC_REVISION_MCMAIN_REVISION_DEF (0x00000000) + +#define MCDECS_CR_PWM_GT_REQCOUNT_MCMAIN_REG (0x00005040) + #define MCDECS_CR_PWM_GT_REQCOUNT_MCMAIN_count_OFF ( 0) + #define MCDECS_CR_PWM_GT_REQCOUNT_MCMAIN_count_WID (32) + #define MCDECS_CR_PWM_GT_REQCOUNT_MCMAIN_count_MSK (0xFFFFFFFF) + #define MCDECS_CR_PWM_GT_REQCOUNT_MCMAIN_count_MAX (0xFFFFFFFF) + #define MCDECS_CR_PWM_GT_REQCOUNT_MCMAIN_count_DEF (0x00000000) + +#define MCDECS_CR_PWM_IA_REQCOUNT_MCMAIN_REG (0x00005044) + #define MCDECS_CR_PWM_IA_REQCOUNT_MCMAIN_count_OFF ( 0) + #define MCDECS_CR_PWM_IA_REQCOUNT_MCMAIN_count_WID (32) + #define MCDECS_CR_PWM_IA_REQCOUNT_MCMAIN_count_MSK (0xFFFFFFFF) + #define MCDECS_CR_PWM_IA_REQCOUNT_MCMAIN_count_MAX (0xFFFFFFFF) + #define MCDECS_CR_PWM_IA_REQCOUNT_MCMAIN_count_DEF (0x00000000) + +#define MCDECS_CR_PWM_IO_REQCOUNT_MCMAIN_REG (0x00005048) + #define MCDECS_CR_PWM_IO_REQCOUNT_MCMAIN_count_OFF ( 0) + #define MCDECS_CR_PWM_IO_REQCOUNT_MCMAIN_count_WID (32) + #define MCDECS_CR_PWM_IO_REQCOUNT_MCMAIN_count_MSK (0xFFFFFFFF) + #define MCDECS_CR_PWM_IO_REQCOUNT_MCMAIN_count_MAX (0xFFFFFFFF) + #define MCDECS_CR_PWM_IO_REQCOUNT_MCMAIN_count_DEF (0x00000000) + +#define MCDECS_CR_PWM_RDDATA_COUNT_MCMAIN_REG (0x00005050) + #define MCDECS_CR_PWM_RDDATA_COUNT_MCMAIN_count_OFF ( 0) + #define MCDECS_CR_PWM_RDDATA_COUNT_MCMAIN_count_WID (32) + #define MCDECS_CR_PWM_RDDATA_COUNT_MCMAIN_count_MSK (0xFFFFFFFF) + #define MCDECS_CR_PWM_RDDATA_COUNT_MCMAIN_count_MAX (0xFFFFFFFF) + #define MCDECS_CR_PWM_RDDATA_COUNT_MCMAIN_count_DEF (0x00000000) + +#define MCDECS_CR_PWM_WRDATA_COUNT_MCMAIN_REG (0x00005054) + #define MCDECS_CR_PWM_WRDATA_COUNT_MCMAIN_count_OFF ( 0) + #define MCDECS_CR_PWM_WRDATA_COUNT_MCMAIN_count_WID (32) + #define MCDECS_CR_PWM_WRDATA_COUNT_MCMAIN_count_MSK (0xFFFFFFFF) + #define MCDECS_CR_PWM_WRDATA_COUNT_MCMAIN_count_MAX (0xFFFFFFFF) + #define MCDECS_CR_PWM_WRDATA_COUNT_MCMAIN_count_DEF (0x00000000) + +#define MCDECS_CR_PWM_COMMAND_COUNT_MCMAIN_REG (0x00005058) + #define MCDECS_CR_PWM_COMMAND_COUNT_MCMAIN_count_OFF ( 0) + #define MCDECS_CR_PWM_COMMAND_COUNT_MCMAIN_count_WID (32) + #define MCDECS_CR_PWM_COMMAND_COUNT_MCMAIN_count_MSK (0xFFFFFFFF) + #define MCDECS_CR_PWM_COMMAND_COUNT_MCMAIN_count_MAX (0xFFFFFFFF) + #define MCDECS_CR_PWM_COMMAND_COUNT_MCMAIN_count_DEF (0x00000000) + +#define MCDECS_CR_PM_SREF_CONFIG_MCMAIN_REG (0x00005060) + #define MCDECS_CR_PM_SREF_CONFIG_MCMAIN_Idle_timer_OFF ( 0) + #define MCDECS_CR_PM_SREF_CONFIG_MCMAIN_Idle_timer_WID (16) + #define MCDECS_CR_PM_SREF_CONFIG_MCMAIN_Idle_timer_MSK (0x0000FFFF) + #define MCDECS_CR_PM_SREF_CONFIG_MCMAIN_Idle_timer_MAX (0x0000FFFF) + #define MCDECS_CR_PM_SREF_CONFIG_MCMAIN_Idle_timer_DEF (0x00000200) + #define MCDECS_CR_PM_SREF_CONFIG_MCMAIN_SR_Enable_OFF (16) + #define MCDECS_CR_PM_SREF_CONFIG_MCMAIN_SR_Enable_WID ( 1) + #define MCDECS_CR_PM_SREF_CONFIG_MCMAIN_SR_Enable_MSK (0x00010000) + #define MCDECS_CR_PM_SREF_CONFIG_MCMAIN_SR_Enable_MAX (0x00000001) + #define MCDECS_CR_PM_SREF_CONFIG_MCMAIN_SR_Enable_DEF (0x00000001) + +#define MCDECS_CR_MCI_CONFIG_MCMAIN_REG (0x00005070) + #define MCDECS_CR_MCI_CONFIG_MCMAIN_Ch_dir_OFF ( 0) + #define MCDECS_CR_MCI_CONFIG_MCMAIN_Ch_dir_WID ( 4) + #define MCDECS_CR_MCI_CONFIG_MCMAIN_Ch_dir_MSK (0x0000000F) + #define MCDECS_CR_MCI_CONFIG_MCMAIN_Ch_dir_MAX (0x0000000F) + #define MCDECS_CR_MCI_CONFIG_MCMAIN_Ch_dir_DEF (0x00000000) + #define MCDECS_CR_MCI_CONFIG_MCMAIN_MCI_clk_div_OFF ( 8) + #define MCDECS_CR_MCI_CONFIG_MCMAIN_MCI_clk_div_WID (10) + #define MCDECS_CR_MCI_CONFIG_MCMAIN_MCI_clk_div_MSK (0x0003FF00) + #define MCDECS_CR_MCI_CONFIG_MCMAIN_MCI_clk_div_MAX (0x000003FF) + #define MCDECS_CR_MCI_CONFIG_MCMAIN_MCI_clk_div_DEF (0x00000000) + +#define MCDECS_CR_STALL_DRAIN_MCMAIN_REG (0x00005074) + #define MCDECS_CR_STALL_DRAIN_MCMAIN_stall_until_drain_OFF ( 0) + #define MCDECS_CR_STALL_DRAIN_MCMAIN_stall_until_drain_WID ( 1) + #define MCDECS_CR_STALL_DRAIN_MCMAIN_stall_until_drain_MSK (0x00000001) + #define MCDECS_CR_STALL_DRAIN_MCMAIN_stall_until_drain_MAX (0x00000001) + #define MCDECS_CR_STALL_DRAIN_MCMAIN_stall_until_drain_DEF (0x00000000) + #define MCDECS_CR_STALL_DRAIN_MCMAIN_stall_input_OFF ( 1) + #define MCDECS_CR_STALL_DRAIN_MCMAIN_stall_input_WID ( 1) + #define MCDECS_CR_STALL_DRAIN_MCMAIN_stall_input_MSK (0x00000002) + #define MCDECS_CR_STALL_DRAIN_MCMAIN_stall_input_MAX (0x00000001) + #define MCDECS_CR_STALL_DRAIN_MCMAIN_stall_input_DEF (0x00000000) + #define MCDECS_CR_STALL_DRAIN_MCMAIN_mc_drained_OFF ( 4) + #define MCDECS_CR_STALL_DRAIN_MCMAIN_mc_drained_WID ( 1) + #define MCDECS_CR_STALL_DRAIN_MCMAIN_mc_drained_MSK (0x00000010) + #define MCDECS_CR_STALL_DRAIN_MCMAIN_mc_drained_MAX (0x00000001) + #define MCDECS_CR_STALL_DRAIN_MCMAIN_mc_drained_DEF (0x00000000) + #define MCDECS_CR_STALL_DRAIN_MCMAIN_sr_state_OFF ( 8) + #define MCDECS_CR_STALL_DRAIN_MCMAIN_sr_state_WID ( 2) + #define MCDECS_CR_STALL_DRAIN_MCMAIN_sr_state_MSK (0x00000300) + #define MCDECS_CR_STALL_DRAIN_MCMAIN_sr_state_MAX (0x00000003) + #define MCDECS_CR_STALL_DRAIN_MCMAIN_sr_state_DEF (0x00000000) + +#define MCDECS_CR_QUEUE_CREDIT_C_MCMAIN_REG (0x00005080) + #define MCDECS_CR_QUEUE_CREDIT_C_MCMAIN_RPQ_count_OFF ( 0) + #define MCDECS_CR_QUEUE_CREDIT_C_MCMAIN_RPQ_count_WID ( 5) + #define MCDECS_CR_QUEUE_CREDIT_C_MCMAIN_RPQ_count_MSK (0x0000001F) + #define MCDECS_CR_QUEUE_CREDIT_C_MCMAIN_RPQ_count_MAX (0x0000001F) + #define MCDECS_CR_QUEUE_CREDIT_C_MCMAIN_RPQ_count_DEF (0x0000001C) + #define MCDECS_CR_QUEUE_CREDIT_C_MCMAIN_WPQ_count_OFF ( 8) + #define MCDECS_CR_QUEUE_CREDIT_C_MCMAIN_WPQ_count_WID ( 7) + #define MCDECS_CR_QUEUE_CREDIT_C_MCMAIN_WPQ_count_MSK (0x00007F00) + #define MCDECS_CR_QUEUE_CREDIT_C_MCMAIN_WPQ_count_MAX (0x0000007F) + #define MCDECS_CR_QUEUE_CREDIT_C_MCMAIN_WPQ_count_DEF (0x00000040) + +#define MCDECS_CR_RCOMP_TIMER_MCMAIN_REG (0x00005084) + #define MCDECS_CR_RCOMP_TIMER_MCMAIN_count_OFF ( 0) + #define MCDECS_CR_RCOMP_TIMER_MCMAIN_count_WID (16) + #define MCDECS_CR_RCOMP_TIMER_MCMAIN_count_MSK (0x0000FFFF) + #define MCDECS_CR_RCOMP_TIMER_MCMAIN_count_MAX (0x0000FFFF) + #define MCDECS_CR_RCOMP_TIMER_MCMAIN_count_DEF (0x00000CFF) + #define MCDECS_CR_RCOMP_TIMER_MCMAIN_First_Rcomp_done_OFF (16) + #define MCDECS_CR_RCOMP_TIMER_MCMAIN_First_Rcomp_done_WID ( 1) + #define MCDECS_CR_RCOMP_TIMER_MCMAIN_First_Rcomp_done_MSK (0x00010000) + #define MCDECS_CR_RCOMP_TIMER_MCMAIN_First_Rcomp_done_MAX (0x00000001) + #define MCDECS_CR_RCOMP_TIMER_MCMAIN_First_Rcomp_done_DEF (0x00000000) + +#define MCDECS_CR_ECC_INJ_ADDR_COMPARE_MCMAIN_REG (0x00005090) + #define MCDECS_CR_ECC_INJ_ADDR_COMPARE_MCMAIN_Address_OFF ( 0) + #define MCDECS_CR_ECC_INJ_ADDR_COMPARE_MCMAIN_Address_WID (32) + #define MCDECS_CR_ECC_INJ_ADDR_COMPARE_MCMAIN_Address_MSK (0xFFFFFFFF) + #define MCDECS_CR_ECC_INJ_ADDR_COMPARE_MCMAIN_Address_MAX (0xFFFFFFFF) + #define MCDECS_CR_ECC_INJ_ADDR_COMPARE_MCMAIN_Address_DEF (0x00000000) + +#define MCDECS_CR_ECC_INJ_ADDR_MASK_MCMAIN_REG (0x00005094) + #define MCDECS_CR_ECC_INJ_ADDR_MASK_MCMAIN_Mask_OFF ( 0) + #define MCDECS_CR_ECC_INJ_ADDR_MASK_MCMAIN_Mask_WID (32) + #define MCDECS_CR_ECC_INJ_ADDR_MASK_MCMAIN_Mask_MSK (0xFFFFFFFF) + #define MCDECS_CR_ECC_INJ_ADDR_MASK_MCMAIN_Mask_MAX (0xFFFFFFFF) + #define MCDECS_CR_ECC_INJ_ADDR_MASK_MCMAIN_Mask_DEF (0xFFFFFFFF) + +#define MCDECS_CR_VISA_CTL_MCDECS_MCMAIN_REG (0x000050A0) + #define MCDECS_CR_VISA_CTL_MCDECS_MCMAIN_Data_OFF ( 0) + #define MCDECS_CR_VISA_CTL_MCDECS_MCMAIN_Data_WID (18) + #define MCDECS_CR_VISA_CTL_MCDECS_MCMAIN_Data_MSK (0x0003FFFF) + #define MCDECS_CR_VISA_CTL_MCDECS_MCMAIN_Data_MAX (0x0003FFFF) + #define MCDECS_CR_VISA_CTL_MCDECS_MCMAIN_Data_DEF (0x00000000) + #define MCDECS_CR_VISA_CTL_MCDECS_MCMAIN_VORANGE_OFF (31) + #define MCDECS_CR_VISA_CTL_MCDECS_MCMAIN_VORANGE_WID ( 1) + #define MCDECS_CR_VISA_CTL_MCDECS_MCMAIN_VORANGE_MSK (0x80000000) + #define MCDECS_CR_VISA_CTL_MCDECS_MCMAIN_VORANGE_MAX (0x00000001) + #define MCDECS_CR_VISA_CTL_MCDECS_MCMAIN_VORANGE_DEF (0x00000000) + +#define MCDECS_CR_VISA_XBAR_MCDECS_MCMAIN_REG (0x000050A4) + #define MCDECS_CR_VISA_XBAR_MCDECS_MCMAIN_Data_OFF ( 0) + #define MCDECS_CR_VISA_XBAR_MCDECS_MCMAIN_Data_WID (32) + #define MCDECS_CR_VISA_XBAR_MCDECS_MCMAIN_Data_MSK (0xFFFFFFFF) + #define MCDECS_CR_VISA_XBAR_MCDECS_MCMAIN_Data_MAX (0xFFFFFFFF) + #define MCDECS_CR_VISA_XBAR_MCDECS_MCMAIN_Data_DEF (0x76543210) + +#define MCDECS_CR_MC_LOCK_MCMAIN_REG (0x000050FC) + #define MCDECS_CR_MC_LOCK_MCMAIN_lock_addr_map_OFF ( 0) + #define MCDECS_CR_MC_LOCK_MCMAIN_lock_addr_map_WID ( 1) + #define MCDECS_CR_MC_LOCK_MCMAIN_lock_addr_map_MSK (0x00000001) + #define MCDECS_CR_MC_LOCK_MCMAIN_lock_addr_map_MAX (0x00000001) + #define MCDECS_CR_MC_LOCK_MCMAIN_lock_addr_map_DEF (0x00000000) + #define MCDECS_CR_MC_LOCK_MCMAIN_lock_mc_config_OFF ( 1) + #define MCDECS_CR_MC_LOCK_MCMAIN_lock_mc_config_WID ( 1) + #define MCDECS_CR_MC_LOCK_MCMAIN_lock_mc_config_MSK (0x00000002) + #define MCDECS_CR_MC_LOCK_MCMAIN_lock_mc_config_MAX (0x00000001) + #define MCDECS_CR_MC_LOCK_MCMAIN_lock_mc_config_DEF (0x00000000) + #define MCDECS_CR_MC_LOCK_MCMAIN_lock_iosav_init_OFF ( 2) + #define MCDECS_CR_MC_LOCK_MCMAIN_lock_iosav_init_WID ( 1) + #define MCDECS_CR_MC_LOCK_MCMAIN_lock_iosav_init_MSK (0x00000004) + #define MCDECS_CR_MC_LOCK_MCMAIN_lock_iosav_init_MAX (0x00000001) + #define MCDECS_CR_MC_LOCK_MCMAIN_lock_iosav_init_DEF (0x00000000) + #define MCDECS_CR_MC_LOCK_MCMAIN_lock_pwr_mngment_OFF ( 3) + #define MCDECS_CR_MC_LOCK_MCMAIN_lock_pwr_mngment_WID ( 1) + #define MCDECS_CR_MC_LOCK_MCMAIN_lock_pwr_mngment_MSK (0x00000008) + #define MCDECS_CR_MC_LOCK_MCMAIN_lock_pwr_mngment_MAX (0x00000001) + #define MCDECS_CR_MC_LOCK_MCMAIN_lock_pwr_mngment_DEF (0x00000000) + #define MCDECS_CR_MC_LOCK_MCMAIN_lock_mc_dft_OFF ( 7) + #define MCDECS_CR_MC_LOCK_MCMAIN_lock_mc_dft_WID ( 1) + #define MCDECS_CR_MC_LOCK_MCMAIN_lock_mc_dft_MSK (0x00000080) + #define MCDECS_CR_MC_LOCK_MCMAIN_lock_mc_dft_MAX (0x00000001) + #define MCDECS_CR_MC_LOCK_MCMAIN_lock_mc_dft_DEF (0x00000000) + +#define MCHBAR_CH0_CR_TC_BANK_REG (0x00004000) + #define MCHBAR_CH0_CR_TC_BANK_tRCD_OFF ( 0) + #define MCHBAR_CH0_CR_TC_BANK_tRCD_WID ( 5) + #define MCHBAR_CH0_CR_TC_BANK_tRCD_MSK (0x0000001F) + #define MCHBAR_CH0_CR_TC_BANK_tRCD_MAX (0x0000001F) + #define MCHBAR_CH0_CR_TC_BANK_tRCD_DEF (0x00000006) + #define MCHBAR_CH0_CR_TC_BANK_tRP_OFF ( 5) + #define MCHBAR_CH0_CR_TC_BANK_tRP_WID ( 5) + #define MCHBAR_CH0_CR_TC_BANK_tRP_MSK (0x000003E0) + #define MCHBAR_CH0_CR_TC_BANK_tRP_MAX (0x0000001F) + #define MCHBAR_CH0_CR_TC_BANK_tRP_DEF (0x00000006) + #define MCHBAR_CH0_CR_TC_BANK_tRAS_OFF (10) + #define MCHBAR_CH0_CR_TC_BANK_tRAS_WID ( 6) + #define MCHBAR_CH0_CR_TC_BANK_tRAS_MSK (0x0000FC00) + #define MCHBAR_CH0_CR_TC_BANK_tRAS_MAX (0x0000003F) + #define MCHBAR_CH0_CR_TC_BANK_tRAS_DEF (0x00000014) + #define MCHBAR_CH0_CR_TC_BANK_tRDPRE_OFF (16) + #define MCHBAR_CH0_CR_TC_BANK_tRDPRE_WID ( 4) + #define MCHBAR_CH0_CR_TC_BANK_tRDPRE_MSK (0x000F0000) + #define MCHBAR_CH0_CR_TC_BANK_tRDPRE_MAX (0x0000000F) + #define MCHBAR_CH0_CR_TC_BANK_tRDPRE_DEF (0x00000004) + #define MCHBAR_CH0_CR_TC_BANK_tWRPRE_OFF (20) + #define MCHBAR_CH0_CR_TC_BANK_tWRPRE_WID ( 6) + #define MCHBAR_CH0_CR_TC_BANK_tWRPRE_MSK (0x03F00000) + #define MCHBAR_CH0_CR_TC_BANK_tWRPRE_MAX (0x0000003F) + #define MCHBAR_CH0_CR_TC_BANK_tWRPRE_DEF (0x00000004) + #define MCHBAR_CH0_CR_TC_BANK_tRRD_OFF (26) + #define MCHBAR_CH0_CR_TC_BANK_tRRD_WID ( 4) + #define MCHBAR_CH0_CR_TC_BANK_tRRD_MSK (0x3C000000) + #define MCHBAR_CH0_CR_TC_BANK_tRRD_MAX (0x0000000F) + #define MCHBAR_CH0_CR_TC_BANK_tRRD_DEF (0x00000004) + #define MCHBAR_CH0_CR_TC_BANK_tRPab_ext_OFF (30) + #define MCHBAR_CH0_CR_TC_BANK_tRPab_ext_WID ( 2) + #define MCHBAR_CH0_CR_TC_BANK_tRPab_ext_MSK (0xC0000000) + #define MCHBAR_CH0_CR_TC_BANK_tRPab_ext_MAX (0x00000003) + #define MCHBAR_CH0_CR_TC_BANK_tRPab_ext_DEF (0x00000000) + +#define MCHBAR_CH0_CR_TC_BANK_RANK_A_REG (0x00004004) + #define MCHBAR_CH0_CR_TC_BANK_RANK_A_tCKE_OFF ( 0) + #define MCHBAR_CH0_CR_TC_BANK_RANK_A_tCKE_WID ( 4) + #define MCHBAR_CH0_CR_TC_BANK_RANK_A_tCKE_MSK (0x0000000F) + #define MCHBAR_CH0_CR_TC_BANK_RANK_A_tCKE_MAX (0x0000000F) + #define MCHBAR_CH0_CR_TC_BANK_RANK_A_tCKE_DEF (0x00000003) + #define MCHBAR_CH0_CR_TC_BANK_RANK_A_tFAW_OFF ( 4) + #define MCHBAR_CH0_CR_TC_BANK_RANK_A_tFAW_WID ( 8) + #define MCHBAR_CH0_CR_TC_BANK_RANK_A_tFAW_MSK (0x00000FF0) + #define MCHBAR_CH0_CR_TC_BANK_RANK_A_tFAW_MAX (0x000000FF) + #define MCHBAR_CH0_CR_TC_BANK_RANK_A_tFAW_DEF (0x00000010) + #define MCHBAR_CH0_CR_TC_BANK_RANK_A_tRDRD_OFF (12) + #define MCHBAR_CH0_CR_TC_BANK_RANK_A_tRDRD_WID ( 3) + #define MCHBAR_CH0_CR_TC_BANK_RANK_A_tRDRD_MSK (0x00007000) + #define MCHBAR_CH0_CR_TC_BANK_RANK_A_tRDRD_MAX (0x00000007) + #define MCHBAR_CH0_CR_TC_BANK_RANK_A_tRDRD_DEF (0x00000004) + #define MCHBAR_CH0_CR_TC_BANK_RANK_A_tRDRD_dr_OFF (15) + #define MCHBAR_CH0_CR_TC_BANK_RANK_A_tRDRD_dr_WID ( 4) + #define MCHBAR_CH0_CR_TC_BANK_RANK_A_tRDRD_dr_MSK (0x00078000) + #define MCHBAR_CH0_CR_TC_BANK_RANK_A_tRDRD_dr_MAX (0x0000000F) + #define MCHBAR_CH0_CR_TC_BANK_RANK_A_tRDRD_dr_DEF (0x00000004) + #define MCHBAR_CH0_CR_TC_BANK_RANK_A_tRDRD_dd_OFF (19) + #define MCHBAR_CH0_CR_TC_BANK_RANK_A_tRDRD_dd_WID ( 4) + #define MCHBAR_CH0_CR_TC_BANK_RANK_A_tRDRD_dd_MSK (0x00780000) + #define MCHBAR_CH0_CR_TC_BANK_RANK_A_tRDRD_dd_MAX (0x0000000F) + #define MCHBAR_CH0_CR_TC_BANK_RANK_A_tRDRD_dd_DEF (0x00000004) + #define MCHBAR_CH0_CR_TC_BANK_RANK_A_tRDPDEN_OFF (23) + #define MCHBAR_CH0_CR_TC_BANK_RANK_A_tRDPDEN_WID ( 5) + #define MCHBAR_CH0_CR_TC_BANK_RANK_A_tRDPDEN_MSK (0x0F800000) + #define MCHBAR_CH0_CR_TC_BANK_RANK_A_tRDPDEN_MAX (0x0000001F) + #define MCHBAR_CH0_CR_TC_BANK_RANK_A_tRDPDEN_DEF (0x00000004) + #define MCHBAR_CH0_CR_TC_BANK_RANK_A_CMD_3st_OFF (29) + #define MCHBAR_CH0_CR_TC_BANK_RANK_A_CMD_3st_WID ( 1) + #define MCHBAR_CH0_CR_TC_BANK_RANK_A_CMD_3st_MSK (0x20000000) + #define MCHBAR_CH0_CR_TC_BANK_RANK_A_CMD_3st_MAX (0x00000001) + #define MCHBAR_CH0_CR_TC_BANK_RANK_A_CMD_3st_DEF (0x00000000) + #define MCHBAR_CH0_CR_TC_BANK_RANK_A_CMD_stretch_OFF (30) + #define MCHBAR_CH0_CR_TC_BANK_RANK_A_CMD_stretch_WID ( 2) + #define MCHBAR_CH0_CR_TC_BANK_RANK_A_CMD_stretch_MSK (0xC0000000) + #define MCHBAR_CH0_CR_TC_BANK_RANK_A_CMD_stretch_MAX (0x00000003) + #define MCHBAR_CH0_CR_TC_BANK_RANK_A_CMD_stretch_DEF (0x00000002) + +#define MCHBAR_CH0_CR_TC_BANK_RANK_B_REG (0x00004008) + #define MCHBAR_CH0_CR_TC_BANK_RANK_B_tWRRD_OFF ( 0) + #define MCHBAR_CH0_CR_TC_BANK_RANK_B_tWRRD_WID ( 6) + #define MCHBAR_CH0_CR_TC_BANK_RANK_B_tWRRD_MSK (0x0000003F) + #define MCHBAR_CH0_CR_TC_BANK_RANK_B_tWRRD_MAX (0x0000003F) + #define MCHBAR_CH0_CR_TC_BANK_RANK_B_tWRRD_DEF (0x00000005) + #define MCHBAR_CH0_CR_TC_BANK_RANK_B_tWRRD_dr_OFF ( 6) + #define MCHBAR_CH0_CR_TC_BANK_RANK_B_tWRRD_dr_WID ( 4) + #define MCHBAR_CH0_CR_TC_BANK_RANK_B_tWRRD_dr_MSK (0x000003C0) + #define MCHBAR_CH0_CR_TC_BANK_RANK_B_tWRRD_dr_MAX (0x0000000F) + #define MCHBAR_CH0_CR_TC_BANK_RANK_B_tWRRD_dr_DEF (0x00000005) + #define MCHBAR_CH0_CR_TC_BANK_RANK_B_tWRRD_dd_OFF (10) + #define MCHBAR_CH0_CR_TC_BANK_RANK_B_tWRRD_dd_WID ( 4) + #define MCHBAR_CH0_CR_TC_BANK_RANK_B_tWRRD_dd_MSK (0x00003C00) + #define MCHBAR_CH0_CR_TC_BANK_RANK_B_tWRRD_dd_MAX (0x0000000F) + #define MCHBAR_CH0_CR_TC_BANK_RANK_B_tWRRD_dd_DEF (0x00000005) + #define MCHBAR_CH0_CR_TC_BANK_RANK_B_tWRWR_OFF (14) + #define MCHBAR_CH0_CR_TC_BANK_RANK_B_tWRWR_WID ( 3) + #define MCHBAR_CH0_CR_TC_BANK_RANK_B_tWRWR_MSK (0x0001C000) + #define MCHBAR_CH0_CR_TC_BANK_RANK_B_tWRWR_MAX (0x00000007) + #define MCHBAR_CH0_CR_TC_BANK_RANK_B_tWRWR_DEF (0x00000005) + #define MCHBAR_CH0_CR_TC_BANK_RANK_B_tWRWR_dr_OFF (17) + #define MCHBAR_CH0_CR_TC_BANK_RANK_B_tWRWR_dr_WID ( 4) + #define MCHBAR_CH0_CR_TC_BANK_RANK_B_tWRWR_dr_MSK (0x001E0000) + #define MCHBAR_CH0_CR_TC_BANK_RANK_B_tWRWR_dr_MAX (0x0000000F) + #define MCHBAR_CH0_CR_TC_BANK_RANK_B_tWRWR_dr_DEF (0x00000005) + #define MCHBAR_CH0_CR_TC_BANK_RANK_B_tWRWR_dd_OFF (21) + #define MCHBAR_CH0_CR_TC_BANK_RANK_B_tWRWR_dd_WID ( 4) + #define MCHBAR_CH0_CR_TC_BANK_RANK_B_tWRWR_dd_MSK (0x01E00000) + #define MCHBAR_CH0_CR_TC_BANK_RANK_B_tWRWR_dd_MAX (0x0000000F) + #define MCHBAR_CH0_CR_TC_BANK_RANK_B_tWRWR_dd_DEF (0x00000005) + #define MCHBAR_CH0_CR_TC_BANK_RANK_B_tWRPDEN_OFF (25) + #define MCHBAR_CH0_CR_TC_BANK_RANK_B_tWRPDEN_WID ( 6) + #define MCHBAR_CH0_CR_TC_BANK_RANK_B_tWRPDEN_MSK (0x7E000000) + #define MCHBAR_CH0_CR_TC_BANK_RANK_B_tWRPDEN_MAX (0x0000003F) + #define MCHBAR_CH0_CR_TC_BANK_RANK_B_tWRPDEN_DEF (0x00000005) + #define MCHBAR_CH0_CR_TC_BANK_RANK_B_Dec_WRD_OFF (31) + #define MCHBAR_CH0_CR_TC_BANK_RANK_B_Dec_WRD_WID ( 1) + #define MCHBAR_CH0_CR_TC_BANK_RANK_B_Dec_WRD_MSK (0x80000000) + #define MCHBAR_CH0_CR_TC_BANK_RANK_B_Dec_WRD_MAX (0x00000001) + #define MCHBAR_CH0_CR_TC_BANK_RANK_B_Dec_WRD_DEF (0x00000000) + +#define MCHBAR_CH0_CR_TC_BANK_RANK_C_REG (0x0000400C) + #define MCHBAR_CH0_CR_TC_BANK_RANK_C_tXPDLL_OFF ( 0) + #define MCHBAR_CH0_CR_TC_BANK_RANK_C_tXPDLL_WID ( 6) + #define MCHBAR_CH0_CR_TC_BANK_RANK_C_tXPDLL_MSK (0x0000003F) + #define MCHBAR_CH0_CR_TC_BANK_RANK_C_tXPDLL_MAX (0x0000003F) + #define MCHBAR_CH0_CR_TC_BANK_RANK_C_tXPDLL_DEF (0x0000000A) + #define MCHBAR_CH0_CR_TC_BANK_RANK_C_tXP_OFF ( 6) + #define MCHBAR_CH0_CR_TC_BANK_RANK_C_tXP_WID ( 4) + #define MCHBAR_CH0_CR_TC_BANK_RANK_C_tXP_MSK (0x000003C0) + #define MCHBAR_CH0_CR_TC_BANK_RANK_C_tXP_MAX (0x0000000F) + #define MCHBAR_CH0_CR_TC_BANK_RANK_C_tXP_DEF (0x00000003) + #define MCHBAR_CH0_CR_TC_BANK_RANK_C_TAONPD_OFF (10) + #define MCHBAR_CH0_CR_TC_BANK_RANK_C_TAONPD_WID ( 4) + #define MCHBAR_CH0_CR_TC_BANK_RANK_C_TAONPD_MSK (0x00003C00) + #define MCHBAR_CH0_CR_TC_BANK_RANK_C_TAONPD_MAX (0x0000000F) + #define MCHBAR_CH0_CR_TC_BANK_RANK_C_TAONPD_DEF (0x00000009) + #define MCHBAR_CH0_CR_TC_BANK_RANK_C_tRDWR_OFF (14) + #define MCHBAR_CH0_CR_TC_BANK_RANK_C_tRDWR_WID ( 5) + #define MCHBAR_CH0_CR_TC_BANK_RANK_C_tRDWR_MSK (0x0007C000) + #define MCHBAR_CH0_CR_TC_BANK_RANK_C_tRDWR_MAX (0x0000001F) + #define MCHBAR_CH0_CR_TC_BANK_RANK_C_tRDWR_DEF (0x00000005) + #define MCHBAR_CH0_CR_TC_BANK_RANK_C_tRDWR_dr_OFF (19) + #define MCHBAR_CH0_CR_TC_BANK_RANK_C_tRDWR_dr_WID ( 5) + #define MCHBAR_CH0_CR_TC_BANK_RANK_C_tRDWR_dr_MSK (0x00F80000) + #define MCHBAR_CH0_CR_TC_BANK_RANK_C_tRDWR_dr_MAX (0x0000001F) + #define MCHBAR_CH0_CR_TC_BANK_RANK_C_tRDWR_dr_DEF (0x00000005) + #define MCHBAR_CH0_CR_TC_BANK_RANK_C_tRDWR_dd_OFF (24) + #define MCHBAR_CH0_CR_TC_BANK_RANK_C_tRDWR_dd_WID ( 5) + #define MCHBAR_CH0_CR_TC_BANK_RANK_C_tRDWR_dd_MSK (0x1F000000) + #define MCHBAR_CH0_CR_TC_BANK_RANK_C_tRDWR_dd_MAX (0x0000001F) + #define MCHBAR_CH0_CR_TC_BANK_RANK_C_tRDWR_dd_DEF (0x00000005) + +#define MCHBAR_CH0_CR_CMD_RATE_REG (0x00004010) + #define MCHBAR_CH0_CR_CMD_RATE_enable_cmd_rate_limit_OFF ( 0) + #define MCHBAR_CH0_CR_CMD_RATE_enable_cmd_rate_limit_WID ( 1) + #define MCHBAR_CH0_CR_CMD_RATE_enable_cmd_rate_limit_MSK (0x00000001) + #define MCHBAR_CH0_CR_CMD_RATE_enable_cmd_rate_limit_MAX (0x00000001) + #define MCHBAR_CH0_CR_CMD_RATE_enable_cmd_rate_limit_DEF (0x00000000) + #define MCHBAR_CH0_CR_CMD_RATE_cmd_rate_limit_OFF ( 1) + #define MCHBAR_CH0_CR_CMD_RATE_cmd_rate_limit_WID ( 3) + #define MCHBAR_CH0_CR_CMD_RATE_cmd_rate_limit_MSK (0x0000000E) + #define MCHBAR_CH0_CR_CMD_RATE_cmd_rate_limit_MAX (0x00000007) + #define MCHBAR_CH0_CR_CMD_RATE_cmd_rate_limit_DEF (0x00000004) + #define MCHBAR_CH0_CR_CMD_RATE_reset_on_command_OFF ( 4) + #define MCHBAR_CH0_CR_CMD_RATE_reset_on_command_WID ( 4) + #define MCHBAR_CH0_CR_CMD_RATE_reset_on_command_MSK (0x000000F0) + #define MCHBAR_CH0_CR_CMD_RATE_reset_on_command_MAX (0x0000000F) + #define MCHBAR_CH0_CR_CMD_RATE_reset_on_command_DEF (0x00000000) + #define MCHBAR_CH0_CR_CMD_RATE_reset_delay_OFF ( 8) + #define MCHBAR_CH0_CR_CMD_RATE_reset_delay_WID ( 4) + #define MCHBAR_CH0_CR_CMD_RATE_reset_delay_MSK (0x00000F00) + #define MCHBAR_CH0_CR_CMD_RATE_reset_delay_MAX (0x0000000F) + #define MCHBAR_CH0_CR_CMD_RATE_reset_delay_DEF (0x00000000) + #define MCHBAR_CH0_CR_CMD_RATE_ck_to_cke_delay_OFF (12) + #define MCHBAR_CH0_CR_CMD_RATE_ck_to_cke_delay_WID ( 2) + #define MCHBAR_CH0_CR_CMD_RATE_ck_to_cke_delay_MSK (0x00003000) + #define MCHBAR_CH0_CR_CMD_RATE_ck_to_cke_delay_MAX (0x00000003) + #define MCHBAR_CH0_CR_CMD_RATE_ck_to_cke_delay_DEF (0x00000001) + #define MCHBAR_CH0_CR_CMD_RATE_spare_OFF (14) + #define MCHBAR_CH0_CR_CMD_RATE_spare_WID (17) + #define MCHBAR_CH0_CR_CMD_RATE_spare_MSK (0x7FFFC000) + #define MCHBAR_CH0_CR_CMD_RATE_spare_MAX (0x0001FFFF) + #define MCHBAR_CH0_CR_CMD_RATE_spare_DEF (0x00000000) + #define MCHBAR_CH0_CR_CMD_RATE_init_mrw_2n_cs_OFF (31) + #define MCHBAR_CH0_CR_CMD_RATE_init_mrw_2n_cs_WID ( 1) + #define MCHBAR_CH0_CR_CMD_RATE_init_mrw_2n_cs_MSK (0x80000000) + #define MCHBAR_CH0_CR_CMD_RATE_init_mrw_2n_cs_MAX (0x00000001) + #define MCHBAR_CH0_CR_CMD_RATE_init_mrw_2n_cs_DEF (0x00000000) + +#define MCHBAR_CH0_CR_TC_BANK_RANK_D_REG (0x00004014) + #define MCHBAR_CH0_CR_TC_BANK_RANK_D_tCL_OFF ( 0) + #define MCHBAR_CH0_CR_TC_BANK_RANK_D_tCL_WID ( 5) + #define MCHBAR_CH0_CR_TC_BANK_RANK_D_tCL_MSK (0x0000001F) + #define MCHBAR_CH0_CR_TC_BANK_RANK_D_tCL_MAX (0x0000001F) + #define MCHBAR_CH0_CR_TC_BANK_RANK_D_tCL_DEF (0x00000006) + #define MCHBAR_CH0_CR_TC_BANK_RANK_D_tWCL_OFF ( 5) + #define MCHBAR_CH0_CR_TC_BANK_RANK_D_tWCL_WID ( 5) + #define MCHBAR_CH0_CR_TC_BANK_RANK_D_tWCL_MSK (0x000003E0) + #define MCHBAR_CH0_CR_TC_BANK_RANK_D_tWCL_MAX (0x0000001F) + #define MCHBAR_CH0_CR_TC_BANK_RANK_D_tWCL_DEF (0x00000006) + #define MCHBAR_CH0_CR_TC_BANK_RANK_D_tCPDED_OFF (10) + #define MCHBAR_CH0_CR_TC_BANK_RANK_D_tCPDED_WID ( 2) + #define MCHBAR_CH0_CR_TC_BANK_RANK_D_tCPDED_MSK (0x00000C00) + #define MCHBAR_CH0_CR_TC_BANK_RANK_D_tCPDED_MAX (0x00000003) + #define MCHBAR_CH0_CR_TC_BANK_RANK_D_tCPDED_DEF (0x00000001) + #define MCHBAR_CH0_CR_TC_BANK_RANK_D_tPRPDEN_OFF (12) + #define MCHBAR_CH0_CR_TC_BANK_RANK_D_tPRPDEN_WID ( 2) + #define MCHBAR_CH0_CR_TC_BANK_RANK_D_tPRPDEN_MSK (0x00003000) + #define MCHBAR_CH0_CR_TC_BANK_RANK_D_tPRPDEN_MAX (0x00000003) + #define MCHBAR_CH0_CR_TC_BANK_RANK_D_tPRPDEN_DEF (0x00000001) + #define MCHBAR_CH0_CR_TC_BANK_RANK_D_Odt_Read_Delay_OFF (14) + #define MCHBAR_CH0_CR_TC_BANK_RANK_D_Odt_Read_Delay_WID ( 3) + #define MCHBAR_CH0_CR_TC_BANK_RANK_D_Odt_Read_Delay_MSK (0x0001C000) + #define MCHBAR_CH0_CR_TC_BANK_RANK_D_Odt_Read_Delay_MAX (0x00000007) + #define MCHBAR_CH0_CR_TC_BANK_RANK_D_Odt_Read_Delay_DEF (0x00000000) + #define MCHBAR_CH0_CR_TC_BANK_RANK_D_Odt_Read_Duration_OFF (17) + #define MCHBAR_CH0_CR_TC_BANK_RANK_D_Odt_Read_Duration_WID ( 2) + #define MCHBAR_CH0_CR_TC_BANK_RANK_D_Odt_Read_Duration_MSK (0x00060000) + #define MCHBAR_CH0_CR_TC_BANK_RANK_D_Odt_Read_Duration_MAX (0x00000003) + #define MCHBAR_CH0_CR_TC_BANK_RANK_D_Odt_Read_Duration_DEF (0x00000000) + #define MCHBAR_CH0_CR_TC_BANK_RANK_D_Odt_Write_Duration_OFF (19) + #define MCHBAR_CH0_CR_TC_BANK_RANK_D_Odt_Write_Duration_WID ( 2) + #define MCHBAR_CH0_CR_TC_BANK_RANK_D_Odt_Write_Duration_MSK (0x00180000) + #define MCHBAR_CH0_CR_TC_BANK_RANK_D_Odt_Write_Duration_MAX (0x00000003) + #define MCHBAR_CH0_CR_TC_BANK_RANK_D_Odt_Write_Duration_DEF (0x00000000) + #define MCHBAR_CH0_CR_TC_BANK_RANK_D_Odt_Write_Duration_Ult_OFF (19) + #define MCHBAR_CH0_CR_TC_BANK_RANK_D_Odt_Write_Duration_Ult_WID ( 3) + #define MCHBAR_CH0_CR_TC_BANK_RANK_D_Odt_Write_Duration_Ult_MSK (0x00380000) + #define MCHBAR_CH0_CR_TC_BANK_RANK_D_Odt_Write_Duration_Ult_MAX (0x00000007) + #define MCHBAR_CH0_CR_TC_BANK_RANK_D_Odt_Write_Duration_Ult_DEF (0x00000000) + #define MCHBAR_CH0_CR_TC_BANK_RANK_D_Odt_Write_Delay_Ult_OFF (22) + #define MCHBAR_CH0_CR_TC_BANK_RANK_D_Odt_Write_Delay_Ult_WID ( 3) + #define MCHBAR_CH0_CR_TC_BANK_RANK_D_Odt_Write_Delay_Ult_MSK (0x01C00000) + #define MCHBAR_CH0_CR_TC_BANK_RANK_D_Odt_Write_Delay_Ult_MAX (0x00000007) + #define MCHBAR_CH0_CR_TC_BANK_RANK_D_Odt_Write_Delay_Ult_DEF (0x00000000) + #define MCHBAR_CH0_CR_TC_BANK_RANK_D_Odt_Always_Rank0_Ult_OFF (25) + #define MCHBAR_CH0_CR_TC_BANK_RANK_D_Odt_Always_Rank0_Ult_WID ( 1) + #define MCHBAR_CH0_CR_TC_BANK_RANK_D_Odt_Always_Rank0_Ult_MSK (0x02000000) + #define MCHBAR_CH0_CR_TC_BANK_RANK_D_Odt_Always_Rank0_Ult_MAX (0x00000001) + #define MCHBAR_CH0_CR_TC_BANK_RANK_D_Odt_Always_Rank0_Ult_DEF (0x00000000) + #define MCHBAR_CH0_CR_TC_BANK_RANK_D_cmd_delay_Ult_OFF (26) + #define MCHBAR_CH0_CR_TC_BANK_RANK_D_cmd_delay_Ult_WID ( 2) + #define MCHBAR_CH0_CR_TC_BANK_RANK_D_cmd_delay_Ult_MSK (0x0C000000) + #define MCHBAR_CH0_CR_TC_BANK_RANK_D_cmd_delay_Ult_MAX (0x00000003) + #define MCHBAR_CH0_CR_TC_BANK_RANK_D_cmd_delay_Ult_DEF (0x00000000) + +#define MCHBAR_CH0_CR_SCHED_CBIT_REG (0x00004020) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_opp_cas_OFF ( 0) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_opp_cas_WID ( 1) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_opp_cas_MSK (0x00000001) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_opp_cas_MAX (0x00000001) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_opp_cas_DEF (0x00000001) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_opp_is_cas_OFF ( 1) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_opp_is_cas_WID ( 1) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_opp_is_cas_MSK (0x00000002) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_opp_is_cas_MAX (0x00000001) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_opp_is_cas_DEF (0x00000000) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_opp_ras_OFF ( 2) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_opp_ras_WID ( 1) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_opp_ras_MSK (0x00000004) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_opp_ras_MAX (0x00000001) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_opp_ras_DEF (0x00000001) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_opp_is_ras_OFF ( 3) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_opp_is_ras_WID ( 1) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_opp_is_ras_MSK (0x00000008) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_opp_is_ras_MAX (0x00000001) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_opp_is_ras_DEF (0x00000000) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_1c_byp_OFF ( 4) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_1c_byp_WID ( 1) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_1c_byp_MSK (0x00000010) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_1c_byp_MAX (0x00000001) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_1c_byp_DEF (0x00000001) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_2c_byp_OFF ( 5) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_2c_byp_WID ( 1) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_2c_byp_MSK (0x00000020) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_2c_byp_MAX (0x00000001) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_2c_byp_DEF (0x00000000) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_deprd_opt_OFF ( 6) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_deprd_opt_WID ( 1) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_deprd_opt_MSK (0x00000040) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_deprd_opt_MAX (0x00000001) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_deprd_opt_DEF (0x00000000) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_pt_it_OFF ( 7) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_pt_it_WID ( 1) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_pt_it_MSK (0x00000080) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_pt_it_MAX (0x00000001) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_pt_it_DEF (0x00000000) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_prcnt_ring_OFF ( 8) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_prcnt_ring_WID ( 1) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_prcnt_ring_MSK (0x00000100) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_prcnt_ring_MAX (0x00000001) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_prcnt_ring_DEF (0x00000000) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_prcnt_sa_OFF ( 9) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_prcnt_sa_WID ( 1) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_prcnt_sa_MSK (0x00000200) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_prcnt_sa_MAX (0x00000001) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_prcnt_sa_DEF (0x00000000) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_blkr_ph_OFF (10) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_blkr_ph_WID ( 1) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_blkr_ph_MSK (0x00000400) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_blkr_ph_MAX (0x00000001) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_blkr_ph_DEF (0x00000000) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_blkr_pe_OFF (11) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_blkr_pe_WID ( 1) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_blkr_pe_MSK (0x00000800) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_blkr_pe_MAX (0x00000001) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_blkr_pe_DEF (0x00000000) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_blkr_pm_OFF (12) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_blkr_pm_WID ( 1) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_blkr_pm_MSK (0x00001000) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_blkr_pm_MAX (0x00000001) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_blkr_pm_DEF (0x00000000) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_odt_OFF (13) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_odt_WID ( 1) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_odt_MSK (0x00002000) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_odt_MAX (0x00000001) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_odt_DEF (0x00000000) + #define MCHBAR_CH0_CR_SCHED_CBIT_OE_alw_off_OFF (14) + #define MCHBAR_CH0_CR_SCHED_CBIT_OE_alw_off_WID ( 1) + #define MCHBAR_CH0_CR_SCHED_CBIT_OE_alw_off_MSK (0x00004000) + #define MCHBAR_CH0_CR_SCHED_CBIT_OE_alw_off_MAX (0x00000001) + #define MCHBAR_CH0_CR_SCHED_CBIT_OE_alw_off_DEF (0x00000000) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_aom_OFF (16) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_aom_WID ( 1) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_aom_MSK (0x00010000) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_aom_MAX (0x00000001) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_aom_DEF (0x00000000) + #define MCHBAR_CH0_CR_SCHED_CBIT_block_rpq_OFF (17) + #define MCHBAR_CH0_CR_SCHED_CBIT_block_rpq_WID ( 1) + #define MCHBAR_CH0_CR_SCHED_CBIT_block_rpq_MSK (0x00020000) + #define MCHBAR_CH0_CR_SCHED_CBIT_block_rpq_MAX (0x00000001) + #define MCHBAR_CH0_CR_SCHED_CBIT_block_rpq_DEF (0x00000000) + #define MCHBAR_CH0_CR_SCHED_CBIT_block_wpq_OFF (18) + #define MCHBAR_CH0_CR_SCHED_CBIT_block_wpq_WID ( 1) + #define MCHBAR_CH0_CR_SCHED_CBIT_block_wpq_MSK (0x00040000) + #define MCHBAR_CH0_CR_SCHED_CBIT_block_wpq_MAX (0x00000001) + #define MCHBAR_CH0_CR_SCHED_CBIT_block_wpq_DEF (0x00000000) + #define MCHBAR_CH0_CR_SCHED_CBIT_invert_align_OFF (19) + #define MCHBAR_CH0_CR_SCHED_CBIT_invert_align_WID ( 1) + #define MCHBAR_CH0_CR_SCHED_CBIT_invert_align_MSK (0x00080000) + #define MCHBAR_CH0_CR_SCHED_CBIT_invert_align_MAX (0x00000001) + #define MCHBAR_CH0_CR_SCHED_CBIT_invert_align_DEF (0x00000000) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_write_gap_OFF (20) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_write_gap_WID ( 1) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_write_gap_MSK (0x00100000) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_write_gap_MAX (0x00000001) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_write_gap_DEF (0x00000001) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_zq_OFF (21) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_zq_WID ( 1) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_zq_MSK (0x00200000) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_zq_MAX (0x00000001) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_zq_DEF (0x00000000) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_tt_OFF (22) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_tt_WID ( 1) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_tt_MSK (0x00400000) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_tt_MAX (0x00000001) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_tt_DEF (0x00000000) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_opp_ref_OFF (23) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_opp_ref_WID ( 1) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_opp_ref_MSK (0x00800000) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_opp_ref_MAX (0x00000001) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_opp_ref_DEF (0x00000000) + #define MCHBAR_CH0_CR_SCHED_CBIT_Long_ZQ_OFF (24) + #define MCHBAR_CH0_CR_SCHED_CBIT_Long_ZQ_WID ( 1) + #define MCHBAR_CH0_CR_SCHED_CBIT_Long_ZQ_MSK (0x01000000) + #define MCHBAR_CH0_CR_SCHED_CBIT_Long_ZQ_MAX (0x00000001) + #define MCHBAR_CH0_CR_SCHED_CBIT_Long_ZQ_DEF (0x00000000) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_srx_zq_OFF (25) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_srx_zq_WID ( 1) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_srx_zq_MSK (0x02000000) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_srx_zq_MAX (0x00000001) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_srx_zq_DEF (0x00000000) + #define MCHBAR_CH0_CR_SCHED_CBIT_Serialize_ZQ_OFF (26) + #define MCHBAR_CH0_CR_SCHED_CBIT_Serialize_ZQ_WID ( 1) + #define MCHBAR_CH0_CR_SCHED_CBIT_Serialize_ZQ_MSK (0x04000000) + #define MCHBAR_CH0_CR_SCHED_CBIT_Serialize_ZQ_MAX (0x00000001) + #define MCHBAR_CH0_CR_SCHED_CBIT_Serialize_ZQ_DEF (0x00000000) + #define MCHBAR_CH0_CR_SCHED_CBIT_ZQ_fast_exec_OFF (27) + #define MCHBAR_CH0_CR_SCHED_CBIT_ZQ_fast_exec_WID ( 1) + #define MCHBAR_CH0_CR_SCHED_CBIT_ZQ_fast_exec_MSK (0x08000000) + #define MCHBAR_CH0_CR_SCHED_CBIT_ZQ_fast_exec_MAX (0x00000001) + #define MCHBAR_CH0_CR_SCHED_CBIT_ZQ_fast_exec_DEF (0x00000000) + #define MCHBAR_CH0_CR_SCHED_CBIT_Dis_DriveNop_OFF (28) + #define MCHBAR_CH0_CR_SCHED_CBIT_Dis_DriveNop_WID ( 1) + #define MCHBAR_CH0_CR_SCHED_CBIT_Dis_DriveNop_MSK (0x10000000) + #define MCHBAR_CH0_CR_SCHED_CBIT_Dis_DriveNop_MAX (0x00000001) + #define MCHBAR_CH0_CR_SCHED_CBIT_Dis_DriveNop_DEF (0x00000000) + #define MCHBAR_CH0_CR_SCHED_CBIT_Pres_WDB_Ent_OFF (29) + #define MCHBAR_CH0_CR_SCHED_CBIT_Pres_WDB_Ent_WID ( 1) + #define MCHBAR_CH0_CR_SCHED_CBIT_Pres_WDB_Ent_MSK (0x20000000) + #define MCHBAR_CH0_CR_SCHED_CBIT_Pres_WDB_Ent_MAX (0x00000001) + #define MCHBAR_CH0_CR_SCHED_CBIT_Pres_WDB_Ent_DEF (0x00000000) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_clk_gate_OFF (30) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_clk_gate_WID ( 1) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_clk_gate_MSK (0x40000000) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_clk_gate_MAX (0x00000001) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_clk_gate_DEF (0x00000000) + +#define MCHBAR_CH0_CR_SC_ROUNDT_LAT_REG (0x00004024) + #define MCHBAR_CH0_CR_SC_ROUNDT_LAT_Lat_R0D0_OFF ( 0) + #define MCHBAR_CH0_CR_SC_ROUNDT_LAT_Lat_R0D0_WID ( 6) + #define MCHBAR_CH0_CR_SC_ROUNDT_LAT_Lat_R0D0_MSK (0x0000003F) + #define MCHBAR_CH0_CR_SC_ROUNDT_LAT_Lat_R0D0_MAX (0x0000003F) + #define MCHBAR_CH0_CR_SC_ROUNDT_LAT_Lat_R0D0_DEF (0x00000020) + #define MCHBAR_CH0_CR_SC_ROUNDT_LAT_Lat_R1D0_OFF ( 8) + #define MCHBAR_CH0_CR_SC_ROUNDT_LAT_Lat_R1D0_WID ( 6) + #define MCHBAR_CH0_CR_SC_ROUNDT_LAT_Lat_R1D0_MSK (0x00003F00) + #define MCHBAR_CH0_CR_SC_ROUNDT_LAT_Lat_R1D0_MAX (0x0000003F) + #define MCHBAR_CH0_CR_SC_ROUNDT_LAT_Lat_R1D0_DEF (0x00000020) + #define MCHBAR_CH0_CR_SC_ROUNDT_LAT_Lat_R0D1_OFF (16) + #define MCHBAR_CH0_CR_SC_ROUNDT_LAT_Lat_R0D1_WID ( 6) + #define MCHBAR_CH0_CR_SC_ROUNDT_LAT_Lat_R0D1_MSK (0x003F0000) + #define MCHBAR_CH0_CR_SC_ROUNDT_LAT_Lat_R0D1_MAX (0x0000003F) + #define MCHBAR_CH0_CR_SC_ROUNDT_LAT_Lat_R0D1_DEF (0x00000020) + #define MCHBAR_CH0_CR_SC_ROUNDT_LAT_Lat_R1D1_OFF (24) + #define MCHBAR_CH0_CR_SC_ROUNDT_LAT_Lat_R1D1_WID ( 6) + #define MCHBAR_CH0_CR_SC_ROUNDT_LAT_Lat_R1D1_MSK (0x3F000000) + #define MCHBAR_CH0_CR_SC_ROUNDT_LAT_Lat_R1D1_MAX (0x0000003F) + #define MCHBAR_CH0_CR_SC_ROUNDT_LAT_Lat_R1D1_DEF (0x00000020) + +#define MCHBAR_CH0_CR_SC_IO_LATENCY_REG (0x00004028) + #define MCHBAR_CH0_CR_SC_IO_LATENCY_IOLAT_R0D0_OFF ( 0) + #define MCHBAR_CH0_CR_SC_IO_LATENCY_IOLAT_R0D0_WID ( 4) + #define MCHBAR_CH0_CR_SC_IO_LATENCY_IOLAT_R0D0_MSK (0x0000000F) + #define MCHBAR_CH0_CR_SC_IO_LATENCY_IOLAT_R0D0_MAX (0x0000000F) + #define MCHBAR_CH0_CR_SC_IO_LATENCY_IOLAT_R0D0_DEF (0x00000000) + #define MCHBAR_CH0_CR_SC_IO_LATENCY_IOLAT_R1D0_OFF ( 4) + #define MCHBAR_CH0_CR_SC_IO_LATENCY_IOLAT_R1D0_WID ( 4) + #define MCHBAR_CH0_CR_SC_IO_LATENCY_IOLAT_R1D0_MSK (0x000000F0) + #define MCHBAR_CH0_CR_SC_IO_LATENCY_IOLAT_R1D0_MAX (0x0000000F) + #define MCHBAR_CH0_CR_SC_IO_LATENCY_IOLAT_R1D0_DEF (0x00000000) + #define MCHBAR_CH0_CR_SC_IO_LATENCY_IOLAT_R0D1_OFF ( 8) + #define MCHBAR_CH0_CR_SC_IO_LATENCY_IOLAT_R0D1_WID ( 4) + #define MCHBAR_CH0_CR_SC_IO_LATENCY_IOLAT_R0D1_MSK (0x00000F00) + #define MCHBAR_CH0_CR_SC_IO_LATENCY_IOLAT_R0D1_MAX (0x0000000F) + #define MCHBAR_CH0_CR_SC_IO_LATENCY_IOLAT_R0D1_DEF (0x00000000) + #define MCHBAR_CH0_CR_SC_IO_LATENCY_IOLAT_R1D1_OFF (12) + #define MCHBAR_CH0_CR_SC_IO_LATENCY_IOLAT_R1D1_WID ( 4) + #define MCHBAR_CH0_CR_SC_IO_LATENCY_IOLAT_R1D1_MSK (0x0000F000) + #define MCHBAR_CH0_CR_SC_IO_LATENCY_IOLAT_R1D1_MAX (0x0000000F) + #define MCHBAR_CH0_CR_SC_IO_LATENCY_IOLAT_R1D1_DEF (0x00000000) + #define MCHBAR_CH0_CR_SC_IO_LATENCY_RT_IOCOMP_OFF (16) + #define MCHBAR_CH0_CR_SC_IO_LATENCY_RT_IOCOMP_WID ( 6) + #define MCHBAR_CH0_CR_SC_IO_LATENCY_RT_IOCOMP_MSK (0x003F0000) + #define MCHBAR_CH0_CR_SC_IO_LATENCY_RT_IOCOMP_MAX (0x0000003F) + #define MCHBAR_CH0_CR_SC_IO_LATENCY_RT_IOCOMP_DEF (0x0000000E) + #define MCHBAR_CH0_CR_SC_IO_LATENCY_three_channels_OFF (30) + #define MCHBAR_CH0_CR_SC_IO_LATENCY_three_channels_WID ( 1) + #define MCHBAR_CH0_CR_SC_IO_LATENCY_three_channels_MSK (0x40000000) + #define MCHBAR_CH0_CR_SC_IO_LATENCY_three_channels_MAX (0x00000001) + #define MCHBAR_CH0_CR_SC_IO_LATENCY_three_channels_DEF (0x00000000) + #define MCHBAR_CH0_CR_SC_IO_LATENCY_DIS_RT_CLK_GATE_OFF (31) + #define MCHBAR_CH0_CR_SC_IO_LATENCY_DIS_RT_CLK_GATE_WID ( 1) + #define MCHBAR_CH0_CR_SC_IO_LATENCY_DIS_RT_CLK_GATE_MSK (0x80000000) + #define MCHBAR_CH0_CR_SC_IO_LATENCY_DIS_RT_CLK_GATE_MAX (0x00000001) + #define MCHBAR_CH0_CR_SC_IO_LATENCY_DIS_RT_CLK_GATE_DEF (0x00000000) + +#define MCHBAR_CH0_CR_ROUND_TRIP_DFT_DATA_REG (0x0000402C) + #define MCHBAR_CH0_CR_ROUND_TRIP_DFT_DATA_DATA_OFF ( 0) + #define MCHBAR_CH0_CR_ROUND_TRIP_DFT_DATA_DATA_WID (32) + #define MCHBAR_CH0_CR_ROUND_TRIP_DFT_DATA_DATA_MSK (0xFFFFFFFF) + #define MCHBAR_CH0_CR_ROUND_TRIP_DFT_DATA_DATA_MAX (0xFFFFFFFF) + #define MCHBAR_CH0_CR_ROUND_TRIP_DFT_DATA_DATA_DEF (0x00000000) + +#define MCHBAR_CH0_CR_DFT_MISC_REG (0x00004030) + #define MCHBAR_CH0_CR_DFT_MISC_WDAR_OFF ( 0) + #define MCHBAR_CH0_CR_DFT_MISC_WDAR_WID ( 1) + #define MCHBAR_CH0_CR_DFT_MISC_WDAR_MSK (0x00000001) + #define MCHBAR_CH0_CR_DFT_MISC_WDAR_MAX (0x00000001) + #define MCHBAR_CH0_CR_DFT_MISC_WDAR_DEF (0x00000000) + #define MCHBAR_CH0_CR_DFT_MISC_safe_mask_sel_OFF ( 1) + #define MCHBAR_CH0_CR_DFT_MISC_safe_mask_sel_WID ( 3) + #define MCHBAR_CH0_CR_DFT_MISC_safe_mask_sel_MSK (0x0000000E) + #define MCHBAR_CH0_CR_DFT_MISC_safe_mask_sel_MAX (0x00000007) + #define MCHBAR_CH0_CR_DFT_MISC_safe_mask_sel_DEF (0x00000000) + #define MCHBAR_CH0_CR_DFT_MISC_force_rcv_en_OFF ( 4) + #define MCHBAR_CH0_CR_DFT_MISC_force_rcv_en_WID ( 1) + #define MCHBAR_CH0_CR_DFT_MISC_force_rcv_en_MSK (0x00000010) + #define MCHBAR_CH0_CR_DFT_MISC_force_rcv_en_MAX (0x00000001) + #define MCHBAR_CH0_CR_DFT_MISC_force_rcv_en_DEF (0x00000000) + #define MCHBAR_CH0_CR_DFT_MISC_DDR_QUAL_OFF ( 8) + #define MCHBAR_CH0_CR_DFT_MISC_DDR_QUAL_WID ( 2) + #define MCHBAR_CH0_CR_DFT_MISC_DDR_QUAL_MSK (0x00000300) + #define MCHBAR_CH0_CR_DFT_MISC_DDR_QUAL_MAX (0x00000003) + #define MCHBAR_CH0_CR_DFT_MISC_DDR_QUAL_DEF (0x00000000) + #define MCHBAR_CH0_CR_DFT_MISC_Qual_length_OFF (10) + #define MCHBAR_CH0_CR_DFT_MISC_Qual_length_WID ( 2) + #define MCHBAR_CH0_CR_DFT_MISC_Qual_length_MSK (0x00000C00) + #define MCHBAR_CH0_CR_DFT_MISC_Qual_length_MAX (0x00000003) + #define MCHBAR_CH0_CR_DFT_MISC_Qual_length_DEF (0x00000000) + #define MCHBAR_CH0_CR_DFT_MISC_WDB_Block_En_OFF (12) + #define MCHBAR_CH0_CR_DFT_MISC_WDB_Block_En_WID ( 1) + #define MCHBAR_CH0_CR_DFT_MISC_WDB_Block_En_MSK (0x00001000) + #define MCHBAR_CH0_CR_DFT_MISC_WDB_Block_En_MAX (0x00000001) + #define MCHBAR_CH0_CR_DFT_MISC_WDB_Block_En_DEF (0x00000000) + #define MCHBAR_CH0_CR_DFT_MISC_RT_DFT_READ_PTR_OFF (13) + #define MCHBAR_CH0_CR_DFT_MISC_RT_DFT_READ_PTR_WID ( 4) + #define MCHBAR_CH0_CR_DFT_MISC_RT_DFT_READ_PTR_MSK (0x0001E000) + #define MCHBAR_CH0_CR_DFT_MISC_RT_DFT_READ_PTR_MAX (0x0000000F) + #define MCHBAR_CH0_CR_DFT_MISC_RT_DFT_READ_PTR_DEF (0x00000000) + #define MCHBAR_CH0_CR_DFT_MISC_RT_DFT_READ_ENABLE_OFF (17) + #define MCHBAR_CH0_CR_DFT_MISC_RT_DFT_READ_ENABLE_WID ( 1) + #define MCHBAR_CH0_CR_DFT_MISC_RT_DFT_READ_ENABLE_MSK (0x00020000) + #define MCHBAR_CH0_CR_DFT_MISC_RT_DFT_READ_ENABLE_MAX (0x00000001) + #define MCHBAR_CH0_CR_DFT_MISC_RT_DFT_READ_ENABLE_DEF (0x00000000) + #define MCHBAR_CH0_CR_DFT_MISC_RT_DFT_READ_SEL_ADDR_OFF (18) + #define MCHBAR_CH0_CR_DFT_MISC_RT_DFT_READ_SEL_ADDR_WID ( 1) + #define MCHBAR_CH0_CR_DFT_MISC_RT_DFT_READ_SEL_ADDR_MSK (0x00040000) + #define MCHBAR_CH0_CR_DFT_MISC_RT_DFT_READ_SEL_ADDR_MAX (0x00000001) + #define MCHBAR_CH0_CR_DFT_MISC_RT_DFT_READ_SEL_ADDR_DEF (0x00000000) + +#define MCHBAR_CH0_CR_READ_RETURN_DFT_REG (0x00004034) + #define MCHBAR_CH0_CR_READ_RETURN_DFT_ECC_OFF ( 0) + #define MCHBAR_CH0_CR_READ_RETURN_DFT_ECC_WID ( 8) + #define MCHBAR_CH0_CR_READ_RETURN_DFT_ECC_MSK (0x000000FF) + #define MCHBAR_CH0_CR_READ_RETURN_DFT_ECC_MAX (0x000000FF) + #define MCHBAR_CH0_CR_READ_RETURN_DFT_ECC_DEF (0x00000000) + #define MCHBAR_CH0_CR_READ_RETURN_DFT_RRD_DFT_Mode_OFF ( 8) + #define MCHBAR_CH0_CR_READ_RETURN_DFT_RRD_DFT_Mode_WID ( 2) + #define MCHBAR_CH0_CR_READ_RETURN_DFT_RRD_DFT_Mode_MSK (0x00000300) + #define MCHBAR_CH0_CR_READ_RETURN_DFT_RRD_DFT_Mode_MAX (0x00000003) + #define MCHBAR_CH0_CR_READ_RETURN_DFT_RRD_DFT_Mode_DEF (0x00000000) + #define MCHBAR_CH0_CR_READ_RETURN_DFT_LFSR_Seed_Index_OFF (10) + #define MCHBAR_CH0_CR_READ_RETURN_DFT_LFSR_Seed_Index_WID ( 5) + #define MCHBAR_CH0_CR_READ_RETURN_DFT_LFSR_Seed_Index_MSK (0x00007C00) + #define MCHBAR_CH0_CR_READ_RETURN_DFT_LFSR_Seed_Index_MAX (0x0000001F) + #define MCHBAR_CH0_CR_READ_RETURN_DFT_LFSR_Seed_Index_DEF (0x00000000) + #define MCHBAR_CH0_CR_READ_RETURN_DFT_Inversion_Mode_OFF (15) + #define MCHBAR_CH0_CR_READ_RETURN_DFT_Inversion_Mode_WID ( 1) + #define MCHBAR_CH0_CR_READ_RETURN_DFT_Inversion_Mode_MSK (0x00008000) + #define MCHBAR_CH0_CR_READ_RETURN_DFT_Inversion_Mode_MAX (0x00000001) + #define MCHBAR_CH0_CR_READ_RETURN_DFT_Inversion_Mode_DEF (0x00000000) + +#define MCHBAR_CH0_CR_SCHED_SECOND_CBIT_REG (0x00004038) + #define MCHBAR_CH0_CR_SCHED_SECOND_CBIT_dis_imph_error_OFF ( 0) + #define MCHBAR_CH0_CR_SCHED_SECOND_CBIT_dis_imph_error_WID ( 1) + #define MCHBAR_CH0_CR_SCHED_SECOND_CBIT_dis_imph_error_MSK (0x00000001) + #define MCHBAR_CH0_CR_SCHED_SECOND_CBIT_dis_imph_error_MAX (0x00000001) + #define MCHBAR_CH0_CR_SCHED_SECOND_CBIT_dis_imph_error_DEF (0x00000000) + #define MCHBAR_CH0_CR_SCHED_SECOND_CBIT_dis_async_odt_OFF ( 8) + #define MCHBAR_CH0_CR_SCHED_SECOND_CBIT_dis_async_odt_WID ( 1) + #define MCHBAR_CH0_CR_SCHED_SECOND_CBIT_dis_async_odt_MSK (0x00000100) + #define MCHBAR_CH0_CR_SCHED_SECOND_CBIT_dis_async_odt_MAX (0x00000001) + #define MCHBAR_CH0_CR_SCHED_SECOND_CBIT_dis_async_odt_DEF (0x00000000) + +#define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_REG (0x00004040) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux0_Control_OFF ( 0) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux0_Control_WID ( 2) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux0_Control_MSK (0x00000003) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux0_Control_MAX (0x00000003) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux0_Control_DEF (0x00000001) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux1_Control_OFF ( 3) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux1_Control_WID ( 2) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux1_Control_MSK (0x00000018) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux1_Control_MAX (0x00000003) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux1_Control_DEF (0x00000001) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux2_Control_OFF ( 6) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux2_Control_WID ( 2) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux2_Control_MSK (0x000000C0) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux2_Control_MAX (0x00000003) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux2_Control_DEF (0x00000001) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_ECC_Replace_Byte_Control_OFF (14) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_ECC_Replace_Byte_Control_WID ( 1) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_ECC_Replace_Byte_Control_MSK (0x00004000) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_ECC_Replace_Byte_Control_MAX (0x00000001) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_ECC_Replace_Byte_Control_DEF (0x00000001) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_ECC_Data_Source_Sel_OFF (15) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_ECC_Data_Source_Sel_WID ( 1) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_ECC_Data_Source_Sel_MSK (0x00008000) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_ECC_Data_Source_Sel_MAX (0x00000001) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_ECC_Data_Source_Sel_DEF (0x00000001) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Save_LFSR_Seed_Rate_OFF (16) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Save_LFSR_Seed_Rate_WID ( 6) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Save_LFSR_Seed_Rate_MSK (0x003F0000) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Save_LFSR_Seed_Rate_MAX (0x0000003F) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Save_LFSR_Seed_Rate_DEF (0x00000000) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Reload_LFSR_Seed_Rate_OFF (24) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Reload_LFSR_Seed_Rate_WID ( 3) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Reload_LFSR_Seed_Rate_MSK (0x07000000) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Reload_LFSR_Seed_Rate_MAX (0x00000007) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Reload_LFSR_Seed_Rate_DEF (0x00000000) + +#define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_RD_STATUS_REG (0x00004044) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_RD_STATUS_WDB_Current_Read_Pointer_OFF ( 0) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_RD_STATUS_WDB_Current_Read_Pointer_WID ( 6) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_RD_STATUS_WDB_Current_Read_Pointer_MSK (0x0000003F) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_RD_STATUS_WDB_Current_Read_Pointer_MAX (0x0000003F) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_RD_STATUS_WDB_Current_Read_Pointer_DEF (0x00000000) + +#define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_0_REG (0x00004048) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_0_Pattern_Buffer_OFF ( 0) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_0_Pattern_Buffer_WID (24) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_0_Pattern_Buffer_MSK (0x00FFFFFF) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_0_Pattern_Buffer_MAX (0x00FFFFFF) + +#define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_1_REG (0x0000404C) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_1_Pattern_Buffer_OFF ( 0) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_1_Pattern_Buffer_WID (24) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_1_Pattern_Buffer_MSK (0x00FFFFFF) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_1_Pattern_Buffer_MAX (0x00FFFFFF) + +#define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_2_REG (0x00004050) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_2_Pattern_Buffer_OFF ( 0) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_2_Pattern_Buffer_WID (24) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_2_Pattern_Buffer_MSK (0x00FFFFFF) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_2_Pattern_Buffer_MAX (0x00FFFFFF) + +#define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_0_REG (0x00004054) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_0_Pattern_Buffer_OFF ( 0) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_0_Pattern_Buffer_WID (24) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_0_Pattern_Buffer_MSK (0x00FFFFFF) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_0_Pattern_Buffer_MAX (0x00FFFFFF) + +#define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_1_REG (0x00004058) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_1_Pattern_Buffer_OFF ( 0) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_1_Pattern_Buffer_WID (24) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_1_Pattern_Buffer_MSK (0x00FFFFFF) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_1_Pattern_Buffer_MAX (0x00FFFFFF) + +#define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_2_REG (0x0000405C) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_2_Pattern_Buffer_OFF ( 0) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_2_Pattern_Buffer_WID (24) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_2_Pattern_Buffer_MSK (0x00FFFFFF) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_2_Pattern_Buffer_MAX (0x00FFFFFF) + +#define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_0_REG (0x00004060) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_0_Pattern_Buffer_OFF ( 0) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_0_Pattern_Buffer_WID (24) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_0_Pattern_Buffer_MSK (0x00FFFFFF) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_0_Pattern_Buffer_MAX (0x00FFFFFF) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_0_Pattern_Buffer_DEF (0x00000000) + +#define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_1_REG (0x00004064) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_1_Pattern_Buffer_OFF ( 0) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_1_Pattern_Buffer_WID (24) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_1_Pattern_Buffer_MSK (0x00FFFFFF) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_1_Pattern_Buffer_MAX (0x00FFFFFF) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_1_Pattern_Buffer_DEF (0x00000000) + +#define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_2_REG (0x00004068) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_2_Pattern_Buffer_OFF ( 0) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_2_Pattern_Buffer_WID (24) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_2_Pattern_Buffer_MSK (0x00FFFFFF) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_2_Pattern_Buffer_MAX (0x00FFFFFF) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_2_Pattern_Buffer_DEF (0x00000000) + +#define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_0_REG (0x0000406C) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_0_Pattern_Buffer_OFF ( 0) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_0_Pattern_Buffer_WID (24) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_0_Pattern_Buffer_MSK (0x00FFFFFF) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_0_Pattern_Buffer_MAX (0x00FFFFFF) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_0_Pattern_Buffer_DEF (0x00000000) + +#define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_1_REG (0x00004070) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_1_Pattern_Buffer_OFF ( 0) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_1_Pattern_Buffer_WID (24) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_1_Pattern_Buffer_MSK (0x00FFFFFF) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_1_Pattern_Buffer_MAX (0x00FFFFFF) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_1_Pattern_Buffer_DEF (0x00000000) + +#define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_2_REG (0x00004074) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_2_Pattern_Buffer_OFF ( 0) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_2_Pattern_Buffer_WID (24) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_2_Pattern_Buffer_MSK (0x00FFFFFF) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_2_Pattern_Buffer_MAX (0x00FFFFFF) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_2_Pattern_Buffer_DEF (0x00000000) + +#define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_REG (0x00004078) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_L_data_select_OFF ( 0) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_L_data_select_WID ( 1) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_L_data_select_MSK (0x00000001) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_L_data_select_MAX (0x00000001) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_L_data_select_DEF (0x00000000) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_Enable_Sweep_Frequency_OFF ( 1) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_Enable_Sweep_Frequency_WID ( 1) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_Enable_Sweep_Frequency_MSK (0x00000002) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_Enable_Sweep_Frequency_MAX (0x00000001) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_Enable_Sweep_Frequency_DEF (0x00000000) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_L_counter_OFF ( 8) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_L_counter_WID ( 8) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_L_counter_MSK (0x0000FF00) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_L_counter_MAX (0x000000FF) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_L_counter_DEF (0x00000001) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_M_counter_OFF (16) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_M_counter_WID ( 8) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_M_counter_MSK (0x00FF0000) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_M_counter_MAX (0x000000FF) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_M_counter_DEF (0x00000001) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_N_counter_OFF (24) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_N_counter_WID ( 8) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_N_counter_MSK (0xFF000000) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_N_counter_MAX (0x000000FF) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_N_counter_DEF (0x00000001) + +#define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_INV_REG (0x00004084) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_INV_ECC_Inv_or_DC_Enable_OFF ( 0) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_INV_ECC_Inv_or_DC_Enable_WID ( 8) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_INV_ECC_Inv_or_DC_Enable_MSK (0x000000FF) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_INV_ECC_Inv_or_DC_Enable_MAX (0x000000FF) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_INV_ECC_Inv_or_DC_Enable_DEF (0x00000000) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Shift_Rate_OFF (16) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Shift_Rate_WID ( 4) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Shift_Rate_MSK (0x000F0000) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Shift_Rate_MAX (0x0000000F) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Shift_Rate_DEF (0x00000000) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_INV_DC_Polarity_Control_OFF (20) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_INV_DC_Polarity_Control_WID ( 1) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_INV_DC_Polarity_Control_MSK (0x00100000) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_INV_DC_Polarity_Control_MAX (0x00000001) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_INV_DC_Polarity_Control_DEF (0x00000000) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Control_OFF (30) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Control_WID ( 1) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Control_MSK (0x40000000) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Control_MAX (0x00000001) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Control_DEF (0x00000000) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Shift_Enable_OFF (31) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Shift_Enable_WID ( 1) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Shift_Enable_MSK (0x80000000) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Shift_Enable_MAX (0x00000001) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Shift_Enable_DEF (0x00000000) + +#define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_DATA_INV_REG (0x00004090) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_DATA_INV_Data_Inv_or_DC_Enable_OFF ( 0) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_DATA_INV_Data_Inv_or_DC_Enable_WID (64) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_DATA_INV_Data_Inv_or_DC_Enable_MSK (0xFFFFFFFFFFFFFFFF) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_DATA_INV_Data_Inv_or_DC_Enable_MAX (0xFFFFFFFFFFFFFFFF) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_DATA_INV_Data_Inv_or_DC_Enable_DEF (0x00000000) + +#define MCHBAR_CH0_CR_REUT_CH_ERR_CTL_REG (0x00004098) + #define MCHBAR_CH0_CR_REUT_CH_ERR_CTL_Stop_on_Nth_Error_OFF ( 0) + #define MCHBAR_CH0_CR_REUT_CH_ERR_CTL_Stop_on_Nth_Error_WID ( 6) + #define MCHBAR_CH0_CR_REUT_CH_ERR_CTL_Stop_on_Nth_Error_MSK (0x0000003F) + #define MCHBAR_CH0_CR_REUT_CH_ERR_CTL_Stop_on_Nth_Error_MAX (0x0000003F) + #define MCHBAR_CH0_CR_REUT_CH_ERR_CTL_Stop_on_Nth_Error_DEF (0x00000001) + #define MCHBAR_CH0_CR_REUT_CH_ERR_CTL_Stop_On_Error_Control_OFF (12) + #define MCHBAR_CH0_CR_REUT_CH_ERR_CTL_Stop_On_Error_Control_WID ( 2) + #define MCHBAR_CH0_CR_REUT_CH_ERR_CTL_Stop_On_Error_Control_MSK (0x00003000) + #define MCHBAR_CH0_CR_REUT_CH_ERR_CTL_Stop_On_Error_Control_MAX (0x00000003) + #define MCHBAR_CH0_CR_REUT_CH_ERR_CTL_Stop_On_Error_Control_DEF (0x00000000) + #define MCHBAR_CH0_CR_REUT_CH_ERR_CTL_Selective_Error_Enable_Chunk_OFF (16) + #define MCHBAR_CH0_CR_REUT_CH_ERR_CTL_Selective_Error_Enable_Chunk_WID ( 8) + #define MCHBAR_CH0_CR_REUT_CH_ERR_CTL_Selective_Error_Enable_Chunk_MSK (0x00FF0000) + #define MCHBAR_CH0_CR_REUT_CH_ERR_CTL_Selective_Error_Enable_Chunk_MAX (0x000000FF) + #define MCHBAR_CH0_CR_REUT_CH_ERR_CTL_Selective_Error_Enable_Chunk_DEF (0x000000FF) + #define MCHBAR_CH0_CR_REUT_CH_ERR_CTL_Selective_Error_Enable_Cacheline_OFF (24) + #define MCHBAR_CH0_CR_REUT_CH_ERR_CTL_Selective_Error_Enable_Cacheline_WID ( 8) + #define MCHBAR_CH0_CR_REUT_CH_ERR_CTL_Selective_Error_Enable_Cacheline_MSK (0xFF000000) + #define MCHBAR_CH0_CR_REUT_CH_ERR_CTL_Selective_Error_Enable_Cacheline_MAX (0x000000FF) + #define MCHBAR_CH0_CR_REUT_CH_ERR_CTL_Selective_Error_Enable_Cacheline_DEF (0x000000FF) + +#define MCHBAR_CH0_CR_REUT_CH_ERR_ECC_MASK_REG (0x0000409C) + #define MCHBAR_CH0_CR_REUT_CH_ERR_ECC_MASK_ECC_Error_Mask_OFF ( 0) + #define MCHBAR_CH0_CR_REUT_CH_ERR_ECC_MASK_ECC_Error_Mask_WID ( 8) + #define MCHBAR_CH0_CR_REUT_CH_ERR_ECC_MASK_ECC_Error_Mask_MSK (0x000000FF) + #define MCHBAR_CH0_CR_REUT_CH_ERR_ECC_MASK_ECC_Error_Mask_MAX (0x000000FF) + #define MCHBAR_CH0_CR_REUT_CH_ERR_ECC_MASK_ECC_Error_Mask_DEF (0x00000000) + +#define MCHBAR_CH0_CR_STM_CONFIG_REG (0x000040A4) + #define MCHBAR_CH0_CR_STM_CONFIG_Stretch_mode_OFF ( 0) + #define MCHBAR_CH0_CR_STM_CONFIG_Stretch_mode_WID ( 2) + #define MCHBAR_CH0_CR_STM_CONFIG_Stretch_mode_MSK (0x00000003) + #define MCHBAR_CH0_CR_STM_CONFIG_Stretch_mode_MAX (0x00000003) + #define MCHBAR_CH0_CR_STM_CONFIG_Stretch_mode_DEF (0x00000000) + #define MCHBAR_CH0_CR_STM_CONFIG_STF_OFF ( 4) + #define MCHBAR_CH0_CR_STM_CONFIG_STF_WID ( 3) + #define MCHBAR_CH0_CR_STM_CONFIG_STF_MSK (0x00000070) + #define MCHBAR_CH0_CR_STM_CONFIG_STF_MAX (0x00000007) + #define MCHBAR_CH0_CR_STM_CONFIG_STF_DEF (0x00000000) + +#define MCHBAR_CH0_CR_SC_PR_CNT_CONFIG_REG (0x000040A8) + #define MCHBAR_CH0_CR_SC_PR_CNT_CONFIG_Priority_count_ring_OFF ( 0) + #define MCHBAR_CH0_CR_SC_PR_CNT_CONFIG_Priority_count_ring_WID (10) + #define MCHBAR_CH0_CR_SC_PR_CNT_CONFIG_Priority_count_ring_MSK (0x000003FF) + #define MCHBAR_CH0_CR_SC_PR_CNT_CONFIG_Priority_count_ring_MAX (0x000003FF) + #define MCHBAR_CH0_CR_SC_PR_CNT_CONFIG_Priority_count_ring_DEF (0x00000040) + #define MCHBAR_CH0_CR_SC_PR_CNT_CONFIG_Priority_count_SA_OFF (16) + #define MCHBAR_CH0_CR_SC_PR_CNT_CONFIG_Priority_count_SA_WID (10) + #define MCHBAR_CH0_CR_SC_PR_CNT_CONFIG_Priority_count_SA_MSK (0x03FF0000) + #define MCHBAR_CH0_CR_SC_PR_CNT_CONFIG_Priority_count_SA_MAX (0x000003FF) + #define MCHBAR_CH0_CR_SC_PR_CNT_CONFIG_Priority_count_SA_DEF (0x00000100) + +#define MCHBAR_CH0_CR_SC_PCIT_REG (0x000040AC) + #define MCHBAR_CH0_CR_SC_PCIT_PCIT_OFF ( 0) + #define MCHBAR_CH0_CR_SC_PCIT_PCIT_WID ( 8) + #define MCHBAR_CH0_CR_SC_PCIT_PCIT_MSK (0x000000FF) + #define MCHBAR_CH0_CR_SC_PCIT_PCIT_MAX (0x000000FF) + #define MCHBAR_CH0_CR_SC_PCIT_PCIT_DEF (0x00000040) + +#define MCHBAR_CH0_CR_PM_PDWN_CONFIG_REG (0x000040B0) + #define MCHBAR_CH0_CR_PM_PDWN_CONFIG_PDWN_idle_counter_OFF ( 0) + #define MCHBAR_CH0_CR_PM_PDWN_CONFIG_PDWN_idle_counter_WID (12) + #define MCHBAR_CH0_CR_PM_PDWN_CONFIG_PDWN_idle_counter_MSK (0x00000FFF) + #define MCHBAR_CH0_CR_PM_PDWN_CONFIG_PDWN_idle_counter_MAX (0x00000FFF) + #define MCHBAR_CH0_CR_PM_PDWN_CONFIG_PDWN_idle_counter_DEF (0x00000000) + #define MCHBAR_CH0_CR_PM_PDWN_CONFIG_PDWN_mode_OFF (12) + #define MCHBAR_CH0_CR_PM_PDWN_CONFIG_PDWN_mode_WID ( 4) + #define MCHBAR_CH0_CR_PM_PDWN_CONFIG_PDWN_mode_MSK (0x0000F000) + #define MCHBAR_CH0_CR_PM_PDWN_CONFIG_PDWN_mode_MAX (0x0000000F) + #define MCHBAR_CH0_CR_PM_PDWN_CONFIG_PDWN_mode_DEF (0x00000000) + +#define MCHBAR_CH0_CR_ECC_INJECT_COUNT_REG (0x000040B4) + #define MCHBAR_CH0_CR_ECC_INJECT_COUNT_Count_OFF ( 0) + #define MCHBAR_CH0_CR_ECC_INJECT_COUNT_Count_WID (32) + #define MCHBAR_CH0_CR_ECC_INJECT_COUNT_Count_MSK (0xFFFFFFFF) + #define MCHBAR_CH0_CR_ECC_INJECT_COUNT_Count_MAX (0xFFFFFFFF) + #define MCHBAR_CH0_CR_ECC_INJECT_COUNT_Count_DEF (0xFFFFFFFF) + +#define MCHBAR_CH0_CR_ECC_DFT_REG (0x000040B8) + #define MCHBAR_CH0_CR_ECC_DFT_ECC4ANA_fill_OFF ( 0) + #define MCHBAR_CH0_CR_ECC_DFT_ECC4ANA_fill_WID ( 8) + #define MCHBAR_CH0_CR_ECC_DFT_ECC4ANA_fill_MSK (0x000000FF) + #define MCHBAR_CH0_CR_ECC_DFT_ECC4ANA_fill_MAX (0x000000FF) + #define MCHBAR_CH0_CR_ECC_DFT_ECC4ANA_fill_DEF (0x00000000) + #define MCHBAR_CH0_CR_ECC_DFT_ECC4ANA_trigger_OFF ( 8) + #define MCHBAR_CH0_CR_ECC_DFT_ECC4ANA_trigger_WID ( 2) + #define MCHBAR_CH0_CR_ECC_DFT_ECC4ANA_trigger_MSK (0x00000300) + #define MCHBAR_CH0_CR_ECC_DFT_ECC4ANA_trigger_MAX (0x00000003) + #define MCHBAR_CH0_CR_ECC_DFT_ECC4ANA_trigger_DEF (0x00000000) + #define MCHBAR_CH0_CR_ECC_DFT_ECC4ANA_BS_OFF (10) + #define MCHBAR_CH0_CR_ECC_DFT_ECC4ANA_BS_WID ( 1) + #define MCHBAR_CH0_CR_ECC_DFT_ECC4ANA_BS_MSK (0x00000400) + #define MCHBAR_CH0_CR_ECC_DFT_ECC4ANA_BS_MAX (0x00000001) + #define MCHBAR_CH0_CR_ECC_DFT_ECC4ANA_BS_DEF (0x00000000) + #define MCHBAR_CH0_CR_ECC_DFT_ECC_Inject_OFF (11) + #define MCHBAR_CH0_CR_ECC_DFT_ECC_Inject_WID ( 3) + #define MCHBAR_CH0_CR_ECC_DFT_ECC_Inject_MSK (0x00003800) + #define MCHBAR_CH0_CR_ECC_DFT_ECC_Inject_MAX (0x00000007) + #define MCHBAR_CH0_CR_ECC_DFT_ECC_Inject_DEF (0x00000000) + #define MCHBAR_CH0_CR_ECC_DFT_ECC_correction_disable_OFF (14) + #define MCHBAR_CH0_CR_ECC_DFT_ECC_correction_disable_WID ( 1) + #define MCHBAR_CH0_CR_ECC_DFT_ECC_correction_disable_MSK (0x00004000) + #define MCHBAR_CH0_CR_ECC_DFT_ECC_correction_disable_MAX (0x00000001) + #define MCHBAR_CH0_CR_ECC_DFT_ECC_correction_disable_DEF (0x00000000) + #define MCHBAR_CH0_CR_ECC_DFT_ECC4ANA_Inject_OFF (15) + #define MCHBAR_CH0_CR_ECC_DFT_ECC4ANA_Inject_WID ( 1) + #define MCHBAR_CH0_CR_ECC_DFT_ECC4ANA_Inject_MSK (0x00008000) + #define MCHBAR_CH0_CR_ECC_DFT_ECC4ANA_Inject_MAX (0x00000001) + #define MCHBAR_CH0_CR_ECC_DFT_ECC4ANA_Inject_DEF (0x00000000) + #define MCHBAR_CH0_CR_ECC_DFT_DIS_MCA_LOG_OFF (16) + #define MCHBAR_CH0_CR_ECC_DFT_DIS_MCA_LOG_WID ( 1) + #define MCHBAR_CH0_CR_ECC_DFT_DIS_MCA_LOG_MSK (0x00010000) + #define MCHBAR_CH0_CR_ECC_DFT_DIS_MCA_LOG_MAX (0x00000001) + #define MCHBAR_CH0_CR_ECC_DFT_DIS_MCA_LOG_DEF (0x00000000) + #define MCHBAR_CH0_CR_ECC_DFT_DIS_PCH_EVENT_OFF (17) + #define MCHBAR_CH0_CR_ECC_DFT_DIS_PCH_EVENT_WID ( 1) + #define MCHBAR_CH0_CR_ECC_DFT_DIS_PCH_EVENT_MSK (0x00020000) + #define MCHBAR_CH0_CR_ECC_DFT_DIS_PCH_EVENT_MAX (0x00000001) + #define MCHBAR_CH0_CR_ECC_DFT_DIS_PCH_EVENT_DEF (0x00000000) + #define MCHBAR_CH0_CR_ECC_DFT_DIS_PCIE_POISON_OFF (18) + #define MCHBAR_CH0_CR_ECC_DFT_DIS_PCIE_POISON_WID ( 1) + #define MCHBAR_CH0_CR_ECC_DFT_DIS_PCIE_POISON_MSK (0x00040000) + #define MCHBAR_CH0_CR_ECC_DFT_DIS_PCIE_POISON_MAX (0x00000001) + #define MCHBAR_CH0_CR_ECC_DFT_DIS_PCIE_POISON_DEF (0x00000000) + +#define MCHBAR_CH0_CR_VISA_CTL_MCSCHEDS_REG (0x000040C0) + #define MCHBAR_CH0_CR_VISA_CTL_MCSCHEDS_Data_OFF ( 0) + #define MCHBAR_CH0_CR_VISA_CTL_MCSCHEDS_Data_WID (18) + #define MCHBAR_CH0_CR_VISA_CTL_MCSCHEDS_Data_MSK (0x0003FFFF) + #define MCHBAR_CH0_CR_VISA_CTL_MCSCHEDS_Data_MAX (0x0003FFFF) + #define MCHBAR_CH0_CR_VISA_CTL_MCSCHEDS_Data_DEF (0x00000000) + #define MCHBAR_CH0_CR_VISA_CTL_MCSCHEDS_VORANGE_OFF (31) + #define MCHBAR_CH0_CR_VISA_CTL_MCSCHEDS_VORANGE_WID ( 1) + #define MCHBAR_CH0_CR_VISA_CTL_MCSCHEDS_VORANGE_MSK (0x80000000) + #define MCHBAR_CH0_CR_VISA_CTL_MCSCHEDS_VORANGE_MAX (0x00000001) + #define MCHBAR_CH0_CR_VISA_CTL_MCSCHEDS_VORANGE_DEF (0x00000000) + +#define MCHBAR_CH0_CR_VISA_XBAR_MCSCHEDS_REG (0x000040C4) + #define MCHBAR_CH0_CR_VISA_XBAR_MCSCHEDS_Data_OFF ( 0) + #define MCHBAR_CH0_CR_VISA_XBAR_MCSCHEDS_Data_WID (32) + #define MCHBAR_CH0_CR_VISA_XBAR_MCSCHEDS_Data_MSK (0xFFFFFFFF) + #define MCHBAR_CH0_CR_VISA_XBAR_MCSCHEDS_Data_MAX (0xFFFFFFFF) + #define MCHBAR_CH0_CR_VISA_XBAR_MCSCHEDS_Data_DEF (0x76543210) + +#define MCHBAR_CH0_CR_ECCERRLOG0_REG (0x000040C8) + #define MCHBAR_CH0_CR_ECCERRLOG0_CERRSTS_OFF ( 0) + #define MCHBAR_CH0_CR_ECCERRLOG0_CERRSTS_WID ( 1) + #define MCHBAR_CH0_CR_ECCERRLOG0_CERRSTS_MSK (0x00000001) + #define MCHBAR_CH0_CR_ECCERRLOG0_CERRSTS_MAX (0x00000001) + #define MCHBAR_CH0_CR_ECCERRLOG0_CERRSTS_DEF (0x00000000) + #define MCHBAR_CH0_CR_ECCERRLOG0_MERRSTS_OFF ( 1) + #define MCHBAR_CH0_CR_ECCERRLOG0_MERRSTS_WID ( 1) + #define MCHBAR_CH0_CR_ECCERRLOG0_MERRSTS_MSK (0x00000002) + #define MCHBAR_CH0_CR_ECCERRLOG0_MERRSTS_MAX (0x00000001) + #define MCHBAR_CH0_CR_ECCERRLOG0_MERRSTS_DEF (0x00000000) + #define MCHBAR_CH0_CR_ECCERRLOG0_ERRSYND_OFF (16) + #define MCHBAR_CH0_CR_ECCERRLOG0_ERRSYND_WID ( 8) + #define MCHBAR_CH0_CR_ECCERRLOG0_ERRSYND_MSK (0x00FF0000) + #define MCHBAR_CH0_CR_ECCERRLOG0_ERRSYND_MAX (0x000000FF) + #define MCHBAR_CH0_CR_ECCERRLOG0_ERRSYND_DEF (0x00000000) + #define MCHBAR_CH0_CR_ECCERRLOG0_ERRCHUNK_OFF (24) + #define MCHBAR_CH0_CR_ECCERRLOG0_ERRCHUNK_WID ( 3) + #define MCHBAR_CH0_CR_ECCERRLOG0_ERRCHUNK_MSK (0x07000000) + #define MCHBAR_CH0_CR_ECCERRLOG0_ERRCHUNK_MAX (0x00000007) + #define MCHBAR_CH0_CR_ECCERRLOG0_ERRCHUNK_DEF (0x00000000) + #define MCHBAR_CH0_CR_ECCERRLOG0_ERRRANK_OFF (27) + #define MCHBAR_CH0_CR_ECCERRLOG0_ERRRANK_WID ( 2) + #define MCHBAR_CH0_CR_ECCERRLOG0_ERRRANK_MSK (0x18000000) + #define MCHBAR_CH0_CR_ECCERRLOG0_ERRRANK_MAX (0x00000003) + #define MCHBAR_CH0_CR_ECCERRLOG0_ERRRANK_DEF (0x00000000) + #define MCHBAR_CH0_CR_ECCERRLOG0_ERRBANK_OFF (29) + #define MCHBAR_CH0_CR_ECCERRLOG0_ERRBANK_WID ( 3) + #define MCHBAR_CH0_CR_ECCERRLOG0_ERRBANK_MSK (0xE0000000) + #define MCHBAR_CH0_CR_ECCERRLOG0_ERRBANK_MAX (0x00000007) + #define MCHBAR_CH0_CR_ECCERRLOG0_ERRBANK_DEF (0x00000000) + +#define MCHBAR_CH0_CR_ECCERRLOG1_REG (0x000040CC) + #define MCHBAR_CH0_CR_ECCERRLOG1_ERRROW_OFF ( 0) + #define MCHBAR_CH0_CR_ECCERRLOG1_ERRROW_WID (16) + #define MCHBAR_CH0_CR_ECCERRLOG1_ERRROW_MSK (0x0000FFFF) + #define MCHBAR_CH0_CR_ECCERRLOG1_ERRROW_MAX (0x0000FFFF) + #define MCHBAR_CH0_CR_ECCERRLOG1_ERRROW_DEF (0x00000000) + #define MCHBAR_CH0_CR_ECCERRLOG1_ERRCOL_OFF (16) + #define MCHBAR_CH0_CR_ECCERRLOG1_ERRCOL_WID (16) + #define MCHBAR_CH0_CR_ECCERRLOG1_ERRCOL_MSK (0xFFFF0000) + #define MCHBAR_CH0_CR_ECCERRLOG1_ERRCOL_MAX (0x0000FFFF) + #define MCHBAR_CH0_CR_ECCERRLOG1_ERRCOL_DEF (0x00000000) + +#define MCHBAR_CH0_CR_SC_WR_ADD_DELAY_REG (0x000040D0) + #define MCHBAR_CH0_CR_SC_WR_ADD_DELAY_D0R0_OFF ( 0) + #define MCHBAR_CH0_CR_SC_WR_ADD_DELAY_D0R0_WID ( 2) + #define MCHBAR_CH0_CR_SC_WR_ADD_DELAY_D0R0_MSK (0x00000003) + #define MCHBAR_CH0_CR_SC_WR_ADD_DELAY_D0R0_MAX (0x00000003) + #define MCHBAR_CH0_CR_SC_WR_ADD_DELAY_D0R0_DEF (0x00000000) + #define MCHBAR_CH0_CR_SC_WR_ADD_DELAY_D0R1_OFF ( 2) + #define MCHBAR_CH0_CR_SC_WR_ADD_DELAY_D0R1_WID ( 2) + #define MCHBAR_CH0_CR_SC_WR_ADD_DELAY_D0R1_MSK (0x0000000C) + #define MCHBAR_CH0_CR_SC_WR_ADD_DELAY_D0R1_MAX (0x00000003) + #define MCHBAR_CH0_CR_SC_WR_ADD_DELAY_D0R1_DEF (0x00000000) + #define MCHBAR_CH0_CR_SC_WR_ADD_DELAY_D1R0_OFF ( 4) + #define MCHBAR_CH0_CR_SC_WR_ADD_DELAY_D1R0_WID ( 2) + #define MCHBAR_CH0_CR_SC_WR_ADD_DELAY_D1R0_MSK (0x00000030) + #define MCHBAR_CH0_CR_SC_WR_ADD_DELAY_D1R0_MAX (0x00000003) + #define MCHBAR_CH0_CR_SC_WR_ADD_DELAY_D1R0_DEF (0x00000000) + #define MCHBAR_CH0_CR_SC_WR_ADD_DELAY_D1R1_OFF ( 6) + #define MCHBAR_CH0_CR_SC_WR_ADD_DELAY_D1R1_WID ( 2) + #define MCHBAR_CH0_CR_SC_WR_ADD_DELAY_D1R1_MSK (0x000000C0) + #define MCHBAR_CH0_CR_SC_WR_ADD_DELAY_D1R1_MAX (0x00000003) + #define MCHBAR_CH0_CR_SC_WR_ADD_DELAY_D1R1_DEF (0x00000000) + +#define MCHBAR_CH0_CR_WMM_READ_CONFIG_REG (0x000040D4) + #define MCHBAR_CH0_CR_WMM_READ_CONFIG_Dis_Opp_rd_OFF ( 0) + #define MCHBAR_CH0_CR_WMM_READ_CONFIG_Dis_Opp_rd_WID ( 1) + #define MCHBAR_CH0_CR_WMM_READ_CONFIG_Dis_Opp_rd_MSK (0x00000001) + #define MCHBAR_CH0_CR_WMM_READ_CONFIG_Dis_Opp_rd_MAX (0x00000001) + #define MCHBAR_CH0_CR_WMM_READ_CONFIG_Dis_Opp_rd_DEF (0x00000000) + #define MCHBAR_CH0_CR_WMM_READ_CONFIG_ACT_Enable_OFF ( 1) + #define MCHBAR_CH0_CR_WMM_READ_CONFIG_ACT_Enable_WID ( 1) + #define MCHBAR_CH0_CR_WMM_READ_CONFIG_ACT_Enable_MSK (0x00000002) + #define MCHBAR_CH0_CR_WMM_READ_CONFIG_ACT_Enable_MAX (0x00000001) + #define MCHBAR_CH0_CR_WMM_READ_CONFIG_ACT_Enable_DEF (0x00000001) + #define MCHBAR_CH0_CR_WMM_READ_CONFIG_PRE_Enable_OFF ( 2) + #define MCHBAR_CH0_CR_WMM_READ_CONFIG_PRE_Enable_WID ( 1) + #define MCHBAR_CH0_CR_WMM_READ_CONFIG_PRE_Enable_MSK (0x00000004) + #define MCHBAR_CH0_CR_WMM_READ_CONFIG_PRE_Enable_MAX (0x00000001) + #define MCHBAR_CH0_CR_WMM_READ_CONFIG_PRE_Enable_DEF (0x00000001) + #define MCHBAR_CH0_CR_WMM_READ_CONFIG_MAX_RPQ_Cas_OFF ( 3) + #define MCHBAR_CH0_CR_WMM_READ_CONFIG_MAX_RPQ_Cas_WID ( 4) + #define MCHBAR_CH0_CR_WMM_READ_CONFIG_MAX_RPQ_Cas_MSK (0x00000078) + #define MCHBAR_CH0_CR_WMM_READ_CONFIG_MAX_RPQ_Cas_MAX (0x0000000F) + #define MCHBAR_CH0_CR_WMM_READ_CONFIG_MAX_RPQ_Cas_DEF (0x00000008) + +#define MCHBAR_CH0_CR_REUT_CH_ERR_DATA_MASK_REG (0x000040D8) + #define MCHBAR_CH0_CR_REUT_CH_ERR_DATA_MASK_Data_Error_Mask_OFF ( 0) + #define MCHBAR_CH0_CR_REUT_CH_ERR_DATA_MASK_Data_Error_Mask_WID (64) + #define MCHBAR_CH0_CR_REUT_CH_ERR_DATA_MASK_Data_Error_Mask_MSK (0xFFFFFFFFFFFFFFFF) + #define MCHBAR_CH0_CR_REUT_CH_ERR_DATA_MASK_Data_Error_Mask_MAX (0xFFFFFFFFFFFFFFFF) + #define MCHBAR_CH0_CR_REUT_CH_ERR_DATA_MASK_Data_Error_Mask_DEF (0x00000000) + +#define MCHBAR_CH0_CR_REUT_CH_ERR_DATA_STATUS_REG (0x000040E0) + #define MCHBAR_CH0_CR_REUT_CH_ERR_DATA_STATUS_Data_Error_Status_OFF ( 0) + #define MCHBAR_CH0_CR_REUT_CH_ERR_DATA_STATUS_Data_Error_Status_WID (64) + #define MCHBAR_CH0_CR_REUT_CH_ERR_DATA_STATUS_Data_Error_Status_MSK (0xFFFFFFFFFFFFFFFF) + #define MCHBAR_CH0_CR_REUT_CH_ERR_DATA_STATUS_Data_Error_Status_MAX (0xFFFFFFFFFFFFFFFF) + #define MCHBAR_CH0_CR_REUT_CH_ERR_DATA_STATUS_Data_Error_Status_DEF (0x00000000) + +#define MCHBAR_CH0_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_REG (0x000040E8) + #define MCHBAR_CH0_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_ECC_Error_Status_OFF ( 0) + #define MCHBAR_CH0_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_ECC_Error_Status_WID ( 8) + #define MCHBAR_CH0_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_ECC_Error_Status_MSK (0x000000FF) + #define MCHBAR_CH0_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_ECC_Error_Status_MAX (0x000000FF) + #define MCHBAR_CH0_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_ECC_Error_Status_DEF (0x00000000) + #define MCHBAR_CH0_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Chunk_Error_Status_OFF ( 8) + #define MCHBAR_CH0_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Chunk_Error_Status_WID ( 8) + #define MCHBAR_CH0_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Chunk_Error_Status_MSK (0x0000FF00) + #define MCHBAR_CH0_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Chunk_Error_Status_MAX (0x000000FF) + #define MCHBAR_CH0_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Chunk_Error_Status_DEF (0x00000000) + #define MCHBAR_CH0_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Rank_Error_Status_OFF (16) + #define MCHBAR_CH0_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Rank_Error_Status_WID ( 4) + #define MCHBAR_CH0_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Rank_Error_Status_MSK (0x000F0000) + #define MCHBAR_CH0_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Rank_Error_Status_MAX (0x0000000F) + #define MCHBAR_CH0_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Rank_Error_Status_DEF (0x00000000) + #define MCHBAR_CH0_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Byte_Group_Error_Status_OFF (32) + #define MCHBAR_CH0_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Byte_Group_Error_Status_WID ( 9) + #define MCHBAR_CH0_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Byte_Group_Error_Status_MSK (0x1FF00000000) + #define MCHBAR_CH0_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Byte_Group_Error_Status_MAX (0x000001FF) + #define MCHBAR_CH0_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Byte_Group_Error_Status_DEF (0x00000000) + #define MCHBAR_CH0_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_WDB_Rd_Chunk_Num_Status_OFF (52) + #define MCHBAR_CH0_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_WDB_Rd_Chunk_Num_Status_WID ( 3) + #define MCHBAR_CH0_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_WDB_Rd_Chunk_Num_Status_MSK (0x70000000000000) + #define MCHBAR_CH0_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_WDB_Rd_Chunk_Num_Status_MAX (0x00000007) + #define MCHBAR_CH0_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_WDB_Rd_Chunk_Num_Status_DEF (0x00000000) + #define MCHBAR_CH0_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Nth_Error_OFF (56) + #define MCHBAR_CH0_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Nth_Error_WID ( 6) + #define MCHBAR_CH0_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Nth_Error_MSK (0x3F00000000000000) + #define MCHBAR_CH0_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Nth_Error_MAX (0x0000003F) + #define MCHBAR_CH0_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Nth_Error_DEF (0x00000000) + +#define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_0_REG (0x000040F0) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_0_Counter_Pointer_OFF ( 0) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_0_Counter_Pointer_WID ( 7) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_0_Counter_Pointer_MSK (0x0000007F) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_0_Counter_Pointer_MAX (0x0000007F) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_0_Counter_Pointer_DEF (0x0000007F) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_0_Counter_Control_OFF ( 7) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_0_Counter_Control_WID ( 2) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_0_Counter_Control_MSK (0x00000180) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_0_Counter_Control_MAX (0x00000003) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_0_Counter_Control_DEF (0x00000000) + +#define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_1_REG (0x000040F4) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_1_Counter_Pointer_OFF ( 0) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_1_Counter_Pointer_WID ( 7) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_1_Counter_Pointer_MSK (0x0000007F) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_1_Counter_Pointer_MAX (0x0000007F) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_1_Counter_Pointer_DEF (0x0000007F) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_1_Counter_Control_OFF ( 7) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_1_Counter_Control_WID ( 2) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_1_Counter_Control_MSK (0x00000180) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_1_Counter_Control_MAX (0x00000003) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_1_Counter_Control_DEF (0x00000000) + +#define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_2_REG (0x000040F8) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_2_Counter_Pointer_OFF ( 0) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_2_Counter_Pointer_WID ( 7) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_2_Counter_Pointer_MSK (0x0000007F) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_2_Counter_Pointer_MAX (0x0000007F) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_2_Counter_Pointer_DEF (0x0000007F) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_2_Counter_Control_OFF ( 7) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_2_Counter_Control_WID ( 2) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_2_Counter_Control_MSK (0x00000180) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_2_Counter_Control_MAX (0x00000003) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_2_Counter_Control_DEF (0x00000000) + +#define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_3_REG (0x000040FC) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_3_Counter_Pointer_OFF ( 0) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_3_Counter_Pointer_WID ( 7) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_3_Counter_Pointer_MSK (0x0000007F) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_3_Counter_Pointer_MAX (0x0000007F) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_3_Counter_Pointer_DEF (0x0000007F) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_3_Counter_Control_OFF ( 7) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_3_Counter_Control_WID ( 2) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_3_Counter_Control_MSK (0x00000180) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_3_Counter_Control_MAX (0x00000003) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_3_Counter_Control_DEF (0x00000000) + +#define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_4_REG (0x00004100) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_4_Counter_Pointer_OFF ( 0) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_4_Counter_Pointer_WID ( 7) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_4_Counter_Pointer_MSK (0x0000007F) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_4_Counter_Pointer_MAX (0x0000007F) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_4_Counter_Pointer_DEF (0x0000007F) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_4_Counter_Control_OFF ( 7) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_4_Counter_Control_WID ( 2) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_4_Counter_Control_MSK (0x00000180) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_4_Counter_Control_MAX (0x00000003) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_4_Counter_Control_DEF (0x00000000) + +#define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_5_REG (0x00004104) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_5_Counter_Pointer_OFF ( 0) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_5_Counter_Pointer_WID ( 7) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_5_Counter_Pointer_MSK (0x0000007F) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_5_Counter_Pointer_MAX (0x0000007F) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_5_Counter_Pointer_DEF (0x0000007F) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_5_Counter_Control_OFF ( 7) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_5_Counter_Control_WID ( 2) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_5_Counter_Control_MSK (0x00000180) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_5_Counter_Control_MAX (0x00000003) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_5_Counter_Control_DEF (0x00000000) + +#define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_6_REG (0x00004108) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_6_Counter_Pointer_OFF ( 0) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_6_Counter_Pointer_WID ( 7) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_6_Counter_Pointer_MSK (0x0000007F) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_6_Counter_Pointer_MAX (0x0000007F) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_6_Counter_Pointer_DEF (0x0000007F) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_6_Counter_Control_OFF ( 7) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_6_Counter_Control_WID ( 2) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_6_Counter_Control_MSK (0x00000180) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_6_Counter_Control_MAX (0x00000003) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_6_Counter_Control_DEF (0x00000000) + +#define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_7_REG (0x0000410C) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_7_Counter_Pointer_OFF ( 0) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_7_Counter_Pointer_WID ( 7) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_7_Counter_Pointer_MSK (0x0000007F) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_7_Counter_Pointer_MAX (0x0000007F) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_7_Counter_Pointer_DEF (0x0000007F) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_7_Counter_Control_OFF ( 7) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_7_Counter_Control_WID ( 2) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_7_Counter_Control_MSK (0x00000180) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_7_Counter_Control_MAX (0x00000003) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_7_Counter_Control_DEF (0x00000000) + +#define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_8_REG (0x00004110) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_8_Counter_Pointer_OFF ( 0) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_8_Counter_Pointer_WID ( 7) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_8_Counter_Pointer_MSK (0x0000007F) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_8_Counter_Pointer_MAX (0x0000007F) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_8_Counter_Pointer_DEF (0x0000007F) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_8_Counter_Control_OFF ( 7) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_8_Counter_Control_WID ( 2) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_8_Counter_Control_MSK (0x00000180) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_8_Counter_Control_MAX (0x00000003) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_8_Counter_Control_DEF (0x00000000) + +#define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_0_REG (0x00004114) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_0_Counter_Status_OFF ( 0) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_0_Counter_Status_WID (23) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_0_Counter_Status_MSK (0x007FFFFF) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_0_Counter_Status_MAX (0x007FFFFF) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_0_Counter_Status_DEF (0x00000000) + +#define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_1_REG (0x00004118) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_1_Counter_Status_OFF ( 0) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_1_Counter_Status_WID (23) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_1_Counter_Status_MSK (0x007FFFFF) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_1_Counter_Status_MAX (0x007FFFFF) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_1_Counter_Status_DEF (0x00000000) + +#define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_2_REG (0x0000411C) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_2_Counter_Status_OFF ( 0) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_2_Counter_Status_WID (23) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_2_Counter_Status_MSK (0x007FFFFF) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_2_Counter_Status_MAX (0x007FFFFF) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_2_Counter_Status_DEF (0x00000000) + +#define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_3_REG (0x00004120) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_3_Counter_Status_OFF ( 0) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_3_Counter_Status_WID (23) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_3_Counter_Status_MSK (0x007FFFFF) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_3_Counter_Status_MAX (0x007FFFFF) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_3_Counter_Status_DEF (0x00000000) + +#define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_4_REG (0x00004124) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_4_Counter_Status_OFF ( 0) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_4_Counter_Status_WID (23) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_4_Counter_Status_MSK (0x007FFFFF) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_4_Counter_Status_MAX (0x007FFFFF) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_4_Counter_Status_DEF (0x00000000) + +#define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_5_REG (0x00004128) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_5_Counter_Status_OFF ( 0) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_5_Counter_Status_WID (23) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_5_Counter_Status_MSK (0x007FFFFF) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_5_Counter_Status_MAX (0x007FFFFF) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_5_Counter_Status_DEF (0x00000000) + +#define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_6_REG (0x0000412C) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_6_Counter_Status_OFF ( 0) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_6_Counter_Status_WID (23) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_6_Counter_Status_MSK (0x007FFFFF) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_6_Counter_Status_MAX (0x007FFFFF) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_6_Counter_Status_DEF (0x00000000) + +#define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_7_REG (0x00004130) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_7_Counter_Status_OFF ( 0) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_7_Counter_Status_WID (23) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_7_Counter_Status_MSK (0x007FFFFF) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_7_Counter_Status_MAX (0x007FFFFF) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_7_Counter_Status_DEF (0x00000000) + +#define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_8_REG (0x00004134) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_8_Counter_Status_OFF ( 0) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_8_Counter_Status_WID (23) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_8_Counter_Status_MSK (0x007FFFFF) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_8_Counter_Status_MAX (0x007FFFFF) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_8_Counter_Status_DEF (0x00000000) + +#define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_OVERFLOW_STATUS_REG (0x00004138) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_OVERFLOW_STATUS_Counter_Overflow_Status_OFF ( 0) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_OVERFLOW_STATUS_Counter_Overflow_Status_WID ( 9) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_OVERFLOW_STATUS_Counter_Overflow_Status_MSK (0x000001FF) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_OVERFLOW_STATUS_Counter_Overflow_Status_MAX (0x000001FF) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_OVERFLOW_STATUS_Counter_Overflow_Status_DEF (0x00000000) + +#define MCHBAR_CH0_CR_REUT_CH_ERROR_ADDR_REG (0x00004180) + #define MCHBAR_CH0_CR_REUT_CH_ERROR_ADDR_Column_Address_OFF ( 0) + #define MCHBAR_CH0_CR_REUT_CH_ERROR_ADDR_Column_Address_WID (10) + #define MCHBAR_CH0_CR_REUT_CH_ERROR_ADDR_Column_Address_MSK (0x000003FF) + #define MCHBAR_CH0_CR_REUT_CH_ERROR_ADDR_Column_Address_MAX (0x000003FF) + #define MCHBAR_CH0_CR_REUT_CH_ERROR_ADDR_Column_Address_DEF (0x00000000) + #define MCHBAR_CH0_CR_REUT_CH_ERROR_ADDR_Row_Address_OFF (24) + #define MCHBAR_CH0_CR_REUT_CH_ERROR_ADDR_Row_Address_WID (16) + #define MCHBAR_CH0_CR_REUT_CH_ERROR_ADDR_Row_Address_MSK (0xFFFF000000) + #define MCHBAR_CH0_CR_REUT_CH_ERROR_ADDR_Row_Address_MAX (0x0000FFFF) + #define MCHBAR_CH0_CR_REUT_CH_ERROR_ADDR_Row_Address_DEF (0x00000000) + #define MCHBAR_CH0_CR_REUT_CH_ERROR_ADDR_Bank_Address_OFF (48) + #define MCHBAR_CH0_CR_REUT_CH_ERROR_ADDR_Bank_Address_WID ( 3) + #define MCHBAR_CH0_CR_REUT_CH_ERROR_ADDR_Bank_Address_MSK (0x7000000000000) + #define MCHBAR_CH0_CR_REUT_CH_ERROR_ADDR_Bank_Address_MAX (0x00000007) + #define MCHBAR_CH0_CR_REUT_CH_ERROR_ADDR_Bank_Address_DEF (0x00000000) + #define MCHBAR_CH0_CR_REUT_CH_ERROR_ADDR_Rank_Address_OFF (56) + #define MCHBAR_CH0_CR_REUT_CH_ERROR_ADDR_Rank_Address_WID ( 2) + #define MCHBAR_CH0_CR_REUT_CH_ERROR_ADDR_Rank_Address_MSK (0x300000000000000) + #define MCHBAR_CH0_CR_REUT_CH_ERROR_ADDR_Rank_Address_MAX (0x00000003) + #define MCHBAR_CH0_CR_REUT_CH_ERROR_ADDR_Rank_Address_DEF (0x00000000) + +#define MCHBAR_CH0_CR_REUT_CH_ERR_WDB_CAPTURE_STATUS_REG (0x00004188) + #define MCHBAR_CH0_CR_REUT_CH_ERR_WDB_CAPTURE_STATUS_WDB_Current_Error_Pointer_OFF ( 0) + #define MCHBAR_CH0_CR_REUT_CH_ERR_WDB_CAPTURE_STATUS_WDB_Current_Error_Pointer_WID ( 6) + #define MCHBAR_CH0_CR_REUT_CH_ERR_WDB_CAPTURE_STATUS_WDB_Current_Error_Pointer_MSK (0x0000003F) + #define MCHBAR_CH0_CR_REUT_CH_ERR_WDB_CAPTURE_STATUS_WDB_Current_Error_Pointer_MAX (0x0000003F) + #define MCHBAR_CH0_CR_REUT_CH_ERR_WDB_CAPTURE_STATUS_WDB_Current_Error_Pointer_DEF (0x00000000) + +#define MCHBAR_CH0_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_REG (0x0000418C) + #define MCHBAR_CH0_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_Enable_WDB_Error_Capture_OFF ( 0) + #define MCHBAR_CH0_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_Enable_WDB_Error_Capture_WID ( 1) + #define MCHBAR_CH0_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_Enable_WDB_Error_Capture_MSK (0x00000001) + #define MCHBAR_CH0_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_Enable_WDB_Error_Capture_MAX (0x00000001) + #define MCHBAR_CH0_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_Enable_WDB_Error_Capture_DEF (0x00000000) + #define MCHBAR_CH0_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_WDB_Starting_Error_Pointer_OFF ( 8) + #define MCHBAR_CH0_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_WDB_Starting_Error_Pointer_WID ( 6) + #define MCHBAR_CH0_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_WDB_Starting_Error_Pointer_MSK (0x00003F00) + #define MCHBAR_CH0_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_WDB_Starting_Error_Pointer_MAX (0x0000003F) + #define MCHBAR_CH0_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_WDB_Starting_Error_Pointer_DEF (0x00000000) + #define MCHBAR_CH0_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_WDB_Ending_Error_Pointer_OFF (16) + #define MCHBAR_CH0_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_WDB_Ending_Error_Pointer_WID ( 6) + #define MCHBAR_CH0_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_WDB_Ending_Error_Pointer_MSK (0x003F0000) + #define MCHBAR_CH0_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_WDB_Ending_Error_Pointer_MAX (0x0000003F) + #define MCHBAR_CH0_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_WDB_Ending_Error_Pointer_DEF (0x00000000) + +#define MCHBAR_CH0_CR_REUT_CH_MISC_CKE_CTRL_REG (0x00004190) + #define MCHBAR_CH0_CR_REUT_CH_MISC_CKE_CTRL_CKE_Override_OFF ( 0) + #define MCHBAR_CH0_CR_REUT_CH_MISC_CKE_CTRL_CKE_Override_WID ( 4) + #define MCHBAR_CH0_CR_REUT_CH_MISC_CKE_CTRL_CKE_Override_MSK (0x0000000F) + #define MCHBAR_CH0_CR_REUT_CH_MISC_CKE_CTRL_CKE_Override_MAX (0x0000000F) + #define MCHBAR_CH0_CR_REUT_CH_MISC_CKE_CTRL_CKE_Override_DEF (0x0000000F) + #define MCHBAR_CH0_CR_REUT_CH_MISC_CKE_CTRL_CKE_En_Start_Test_Sync_OFF ( 8) + #define MCHBAR_CH0_CR_REUT_CH_MISC_CKE_CTRL_CKE_En_Start_Test_Sync_WID ( 1) + #define MCHBAR_CH0_CR_REUT_CH_MISC_CKE_CTRL_CKE_En_Start_Test_Sync_MSK (0x00000100) + #define MCHBAR_CH0_CR_REUT_CH_MISC_CKE_CTRL_CKE_En_Start_Test_Sync_MAX (0x00000001) + #define MCHBAR_CH0_CR_REUT_CH_MISC_CKE_CTRL_CKE_En_Start_Test_Sync_DEF (0x00000000) + #define MCHBAR_CH0_CR_REUT_CH_MISC_CKE_CTRL_CKE_On_OFF (16) + #define MCHBAR_CH0_CR_REUT_CH_MISC_CKE_CTRL_CKE_On_WID ( 4) + #define MCHBAR_CH0_CR_REUT_CH_MISC_CKE_CTRL_CKE_On_MSK (0x000F0000) + #define MCHBAR_CH0_CR_REUT_CH_MISC_CKE_CTRL_CKE_On_MAX (0x0000000F) + #define MCHBAR_CH0_CR_REUT_CH_MISC_CKE_CTRL_CKE_On_DEF (0x00000000) + +#define MCHBAR_CH0_CR_REUT_CH_MISC_ODT_CTRL_REG (0x00004194) + #define MCHBAR_CH0_CR_REUT_CH_MISC_ODT_CTRL_ODT_Override_OFF ( 0) + #define MCHBAR_CH0_CR_REUT_CH_MISC_ODT_CTRL_ODT_Override_WID ( 4) + #define MCHBAR_CH0_CR_REUT_CH_MISC_ODT_CTRL_ODT_Override_MSK (0x0000000F) + #define MCHBAR_CH0_CR_REUT_CH_MISC_ODT_CTRL_ODT_Override_MAX (0x0000000F) + #define MCHBAR_CH0_CR_REUT_CH_MISC_ODT_CTRL_ODT_Override_DEF (0x0000000F) + #define MCHBAR_CH0_CR_REUT_CH_MISC_ODT_CTRL_ODT_On_OFF (16) + #define MCHBAR_CH0_CR_REUT_CH_MISC_ODT_CTRL_ODT_On_WID ( 4) + #define MCHBAR_CH0_CR_REUT_CH_MISC_ODT_CTRL_ODT_On_MSK (0x000F0000) + #define MCHBAR_CH0_CR_REUT_CH_MISC_ODT_CTRL_ODT_On_MAX (0x0000000F) + #define MCHBAR_CH0_CR_REUT_CH_MISC_ODT_CTRL_ODT_On_DEF (0x00000000) + #define MCHBAR_CH0_CR_REUT_CH_MISC_ODT_CTRL_MPR_Train_DDR_On_OFF (31) + #define MCHBAR_CH0_CR_REUT_CH_MISC_ODT_CTRL_MPR_Train_DDR_On_WID ( 1) + #define MCHBAR_CH0_CR_REUT_CH_MISC_ODT_CTRL_MPR_Train_DDR_On_MSK (0x80000000) + #define MCHBAR_CH0_CR_REUT_CH_MISC_ODT_CTRL_MPR_Train_DDR_On_MAX (0x00000001) + #define MCHBAR_CH0_CR_REUT_CH_MISC_ODT_CTRL_MPR_Train_DDR_On_DEF (0x00000000) + +#define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_REG (0x00004198) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_Enable_CADB_on_Deselect_OFF ( 0) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_Enable_CADB_on_Deselect_WID ( 1) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_Enable_CADB_on_Deselect_MSK (0x00000001) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_Enable_CADB_on_Deselect_MAX (0x00000001) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_Enable_CADB_on_Deselect_DEF (0x00000000) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_Enable_CADB_Always_On_OFF ( 1) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_Enable_CADB_Always_On_WID ( 1) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_Enable_CADB_Always_On_MSK (0x00000002) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_Enable_CADB_Always_On_MAX (0x00000001) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_Enable_CADB_Always_On_DEF (0x00000000) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_CMD_Deselect_Start_OFF ( 2) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_CMD_Deselect_Start_WID ( 4) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_CMD_Deselect_Start_MSK (0x0000003C) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_CMD_Deselect_Start_MAX (0x0000000F) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_CMD_Deselect_Start_DEF (0x00000000) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_CMD_Deselect_Stop_OFF ( 6) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_CMD_Deselect_Stop_WID ( 4) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_CMD_Deselect_Stop_MSK (0x000003C0) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_CMD_Deselect_Stop_MAX (0x0000000F) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_CMD_Deselect_Stop_DEF (0x00000000) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_Lane_Deselect_Enable_OFF ( 10) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_Lane_Deselect_Enable_WID ( 4) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_Lane_Deselect_Enable_MSK (0x00003C00) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_Lane_Deselect_Enable_MAX (0x0000000F) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_Lane_Deselect_Enable_DEF (0x00000000) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_CAS_Select_Enable_OFF ( 14) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_CAS_Select_Enable_WID ( 2) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_CAS_Select_Enable_MSK (0x0000C000) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_CAS_Select_Enable_MAX (0x00000003) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_CAS_Select_Enable_DEF (0x00000000) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_ACT_Select_Enable_OFF ( 16) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_ACT_Select_Enable_WID ( 2) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_ACT_Select_Enable_MSK (0x00030000) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_ACT_Select_Enable_MAX (0x00000003) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_ACT_Select_Enable_DEF (0x00000000) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_PRE_Select_Enable_OFF ( 18) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_PRE_Select_Enable_WID ( 2) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_PRE_Select_Enable_MSK (0x000C0000) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_PRE_Select_Enable_MAX (0x00000003) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_PRE_Select_Enable_DEF (0x00000000) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_Save_Current_Seed_OFF ( 20) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_Save_Current_Seed_WID ( 4) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_Save_Current_Seed_MSK (0x00F00000) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_Save_Current_Seed_MAX (0x0000000F) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_Save_Current_Seed_DEF (0x00000000) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_Reload_Starting_Seed_OFF ( 24) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_Reload_Starting_Seed_WID ( 4) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_Reload_Starting_Seed_MSK (0x0F000000) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_Reload_Starting_Seed_MAX (0x0000000F) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_Reload_Starting_Seed_DEF (0x00000000) + +#define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MRS_REG (0x0000419C) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MRS_MRS_Gap_OFF ( 0) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MRS_MRS_Gap_WID ( 3) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MRS_MRS_Gap_MSK (0x00000007) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MRS_MRS_Gap_MAX (0x00000007) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MRS_MRS_Gap_DEF (0x00000002) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_Start_Pointer_OFF ( 8) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_Start_Pointer_WID ( 3) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_Start_Pointer_MSK (0x00000700) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_Start_Pointer_MAX (0x00000007) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_Start_Pointer_DEF (0x00000000) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_End_Pointer_OFF (16) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_End_Pointer_WID ( 3) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_End_Pointer_MSK (0x00070000) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_End_Pointer_MAX (0x00000007) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_End_Pointer_DEF (0x00000007) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_Current_Pointer_OFF (24) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_Current_Pointer_WID ( 3) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_Current_Pointer_MSK (0x07000000) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_Current_Pointer_MAX (0x00000007) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_Current_Pointer_DEF (0x00000000) + +#define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_CTRL_REG (0x000041A0) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux0_Control_OFF ( 0) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux0_Control_WID ( 2) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux0_Control_MSK (0x00000003) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux0_Control_MAX (0x00000003) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux0_Control_DEF (0x00000001) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux1_Control_OFF ( 4) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux1_Control_WID ( 2) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux1_Control_MSK (0x00000030) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux1_Control_MAX (0x00000003) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux1_Control_DEF (0x00000001) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux2_Control_OFF ( 8) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux2_Control_WID ( 2) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux2_Control_MSK (0x00000300) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux2_Control_MAX (0x00000003) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux2_Control_DEF (0x00000001) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux0_Control_OFF ( 16) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux0_Control_WID ( 2) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux0_Control_MSK (0x00030000) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux0_Control_MAX (0x00000003) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux0_Control_DEF (0x00000001) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux1_Control_OFF ( 20) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux1_Control_WID ( 2) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux1_Control_MSK (0x00300000) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux1_Control_MAX (0x00000003) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux1_Control_DEF (0x00000001) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux2_Control_OFF ( 24) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux2_Control_WID ( 2) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux2_Control_MSK (0x03000000) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux2_Control_MAX (0x00000003) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux2_Control_DEF (0x00000001) + +#define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_PB_0_REG (0x000041A4) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_PB_0_Pattern_Buffer_OFF ( 0) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_PB_0_Pattern_Buffer_WID (16) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_PB_0_Pattern_Buffer_MSK (0x0000FFFF) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_PB_0_Pattern_Buffer_MAX (0x0000FFFF) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_PB_0_Pattern_Buffer_DEF (0x00000000) + +#define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_PB_1_REG (0x000041A8) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_PB_1_Pattern_Buffer_OFF ( 0) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_PB_1_Pattern_Buffer_WID (16) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_PB_1_Pattern_Buffer_MSK (0x0000FFFF) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_PB_1_Pattern_Buffer_MAX (0x0000FFFF) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_PB_1_Pattern_Buffer_DEF (0x00000000) + +#define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_PB_2_REG (0x000041AC) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_PB_2_Pattern_Buffer_OFF ( 0) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_PB_2_Pattern_Buffer_WID (16) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_PB_2_Pattern_Buffer_MSK (0x0000FFFF) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_PB_2_Pattern_Buffer_MAX (0x0000FFFF) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_PB_2_Pattern_Buffer_DEF (0x00000000) + +#define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_REG (0x000041B0) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_L_data_select_OFF ( 0) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_L_data_select_WID ( 1) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_L_data_select_MSK (0x00000001) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_L_data_select_MAX (0x00000001) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_L_data_select_DEF (0x00000000) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_Enable_Sweep_Frequency_OFF ( 1) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_Enable_Sweep_Frequency_WID ( 1) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_Enable_Sweep_Frequency_MSK (0x00000002) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_Enable_Sweep_Frequency_MAX (0x00000001) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_Enable_Sweep_Frequency_DEF (0x00000000) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_L_counter_OFF ( 8) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_L_counter_WID ( 8) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_L_counter_MSK (0x0000FF00) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_L_counter_MAX (0x000000FF) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_L_counter_DEF (0x00000001) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_M_counter_OFF (16) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_M_counter_WID ( 8) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_M_counter_MSK (0x00FF0000) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_M_counter_MAX (0x000000FF) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_M_counter_DEF (0x00000001) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_N_counter_OFF (24) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_N_counter_WID ( 8) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_N_counter_MSK (0xFF000000) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_N_counter_MAX (0x000000FF) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_N_counter_DEF (0x00000001) + +#define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_WRITE_POINTER_REG (0x000041BC) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_WRITE_POINTER_CADB_Write_Pointer_OFF ( 0) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_WRITE_POINTER_CADB_Write_Pointer_WID ( 3) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_WRITE_POINTER_CADB_Write_Pointer_MSK (0x00000007) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_WRITE_POINTER_CADB_Write_Pointer_MAX (0x00000007) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_WRITE_POINTER_CADB_Write_Pointer_DEF (0x00000000) + +#define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_0_REG (0x000041C8) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_0_Pattern_Buffer_OFF ( 0) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_0_Pattern_Buffer_WID (16) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_0_Pattern_Buffer_MSK (0x0000FFFF) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_0_Pattern_Buffer_MAX (0x0000FFFF) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_0_Pattern_Buffer_DEF (0x00000000) + +#define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_1_REG (0x000041CC) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_1_Pattern_Buffer_OFF ( 0) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_1_Pattern_Buffer_WID (16) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_1_Pattern_Buffer_MSK (0x0000FFFF) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_1_Pattern_Buffer_MAX (0x0000FFFF) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_1_Pattern_Buffer_DEF (0x00000000) + +#define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_2_REG (0x000041D0) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_2_Pattern_Buffer_OFF ( 0) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_2_Pattern_Buffer_WID (16) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_2_Pattern_Buffer_MSK (0x0000FFFF) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_2_Pattern_Buffer_MAX (0x0000FFFF) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_2_Pattern_Buffer_DEF (0x00000000) + +#define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_PROG_REG (0x000041C0) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Address_OFF ( 0) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Address_WID (16) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Address_MSK (0x0000FFFF) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Address_MAX (0x0000FFFF) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Address_DEF (0x00000000) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Bank_OFF (24) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Bank_WID ( 3) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Bank_MSK (0x07000000) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Bank_MAX (0x00000007) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Bank_DEF (0x00000000) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_CS_OFF (32) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_CS_WID ( 4) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_CS_MSK (0xF00000000) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_CS_MAX (0x0000000F) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_CS_DEF (0x00000000) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Control_OFF (40) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Control_WID ( 3) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Control_MSK (0x70000000000) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Control_MAX (0x00000007) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Control_DEF (0x00000000) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_ODT_OFF (48) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_ODT_WID ( 4) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_ODT_MSK (0xF000000000000) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_ODT_MAX (0x0000000F) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_ODT_DEF (0x00000000) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_CKE_OFF (56) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_CKE_WID ( 4) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_CKE_MSK (0xF00000000000000) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_CKE_MAX (0x0000000F) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_CKE_DEF (0x00000000) + +#define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_CTRL_REG (0x00004200) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Increment_Rate_OFF ( 0) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Increment_Rate_WID ( 5) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Increment_Rate_MSK (0x0000001F) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Increment_Rate_MAX (0x0000001F) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Increment_Rate_DEF (0x00000000) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Increment_Scale_OFF ( 5) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Increment_Scale_WID ( 1) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Increment_Scale_MSK (0x00000020) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Increment_Scale_MAX (0x00000001) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Increment_Scale_DEF (0x00000000) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Start_Pointer_OFF ( 8) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Start_Pointer_WID ( 6) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Start_Pointer_MSK (0x00003F00) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Start_Pointer_MAX (0x0000003F) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Start_Pointer_DEF (0x00000000) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_End_Pointer_OFF (16) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_End_Pointer_WID ( 6) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_End_Pointer_MSK (0x003F0000) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_End_Pointer_MAX (0x0000003F) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_End_Pointer_DEF (0x0000003F) + +#define MCHBAR_CH0_CR_REUT_CH_MISC_REFRESH_CTRL_REG (0x00004204) + #define MCHBAR_CH0_CR_REUT_CH_MISC_REFRESH_CTRL_Refresh_Rank_Mask_OFF ( 0) + #define MCHBAR_CH0_CR_REUT_CH_MISC_REFRESH_CTRL_Refresh_Rank_Mask_WID ( 4) + #define MCHBAR_CH0_CR_REUT_CH_MISC_REFRESH_CTRL_Refresh_Rank_Mask_MSK (0x0000000F) + #define MCHBAR_CH0_CR_REUT_CH_MISC_REFRESH_CTRL_Refresh_Rank_Mask_MAX (0x0000000F) + #define MCHBAR_CH0_CR_REUT_CH_MISC_REFRESH_CTRL_Refresh_Rank_Mask_DEF (0x00000000) + #define MCHBAR_CH0_CR_REUT_CH_MISC_REFRESH_CTRL_RefZQ_En_Start_Test_Sync_OFF ( 8) + #define MCHBAR_CH0_CR_REUT_CH_MISC_REFRESH_CTRL_RefZQ_En_Start_Test_Sync_WID ( 1) + #define MCHBAR_CH0_CR_REUT_CH_MISC_REFRESH_CTRL_RefZQ_En_Start_Test_Sync_MSK (0x00000100) + #define MCHBAR_CH0_CR_REUT_CH_MISC_REFRESH_CTRL_RefZQ_En_Start_Test_Sync_MAX (0x00000001) + #define MCHBAR_CH0_CR_REUT_CH_MISC_REFRESH_CTRL_RefZQ_En_Start_Test_Sync_DEF (0x00000000) + #define MCHBAR_CH0_CR_REUT_CH_MISC_REFRESH_CTRL_Panic_Refresh_Only_OFF (31) + #define MCHBAR_CH0_CR_REUT_CH_MISC_REFRESH_CTRL_Panic_Refresh_Only_WID ( 1) + #define MCHBAR_CH0_CR_REUT_CH_MISC_REFRESH_CTRL_Panic_Refresh_Only_MSK (0x80000000) + #define MCHBAR_CH0_CR_REUT_CH_MISC_REFRESH_CTRL_Panic_Refresh_Only_MAX (0x00000001) + #define MCHBAR_CH0_CR_REUT_CH_MISC_REFRESH_CTRL_Panic_Refresh_Only_DEF (0x00000000) + +#define MCHBAR_CH0_CR_REUT_CH_MISC_ZQ_CTRL_REG (0x00004208) + #define MCHBAR_CH0_CR_REUT_CH_MISC_ZQ_CTRL_ZQ_Rank_Mask_OFF ( 0) + #define MCHBAR_CH0_CR_REUT_CH_MISC_ZQ_CTRL_ZQ_Rank_Mask_WID ( 4) + #define MCHBAR_CH0_CR_REUT_CH_MISC_ZQ_CTRL_ZQ_Rank_Mask_MSK (0x0000000F) + #define MCHBAR_CH0_CR_REUT_CH_MISC_ZQ_CTRL_ZQ_Rank_Mask_MAX (0x0000000F) + #define MCHBAR_CH0_CR_REUT_CH_MISC_ZQ_CTRL_ZQ_Rank_Mask_DEF (0x00000000) + #define MCHBAR_CH0_CR_REUT_CH_MISC_ZQ_CTRL_Always_Do_ZQ_OFF (31) + #define MCHBAR_CH0_CR_REUT_CH_MISC_ZQ_CTRL_Always_Do_ZQ_WID ( 1) + #define MCHBAR_CH0_CR_REUT_CH_MISC_ZQ_CTRL_Always_Do_ZQ_MSK (0x80000000) + #define MCHBAR_CH0_CR_REUT_CH_MISC_ZQ_CTRL_Always_Do_ZQ_MAX (0x00000001) + #define MCHBAR_CH0_CR_REUT_CH_MISC_ZQ_CTRL_Always_Do_ZQ_DEF (0x00000000) + +#define MCHBAR_CH0_CR_LPDDR_MR_PARAMS_REG (0x00004210) + #define MCHBAR_CH0_CR_LPDDR_MR_PARAMS_Rank_0_x32_OFF ( 0) + #define MCHBAR_CH0_CR_LPDDR_MR_PARAMS_Rank_0_x32_WID ( 1) + #define MCHBAR_CH0_CR_LPDDR_MR_PARAMS_Rank_0_x32_MSK (0x00000001) + #define MCHBAR_CH0_CR_LPDDR_MR_PARAMS_Rank_0_x32_MAX (0x00000001) + #define MCHBAR_CH0_CR_LPDDR_MR_PARAMS_Rank_0_x32_DEF (0x00000000) + #define MCHBAR_CH0_CR_LPDDR_MR_PARAMS_Rank_1_x32_OFF ( 1) + #define MCHBAR_CH0_CR_LPDDR_MR_PARAMS_Rank_1_x32_WID ( 1) + #define MCHBAR_CH0_CR_LPDDR_MR_PARAMS_Rank_1_x32_MSK (0x00000002) + #define MCHBAR_CH0_CR_LPDDR_MR_PARAMS_Rank_1_x32_MAX (0x00000001) + #define MCHBAR_CH0_CR_LPDDR_MR_PARAMS_Rank_1_x32_DEF (0x00000000) + #define MCHBAR_CH0_CR_LPDDR_MR_PARAMS_Rank_2_x32_OFF ( 2) + #define MCHBAR_CH0_CR_LPDDR_MR_PARAMS_Rank_2_x32_WID ( 1) + #define MCHBAR_CH0_CR_LPDDR_MR_PARAMS_Rank_2_x32_MSK (0x00000004) + #define MCHBAR_CH0_CR_LPDDR_MR_PARAMS_Rank_2_x32_MAX (0x00000001) + #define MCHBAR_CH0_CR_LPDDR_MR_PARAMS_Rank_2_x32_DEF (0x00000000) + #define MCHBAR_CH0_CR_LPDDR_MR_PARAMS_Rank_3_x32_OFF ( 3) + #define MCHBAR_CH0_CR_LPDDR_MR_PARAMS_Rank_3_x32_WID ( 1) + #define MCHBAR_CH0_CR_LPDDR_MR_PARAMS_Rank_3_x32_MSK (0x00000008) + #define MCHBAR_CH0_CR_LPDDR_MR_PARAMS_Rank_3_x32_MAX (0x00000001) + #define MCHBAR_CH0_CR_LPDDR_MR_PARAMS_Rank_3_x32_DEF (0x00000000) + #define MCHBAR_CH0_CR_LPDDR_MR_PARAMS_LPDDR2_OFF ( 4) + #define MCHBAR_CH0_CR_LPDDR_MR_PARAMS_LPDDR2_WID ( 1) + #define MCHBAR_CH0_CR_LPDDR_MR_PARAMS_LPDDR2_MSK (0x00000010) + #define MCHBAR_CH0_CR_LPDDR_MR_PARAMS_LPDDR2_MAX (0x00000001) + #define MCHBAR_CH0_CR_LPDDR_MR_PARAMS_LPDDR2_DEF (0x00000000) + #define MCHBAR_CH0_CR_LPDDR_MR_PARAMS_MR4_PERIOD_OFF ( 8) + #define MCHBAR_CH0_CR_LPDDR_MR_PARAMS_MR4_PERIOD_WID (16) + #define MCHBAR_CH0_CR_LPDDR_MR_PARAMS_MR4_PERIOD_MSK (0x00FFFF00) + #define MCHBAR_CH0_CR_LPDDR_MR_PARAMS_MR4_PERIOD_MAX (0x0000FFFF) + #define MCHBAR_CH0_CR_LPDDR_MR_PARAMS_MR4_PERIOD_DEF (0x00000000) + +#define MCHBAR_CH0_CR_LPDDR_MR_COMMAND_REG (0x00004214) + #define MCHBAR_CH0_CR_LPDDR_MR_COMMAND_Address_OFF ( 0) + #define MCHBAR_CH0_CR_LPDDR_MR_COMMAND_Address_WID ( 8) + #define MCHBAR_CH0_CR_LPDDR_MR_COMMAND_Address_MSK (0x000000FF) + #define MCHBAR_CH0_CR_LPDDR_MR_COMMAND_Address_MAX (0x000000FF) + #define MCHBAR_CH0_CR_LPDDR_MR_COMMAND_Address_DEF (0x00000000) + #define MCHBAR_CH0_CR_LPDDR_MR_COMMAND_Data_OFF ( 8) + #define MCHBAR_CH0_CR_LPDDR_MR_COMMAND_Data_WID ( 8) + #define MCHBAR_CH0_CR_LPDDR_MR_COMMAND_Data_MSK (0x0000FF00) + #define MCHBAR_CH0_CR_LPDDR_MR_COMMAND_Data_MAX (0x000000FF) + #define MCHBAR_CH0_CR_LPDDR_MR_COMMAND_Data_DEF (0x00000000) + #define MCHBAR_CH0_CR_LPDDR_MR_COMMAND_Rank_OFF (16) + #define MCHBAR_CH0_CR_LPDDR_MR_COMMAND_Rank_WID ( 2) + #define MCHBAR_CH0_CR_LPDDR_MR_COMMAND_Rank_MSK (0x00030000) + #define MCHBAR_CH0_CR_LPDDR_MR_COMMAND_Rank_MAX (0x00000003) + #define MCHBAR_CH0_CR_LPDDR_MR_COMMAND_Rank_DEF (0x00000000) + #define MCHBAR_CH0_CR_LPDDR_MR_COMMAND_Write_OFF (18) + #define MCHBAR_CH0_CR_LPDDR_MR_COMMAND_Write_WID ( 1) + #define MCHBAR_CH0_CR_LPDDR_MR_COMMAND_Write_MSK (0x00040000) + #define MCHBAR_CH0_CR_LPDDR_MR_COMMAND_Write_MAX (0x00000001) + #define MCHBAR_CH0_CR_LPDDR_MR_COMMAND_Write_DEF (0x00000000) + #define MCHBAR_CH0_CR_LPDDR_MR_COMMAND_Init_MRW_OFF (19) + #define MCHBAR_CH0_CR_LPDDR_MR_COMMAND_Init_MRW_WID ( 1) + #define MCHBAR_CH0_CR_LPDDR_MR_COMMAND_Init_MRW_MSK (0x00080000) + #define MCHBAR_CH0_CR_LPDDR_MR_COMMAND_Init_MRW_MAX (0x00000001) + #define MCHBAR_CH0_CR_LPDDR_MR_COMMAND_Init_MRW_DEF (0x00000000) + #define MCHBAR_CH0_CR_LPDDR_MR_COMMAND_Busy_OFF (31) + #define MCHBAR_CH0_CR_LPDDR_MR_COMMAND_Busy_WID ( 1) + #define MCHBAR_CH0_CR_LPDDR_MR_COMMAND_Busy_MSK (0x80000000) + #define MCHBAR_CH0_CR_LPDDR_MR_COMMAND_Busy_MAX (0x00000001) + #define MCHBAR_CH0_CR_LPDDR_MR_COMMAND_Busy_DEF (0x00000000) + +#define MCHBAR_CH0_CR_LPDDR_MR_RESULT_REG (0x00004218) + #define MCHBAR_CH0_CR_LPDDR_MR_RESULT_Device_0_OFF ( 0) + #define MCHBAR_CH0_CR_LPDDR_MR_RESULT_Device_0_WID ( 8) + #define MCHBAR_CH0_CR_LPDDR_MR_RESULT_Device_0_MSK (0x000000FF) + #define MCHBAR_CH0_CR_LPDDR_MR_RESULT_Device_0_MAX (0x000000FF) + #define MCHBAR_CH0_CR_LPDDR_MR_RESULT_Device_0_DEF (0x00000000) + #define MCHBAR_CH0_CR_LPDDR_MR_RESULT_Device_1_OFF ( 8) + #define MCHBAR_CH0_CR_LPDDR_MR_RESULT_Device_1_WID ( 8) + #define MCHBAR_CH0_CR_LPDDR_MR_RESULT_Device_1_MSK (0x0000FF00) + #define MCHBAR_CH0_CR_LPDDR_MR_RESULT_Device_1_MAX (0x000000FF) + #define MCHBAR_CH0_CR_LPDDR_MR_RESULT_Device_1_DEF (0x00000000) + #define MCHBAR_CH0_CR_LPDDR_MR_RESULT_Device_2_OFF (16) + #define MCHBAR_CH0_CR_LPDDR_MR_RESULT_Device_2_WID ( 8) + #define MCHBAR_CH0_CR_LPDDR_MR_RESULT_Device_2_MSK (0x00FF0000) + #define MCHBAR_CH0_CR_LPDDR_MR_RESULT_Device_2_MAX (0x000000FF) + #define MCHBAR_CH0_CR_LPDDR_MR_RESULT_Device_2_DEF (0x00000000) + #define MCHBAR_CH0_CR_LPDDR_MR_RESULT_Device_3_OFF (24) + #define MCHBAR_CH0_CR_LPDDR_MR_RESULT_Device_3_WID ( 8) + #define MCHBAR_CH0_CR_LPDDR_MR_RESULT_Device_3_MSK (0xFF000000) + #define MCHBAR_CH0_CR_LPDDR_MR_RESULT_Device_3_MAX (0x000000FF) + #define MCHBAR_CH0_CR_LPDDR_MR_RESULT_Device_3_DEF (0x00000000) + +#define MCHBAR_CH0_CR_LPDDR_MR4_RANK_TEMPERATURE_REG (0x0000421C) + #define MCHBAR_CH0_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_0_OFF ( 0) + #define MCHBAR_CH0_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_0_WID ( 3) + #define MCHBAR_CH0_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_0_MSK (0x00000007) + #define MCHBAR_CH0_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_0_MAX (0x00000007) + #define MCHBAR_CH0_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_0_DEF (0x00000003) + #define MCHBAR_CH0_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_1_OFF ( 8) + #define MCHBAR_CH0_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_1_WID ( 3) + #define MCHBAR_CH0_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_1_MSK (0x00000700) + #define MCHBAR_CH0_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_1_MAX (0x00000007) + #define MCHBAR_CH0_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_1_DEF (0x00000003) + #define MCHBAR_CH0_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_2_OFF (16) + #define MCHBAR_CH0_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_2_WID ( 3) + #define MCHBAR_CH0_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_2_MSK (0x00070000) + #define MCHBAR_CH0_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_2_MAX (0x00000007) + #define MCHBAR_CH0_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_2_DEF (0x00000003) + #define MCHBAR_CH0_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_3_OFF (24) + #define MCHBAR_CH0_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_3_WID ( 3) + #define MCHBAR_CH0_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_3_MSK (0x07000000) + #define MCHBAR_CH0_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_3_MAX (0x00000007) + #define MCHBAR_CH0_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_3_DEF (0x00000003) + +#define MCHBAR_CH0_CR_DESWIZZLE_LOW_REG (0x00004220) + #define MCHBAR_CH0_CR_DESWIZZLE_LOW_Bit_0_OFF ( 0) + #define MCHBAR_CH0_CR_DESWIZZLE_LOW_Bit_0_WID ( 3) + #define MCHBAR_CH0_CR_DESWIZZLE_LOW_Bit_0_MSK (0x00000007) + #define MCHBAR_CH0_CR_DESWIZZLE_LOW_Bit_0_MAX (0x00000007) + #define MCHBAR_CH0_CR_DESWIZZLE_LOW_Bit_0_DEF (0x00000000) + #define MCHBAR_CH0_CR_DESWIZZLE_LOW_Bit_1_OFF ( 4) + #define MCHBAR_CH0_CR_DESWIZZLE_LOW_Bit_1_WID ( 3) + #define MCHBAR_CH0_CR_DESWIZZLE_LOW_Bit_1_MSK (0x00000070) + #define MCHBAR_CH0_CR_DESWIZZLE_LOW_Bit_1_MAX (0x00000007) + #define MCHBAR_CH0_CR_DESWIZZLE_LOW_Bit_1_DEF (0x00000001) + #define MCHBAR_CH0_CR_DESWIZZLE_LOW_Bit_2_OFF ( 8) + #define MCHBAR_CH0_CR_DESWIZZLE_LOW_Bit_2_WID ( 3) + #define MCHBAR_CH0_CR_DESWIZZLE_LOW_Bit_2_MSK (0x00000700) + #define MCHBAR_CH0_CR_DESWIZZLE_LOW_Bit_2_MAX (0x00000007) + #define MCHBAR_CH0_CR_DESWIZZLE_LOW_Bit_2_DEF (0x00000002) + #define MCHBAR_CH0_CR_DESWIZZLE_LOW_Bit_16_OFF (12) + #define MCHBAR_CH0_CR_DESWIZZLE_LOW_Bit_16_WID ( 3) + #define MCHBAR_CH0_CR_DESWIZZLE_LOW_Bit_16_MSK (0x00007000) + #define MCHBAR_CH0_CR_DESWIZZLE_LOW_Bit_16_MAX (0x00000007) + #define MCHBAR_CH0_CR_DESWIZZLE_LOW_Bit_16_DEF (0x00000000) + #define MCHBAR_CH0_CR_DESWIZZLE_LOW_Bit_17_OFF (16) + #define MCHBAR_CH0_CR_DESWIZZLE_LOW_Bit_17_WID ( 3) + #define MCHBAR_CH0_CR_DESWIZZLE_LOW_Bit_17_MSK (0x00070000) + #define MCHBAR_CH0_CR_DESWIZZLE_LOW_Bit_17_MAX (0x00000007) + #define MCHBAR_CH0_CR_DESWIZZLE_LOW_Bit_17_DEF (0x00000001) + #define MCHBAR_CH0_CR_DESWIZZLE_LOW_Bit_18_OFF (20) + #define MCHBAR_CH0_CR_DESWIZZLE_LOW_Bit_18_WID ( 3) + #define MCHBAR_CH0_CR_DESWIZZLE_LOW_Bit_18_MSK (0x00700000) + #define MCHBAR_CH0_CR_DESWIZZLE_LOW_Bit_18_MAX (0x00000007) + #define MCHBAR_CH0_CR_DESWIZZLE_LOW_Bit_18_DEF (0x00000002) + #define MCHBAR_CH0_CR_DESWIZZLE_LOW_Byte_0_OFF (24) + #define MCHBAR_CH0_CR_DESWIZZLE_LOW_Byte_0_WID ( 3) + #define MCHBAR_CH0_CR_DESWIZZLE_LOW_Byte_0_MSK (0x07000000) + #define MCHBAR_CH0_CR_DESWIZZLE_LOW_Byte_0_MAX (0x00000007) + #define MCHBAR_CH0_CR_DESWIZZLE_LOW_Byte_0_DEF (0x00000000) + #define MCHBAR_CH0_CR_DESWIZZLE_LOW_Byte_2_OFF (28) + #define MCHBAR_CH0_CR_DESWIZZLE_LOW_Byte_2_WID ( 3) + #define MCHBAR_CH0_CR_DESWIZZLE_LOW_Byte_2_MSK (0x70000000) + #define MCHBAR_CH0_CR_DESWIZZLE_LOW_Byte_2_MAX (0x00000007) + #define MCHBAR_CH0_CR_DESWIZZLE_LOW_Byte_2_DEF (0x00000002) + +#define MCHBAR_CH0_CR_DESWIZZLE_HIGH_REG (0x00004224) + #define MCHBAR_CH0_CR_DESWIZZLE_HIGH_Bit_32_OFF ( 0) + #define MCHBAR_CH0_CR_DESWIZZLE_HIGH_Bit_32_WID ( 3) + #define MCHBAR_CH0_CR_DESWIZZLE_HIGH_Bit_32_MSK (0x00000007) + #define MCHBAR_CH0_CR_DESWIZZLE_HIGH_Bit_32_MAX (0x00000007) + #define MCHBAR_CH0_CR_DESWIZZLE_HIGH_Bit_32_DEF (0x00000000) + #define MCHBAR_CH0_CR_DESWIZZLE_HIGH_Bit_33_OFF ( 4) + #define MCHBAR_CH0_CR_DESWIZZLE_HIGH_Bit_33_WID ( 3) + #define MCHBAR_CH0_CR_DESWIZZLE_HIGH_Bit_33_MSK (0x00000070) + #define MCHBAR_CH0_CR_DESWIZZLE_HIGH_Bit_33_MAX (0x00000007) + #define MCHBAR_CH0_CR_DESWIZZLE_HIGH_Bit_33_DEF (0x00000001) + #define MCHBAR_CH0_CR_DESWIZZLE_HIGH_Bit_34_OFF ( 8) + #define MCHBAR_CH0_CR_DESWIZZLE_HIGH_Bit_34_WID ( 3) + #define MCHBAR_CH0_CR_DESWIZZLE_HIGH_Bit_34_MSK (0x00000700) + #define MCHBAR_CH0_CR_DESWIZZLE_HIGH_Bit_34_MAX (0x00000007) + #define MCHBAR_CH0_CR_DESWIZZLE_HIGH_Bit_34_DEF (0x00000002) + #define MCHBAR_CH0_CR_DESWIZZLE_HIGH_Bit_48_OFF (12) + #define MCHBAR_CH0_CR_DESWIZZLE_HIGH_Bit_48_WID ( 3) + #define MCHBAR_CH0_CR_DESWIZZLE_HIGH_Bit_48_MSK (0x00007000) + #define MCHBAR_CH0_CR_DESWIZZLE_HIGH_Bit_48_MAX (0x00000007) + #define MCHBAR_CH0_CR_DESWIZZLE_HIGH_Bit_48_DEF (0x00000000) + #define MCHBAR_CH0_CR_DESWIZZLE_HIGH_Bit_49_OFF (16) + #define MCHBAR_CH0_CR_DESWIZZLE_HIGH_Bit_49_WID ( 3) + #define MCHBAR_CH0_CR_DESWIZZLE_HIGH_Bit_49_MSK (0x00070000) + #define MCHBAR_CH0_CR_DESWIZZLE_HIGH_Bit_49_MAX (0x00000007) + #define MCHBAR_CH0_CR_DESWIZZLE_HIGH_Bit_49_DEF (0x00000001) + #define MCHBAR_CH0_CR_DESWIZZLE_HIGH_Bit_50_OFF (20) + #define MCHBAR_CH0_CR_DESWIZZLE_HIGH_Bit_50_WID ( 3) + #define MCHBAR_CH0_CR_DESWIZZLE_HIGH_Bit_50_MSK (0x00700000) + #define MCHBAR_CH0_CR_DESWIZZLE_HIGH_Bit_50_MAX (0x00000007) + #define MCHBAR_CH0_CR_DESWIZZLE_HIGH_Bit_50_DEF (0x00000002) + #define MCHBAR_CH0_CR_DESWIZZLE_HIGH_Byte_4_OFF (24) + #define MCHBAR_CH0_CR_DESWIZZLE_HIGH_Byte_4_WID ( 3) + #define MCHBAR_CH0_CR_DESWIZZLE_HIGH_Byte_4_MSK (0x07000000) + #define MCHBAR_CH0_CR_DESWIZZLE_HIGH_Byte_4_MAX (0x00000007) + #define MCHBAR_CH0_CR_DESWIZZLE_HIGH_Byte_4_DEF (0x00000004) + #define MCHBAR_CH0_CR_DESWIZZLE_HIGH_Byte_6_OFF (28) + #define MCHBAR_CH0_CR_DESWIZZLE_HIGH_Byte_6_WID ( 3) + #define MCHBAR_CH0_CR_DESWIZZLE_HIGH_Byte_6_MSK (0x70000000) + #define MCHBAR_CH0_CR_DESWIZZLE_HIGH_Byte_6_MAX (0x00000007) + #define MCHBAR_CH0_CR_DESWIZZLE_HIGH_Byte_6_DEF (0x00000006) + +#define MCHBAR_CH0_CR_MC_REFRESH_STAGGER_REG (0x0000428C) + #define MCHBAR_CH0_CR_MC_REFRESH_STAGGER_Ref_Interval_OFF ( 0) + #define MCHBAR_CH0_CR_MC_REFRESH_STAGGER_Ref_Interval_WID (11) + #define MCHBAR_CH0_CR_MC_REFRESH_STAGGER_Ref_Interval_MSK (0x000007FF) + #define MCHBAR_CH0_CR_MC_REFRESH_STAGGER_Ref_Interval_MAX (0x000007FF) + #define MCHBAR_CH0_CR_MC_REFRESH_STAGGER_Ref_Interval_DEF (0x00000000) + #define MCHBAR_CH0_CR_MC_REFRESH_STAGGER_Ref_Stagger_En_OFF (11) + #define MCHBAR_CH0_CR_MC_REFRESH_STAGGER_Ref_Stagger_En_WID ( 1) + #define MCHBAR_CH0_CR_MC_REFRESH_STAGGER_Ref_Stagger_En_MSK (0x00000800) + #define MCHBAR_CH0_CR_MC_REFRESH_STAGGER_Ref_Stagger_En_MAX (0x00000001) + #define MCHBAR_CH0_CR_MC_REFRESH_STAGGER_Ref_Stagger_En_DEF (0x00000000) + #define MCHBAR_CH0_CR_MC_REFRESH_STAGGER_Ref_Stagger_Mode_OFF (12) + #define MCHBAR_CH0_CR_MC_REFRESH_STAGGER_Ref_Stagger_Mode_WID ( 1) + #define MCHBAR_CH0_CR_MC_REFRESH_STAGGER_Ref_Stagger_Mode_MSK (0x00001000) + #define MCHBAR_CH0_CR_MC_REFRESH_STAGGER_Ref_Stagger_Mode_MAX (0x00000001) + #define MCHBAR_CH0_CR_MC_REFRESH_STAGGER_Ref_Stagger_Mode_DEF (0x00000000) + #define MCHBAR_CH0_CR_MC_REFRESH_STAGGER_Disable_Stolen_Refresh_OFF (13) + #define MCHBAR_CH0_CR_MC_REFRESH_STAGGER_Disable_Stolen_Refresh_WID ( 1) + #define MCHBAR_CH0_CR_MC_REFRESH_STAGGER_Disable_Stolen_Refresh_MSK (0x00002000) + #define MCHBAR_CH0_CR_MC_REFRESH_STAGGER_Disable_Stolen_Refresh_MAX (0x00000001) + #define MCHBAR_CH0_CR_MC_REFRESH_STAGGER_Disable_Stolen_Refresh_DEF (0x00000000) + #define MCHBAR_CH0_CR_MC_REFRESH_STAGGER_En_Ref_Type_Display_OFF (14) + #define MCHBAR_CH0_CR_MC_REFRESH_STAGGER_En_Ref_Type_Display_WID ( 1) + #define MCHBAR_CH0_CR_MC_REFRESH_STAGGER_En_Ref_Type_Display_MSK (0x00004000) + #define MCHBAR_CH0_CR_MC_REFRESH_STAGGER_En_Ref_Type_Display_MAX (0x00000001) + #define MCHBAR_CH0_CR_MC_REFRESH_STAGGER_En_Ref_Type_Display_DEF (0x00000000) + +#define MCHBAR_CH0_CR_TC_ZQCAL_REG (0x00004290) + #define MCHBAR_CH0_CR_TC_ZQCAL_ZQCS_period_OFF ( 0) + #define MCHBAR_CH0_CR_TC_ZQCAL_ZQCS_period_WID ( 8) + #define MCHBAR_CH0_CR_TC_ZQCAL_ZQCS_period_MSK (0x000000FF) + #define MCHBAR_CH0_CR_TC_ZQCAL_ZQCS_period_MAX (0x000000FF) + #define MCHBAR_CH0_CR_TC_ZQCAL_ZQCS_period_DEF (0x00000080) + #define MCHBAR_CH0_CR_TC_ZQCAL_tZQCS_OFF ( 8) + #define MCHBAR_CH0_CR_TC_ZQCAL_tZQCS_WID ( 8) + #define MCHBAR_CH0_CR_TC_ZQCAL_tZQCS_MSK (0x0000FF00) + #define MCHBAR_CH0_CR_TC_ZQCAL_tZQCS_MAX (0x000000FF) + #define MCHBAR_CH0_CR_TC_ZQCAL_tZQCS_DEF (0x00000040) + #define MCHBAR_CH0_CR_TC_ZQCAL_ZQCS_period_Ult_OFF ( 0) + #define MCHBAR_CH0_CR_TC_ZQCAL_ZQCS_period_Ult_WID (10) + #define MCHBAR_CH0_CR_TC_ZQCAL_ZQCS_period_Ult_MSK (0x000003FF) + #define MCHBAR_CH0_CR_TC_ZQCAL_ZQCS_period_Ult_MAX (0x000003FF) + #define MCHBAR_CH0_CR_TC_ZQCAL_ZQCS_period_Ult_DEF (0x00000080) + #define MCHBAR_CH0_CR_TC_ZQCAL_tZQCS_Ult_OFF (10) + #define MCHBAR_CH0_CR_TC_ZQCAL_tZQCS_Ult_WID (10) + #define MCHBAR_CH0_CR_TC_ZQCAL_tZQCS_Ult_MSK (0x000FFC00) + #define MCHBAR_CH0_CR_TC_ZQCAL_tZQCS_Ult_MAX (0x000003FF) + #define MCHBAR_CH0_CR_TC_ZQCAL_tZQCS_Ult_DEF (0x00000040) + +#define MCHBAR_CH0_CR_TC_RFP_REG (0x00004294) + #define MCHBAR_CH0_CR_TC_RFP_OREF_RI_OFF ( 0) + #define MCHBAR_CH0_CR_TC_RFP_OREF_RI_WID ( 8) + #define MCHBAR_CH0_CR_TC_RFP_OREF_RI_MSK (0x000000FF) + #define MCHBAR_CH0_CR_TC_RFP_OREF_RI_MAX (0x000000FF) + #define MCHBAR_CH0_CR_TC_RFP_OREF_RI_DEF (0x0000000F) + #define MCHBAR_CH0_CR_TC_RFP_Refresh_HP_WM_OFF ( 8) + #define MCHBAR_CH0_CR_TC_RFP_Refresh_HP_WM_WID ( 4) + #define MCHBAR_CH0_CR_TC_RFP_Refresh_HP_WM_MSK (0x00000F00) + #define MCHBAR_CH0_CR_TC_RFP_Refresh_HP_WM_MAX (0x0000000F) + #define MCHBAR_CH0_CR_TC_RFP_Refresh_HP_WM_DEF (0x00000008) + #define MCHBAR_CH0_CR_TC_RFP_Refresh_panic_wm_OFF (12) + #define MCHBAR_CH0_CR_TC_RFP_Refresh_panic_wm_WID ( 4) + #define MCHBAR_CH0_CR_TC_RFP_Refresh_panic_wm_MSK (0x0000F000) + #define MCHBAR_CH0_CR_TC_RFP_Refresh_panic_wm_MAX (0x0000000F) + #define MCHBAR_CH0_CR_TC_RFP_Refresh_panic_wm_DEF (0x00000009) + +#define MCHBAR_CH0_CR_TC_RFTP_REG (0x00004298) + #define MCHBAR_CH0_CR_TC_RFTP_tREFI_OFF ( 0) + #define MCHBAR_CH0_CR_TC_RFTP_tREFI_WID (16) + #define MCHBAR_CH0_CR_TC_RFTP_tREFI_MSK (0x0000FFFF) + #define MCHBAR_CH0_CR_TC_RFTP_tREFI_MAX (0x0000FFFF) + #define MCHBAR_CH0_CR_TC_RFTP_tREFI_DEF (0x00001004) + #define MCHBAR_CH0_CR_TC_RFTP_tRFC_OFF (16) + #define MCHBAR_CH0_CR_TC_RFTP_tRFC_WID ( 9) + #define MCHBAR_CH0_CR_TC_RFTP_tRFC_MSK (0x01FF0000) + #define MCHBAR_CH0_CR_TC_RFTP_tRFC_MAX (0x000001FF) + #define MCHBAR_CH0_CR_TC_RFTP_tRFC_DEF (0x000000B4) + #define MCHBAR_CH0_CR_TC_RFTP_tREFIx9_OFF (25) + #define MCHBAR_CH0_CR_TC_RFTP_tREFIx9_WID ( 7) + #define MCHBAR_CH0_CR_TC_RFTP_tREFIx9_MSK (0xFE000000) + #define MCHBAR_CH0_CR_TC_RFTP_tREFIx9_MAX (0x0000007F) + #define MCHBAR_CH0_CR_TC_RFTP_tREFIx9_DEF (0x00000023) + +#define MCHBAR_CH0_CR_TC_MR2_SHADDOW_REG (0x0000429C) + #define MCHBAR_CH0_CR_TC_MR2_SHADDOW_MR2_sh_low_OFF ( 0) + #define MCHBAR_CH0_CR_TC_MR2_SHADDOW_MR2_sh_low_WID ( 6) + #define MCHBAR_CH0_CR_TC_MR2_SHADDOW_MR2_sh_low_MSK (0x0000003F) + #define MCHBAR_CH0_CR_TC_MR2_SHADDOW_MR2_sh_low_MAX (0x0000003F) + #define MCHBAR_CH0_CR_TC_MR2_SHADDOW_MR2_sh_low_DEF (0x00000000) + #define MCHBAR_CH0_CR_TC_MR2_SHADDOW_SRT_avail_OFF ( 6) + #define MCHBAR_CH0_CR_TC_MR2_SHADDOW_SRT_avail_WID ( 2) + #define MCHBAR_CH0_CR_TC_MR2_SHADDOW_SRT_avail_MSK (0x000000C0) + #define MCHBAR_CH0_CR_TC_MR2_SHADDOW_SRT_avail_MAX (0x00000003) + #define MCHBAR_CH0_CR_TC_MR2_SHADDOW_SRT_avail_DEF (0x00000000) + #define MCHBAR_CH0_CR_TC_MR2_SHADDOW_MR2_sh_high_OFF ( 8) + #define MCHBAR_CH0_CR_TC_MR2_SHADDOW_MR2_sh_high_WID ( 3) + #define MCHBAR_CH0_CR_TC_MR2_SHADDOW_MR2_sh_high_MSK (0x00000700) + #define MCHBAR_CH0_CR_TC_MR2_SHADDOW_MR2_sh_high_MAX (0x00000007) + #define MCHBAR_CH0_CR_TC_MR2_SHADDOW_MR2_sh_high_DEF (0x00000000) + #define MCHBAR_CH0_CR_TC_MR2_SHADDOW_Addr_bit_swizzle_OFF (14) + #define MCHBAR_CH0_CR_TC_MR2_SHADDOW_Addr_bit_swizzle_WID ( 2) + #define MCHBAR_CH0_CR_TC_MR2_SHADDOW_Addr_bit_swizzle_MSK (0x0000C000) + #define MCHBAR_CH0_CR_TC_MR2_SHADDOW_Addr_bit_swizzle_MAX (0x00000003) + #define MCHBAR_CH0_CR_TC_MR2_SHADDOW_Addr_bit_swizzle_DEF (0x00000000) + +#define MCHBAR_CH0_CR_MC_INIT_STATE_REG (0x000042A0) + #define MCHBAR_CH0_CR_MC_INIT_STATE_Rank_occupancy_OFF ( 0) + #define MCHBAR_CH0_CR_MC_INIT_STATE_Rank_occupancy_WID ( 4) + #define MCHBAR_CH0_CR_MC_INIT_STATE_Rank_occupancy_MSK (0x0000000F) + #define MCHBAR_CH0_CR_MC_INIT_STATE_Rank_occupancy_MAX (0x0000000F) + #define MCHBAR_CH0_CR_MC_INIT_STATE_Rank_occupancy_DEF (0x0000000F) + +#define MCHBAR_CH0_CR_TC_SRFTP_REG (0x000042A4) + #define MCHBAR_CH0_CR_TC_SRFTP_tXSDLL_OFF ( 0) + #define MCHBAR_CH0_CR_TC_SRFTP_tXSDLL_WID (12) + #define MCHBAR_CH0_CR_TC_SRFTP_tXSDLL_MSK (0x00000FFF) + #define MCHBAR_CH0_CR_TC_SRFTP_tXSDLL_MAX (0x00000FFF) + #define MCHBAR_CH0_CR_TC_SRFTP_tXSDLL_DEF (0x00000200) + #define MCHBAR_CH0_CR_TC_SRFTP_tXS_offset_OFF (12) + #define MCHBAR_CH0_CR_TC_SRFTP_tXS_offset_WID ( 4) + #define MCHBAR_CH0_CR_TC_SRFTP_tXS_offset_MSK (0x0000F000) + #define MCHBAR_CH0_CR_TC_SRFTP_tXS_offset_MAX (0x0000000F) + #define MCHBAR_CH0_CR_TC_SRFTP_tXS_offset_DEF (0x0000000B) + #define MCHBAR_CH0_CR_TC_SRFTP_tZQOPER_OFF (16) + #define MCHBAR_CH0_CR_TC_SRFTP_tZQOPER_WID (10) + #define MCHBAR_CH0_CR_TC_SRFTP_tZQOPER_MSK (0x03FF0000) + #define MCHBAR_CH0_CR_TC_SRFTP_tZQOPER_MAX (0x000003FF) + #define MCHBAR_CH0_CR_TC_SRFTP_tZQOPER_DEF (0x00000100) + #define MCHBAR_CH0_CR_TC_SRFTP_tMOD_OFF (28) + #define MCHBAR_CH0_CR_TC_SRFTP_tMOD_WID ( 4) + #define MCHBAR_CH0_CR_TC_SRFTP_tMOD_MSK (0xF0000000) + #define MCHBAR_CH0_CR_TC_SRFTP_tMOD_MAX (0x0000000F) + #define MCHBAR_CH0_CR_TC_SRFTP_tMOD_DEF (0x00000000) + +#define MCHBAR_CH0_CR_WDB_VISA_SEL_REG (0x000042A8) + #define MCHBAR_CH0_CR_WDB_VISA_SEL_VISAByteSel_OFF ( 0) + #define MCHBAR_CH0_CR_WDB_VISA_SEL_VISAByteSel_WID ( 3) + #define MCHBAR_CH0_CR_WDB_VISA_SEL_VISAByteSel_MSK (0x00000007) + #define MCHBAR_CH0_CR_WDB_VISA_SEL_VISAByteSel_MAX (0x00000007) + #define MCHBAR_CH0_CR_WDB_VISA_SEL_VISAByteSel_DEF (0x00000000) + +#define MCHBAR_CH0_CR_DCLK_LDAT_PDAT_REG (0x000042C0) + #define MCHBAR_CH0_CR_DCLK_LDAT_PDAT_FASTADDR_OFF ( 0) + #define MCHBAR_CH0_CR_DCLK_LDAT_PDAT_FASTADDR_WID (12) + #define MCHBAR_CH0_CR_DCLK_LDAT_PDAT_FASTADDR_MSK (0x00000FFF) + #define MCHBAR_CH0_CR_DCLK_LDAT_PDAT_FASTADDR_MAX (0x00000FFF) + #define MCHBAR_CH0_CR_DCLK_LDAT_PDAT_FASTADDR_DEF (0x00000000) + #define MCHBAR_CH0_CR_DCLK_LDAT_PDAT_ADDREN_OFF (16) + #define MCHBAR_CH0_CR_DCLK_LDAT_PDAT_ADDREN_WID ( 1) + #define MCHBAR_CH0_CR_DCLK_LDAT_PDAT_ADDREN_MSK (0x00010000) + #define MCHBAR_CH0_CR_DCLK_LDAT_PDAT_ADDREN_MAX (0x00000001) + #define MCHBAR_CH0_CR_DCLK_LDAT_PDAT_ADDREN_DEF (0x00000000) + #define MCHBAR_CH0_CR_DCLK_LDAT_PDAT_SEQEN_OFF (17) + #define MCHBAR_CH0_CR_DCLK_LDAT_PDAT_SEQEN_WID ( 1) + #define MCHBAR_CH0_CR_DCLK_LDAT_PDAT_SEQEN_MSK (0x00020000) + #define MCHBAR_CH0_CR_DCLK_LDAT_PDAT_SEQEN_MAX (0x00000001) + #define MCHBAR_CH0_CR_DCLK_LDAT_PDAT_SEQEN_DEF (0x00000000) + #define MCHBAR_CH0_CR_DCLK_LDAT_PDAT_POL0_OFF (18) + #define MCHBAR_CH0_CR_DCLK_LDAT_PDAT_POL0_WID ( 1) + #define MCHBAR_CH0_CR_DCLK_LDAT_PDAT_POL0_MSK (0x00040000) + #define MCHBAR_CH0_CR_DCLK_LDAT_PDAT_POL0_MAX (0x00000001) + #define MCHBAR_CH0_CR_DCLK_LDAT_PDAT_POL0_DEF (0x00000000) + #define MCHBAR_CH0_CR_DCLK_LDAT_PDAT_POL1_OFF (19) + #define MCHBAR_CH0_CR_DCLK_LDAT_PDAT_POL1_WID ( 1) + #define MCHBAR_CH0_CR_DCLK_LDAT_PDAT_POL1_MSK (0x00080000) + #define MCHBAR_CH0_CR_DCLK_LDAT_PDAT_POL1_MAX (0x00000001) + #define MCHBAR_CH0_CR_DCLK_LDAT_PDAT_POL1_DEF (0x00000000) + #define MCHBAR_CH0_CR_DCLK_LDAT_PDAT_CMDA_OFF (20) + #define MCHBAR_CH0_CR_DCLK_LDAT_PDAT_CMDA_WID ( 4) + #define MCHBAR_CH0_CR_DCLK_LDAT_PDAT_CMDA_MSK (0x00F00000) + #define MCHBAR_CH0_CR_DCLK_LDAT_PDAT_CMDA_MAX (0x0000000F) + #define MCHBAR_CH0_CR_DCLK_LDAT_PDAT_CMDA_DEF (0x00000000) + #define MCHBAR_CH0_CR_DCLK_LDAT_PDAT_CMDB_OFF (24) + #define MCHBAR_CH0_CR_DCLK_LDAT_PDAT_CMDB_WID ( 4) + #define MCHBAR_CH0_CR_DCLK_LDAT_PDAT_CMDB_MSK (0x0F000000) + #define MCHBAR_CH0_CR_DCLK_LDAT_PDAT_CMDB_MAX (0x0000000F) + #define MCHBAR_CH0_CR_DCLK_LDAT_PDAT_CMDB_DEF (0x00000000) + #define MCHBAR_CH0_CR_DCLK_LDAT_PDAT_CMDC_OFF (28) + #define MCHBAR_CH0_CR_DCLK_LDAT_PDAT_CMDC_WID ( 4) + #define MCHBAR_CH0_CR_DCLK_LDAT_PDAT_CMDC_MSK (0xF0000000) + #define MCHBAR_CH0_CR_DCLK_LDAT_PDAT_CMDC_MAX (0x0000000F) + #define MCHBAR_CH0_CR_DCLK_LDAT_PDAT_CMDC_DEF (0x00000000) + +#define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_REG (0x000042C4) + #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_BANKSEL_OFF ( 0) + #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_BANKSEL_WID ( 4) + #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_BANKSEL_MSK (0x0000000F) + #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_BANKSEL_MAX (0x0000000F) + #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_BANKSEL_DEF (0x00000000) + #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_ARRAYSEL_OFF ( 5) + #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_ARRAYSEL_WID ( 5) + #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_ARRAYSEL_MSK (0x000003E0) + #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_ARRAYSEL_MAX (0x0000001F) + #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_ARRAYSEL_DEF (0x00000000) + #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_CMP_OFF (10) + #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_CMP_WID ( 1) + #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_CMP_MSK (0x00000400) + #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_CMP_MAX (0x00000001) + #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_CMP_DEF (0x00000000) + #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_REP_OFF (11) + #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_REP_WID ( 1) + #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_REP_MSK (0x00000800) + #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_REP_MAX (0x00000001) + #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_REP_DEF (0x00000000) + #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_DWORD_OFF (12) + #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_DWORD_WID ( 4) + #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_DWORD_MSK (0x0000F000) + #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_DWORD_MAX (0x0000000F) + #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_DWORD_DEF (0x00000000) + #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_MODE_OFF (16) + #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_MODE_WID ( 2) + #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_MODE_MSK (0x00030000) + #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_MODE_MAX (0x00000003) + #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_MODE_DEF (0x00000000) + #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_MPMAP_OFF (18) + #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_MPMAP_WID ( 6) + #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_MPMAP_MSK (0x00FC0000) + #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_MPMAP_MAX (0x0000003F) + #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_MPMAP_DEF (0x00000000) + #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_MPBOFFSET_OFF (24) + #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_MPBOFFSET_WID ( 4) + #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_MPBOFFSET_MSK (0x0F000000) + #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_MPBOFFSET_MAX (0x0000000F) + #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_MPBOFFSET_DEF (0x00000000) + #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_STAGE_EN_OFF (28) + #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_STAGE_EN_WID ( 1) + #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_STAGE_EN_MSK (0x10000000) + #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_STAGE_EN_MAX (0x00000001) + #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_STAGE_EN_DEF (0x00000000) + #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_SHADOW_OFF (29) + #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_SHADOW_WID ( 2) + #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_SHADOW_MSK (0x60000000) + #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_SHADOW_MAX (0x00000003) + #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_SHADOW_DEF (0x00000000) + +#define MCHBAR_CH0_CR_DCLK_LDAT_DATAOUT_REG (0x000042C8) + #define MCHBAR_CH0_CR_DCLK_LDAT_DATAOUT_DATOUT_OFF ( 0) + #define MCHBAR_CH0_CR_DCLK_LDAT_DATAOUT_DATOUT_WID (32) + #define MCHBAR_CH0_CR_DCLK_LDAT_DATAOUT_DATOUT_MSK (0xFFFFFFFF) + #define MCHBAR_CH0_CR_DCLK_LDAT_DATAOUT_DATOUT_MAX (0xFFFFFFFF) + #define MCHBAR_CH0_CR_DCLK_LDAT_DATAOUT_DATOUT_DEF (0x00000000) + +#define MCHBAR_CH0_CR_DCLK_LDAT_DATAIN_0_REG (0x000042CC) + #define MCHBAR_CH0_CR_DCLK_LDAT_DATAIN_0_DATIN_OFF ( 0) + #define MCHBAR_CH0_CR_DCLK_LDAT_DATAIN_0_DATIN_WID (32) + #define MCHBAR_CH0_CR_DCLK_LDAT_DATAIN_0_DATIN_MSK (0xFFFFFFFF) + #define MCHBAR_CH0_CR_DCLK_LDAT_DATAIN_0_DATIN_MAX (0xFFFFFFFF) + #define MCHBAR_CH0_CR_DCLK_LDAT_DATAIN_0_DATIN_DEF (0x00000000) + +#define MCHBAR_CH0_CR_QCLK_LDAT_PDAT_REG (0x000042D0) + #define MCHBAR_CH0_CR_QCLK_LDAT_PDAT_FASTADDR_OFF ( 0) + #define MCHBAR_CH0_CR_QCLK_LDAT_PDAT_FASTADDR_WID (12) + #define MCHBAR_CH0_CR_QCLK_LDAT_PDAT_FASTADDR_MSK (0x00000FFF) + #define MCHBAR_CH0_CR_QCLK_LDAT_PDAT_FASTADDR_MAX (0x00000FFF) + #define MCHBAR_CH0_CR_QCLK_LDAT_PDAT_FASTADDR_DEF (0x00000000) + #define MCHBAR_CH0_CR_QCLK_LDAT_PDAT_ADDREN_OFF (16) + #define MCHBAR_CH0_CR_QCLK_LDAT_PDAT_ADDREN_WID ( 1) + #define MCHBAR_CH0_CR_QCLK_LDAT_PDAT_ADDREN_MSK (0x00010000) + #define MCHBAR_CH0_CR_QCLK_LDAT_PDAT_ADDREN_MAX (0x00000001) + #define MCHBAR_CH0_CR_QCLK_LDAT_PDAT_ADDREN_DEF (0x00000000) + #define MCHBAR_CH0_CR_QCLK_LDAT_PDAT_SEQEN_OFF (17) + #define MCHBAR_CH0_CR_QCLK_LDAT_PDAT_SEQEN_WID ( 1) + #define MCHBAR_CH0_CR_QCLK_LDAT_PDAT_SEQEN_MSK (0x00020000) + #define MCHBAR_CH0_CR_QCLK_LDAT_PDAT_SEQEN_MAX (0x00000001) + #define MCHBAR_CH0_CR_QCLK_LDAT_PDAT_SEQEN_DEF (0x00000000) + #define MCHBAR_CH0_CR_QCLK_LDAT_PDAT_POL0_OFF (18) + #define MCHBAR_CH0_CR_QCLK_LDAT_PDAT_POL0_WID ( 1) + #define MCHBAR_CH0_CR_QCLK_LDAT_PDAT_POL0_MSK (0x00040000) + #define MCHBAR_CH0_CR_QCLK_LDAT_PDAT_POL0_MAX (0x00000001) + #define MCHBAR_CH0_CR_QCLK_LDAT_PDAT_POL0_DEF (0x00000000) + #define MCHBAR_CH0_CR_QCLK_LDAT_PDAT_POL1_OFF (19) + #define MCHBAR_CH0_CR_QCLK_LDAT_PDAT_POL1_WID ( 1) + #define MCHBAR_CH0_CR_QCLK_LDAT_PDAT_POL1_MSK (0x00080000) + #define MCHBAR_CH0_CR_QCLK_LDAT_PDAT_POL1_MAX (0x00000001) + #define MCHBAR_CH0_CR_QCLK_LDAT_PDAT_POL1_DEF (0x00000000) + #define MCHBAR_CH0_CR_QCLK_LDAT_PDAT_CMDA_OFF (20) + #define MCHBAR_CH0_CR_QCLK_LDAT_PDAT_CMDA_WID ( 4) + #define MCHBAR_CH0_CR_QCLK_LDAT_PDAT_CMDA_MSK (0x00F00000) + #define MCHBAR_CH0_CR_QCLK_LDAT_PDAT_CMDA_MAX (0x0000000F) + #define MCHBAR_CH0_CR_QCLK_LDAT_PDAT_CMDA_DEF (0x00000000) + #define MCHBAR_CH0_CR_QCLK_LDAT_PDAT_CMDB_OFF (24) + #define MCHBAR_CH0_CR_QCLK_LDAT_PDAT_CMDB_WID ( 4) + #define MCHBAR_CH0_CR_QCLK_LDAT_PDAT_CMDB_MSK (0x0F000000) + #define MCHBAR_CH0_CR_QCLK_LDAT_PDAT_CMDB_MAX (0x0000000F) + #define MCHBAR_CH0_CR_QCLK_LDAT_PDAT_CMDB_DEF (0x00000000) + #define MCHBAR_CH0_CR_QCLK_LDAT_PDAT_CMDC_OFF (28) + #define MCHBAR_CH0_CR_QCLK_LDAT_PDAT_CMDC_WID ( 4) + #define MCHBAR_CH0_CR_QCLK_LDAT_PDAT_CMDC_MSK (0xF0000000) + #define MCHBAR_CH0_CR_QCLK_LDAT_PDAT_CMDC_MAX (0x0000000F) + #define MCHBAR_CH0_CR_QCLK_LDAT_PDAT_CMDC_DEF (0x00000000) + +#define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_REG (0x000042D4) + #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_BANKSEL_OFF ( 0) + #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_BANKSEL_WID ( 4) + #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_BANKSEL_MSK (0x0000000F) + #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_BANKSEL_MAX (0x0000000F) + #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_BANKSEL_DEF (0x00000000) + #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_ARRAYSEL_OFF ( 5) + #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_ARRAYSEL_WID ( 5) + #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_ARRAYSEL_MSK (0x000003E0) + #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_ARRAYSEL_MAX (0x0000001F) + #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_ARRAYSEL_DEF (0x00000000) + #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_CMP_OFF (10) + #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_CMP_WID ( 1) + #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_CMP_MSK (0x00000400) + #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_CMP_MAX (0x00000001) + #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_CMP_DEF (0x00000000) + #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_REP_OFF (11) + #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_REP_WID ( 1) + #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_REP_MSK (0x00000800) + #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_REP_MAX (0x00000001) + #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_REP_DEF (0x00000000) + #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_DWORD_OFF (12) + #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_DWORD_WID ( 4) + #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_DWORD_MSK (0x0000F000) + #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_DWORD_MAX (0x0000000F) + #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_DWORD_DEF (0x00000000) + #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_MODE_OFF (16) + #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_MODE_WID ( 2) + #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_MODE_MSK (0x00030000) + #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_MODE_MAX (0x00000003) + #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_MODE_DEF (0x00000000) + #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_MPMAP_OFF (18) + #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_MPMAP_WID ( 6) + #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_MPMAP_MSK (0x00FC0000) + #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_MPMAP_MAX (0x0000003F) + #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_MPMAP_DEF (0x00000000) + #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_MPBOFFSET_OFF (24) + #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_MPBOFFSET_WID ( 4) + #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_MPBOFFSET_MSK (0x0F000000) + #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_MPBOFFSET_MAX (0x0000000F) + #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_MPBOFFSET_DEF (0x00000000) + #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_STAGE_EN_OFF (28) + #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_STAGE_EN_WID ( 1) + #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_STAGE_EN_MSK (0x10000000) + #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_STAGE_EN_MAX (0x00000001) + #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_STAGE_EN_DEF (0x00000000) + #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_SHADOW_OFF (29) + #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_SHADOW_WID ( 2) + #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_SHADOW_MSK (0x60000000) + #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_SHADOW_MAX (0x00000003) + #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_SHADOW_DEF (0x00000000) + +#define MCHBAR_CH0_CR_QCLK_LDAT_DATAOUT_REG (0x000042D8) + #define MCHBAR_CH0_CR_QCLK_LDAT_DATAOUT_DATOUT_OFF ( 0) + #define MCHBAR_CH0_CR_QCLK_LDAT_DATAOUT_DATOUT_WID (32) + #define MCHBAR_CH0_CR_QCLK_LDAT_DATAOUT_DATOUT_MSK (0xFFFFFFFF) + #define MCHBAR_CH0_CR_QCLK_LDAT_DATAOUT_DATOUT_MAX (0xFFFFFFFF) + #define MCHBAR_CH0_CR_QCLK_LDAT_DATAOUT_DATOUT_DEF (0x00000000) + +#define MCHBAR_CH0_CR_QCLK_LDAT_DATAIN_0_REG (0x000042DC) + #define MCHBAR_CH0_CR_QCLK_LDAT_DATAIN_0_DATIN_OFF ( 0) + #define MCHBAR_CH0_CR_QCLK_LDAT_DATAIN_0_DATIN_WID (32) + #define MCHBAR_CH0_CR_QCLK_LDAT_DATAIN_0_DATIN_MSK (0xFFFFFFFF) + #define MCHBAR_CH0_CR_QCLK_LDAT_DATAIN_0_DATIN_MAX (0xFFFFFFFF) + #define MCHBAR_CH0_CR_QCLK_LDAT_DATAIN_0_DATIN_DEF (0x00000000) + +#define MCHBAR_CH0_CR_QCLK_LDAT_DATAIN_1_REG (0x000042E0) + #define MCHBAR_CH0_CR_QCLK_LDAT_DATAIN_1_DATIN_OFF ( 0) + #define MCHBAR_CH0_CR_QCLK_LDAT_DATAIN_1_DATIN_WID (32) + #define MCHBAR_CH0_CR_QCLK_LDAT_DATAIN_1_DATIN_MSK (0xFFFFFFFF) + #define MCHBAR_CH0_CR_QCLK_LDAT_DATAIN_1_DATIN_MAX (0xFFFFFFFF) + #define MCHBAR_CH0_CR_QCLK_LDAT_DATAIN_1_DATIN_DEF (0x00000000) + +#define MCHBAR_CH0_CR_QUEUE_ENTRY_DISABLE_RPQ_REG (0x000042E4) + #define MCHBAR_CH0_CR_QUEUE_ENTRY_DISABLE_RPQ_RPQ_disable_OFF ( 0) + #define MCHBAR_CH0_CR_QUEUE_ENTRY_DISABLE_RPQ_RPQ_disable_WID (28) + #define MCHBAR_CH0_CR_QUEUE_ENTRY_DISABLE_RPQ_RPQ_disable_MSK (0x0FFFFFFF) + #define MCHBAR_CH0_CR_QUEUE_ENTRY_DISABLE_RPQ_RPQ_disable_MAX (0x0FFFFFFF) + #define MCHBAR_CH0_CR_QUEUE_ENTRY_DISABLE_RPQ_RPQ_disable_DEF (0x00000000) + +#define MCHBAR_CH0_CR_QUEUE_ENTRY_DISABLE_WPQ_REG (0x000042E8) + #define MCHBAR_CH0_CR_QUEUE_ENTRY_DISABLE_WPQ_WPQ_disable_OFF ( 0) + #define MCHBAR_CH0_CR_QUEUE_ENTRY_DISABLE_WPQ_WPQ_disable_WID (32) + #define MCHBAR_CH0_CR_QUEUE_ENTRY_DISABLE_WPQ_WPQ_disable_MSK (0xFFFFFFFF) + #define MCHBAR_CH0_CR_QUEUE_ENTRY_DISABLE_WPQ_WPQ_disable_MAX (0xFFFFFFFF) + #define MCHBAR_CH0_CR_QUEUE_ENTRY_DISABLE_WPQ_WPQ_disable_DEF (0x00000000) + +#define MCHBAR_CH0_CR_PM_DIMM_IDLE_ENERGY_REG (0x000042EC) + #define MCHBAR_CH0_CR_PM_DIMM_IDLE_ENERGY_DIMM0_IDLE_ENERGY_OFF ( 0) + #define MCHBAR_CH0_CR_PM_DIMM_IDLE_ENERGY_DIMM0_IDLE_ENERGY_WID ( 6) + #define MCHBAR_CH0_CR_PM_DIMM_IDLE_ENERGY_DIMM0_IDLE_ENERGY_MSK (0x0000003F) + #define MCHBAR_CH0_CR_PM_DIMM_IDLE_ENERGY_DIMM0_IDLE_ENERGY_MAX (0x0000003F) + #define MCHBAR_CH0_CR_PM_DIMM_IDLE_ENERGY_DIMM0_IDLE_ENERGY_DEF (0x00000000) + #define MCHBAR_CH0_CR_PM_DIMM_IDLE_ENERGY_DIMM1_IDLE_ENERGY_OFF ( 8) + #define MCHBAR_CH0_CR_PM_DIMM_IDLE_ENERGY_DIMM1_IDLE_ENERGY_WID ( 6) + #define MCHBAR_CH0_CR_PM_DIMM_IDLE_ENERGY_DIMM1_IDLE_ENERGY_MSK (0x00003F00) + #define MCHBAR_CH0_CR_PM_DIMM_IDLE_ENERGY_DIMM1_IDLE_ENERGY_MAX (0x0000003F) + #define MCHBAR_CH0_CR_PM_DIMM_IDLE_ENERGY_DIMM1_IDLE_ENERGY_DEF (0x00000000) + +#define MCHBAR_CH0_CR_PM_DIMM_PD_ENERGY_REG (0x000042F0) + #define MCHBAR_CH0_CR_PM_DIMM_PD_ENERGY_DIMM0_PD_ENERGY_OFF ( 0) + #define MCHBAR_CH0_CR_PM_DIMM_PD_ENERGY_DIMM0_PD_ENERGY_WID ( 6) + #define MCHBAR_CH0_CR_PM_DIMM_PD_ENERGY_DIMM0_PD_ENERGY_MSK (0x0000003F) + #define MCHBAR_CH0_CR_PM_DIMM_PD_ENERGY_DIMM0_PD_ENERGY_MAX (0x0000003F) + #define MCHBAR_CH0_CR_PM_DIMM_PD_ENERGY_DIMM0_PD_ENERGY_DEF (0x00000000) + #define MCHBAR_CH0_CR_PM_DIMM_PD_ENERGY_DIMM1_PD_ENERGY_OFF ( 8) + #define MCHBAR_CH0_CR_PM_DIMM_PD_ENERGY_DIMM1_PD_ENERGY_WID ( 6) + #define MCHBAR_CH0_CR_PM_DIMM_PD_ENERGY_DIMM1_PD_ENERGY_MSK (0x00003F00) + #define MCHBAR_CH0_CR_PM_DIMM_PD_ENERGY_DIMM1_PD_ENERGY_MAX (0x0000003F) + #define MCHBAR_CH0_CR_PM_DIMM_PD_ENERGY_DIMM1_PD_ENERGY_DEF (0x00000000) + +#define MCHBAR_CH0_CR_PM_DIMM_ACT_ENERGY_REG (0x000042F4) + #define MCHBAR_CH0_CR_PM_DIMM_ACT_ENERGY_DIMM0_ACT_ENERGY_OFF ( 0) + #define MCHBAR_CH0_CR_PM_DIMM_ACT_ENERGY_DIMM0_ACT_ENERGY_WID ( 8) + #define MCHBAR_CH0_CR_PM_DIMM_ACT_ENERGY_DIMM0_ACT_ENERGY_MSK (0x000000FF) + #define MCHBAR_CH0_CR_PM_DIMM_ACT_ENERGY_DIMM0_ACT_ENERGY_MAX (0x000000FF) + #define MCHBAR_CH0_CR_PM_DIMM_ACT_ENERGY_DIMM0_ACT_ENERGY_DEF (0x00000000) + #define MCHBAR_CH0_CR_PM_DIMM_ACT_ENERGY_DIMM1_ACT_ENERGY_OFF ( 8) + #define MCHBAR_CH0_CR_PM_DIMM_ACT_ENERGY_DIMM1_ACT_ENERGY_WID ( 8) + #define MCHBAR_CH0_CR_PM_DIMM_ACT_ENERGY_DIMM1_ACT_ENERGY_MSK (0x0000FF00) + #define MCHBAR_CH0_CR_PM_DIMM_ACT_ENERGY_DIMM1_ACT_ENERGY_MAX (0x000000FF) + #define MCHBAR_CH0_CR_PM_DIMM_ACT_ENERGY_DIMM1_ACT_ENERGY_DEF (0x00000000) + +#define MCHBAR_CH0_CR_PM_DIMM_RD_ENERGY_REG (0x000042F8) + #define MCHBAR_CH0_CR_PM_DIMM_RD_ENERGY_DIMM0_RD_ENERGY_OFF ( 0) + #define MCHBAR_CH0_CR_PM_DIMM_RD_ENERGY_DIMM0_RD_ENERGY_WID ( 8) + #define MCHBAR_CH0_CR_PM_DIMM_RD_ENERGY_DIMM0_RD_ENERGY_MSK (0x000000FF) + #define MCHBAR_CH0_CR_PM_DIMM_RD_ENERGY_DIMM0_RD_ENERGY_MAX (0x000000FF) + #define MCHBAR_CH0_CR_PM_DIMM_RD_ENERGY_DIMM0_RD_ENERGY_DEF (0x00000000) + #define MCHBAR_CH0_CR_PM_DIMM_RD_ENERGY_DIMM1_RD_ENERGY_OFF ( 8) + #define MCHBAR_CH0_CR_PM_DIMM_RD_ENERGY_DIMM1_RD_ENERGY_WID ( 8) + #define MCHBAR_CH0_CR_PM_DIMM_RD_ENERGY_DIMM1_RD_ENERGY_MSK (0x0000FF00) + #define MCHBAR_CH0_CR_PM_DIMM_RD_ENERGY_DIMM1_RD_ENERGY_MAX (0x000000FF) + #define MCHBAR_CH0_CR_PM_DIMM_RD_ENERGY_DIMM1_RD_ENERGY_DEF (0x00000000) + +#define MCHBAR_CH0_CR_PM_DIMM_WR_ENERGY_REG (0x000042FC) + #define MCHBAR_CH0_CR_PM_DIMM_WR_ENERGY_DIMM0_WR_ENERGY_OFF ( 0) + #define MCHBAR_CH0_CR_PM_DIMM_WR_ENERGY_DIMM0_WR_ENERGY_WID ( 8) + #define MCHBAR_CH0_CR_PM_DIMM_WR_ENERGY_DIMM0_WR_ENERGY_MSK (0x000000FF) + #define MCHBAR_CH0_CR_PM_DIMM_WR_ENERGY_DIMM0_WR_ENERGY_MAX (0x000000FF) + #define MCHBAR_CH0_CR_PM_DIMM_WR_ENERGY_DIMM0_WR_ENERGY_DEF (0x00000000) + #define MCHBAR_CH0_CR_PM_DIMM_WR_ENERGY_DIMM1_WR_ENERGY_OFF ( 8) + #define MCHBAR_CH0_CR_PM_DIMM_WR_ENERGY_DIMM1_WR_ENERGY_WID ( 8) + #define MCHBAR_CH0_CR_PM_DIMM_WR_ENERGY_DIMM1_WR_ENERGY_MSK (0x0000FF00) + #define MCHBAR_CH0_CR_PM_DIMM_WR_ENERGY_DIMM1_WR_ENERGY_MAX (0x000000FF) + #define MCHBAR_CH0_CR_PM_DIMM_WR_ENERGY_DIMM1_WR_ENERGY_DEF (0x00000000) + +#define MCHBAR_CH0_CR_PM_THRT_CKE_MIN_REG (0x00004328) + #define MCHBAR_CH0_CR_PM_THRT_CKE_MIN_CKE_MIN_OFF ( 0) + #define MCHBAR_CH0_CR_PM_THRT_CKE_MIN_CKE_MIN_WID ( 8) + #define MCHBAR_CH0_CR_PM_THRT_CKE_MIN_CKE_MIN_MSK (0x000000FF) + #define MCHBAR_CH0_CR_PM_THRT_CKE_MIN_CKE_MIN_MAX (0x000000FF) + #define MCHBAR_CH0_CR_PM_THRT_CKE_MIN_CKE_MIN_DEF (0x00000000) + #define MCHBAR_CH0_CR_PM_THRT_CKE_MIN_CKE_MIN_DEFEATURE_OFF ( 8) + #define MCHBAR_CH0_CR_PM_THRT_CKE_MIN_CKE_MIN_DEFEATURE_WID ( 1) + #define MCHBAR_CH0_CR_PM_THRT_CKE_MIN_CKE_MIN_DEFEATURE_MSK (0x00000100) + #define MCHBAR_CH0_CR_PM_THRT_CKE_MIN_CKE_MIN_DEFEATURE_MAX (0x00000001) + #define MCHBAR_CH0_CR_PM_THRT_CKE_MIN_CKE_MIN_DEFEATURE_DEF (0x00000000) + +#define MCHBAR_CH0_CR_ODLAT_CMD_MATCH0_REG (0x00004340) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH0_ODT_OFF ( 0) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH0_ODT_WID ( 4) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH0_ODT_MSK (0x0000000F) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH0_ODT_MAX (0x0000000F) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH0_ODT_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH0_Web_OFF ( 4) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH0_Web_WID ( 1) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH0_Web_MSK (0x00000010) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH0_Web_MAX (0x00000001) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH0_Web_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH0_CASb_OFF ( 5) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH0_CASb_WID ( 1) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH0_CASb_MSK (0x00000020) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH0_CASb_MAX (0x00000001) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH0_CASb_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH0_RASb_OFF ( 6) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH0_RASb_WID ( 1) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH0_RASb_MSK (0x00000040) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH0_RASb_MAX (0x00000001) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH0_RASb_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH0_CSb_OFF ( 7) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH0_CSb_WID ( 4) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH0_CSb_MSK (0x00000780) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH0_CSb_MAX (0x0000000F) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH0_CSb_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH0_CKE_OFF (11) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH0_CKE_WID ( 4) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH0_CKE_MSK (0x00007800) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH0_CKE_MAX (0x0000000F) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH0_CKE_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH0_MA_OFF (15) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH0_MA_WID (16) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH0_MA_MSK (0x7FFF8000) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH0_MA_MAX (0x0000FFFF) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH0_MA_DEF (0x00000000) + +#define MCHBAR_CH0_CR_ODLAT_CMD_MATCH1_REG (0x00004344) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH1_ODT_OFF ( 0) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH1_ODT_WID ( 4) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH1_ODT_MSK (0x0000000F) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH1_ODT_MAX (0x0000000F) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH1_ODT_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH1_Web_OFF ( 4) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH1_Web_WID ( 1) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH1_Web_MSK (0x00000010) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH1_Web_MAX (0x00000001) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH1_Web_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH1_CASb_OFF ( 5) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH1_CASb_WID ( 1) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH1_CASb_MSK (0x00000020) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH1_CASb_MAX (0x00000001) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH1_CASb_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH1_RASb_OFF ( 6) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH1_RASb_WID ( 1) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH1_RASb_MSK (0x00000040) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH1_RASb_MAX (0x00000001) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH1_RASb_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH1_CSb_OFF ( 7) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH1_CSb_WID ( 4) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH1_CSb_MSK (0x00000780) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH1_CSb_MAX (0x0000000F) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH1_CSb_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH1_CKE_OFF (11) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH1_CKE_WID ( 4) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH1_CKE_MSK (0x00007800) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH1_CKE_MAX (0x0000000F) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH1_CKE_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH1_MA_OFF (15) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH1_MA_WID (16) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH1_MA_MSK (0x7FFF8000) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH1_MA_MAX (0x0000FFFF) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH1_MA_DEF (0x00000000) + +#define MCHBAR_CH0_CR_ODLAT_CMD_MATCH2_REG (0x00004348) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH2_ODT_OFF ( 0) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH2_ODT_WID ( 4) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH2_ODT_MSK (0x0000000F) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH2_ODT_MAX (0x0000000F) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH2_ODT_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH2_Web_OFF ( 4) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH2_Web_WID ( 1) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH2_Web_MSK (0x00000010) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH2_Web_MAX (0x00000001) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH2_Web_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH2_CASb_OFF ( 5) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH2_CASb_WID ( 1) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH2_CASb_MSK (0x00000020) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH2_CASb_MAX (0x00000001) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH2_CASb_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH2_RASb_OFF ( 6) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH2_RASb_WID ( 1) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH2_RASb_MSK (0x00000040) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH2_RASb_MAX (0x00000001) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH2_RASb_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH2_CSb_OFF ( 7) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH2_CSb_WID ( 4) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH2_CSb_MSK (0x00000780) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH2_CSb_MAX (0x0000000F) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH2_CSb_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH2_CKE_OFF (11) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH2_CKE_WID ( 4) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH2_CKE_MSK (0x00007800) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH2_CKE_MAX (0x0000000F) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH2_CKE_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH2_MA_OFF (15) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH2_MA_WID (16) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH2_MA_MSK (0x7FFF8000) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH2_MA_MAX (0x0000FFFF) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH2_MA_DEF (0x00000000) + +#define MCHBAR_CH0_CR_ODLAT_CMD_MATCH3_REG (0x0000434C) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH3_ODT_OFF ( 0) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH3_ODT_WID ( 4) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH3_ODT_MSK (0x0000000F) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH3_ODT_MAX (0x0000000F) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH3_ODT_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH3_Web_OFF ( 4) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH3_Web_WID ( 1) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH3_Web_MSK (0x00000010) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH3_Web_MAX (0x00000001) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH3_Web_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH3_CASb_OFF ( 5) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH3_CASb_WID ( 1) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH3_CASb_MSK (0x00000020) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH3_CASb_MAX (0x00000001) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH3_CASb_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH3_RASb_OFF ( 6) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH3_RASb_WID ( 1) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH3_RASb_MSK (0x00000040) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH3_RASb_MAX (0x00000001) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH3_RASb_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH3_CSb_OFF ( 7) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH3_CSb_WID ( 4) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH3_CSb_MSK (0x00000780) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH3_CSb_MAX (0x0000000F) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH3_CSb_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH3_CKE_OFF (11) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH3_CKE_WID ( 4) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH3_CKE_MSK (0x00007800) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH3_CKE_MAX (0x0000000F) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH3_CKE_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH3_MA_OFF (15) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH3_MA_WID (16) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH3_MA_MSK (0x7FFF8000) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH3_MA_MAX (0x0000FFFF) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH3_MA_DEF (0x00000000) + +#define MCHBAR_CH0_CR_ODLAT_CMD_MASK0_REG (0x00004350) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK0_ODT_OFF ( 0) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK0_ODT_WID ( 4) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK0_ODT_MSK (0x0000000F) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK0_ODT_MAX (0x0000000F) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK0_ODT_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK0_Web_OFF ( 4) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK0_Web_WID ( 1) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK0_Web_MSK (0x00000010) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK0_Web_MAX (0x00000001) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK0_Web_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK0_CASb_OFF ( 5) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK0_CASb_WID ( 1) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK0_CASb_MSK (0x00000020) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK0_CASb_MAX (0x00000001) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK0_CASb_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK0_RASb_OFF ( 6) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK0_RASb_WID ( 1) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK0_RASb_MSK (0x00000040) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK0_RASb_MAX (0x00000001) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK0_RASb_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK0_CSb_OFF ( 7) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK0_CSb_WID ( 4) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK0_CSb_MSK (0x00000780) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK0_CSb_MAX (0x0000000F) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK0_CSb_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK0_CKE_OFF (11) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK0_CKE_WID ( 4) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK0_CKE_MSK (0x00007800) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK0_CKE_MAX (0x0000000F) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK0_CKE_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK0_MA_OFF (15) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK0_MA_WID (16) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK0_MA_MSK (0x7FFF8000) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK0_MA_MAX (0x0000FFFF) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK0_MA_DEF (0x00000000) + +#define MCHBAR_CH0_CR_ODLAT_CMD_MASK1_REG (0x00004354) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK1_ODT_OFF ( 0) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK1_ODT_WID ( 4) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK1_ODT_MSK (0x0000000F) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK1_ODT_MAX (0x0000000F) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK1_ODT_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK1_Web_OFF ( 4) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK1_Web_WID ( 1) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK1_Web_MSK (0x00000010) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK1_Web_MAX (0x00000001) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK1_Web_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK1_CASb_OFF ( 5) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK1_CASb_WID ( 1) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK1_CASb_MSK (0x00000020) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK1_CASb_MAX (0x00000001) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK1_CASb_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK1_RASb_OFF ( 6) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK1_RASb_WID ( 1) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK1_RASb_MSK (0x00000040) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK1_RASb_MAX (0x00000001) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK1_RASb_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK1_CSb_OFF ( 7) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK1_CSb_WID ( 4) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK1_CSb_MSK (0x00000780) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK1_CSb_MAX (0x0000000F) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK1_CSb_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK1_CKE_OFF (11) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK1_CKE_WID ( 4) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK1_CKE_MSK (0x00007800) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK1_CKE_MAX (0x0000000F) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK1_CKE_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK1_MA_OFF (15) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK1_MA_WID (16) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK1_MA_MSK (0x7FFF8000) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK1_MA_MAX (0x0000FFFF) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK1_MA_DEF (0x00000000) + +#define MCHBAR_CH0_CR_ODLAT_CMD_MASK2_REG (0x00004358) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK2_ODT_OFF ( 0) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK2_ODT_WID ( 4) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK2_ODT_MSK (0x0000000F) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK2_ODT_MAX (0x0000000F) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK2_ODT_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK2_Web_OFF ( 4) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK2_Web_WID ( 1) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK2_Web_MSK (0x00000010) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK2_Web_MAX (0x00000001) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK2_Web_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK2_CASb_OFF ( 5) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK2_CASb_WID ( 1) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK2_CASb_MSK (0x00000020) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK2_CASb_MAX (0x00000001) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK2_CASb_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK2_RASb_OFF ( 6) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK2_RASb_WID ( 1) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK2_RASb_MSK (0x00000040) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK2_RASb_MAX (0x00000001) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK2_RASb_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK2_CSb_OFF ( 7) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK2_CSb_WID ( 4) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK2_CSb_MSK (0x00000780) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK2_CSb_MAX (0x0000000F) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK2_CSb_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK2_CKE_OFF (11) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK2_CKE_WID ( 4) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK2_CKE_MSK (0x00007800) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK2_CKE_MAX (0x0000000F) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK2_CKE_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK2_MA_OFF (15) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK2_MA_WID (16) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK2_MA_MSK (0x7FFF8000) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK2_MA_MAX (0x0000FFFF) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK2_MA_DEF (0x00000000) + +#define MCHBAR_CH0_CR_ODLAT_CMD_MASK3_REG (0x0000435C) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK3_ODT_OFF ( 0) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK3_ODT_WID ( 4) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK3_ODT_MSK (0x0000000F) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK3_ODT_MAX (0x0000000F) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK3_ODT_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK3_Web_OFF ( 4) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK3_Web_WID ( 1) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK3_Web_MSK (0x00000010) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK3_Web_MAX (0x00000001) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK3_Web_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK3_CASb_OFF ( 5) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK3_CASb_WID ( 1) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK3_CASb_MSK (0x00000020) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK3_CASb_MAX (0x00000001) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK3_CASb_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK3_RASb_OFF ( 6) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK3_RASb_WID ( 1) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK3_RASb_MSK (0x00000040) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK3_RASb_MAX (0x00000001) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK3_RASb_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK3_CSb_OFF ( 7) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK3_CSb_WID ( 4) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK3_CSb_MSK (0x00000780) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK3_CSb_MAX (0x0000000F) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK3_CSb_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK3_CKE_OFF (11) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK3_CKE_WID ( 4) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK3_CKE_MSK (0x00007800) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK3_CKE_MAX (0x0000000F) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK3_CKE_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK3_MA_OFF (15) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK3_MA_WID (16) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK3_MA_MSK (0x7FFF8000) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK3_MA_MAX (0x0000FFFF) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK3_MA_DEF (0x00000000) + +#define MCHBAR_CH0_CR_ODLAT_CMD_BANK_REG (0x00004360) + #define MCHBAR_CH0_CR_ODLAT_CMD_BANK_BankMatch0_OFF ( 0) + #define MCHBAR_CH0_CR_ODLAT_CMD_BANK_BankMatch0_WID ( 3) + #define MCHBAR_CH0_CR_ODLAT_CMD_BANK_BankMatch0_MSK (0x00000007) + #define MCHBAR_CH0_CR_ODLAT_CMD_BANK_BankMatch0_MAX (0x00000007) + #define MCHBAR_CH0_CR_ODLAT_CMD_BANK_BankMatch0_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_CMD_BANK_BankMatch1_OFF ( 3) + #define MCHBAR_CH0_CR_ODLAT_CMD_BANK_BankMatch1_WID ( 3) + #define MCHBAR_CH0_CR_ODLAT_CMD_BANK_BankMatch1_MSK (0x00000038) + #define MCHBAR_CH0_CR_ODLAT_CMD_BANK_BankMatch1_MAX (0x00000007) + #define MCHBAR_CH0_CR_ODLAT_CMD_BANK_BankMatch1_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_CMD_BANK_BankMatch2_OFF ( 6) + #define MCHBAR_CH0_CR_ODLAT_CMD_BANK_BankMatch2_WID ( 3) + #define MCHBAR_CH0_CR_ODLAT_CMD_BANK_BankMatch2_MSK (0x000001C0) + #define MCHBAR_CH0_CR_ODLAT_CMD_BANK_BankMatch2_MAX (0x00000007) + #define MCHBAR_CH0_CR_ODLAT_CMD_BANK_BankMatch2_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_CMD_BANK_BankMatch3_OFF ( 9) + #define MCHBAR_CH0_CR_ODLAT_CMD_BANK_BankMatch3_WID ( 3) + #define MCHBAR_CH0_CR_ODLAT_CMD_BANK_BankMatch3_MSK (0x00000E00) + #define MCHBAR_CH0_CR_ODLAT_CMD_BANK_BankMatch3_MAX (0x00000007) + #define MCHBAR_CH0_CR_ODLAT_CMD_BANK_BankMatch3_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_CMD_BANK_BankMask0_OFF (12) + #define MCHBAR_CH0_CR_ODLAT_CMD_BANK_BankMask0_WID ( 3) + #define MCHBAR_CH0_CR_ODLAT_CMD_BANK_BankMask0_MSK (0x00007000) + #define MCHBAR_CH0_CR_ODLAT_CMD_BANK_BankMask0_MAX (0x00000007) + #define MCHBAR_CH0_CR_ODLAT_CMD_BANK_BankMask0_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_CMD_BANK_BankMask1_OFF (15) + #define MCHBAR_CH0_CR_ODLAT_CMD_BANK_BankMask1_WID ( 3) + #define MCHBAR_CH0_CR_ODLAT_CMD_BANK_BankMask1_MSK (0x00038000) + #define MCHBAR_CH0_CR_ODLAT_CMD_BANK_BankMask1_MAX (0x00000007) + #define MCHBAR_CH0_CR_ODLAT_CMD_BANK_BankMask1_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_CMD_BANK_BankMask2_OFF (18) + #define MCHBAR_CH0_CR_ODLAT_CMD_BANK_BankMask2_WID ( 3) + #define MCHBAR_CH0_CR_ODLAT_CMD_BANK_BankMask2_MSK (0x001C0000) + #define MCHBAR_CH0_CR_ODLAT_CMD_BANK_BankMask2_MAX (0x00000007) + #define MCHBAR_CH0_CR_ODLAT_CMD_BANK_BankMask2_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_CMD_BANK_BankMask3_OFF (21) + #define MCHBAR_CH0_CR_ODLAT_CMD_BANK_BankMask3_WID ( 3) + #define MCHBAR_CH0_CR_ODLAT_CMD_BANK_BankMask3_MSK (0x00E00000) + #define MCHBAR_CH0_CR_ODLAT_CMD_BANK_BankMask3_MAX (0x00000007) + #define MCHBAR_CH0_CR_ODLAT_CMD_BANK_BankMask3_DEF (0x00000000) + +#define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL0_REG (0x00004364) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL0_InputMatch_OFF ( 0) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL0_InputMatch_WID ( 4) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL0_InputMatch_MSK (0x0000000F) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL0_InputMatch_MAX (0x0000000F) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL0_InputMatch_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL0_InputInvert_OFF ( 4) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL0_InputInvert_WID ( 4) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL0_InputInvert_MSK (0x000000F0) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL0_InputInvert_MAX (0x0000000F) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL0_InputInvert_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL0_CountMatches_OFF ( 8) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL0_CountMatches_WID ( 1) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL0_CountMatches_MSK (0x00000100) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL0_CountMatches_MAX (0x00000001) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL0_CountMatches_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL0_CounterThreshold_OFF ( 9) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL0_CounterThreshold_WID (15) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL0_CounterThreshold_MSK (0x00FFFE00) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL0_CounterThreshold_MAX (0x00007FFF) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL0_CounterThreshold_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL0_CounterAction_OFF (24) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL0_CounterAction_WID ( 2) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL0_CounterAction_MSK (0x03000000) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL0_CounterAction_MAX (0x00000003) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL0_CounterAction_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL0_CounterNextState_OFF (26) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL0_CounterNextState_WID ( 2) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL0_CounterNextState_MSK (0x0C000000) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL0_CounterNextState_MAX (0x00000003) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL0_CounterNextState_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL0_MatchAction_OFF (28) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL0_MatchAction_WID ( 2) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL0_MatchAction_MSK (0x30000000) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL0_MatchAction_MAX (0x00000003) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL0_MatchAction_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL0_MatchNextState_OFF (30) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL0_MatchNextState_WID ( 2) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL0_MatchNextState_MSK (0xC0000000) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL0_MatchNextState_MAX (0x00000003) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL0_MatchNextState_DEF (0x00000000) + +#define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL1_REG (0x00004368) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL1_InputMatch_OFF ( 0) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL1_InputMatch_WID ( 4) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL1_InputMatch_MSK (0x0000000F) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL1_InputMatch_MAX (0x0000000F) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL1_InputMatch_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL1_InputInvert_OFF ( 4) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL1_InputInvert_WID ( 4) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL1_InputInvert_MSK (0x000000F0) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL1_InputInvert_MAX (0x0000000F) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL1_InputInvert_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL1_CountMatches_OFF ( 8) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL1_CountMatches_WID ( 1) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL1_CountMatches_MSK (0x00000100) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL1_CountMatches_MAX (0x00000001) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL1_CountMatches_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL1_CounterThreshold_OFF ( 9) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL1_CounterThreshold_WID (15) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL1_CounterThreshold_MSK (0x00FFFE00) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL1_CounterThreshold_MAX (0x00007FFF) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL1_CounterThreshold_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL1_CounterAction_OFF (24) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL1_CounterAction_WID ( 2) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL1_CounterAction_MSK (0x03000000) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL1_CounterAction_MAX (0x00000003) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL1_CounterAction_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL1_CounterNextState_OFF (26) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL1_CounterNextState_WID ( 2) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL1_CounterNextState_MSK (0x0C000000) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL1_CounterNextState_MAX (0x00000003) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL1_CounterNextState_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL1_MatchAction_OFF (28) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL1_MatchAction_WID ( 2) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL1_MatchAction_MSK (0x30000000) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL1_MatchAction_MAX (0x00000003) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL1_MatchAction_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL1_MatchNextState_OFF (30) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL1_MatchNextState_WID ( 2) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL1_MatchNextState_MSK (0xC0000000) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL1_MatchNextState_MAX (0x00000003) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL1_MatchNextState_DEF (0x00000000) + +#define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL2_REG (0x0000436C) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL2_InputMatch_OFF ( 0) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL2_InputMatch_WID ( 4) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL2_InputMatch_MSK (0x0000000F) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL2_InputMatch_MAX (0x0000000F) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL2_InputMatch_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL2_InputInvert_OFF ( 4) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL2_InputInvert_WID ( 4) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL2_InputInvert_MSK (0x000000F0) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL2_InputInvert_MAX (0x0000000F) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL2_InputInvert_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL2_CountMatches_OFF ( 8) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL2_CountMatches_WID ( 1) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL2_CountMatches_MSK (0x00000100) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL2_CountMatches_MAX (0x00000001) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL2_CountMatches_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL2_CounterThreshold_OFF ( 9) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL2_CounterThreshold_WID (15) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL2_CounterThreshold_MSK (0x00FFFE00) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL2_CounterThreshold_MAX (0x00007FFF) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL2_CounterThreshold_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL2_CounterAction_OFF (24) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL2_CounterAction_WID ( 2) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL2_CounterAction_MSK (0x03000000) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL2_CounterAction_MAX (0x00000003) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL2_CounterAction_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL2_CounterNextState_OFF (26) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL2_CounterNextState_WID ( 2) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL2_CounterNextState_MSK (0x0C000000) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL2_CounterNextState_MAX (0x00000003) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL2_CounterNextState_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL2_MatchAction_OFF (28) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL2_MatchAction_WID ( 2) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL2_MatchAction_MSK (0x30000000) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL2_MatchAction_MAX (0x00000003) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL2_MatchAction_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL2_MatchNextState_OFF (30) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL2_MatchNextState_WID ( 2) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL2_MatchNextState_MSK (0xC0000000) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL2_MatchNextState_MAX (0x00000003) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL2_MatchNextState_DEF (0x00000000) + +#define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL3_REG (0x00004370) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL3_InputMatch_OFF ( 0) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL3_InputMatch_WID ( 4) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL3_InputMatch_MSK (0x0000000F) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL3_InputMatch_MAX (0x0000000F) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL3_InputMatch_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL3_InputInvert_OFF ( 4) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL3_InputInvert_WID ( 4) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL3_InputInvert_MSK (0x000000F0) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL3_InputInvert_MAX (0x0000000F) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL3_InputInvert_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL3_CountMatches_OFF ( 8) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL3_CountMatches_WID ( 1) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL3_CountMatches_MSK (0x00000100) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL3_CountMatches_MAX (0x00000001) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL3_CountMatches_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL3_CounterThreshold_OFF ( 9) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL3_CounterThreshold_WID (15) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL3_CounterThreshold_MSK (0x00FFFE00) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL3_CounterThreshold_MAX (0x00007FFF) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL3_CounterThreshold_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL3_CounterAction_OFF (24) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL3_CounterAction_WID ( 2) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL3_CounterAction_MSK (0x03000000) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL3_CounterAction_MAX (0x00000003) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL3_CounterAction_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL3_CounterNextState_OFF (26) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL3_CounterNextState_WID ( 2) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL3_CounterNextState_MSK (0x0C000000) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL3_CounterNextState_MAX (0x00000003) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL3_CounterNextState_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL3_MatchAction_OFF (28) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL3_MatchAction_WID ( 2) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL3_MatchAction_MSK (0x30000000) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL3_MatchAction_MAX (0x00000003) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL3_MatchAction_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL3_MatchNextState_OFF (30) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL3_MatchNextState_WID ( 2) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL3_MatchNextState_MSK (0xC0000000) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL3_MatchNextState_MAX (0x00000003) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL3_MatchNextState_DEF (0x00000000) + +#define MCHBAR_CH0_CR_ODLAT_SEQ_GLOBAL_REG (0x00004374) + #define MCHBAR_CH0_CR_ODLAT_SEQ_GLOBAL_TriggerBlockEnable_OFF ( 0) + #define MCHBAR_CH0_CR_ODLAT_SEQ_GLOBAL_TriggerBlockEnable_WID ( 1) + #define MCHBAR_CH0_CR_ODLAT_SEQ_GLOBAL_TriggerBlockEnable_MSK (0x00000001) + #define MCHBAR_CH0_CR_ODLAT_SEQ_GLOBAL_TriggerBlockEnable_MAX (0x00000001) + #define MCHBAR_CH0_CR_ODLAT_SEQ_GLOBAL_TriggerBlockEnable_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_SEQ_GLOBAL_GlobalCounterThreshold_OFF ( 1) + #define MCHBAR_CH0_CR_ODLAT_SEQ_GLOBAL_GlobalCounterThreshold_WID (16) + #define MCHBAR_CH0_CR_ODLAT_SEQ_GLOBAL_GlobalCounterThreshold_MSK (0x0001FFFE) + #define MCHBAR_CH0_CR_ODLAT_SEQ_GLOBAL_GlobalCounterThreshold_MAX (0x0000FFFF) + #define MCHBAR_CH0_CR_ODLAT_SEQ_GLOBAL_GlobalCounterThreshold_DEF (0x00000000) + +#define MCHBAR_CH0_CR_SC_WDBWM_REG (0x0000438C) + #define MCHBAR_CH0_CR_SC_WDBWM_WMM_Enter_OFF ( 0) + #define MCHBAR_CH0_CR_SC_WDBWM_WMM_Enter_WID ( 8) + #define MCHBAR_CH0_CR_SC_WDBWM_WMM_Enter_MSK (0x000000FF) + #define MCHBAR_CH0_CR_SC_WDBWM_WMM_Enter_MAX (0x000000FF) + #define MCHBAR_CH0_CR_SC_WDBWM_WMM_Enter_DEF (0x00000038) + #define MCHBAR_CH0_CR_SC_WDBWM_WMM_Exit_OFF ( 8) + #define MCHBAR_CH0_CR_SC_WDBWM_WMM_Exit_WID ( 8) + #define MCHBAR_CH0_CR_SC_WDBWM_WMM_Exit_MSK (0x0000FF00) + #define MCHBAR_CH0_CR_SC_WDBWM_WMM_Exit_MAX (0x000000FF) + #define MCHBAR_CH0_CR_SC_WDBWM_WMM_Exit_DEF (0x00000030) + #define MCHBAR_CH0_CR_SC_WDBWM_WPQ_IS_OFF (16) + #define MCHBAR_CH0_CR_SC_WDBWM_WPQ_IS_WID ( 8) + #define MCHBAR_CH0_CR_SC_WDBWM_WPQ_IS_MSK (0x00FF0000) + #define MCHBAR_CH0_CR_SC_WDBWM_WPQ_IS_MAX (0x000000FF) + #define MCHBAR_CH0_CR_SC_WDBWM_WPQ_IS_DEF (0x0000003C) + #define MCHBAR_CH0_CR_SC_WDBWM_Starve_count_OFF (24) + #define MCHBAR_CH0_CR_SC_WDBWM_Starve_count_WID ( 8) + #define MCHBAR_CH0_CR_SC_WDBWM_Starve_count_MSK (0xFF000000) + #define MCHBAR_CH0_CR_SC_WDBWM_Starve_count_MAX (0x000000FF) + #define MCHBAR_CH0_CR_SC_WDBWM_Starve_count_DEF (0x000000FF) + +#define MCHBAR_CH0_CR_VISA_CTL_MCMNTS_REG (0x00004390) + #define MCHBAR_CH0_CR_VISA_CTL_MCMNTS_Data_OFF ( 0) + #define MCHBAR_CH0_CR_VISA_CTL_MCMNTS_Data_WID (18) + #define MCHBAR_CH0_CR_VISA_CTL_MCMNTS_Data_MSK (0x0003FFFF) + #define MCHBAR_CH0_CR_VISA_CTL_MCMNTS_Data_MAX (0x0003FFFF) + #define MCHBAR_CH0_CR_VISA_CTL_MCMNTS_Data_DEF (0x00000000) + #define MCHBAR_CH0_CR_VISA_CTL_MCMNTS_VORANGE_OFF (31) + #define MCHBAR_CH0_CR_VISA_CTL_MCMNTS_VORANGE_WID ( 1) + #define MCHBAR_CH0_CR_VISA_CTL_MCMNTS_VORANGE_MSK (0x80000000) + #define MCHBAR_CH0_CR_VISA_CTL_MCMNTS_VORANGE_MAX (0x00000001) + #define MCHBAR_CH0_CR_VISA_CTL_MCMNTS_VORANGE_DEF (0x00000000) + +#define MCHBAR_CH1_CR_TC_BANK_REG (0x00004400) + #define MCHBAR_CH1_CR_TC_BANK_tRCD_OFF ( 0) + #define MCHBAR_CH1_CR_TC_BANK_tRCD_WID ( 5) + #define MCHBAR_CH1_CR_TC_BANK_tRCD_MSK (0x0000001F) + #define MCHBAR_CH1_CR_TC_BANK_tRCD_MAX (0x0000001F) + #define MCHBAR_CH1_CR_TC_BANK_tRCD_DEF (0x00000006) + #define MCHBAR_CH1_CR_TC_BANK_tRP_OFF ( 5) + #define MCHBAR_CH1_CR_TC_BANK_tRP_WID ( 5) + #define MCHBAR_CH1_CR_TC_BANK_tRP_MSK (0x000003E0) + #define MCHBAR_CH1_CR_TC_BANK_tRP_MAX (0x0000001F) + #define MCHBAR_CH1_CR_TC_BANK_tRP_DEF (0x00000006) + #define MCHBAR_CH1_CR_TC_BANK_tRAS_OFF (10) + #define MCHBAR_CH1_CR_TC_BANK_tRAS_WID ( 6) + #define MCHBAR_CH1_CR_TC_BANK_tRAS_MSK (0x0000FC00) + #define MCHBAR_CH1_CR_TC_BANK_tRAS_MAX (0x0000003F) + #define MCHBAR_CH1_CR_TC_BANK_tRAS_DEF (0x00000014) + #define MCHBAR_CH1_CR_TC_BANK_tRDPRE_OFF (16) + #define MCHBAR_CH1_CR_TC_BANK_tRDPRE_WID ( 4) + #define MCHBAR_CH1_CR_TC_BANK_tRDPRE_MSK (0x000F0000) + #define MCHBAR_CH1_CR_TC_BANK_tRDPRE_MAX (0x0000000F) + #define MCHBAR_CH1_CR_TC_BANK_tRDPRE_DEF (0x00000004) + #define MCHBAR_CH1_CR_TC_BANK_tWRPRE_OFF (20) + #define MCHBAR_CH1_CR_TC_BANK_tWRPRE_WID ( 6) + #define MCHBAR_CH1_CR_TC_BANK_tWRPRE_MSK (0x03F00000) + #define MCHBAR_CH1_CR_TC_BANK_tWRPRE_MAX (0x0000003F) + #define MCHBAR_CH1_CR_TC_BANK_tWRPRE_DEF (0x00000004) + #define MCHBAR_CH1_CR_TC_BANK_tRRD_OFF (26) + #define MCHBAR_CH1_CR_TC_BANK_tRRD_WID ( 4) + #define MCHBAR_CH1_CR_TC_BANK_tRRD_MSK (0x3C000000) + #define MCHBAR_CH1_CR_TC_BANK_tRRD_MAX (0x0000000F) + #define MCHBAR_CH1_CR_TC_BANK_tRRD_DEF (0x00000004) + #define MCHBAR_CH1_CR_TC_BANK_tRPab_ext_OFF (30) + #define MCHBAR_CH1_CR_TC_BANK_tRPab_ext_WID ( 2) + #define MCHBAR_CH1_CR_TC_BANK_tRPab_ext_MSK (0xC0000000) + #define MCHBAR_CH1_CR_TC_BANK_tRPab_ext_MAX (0x00000003) + #define MCHBAR_CH1_CR_TC_BANK_tRPab_ext_DEF (0x00000000) + +#define MCHBAR_CH1_CR_TC_BANK_RANK_A_REG (0x00004404) + #define MCHBAR_CH1_CR_TC_BANK_RANK_A_tCKE_OFF ( 0) + #define MCHBAR_CH1_CR_TC_BANK_RANK_A_tCKE_WID ( 4) + #define MCHBAR_CH1_CR_TC_BANK_RANK_A_tCKE_MSK (0x0000000F) + #define MCHBAR_CH1_CR_TC_BANK_RANK_A_tCKE_MAX (0x0000000F) + #define MCHBAR_CH1_CR_TC_BANK_RANK_A_tCKE_DEF (0x00000003) + #define MCHBAR_CH1_CR_TC_BANK_RANK_A_tFAW_OFF ( 4) + #define MCHBAR_CH1_CR_TC_BANK_RANK_A_tFAW_WID ( 8) + #define MCHBAR_CH1_CR_TC_BANK_RANK_A_tFAW_MSK (0x00000FF0) + #define MCHBAR_CH1_CR_TC_BANK_RANK_A_tFAW_MAX (0x000000FF) + #define MCHBAR_CH1_CR_TC_BANK_RANK_A_tFAW_DEF (0x00000010) + #define MCHBAR_CH1_CR_TC_BANK_RANK_A_tRDRD_OFF (12) + #define MCHBAR_CH1_CR_TC_BANK_RANK_A_tRDRD_WID ( 3) + #define MCHBAR_CH1_CR_TC_BANK_RANK_A_tRDRD_MSK (0x00007000) + #define MCHBAR_CH1_CR_TC_BANK_RANK_A_tRDRD_MAX (0x00000007) + #define MCHBAR_CH1_CR_TC_BANK_RANK_A_tRDRD_DEF (0x00000004) + #define MCHBAR_CH1_CR_TC_BANK_RANK_A_tRDRD_dr_OFF (15) + #define MCHBAR_CH1_CR_TC_BANK_RANK_A_tRDRD_dr_WID ( 4) + #define MCHBAR_CH1_CR_TC_BANK_RANK_A_tRDRD_dr_MSK (0x00078000) + #define MCHBAR_CH1_CR_TC_BANK_RANK_A_tRDRD_dr_MAX (0x0000000F) + #define MCHBAR_CH1_CR_TC_BANK_RANK_A_tRDRD_dr_DEF (0x00000004) + #define MCHBAR_CH1_CR_TC_BANK_RANK_A_tRDRD_dd_OFF (19) + #define MCHBAR_CH1_CR_TC_BANK_RANK_A_tRDRD_dd_WID ( 4) + #define MCHBAR_CH1_CR_TC_BANK_RANK_A_tRDRD_dd_MSK (0x00780000) + #define MCHBAR_CH1_CR_TC_BANK_RANK_A_tRDRD_dd_MAX (0x0000000F) + #define MCHBAR_CH1_CR_TC_BANK_RANK_A_tRDRD_dd_DEF (0x00000004) + #define MCHBAR_CH1_CR_TC_BANK_RANK_A_tRDPDEN_OFF (23) + #define MCHBAR_CH1_CR_TC_BANK_RANK_A_tRDPDEN_WID ( 5) + #define MCHBAR_CH1_CR_TC_BANK_RANK_A_tRDPDEN_MSK (0x0F800000) + #define MCHBAR_CH1_CR_TC_BANK_RANK_A_tRDPDEN_MAX (0x0000001F) + #define MCHBAR_CH1_CR_TC_BANK_RANK_A_tRDPDEN_DEF (0x00000004) + #define MCHBAR_CH1_CR_TC_BANK_RANK_A_CMD_3st_OFF (29) + #define MCHBAR_CH1_CR_TC_BANK_RANK_A_CMD_3st_WID ( 1) + #define MCHBAR_CH1_CR_TC_BANK_RANK_A_CMD_3st_MSK (0x20000000) + #define MCHBAR_CH1_CR_TC_BANK_RANK_A_CMD_3st_MAX (0x00000001) + #define MCHBAR_CH1_CR_TC_BANK_RANK_A_CMD_3st_DEF (0x00000000) + #define MCHBAR_CH1_CR_TC_BANK_RANK_A_CMD_stretch_OFF (30) + #define MCHBAR_CH1_CR_TC_BANK_RANK_A_CMD_stretch_WID ( 2) + #define MCHBAR_CH1_CR_TC_BANK_RANK_A_CMD_stretch_MSK (0xC0000000) + #define MCHBAR_CH1_CR_TC_BANK_RANK_A_CMD_stretch_MAX (0x00000003) + #define MCHBAR_CH1_CR_TC_BANK_RANK_A_CMD_stretch_DEF (0x00000002) + +#define MCHBAR_CH1_CR_TC_BANK_RANK_B_REG (0x00004408) + #define MCHBAR_CH1_CR_TC_BANK_RANK_B_tWRRD_OFF ( 0) + #define MCHBAR_CH1_CR_TC_BANK_RANK_B_tWRRD_WID ( 6) + #define MCHBAR_CH1_CR_TC_BANK_RANK_B_tWRRD_MSK (0x0000003F) + #define MCHBAR_CH1_CR_TC_BANK_RANK_B_tWRRD_MAX (0x0000003F) + #define MCHBAR_CH1_CR_TC_BANK_RANK_B_tWRRD_DEF (0x00000005) + #define MCHBAR_CH1_CR_TC_BANK_RANK_B_tWRRD_dr_OFF ( 6) + #define MCHBAR_CH1_CR_TC_BANK_RANK_B_tWRRD_dr_WID ( 4) + #define MCHBAR_CH1_CR_TC_BANK_RANK_B_tWRRD_dr_MSK (0x000003C0) + #define MCHBAR_CH1_CR_TC_BANK_RANK_B_tWRRD_dr_MAX (0x0000000F) + #define MCHBAR_CH1_CR_TC_BANK_RANK_B_tWRRD_dr_DEF (0x00000005) + #define MCHBAR_CH1_CR_TC_BANK_RANK_B_tWRRD_dd_OFF (10) + #define MCHBAR_CH1_CR_TC_BANK_RANK_B_tWRRD_dd_WID ( 4) + #define MCHBAR_CH1_CR_TC_BANK_RANK_B_tWRRD_dd_MSK (0x00003C00) + #define MCHBAR_CH1_CR_TC_BANK_RANK_B_tWRRD_dd_MAX (0x0000000F) + #define MCHBAR_CH1_CR_TC_BANK_RANK_B_tWRRD_dd_DEF (0x00000005) + #define MCHBAR_CH1_CR_TC_BANK_RANK_B_tWRWR_OFF (14) + #define MCHBAR_CH1_CR_TC_BANK_RANK_B_tWRWR_WID ( 3) + #define MCHBAR_CH1_CR_TC_BANK_RANK_B_tWRWR_MSK (0x0001C000) + #define MCHBAR_CH1_CR_TC_BANK_RANK_B_tWRWR_MAX (0x00000007) + #define MCHBAR_CH1_CR_TC_BANK_RANK_B_tWRWR_DEF (0x00000005) + #define MCHBAR_CH1_CR_TC_BANK_RANK_B_tWRWR_dr_OFF (17) + #define MCHBAR_CH1_CR_TC_BANK_RANK_B_tWRWR_dr_WID ( 4) + #define MCHBAR_CH1_CR_TC_BANK_RANK_B_tWRWR_dr_MSK (0x001E0000) + #define MCHBAR_CH1_CR_TC_BANK_RANK_B_tWRWR_dr_MAX (0x0000000F) + #define MCHBAR_CH1_CR_TC_BANK_RANK_B_tWRWR_dr_DEF (0x00000005) + #define MCHBAR_CH1_CR_TC_BANK_RANK_B_tWRWR_dd_OFF (21) + #define MCHBAR_CH1_CR_TC_BANK_RANK_B_tWRWR_dd_WID ( 4) + #define MCHBAR_CH1_CR_TC_BANK_RANK_B_tWRWR_dd_MSK (0x01E00000) + #define MCHBAR_CH1_CR_TC_BANK_RANK_B_tWRWR_dd_MAX (0x0000000F) + #define MCHBAR_CH1_CR_TC_BANK_RANK_B_tWRWR_dd_DEF (0x00000005) + #define MCHBAR_CH1_CR_TC_BANK_RANK_B_tWRPDEN_OFF (25) + #define MCHBAR_CH1_CR_TC_BANK_RANK_B_tWRPDEN_WID ( 6) + #define MCHBAR_CH1_CR_TC_BANK_RANK_B_tWRPDEN_MSK (0x7E000000) + #define MCHBAR_CH1_CR_TC_BANK_RANK_B_tWRPDEN_MAX (0x0000003F) + #define MCHBAR_CH1_CR_TC_BANK_RANK_B_tWRPDEN_DEF (0x00000005) + #define MCHBAR_CH1_CR_TC_BANK_RANK_B_Dec_WRD_OFF (31) + #define MCHBAR_CH1_CR_TC_BANK_RANK_B_Dec_WRD_WID ( 1) + #define MCHBAR_CH1_CR_TC_BANK_RANK_B_Dec_WRD_MSK (0x80000000) + #define MCHBAR_CH1_CR_TC_BANK_RANK_B_Dec_WRD_MAX (0x00000001) + #define MCHBAR_CH1_CR_TC_BANK_RANK_B_Dec_WRD_DEF (0x00000000) + +#define MCHBAR_CH1_CR_TC_BANK_RANK_C_REG (0x0000440C) + #define MCHBAR_CH1_CR_TC_BANK_RANK_C_tXPDLL_OFF ( 0) + #define MCHBAR_CH1_CR_TC_BANK_RANK_C_tXPDLL_WID ( 6) + #define MCHBAR_CH1_CR_TC_BANK_RANK_C_tXPDLL_MSK (0x0000003F) + #define MCHBAR_CH1_CR_TC_BANK_RANK_C_tXPDLL_MAX (0x0000003F) + #define MCHBAR_CH1_CR_TC_BANK_RANK_C_tXPDLL_DEF (0x0000000A) + #define MCHBAR_CH1_CR_TC_BANK_RANK_C_tXP_OFF ( 6) + #define MCHBAR_CH1_CR_TC_BANK_RANK_C_tXP_WID ( 4) + #define MCHBAR_CH1_CR_TC_BANK_RANK_C_tXP_MSK (0x000003C0) + #define MCHBAR_CH1_CR_TC_BANK_RANK_C_tXP_MAX (0x0000000F) + #define MCHBAR_CH1_CR_TC_BANK_RANK_C_tXP_DEF (0x00000003) + #define MCHBAR_CH1_CR_TC_BANK_RANK_C_TAONPD_OFF (10) + #define MCHBAR_CH1_CR_TC_BANK_RANK_C_TAONPD_WID ( 4) + #define MCHBAR_CH1_CR_TC_BANK_RANK_C_TAONPD_MSK (0x00003C00) + #define MCHBAR_CH1_CR_TC_BANK_RANK_C_TAONPD_MAX (0x0000000F) + #define MCHBAR_CH1_CR_TC_BANK_RANK_C_TAONPD_DEF (0x00000009) + #define MCHBAR_CH1_CR_TC_BANK_RANK_C_tRDWR_OFF (14) + #define MCHBAR_CH1_CR_TC_BANK_RANK_C_tRDWR_WID ( 5) + #define MCHBAR_CH1_CR_TC_BANK_RANK_C_tRDWR_MSK (0x0007C000) + #define MCHBAR_CH1_CR_TC_BANK_RANK_C_tRDWR_MAX (0x0000001F) + #define MCHBAR_CH1_CR_TC_BANK_RANK_C_tRDWR_DEF (0x00000005) + #define MCHBAR_CH1_CR_TC_BANK_RANK_C_tRDWR_dr_OFF (19) + #define MCHBAR_CH1_CR_TC_BANK_RANK_C_tRDWR_dr_WID ( 5) + #define MCHBAR_CH1_CR_TC_BANK_RANK_C_tRDWR_dr_MSK (0x00F80000) + #define MCHBAR_CH1_CR_TC_BANK_RANK_C_tRDWR_dr_MAX (0x0000001F) + #define MCHBAR_CH1_CR_TC_BANK_RANK_C_tRDWR_dr_DEF (0x00000005) + #define MCHBAR_CH1_CR_TC_BANK_RANK_C_tRDWR_dd_OFF (24) + #define MCHBAR_CH1_CR_TC_BANK_RANK_C_tRDWR_dd_WID ( 5) + #define MCHBAR_CH1_CR_TC_BANK_RANK_C_tRDWR_dd_MSK (0x1F000000) + #define MCHBAR_CH1_CR_TC_BANK_RANK_C_tRDWR_dd_MAX (0x0000001F) + #define MCHBAR_CH1_CR_TC_BANK_RANK_C_tRDWR_dd_DEF (0x00000005) + +#define MCHBAR_CH1_CR_CMD_RATE_REG (0x00004410) + #define MCHBAR_CH1_CR_CMD_RATE_enable_cmd_rate_limit_OFF ( 0) + #define MCHBAR_CH1_CR_CMD_RATE_enable_cmd_rate_limit_WID ( 1) + #define MCHBAR_CH1_CR_CMD_RATE_enable_cmd_rate_limit_MSK (0x00000001) + #define MCHBAR_CH1_CR_CMD_RATE_enable_cmd_rate_limit_MAX (0x00000001) + #define MCHBAR_CH1_CR_CMD_RATE_enable_cmd_rate_limit_DEF (0x00000000) + #define MCHBAR_CH1_CR_CMD_RATE_cmd_rate_limit_OFF ( 1) + #define MCHBAR_CH1_CR_CMD_RATE_cmd_rate_limit_WID ( 3) + #define MCHBAR_CH1_CR_CMD_RATE_cmd_rate_limit_MSK (0x0000000E) + #define MCHBAR_CH1_CR_CMD_RATE_cmd_rate_limit_MAX (0x00000007) + #define MCHBAR_CH1_CR_CMD_RATE_cmd_rate_limit_DEF (0x00000004) + #define MCHBAR_CH1_CR_CMD_RATE_reset_on_command_OFF ( 4) + #define MCHBAR_CH1_CR_CMD_RATE_reset_on_command_WID ( 4) + #define MCHBAR_CH1_CR_CMD_RATE_reset_on_command_MSK (0x000000F0) + #define MCHBAR_CH1_CR_CMD_RATE_reset_on_command_MAX (0x0000000F) + #define MCHBAR_CH1_CR_CMD_RATE_reset_on_command_DEF (0x00000000) + #define MCHBAR_CH1_CR_CMD_RATE_reset_delay_OFF ( 8) + #define MCHBAR_CH1_CR_CMD_RATE_reset_delay_WID ( 4) + #define MCHBAR_CH1_CR_CMD_RATE_reset_delay_MSK (0x00000F00) + #define MCHBAR_CH1_CR_CMD_RATE_reset_delay_MAX (0x0000000F) + #define MCHBAR_CH1_CR_CMD_RATE_reset_delay_DEF (0x00000000) + #define MCHBAR_CH1_CR_CMD_RATE_ck_to_cke_delay_OFF (12) + #define MCHBAR_CH1_CR_CMD_RATE_ck_to_cke_delay_WID ( 2) + #define MCHBAR_CH1_CR_CMD_RATE_ck_to_cke_delay_MSK (0x00003000) + #define MCHBAR_CH1_CR_CMD_RATE_ck_to_cke_delay_MAX (0x00000003) + #define MCHBAR_CH1_CR_CMD_RATE_ck_to_cke_delay_DEF (0x00000001) + #define MCHBAR_CH1_CR_CMD_RATE_spare_OFF (14) + #define MCHBAR_CH1_CR_CMD_RATE_spare_WID (17) + #define MCHBAR_CH1_CR_CMD_RATE_spare_MSK (0x7FFFC000) + #define MCHBAR_CH1_CR_CMD_RATE_spare_MAX (0x0001FFFF) + #define MCHBAR_CH1_CR_CMD_RATE_spare_DEF (0x00000000) + #define MCHBAR_CH1_CR_CMD_RATE_init_mrw_2n_cs_OFF (31) + #define MCHBAR_CH1_CR_CMD_RATE_init_mrw_2n_cs_WID ( 1) + #define MCHBAR_CH1_CR_CMD_RATE_init_mrw_2n_cs_MSK (0x80000000) + #define MCHBAR_CH1_CR_CMD_RATE_init_mrw_2n_cs_MAX (0x00000001) + #define MCHBAR_CH1_CR_CMD_RATE_init_mrw_2n_cs_DEF (0x00000000) + +#define MCHBAR_CH1_CR_TC_BANK_RANK_D_REG (0x00004414) + #define MCHBAR_CH1_CR_TC_BANK_RANK_D_tCL_OFF ( 0) + #define MCHBAR_CH1_CR_TC_BANK_RANK_D_tCL_WID ( 5) + #define MCHBAR_CH1_CR_TC_BANK_RANK_D_tCL_MSK (0x0000001F) + #define MCHBAR_CH1_CR_TC_BANK_RANK_D_tCL_MAX (0x0000001F) + #define MCHBAR_CH1_CR_TC_BANK_RANK_D_tCL_DEF (0x00000006) + #define MCHBAR_CH1_CR_TC_BANK_RANK_D_tWCL_OFF ( 5) + #define MCHBAR_CH1_CR_TC_BANK_RANK_D_tWCL_WID ( 5) + #define MCHBAR_CH1_CR_TC_BANK_RANK_D_tWCL_MSK (0x000003E0) + #define MCHBAR_CH1_CR_TC_BANK_RANK_D_tWCL_MAX (0x0000001F) + #define MCHBAR_CH1_CR_TC_BANK_RANK_D_tWCL_DEF (0x00000006) + #define MCHBAR_CH1_CR_TC_BANK_RANK_D_tCPDED_OFF (10) + #define MCHBAR_CH1_CR_TC_BANK_RANK_D_tCPDED_WID ( 2) + #define MCHBAR_CH1_CR_TC_BANK_RANK_D_tCPDED_MSK (0x00000C00) + #define MCHBAR_CH1_CR_TC_BANK_RANK_D_tCPDED_MAX (0x00000003) + #define MCHBAR_CH1_CR_TC_BANK_RANK_D_tCPDED_DEF (0x00000001) + #define MCHBAR_CH1_CR_TC_BANK_RANK_D_tPRPDEN_OFF (12) + #define MCHBAR_CH1_CR_TC_BANK_RANK_D_tPRPDEN_WID ( 2) + #define MCHBAR_CH1_CR_TC_BANK_RANK_D_tPRPDEN_MSK (0x00003000) + #define MCHBAR_CH1_CR_TC_BANK_RANK_D_tPRPDEN_MAX (0x00000003) + #define MCHBAR_CH1_CR_TC_BANK_RANK_D_tPRPDEN_DEF (0x00000001) + #define MCHBAR_CH1_CR_TC_BANK_RANK_D_Odt_Read_Delay_OFF (14) + #define MCHBAR_CH1_CR_TC_BANK_RANK_D_Odt_Read_Delay_WID ( 3) + #define MCHBAR_CH1_CR_TC_BANK_RANK_D_Odt_Read_Delay_MSK (0x0001C000) + #define MCHBAR_CH1_CR_TC_BANK_RANK_D_Odt_Read_Delay_MAX (0x00000007) + #define MCHBAR_CH1_CR_TC_BANK_RANK_D_Odt_Read_Delay_DEF (0x00000000) + #define MCHBAR_CH1_CR_TC_BANK_RANK_D_Odt_Read_Duration_OFF (17) + #define MCHBAR_CH1_CR_TC_BANK_RANK_D_Odt_Read_Duration_WID ( 2) + #define MCHBAR_CH1_CR_TC_BANK_RANK_D_Odt_Read_Duration_MSK (0x00060000) + #define MCHBAR_CH1_CR_TC_BANK_RANK_D_Odt_Read_Duration_MAX (0x00000003) + #define MCHBAR_CH1_CR_TC_BANK_RANK_D_Odt_Read_Duration_DEF (0x00000000) + #define MCHBAR_CH1_CR_TC_BANK_RANK_D_Odt_Write_Duration_OFF (19) + #define MCHBAR_CH1_CR_TC_BANK_RANK_D_Odt_Write_Duration_WID ( 2) + #define MCHBAR_CH1_CR_TC_BANK_RANK_D_Odt_Write_Duration_MSK (0x00180000) + #define MCHBAR_CH1_CR_TC_BANK_RANK_D_Odt_Write_Duration_MAX (0x00000003) + #define MCHBAR_CH1_CR_TC_BANK_RANK_D_Odt_Write_Duration_DEF (0x00000000) + #define MCHBAR_CH1_CR_TC_BANK_RANK_D_Odt_Write_Duration_Ult_OFF (19) + #define MCHBAR_CH1_CR_TC_BANK_RANK_D_Odt_Write_Duration_Ult_WID ( 3) + #define MCHBAR_CH1_CR_TC_BANK_RANK_D_Odt_Write_Duration_Ult_MSK (0x00380000) + #define MCHBAR_CH1_CR_TC_BANK_RANK_D_Odt_Write_Duration_Ult_MAX (0x00000007) + #define MCHBAR_CH1_CR_TC_BANK_RANK_D_Odt_Write_Duration_Ult_DEF (0x00000000) + #define MCHBAR_CH1_CR_TC_BANK_RANK_D_Odt_Write_Delay_Ult_OFF (22) + #define MCHBAR_CH1_CR_TC_BANK_RANK_D_Odt_Write_Delay_Ult_WID ( 3) + #define MCHBAR_CH1_CR_TC_BANK_RANK_D_Odt_Write_Delay_Ult_MSK (0x01C00000) + #define MCHBAR_CH1_CR_TC_BANK_RANK_D_Odt_Write_Delay_Ult_MAX (0x00000007) + #define MCHBAR_CH1_CR_TC_BANK_RANK_D_Odt_Write_Delay_Ult_DEF (0x00000000) + #define MCHBAR_CH1_CR_TC_BANK_RANK_D_Odt_Always_Rank0_Ult_OFF (25) + #define MCHBAR_CH1_CR_TC_BANK_RANK_D_Odt_Always_Rank0_Ult_WID ( 1) + #define MCHBAR_CH1_CR_TC_BANK_RANK_D_Odt_Always_Rank0_Ult_MSK (0x02000000) + #define MCHBAR_CH1_CR_TC_BANK_RANK_D_Odt_Always_Rank0_Ult_MAX (0x00000001) + #define MCHBAR_CH1_CR_TC_BANK_RANK_D_Odt_Always_Rank0_Ult_DEF (0x00000000) + #define MCHBAR_CH1_CR_TC_BANK_RANK_D_cmd_delay_Ult_OFF (26) + #define MCHBAR_CH1_CR_TC_BANK_RANK_D_cmd_delay_Ult_WID ( 2) + #define MCHBAR_CH1_CR_TC_BANK_RANK_D_cmd_delay_Ult_MSK (0x0C000000) + #define MCHBAR_CH1_CR_TC_BANK_RANK_D_cmd_delay_Ult_MAX (0x00000003) + #define MCHBAR_CH1_CR_TC_BANK_RANK_D_cmd_delay_Ult_DEF (0x00000000) + +#define MCHBAR_CH1_CR_SCHED_CBIT_REG (0x00004420) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_opp_cas_OFF ( 0) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_opp_cas_WID ( 1) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_opp_cas_MSK (0x00000001) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_opp_cas_MAX (0x00000001) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_opp_cas_DEF (0x00000001) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_opp_is_cas_OFF ( 1) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_opp_is_cas_WID ( 1) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_opp_is_cas_MSK (0x00000002) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_opp_is_cas_MAX (0x00000001) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_opp_is_cas_DEF (0x00000000) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_opp_ras_OFF ( 2) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_opp_ras_WID ( 1) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_opp_ras_MSK (0x00000004) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_opp_ras_MAX (0x00000001) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_opp_ras_DEF (0x00000001) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_opp_is_ras_OFF ( 3) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_opp_is_ras_WID ( 1) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_opp_is_ras_MSK (0x00000008) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_opp_is_ras_MAX (0x00000001) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_opp_is_ras_DEF (0x00000000) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_1c_byp_OFF ( 4) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_1c_byp_WID ( 1) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_1c_byp_MSK (0x00000010) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_1c_byp_MAX (0x00000001) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_1c_byp_DEF (0x00000001) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_2c_byp_OFF ( 5) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_2c_byp_WID ( 1) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_2c_byp_MSK (0x00000020) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_2c_byp_MAX (0x00000001) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_2c_byp_DEF (0x00000000) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_deprd_opt_OFF ( 6) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_deprd_opt_WID ( 1) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_deprd_opt_MSK (0x00000040) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_deprd_opt_MAX (0x00000001) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_deprd_opt_DEF (0x00000000) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_pt_it_OFF ( 7) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_pt_it_WID ( 1) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_pt_it_MSK (0x00000080) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_pt_it_MAX (0x00000001) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_pt_it_DEF (0x00000000) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_prcnt_ring_OFF ( 8) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_prcnt_ring_WID ( 1) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_prcnt_ring_MSK (0x00000100) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_prcnt_ring_MAX (0x00000001) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_prcnt_ring_DEF (0x00000000) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_prcnt_sa_OFF ( 9) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_prcnt_sa_WID ( 1) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_prcnt_sa_MSK (0x00000200) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_prcnt_sa_MAX (0x00000001) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_prcnt_sa_DEF (0x00000000) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_blkr_ph_OFF (10) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_blkr_ph_WID ( 1) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_blkr_ph_MSK (0x00000400) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_blkr_ph_MAX (0x00000001) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_blkr_ph_DEF (0x00000000) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_blkr_pe_OFF (11) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_blkr_pe_WID ( 1) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_blkr_pe_MSK (0x00000800) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_blkr_pe_MAX (0x00000001) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_blkr_pe_DEF (0x00000000) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_blkr_pm_OFF (12) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_blkr_pm_WID ( 1) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_blkr_pm_MSK (0x00001000) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_blkr_pm_MAX (0x00000001) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_blkr_pm_DEF (0x00000000) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_odt_OFF (13) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_odt_WID ( 1) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_odt_MSK (0x00002000) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_odt_MAX (0x00000001) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_odt_DEF (0x00000000) + #define MCHBAR_CH1_CR_SCHED_CBIT_OE_alw_off_OFF (14) + #define MCHBAR_CH1_CR_SCHED_CBIT_OE_alw_off_WID ( 1) + #define MCHBAR_CH1_CR_SCHED_CBIT_OE_alw_off_MSK (0x00004000) + #define MCHBAR_CH1_CR_SCHED_CBIT_OE_alw_off_MAX (0x00000001) + #define MCHBAR_CH1_CR_SCHED_CBIT_OE_alw_off_DEF (0x00000000) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_aom_OFF (16) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_aom_WID ( 1) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_aom_MSK (0x00010000) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_aom_MAX (0x00000001) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_aom_DEF (0x00000000) + #define MCHBAR_CH1_CR_SCHED_CBIT_block_rpq_OFF (17) + #define MCHBAR_CH1_CR_SCHED_CBIT_block_rpq_WID ( 1) + #define MCHBAR_CH1_CR_SCHED_CBIT_block_rpq_MSK (0x00020000) + #define MCHBAR_CH1_CR_SCHED_CBIT_block_rpq_MAX (0x00000001) + #define MCHBAR_CH1_CR_SCHED_CBIT_block_rpq_DEF (0x00000000) + #define MCHBAR_CH1_CR_SCHED_CBIT_block_wpq_OFF (18) + #define MCHBAR_CH1_CR_SCHED_CBIT_block_wpq_WID ( 1) + #define MCHBAR_CH1_CR_SCHED_CBIT_block_wpq_MSK (0x00040000) + #define MCHBAR_CH1_CR_SCHED_CBIT_block_wpq_MAX (0x00000001) + #define MCHBAR_CH1_CR_SCHED_CBIT_block_wpq_DEF (0x00000000) + #define MCHBAR_CH1_CR_SCHED_CBIT_invert_align_OFF (19) + #define MCHBAR_CH1_CR_SCHED_CBIT_invert_align_WID ( 1) + #define MCHBAR_CH1_CR_SCHED_CBIT_invert_align_MSK (0x00080000) + #define MCHBAR_CH1_CR_SCHED_CBIT_invert_align_MAX (0x00000001) + #define MCHBAR_CH1_CR_SCHED_CBIT_invert_align_DEF (0x00000000) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_write_gap_OFF (20) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_write_gap_WID ( 1) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_write_gap_MSK (0x00100000) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_write_gap_MAX (0x00000001) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_write_gap_DEF (0x00000001) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_zq_OFF (21) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_zq_WID ( 1) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_zq_MSK (0x00200000) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_zq_MAX (0x00000001) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_zq_DEF (0x00000000) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_tt_OFF (22) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_tt_WID ( 1) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_tt_MSK (0x00400000) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_tt_MAX (0x00000001) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_tt_DEF (0x00000000) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_opp_ref_OFF (23) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_opp_ref_WID ( 1) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_opp_ref_MSK (0x00800000) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_opp_ref_MAX (0x00000001) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_opp_ref_DEF (0x00000000) + #define MCHBAR_CH1_CR_SCHED_CBIT_Long_ZQ_OFF (24) + #define MCHBAR_CH1_CR_SCHED_CBIT_Long_ZQ_WID ( 1) + #define MCHBAR_CH1_CR_SCHED_CBIT_Long_ZQ_MSK (0x01000000) + #define MCHBAR_CH1_CR_SCHED_CBIT_Long_ZQ_MAX (0x00000001) + #define MCHBAR_CH1_CR_SCHED_CBIT_Long_ZQ_DEF (0x00000000) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_srx_zq_OFF (25) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_srx_zq_WID ( 1) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_srx_zq_MSK (0x02000000) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_srx_zq_MAX (0x00000001) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_srx_zq_DEF (0x00000000) + #define MCHBAR_CH1_CR_SCHED_CBIT_Serialize_ZQ_OFF (26) + #define MCHBAR_CH1_CR_SCHED_CBIT_Serialize_ZQ_WID ( 1) + #define MCHBAR_CH1_CR_SCHED_CBIT_Serialize_ZQ_MSK (0x04000000) + #define MCHBAR_CH1_CR_SCHED_CBIT_Serialize_ZQ_MAX (0x00000001) + #define MCHBAR_CH1_CR_SCHED_CBIT_Serialize_ZQ_DEF (0x00000000) + #define MCHBAR_CH1_CR_SCHED_CBIT_ZQ_fast_exec_OFF (27) + #define MCHBAR_CH1_CR_SCHED_CBIT_ZQ_fast_exec_WID ( 1) + #define MCHBAR_CH1_CR_SCHED_CBIT_ZQ_fast_exec_MSK (0x08000000) + #define MCHBAR_CH1_CR_SCHED_CBIT_ZQ_fast_exec_MAX (0x00000001) + #define MCHBAR_CH1_CR_SCHED_CBIT_ZQ_fast_exec_DEF (0x00000000) + #define MCHBAR_CH1_CR_SCHED_CBIT_Dis_DriveNop_OFF (28) + #define MCHBAR_CH1_CR_SCHED_CBIT_Dis_DriveNop_WID ( 1) + #define MCHBAR_CH1_CR_SCHED_CBIT_Dis_DriveNop_MSK (0x10000000) + #define MCHBAR_CH1_CR_SCHED_CBIT_Dis_DriveNop_MAX (0x00000001) + #define MCHBAR_CH1_CR_SCHED_CBIT_Dis_DriveNop_DEF (0x00000000) + #define MCHBAR_CH1_CR_SCHED_CBIT_Pres_WDB_Ent_OFF (29) + #define MCHBAR_CH1_CR_SCHED_CBIT_Pres_WDB_Ent_WID ( 1) + #define MCHBAR_CH1_CR_SCHED_CBIT_Pres_WDB_Ent_MSK (0x20000000) + #define MCHBAR_CH1_CR_SCHED_CBIT_Pres_WDB_Ent_MAX (0x00000001) + #define MCHBAR_CH1_CR_SCHED_CBIT_Pres_WDB_Ent_DEF (0x00000000) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_clk_gate_OFF (30) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_clk_gate_WID ( 1) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_clk_gate_MSK (0x40000000) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_clk_gate_MAX (0x00000001) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_clk_gate_DEF (0x00000000) + +#define MCHBAR_CH1_CR_SC_ROUNDT_LAT_REG (0x00004424) + #define MCHBAR_CH1_CR_SC_ROUNDT_LAT_Lat_R0D0_OFF ( 0) + #define MCHBAR_CH1_CR_SC_ROUNDT_LAT_Lat_R0D0_WID ( 6) + #define MCHBAR_CH1_CR_SC_ROUNDT_LAT_Lat_R0D0_MSK (0x0000003F) + #define MCHBAR_CH1_CR_SC_ROUNDT_LAT_Lat_R0D0_MAX (0x0000003F) + #define MCHBAR_CH1_CR_SC_ROUNDT_LAT_Lat_R0D0_DEF (0x00000020) + #define MCHBAR_CH1_CR_SC_ROUNDT_LAT_Lat_R1D0_OFF ( 8) + #define MCHBAR_CH1_CR_SC_ROUNDT_LAT_Lat_R1D0_WID ( 6) + #define MCHBAR_CH1_CR_SC_ROUNDT_LAT_Lat_R1D0_MSK (0x00003F00) + #define MCHBAR_CH1_CR_SC_ROUNDT_LAT_Lat_R1D0_MAX (0x0000003F) + #define MCHBAR_CH1_CR_SC_ROUNDT_LAT_Lat_R1D0_DEF (0x00000020) + #define MCHBAR_CH1_CR_SC_ROUNDT_LAT_Lat_R0D1_OFF (16) + #define MCHBAR_CH1_CR_SC_ROUNDT_LAT_Lat_R0D1_WID ( 6) + #define MCHBAR_CH1_CR_SC_ROUNDT_LAT_Lat_R0D1_MSK (0x003F0000) + #define MCHBAR_CH1_CR_SC_ROUNDT_LAT_Lat_R0D1_MAX (0x0000003F) + #define MCHBAR_CH1_CR_SC_ROUNDT_LAT_Lat_R0D1_DEF (0x00000020) + #define MCHBAR_CH1_CR_SC_ROUNDT_LAT_Lat_R1D1_OFF (24) + #define MCHBAR_CH1_CR_SC_ROUNDT_LAT_Lat_R1D1_WID ( 6) + #define MCHBAR_CH1_CR_SC_ROUNDT_LAT_Lat_R1D1_MSK (0x3F000000) + #define MCHBAR_CH1_CR_SC_ROUNDT_LAT_Lat_R1D1_MAX (0x0000003F) + #define MCHBAR_CH1_CR_SC_ROUNDT_LAT_Lat_R1D1_DEF (0x00000020) + +#define MCHBAR_CH1_CR_SC_IO_LATENCY_REG (0x00004428) + #define MCHBAR_CH1_CR_SC_IO_LATENCY_IOLAT_R0D0_OFF ( 0) + #define MCHBAR_CH1_CR_SC_IO_LATENCY_IOLAT_R0D0_WID ( 4) + #define MCHBAR_CH1_CR_SC_IO_LATENCY_IOLAT_R0D0_MSK (0x0000000F) + #define MCHBAR_CH1_CR_SC_IO_LATENCY_IOLAT_R0D0_MAX (0x0000000F) + #define MCHBAR_CH1_CR_SC_IO_LATENCY_IOLAT_R0D0_DEF (0x00000000) + #define MCHBAR_CH1_CR_SC_IO_LATENCY_IOLAT_R1D0_OFF ( 4) + #define MCHBAR_CH1_CR_SC_IO_LATENCY_IOLAT_R1D0_WID ( 4) + #define MCHBAR_CH1_CR_SC_IO_LATENCY_IOLAT_R1D0_MSK (0x000000F0) + #define MCHBAR_CH1_CR_SC_IO_LATENCY_IOLAT_R1D0_MAX (0x0000000F) + #define MCHBAR_CH1_CR_SC_IO_LATENCY_IOLAT_R1D0_DEF (0x00000000) + #define MCHBAR_CH1_CR_SC_IO_LATENCY_IOLAT_R0D1_OFF ( 8) + #define MCHBAR_CH1_CR_SC_IO_LATENCY_IOLAT_R0D1_WID ( 4) + #define MCHBAR_CH1_CR_SC_IO_LATENCY_IOLAT_R0D1_MSK (0x00000F00) + #define MCHBAR_CH1_CR_SC_IO_LATENCY_IOLAT_R0D1_MAX (0x0000000F) + #define MCHBAR_CH1_CR_SC_IO_LATENCY_IOLAT_R0D1_DEF (0x00000000) + #define MCHBAR_CH1_CR_SC_IO_LATENCY_IOLAT_R1D1_OFF (12) + #define MCHBAR_CH1_CR_SC_IO_LATENCY_IOLAT_R1D1_WID ( 4) + #define MCHBAR_CH1_CR_SC_IO_LATENCY_IOLAT_R1D1_MSK (0x0000F000) + #define MCHBAR_CH1_CR_SC_IO_LATENCY_IOLAT_R1D1_MAX (0x0000000F) + #define MCHBAR_CH1_CR_SC_IO_LATENCY_IOLAT_R1D1_DEF (0x00000000) + #define MCHBAR_CH1_CR_SC_IO_LATENCY_RT_IOCOMP_OFF (16) + #define MCHBAR_CH1_CR_SC_IO_LATENCY_RT_IOCOMP_WID ( 6) + #define MCHBAR_CH1_CR_SC_IO_LATENCY_RT_IOCOMP_MSK (0x003F0000) + #define MCHBAR_CH1_CR_SC_IO_LATENCY_RT_IOCOMP_MAX (0x0000003F) + #define MCHBAR_CH1_CR_SC_IO_LATENCY_RT_IOCOMP_DEF (0x0000000E) + #define MCHBAR_CH1_CR_SC_IO_LATENCY_three_channels_OFF (30) + #define MCHBAR_CH1_CR_SC_IO_LATENCY_three_channels_WID ( 1) + #define MCHBAR_CH1_CR_SC_IO_LATENCY_three_channels_MSK (0x40000000) + #define MCHBAR_CH1_CR_SC_IO_LATENCY_three_channels_MAX (0x00000001) + #define MCHBAR_CH1_CR_SC_IO_LATENCY_three_channels_DEF (0x00000000) + #define MCHBAR_CH1_CR_SC_IO_LATENCY_DIS_RT_CLK_GATE_OFF (31) + #define MCHBAR_CH1_CR_SC_IO_LATENCY_DIS_RT_CLK_GATE_WID ( 1) + #define MCHBAR_CH1_CR_SC_IO_LATENCY_DIS_RT_CLK_GATE_MSK (0x80000000) + #define MCHBAR_CH1_CR_SC_IO_LATENCY_DIS_RT_CLK_GATE_MAX (0x00000001) + #define MCHBAR_CH1_CR_SC_IO_LATENCY_DIS_RT_CLK_GATE_DEF (0x00000000) + +#define MCHBAR_CH1_CR_ROUND_TRIP_DFT_DATA_REG (0x0000442C) + #define MCHBAR_CH1_CR_ROUND_TRIP_DFT_DATA_DATA_OFF ( 0) + #define MCHBAR_CH1_CR_ROUND_TRIP_DFT_DATA_DATA_WID (32) + #define MCHBAR_CH1_CR_ROUND_TRIP_DFT_DATA_DATA_MSK (0xFFFFFFFF) + #define MCHBAR_CH1_CR_ROUND_TRIP_DFT_DATA_DATA_MAX (0xFFFFFFFF) + #define MCHBAR_CH1_CR_ROUND_TRIP_DFT_DATA_DATA_DEF (0x00000000) + +#define MCHBAR_CH1_CR_DFT_MISC_REG (0x00004430) + #define MCHBAR_CH1_CR_DFT_MISC_WDAR_OFF ( 0) + #define MCHBAR_CH1_CR_DFT_MISC_WDAR_WID ( 1) + #define MCHBAR_CH1_CR_DFT_MISC_WDAR_MSK (0x00000001) + #define MCHBAR_CH1_CR_DFT_MISC_WDAR_MAX (0x00000001) + #define MCHBAR_CH1_CR_DFT_MISC_WDAR_DEF (0x00000000) + #define MCHBAR_CH1_CR_DFT_MISC_safe_mask_sel_OFF ( 1) + #define MCHBAR_CH1_CR_DFT_MISC_safe_mask_sel_WID ( 3) + #define MCHBAR_CH1_CR_DFT_MISC_safe_mask_sel_MSK (0x0000000E) + #define MCHBAR_CH1_CR_DFT_MISC_safe_mask_sel_MAX (0x00000007) + #define MCHBAR_CH1_CR_DFT_MISC_safe_mask_sel_DEF (0x00000000) + #define MCHBAR_CH1_CR_DFT_MISC_force_rcv_en_OFF ( 4) + #define MCHBAR_CH1_CR_DFT_MISC_force_rcv_en_WID ( 1) + #define MCHBAR_CH1_CR_DFT_MISC_force_rcv_en_MSK (0x00000010) + #define MCHBAR_CH1_CR_DFT_MISC_force_rcv_en_MAX (0x00000001) + #define MCHBAR_CH1_CR_DFT_MISC_force_rcv_en_DEF (0x00000000) + #define MCHBAR_CH1_CR_DFT_MISC_DDR_QUAL_OFF ( 8) + #define MCHBAR_CH1_CR_DFT_MISC_DDR_QUAL_WID ( 2) + #define MCHBAR_CH1_CR_DFT_MISC_DDR_QUAL_MSK (0x00000300) + #define MCHBAR_CH1_CR_DFT_MISC_DDR_QUAL_MAX (0x00000003) + #define MCHBAR_CH1_CR_DFT_MISC_DDR_QUAL_DEF (0x00000000) + #define MCHBAR_CH1_CR_DFT_MISC_Qual_length_OFF (10) + #define MCHBAR_CH1_CR_DFT_MISC_Qual_length_WID ( 2) + #define MCHBAR_CH1_CR_DFT_MISC_Qual_length_MSK (0x00000C00) + #define MCHBAR_CH1_CR_DFT_MISC_Qual_length_MAX (0x00000003) + #define MCHBAR_CH1_CR_DFT_MISC_Qual_length_DEF (0x00000000) + #define MCHBAR_CH1_CR_DFT_MISC_WDB_Block_En_OFF (12) + #define MCHBAR_CH1_CR_DFT_MISC_WDB_Block_En_WID ( 1) + #define MCHBAR_CH1_CR_DFT_MISC_WDB_Block_En_MSK (0x00001000) + #define MCHBAR_CH1_CR_DFT_MISC_WDB_Block_En_MAX (0x00000001) + #define MCHBAR_CH1_CR_DFT_MISC_WDB_Block_En_DEF (0x00000000) + #define MCHBAR_CH1_CR_DFT_MISC_RT_DFT_READ_PTR_OFF (13) + #define MCHBAR_CH1_CR_DFT_MISC_RT_DFT_READ_PTR_WID ( 4) + #define MCHBAR_CH1_CR_DFT_MISC_RT_DFT_READ_PTR_MSK (0x0001E000) + #define MCHBAR_CH1_CR_DFT_MISC_RT_DFT_READ_PTR_MAX (0x0000000F) + #define MCHBAR_CH1_CR_DFT_MISC_RT_DFT_READ_PTR_DEF (0x00000000) + #define MCHBAR_CH1_CR_DFT_MISC_RT_DFT_READ_ENABLE_OFF (17) + #define MCHBAR_CH1_CR_DFT_MISC_RT_DFT_READ_ENABLE_WID ( 1) + #define MCHBAR_CH1_CR_DFT_MISC_RT_DFT_READ_ENABLE_MSK (0x00020000) + #define MCHBAR_CH1_CR_DFT_MISC_RT_DFT_READ_ENABLE_MAX (0x00000001) + #define MCHBAR_CH1_CR_DFT_MISC_RT_DFT_READ_ENABLE_DEF (0x00000000) + #define MCHBAR_CH1_CR_DFT_MISC_RT_DFT_READ_SEL_ADDR_OFF (18) + #define MCHBAR_CH1_CR_DFT_MISC_RT_DFT_READ_SEL_ADDR_WID ( 1) + #define MCHBAR_CH1_CR_DFT_MISC_RT_DFT_READ_SEL_ADDR_MSK (0x00040000) + #define MCHBAR_CH1_CR_DFT_MISC_RT_DFT_READ_SEL_ADDR_MAX (0x00000001) + #define MCHBAR_CH1_CR_DFT_MISC_RT_DFT_READ_SEL_ADDR_DEF (0x00000000) + +#define MCHBAR_CH1_CR_READ_RETURN_DFT_REG (0x00004434) + #define MCHBAR_CH1_CR_READ_RETURN_DFT_ECC_OFF ( 0) + #define MCHBAR_CH1_CR_READ_RETURN_DFT_ECC_WID ( 8) + #define MCHBAR_CH1_CR_READ_RETURN_DFT_ECC_MSK (0x000000FF) + #define MCHBAR_CH1_CR_READ_RETURN_DFT_ECC_MAX (0x000000FF) + #define MCHBAR_CH1_CR_READ_RETURN_DFT_ECC_DEF (0x00000000) + #define MCHBAR_CH1_CR_READ_RETURN_DFT_RRD_DFT_Mode_OFF ( 8) + #define MCHBAR_CH1_CR_READ_RETURN_DFT_RRD_DFT_Mode_WID ( 2) + #define MCHBAR_CH1_CR_READ_RETURN_DFT_RRD_DFT_Mode_MSK (0x00000300) + #define MCHBAR_CH1_CR_READ_RETURN_DFT_RRD_DFT_Mode_MAX (0x00000003) + #define MCHBAR_CH1_CR_READ_RETURN_DFT_RRD_DFT_Mode_DEF (0x00000000) + #define MCHBAR_CH1_CR_READ_RETURN_DFT_LFSR_Seed_Index_OFF (10) + #define MCHBAR_CH1_CR_READ_RETURN_DFT_LFSR_Seed_Index_WID ( 5) + #define MCHBAR_CH1_CR_READ_RETURN_DFT_LFSR_Seed_Index_MSK (0x00007C00) + #define MCHBAR_CH1_CR_READ_RETURN_DFT_LFSR_Seed_Index_MAX (0x0000001F) + #define MCHBAR_CH1_CR_READ_RETURN_DFT_LFSR_Seed_Index_DEF (0x00000000) + #define MCHBAR_CH1_CR_READ_RETURN_DFT_Inversion_Mode_OFF (15) + #define MCHBAR_CH1_CR_READ_RETURN_DFT_Inversion_Mode_WID ( 1) + #define MCHBAR_CH1_CR_READ_RETURN_DFT_Inversion_Mode_MSK (0x00008000) + #define MCHBAR_CH1_CR_READ_RETURN_DFT_Inversion_Mode_MAX (0x00000001) + #define MCHBAR_CH1_CR_READ_RETURN_DFT_Inversion_Mode_DEF (0x00000000) + +#define MCHBAR_CH1_CR_SCHED_SECOND_CBIT_REG (0x00004438) + #define MCHBAR_CH1_CR_SCHED_SECOND_CBIT_dis_imph_error_OFF ( 0) + #define MCHBAR_CH1_CR_SCHED_SECOND_CBIT_dis_imph_error_WID ( 1) + #define MCHBAR_CH1_CR_SCHED_SECOND_CBIT_dis_imph_error_MSK (0x00000001) + #define MCHBAR_CH1_CR_SCHED_SECOND_CBIT_dis_imph_error_MAX (0x00000001) + #define MCHBAR_CH1_CR_SCHED_SECOND_CBIT_dis_imph_error_DEF (0x00000000) + #define MCHBAR_CH1_CR_SCHED_SECOND_CBIT_dis_async_odt_OFF ( 8) + #define MCHBAR_CH1_CR_SCHED_SECOND_CBIT_dis_async_odt_WID ( 1) + #define MCHBAR_CH1_CR_SCHED_SECOND_CBIT_dis_async_odt_MSK (0x00000100) + #define MCHBAR_CH1_CR_SCHED_SECOND_CBIT_dis_async_odt_MAX (0x00000001) + #define MCHBAR_CH1_CR_SCHED_SECOND_CBIT_dis_async_odt_DEF (0x00000000) + +#define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_REG (0x00004440) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux0_Control_OFF ( 0) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux0_Control_WID ( 2) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux0_Control_MSK (0x00000003) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux0_Control_MAX (0x00000003) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux0_Control_DEF (0x00000001) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux1_Control_OFF ( 3) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux1_Control_WID ( 2) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux1_Control_MSK (0x00000018) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux1_Control_MAX (0x00000003) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux1_Control_DEF (0x00000001) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux2_Control_OFF ( 6) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux2_Control_WID ( 2) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux2_Control_MSK (0x000000C0) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux2_Control_MAX (0x00000003) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux2_Control_DEF (0x00000001) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_ECC_Replace_Byte_Control_OFF (14) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_ECC_Replace_Byte_Control_WID ( 1) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_ECC_Replace_Byte_Control_MSK (0x00004000) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_ECC_Replace_Byte_Control_MAX (0x00000001) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_ECC_Replace_Byte_Control_DEF (0x00000001) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_ECC_Data_Source_Sel_OFF (15) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_ECC_Data_Source_Sel_WID ( 1) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_ECC_Data_Source_Sel_MSK (0x00008000) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_ECC_Data_Source_Sel_MAX (0x00000001) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_ECC_Data_Source_Sel_DEF (0x00000001) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Save_LFSR_Seed_Rate_OFF (16) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Save_LFSR_Seed_Rate_WID ( 6) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Save_LFSR_Seed_Rate_MSK (0x003F0000) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Save_LFSR_Seed_Rate_MAX (0x0000003F) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Save_LFSR_Seed_Rate_DEF (0x00000000) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Reload_LFSR_Seed_Rate_OFF (24) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Reload_LFSR_Seed_Rate_WID ( 3) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Reload_LFSR_Seed_Rate_MSK (0x07000000) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Reload_LFSR_Seed_Rate_MAX (0x00000007) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Reload_LFSR_Seed_Rate_DEF (0x00000000) + +#define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_RD_STATUS_REG (0x00004444) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_RD_STATUS_WDB_Current_Read_Pointer_OFF ( 0) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_RD_STATUS_WDB_Current_Read_Pointer_WID ( 6) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_RD_STATUS_WDB_Current_Read_Pointer_MSK (0x0000003F) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_RD_STATUS_WDB_Current_Read_Pointer_MAX (0x0000003F) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_RD_STATUS_WDB_Current_Read_Pointer_DEF (0x00000000) + +#define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_0_REG (0x00004448) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_0_Pattern_Buffer_OFF ( 0) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_0_Pattern_Buffer_WID (24) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_0_Pattern_Buffer_MSK (0x00FFFFFF) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_0_Pattern_Buffer_MAX (0x00FFFFFF) + +#define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_1_REG (0x0000444C) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_1_Pattern_Buffer_OFF ( 0) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_1_Pattern_Buffer_WID (24) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_1_Pattern_Buffer_MSK (0x00FFFFFF) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_1_Pattern_Buffer_MAX (0x00FFFFFF) + +#define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_2_REG (0x00004450) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_2_Pattern_Buffer_OFF ( 0) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_2_Pattern_Buffer_WID (24) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_2_Pattern_Buffer_MSK (0x00FFFFFF) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_2_Pattern_Buffer_MAX (0x00FFFFFF) + +#define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_0_REG (0x00004454) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_0_Pattern_Buffer_OFF ( 0) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_0_Pattern_Buffer_WID (24) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_0_Pattern_Buffer_MSK (0x00FFFFFF) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_0_Pattern_Buffer_MAX (0x00FFFFFF) + +#define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_1_REG (0x00004458) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_1_Pattern_Buffer_OFF ( 0) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_1_Pattern_Buffer_WID (24) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_1_Pattern_Buffer_MSK (0x00FFFFFF) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_1_Pattern_Buffer_MAX (0x00FFFFFF) + +#define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_2_REG (0x0000445C) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_2_Pattern_Buffer_OFF ( 0) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_2_Pattern_Buffer_WID (24) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_2_Pattern_Buffer_MSK (0x00FFFFFF) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_2_Pattern_Buffer_MAX (0x00FFFFFF) + +#define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_0_REG (0x00004460) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_0_Pattern_Buffer_OFF ( 0) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_0_Pattern_Buffer_WID (24) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_0_Pattern_Buffer_MSK (0x00FFFFFF) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_0_Pattern_Buffer_MAX (0x00FFFFFF) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_0_Pattern_Buffer_DEF (0x00000000) + +#define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_1_REG (0x00004464) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_1_Pattern_Buffer_OFF ( 0) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_1_Pattern_Buffer_WID (24) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_1_Pattern_Buffer_MSK (0x00FFFFFF) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_1_Pattern_Buffer_MAX (0x00FFFFFF) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_1_Pattern_Buffer_DEF (0x00000000) + +#define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_2_REG (0x00004468) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_2_Pattern_Buffer_OFF ( 0) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_2_Pattern_Buffer_WID (24) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_2_Pattern_Buffer_MSK (0x00FFFFFF) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_2_Pattern_Buffer_MAX (0x00FFFFFF) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_2_Pattern_Buffer_DEF (0x00000000) + +#define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_0_REG (0x0000446C) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_0_Pattern_Buffer_OFF ( 0) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_0_Pattern_Buffer_WID (24) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_0_Pattern_Buffer_MSK (0x00FFFFFF) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_0_Pattern_Buffer_MAX (0x00FFFFFF) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_0_Pattern_Buffer_DEF (0x00000000) + +#define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_1_REG (0x00004470) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_1_Pattern_Buffer_OFF ( 0) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_1_Pattern_Buffer_WID (24) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_1_Pattern_Buffer_MSK (0x00FFFFFF) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_1_Pattern_Buffer_MAX (0x00FFFFFF) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_1_Pattern_Buffer_DEF (0x00000000) + +#define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_2_REG (0x00004474) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_2_Pattern_Buffer_OFF ( 0) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_2_Pattern_Buffer_WID (24) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_2_Pattern_Buffer_MSK (0x00FFFFFF) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_2_Pattern_Buffer_MAX (0x00FFFFFF) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_2_Pattern_Buffer_DEF (0x00000000) + +#define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_REG (0x00004478) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_L_data_select_OFF ( 0) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_L_data_select_WID ( 1) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_L_data_select_MSK (0x00000001) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_L_data_select_MAX (0x00000001) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_L_data_select_DEF (0x00000000) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_Enable_Sweep_Frequency_OFF ( 1) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_Enable_Sweep_Frequency_WID ( 1) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_Enable_Sweep_Frequency_MSK (0x00000002) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_Enable_Sweep_Frequency_MAX (0x00000001) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_Enable_Sweep_Frequency_DEF (0x00000000) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_L_counter_OFF ( 8) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_L_counter_WID ( 8) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_L_counter_MSK (0x0000FF00) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_L_counter_MAX (0x000000FF) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_L_counter_DEF (0x00000001) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_M_counter_OFF (16) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_M_counter_WID ( 8) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_M_counter_MSK (0x00FF0000) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_M_counter_MAX (0x000000FF) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_M_counter_DEF (0x00000001) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_N_counter_OFF (24) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_N_counter_WID ( 8) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_N_counter_MSK (0xFF000000) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_N_counter_MAX (0x000000FF) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_N_counter_DEF (0x00000001) + +#define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_INV_REG (0x00004484) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_INV_ECC_Inv_or_DC_Enable_OFF ( 0) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_INV_ECC_Inv_or_DC_Enable_WID ( 8) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_INV_ECC_Inv_or_DC_Enable_MSK (0x000000FF) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_INV_ECC_Inv_or_DC_Enable_MAX (0x000000FF) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_INV_ECC_Inv_or_DC_Enable_DEF (0x00000000) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Shift_Rate_OFF (16) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Shift_Rate_WID ( 4) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Shift_Rate_MSK (0x000F0000) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Shift_Rate_MAX (0x0000000F) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Shift_Rate_DEF (0x00000000) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_INV_DC_Polarity_Control_OFF (20) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_INV_DC_Polarity_Control_WID ( 1) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_INV_DC_Polarity_Control_MSK (0x00100000) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_INV_DC_Polarity_Control_MAX (0x00000001) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_INV_DC_Polarity_Control_DEF (0x00000000) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Control_OFF (30) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Control_WID ( 1) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Control_MSK (0x40000000) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Control_MAX (0x00000001) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Control_DEF (0x00000000) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Shift_Enable_OFF (31) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Shift_Enable_WID ( 1) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Shift_Enable_MSK (0x80000000) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Shift_Enable_MAX (0x00000001) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Shift_Enable_DEF (0x00000000) + +#define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_DATA_INV_REG (0x00004490) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_DATA_INV_Data_Inv_or_DC_Enable_OFF ( 0) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_DATA_INV_Data_Inv_or_DC_Enable_WID (64) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_DATA_INV_Data_Inv_or_DC_Enable_MSK (0xFFFFFFFFFFFFFFFF) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_DATA_INV_Data_Inv_or_DC_Enable_MAX (0xFFFFFFFFFFFFFFFF) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_DATA_INV_Data_Inv_or_DC_Enable_DEF (0x00000000) + +#define MCHBAR_CH1_CR_REUT_CH_ERR_CTL_REG (0x00004498) + #define MCHBAR_CH1_CR_REUT_CH_ERR_CTL_Stop_on_Nth_Error_OFF ( 0) + #define MCHBAR_CH1_CR_REUT_CH_ERR_CTL_Stop_on_Nth_Error_WID ( 6) + #define MCHBAR_CH1_CR_REUT_CH_ERR_CTL_Stop_on_Nth_Error_MSK (0x0000003F) + #define MCHBAR_CH1_CR_REUT_CH_ERR_CTL_Stop_on_Nth_Error_MAX (0x0000003F) + #define MCHBAR_CH1_CR_REUT_CH_ERR_CTL_Stop_on_Nth_Error_DEF (0x00000001) + #define MCHBAR_CH1_CR_REUT_CH_ERR_CTL_Stop_On_Error_Control_OFF (12) + #define MCHBAR_CH1_CR_REUT_CH_ERR_CTL_Stop_On_Error_Control_WID ( 2) + #define MCHBAR_CH1_CR_REUT_CH_ERR_CTL_Stop_On_Error_Control_MSK (0x00003000) + #define MCHBAR_CH1_CR_REUT_CH_ERR_CTL_Stop_On_Error_Control_MAX (0x00000003) + #define MCHBAR_CH1_CR_REUT_CH_ERR_CTL_Stop_On_Error_Control_DEF (0x00000000) + #define MCHBAR_CH1_CR_REUT_CH_ERR_CTL_Selective_Error_Enable_Chunk_OFF (16) + #define MCHBAR_CH1_CR_REUT_CH_ERR_CTL_Selective_Error_Enable_Chunk_WID ( 8) + #define MCHBAR_CH1_CR_REUT_CH_ERR_CTL_Selective_Error_Enable_Chunk_MSK (0x00FF0000) + #define MCHBAR_CH1_CR_REUT_CH_ERR_CTL_Selective_Error_Enable_Chunk_MAX (0x000000FF) + #define MCHBAR_CH1_CR_REUT_CH_ERR_CTL_Selective_Error_Enable_Chunk_DEF (0x000000FF) + #define MCHBAR_CH1_CR_REUT_CH_ERR_CTL_Selective_Error_Enable_Cacheline_OFF (24) + #define MCHBAR_CH1_CR_REUT_CH_ERR_CTL_Selective_Error_Enable_Cacheline_WID ( 8) + #define MCHBAR_CH1_CR_REUT_CH_ERR_CTL_Selective_Error_Enable_Cacheline_MSK (0xFF000000) + #define MCHBAR_CH1_CR_REUT_CH_ERR_CTL_Selective_Error_Enable_Cacheline_MAX (0x000000FF) + #define MCHBAR_CH1_CR_REUT_CH_ERR_CTL_Selective_Error_Enable_Cacheline_DEF (0x000000FF) + +#define MCHBAR_CH1_CR_REUT_CH_ERR_ECC_MASK_REG (0x0000449C) + #define MCHBAR_CH1_CR_REUT_CH_ERR_ECC_MASK_ECC_Error_Mask_OFF ( 0) + #define MCHBAR_CH1_CR_REUT_CH_ERR_ECC_MASK_ECC_Error_Mask_WID ( 8) + #define MCHBAR_CH1_CR_REUT_CH_ERR_ECC_MASK_ECC_Error_Mask_MSK (0x000000FF) + #define MCHBAR_CH1_CR_REUT_CH_ERR_ECC_MASK_ECC_Error_Mask_MAX (0x000000FF) + #define MCHBAR_CH1_CR_REUT_CH_ERR_ECC_MASK_ECC_Error_Mask_DEF (0x00000000) + +#define MCHBAR_CH1_CR_STM_CONFIG_REG (0x000044A4) + #define MCHBAR_CH1_CR_STM_CONFIG_Stretch_mode_OFF ( 0) + #define MCHBAR_CH1_CR_STM_CONFIG_Stretch_mode_WID ( 2) + #define MCHBAR_CH1_CR_STM_CONFIG_Stretch_mode_MSK (0x00000003) + #define MCHBAR_CH1_CR_STM_CONFIG_Stretch_mode_MAX (0x00000003) + #define MCHBAR_CH1_CR_STM_CONFIG_Stretch_mode_DEF (0x00000000) + #define MCHBAR_CH1_CR_STM_CONFIG_STF_OFF ( 4) + #define MCHBAR_CH1_CR_STM_CONFIG_STF_WID ( 3) + #define MCHBAR_CH1_CR_STM_CONFIG_STF_MSK (0x00000070) + #define MCHBAR_CH1_CR_STM_CONFIG_STF_MAX (0x00000007) + #define MCHBAR_CH1_CR_STM_CONFIG_STF_DEF (0x00000000) + +#define MCHBAR_CH1_CR_SC_PR_CNT_CONFIG_REG (0x000044A8) + #define MCHBAR_CH1_CR_SC_PR_CNT_CONFIG_Priority_count_ring_OFF ( 0) + #define MCHBAR_CH1_CR_SC_PR_CNT_CONFIG_Priority_count_ring_WID (10) + #define MCHBAR_CH1_CR_SC_PR_CNT_CONFIG_Priority_count_ring_MSK (0x000003FF) + #define MCHBAR_CH1_CR_SC_PR_CNT_CONFIG_Priority_count_ring_MAX (0x000003FF) + #define MCHBAR_CH1_CR_SC_PR_CNT_CONFIG_Priority_count_ring_DEF (0x00000040) + #define MCHBAR_CH1_CR_SC_PR_CNT_CONFIG_Priority_count_SA_OFF (16) + #define MCHBAR_CH1_CR_SC_PR_CNT_CONFIG_Priority_count_SA_WID (10) + #define MCHBAR_CH1_CR_SC_PR_CNT_CONFIG_Priority_count_SA_MSK (0x03FF0000) + #define MCHBAR_CH1_CR_SC_PR_CNT_CONFIG_Priority_count_SA_MAX (0x000003FF) + #define MCHBAR_CH1_CR_SC_PR_CNT_CONFIG_Priority_count_SA_DEF (0x00000100) + +#define MCHBAR_CH1_CR_SC_PCIT_REG (0x000044AC) + #define MCHBAR_CH1_CR_SC_PCIT_PCIT_OFF ( 0) + #define MCHBAR_CH1_CR_SC_PCIT_PCIT_WID ( 8) + #define MCHBAR_CH1_CR_SC_PCIT_PCIT_MSK (0x000000FF) + #define MCHBAR_CH1_CR_SC_PCIT_PCIT_MAX (0x000000FF) + #define MCHBAR_CH1_CR_SC_PCIT_PCIT_DEF (0x00000040) + +#define MCHBAR_CH1_CR_PM_PDWN_CONFIG_REG (0x000044B0) + #define MCHBAR_CH1_CR_PM_PDWN_CONFIG_PDWN_idle_counter_OFF ( 0) + #define MCHBAR_CH1_CR_PM_PDWN_CONFIG_PDWN_idle_counter_WID (12) + #define MCHBAR_CH1_CR_PM_PDWN_CONFIG_PDWN_idle_counter_MSK (0x00000FFF) + #define MCHBAR_CH1_CR_PM_PDWN_CONFIG_PDWN_idle_counter_MAX (0x00000FFF) + #define MCHBAR_CH1_CR_PM_PDWN_CONFIG_PDWN_idle_counter_DEF (0x00000000) + #define MCHBAR_CH1_CR_PM_PDWN_CONFIG_PDWN_mode_OFF (12) + #define MCHBAR_CH1_CR_PM_PDWN_CONFIG_PDWN_mode_WID ( 4) + #define MCHBAR_CH1_CR_PM_PDWN_CONFIG_PDWN_mode_MSK (0x0000F000) + #define MCHBAR_CH1_CR_PM_PDWN_CONFIG_PDWN_mode_MAX (0x0000000F) + #define MCHBAR_CH1_CR_PM_PDWN_CONFIG_PDWN_mode_DEF (0x00000000) + +#define MCHBAR_CH1_CR_ECC_INJECT_COUNT_REG (0x000044B4) + #define MCHBAR_CH1_CR_ECC_INJECT_COUNT_Count_OFF ( 0) + #define MCHBAR_CH1_CR_ECC_INJECT_COUNT_Count_WID (32) + #define MCHBAR_CH1_CR_ECC_INJECT_COUNT_Count_MSK (0xFFFFFFFF) + #define MCHBAR_CH1_CR_ECC_INJECT_COUNT_Count_MAX (0xFFFFFFFF) + #define MCHBAR_CH1_CR_ECC_INJECT_COUNT_Count_DEF (0xFFFFFFFF) + +#define MCHBAR_CH1_CR_ECC_DFT_REG (0x000044B8) + #define MCHBAR_CH1_CR_ECC_DFT_ECC4ANA_fill_OFF ( 0) + #define MCHBAR_CH1_CR_ECC_DFT_ECC4ANA_fill_WID ( 8) + #define MCHBAR_CH1_CR_ECC_DFT_ECC4ANA_fill_MSK (0x000000FF) + #define MCHBAR_CH1_CR_ECC_DFT_ECC4ANA_fill_MAX (0x000000FF) + #define MCHBAR_CH1_CR_ECC_DFT_ECC4ANA_fill_DEF (0x00000000) + #define MCHBAR_CH1_CR_ECC_DFT_ECC4ANA_trigger_OFF ( 8) + #define MCHBAR_CH1_CR_ECC_DFT_ECC4ANA_trigger_WID ( 2) + #define MCHBAR_CH1_CR_ECC_DFT_ECC4ANA_trigger_MSK (0x00000300) + #define MCHBAR_CH1_CR_ECC_DFT_ECC4ANA_trigger_MAX (0x00000003) + #define MCHBAR_CH1_CR_ECC_DFT_ECC4ANA_trigger_DEF (0x00000000) + #define MCHBAR_CH1_CR_ECC_DFT_ECC4ANA_BS_OFF (10) + #define MCHBAR_CH1_CR_ECC_DFT_ECC4ANA_BS_WID ( 1) + #define MCHBAR_CH1_CR_ECC_DFT_ECC4ANA_BS_MSK (0x00000400) + #define MCHBAR_CH1_CR_ECC_DFT_ECC4ANA_BS_MAX (0x00000001) + #define MCHBAR_CH1_CR_ECC_DFT_ECC4ANA_BS_DEF (0x00000000) + #define MCHBAR_CH1_CR_ECC_DFT_ECC_Inject_OFF (11) + #define MCHBAR_CH1_CR_ECC_DFT_ECC_Inject_WID ( 3) + #define MCHBAR_CH1_CR_ECC_DFT_ECC_Inject_MSK (0x00003800) + #define MCHBAR_CH1_CR_ECC_DFT_ECC_Inject_MAX (0x00000007) + #define MCHBAR_CH1_CR_ECC_DFT_ECC_Inject_DEF (0x00000000) + #define MCHBAR_CH1_CR_ECC_DFT_ECC_correction_disable_OFF (14) + #define MCHBAR_CH1_CR_ECC_DFT_ECC_correction_disable_WID ( 1) + #define MCHBAR_CH1_CR_ECC_DFT_ECC_correction_disable_MSK (0x00004000) + #define MCHBAR_CH1_CR_ECC_DFT_ECC_correction_disable_MAX (0x00000001) + #define MCHBAR_CH1_CR_ECC_DFT_ECC_correction_disable_DEF (0x00000000) + #define MCHBAR_CH1_CR_ECC_DFT_ECC4ANA_Inject_OFF (15) + #define MCHBAR_CH1_CR_ECC_DFT_ECC4ANA_Inject_WID ( 1) + #define MCHBAR_CH1_CR_ECC_DFT_ECC4ANA_Inject_MSK (0x00008000) + #define MCHBAR_CH1_CR_ECC_DFT_ECC4ANA_Inject_MAX (0x00000001) + #define MCHBAR_CH1_CR_ECC_DFT_ECC4ANA_Inject_DEF (0x00000000) + #define MCHBAR_CH1_CR_ECC_DFT_DIS_MCA_LOG_OFF (16) + #define MCHBAR_CH1_CR_ECC_DFT_DIS_MCA_LOG_WID ( 1) + #define MCHBAR_CH1_CR_ECC_DFT_DIS_MCA_LOG_MSK (0x00010000) + #define MCHBAR_CH1_CR_ECC_DFT_DIS_MCA_LOG_MAX (0x00000001) + #define MCHBAR_CH1_CR_ECC_DFT_DIS_MCA_LOG_DEF (0x00000000) + #define MCHBAR_CH1_CR_ECC_DFT_DIS_PCH_EVENT_OFF (17) + #define MCHBAR_CH1_CR_ECC_DFT_DIS_PCH_EVENT_WID ( 1) + #define MCHBAR_CH1_CR_ECC_DFT_DIS_PCH_EVENT_MSK (0x00020000) + #define MCHBAR_CH1_CR_ECC_DFT_DIS_PCH_EVENT_MAX (0x00000001) + #define MCHBAR_CH1_CR_ECC_DFT_DIS_PCH_EVENT_DEF (0x00000000) + #define MCHBAR_CH1_CR_ECC_DFT_DIS_PCIE_POISON_OFF (18) + #define MCHBAR_CH1_CR_ECC_DFT_DIS_PCIE_POISON_WID ( 1) + #define MCHBAR_CH1_CR_ECC_DFT_DIS_PCIE_POISON_MSK (0x00040000) + #define MCHBAR_CH1_CR_ECC_DFT_DIS_PCIE_POISON_MAX (0x00000001) + #define MCHBAR_CH1_CR_ECC_DFT_DIS_PCIE_POISON_DEF (0x00000000) + +#define MCHBAR_CH1_CR_VISA_CTL_MCSCHEDS_REG (0x000044C0) + #define MCHBAR_CH1_CR_VISA_CTL_MCSCHEDS_Data_OFF ( 0) + #define MCHBAR_CH1_CR_VISA_CTL_MCSCHEDS_Data_WID (18) + #define MCHBAR_CH1_CR_VISA_CTL_MCSCHEDS_Data_MSK (0x0003FFFF) + #define MCHBAR_CH1_CR_VISA_CTL_MCSCHEDS_Data_MAX (0x0003FFFF) + #define MCHBAR_CH1_CR_VISA_CTL_MCSCHEDS_Data_DEF (0x00000000) + #define MCHBAR_CH1_CR_VISA_CTL_MCSCHEDS_VORANGE_OFF (31) + #define MCHBAR_CH1_CR_VISA_CTL_MCSCHEDS_VORANGE_WID ( 1) + #define MCHBAR_CH1_CR_VISA_CTL_MCSCHEDS_VORANGE_MSK (0x80000000) + #define MCHBAR_CH1_CR_VISA_CTL_MCSCHEDS_VORANGE_MAX (0x00000001) + #define MCHBAR_CH1_CR_VISA_CTL_MCSCHEDS_VORANGE_DEF (0x00000000) + +#define MCHBAR_CH1_CR_VISA_XBAR_MCSCHEDS_REG (0x000044C4) + #define MCHBAR_CH1_CR_VISA_XBAR_MCSCHEDS_Data_OFF ( 0) + #define MCHBAR_CH1_CR_VISA_XBAR_MCSCHEDS_Data_WID (32) + #define MCHBAR_CH1_CR_VISA_XBAR_MCSCHEDS_Data_MSK (0xFFFFFFFF) + #define MCHBAR_CH1_CR_VISA_XBAR_MCSCHEDS_Data_MAX (0xFFFFFFFF) + #define MCHBAR_CH1_CR_VISA_XBAR_MCSCHEDS_Data_DEF (0x76543210) + +#define MCHBAR_CH1_CR_ECCERRLOG0_REG (0x000044C8) + #define MCHBAR_CH1_CR_ECCERRLOG0_CERRSTS_OFF ( 0) + #define MCHBAR_CH1_CR_ECCERRLOG0_CERRSTS_WID ( 1) + #define MCHBAR_CH1_CR_ECCERRLOG0_CERRSTS_MSK (0x00000001) + #define MCHBAR_CH1_CR_ECCERRLOG0_CERRSTS_MAX (0x00000001) + #define MCHBAR_CH1_CR_ECCERRLOG0_CERRSTS_DEF (0x00000000) + #define MCHBAR_CH1_CR_ECCERRLOG0_MERRSTS_OFF ( 1) + #define MCHBAR_CH1_CR_ECCERRLOG0_MERRSTS_WID ( 1) + #define MCHBAR_CH1_CR_ECCERRLOG0_MERRSTS_MSK (0x00000002) + #define MCHBAR_CH1_CR_ECCERRLOG0_MERRSTS_MAX (0x00000001) + #define MCHBAR_CH1_CR_ECCERRLOG0_MERRSTS_DEF (0x00000000) + #define MCHBAR_CH1_CR_ECCERRLOG0_ERRSYND_OFF (16) + #define MCHBAR_CH1_CR_ECCERRLOG0_ERRSYND_WID ( 8) + #define MCHBAR_CH1_CR_ECCERRLOG0_ERRSYND_MSK (0x00FF0000) + #define MCHBAR_CH1_CR_ECCERRLOG0_ERRSYND_MAX (0x000000FF) + #define MCHBAR_CH1_CR_ECCERRLOG0_ERRSYND_DEF (0x00000000) + #define MCHBAR_CH1_CR_ECCERRLOG0_ERRCHUNK_OFF (24) + #define MCHBAR_CH1_CR_ECCERRLOG0_ERRCHUNK_WID ( 3) + #define MCHBAR_CH1_CR_ECCERRLOG0_ERRCHUNK_MSK (0x07000000) + #define MCHBAR_CH1_CR_ECCERRLOG0_ERRCHUNK_MAX (0x00000007) + #define MCHBAR_CH1_CR_ECCERRLOG0_ERRCHUNK_DEF (0x00000000) + #define MCHBAR_CH1_CR_ECCERRLOG0_ERRRANK_OFF (27) + #define MCHBAR_CH1_CR_ECCERRLOG0_ERRRANK_WID ( 2) + #define MCHBAR_CH1_CR_ECCERRLOG0_ERRRANK_MSK (0x18000000) + #define MCHBAR_CH1_CR_ECCERRLOG0_ERRRANK_MAX (0x00000003) + #define MCHBAR_CH1_CR_ECCERRLOG0_ERRRANK_DEF (0x00000000) + #define MCHBAR_CH1_CR_ECCERRLOG0_ERRBANK_OFF (29) + #define MCHBAR_CH1_CR_ECCERRLOG0_ERRBANK_WID ( 3) + #define MCHBAR_CH1_CR_ECCERRLOG0_ERRBANK_MSK (0xE0000000) + #define MCHBAR_CH1_CR_ECCERRLOG0_ERRBANK_MAX (0x00000007) + #define MCHBAR_CH1_CR_ECCERRLOG0_ERRBANK_DEF (0x00000000) + +#define MCHBAR_CH1_CR_ECCERRLOG1_REG (0x000044CC) + #define MCHBAR_CH1_CR_ECCERRLOG1_ERRROW_OFF ( 0) + #define MCHBAR_CH1_CR_ECCERRLOG1_ERRROW_WID (16) + #define MCHBAR_CH1_CR_ECCERRLOG1_ERRROW_MSK (0x0000FFFF) + #define MCHBAR_CH1_CR_ECCERRLOG1_ERRROW_MAX (0x0000FFFF) + #define MCHBAR_CH1_CR_ECCERRLOG1_ERRROW_DEF (0x00000000) + #define MCHBAR_CH1_CR_ECCERRLOG1_ERRCOL_OFF (16) + #define MCHBAR_CH1_CR_ECCERRLOG1_ERRCOL_WID (16) + #define MCHBAR_CH1_CR_ECCERRLOG1_ERRCOL_MSK (0xFFFF0000) + #define MCHBAR_CH1_CR_ECCERRLOG1_ERRCOL_MAX (0x0000FFFF) + #define MCHBAR_CH1_CR_ECCERRLOG1_ERRCOL_DEF (0x00000000) + +#define MCHBAR_CH1_CR_SC_WR_ADD_DELAY_REG (0x000044D0) + #define MCHBAR_CH1_CR_SC_WR_ADD_DELAY_D0R0_OFF ( 0) + #define MCHBAR_CH1_CR_SC_WR_ADD_DELAY_D0R0_WID ( 2) + #define MCHBAR_CH1_CR_SC_WR_ADD_DELAY_D0R0_MSK (0x00000003) + #define MCHBAR_CH1_CR_SC_WR_ADD_DELAY_D0R0_MAX (0x00000003) + #define MCHBAR_CH1_CR_SC_WR_ADD_DELAY_D0R0_DEF (0x00000000) + #define MCHBAR_CH1_CR_SC_WR_ADD_DELAY_D0R1_OFF ( 2) + #define MCHBAR_CH1_CR_SC_WR_ADD_DELAY_D0R1_WID ( 2) + #define MCHBAR_CH1_CR_SC_WR_ADD_DELAY_D0R1_MSK (0x0000000C) + #define MCHBAR_CH1_CR_SC_WR_ADD_DELAY_D0R1_MAX (0x00000003) + #define MCHBAR_CH1_CR_SC_WR_ADD_DELAY_D0R1_DEF (0x00000000) + #define MCHBAR_CH1_CR_SC_WR_ADD_DELAY_D1R0_OFF ( 4) + #define MCHBAR_CH1_CR_SC_WR_ADD_DELAY_D1R0_WID ( 2) + #define MCHBAR_CH1_CR_SC_WR_ADD_DELAY_D1R0_MSK (0x00000030) + #define MCHBAR_CH1_CR_SC_WR_ADD_DELAY_D1R0_MAX (0x00000003) + #define MCHBAR_CH1_CR_SC_WR_ADD_DELAY_D1R0_DEF (0x00000000) + #define MCHBAR_CH1_CR_SC_WR_ADD_DELAY_D1R1_OFF ( 6) + #define MCHBAR_CH1_CR_SC_WR_ADD_DELAY_D1R1_WID ( 2) + #define MCHBAR_CH1_CR_SC_WR_ADD_DELAY_D1R1_MSK (0x000000C0) + #define MCHBAR_CH1_CR_SC_WR_ADD_DELAY_D1R1_MAX (0x00000003) + #define MCHBAR_CH1_CR_SC_WR_ADD_DELAY_D1R1_DEF (0x00000000) + +#define MCHBAR_CH1_CR_WMM_READ_CONFIG_REG (0x000044D4) + #define MCHBAR_CH1_CR_WMM_READ_CONFIG_Dis_Opp_rd_OFF ( 0) + #define MCHBAR_CH1_CR_WMM_READ_CONFIG_Dis_Opp_rd_WID ( 1) + #define MCHBAR_CH1_CR_WMM_READ_CONFIG_Dis_Opp_rd_MSK (0x00000001) + #define MCHBAR_CH1_CR_WMM_READ_CONFIG_Dis_Opp_rd_MAX (0x00000001) + #define MCHBAR_CH1_CR_WMM_READ_CONFIG_Dis_Opp_rd_DEF (0x00000000) + #define MCHBAR_CH1_CR_WMM_READ_CONFIG_ACT_Enable_OFF ( 1) + #define MCHBAR_CH1_CR_WMM_READ_CONFIG_ACT_Enable_WID ( 1) + #define MCHBAR_CH1_CR_WMM_READ_CONFIG_ACT_Enable_MSK (0x00000002) + #define MCHBAR_CH1_CR_WMM_READ_CONFIG_ACT_Enable_MAX (0x00000001) + #define MCHBAR_CH1_CR_WMM_READ_CONFIG_ACT_Enable_DEF (0x00000001) + #define MCHBAR_CH1_CR_WMM_READ_CONFIG_PRE_Enable_OFF ( 2) + #define MCHBAR_CH1_CR_WMM_READ_CONFIG_PRE_Enable_WID ( 1) + #define MCHBAR_CH1_CR_WMM_READ_CONFIG_PRE_Enable_MSK (0x00000004) + #define MCHBAR_CH1_CR_WMM_READ_CONFIG_PRE_Enable_MAX (0x00000001) + #define MCHBAR_CH1_CR_WMM_READ_CONFIG_PRE_Enable_DEF (0x00000001) + #define MCHBAR_CH1_CR_WMM_READ_CONFIG_MAX_RPQ_Cas_OFF ( 3) + #define MCHBAR_CH1_CR_WMM_READ_CONFIG_MAX_RPQ_Cas_WID ( 4) + #define MCHBAR_CH1_CR_WMM_READ_CONFIG_MAX_RPQ_Cas_MSK (0x00000078) + #define MCHBAR_CH1_CR_WMM_READ_CONFIG_MAX_RPQ_Cas_MAX (0x0000000F) + #define MCHBAR_CH1_CR_WMM_READ_CONFIG_MAX_RPQ_Cas_DEF (0x00000008) + +#define MCHBAR_CH1_CR_REUT_CH_ERR_DATA_MASK_REG (0x000044D8) + #define MCHBAR_CH1_CR_REUT_CH_ERR_DATA_MASK_Data_Error_Mask_OFF ( 0) + #define MCHBAR_CH1_CR_REUT_CH_ERR_DATA_MASK_Data_Error_Mask_WID (64) + #define MCHBAR_CH1_CR_REUT_CH_ERR_DATA_MASK_Data_Error_Mask_MSK (0xFFFFFFFFFFFFFFFF) + #define MCHBAR_CH1_CR_REUT_CH_ERR_DATA_MASK_Data_Error_Mask_MAX (0xFFFFFFFFFFFFFFFF) + #define MCHBAR_CH1_CR_REUT_CH_ERR_DATA_MASK_Data_Error_Mask_DEF (0x00000000) + +#define MCHBAR_CH1_CR_REUT_CH_ERR_DATA_STATUS_REG (0x000044E0) + #define MCHBAR_CH1_CR_REUT_CH_ERR_DATA_STATUS_Data_Error_Status_OFF ( 0) + #define MCHBAR_CH1_CR_REUT_CH_ERR_DATA_STATUS_Data_Error_Status_WID (64) + #define MCHBAR_CH1_CR_REUT_CH_ERR_DATA_STATUS_Data_Error_Status_MSK (0xFFFFFFFFFFFFFFFF) + #define MCHBAR_CH1_CR_REUT_CH_ERR_DATA_STATUS_Data_Error_Status_MAX (0xFFFFFFFFFFFFFFFF) + #define MCHBAR_CH1_CR_REUT_CH_ERR_DATA_STATUS_Data_Error_Status_DEF (0x00000000) + +#define MCHBAR_CH1_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_REG (0x000044E8) + #define MCHBAR_CH1_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_ECC_Error_Status_OFF ( 0) + #define MCHBAR_CH1_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_ECC_Error_Status_WID ( 8) + #define MCHBAR_CH1_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_ECC_Error_Status_MSK (0x000000FF) + #define MCHBAR_CH1_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_ECC_Error_Status_MAX (0x000000FF) + #define MCHBAR_CH1_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_ECC_Error_Status_DEF (0x00000000) + #define MCHBAR_CH1_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Chunk_Error_Status_OFF ( 8) + #define MCHBAR_CH1_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Chunk_Error_Status_WID ( 8) + #define MCHBAR_CH1_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Chunk_Error_Status_MSK (0x0000FF00) + #define MCHBAR_CH1_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Chunk_Error_Status_MAX (0x000000FF) + #define MCHBAR_CH1_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Chunk_Error_Status_DEF (0x00000000) + #define MCHBAR_CH1_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Rank_Error_Status_OFF (16) + #define MCHBAR_CH1_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Rank_Error_Status_WID ( 4) + #define MCHBAR_CH1_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Rank_Error_Status_MSK (0x000F0000) + #define MCHBAR_CH1_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Rank_Error_Status_MAX (0x0000000F) + #define MCHBAR_CH1_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Rank_Error_Status_DEF (0x00000000) + #define MCHBAR_CH1_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Byte_Group_Error_Status_OFF (32) + #define MCHBAR_CH1_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Byte_Group_Error_Status_WID ( 9) + #define MCHBAR_CH1_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Byte_Group_Error_Status_MSK (0x1FF00000000) + #define MCHBAR_CH1_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Byte_Group_Error_Status_MAX (0x000001FF) + #define MCHBAR_CH1_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Byte_Group_Error_Status_DEF (0x00000000) + #define MCHBAR_CH1_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_WDB_Rd_Chunk_Num_Status_OFF (52) + #define MCHBAR_CH1_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_WDB_Rd_Chunk_Num_Status_WID ( 3) + #define MCHBAR_CH1_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_WDB_Rd_Chunk_Num_Status_MSK (0x70000000000000) + #define MCHBAR_CH1_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_WDB_Rd_Chunk_Num_Status_MAX (0x00000007) + #define MCHBAR_CH1_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_WDB_Rd_Chunk_Num_Status_DEF (0x00000000) + #define MCHBAR_CH1_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Nth_Error_OFF (56) + #define MCHBAR_CH1_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Nth_Error_WID ( 6) + #define MCHBAR_CH1_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Nth_Error_MSK (0x3F00000000000000) + #define MCHBAR_CH1_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Nth_Error_MAX (0x0000003F) + #define MCHBAR_CH1_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Nth_Error_DEF (0x00000000) + +#define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_0_REG (0x000044F0) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_0_Counter_Pointer_OFF ( 0) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_0_Counter_Pointer_WID ( 7) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_0_Counter_Pointer_MSK (0x0000007F) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_0_Counter_Pointer_MAX (0x0000007F) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_0_Counter_Pointer_DEF (0x0000007F) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_0_Counter_Control_OFF ( 7) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_0_Counter_Control_WID ( 2) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_0_Counter_Control_MSK (0x00000180) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_0_Counter_Control_MAX (0x00000003) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_0_Counter_Control_DEF (0x00000000) + +#define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_1_REG (0x000044F4) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_1_Counter_Pointer_OFF ( 0) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_1_Counter_Pointer_WID ( 7) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_1_Counter_Pointer_MSK (0x0000007F) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_1_Counter_Pointer_MAX (0x0000007F) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_1_Counter_Pointer_DEF (0x0000007F) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_1_Counter_Control_OFF ( 7) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_1_Counter_Control_WID ( 2) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_1_Counter_Control_MSK (0x00000180) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_1_Counter_Control_MAX (0x00000003) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_1_Counter_Control_DEF (0x00000000) + +#define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_2_REG (0x000044F8) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_2_Counter_Pointer_OFF ( 0) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_2_Counter_Pointer_WID ( 7) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_2_Counter_Pointer_MSK (0x0000007F) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_2_Counter_Pointer_MAX (0x0000007F) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_2_Counter_Pointer_DEF (0x0000007F) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_2_Counter_Control_OFF ( 7) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_2_Counter_Control_WID ( 2) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_2_Counter_Control_MSK (0x00000180) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_2_Counter_Control_MAX (0x00000003) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_2_Counter_Control_DEF (0x00000000) + +#define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_3_REG (0x000044FC) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_3_Counter_Pointer_OFF ( 0) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_3_Counter_Pointer_WID ( 7) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_3_Counter_Pointer_MSK (0x0000007F) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_3_Counter_Pointer_MAX (0x0000007F) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_3_Counter_Pointer_DEF (0x0000007F) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_3_Counter_Control_OFF ( 7) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_3_Counter_Control_WID ( 2) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_3_Counter_Control_MSK (0x00000180) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_3_Counter_Control_MAX (0x00000003) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_3_Counter_Control_DEF (0x00000000) + +#define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_4_REG (0x00004500) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_4_Counter_Pointer_OFF ( 0) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_4_Counter_Pointer_WID ( 7) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_4_Counter_Pointer_MSK (0x0000007F) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_4_Counter_Pointer_MAX (0x0000007F) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_4_Counter_Pointer_DEF (0x0000007F) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_4_Counter_Control_OFF ( 7) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_4_Counter_Control_WID ( 2) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_4_Counter_Control_MSK (0x00000180) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_4_Counter_Control_MAX (0x00000003) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_4_Counter_Control_DEF (0x00000000) + +#define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_5_REG (0x00004504) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_5_Counter_Pointer_OFF ( 0) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_5_Counter_Pointer_WID ( 7) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_5_Counter_Pointer_MSK (0x0000007F) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_5_Counter_Pointer_MAX (0x0000007F) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_5_Counter_Pointer_DEF (0x0000007F) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_5_Counter_Control_OFF ( 7) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_5_Counter_Control_WID ( 2) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_5_Counter_Control_MSK (0x00000180) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_5_Counter_Control_MAX (0x00000003) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_5_Counter_Control_DEF (0x00000000) + +#define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_6_REG (0x00004508) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_6_Counter_Pointer_OFF ( 0) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_6_Counter_Pointer_WID ( 7) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_6_Counter_Pointer_MSK (0x0000007F) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_6_Counter_Pointer_MAX (0x0000007F) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_6_Counter_Pointer_DEF (0x0000007F) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_6_Counter_Control_OFF ( 7) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_6_Counter_Control_WID ( 2) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_6_Counter_Control_MSK (0x00000180) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_6_Counter_Control_MAX (0x00000003) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_6_Counter_Control_DEF (0x00000000) + +#define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_7_REG (0x0000450C) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_7_Counter_Pointer_OFF ( 0) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_7_Counter_Pointer_WID ( 7) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_7_Counter_Pointer_MSK (0x0000007F) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_7_Counter_Pointer_MAX (0x0000007F) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_7_Counter_Pointer_DEF (0x0000007F) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_7_Counter_Control_OFF ( 7) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_7_Counter_Control_WID ( 2) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_7_Counter_Control_MSK (0x00000180) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_7_Counter_Control_MAX (0x00000003) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_7_Counter_Control_DEF (0x00000000) + +#define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_8_REG (0x00004510) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_8_Counter_Pointer_OFF ( 0) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_8_Counter_Pointer_WID ( 7) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_8_Counter_Pointer_MSK (0x0000007F) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_8_Counter_Pointer_MAX (0x0000007F) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_8_Counter_Pointer_DEF (0x0000007F) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_8_Counter_Control_OFF ( 7) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_8_Counter_Control_WID ( 2) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_8_Counter_Control_MSK (0x00000180) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_8_Counter_Control_MAX (0x00000003) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_8_Counter_Control_DEF (0x00000000) + +#define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_0_REG (0x00004514) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_0_Counter_Status_OFF ( 0) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_0_Counter_Status_WID (23) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_0_Counter_Status_MSK (0x007FFFFF) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_0_Counter_Status_MAX (0x007FFFFF) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_0_Counter_Status_DEF (0x00000000) + +#define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_1_REG (0x00004518) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_1_Counter_Status_OFF ( 0) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_1_Counter_Status_WID (23) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_1_Counter_Status_MSK (0x007FFFFF) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_1_Counter_Status_MAX (0x007FFFFF) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_1_Counter_Status_DEF (0x00000000) + +#define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_2_REG (0x0000451C) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_2_Counter_Status_OFF ( 0) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_2_Counter_Status_WID (23) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_2_Counter_Status_MSK (0x007FFFFF) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_2_Counter_Status_MAX (0x007FFFFF) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_2_Counter_Status_DEF (0x00000000) + +#define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_3_REG (0x00004520) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_3_Counter_Status_OFF ( 0) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_3_Counter_Status_WID (23) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_3_Counter_Status_MSK (0x007FFFFF) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_3_Counter_Status_MAX (0x007FFFFF) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_3_Counter_Status_DEF (0x00000000) + +#define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_4_REG (0x00004524) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_4_Counter_Status_OFF ( 0) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_4_Counter_Status_WID (23) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_4_Counter_Status_MSK (0x007FFFFF) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_4_Counter_Status_MAX (0x007FFFFF) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_4_Counter_Status_DEF (0x00000000) + +#define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_5_REG (0x00004528) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_5_Counter_Status_OFF ( 0) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_5_Counter_Status_WID (23) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_5_Counter_Status_MSK (0x007FFFFF) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_5_Counter_Status_MAX (0x007FFFFF) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_5_Counter_Status_DEF (0x00000000) + +#define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_6_REG (0x0000452C) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_6_Counter_Status_OFF ( 0) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_6_Counter_Status_WID (23) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_6_Counter_Status_MSK (0x007FFFFF) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_6_Counter_Status_MAX (0x007FFFFF) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_6_Counter_Status_DEF (0x00000000) + +#define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_7_REG (0x00004530) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_7_Counter_Status_OFF ( 0) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_7_Counter_Status_WID (23) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_7_Counter_Status_MSK (0x007FFFFF) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_7_Counter_Status_MAX (0x007FFFFF) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_7_Counter_Status_DEF (0x00000000) + +#define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_8_REG (0x00004534) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_8_Counter_Status_OFF ( 0) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_8_Counter_Status_WID (23) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_8_Counter_Status_MSK (0x007FFFFF) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_8_Counter_Status_MAX (0x007FFFFF) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_8_Counter_Status_DEF (0x00000000) + +#define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_OVERFLOW_STATUS_REG (0x00004538) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_OVERFLOW_STATUS_Counter_Overflow_Status_OFF ( 0) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_OVERFLOW_STATUS_Counter_Overflow_Status_WID ( 9) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_OVERFLOW_STATUS_Counter_Overflow_Status_MSK (0x000001FF) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_OVERFLOW_STATUS_Counter_Overflow_Status_MAX (0x000001FF) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_OVERFLOW_STATUS_Counter_Overflow_Status_DEF (0x00000000) + +#define MCHBAR_CH1_CR_REUT_CH_ERROR_ADDR_REG (0x00004580) + #define MCHBAR_CH1_CR_REUT_CH_ERROR_ADDR_Column_Address_OFF ( 0) + #define MCHBAR_CH1_CR_REUT_CH_ERROR_ADDR_Column_Address_WID (10) + #define MCHBAR_CH1_CR_REUT_CH_ERROR_ADDR_Column_Address_MSK (0x000003FF) + #define MCHBAR_CH1_CR_REUT_CH_ERROR_ADDR_Column_Address_MAX (0x000003FF) + #define MCHBAR_CH1_CR_REUT_CH_ERROR_ADDR_Column_Address_DEF (0x00000000) + #define MCHBAR_CH1_CR_REUT_CH_ERROR_ADDR_Row_Address_OFF (24) + #define MCHBAR_CH1_CR_REUT_CH_ERROR_ADDR_Row_Address_WID (16) + #define MCHBAR_CH1_CR_REUT_CH_ERROR_ADDR_Row_Address_MSK (0xFFFF000000) + #define MCHBAR_CH1_CR_REUT_CH_ERROR_ADDR_Row_Address_MAX (0x0000FFFF) + #define MCHBAR_CH1_CR_REUT_CH_ERROR_ADDR_Row_Address_DEF (0x00000000) + #define MCHBAR_CH1_CR_REUT_CH_ERROR_ADDR_Bank_Address_OFF (48) + #define MCHBAR_CH1_CR_REUT_CH_ERROR_ADDR_Bank_Address_WID ( 3) + #define MCHBAR_CH1_CR_REUT_CH_ERROR_ADDR_Bank_Address_MSK (0x7000000000000) + #define MCHBAR_CH1_CR_REUT_CH_ERROR_ADDR_Bank_Address_MAX (0x00000007) + #define MCHBAR_CH1_CR_REUT_CH_ERROR_ADDR_Bank_Address_DEF (0x00000000) + #define MCHBAR_CH1_CR_REUT_CH_ERROR_ADDR_Rank_Address_OFF (56) + #define MCHBAR_CH1_CR_REUT_CH_ERROR_ADDR_Rank_Address_WID ( 2) + #define MCHBAR_CH1_CR_REUT_CH_ERROR_ADDR_Rank_Address_MSK (0x300000000000000) + #define MCHBAR_CH1_CR_REUT_CH_ERROR_ADDR_Rank_Address_MAX (0x00000003) + #define MCHBAR_CH1_CR_REUT_CH_ERROR_ADDR_Rank_Address_DEF (0x00000000) + +#define MCHBAR_CH1_CR_REUT_CH_ERR_WDB_CAPTURE_STATUS_REG (0x00004588) + #define MCHBAR_CH1_CR_REUT_CH_ERR_WDB_CAPTURE_STATUS_WDB_Current_Error_Pointer_OFF ( 0) + #define MCHBAR_CH1_CR_REUT_CH_ERR_WDB_CAPTURE_STATUS_WDB_Current_Error_Pointer_WID ( 6) + #define MCHBAR_CH1_CR_REUT_CH_ERR_WDB_CAPTURE_STATUS_WDB_Current_Error_Pointer_MSK (0x0000003F) + #define MCHBAR_CH1_CR_REUT_CH_ERR_WDB_CAPTURE_STATUS_WDB_Current_Error_Pointer_MAX (0x0000003F) + #define MCHBAR_CH1_CR_REUT_CH_ERR_WDB_CAPTURE_STATUS_WDB_Current_Error_Pointer_DEF (0x00000000) + +#define MCHBAR_CH1_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_REG (0x0000458C) + #define MCHBAR_CH1_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_Enable_WDB_Error_Capture_OFF ( 0) + #define MCHBAR_CH1_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_Enable_WDB_Error_Capture_WID ( 1) + #define MCHBAR_CH1_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_Enable_WDB_Error_Capture_MSK (0x00000001) + #define MCHBAR_CH1_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_Enable_WDB_Error_Capture_MAX (0x00000001) + #define MCHBAR_CH1_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_Enable_WDB_Error_Capture_DEF (0x00000000) + #define MCHBAR_CH1_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_WDB_Starting_Error_Pointer_OFF ( 8) + #define MCHBAR_CH1_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_WDB_Starting_Error_Pointer_WID ( 6) + #define MCHBAR_CH1_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_WDB_Starting_Error_Pointer_MSK (0x00003F00) + #define MCHBAR_CH1_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_WDB_Starting_Error_Pointer_MAX (0x0000003F) + #define MCHBAR_CH1_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_WDB_Starting_Error_Pointer_DEF (0x00000000) + #define MCHBAR_CH1_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_WDB_Ending_Error_Pointer_OFF (16) + #define MCHBAR_CH1_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_WDB_Ending_Error_Pointer_WID ( 6) + #define MCHBAR_CH1_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_WDB_Ending_Error_Pointer_MSK (0x003F0000) + #define MCHBAR_CH1_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_WDB_Ending_Error_Pointer_MAX (0x0000003F) + #define MCHBAR_CH1_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_WDB_Ending_Error_Pointer_DEF (0x00000000) + +#define MCHBAR_CH1_CR_REUT_CH_MISC_CKE_CTRL_REG (0x00004590) + #define MCHBAR_CH1_CR_REUT_CH_MISC_CKE_CTRL_CKE_Override_OFF ( 0) + #define MCHBAR_CH1_CR_REUT_CH_MISC_CKE_CTRL_CKE_Override_WID ( 4) + #define MCHBAR_CH1_CR_REUT_CH_MISC_CKE_CTRL_CKE_Override_MSK (0x0000000F) + #define MCHBAR_CH1_CR_REUT_CH_MISC_CKE_CTRL_CKE_Override_MAX (0x0000000F) + #define MCHBAR_CH1_CR_REUT_CH_MISC_CKE_CTRL_CKE_Override_DEF (0x0000000F) + #define MCHBAR_CH1_CR_REUT_CH_MISC_CKE_CTRL_CKE_En_Start_Test_Sync_OFF ( 8) + #define MCHBAR_CH1_CR_REUT_CH_MISC_CKE_CTRL_CKE_En_Start_Test_Sync_WID ( 1) + #define MCHBAR_CH1_CR_REUT_CH_MISC_CKE_CTRL_CKE_En_Start_Test_Sync_MSK (0x00000100) + #define MCHBAR_CH1_CR_REUT_CH_MISC_CKE_CTRL_CKE_En_Start_Test_Sync_MAX (0x00000001) + #define MCHBAR_CH1_CR_REUT_CH_MISC_CKE_CTRL_CKE_En_Start_Test_Sync_DEF (0x00000000) + #define MCHBAR_CH1_CR_REUT_CH_MISC_CKE_CTRL_CKE_On_OFF (16) + #define MCHBAR_CH1_CR_REUT_CH_MISC_CKE_CTRL_CKE_On_WID ( 4) + #define MCHBAR_CH1_CR_REUT_CH_MISC_CKE_CTRL_CKE_On_MSK (0x000F0000) + #define MCHBAR_CH1_CR_REUT_CH_MISC_CKE_CTRL_CKE_On_MAX (0x0000000F) + #define MCHBAR_CH1_CR_REUT_CH_MISC_CKE_CTRL_CKE_On_DEF (0x00000000) + +#define MCHBAR_CH1_CR_REUT_CH_MISC_ODT_CTRL_REG (0x00004594) + #define MCHBAR_CH1_CR_REUT_CH_MISC_ODT_CTRL_ODT_Override_OFF ( 0) + #define MCHBAR_CH1_CR_REUT_CH_MISC_ODT_CTRL_ODT_Override_WID ( 4) + #define MCHBAR_CH1_CR_REUT_CH_MISC_ODT_CTRL_ODT_Override_MSK (0x0000000F) + #define MCHBAR_CH1_CR_REUT_CH_MISC_ODT_CTRL_ODT_Override_MAX (0x0000000F) + #define MCHBAR_CH1_CR_REUT_CH_MISC_ODT_CTRL_ODT_Override_DEF (0x0000000F) + #define MCHBAR_CH1_CR_REUT_CH_MISC_ODT_CTRL_ODT_On_OFF (16) + #define MCHBAR_CH1_CR_REUT_CH_MISC_ODT_CTRL_ODT_On_WID ( 4) + #define MCHBAR_CH1_CR_REUT_CH_MISC_ODT_CTRL_ODT_On_MSK (0x000F0000) + #define MCHBAR_CH1_CR_REUT_CH_MISC_ODT_CTRL_ODT_On_MAX (0x0000000F) + #define MCHBAR_CH1_CR_REUT_CH_MISC_ODT_CTRL_ODT_On_DEF (0x00000000) + #define MCHBAR_CH1_CR_REUT_CH_MISC_ODT_CTRL_MPR_Train_DDR_On_OFF (31) + #define MCHBAR_CH1_CR_REUT_CH_MISC_ODT_CTRL_MPR_Train_DDR_On_WID ( 1) + #define MCHBAR_CH1_CR_REUT_CH_MISC_ODT_CTRL_MPR_Train_DDR_On_MSK (0x80000000) + #define MCHBAR_CH1_CR_REUT_CH_MISC_ODT_CTRL_MPR_Train_DDR_On_MAX (0x00000001) + #define MCHBAR_CH1_CR_REUT_CH_MISC_ODT_CTRL_MPR_Train_DDR_On_DEF (0x00000000) + +#define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_REG (0x00004598) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_Enable_CADB_on_Deselect_OFF ( 0) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_Enable_CADB_on_Deselect_WID ( 1) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_Enable_CADB_on_Deselect_MSK (0x00000001) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_Enable_CADB_on_Deselect_MAX (0x00000001) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_Enable_CADB_on_Deselect_DEF (0x00000000) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_Enable_CADB_Always_On_OFF ( 1) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_Enable_CADB_Always_On_WID ( 1) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_Enable_CADB_Always_On_MSK (0x00000002) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_Enable_CADB_Always_On_MAX (0x00000001) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_Enable_CADB_Always_On_DEF (0x00000000) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_CMD_Deselect_Start_OFF ( 2) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_CMD_Deselect_Start_WID ( 4) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_CMD_Deselect_Start_MSK (0x0000003C) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_CMD_Deselect_Start_MAX (0x0000000F) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_CMD_Deselect_Start_DEF (0x00000000) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_CMD_Deselect_Stop_OFF ( 6) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_CMD_Deselect_Stop_WID ( 4) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_CMD_Deselect_Stop_MSK (0x000003C0) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_CMD_Deselect_Stop_MAX (0x0000000F) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_CMD_Deselect_Stop_DEF (0x00000000) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_Lane_Deselect_Enable_OFF ( 10) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_Lane_Deselect_Enable_WID ( 4) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_Lane_Deselect_Enable_MSK (0x00003C00) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_Lane_Deselect_Enable_MAX (0x0000000F) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_Lane_Deselect_Enable_DEF (0x00000000) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_CAS_Select_Enable_OFF ( 14) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_CAS_Select_Enable_WID ( 2) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_CAS_Select_Enable_MSK (0x0000C000) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_CAS_Select_Enable_MAX (0x00000003) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_CAS_Select_Enable_DEF (0x00000000) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_ACT_Select_Enable_OFF ( 16) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_ACT_Select_Enable_WID ( 2) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_ACT_Select_Enable_MSK (0x00030000) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_ACT_Select_Enable_MAX (0x00000003) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_ACT_Select_Enable_DEF (0x00000000) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_PRE_Select_Enable_OFF ( 18) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_PRE_Select_Enable_WID ( 2) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_PRE_Select_Enable_MSK (0x000C0000) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_PRE_Select_Enable_MAX (0x00000003) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_PRE_Select_Enable_DEF (0x00000000) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_Save_Current_Seed_OFF ( 20) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_Save_Current_Seed_WID ( 4) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_Save_Current_Seed_MSK (0x00F00000) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_Save_Current_Seed_MAX (0x0000000F) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_Save_Current_Seed_DEF (0x00000000) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_Reload_Starting_Seed_OFF ( 24) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_Reload_Starting_Seed_WID ( 4) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_Reload_Starting_Seed_MSK (0x0F000000) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_Reload_Starting_Seed_MAX (0x0000000F) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_Reload_Starting_Seed_DEF (0x00000000) + +#define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MRS_REG (0x0000459C) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MRS_MRS_Gap_OFF ( 0) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MRS_MRS_Gap_WID ( 3) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MRS_MRS_Gap_MSK (0x00000007) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MRS_MRS_Gap_MAX (0x00000007) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MRS_MRS_Gap_DEF (0x00000002) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_Start_Pointer_OFF ( 8) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_Start_Pointer_WID ( 3) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_Start_Pointer_MSK (0x00000700) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_Start_Pointer_MAX (0x00000007) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_Start_Pointer_DEF (0x00000000) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_End_Pointer_OFF (16) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_End_Pointer_WID ( 3) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_End_Pointer_MSK (0x00070000) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_End_Pointer_MAX (0x00000007) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_End_Pointer_DEF (0x00000007) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_Current_Pointer_OFF (24) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_Current_Pointer_WID ( 3) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_Current_Pointer_MSK (0x07000000) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_Current_Pointer_MAX (0x00000007) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_Current_Pointer_DEF (0x00000000) + +#define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_CTRL_REG (0x000045A0) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux0_Control_OFF ( 0) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux0_Control_WID ( 2) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux0_Control_MSK (0x00000003) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux0_Control_MAX (0x00000003) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux0_Control_DEF (0x00000001) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux1_Control_OFF ( 4) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux1_Control_WID ( 2) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux1_Control_MSK (0x00000030) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux1_Control_MAX (0x00000003) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux1_Control_DEF (0x00000001) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux2_Control_OFF ( 8) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux2_Control_WID ( 2) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux2_Control_MSK (0x00000300) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux2_Control_MAX (0x00000003) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux2_Control_DEF (0x00000001) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux0_Control_OFF ( 16) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux0_Control_WID ( 2) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux0_Control_MSK (0x00030000) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux0_Control_MAX (0x00000003) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux0_Control_DEF (0x00000001) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux1_Control_OFF ( 20) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux1_Control_WID ( 2) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux1_Control_MSK (0x00300000) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux1_Control_MAX (0x00000003) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux1_Control_DEF (0x00000001) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux2_Control_OFF ( 24) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux2_Control_WID ( 2) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux2_Control_MSK (0x03000000) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux2_Control_MAX (0x00000003) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux2_Control_DEF (0x00000001) + +#define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_PB_0_REG (0x000045A4) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_PB_0_Pattern_Buffer_OFF ( 0) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_PB_0_Pattern_Buffer_WID (16) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_PB_0_Pattern_Buffer_MSK (0x0000FFFF) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_PB_0_Pattern_Buffer_MAX (0x0000FFFF) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_PB_0_Pattern_Buffer_DEF (0x00000000) + +#define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_PB_1_REG (0x000045A8) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_PB_1_Pattern_Buffer_OFF ( 0) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_PB_1_Pattern_Buffer_WID (16) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_PB_1_Pattern_Buffer_MSK (0x0000FFFF) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_PB_1_Pattern_Buffer_MAX (0x0000FFFF) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_PB_1_Pattern_Buffer_DEF (0x00000000) + +#define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_PB_2_REG (0x000045AC) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_PB_2_Pattern_Buffer_OFF ( 0) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_PB_2_Pattern_Buffer_WID (16) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_PB_2_Pattern_Buffer_MSK (0x0000FFFF) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_PB_2_Pattern_Buffer_MAX (0x0000FFFF) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_PB_2_Pattern_Buffer_DEF (0x00000000) + +#define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_REG (0x000045B0) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_L_data_select_OFF ( 0) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_L_data_select_WID ( 1) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_L_data_select_MSK (0x00000001) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_L_data_select_MAX (0x00000001) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_L_data_select_DEF (0x00000000) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_Enable_Sweep_Frequency_OFF ( 1) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_Enable_Sweep_Frequency_WID ( 1) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_Enable_Sweep_Frequency_MSK (0x00000002) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_Enable_Sweep_Frequency_MAX (0x00000001) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_Enable_Sweep_Frequency_DEF (0x00000000) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_L_counter_OFF ( 8) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_L_counter_WID ( 8) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_L_counter_MSK (0x0000FF00) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_L_counter_MAX (0x000000FF) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_L_counter_DEF (0x00000001) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_M_counter_OFF (16) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_M_counter_WID ( 8) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_M_counter_MSK (0x00FF0000) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_M_counter_MAX (0x000000FF) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_M_counter_DEF (0x00000001) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_N_counter_OFF (24) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_N_counter_WID ( 8) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_N_counter_MSK (0xFF000000) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_N_counter_MAX (0x000000FF) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_N_counter_DEF (0x00000001) + +#define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_WRITE_POINTER_REG (0x000045BC) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_WRITE_POINTER_CADB_Write_Pointer_OFF ( 0) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_WRITE_POINTER_CADB_Write_Pointer_WID ( 3) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_WRITE_POINTER_CADB_Write_Pointer_MSK (0x00000007) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_WRITE_POINTER_CADB_Write_Pointer_MAX (0x00000007) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_WRITE_POINTER_CADB_Write_Pointer_DEF (0x00000000) + +#define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_PROG_REG (0x000045C0) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Address_OFF ( 0) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Address_WID (16) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Address_MSK (0x0000FFFF) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Address_MAX (0x0000FFFF) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Address_DEF (0x00000000) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Bank_OFF (24) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Bank_WID ( 3) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Bank_MSK (0x07000000) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Bank_MAX (0x00000007) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Bank_DEF (0x00000000) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_CS_OFF (32) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_CS_WID ( 4) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_CS_MSK (0xF00000000) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_CS_MAX (0x0000000F) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_CS_DEF (0x00000000) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Control_OFF (40) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Control_WID ( 3) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Control_MSK (0x70000000000) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Control_MAX (0x00000007) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Control_DEF (0x00000000) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_ODT_OFF (48) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_ODT_WID ( 4) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_ODT_MSK (0xF000000000000) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_ODT_MAX (0x0000000F) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_ODT_DEF (0x00000000) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_CKE_OFF (56) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_CKE_WID ( 4) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_CKE_MSK (0xF00000000000000) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_CKE_MAX (0x0000000F) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_CKE_DEF (0x00000000) + +#define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_0_REG (0x000045C8) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_0_Pattern_Buffer_OFF ( 0) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_0_Pattern_Buffer_WID (16) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_0_Pattern_Buffer_MSK (0x0000FFFF) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_0_Pattern_Buffer_MAX (0x0000FFFF) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_0_Pattern_Buffer_DEF (0x00000000) + +#define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_1_REG (0x000045CC) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_1_Pattern_Buffer_OFF ( 0) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_1_Pattern_Buffer_WID (16) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_1_Pattern_Buffer_MSK (0x0000FFFF) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_1_Pattern_Buffer_MAX (0x0000FFFF) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_1_Pattern_Buffer_DEF (0x00000000) + +#define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_2_REG (0x000045D0) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_2_Pattern_Buffer_OFF ( 0) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_2_Pattern_Buffer_WID (16) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_2_Pattern_Buffer_MSK (0x0000FFFF) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_2_Pattern_Buffer_MAX (0x0000FFFF) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_2_Pattern_Buffer_DEF (0x00000000) + +#define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_CTRL_REG (0x00004600) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Increment_Rate_OFF ( 0) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Increment_Rate_WID ( 5) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Increment_Rate_MSK (0x0000001F) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Increment_Rate_MAX (0x0000001F) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Increment_Rate_DEF (0x00000000) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Increment_Scale_OFF ( 5) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Increment_Scale_WID ( 1) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Increment_Scale_MSK (0x00000020) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Increment_Scale_MAX (0x00000001) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Increment_Scale_DEF (0x00000000) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Start_Pointer_OFF ( 8) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Start_Pointer_WID ( 6) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Start_Pointer_MSK (0x00003F00) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Start_Pointer_MAX (0x0000003F) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Start_Pointer_DEF (0x00000000) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_End_Pointer_OFF (16) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_End_Pointer_WID ( 6) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_End_Pointer_MSK (0x003F0000) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_End_Pointer_MAX (0x0000003F) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_End_Pointer_DEF (0x0000003F) + +#define MCHBAR_CH1_CR_REUT_CH_MISC_REFRESH_CTRL_REG (0x00004604) + #define MCHBAR_CH1_CR_REUT_CH_MISC_REFRESH_CTRL_Refresh_Rank_Mask_OFF ( 0) + #define MCHBAR_CH1_CR_REUT_CH_MISC_REFRESH_CTRL_Refresh_Rank_Mask_WID ( 4) + #define MCHBAR_CH1_CR_REUT_CH_MISC_REFRESH_CTRL_Refresh_Rank_Mask_MSK (0x0000000F) + #define MCHBAR_CH1_CR_REUT_CH_MISC_REFRESH_CTRL_Refresh_Rank_Mask_MAX (0x0000000F) + #define MCHBAR_CH1_CR_REUT_CH_MISC_REFRESH_CTRL_Refresh_Rank_Mask_DEF (0x00000000) + #define MCHBAR_CH1_CR_REUT_CH_MISC_REFRESH_CTRL_RefZQ_En_Start_Test_Sync_OFF ( 8) + #define MCHBAR_CH1_CR_REUT_CH_MISC_REFRESH_CTRL_RefZQ_En_Start_Test_Sync_WID ( 1) + #define MCHBAR_CH1_CR_REUT_CH_MISC_REFRESH_CTRL_RefZQ_En_Start_Test_Sync_MSK (0x00000100) + #define MCHBAR_CH1_CR_REUT_CH_MISC_REFRESH_CTRL_RefZQ_En_Start_Test_Sync_MAX (0x00000001) + #define MCHBAR_CH1_CR_REUT_CH_MISC_REFRESH_CTRL_RefZQ_En_Start_Test_Sync_DEF (0x00000000) + #define MCHBAR_CH1_CR_REUT_CH_MISC_REFRESH_CTRL_Panic_Refresh_Only_OFF (31) + #define MCHBAR_CH1_CR_REUT_CH_MISC_REFRESH_CTRL_Panic_Refresh_Only_WID ( 1) + #define MCHBAR_CH1_CR_REUT_CH_MISC_REFRESH_CTRL_Panic_Refresh_Only_MSK (0x80000000) + #define MCHBAR_CH1_CR_REUT_CH_MISC_REFRESH_CTRL_Panic_Refresh_Only_MAX (0x00000001) + #define MCHBAR_CH1_CR_REUT_CH_MISC_REFRESH_CTRL_Panic_Refresh_Only_DEF (0x00000000) + +#define MCHBAR_CH1_CR_REUT_CH_MISC_ZQ_CTRL_REG (0x00004608) + #define MCHBAR_CH1_CR_REUT_CH_MISC_ZQ_CTRL_ZQ_Rank_Mask_OFF ( 0) + #define MCHBAR_CH1_CR_REUT_CH_MISC_ZQ_CTRL_ZQ_Rank_Mask_WID ( 4) + #define MCHBAR_CH1_CR_REUT_CH_MISC_ZQ_CTRL_ZQ_Rank_Mask_MSK (0x0000000F) + #define MCHBAR_CH1_CR_REUT_CH_MISC_ZQ_CTRL_ZQ_Rank_Mask_MAX (0x0000000F) + #define MCHBAR_CH1_CR_REUT_CH_MISC_ZQ_CTRL_ZQ_Rank_Mask_DEF (0x00000000) + #define MCHBAR_CH1_CR_REUT_CH_MISC_ZQ_CTRL_Always_Do_ZQ_OFF (31) + #define MCHBAR_CH1_CR_REUT_CH_MISC_ZQ_CTRL_Always_Do_ZQ_WID ( 1) + #define MCHBAR_CH1_CR_REUT_CH_MISC_ZQ_CTRL_Always_Do_ZQ_MSK (0x80000000) + #define MCHBAR_CH1_CR_REUT_CH_MISC_ZQ_CTRL_Always_Do_ZQ_MAX (0x00000001) + #define MCHBAR_CH1_CR_REUT_CH_MISC_ZQ_CTRL_Always_Do_ZQ_DEF (0x00000000) + +#define MCHBAR_CH1_CR_LPDDR_MR_PARAMS_REG (0x00004610) + #define MCHBAR_CH1_CR_LPDDR_MR_PARAMS_Rank_0_x32_OFF ( 0) + #define MCHBAR_CH1_CR_LPDDR_MR_PARAMS_Rank_0_x32_WID ( 1) + #define MCHBAR_CH1_CR_LPDDR_MR_PARAMS_Rank_0_x32_MSK (0x00000001) + #define MCHBAR_CH1_CR_LPDDR_MR_PARAMS_Rank_0_x32_MAX (0x00000001) + #define MCHBAR_CH1_CR_LPDDR_MR_PARAMS_Rank_0_x32_DEF (0x00000000) + #define MCHBAR_CH1_CR_LPDDR_MR_PARAMS_Rank_1_x32_OFF ( 1) + #define MCHBAR_CH1_CR_LPDDR_MR_PARAMS_Rank_1_x32_WID ( 1) + #define MCHBAR_CH1_CR_LPDDR_MR_PARAMS_Rank_1_x32_MSK (0x00000002) + #define MCHBAR_CH1_CR_LPDDR_MR_PARAMS_Rank_1_x32_MAX (0x00000001) + #define MCHBAR_CH1_CR_LPDDR_MR_PARAMS_Rank_1_x32_DEF (0x00000000) + #define MCHBAR_CH1_CR_LPDDR_MR_PARAMS_Rank_2_x32_OFF ( 2) + #define MCHBAR_CH1_CR_LPDDR_MR_PARAMS_Rank_2_x32_WID ( 1) + #define MCHBAR_CH1_CR_LPDDR_MR_PARAMS_Rank_2_x32_MSK (0x00000004) + #define MCHBAR_CH1_CR_LPDDR_MR_PARAMS_Rank_2_x32_MAX (0x00000001) + #define MCHBAR_CH1_CR_LPDDR_MR_PARAMS_Rank_2_x32_DEF (0x00000000) + #define MCHBAR_CH1_CR_LPDDR_MR_PARAMS_Rank_3_x32_OFF ( 3) + #define MCHBAR_CH1_CR_LPDDR_MR_PARAMS_Rank_3_x32_WID ( 1) + #define MCHBAR_CH1_CR_LPDDR_MR_PARAMS_Rank_3_x32_MSK (0x00000008) + #define MCHBAR_CH1_CR_LPDDR_MR_PARAMS_Rank_3_x32_MAX (0x00000001) + #define MCHBAR_CH1_CR_LPDDR_MR_PARAMS_Rank_3_x32_DEF (0x00000000) + #define MCHBAR_CH1_CR_LPDDR_MR_PARAMS_LPDDR2_OFF ( 4) + #define MCHBAR_CH1_CR_LPDDR_MR_PARAMS_LPDDR2_WID ( 1) + #define MCHBAR_CH1_CR_LPDDR_MR_PARAMS_LPDDR2_MSK (0x00000010) + #define MCHBAR_CH1_CR_LPDDR_MR_PARAMS_LPDDR2_MAX (0x00000001) + #define MCHBAR_CH1_CR_LPDDR_MR_PARAMS_LPDDR2_DEF (0x00000000) + #define MCHBAR_CH1_CR_LPDDR_MR_PARAMS_MR4_PERIOD_OFF ( 8) + #define MCHBAR_CH1_CR_LPDDR_MR_PARAMS_MR4_PERIOD_WID (16) + #define MCHBAR_CH1_CR_LPDDR_MR_PARAMS_MR4_PERIOD_MSK (0x00FFFF00) + #define MCHBAR_CH1_CR_LPDDR_MR_PARAMS_MR4_PERIOD_MAX (0x0000FFFF) + #define MCHBAR_CH1_CR_LPDDR_MR_PARAMS_MR4_PERIOD_DEF (0x00000000) + +#define MCHBAR_CH1_CR_LPDDR_MR_COMMAND_REG (0x00004614) + #define MCHBAR_CH1_CR_LPDDR_MR_COMMAND_Address_OFF ( 0) + #define MCHBAR_CH1_CR_LPDDR_MR_COMMAND_Address_WID ( 8) + #define MCHBAR_CH1_CR_LPDDR_MR_COMMAND_Address_MSK (0x000000FF) + #define MCHBAR_CH1_CR_LPDDR_MR_COMMAND_Address_MAX (0x000000FF) + #define MCHBAR_CH1_CR_LPDDR_MR_COMMAND_Address_DEF (0x00000000) + #define MCHBAR_CH1_CR_LPDDR_MR_COMMAND_Data_OFF ( 8) + #define MCHBAR_CH1_CR_LPDDR_MR_COMMAND_Data_WID ( 8) + #define MCHBAR_CH1_CR_LPDDR_MR_COMMAND_Data_MSK (0x0000FF00) + #define MCHBAR_CH1_CR_LPDDR_MR_COMMAND_Data_MAX (0x000000FF) + #define MCHBAR_CH1_CR_LPDDR_MR_COMMAND_Data_DEF (0x00000000) + #define MCHBAR_CH1_CR_LPDDR_MR_COMMAND_Rank_OFF (16) + #define MCHBAR_CH1_CR_LPDDR_MR_COMMAND_Rank_WID ( 2) + #define MCHBAR_CH1_CR_LPDDR_MR_COMMAND_Rank_MSK (0x00030000) + #define MCHBAR_CH1_CR_LPDDR_MR_COMMAND_Rank_MAX (0x00000003) + #define MCHBAR_CH1_CR_LPDDR_MR_COMMAND_Rank_DEF (0x00000000) + #define MCHBAR_CH1_CR_LPDDR_MR_COMMAND_Write_OFF (18) + #define MCHBAR_CH1_CR_LPDDR_MR_COMMAND_Write_WID ( 1) + #define MCHBAR_CH1_CR_LPDDR_MR_COMMAND_Write_MSK (0x00040000) + #define MCHBAR_CH1_CR_LPDDR_MR_COMMAND_Write_MAX (0x00000001) + #define MCHBAR_CH1_CR_LPDDR_MR_COMMAND_Write_DEF (0x00000000) + #define MCHBAR_CH1_CR_LPDDR_MR_COMMAND_Init_MRW_OFF (19) + #define MCHBAR_CH1_CR_LPDDR_MR_COMMAND_Init_MRW_WID ( 1) + #define MCHBAR_CH1_CR_LPDDR_MR_COMMAND_Init_MRW_MSK (0x00080000) + #define MCHBAR_CH1_CR_LPDDR_MR_COMMAND_Init_MRW_MAX (0x00000001) + #define MCHBAR_CH1_CR_LPDDR_MR_COMMAND_Init_MRW_DEF (0x00000000) + #define MCHBAR_CH1_CR_LPDDR_MR_COMMAND_Busy_OFF (31) + #define MCHBAR_CH1_CR_LPDDR_MR_COMMAND_Busy_WID ( 1) + #define MCHBAR_CH1_CR_LPDDR_MR_COMMAND_Busy_MSK (0x80000000) + #define MCHBAR_CH1_CR_LPDDR_MR_COMMAND_Busy_MAX (0x00000001) + #define MCHBAR_CH1_CR_LPDDR_MR_COMMAND_Busy_DEF (0x00000000) + +#define MCHBAR_CH1_CR_LPDDR_MR_RESULT_REG (0x00004618) + #define MCHBAR_CH1_CR_LPDDR_MR_RESULT_Device_0_OFF ( 0) + #define MCHBAR_CH1_CR_LPDDR_MR_RESULT_Device_0_WID ( 8) + #define MCHBAR_CH1_CR_LPDDR_MR_RESULT_Device_0_MSK (0x000000FF) + #define MCHBAR_CH1_CR_LPDDR_MR_RESULT_Device_0_MAX (0x000000FF) + #define MCHBAR_CH1_CR_LPDDR_MR_RESULT_Device_0_DEF (0x00000000) + #define MCHBAR_CH1_CR_LPDDR_MR_RESULT_Device_1_OFF ( 8) + #define MCHBAR_CH1_CR_LPDDR_MR_RESULT_Device_1_WID ( 8) + #define MCHBAR_CH1_CR_LPDDR_MR_RESULT_Device_1_MSK (0x0000FF00) + #define MCHBAR_CH1_CR_LPDDR_MR_RESULT_Device_1_MAX (0x000000FF) + #define MCHBAR_CH1_CR_LPDDR_MR_RESULT_Device_1_DEF (0x00000000) + #define MCHBAR_CH1_CR_LPDDR_MR_RESULT_Device_2_OFF (16) + #define MCHBAR_CH1_CR_LPDDR_MR_RESULT_Device_2_WID ( 8) + #define MCHBAR_CH1_CR_LPDDR_MR_RESULT_Device_2_MSK (0x00FF0000) + #define MCHBAR_CH1_CR_LPDDR_MR_RESULT_Device_2_MAX (0x000000FF) + #define MCHBAR_CH1_CR_LPDDR_MR_RESULT_Device_2_DEF (0x00000000) + #define MCHBAR_CH1_CR_LPDDR_MR_RESULT_Device_3_OFF (24) + #define MCHBAR_CH1_CR_LPDDR_MR_RESULT_Device_3_WID ( 8) + #define MCHBAR_CH1_CR_LPDDR_MR_RESULT_Device_3_MSK (0xFF000000) + #define MCHBAR_CH1_CR_LPDDR_MR_RESULT_Device_3_MAX (0x000000FF) + #define MCHBAR_CH1_CR_LPDDR_MR_RESULT_Device_3_DEF (0x00000000) + +#define MCHBAR_CH1_CR_LPDDR_MR4_RANK_TEMPERATURE_REG (0x0000461C) + #define MCHBAR_CH1_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_0_OFF ( 0) + #define MCHBAR_CH1_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_0_WID ( 3) + #define MCHBAR_CH1_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_0_MSK (0x00000007) + #define MCHBAR_CH1_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_0_MAX (0x00000007) + #define MCHBAR_CH1_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_0_DEF (0x00000003) + #define MCHBAR_CH1_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_1_OFF ( 8) + #define MCHBAR_CH1_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_1_WID ( 3) + #define MCHBAR_CH1_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_1_MSK (0x00000700) + #define MCHBAR_CH1_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_1_MAX (0x00000007) + #define MCHBAR_CH1_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_1_DEF (0x00000003) + #define MCHBAR_CH1_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_2_OFF (16) + #define MCHBAR_CH1_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_2_WID ( 3) + #define MCHBAR_CH1_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_2_MSK (0x00070000) + #define MCHBAR_CH1_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_2_MAX (0x00000007) + #define MCHBAR_CH1_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_2_DEF (0x00000003) + #define MCHBAR_CH1_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_3_OFF (24) + #define MCHBAR_CH1_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_3_WID ( 3) + #define MCHBAR_CH1_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_3_MSK (0x07000000) + #define MCHBAR_CH1_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_3_MAX (0x00000007) + #define MCHBAR_CH1_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_3_DEF (0x00000003) + +#define MCHBAR_CH1_CR_DESWIZZLE_LOW_REG (0x00004620) + #define MCHBAR_CH1_CR_DESWIZZLE_LOW_Bit_0_OFF ( 0) + #define MCHBAR_CH1_CR_DESWIZZLE_LOW_Bit_0_WID ( 3) + #define MCHBAR_CH1_CR_DESWIZZLE_LOW_Bit_0_MSK (0x00000007) + #define MCHBAR_CH1_CR_DESWIZZLE_LOW_Bit_0_MAX (0x00000007) + #define MCHBAR_CH1_CR_DESWIZZLE_LOW_Bit_0_DEF (0x00000000) + #define MCHBAR_CH1_CR_DESWIZZLE_LOW_Bit_1_OFF ( 4) + #define MCHBAR_CH1_CR_DESWIZZLE_LOW_Bit_1_WID ( 3) + #define MCHBAR_CH1_CR_DESWIZZLE_LOW_Bit_1_MSK (0x00000070) + #define MCHBAR_CH1_CR_DESWIZZLE_LOW_Bit_1_MAX (0x00000007) + #define MCHBAR_CH1_CR_DESWIZZLE_LOW_Bit_1_DEF (0x00000001) + #define MCHBAR_CH1_CR_DESWIZZLE_LOW_Bit_2_OFF ( 8) + #define MCHBAR_CH1_CR_DESWIZZLE_LOW_Bit_2_WID ( 3) + #define MCHBAR_CH1_CR_DESWIZZLE_LOW_Bit_2_MSK (0x00000700) + #define MCHBAR_CH1_CR_DESWIZZLE_LOW_Bit_2_MAX (0x00000007) + #define MCHBAR_CH1_CR_DESWIZZLE_LOW_Bit_2_DEF (0x00000002) + #define MCHBAR_CH1_CR_DESWIZZLE_LOW_Bit_16_OFF (12) + #define MCHBAR_CH1_CR_DESWIZZLE_LOW_Bit_16_WID ( 3) + #define MCHBAR_CH1_CR_DESWIZZLE_LOW_Bit_16_MSK (0x00007000) + #define MCHBAR_CH1_CR_DESWIZZLE_LOW_Bit_16_MAX (0x00000007) + #define MCHBAR_CH1_CR_DESWIZZLE_LOW_Bit_16_DEF (0x00000000) + #define MCHBAR_CH1_CR_DESWIZZLE_LOW_Bit_17_OFF (16) + #define MCHBAR_CH1_CR_DESWIZZLE_LOW_Bit_17_WID ( 3) + #define MCHBAR_CH1_CR_DESWIZZLE_LOW_Bit_17_MSK (0x00070000) + #define MCHBAR_CH1_CR_DESWIZZLE_LOW_Bit_17_MAX (0x00000007) + #define MCHBAR_CH1_CR_DESWIZZLE_LOW_Bit_17_DEF (0x00000001) + #define MCHBAR_CH1_CR_DESWIZZLE_LOW_Bit_18_OFF (20) + #define MCHBAR_CH1_CR_DESWIZZLE_LOW_Bit_18_WID ( 3) + #define MCHBAR_CH1_CR_DESWIZZLE_LOW_Bit_18_MSK (0x00700000) + #define MCHBAR_CH1_CR_DESWIZZLE_LOW_Bit_18_MAX (0x00000007) + #define MCHBAR_CH1_CR_DESWIZZLE_LOW_Bit_18_DEF (0x00000002) + #define MCHBAR_CH1_CR_DESWIZZLE_LOW_Byte_0_OFF (24) + #define MCHBAR_CH1_CR_DESWIZZLE_LOW_Byte_0_WID ( 3) + #define MCHBAR_CH1_CR_DESWIZZLE_LOW_Byte_0_MSK (0x07000000) + #define MCHBAR_CH1_CR_DESWIZZLE_LOW_Byte_0_MAX (0x00000007) + #define MCHBAR_CH1_CR_DESWIZZLE_LOW_Byte_0_DEF (0x00000000) + #define MCHBAR_CH1_CR_DESWIZZLE_LOW_Byte_2_OFF (28) + #define MCHBAR_CH1_CR_DESWIZZLE_LOW_Byte_2_WID ( 3) + #define MCHBAR_CH1_CR_DESWIZZLE_LOW_Byte_2_MSK (0x70000000) + #define MCHBAR_CH1_CR_DESWIZZLE_LOW_Byte_2_MAX (0x00000007) + #define MCHBAR_CH1_CR_DESWIZZLE_LOW_Byte_2_DEF (0x00000002) + +#define MCHBAR_CH1_CR_DESWIZZLE_HIGH_REG (0x00004624) + #define MCHBAR_CH1_CR_DESWIZZLE_HIGH_Bit_32_OFF ( 0) + #define MCHBAR_CH1_CR_DESWIZZLE_HIGH_Bit_32_WID ( 3) + #define MCHBAR_CH1_CR_DESWIZZLE_HIGH_Bit_32_MSK (0x00000007) + #define MCHBAR_CH1_CR_DESWIZZLE_HIGH_Bit_32_MAX (0x00000007) + #define MCHBAR_CH1_CR_DESWIZZLE_HIGH_Bit_32_DEF (0x00000000) + #define MCHBAR_CH1_CR_DESWIZZLE_HIGH_Bit_33_OFF ( 4) + #define MCHBAR_CH1_CR_DESWIZZLE_HIGH_Bit_33_WID ( 3) + #define MCHBAR_CH1_CR_DESWIZZLE_HIGH_Bit_33_MSK (0x00000070) + #define MCHBAR_CH1_CR_DESWIZZLE_HIGH_Bit_33_MAX (0x00000007) + #define MCHBAR_CH1_CR_DESWIZZLE_HIGH_Bit_33_DEF (0x00000001) + #define MCHBAR_CH1_CR_DESWIZZLE_HIGH_Bit_34_OFF ( 8) + #define MCHBAR_CH1_CR_DESWIZZLE_HIGH_Bit_34_WID ( 3) + #define MCHBAR_CH1_CR_DESWIZZLE_HIGH_Bit_34_MSK (0x00000700) + #define MCHBAR_CH1_CR_DESWIZZLE_HIGH_Bit_34_MAX (0x00000007) + #define MCHBAR_CH1_CR_DESWIZZLE_HIGH_Bit_34_DEF (0x00000002) + #define MCHBAR_CH1_CR_DESWIZZLE_HIGH_Bit_48_OFF (12) + #define MCHBAR_CH1_CR_DESWIZZLE_HIGH_Bit_48_WID ( 3) + #define MCHBAR_CH1_CR_DESWIZZLE_HIGH_Bit_48_MSK (0x00007000) + #define MCHBAR_CH1_CR_DESWIZZLE_HIGH_Bit_48_MAX (0x00000007) + #define MCHBAR_CH1_CR_DESWIZZLE_HIGH_Bit_48_DEF (0x00000000) + #define MCHBAR_CH1_CR_DESWIZZLE_HIGH_Bit_49_OFF (16) + #define MCHBAR_CH1_CR_DESWIZZLE_HIGH_Bit_49_WID ( 3) + #define MCHBAR_CH1_CR_DESWIZZLE_HIGH_Bit_49_MSK (0x00070000) + #define MCHBAR_CH1_CR_DESWIZZLE_HIGH_Bit_49_MAX (0x00000007) + #define MCHBAR_CH1_CR_DESWIZZLE_HIGH_Bit_49_DEF (0x00000001) + #define MCHBAR_CH1_CR_DESWIZZLE_HIGH_Bit_50_OFF (20) + #define MCHBAR_CH1_CR_DESWIZZLE_HIGH_Bit_50_WID ( 3) + #define MCHBAR_CH1_CR_DESWIZZLE_HIGH_Bit_50_MSK (0x00700000) + #define MCHBAR_CH1_CR_DESWIZZLE_HIGH_Bit_50_MAX (0x00000007) + #define MCHBAR_CH1_CR_DESWIZZLE_HIGH_Bit_50_DEF (0x00000002) + #define MCHBAR_CH1_CR_DESWIZZLE_HIGH_Byte_4_OFF (24) + #define MCHBAR_CH1_CR_DESWIZZLE_HIGH_Byte_4_WID ( 3) + #define MCHBAR_CH1_CR_DESWIZZLE_HIGH_Byte_4_MSK (0x07000000) + #define MCHBAR_CH1_CR_DESWIZZLE_HIGH_Byte_4_MAX (0x00000007) + #define MCHBAR_CH1_CR_DESWIZZLE_HIGH_Byte_4_DEF (0x00000004) + #define MCHBAR_CH1_CR_DESWIZZLE_HIGH_Byte_6_OFF (28) + #define MCHBAR_CH1_CR_DESWIZZLE_HIGH_Byte_6_WID ( 3) + #define MCHBAR_CH1_CR_DESWIZZLE_HIGH_Byte_6_MSK (0x70000000) + #define MCHBAR_CH1_CR_DESWIZZLE_HIGH_Byte_6_MAX (0x00000007) + #define MCHBAR_CH1_CR_DESWIZZLE_HIGH_Byte_6_DEF (0x00000006) + +#define MCHBAR_CH1_CR_MC_REFRESH_STAGGER_REG (0x0000468C) + #define MCHBAR_CH1_CR_MC_REFRESH_STAGGER_Ref_Interval_OFF ( 0) + #define MCHBAR_CH1_CR_MC_REFRESH_STAGGER_Ref_Interval_WID (11) + #define MCHBAR_CH1_CR_MC_REFRESH_STAGGER_Ref_Interval_MSK (0x000007FF) + #define MCHBAR_CH1_CR_MC_REFRESH_STAGGER_Ref_Interval_MAX (0x000007FF) + #define MCHBAR_CH1_CR_MC_REFRESH_STAGGER_Ref_Interval_DEF (0x00000000) + #define MCHBAR_CH1_CR_MC_REFRESH_STAGGER_Ref_Stagger_En_OFF (11) + #define MCHBAR_CH1_CR_MC_REFRESH_STAGGER_Ref_Stagger_En_WID ( 1) + #define MCHBAR_CH1_CR_MC_REFRESH_STAGGER_Ref_Stagger_En_MSK (0x00000800) + #define MCHBAR_CH1_CR_MC_REFRESH_STAGGER_Ref_Stagger_En_MAX (0x00000001) + #define MCHBAR_CH1_CR_MC_REFRESH_STAGGER_Ref_Stagger_En_DEF (0x00000000) + #define MCHBAR_CH1_CR_MC_REFRESH_STAGGER_Ref_Stagger_Mode_OFF (12) + #define MCHBAR_CH1_CR_MC_REFRESH_STAGGER_Ref_Stagger_Mode_WID ( 1) + #define MCHBAR_CH1_CR_MC_REFRESH_STAGGER_Ref_Stagger_Mode_MSK (0x00001000) + #define MCHBAR_CH1_CR_MC_REFRESH_STAGGER_Ref_Stagger_Mode_MAX (0x00000001) + #define MCHBAR_CH1_CR_MC_REFRESH_STAGGER_Ref_Stagger_Mode_DEF (0x00000000) + #define MCHBAR_CH1_CR_MC_REFRESH_STAGGER_Disable_Stolen_Refresh_OFF (13) + #define MCHBAR_CH1_CR_MC_REFRESH_STAGGER_Disable_Stolen_Refresh_WID ( 1) + #define MCHBAR_CH1_CR_MC_REFRESH_STAGGER_Disable_Stolen_Refresh_MSK (0x00002000) + #define MCHBAR_CH1_CR_MC_REFRESH_STAGGER_Disable_Stolen_Refresh_MAX (0x00000001) + #define MCHBAR_CH1_CR_MC_REFRESH_STAGGER_Disable_Stolen_Refresh_DEF (0x00000000) + #define MCHBAR_CH1_CR_MC_REFRESH_STAGGER_En_Ref_Type_Display_OFF (14) + #define MCHBAR_CH1_CR_MC_REFRESH_STAGGER_En_Ref_Type_Display_WID ( 1) + #define MCHBAR_CH1_CR_MC_REFRESH_STAGGER_En_Ref_Type_Display_MSK (0x00004000) + #define MCHBAR_CH1_CR_MC_REFRESH_STAGGER_En_Ref_Type_Display_MAX (0x00000001) + #define MCHBAR_CH1_CR_MC_REFRESH_STAGGER_En_Ref_Type_Display_DEF (0x00000000) + +#define MCHBAR_CH1_CR_TC_ZQCAL_REG (0x00004690) + #define MCHBAR_CH1_CR_TC_ZQCAL_ZQCS_period_OFF ( 0) + #define MCHBAR_CH1_CR_TC_ZQCAL_ZQCS_period_WID ( 8) + #define MCHBAR_CH1_CR_TC_ZQCAL_ZQCS_period_MSK (0x000000FF) + #define MCHBAR_CH1_CR_TC_ZQCAL_ZQCS_period_MAX (0x000000FF) + #define MCHBAR_CH1_CR_TC_ZQCAL_ZQCS_period_DEF (0x00000080) + #define MCHBAR_CH1_CR_TC_ZQCAL_tZQCS_OFF ( 8) + #define MCHBAR_CH1_CR_TC_ZQCAL_tZQCS_WID ( 8) + #define MCHBAR_CH1_CR_TC_ZQCAL_tZQCS_MSK (0x0000FF00) + #define MCHBAR_CH1_CR_TC_ZQCAL_tZQCS_MAX (0x000000FF) + #define MCHBAR_CH1_CR_TC_ZQCAL_tZQCS_DEF (0x00000040) + #define MCHBAR_CH1_CR_TC_ZQCAL_ZQCS_period_Ult_OFF ( 0) + #define MCHBAR_CH1_CR_TC_ZQCAL_ZQCS_period_Ult_WID (10) + #define MCHBAR_CH1_CR_TC_ZQCAL_ZQCS_period_Ult_MSK (0x000003FF) + #define MCHBAR_CH1_CR_TC_ZQCAL_ZQCS_period_Ult_MAX (0x000003FF) + #define MCHBAR_CH1_CR_TC_ZQCAL_ZQCS_period_Ult_DEF (0x00000080) + #define MCHBAR_CH1_CR_TC_ZQCAL_tZQCS_Ult_OFF (10) + #define MCHBAR_CH1_CR_TC_ZQCAL_tZQCS_Ult_WID (10) + #define MCHBAR_CH1_CR_TC_ZQCAL_tZQCS_Ult_MSK (0x000FFC00) + #define MCHBAR_CH1_CR_TC_ZQCAL_tZQCS_Ult_MAX (0x000003FF) + #define MCHBAR_CH1_CR_TC_ZQCAL_tZQCS_Ult_DEF (0x00000040) + +#define MCHBAR_CH1_CR_TC_RFP_REG (0x00004694) + #define MCHBAR_CH1_CR_TC_RFP_OREF_RI_OFF ( 0) + #define MCHBAR_CH1_CR_TC_RFP_OREF_RI_WID ( 8) + #define MCHBAR_CH1_CR_TC_RFP_OREF_RI_MSK (0x000000FF) + #define MCHBAR_CH1_CR_TC_RFP_OREF_RI_MAX (0x000000FF) + #define MCHBAR_CH1_CR_TC_RFP_OREF_RI_DEF (0x0000000F) + #define MCHBAR_CH1_CR_TC_RFP_Refresh_HP_WM_OFF ( 8) + #define MCHBAR_CH1_CR_TC_RFP_Refresh_HP_WM_WID ( 4) + #define MCHBAR_CH1_CR_TC_RFP_Refresh_HP_WM_MSK (0x00000F00) + #define MCHBAR_CH1_CR_TC_RFP_Refresh_HP_WM_MAX (0x0000000F) + #define MCHBAR_CH1_CR_TC_RFP_Refresh_HP_WM_DEF (0x00000008) + #define MCHBAR_CH1_CR_TC_RFP_Refresh_panic_wm_OFF (12) + #define MCHBAR_CH1_CR_TC_RFP_Refresh_panic_wm_WID ( 4) + #define MCHBAR_CH1_CR_TC_RFP_Refresh_panic_wm_MSK (0x0000F000) + #define MCHBAR_CH1_CR_TC_RFP_Refresh_panic_wm_MAX (0x0000000F) + #define MCHBAR_CH1_CR_TC_RFP_Refresh_panic_wm_DEF (0x00000009) + +#define MCHBAR_CH1_CR_TC_RFTP_REG (0x00004698) + #define MCHBAR_CH1_CR_TC_RFTP_tREFI_OFF ( 0) + #define MCHBAR_CH1_CR_TC_RFTP_tREFI_WID (16) + #define MCHBAR_CH1_CR_TC_RFTP_tREFI_MSK (0x0000FFFF) + #define MCHBAR_CH1_CR_TC_RFTP_tREFI_MAX (0x0000FFFF) + #define MCHBAR_CH1_CR_TC_RFTP_tREFI_DEF (0x00001004) + #define MCHBAR_CH1_CR_TC_RFTP_tRFC_OFF (16) + #define MCHBAR_CH1_CR_TC_RFTP_tRFC_WID ( 9) + #define MCHBAR_CH1_CR_TC_RFTP_tRFC_MSK (0x01FF0000) + #define MCHBAR_CH1_CR_TC_RFTP_tRFC_MAX (0x000001FF) + #define MCHBAR_CH1_CR_TC_RFTP_tRFC_DEF (0x000000B4) + #define MCHBAR_CH1_CR_TC_RFTP_tREFIx9_OFF (25) + #define MCHBAR_CH1_CR_TC_RFTP_tREFIx9_WID ( 7) + #define MCHBAR_CH1_CR_TC_RFTP_tREFIx9_MSK (0xFE000000) + #define MCHBAR_CH1_CR_TC_RFTP_tREFIx9_MAX (0x0000007F) + #define MCHBAR_CH1_CR_TC_RFTP_tREFIx9_DEF (0x00000023) + +#define MCHBAR_CH1_CR_TC_MR2_SHADDOW_REG (0x0000469C) + #define MCHBAR_CH1_CR_TC_MR2_SHADDOW_MR2_sh_low_OFF ( 0) + #define MCHBAR_CH1_CR_TC_MR2_SHADDOW_MR2_sh_low_WID ( 6) + #define MCHBAR_CH1_CR_TC_MR2_SHADDOW_MR2_sh_low_MSK (0x0000003F) + #define MCHBAR_CH1_CR_TC_MR2_SHADDOW_MR2_sh_low_MAX (0x0000003F) + #define MCHBAR_CH1_CR_TC_MR2_SHADDOW_MR2_sh_low_DEF (0x00000000) + #define MCHBAR_CH1_CR_TC_MR2_SHADDOW_SRT_avail_OFF ( 6) + #define MCHBAR_CH1_CR_TC_MR2_SHADDOW_SRT_avail_WID ( 2) + #define MCHBAR_CH1_CR_TC_MR2_SHADDOW_SRT_avail_MSK (0x000000C0) + #define MCHBAR_CH1_CR_TC_MR2_SHADDOW_SRT_avail_MAX (0x00000003) + #define MCHBAR_CH1_CR_TC_MR2_SHADDOW_SRT_avail_DEF (0x00000000) + #define MCHBAR_CH1_CR_TC_MR2_SHADDOW_MR2_sh_high_OFF ( 8) + #define MCHBAR_CH1_CR_TC_MR2_SHADDOW_MR2_sh_high_WID ( 3) + #define MCHBAR_CH1_CR_TC_MR2_SHADDOW_MR2_sh_high_MSK (0x00000700) + #define MCHBAR_CH1_CR_TC_MR2_SHADDOW_MR2_sh_high_MAX (0x00000007) + #define MCHBAR_CH1_CR_TC_MR2_SHADDOW_MR2_sh_high_DEF (0x00000000) + #define MCHBAR_CH1_CR_TC_MR2_SHADDOW_Addr_bit_swizzle_OFF (14) + #define MCHBAR_CH1_CR_TC_MR2_SHADDOW_Addr_bit_swizzle_WID ( 2) + #define MCHBAR_CH1_CR_TC_MR2_SHADDOW_Addr_bit_swizzle_MSK (0x0000C000) + #define MCHBAR_CH1_CR_TC_MR2_SHADDOW_Addr_bit_swizzle_MAX (0x00000003) + #define MCHBAR_CH1_CR_TC_MR2_SHADDOW_Addr_bit_swizzle_DEF (0x00000000) + +#define MCHBAR_CH1_CR_MC_INIT_STATE_REG (0x000046A0) + #define MCHBAR_CH1_CR_MC_INIT_STATE_Rank_occupancy_OFF ( 0) + #define MCHBAR_CH1_CR_MC_INIT_STATE_Rank_occupancy_WID ( 4) + #define MCHBAR_CH1_CR_MC_INIT_STATE_Rank_occupancy_MSK (0x0000000F) + #define MCHBAR_CH1_CR_MC_INIT_STATE_Rank_occupancy_MAX (0x0000000F) + #define MCHBAR_CH1_CR_MC_INIT_STATE_Rank_occupancy_DEF (0x0000000F) + +#define MCHBAR_CH1_CR_TC_SRFTP_REG (0x000046A4) + #define MCHBAR_CH1_CR_TC_SRFTP_tXSDLL_OFF ( 0) + #define MCHBAR_CH1_CR_TC_SRFTP_tXSDLL_WID (12) + #define MCHBAR_CH1_CR_TC_SRFTP_tXSDLL_MSK (0x00000FFF) + #define MCHBAR_CH1_CR_TC_SRFTP_tXSDLL_MAX (0x00000FFF) + #define MCHBAR_CH1_CR_TC_SRFTP_tXSDLL_DEF (0x00000200) + #define MCHBAR_CH1_CR_TC_SRFTP_tXS_offset_OFF (12) + #define MCHBAR_CH1_CR_TC_SRFTP_tXS_offset_WID ( 4) + #define MCHBAR_CH1_CR_TC_SRFTP_tXS_offset_MSK (0x0000F000) + #define MCHBAR_CH1_CR_TC_SRFTP_tXS_offset_MAX (0x0000000F) + #define MCHBAR_CH1_CR_TC_SRFTP_tXS_offset_DEF (0x0000000B) + #define MCHBAR_CH1_CR_TC_SRFTP_tZQOPER_OFF (16) + #define MCHBAR_CH1_CR_TC_SRFTP_tZQOPER_WID (10) + #define MCHBAR_CH1_CR_TC_SRFTP_tZQOPER_MSK (0x03FF0000) + #define MCHBAR_CH1_CR_TC_SRFTP_tZQOPER_MAX (0x000003FF) + #define MCHBAR_CH1_CR_TC_SRFTP_tZQOPER_DEF (0x00000100) + #define MCHBAR_CH1_CR_TC_SRFTP_tMOD_OFF (28) + #define MCHBAR_CH1_CR_TC_SRFTP_tMOD_WID ( 4) + #define MCHBAR_CH1_CR_TC_SRFTP_tMOD_MSK (0xF0000000) + #define MCHBAR_CH1_CR_TC_SRFTP_tMOD_MAX (0x0000000F) + #define MCHBAR_CH1_CR_TC_SRFTP_tMOD_DEF (0x00000000) + +#define MCHBAR_CH1_CR_WDB_VISA_SEL_REG (0x000046A8) + #define MCHBAR_CH1_CR_WDB_VISA_SEL_VISAByteSel_OFF ( 0) + #define MCHBAR_CH1_CR_WDB_VISA_SEL_VISAByteSel_WID ( 3) + #define MCHBAR_CH1_CR_WDB_VISA_SEL_VISAByteSel_MSK (0x00000007) + #define MCHBAR_CH1_CR_WDB_VISA_SEL_VISAByteSel_MAX (0x00000007) + #define MCHBAR_CH1_CR_WDB_VISA_SEL_VISAByteSel_DEF (0x00000000) + +#define MCHBAR_CH1_CR_DCLK_LDAT_PDAT_REG (0x000046C0) + #define MCHBAR_CH1_CR_DCLK_LDAT_PDAT_FASTADDR_OFF ( 0) + #define MCHBAR_CH1_CR_DCLK_LDAT_PDAT_FASTADDR_WID (12) + #define MCHBAR_CH1_CR_DCLK_LDAT_PDAT_FASTADDR_MSK (0x00000FFF) + #define MCHBAR_CH1_CR_DCLK_LDAT_PDAT_FASTADDR_MAX (0x00000FFF) + #define MCHBAR_CH1_CR_DCLK_LDAT_PDAT_FASTADDR_DEF (0x00000000) + #define MCHBAR_CH1_CR_DCLK_LDAT_PDAT_ADDREN_OFF (16) + #define MCHBAR_CH1_CR_DCLK_LDAT_PDAT_ADDREN_WID ( 1) + #define MCHBAR_CH1_CR_DCLK_LDAT_PDAT_ADDREN_MSK (0x00010000) + #define MCHBAR_CH1_CR_DCLK_LDAT_PDAT_ADDREN_MAX (0x00000001) + #define MCHBAR_CH1_CR_DCLK_LDAT_PDAT_ADDREN_DEF (0x00000000) + #define MCHBAR_CH1_CR_DCLK_LDAT_PDAT_SEQEN_OFF (17) + #define MCHBAR_CH1_CR_DCLK_LDAT_PDAT_SEQEN_WID ( 1) + #define MCHBAR_CH1_CR_DCLK_LDAT_PDAT_SEQEN_MSK (0x00020000) + #define MCHBAR_CH1_CR_DCLK_LDAT_PDAT_SEQEN_MAX (0x00000001) + #define MCHBAR_CH1_CR_DCLK_LDAT_PDAT_SEQEN_DEF (0x00000000) + #define MCHBAR_CH1_CR_DCLK_LDAT_PDAT_POL0_OFF (18) + #define MCHBAR_CH1_CR_DCLK_LDAT_PDAT_POL0_WID ( 1) + #define MCHBAR_CH1_CR_DCLK_LDAT_PDAT_POL0_MSK (0x00040000) + #define MCHBAR_CH1_CR_DCLK_LDAT_PDAT_POL0_MAX (0x00000001) + #define MCHBAR_CH1_CR_DCLK_LDAT_PDAT_POL0_DEF (0x00000000) + #define MCHBAR_CH1_CR_DCLK_LDAT_PDAT_POL1_OFF (19) + #define MCHBAR_CH1_CR_DCLK_LDAT_PDAT_POL1_WID ( 1) + #define MCHBAR_CH1_CR_DCLK_LDAT_PDAT_POL1_MSK (0x00080000) + #define MCHBAR_CH1_CR_DCLK_LDAT_PDAT_POL1_MAX (0x00000001) + #define MCHBAR_CH1_CR_DCLK_LDAT_PDAT_POL1_DEF (0x00000000) + #define MCHBAR_CH1_CR_DCLK_LDAT_PDAT_CMDA_OFF (20) + #define MCHBAR_CH1_CR_DCLK_LDAT_PDAT_CMDA_WID ( 4) + #define MCHBAR_CH1_CR_DCLK_LDAT_PDAT_CMDA_MSK (0x00F00000) + #define MCHBAR_CH1_CR_DCLK_LDAT_PDAT_CMDA_MAX (0x0000000F) + #define MCHBAR_CH1_CR_DCLK_LDAT_PDAT_CMDA_DEF (0x00000000) + #define MCHBAR_CH1_CR_DCLK_LDAT_PDAT_CMDB_OFF (24) + #define MCHBAR_CH1_CR_DCLK_LDAT_PDAT_CMDB_WID ( 4) + #define MCHBAR_CH1_CR_DCLK_LDAT_PDAT_CMDB_MSK (0x0F000000) + #define MCHBAR_CH1_CR_DCLK_LDAT_PDAT_CMDB_MAX (0x0000000F) + #define MCHBAR_CH1_CR_DCLK_LDAT_PDAT_CMDB_DEF (0x00000000) + #define MCHBAR_CH1_CR_DCLK_LDAT_PDAT_CMDC_OFF (28) + #define MCHBAR_CH1_CR_DCLK_LDAT_PDAT_CMDC_WID ( 4) + #define MCHBAR_CH1_CR_DCLK_LDAT_PDAT_CMDC_MSK (0xF0000000) + #define MCHBAR_CH1_CR_DCLK_LDAT_PDAT_CMDC_MAX (0x0000000F) + #define MCHBAR_CH1_CR_DCLK_LDAT_PDAT_CMDC_DEF (0x00000000) + +#define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_REG (0x000046C4) + #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_BANKSEL_OFF ( 0) + #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_BANKSEL_WID ( 4) + #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_BANKSEL_MSK (0x0000000F) + #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_BANKSEL_MAX (0x0000000F) + #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_BANKSEL_DEF (0x00000000) + #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_ARRAYSEL_OFF ( 5) + #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_ARRAYSEL_WID ( 5) + #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_ARRAYSEL_MSK (0x000003E0) + #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_ARRAYSEL_MAX (0x0000001F) + #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_ARRAYSEL_DEF (0x00000000) + #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_CMP_OFF (10) + #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_CMP_WID ( 1) + #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_CMP_MSK (0x00000400) + #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_CMP_MAX (0x00000001) + #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_CMP_DEF (0x00000000) + #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_REP_OFF (11) + #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_REP_WID ( 1) + #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_REP_MSK (0x00000800) + #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_REP_MAX (0x00000001) + #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_REP_DEF (0x00000000) + #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_DWORD_OFF (12) + #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_DWORD_WID ( 4) + #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_DWORD_MSK (0x0000F000) + #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_DWORD_MAX (0x0000000F) + #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_DWORD_DEF (0x00000000) + #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_MODE_OFF (16) + #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_MODE_WID ( 2) + #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_MODE_MSK (0x00030000) + #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_MODE_MAX (0x00000003) + #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_MODE_DEF (0x00000000) + #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_MPMAP_OFF (18) + #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_MPMAP_WID ( 6) + #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_MPMAP_MSK (0x00FC0000) + #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_MPMAP_MAX (0x0000003F) + #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_MPMAP_DEF (0x00000000) + #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_MPBOFFSET_OFF (24) + #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_MPBOFFSET_WID ( 4) + #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_MPBOFFSET_MSK (0x0F000000) + #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_MPBOFFSET_MAX (0x0000000F) + #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_MPBOFFSET_DEF (0x00000000) + #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_STAGE_EN_OFF (28) + #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_STAGE_EN_WID ( 1) + #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_STAGE_EN_MSK (0x10000000) + #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_STAGE_EN_MAX (0x00000001) + #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_STAGE_EN_DEF (0x00000000) + #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_SHADOW_OFF (29) + #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_SHADOW_WID ( 2) + #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_SHADOW_MSK (0x60000000) + #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_SHADOW_MAX (0x00000003) + #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_SHADOW_DEF (0x00000000) + +#define MCHBAR_CH1_CR_DCLK_LDAT_DATAOUT_REG (0x000046C8) + #define MCHBAR_CH1_CR_DCLK_LDAT_DATAOUT_DATOUT_OFF ( 0) + #define MCHBAR_CH1_CR_DCLK_LDAT_DATAOUT_DATOUT_WID (32) + #define MCHBAR_CH1_CR_DCLK_LDAT_DATAOUT_DATOUT_MSK (0xFFFFFFFF) + #define MCHBAR_CH1_CR_DCLK_LDAT_DATAOUT_DATOUT_MAX (0xFFFFFFFF) + #define MCHBAR_CH1_CR_DCLK_LDAT_DATAOUT_DATOUT_DEF (0x00000000) + +#define MCHBAR_CH1_CR_DCLK_LDAT_DATAIN_0_REG (0x000046CC) + #define MCHBAR_CH1_CR_DCLK_LDAT_DATAIN_0_DATIN_OFF ( 0) + #define MCHBAR_CH1_CR_DCLK_LDAT_DATAIN_0_DATIN_WID (32) + #define MCHBAR_CH1_CR_DCLK_LDAT_DATAIN_0_DATIN_MSK (0xFFFFFFFF) + #define MCHBAR_CH1_CR_DCLK_LDAT_DATAIN_0_DATIN_MAX (0xFFFFFFFF) + #define MCHBAR_CH1_CR_DCLK_LDAT_DATAIN_0_DATIN_DEF (0x00000000) + +#define MCHBAR_CH1_CR_QCLK_LDAT_PDAT_REG (0x000046D0) + #define MCHBAR_CH1_CR_QCLK_LDAT_PDAT_FASTADDR_OFF ( 0) + #define MCHBAR_CH1_CR_QCLK_LDAT_PDAT_FASTADDR_WID (12) + #define MCHBAR_CH1_CR_QCLK_LDAT_PDAT_FASTADDR_MSK (0x00000FFF) + #define MCHBAR_CH1_CR_QCLK_LDAT_PDAT_FASTADDR_MAX (0x00000FFF) + #define MCHBAR_CH1_CR_QCLK_LDAT_PDAT_FASTADDR_DEF (0x00000000) + #define MCHBAR_CH1_CR_QCLK_LDAT_PDAT_ADDREN_OFF (16) + #define MCHBAR_CH1_CR_QCLK_LDAT_PDAT_ADDREN_WID ( 1) + #define MCHBAR_CH1_CR_QCLK_LDAT_PDAT_ADDREN_MSK (0x00010000) + #define MCHBAR_CH1_CR_QCLK_LDAT_PDAT_ADDREN_MAX (0x00000001) + #define MCHBAR_CH1_CR_QCLK_LDAT_PDAT_ADDREN_DEF (0x00000000) + #define MCHBAR_CH1_CR_QCLK_LDAT_PDAT_SEQEN_OFF (17) + #define MCHBAR_CH1_CR_QCLK_LDAT_PDAT_SEQEN_WID ( 1) + #define MCHBAR_CH1_CR_QCLK_LDAT_PDAT_SEQEN_MSK (0x00020000) + #define MCHBAR_CH1_CR_QCLK_LDAT_PDAT_SEQEN_MAX (0x00000001) + #define MCHBAR_CH1_CR_QCLK_LDAT_PDAT_SEQEN_DEF (0x00000000) + #define MCHBAR_CH1_CR_QCLK_LDAT_PDAT_POL0_OFF (18) + #define MCHBAR_CH1_CR_QCLK_LDAT_PDAT_POL0_WID ( 1) + #define MCHBAR_CH1_CR_QCLK_LDAT_PDAT_POL0_MSK (0x00040000) + #define MCHBAR_CH1_CR_QCLK_LDAT_PDAT_POL0_MAX (0x00000001) + #define MCHBAR_CH1_CR_QCLK_LDAT_PDAT_POL0_DEF (0x00000000) + #define MCHBAR_CH1_CR_QCLK_LDAT_PDAT_POL1_OFF (19) + #define MCHBAR_CH1_CR_QCLK_LDAT_PDAT_POL1_WID ( 1) + #define MCHBAR_CH1_CR_QCLK_LDAT_PDAT_POL1_MSK (0x00080000) + #define MCHBAR_CH1_CR_QCLK_LDAT_PDAT_POL1_MAX (0x00000001) + #define MCHBAR_CH1_CR_QCLK_LDAT_PDAT_POL1_DEF (0x00000000) + #define MCHBAR_CH1_CR_QCLK_LDAT_PDAT_CMDA_OFF (20) + #define MCHBAR_CH1_CR_QCLK_LDAT_PDAT_CMDA_WID ( 4) + #define MCHBAR_CH1_CR_QCLK_LDAT_PDAT_CMDA_MSK (0x00F00000) + #define MCHBAR_CH1_CR_QCLK_LDAT_PDAT_CMDA_MAX (0x0000000F) + #define MCHBAR_CH1_CR_QCLK_LDAT_PDAT_CMDA_DEF (0x00000000) + #define MCHBAR_CH1_CR_QCLK_LDAT_PDAT_CMDB_OFF (24) + #define MCHBAR_CH1_CR_QCLK_LDAT_PDAT_CMDB_WID ( 4) + #define MCHBAR_CH1_CR_QCLK_LDAT_PDAT_CMDB_MSK (0x0F000000) + #define MCHBAR_CH1_CR_QCLK_LDAT_PDAT_CMDB_MAX (0x0000000F) + #define MCHBAR_CH1_CR_QCLK_LDAT_PDAT_CMDB_DEF (0x00000000) + #define MCHBAR_CH1_CR_QCLK_LDAT_PDAT_CMDC_OFF (28) + #define MCHBAR_CH1_CR_QCLK_LDAT_PDAT_CMDC_WID ( 4) + #define MCHBAR_CH1_CR_QCLK_LDAT_PDAT_CMDC_MSK (0xF0000000) + #define MCHBAR_CH1_CR_QCLK_LDAT_PDAT_CMDC_MAX (0x0000000F) + #define MCHBAR_CH1_CR_QCLK_LDAT_PDAT_CMDC_DEF (0x00000000) + +#define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_REG (0x000046D4) + #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_BANKSEL_OFF ( 0) + #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_BANKSEL_WID ( 4) + #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_BANKSEL_MSK (0x0000000F) + #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_BANKSEL_MAX (0x0000000F) + #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_BANKSEL_DEF (0x00000000) + #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_ARRAYSEL_OFF ( 5) + #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_ARRAYSEL_WID ( 5) + #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_ARRAYSEL_MSK (0x000003E0) + #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_ARRAYSEL_MAX (0x0000001F) + #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_ARRAYSEL_DEF (0x00000000) + #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_CMP_OFF (10) + #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_CMP_WID ( 1) + #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_CMP_MSK (0x00000400) + #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_CMP_MAX (0x00000001) + #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_CMP_DEF (0x00000000) + #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_REP_OFF (11) + #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_REP_WID ( 1) + #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_REP_MSK (0x00000800) + #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_REP_MAX (0x00000001) + #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_REP_DEF (0x00000000) + #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_DWORD_OFF (12) + #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_DWORD_WID ( 4) + #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_DWORD_MSK (0x0000F000) + #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_DWORD_MAX (0x0000000F) + #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_DWORD_DEF (0x00000000) + #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_MODE_OFF (16) + #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_MODE_WID ( 2) + #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_MODE_MSK (0x00030000) + #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_MODE_MAX (0x00000003) + #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_MODE_DEF (0x00000000) + #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_MPMAP_OFF (18) + #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_MPMAP_WID ( 6) + #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_MPMAP_MSK (0x00FC0000) + #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_MPMAP_MAX (0x0000003F) + #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_MPMAP_DEF (0x00000000) + #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_MPBOFFSET_OFF (24) + #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_MPBOFFSET_WID ( 4) + #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_MPBOFFSET_MSK (0x0F000000) + #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_MPBOFFSET_MAX (0x0000000F) + #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_MPBOFFSET_DEF (0x00000000) + #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_STAGE_EN_OFF (28) + #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_STAGE_EN_WID ( 1) + #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_STAGE_EN_MSK (0x10000000) + #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_STAGE_EN_MAX (0x00000001) + #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_STAGE_EN_DEF (0x00000000) + #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_SHADOW_OFF (29) + #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_SHADOW_WID ( 2) + #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_SHADOW_MSK (0x60000000) + #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_SHADOW_MAX (0x00000003) + #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_SHADOW_DEF (0x00000000) + +#define MCHBAR_CH1_CR_QCLK_LDAT_DATAOUT_REG (0x000046D8) + #define MCHBAR_CH1_CR_QCLK_LDAT_DATAOUT_DATOUT_OFF ( 0) + #define MCHBAR_CH1_CR_QCLK_LDAT_DATAOUT_DATOUT_WID (32) + #define MCHBAR_CH1_CR_QCLK_LDAT_DATAOUT_DATOUT_MSK (0xFFFFFFFF) + #define MCHBAR_CH1_CR_QCLK_LDAT_DATAOUT_DATOUT_MAX (0xFFFFFFFF) + #define MCHBAR_CH1_CR_QCLK_LDAT_DATAOUT_DATOUT_DEF (0x00000000) + +#define MCHBAR_CH1_CR_QCLK_LDAT_DATAIN_0_REG (0x000046DC) + #define MCHBAR_CH1_CR_QCLK_LDAT_DATAIN_0_DATIN_OFF ( 0) + #define MCHBAR_CH1_CR_QCLK_LDAT_DATAIN_0_DATIN_WID (32) + #define MCHBAR_CH1_CR_QCLK_LDAT_DATAIN_0_DATIN_MSK (0xFFFFFFFF) + #define MCHBAR_CH1_CR_QCLK_LDAT_DATAIN_0_DATIN_MAX (0xFFFFFFFF) + #define MCHBAR_CH1_CR_QCLK_LDAT_DATAIN_0_DATIN_DEF (0x00000000) + +#define MCHBAR_CH1_CR_QCLK_LDAT_DATAIN_1_REG (0x000046E0) + #define MCHBAR_CH1_CR_QCLK_LDAT_DATAIN_1_DATIN_OFF ( 0) + #define MCHBAR_CH1_CR_QCLK_LDAT_DATAIN_1_DATIN_WID (32) + #define MCHBAR_CH1_CR_QCLK_LDAT_DATAIN_1_DATIN_MSK (0xFFFFFFFF) + #define MCHBAR_CH1_CR_QCLK_LDAT_DATAIN_1_DATIN_MAX (0xFFFFFFFF) + #define MCHBAR_CH1_CR_QCLK_LDAT_DATAIN_1_DATIN_DEF (0x00000000) + +#define MCHBAR_CH1_CR_QUEUE_ENTRY_DISABLE_RPQ_REG (0x000046E4) + #define MCHBAR_CH1_CR_QUEUE_ENTRY_DISABLE_RPQ_RPQ_disable_OFF ( 0) + #define MCHBAR_CH1_CR_QUEUE_ENTRY_DISABLE_RPQ_RPQ_disable_WID (28) + #define MCHBAR_CH1_CR_QUEUE_ENTRY_DISABLE_RPQ_RPQ_disable_MSK (0x0FFFFFFF) + #define MCHBAR_CH1_CR_QUEUE_ENTRY_DISABLE_RPQ_RPQ_disable_MAX (0x0FFFFFFF) + #define MCHBAR_CH1_CR_QUEUE_ENTRY_DISABLE_RPQ_RPQ_disable_DEF (0x00000000) + +#define MCHBAR_CH1_CR_QUEUE_ENTRY_DISABLE_WPQ_REG (0x000046E8) + #define MCHBAR_CH1_CR_QUEUE_ENTRY_DISABLE_WPQ_WPQ_disable_OFF ( 0) + #define MCHBAR_CH1_CR_QUEUE_ENTRY_DISABLE_WPQ_WPQ_disable_WID (32) + #define MCHBAR_CH1_CR_QUEUE_ENTRY_DISABLE_WPQ_WPQ_disable_MSK (0xFFFFFFFF) + #define MCHBAR_CH1_CR_QUEUE_ENTRY_DISABLE_WPQ_WPQ_disable_MAX (0xFFFFFFFF) + #define MCHBAR_CH1_CR_QUEUE_ENTRY_DISABLE_WPQ_WPQ_disable_DEF (0x00000000) + +#define MCHBAR_CH1_CR_PM_DIMM_IDLE_ENERGY_REG (0x000046EC) + #define MCHBAR_CH1_CR_PM_DIMM_IDLE_ENERGY_DIMM0_IDLE_ENERGY_OFF ( 0) + #define MCHBAR_CH1_CR_PM_DIMM_IDLE_ENERGY_DIMM0_IDLE_ENERGY_WID ( 6) + #define MCHBAR_CH1_CR_PM_DIMM_IDLE_ENERGY_DIMM0_IDLE_ENERGY_MSK (0x0000003F) + #define MCHBAR_CH1_CR_PM_DIMM_IDLE_ENERGY_DIMM0_IDLE_ENERGY_MAX (0x0000003F) + #define MCHBAR_CH1_CR_PM_DIMM_IDLE_ENERGY_DIMM0_IDLE_ENERGY_DEF (0x00000000) + #define MCHBAR_CH1_CR_PM_DIMM_IDLE_ENERGY_DIMM1_IDLE_ENERGY_OFF ( 8) + #define MCHBAR_CH1_CR_PM_DIMM_IDLE_ENERGY_DIMM1_IDLE_ENERGY_WID ( 6) + #define MCHBAR_CH1_CR_PM_DIMM_IDLE_ENERGY_DIMM1_IDLE_ENERGY_MSK (0x00003F00) + #define MCHBAR_CH1_CR_PM_DIMM_IDLE_ENERGY_DIMM1_IDLE_ENERGY_MAX (0x0000003F) + #define MCHBAR_CH1_CR_PM_DIMM_IDLE_ENERGY_DIMM1_IDLE_ENERGY_DEF (0x00000000) + +#define MCHBAR_CH1_CR_PM_DIMM_PD_ENERGY_REG (0x000046F0) + #define MCHBAR_CH1_CR_PM_DIMM_PD_ENERGY_DIMM0_PD_ENERGY_OFF ( 0) + #define MCHBAR_CH1_CR_PM_DIMM_PD_ENERGY_DIMM0_PD_ENERGY_WID ( 6) + #define MCHBAR_CH1_CR_PM_DIMM_PD_ENERGY_DIMM0_PD_ENERGY_MSK (0x0000003F) + #define MCHBAR_CH1_CR_PM_DIMM_PD_ENERGY_DIMM0_PD_ENERGY_MAX (0x0000003F) + #define MCHBAR_CH1_CR_PM_DIMM_PD_ENERGY_DIMM0_PD_ENERGY_DEF (0x00000000) + #define MCHBAR_CH1_CR_PM_DIMM_PD_ENERGY_DIMM1_PD_ENERGY_OFF ( 8) + #define MCHBAR_CH1_CR_PM_DIMM_PD_ENERGY_DIMM1_PD_ENERGY_WID ( 6) + #define MCHBAR_CH1_CR_PM_DIMM_PD_ENERGY_DIMM1_PD_ENERGY_MSK (0x00003F00) + #define MCHBAR_CH1_CR_PM_DIMM_PD_ENERGY_DIMM1_PD_ENERGY_MAX (0x0000003F) + #define MCHBAR_CH1_CR_PM_DIMM_PD_ENERGY_DIMM1_PD_ENERGY_DEF (0x00000000) + +#define MCHBAR_CH1_CR_PM_DIMM_ACT_ENERGY_REG (0x000046F4) + #define MCHBAR_CH1_CR_PM_DIMM_ACT_ENERGY_DIMM0_ACT_ENERGY_OFF ( 0) + #define MCHBAR_CH1_CR_PM_DIMM_ACT_ENERGY_DIMM0_ACT_ENERGY_WID ( 8) + #define MCHBAR_CH1_CR_PM_DIMM_ACT_ENERGY_DIMM0_ACT_ENERGY_MSK (0x000000FF) + #define MCHBAR_CH1_CR_PM_DIMM_ACT_ENERGY_DIMM0_ACT_ENERGY_MAX (0x000000FF) + #define MCHBAR_CH1_CR_PM_DIMM_ACT_ENERGY_DIMM0_ACT_ENERGY_DEF (0x00000000) + #define MCHBAR_CH1_CR_PM_DIMM_ACT_ENERGY_DIMM1_ACT_ENERGY_OFF ( 8) + #define MCHBAR_CH1_CR_PM_DIMM_ACT_ENERGY_DIMM1_ACT_ENERGY_WID ( 8) + #define MCHBAR_CH1_CR_PM_DIMM_ACT_ENERGY_DIMM1_ACT_ENERGY_MSK (0x0000FF00) + #define MCHBAR_CH1_CR_PM_DIMM_ACT_ENERGY_DIMM1_ACT_ENERGY_MAX (0x000000FF) + #define MCHBAR_CH1_CR_PM_DIMM_ACT_ENERGY_DIMM1_ACT_ENERGY_DEF (0x00000000) + +#define MCHBAR_CH1_CR_PM_DIMM_RD_ENERGY_REG (0x000046F8) + #define MCHBAR_CH1_CR_PM_DIMM_RD_ENERGY_DIMM0_RD_ENERGY_OFF ( 0) + #define MCHBAR_CH1_CR_PM_DIMM_RD_ENERGY_DIMM0_RD_ENERGY_WID ( 8) + #define MCHBAR_CH1_CR_PM_DIMM_RD_ENERGY_DIMM0_RD_ENERGY_MSK (0x000000FF) + #define MCHBAR_CH1_CR_PM_DIMM_RD_ENERGY_DIMM0_RD_ENERGY_MAX (0x000000FF) + #define MCHBAR_CH1_CR_PM_DIMM_RD_ENERGY_DIMM0_RD_ENERGY_DEF (0x00000000) + #define MCHBAR_CH1_CR_PM_DIMM_RD_ENERGY_DIMM1_RD_ENERGY_OFF ( 8) + #define MCHBAR_CH1_CR_PM_DIMM_RD_ENERGY_DIMM1_RD_ENERGY_WID ( 8) + #define MCHBAR_CH1_CR_PM_DIMM_RD_ENERGY_DIMM1_RD_ENERGY_MSK (0x0000FF00) + #define MCHBAR_CH1_CR_PM_DIMM_RD_ENERGY_DIMM1_RD_ENERGY_MAX (0x000000FF) + #define MCHBAR_CH1_CR_PM_DIMM_RD_ENERGY_DIMM1_RD_ENERGY_DEF (0x00000000) + +#define MCHBAR_CH1_CR_PM_DIMM_WR_ENERGY_REG (0x000046FC) + #define MCHBAR_CH1_CR_PM_DIMM_WR_ENERGY_DIMM0_WR_ENERGY_OFF ( 0) + #define MCHBAR_CH1_CR_PM_DIMM_WR_ENERGY_DIMM0_WR_ENERGY_WID ( 8) + #define MCHBAR_CH1_CR_PM_DIMM_WR_ENERGY_DIMM0_WR_ENERGY_MSK (0x000000FF) + #define MCHBAR_CH1_CR_PM_DIMM_WR_ENERGY_DIMM0_WR_ENERGY_MAX (0x000000FF) + #define MCHBAR_CH1_CR_PM_DIMM_WR_ENERGY_DIMM0_WR_ENERGY_DEF (0x00000000) + #define MCHBAR_CH1_CR_PM_DIMM_WR_ENERGY_DIMM1_WR_ENERGY_OFF ( 8) + #define MCHBAR_CH1_CR_PM_DIMM_WR_ENERGY_DIMM1_WR_ENERGY_WID ( 8) + #define MCHBAR_CH1_CR_PM_DIMM_WR_ENERGY_DIMM1_WR_ENERGY_MSK (0x0000FF00) + #define MCHBAR_CH1_CR_PM_DIMM_WR_ENERGY_DIMM1_WR_ENERGY_MAX (0x000000FF) + #define MCHBAR_CH1_CR_PM_DIMM_WR_ENERGY_DIMM1_WR_ENERGY_DEF (0x00000000) + +#define MCHBAR_CH1_CR_PM_THRT_CKE_MIN_REG (0x00004728) + #define MCHBAR_CH1_CR_PM_THRT_CKE_MIN_CKE_MIN_OFF ( 0) + #define MCHBAR_CH1_CR_PM_THRT_CKE_MIN_CKE_MIN_WID ( 8) + #define MCHBAR_CH1_CR_PM_THRT_CKE_MIN_CKE_MIN_MSK (0x000000FF) + #define MCHBAR_CH1_CR_PM_THRT_CKE_MIN_CKE_MIN_MAX (0x000000FF) + #define MCHBAR_CH1_CR_PM_THRT_CKE_MIN_CKE_MIN_DEF (0x00000000) + #define MCHBAR_CH1_CR_PM_THRT_CKE_MIN_CKE_MIN_DEFEATURE_OFF ( 8) + #define MCHBAR_CH1_CR_PM_THRT_CKE_MIN_CKE_MIN_DEFEATURE_WID ( 1) + #define MCHBAR_CH1_CR_PM_THRT_CKE_MIN_CKE_MIN_DEFEATURE_MSK (0x00000100) + #define MCHBAR_CH1_CR_PM_THRT_CKE_MIN_CKE_MIN_DEFEATURE_MAX (0x00000001) + #define MCHBAR_CH1_CR_PM_THRT_CKE_MIN_CKE_MIN_DEFEATURE_DEF (0x00000000) + +#define MCHBAR_CH1_CR_ODLAT_CMD_MATCH0_REG (0x00004740) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH0_ODT_OFF ( 0) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH0_ODT_WID ( 4) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH0_ODT_MSK (0x0000000F) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH0_ODT_MAX (0x0000000F) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH0_ODT_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH0_Web_OFF ( 4) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH0_Web_WID ( 1) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH0_Web_MSK (0x00000010) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH0_Web_MAX (0x00000001) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH0_Web_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH0_CASb_OFF ( 5) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH0_CASb_WID ( 1) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH0_CASb_MSK (0x00000020) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH0_CASb_MAX (0x00000001) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH0_CASb_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH0_RASb_OFF ( 6) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH0_RASb_WID ( 1) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH0_RASb_MSK (0x00000040) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH0_RASb_MAX (0x00000001) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH0_RASb_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH0_CSb_OFF ( 7) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH0_CSb_WID ( 4) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH0_CSb_MSK (0x00000780) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH0_CSb_MAX (0x0000000F) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH0_CSb_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH0_CKE_OFF (11) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH0_CKE_WID ( 4) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH0_CKE_MSK (0x00007800) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH0_CKE_MAX (0x0000000F) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH0_CKE_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH0_MA_OFF (15) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH0_MA_WID (16) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH0_MA_MSK (0x7FFF8000) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH0_MA_MAX (0x0000FFFF) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH0_MA_DEF (0x00000000) + +#define MCHBAR_CH1_CR_ODLAT_CMD_MATCH1_REG (0x00004744) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH1_ODT_OFF ( 0) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH1_ODT_WID ( 4) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH1_ODT_MSK (0x0000000F) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH1_ODT_MAX (0x0000000F) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH1_ODT_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH1_Web_OFF ( 4) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH1_Web_WID ( 1) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH1_Web_MSK (0x00000010) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH1_Web_MAX (0x00000001) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH1_Web_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH1_CASb_OFF ( 5) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH1_CASb_WID ( 1) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH1_CASb_MSK (0x00000020) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH1_CASb_MAX (0x00000001) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH1_CASb_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH1_RASb_OFF ( 6) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH1_RASb_WID ( 1) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH1_RASb_MSK (0x00000040) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH1_RASb_MAX (0x00000001) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH1_RASb_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH1_CSb_OFF ( 7) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH1_CSb_WID ( 4) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH1_CSb_MSK (0x00000780) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH1_CSb_MAX (0x0000000F) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH1_CSb_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH1_CKE_OFF (11) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH1_CKE_WID ( 4) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH1_CKE_MSK (0x00007800) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH1_CKE_MAX (0x0000000F) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH1_CKE_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH1_MA_OFF (15) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH1_MA_WID (16) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH1_MA_MSK (0x7FFF8000) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH1_MA_MAX (0x0000FFFF) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH1_MA_DEF (0x00000000) + +#define MCHBAR_CH1_CR_ODLAT_CMD_MATCH2_REG (0x00004748) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH2_ODT_OFF ( 0) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH2_ODT_WID ( 4) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH2_ODT_MSK (0x0000000F) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH2_ODT_MAX (0x0000000F) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH2_ODT_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH2_Web_OFF ( 4) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH2_Web_WID ( 1) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH2_Web_MSK (0x00000010) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH2_Web_MAX (0x00000001) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH2_Web_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH2_CASb_OFF ( 5) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH2_CASb_WID ( 1) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH2_CASb_MSK (0x00000020) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH2_CASb_MAX (0x00000001) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH2_CASb_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH2_RASb_OFF ( 6) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH2_RASb_WID ( 1) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH2_RASb_MSK (0x00000040) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH2_RASb_MAX (0x00000001) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH2_RASb_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH2_CSb_OFF ( 7) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH2_CSb_WID ( 4) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH2_CSb_MSK (0x00000780) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH2_CSb_MAX (0x0000000F) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH2_CSb_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH2_CKE_OFF (11) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH2_CKE_WID ( 4) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH2_CKE_MSK (0x00007800) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH2_CKE_MAX (0x0000000F) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH2_CKE_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH2_MA_OFF (15) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH2_MA_WID (16) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH2_MA_MSK (0x7FFF8000) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH2_MA_MAX (0x0000FFFF) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH2_MA_DEF (0x00000000) + +#define MCHBAR_CH1_CR_ODLAT_CMD_MATCH3_REG (0x0000474C) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH3_ODT_OFF ( 0) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH3_ODT_WID ( 4) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH3_ODT_MSK (0x0000000F) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH3_ODT_MAX (0x0000000F) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH3_ODT_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH3_Web_OFF ( 4) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH3_Web_WID ( 1) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH3_Web_MSK (0x00000010) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH3_Web_MAX (0x00000001) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH3_Web_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH3_CASb_OFF ( 5) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH3_CASb_WID ( 1) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH3_CASb_MSK (0x00000020) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH3_CASb_MAX (0x00000001) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH3_CASb_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH3_RASb_OFF ( 6) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH3_RASb_WID ( 1) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH3_RASb_MSK (0x00000040) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH3_RASb_MAX (0x00000001) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH3_RASb_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH3_CSb_OFF ( 7) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH3_CSb_WID ( 4) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH3_CSb_MSK (0x00000780) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH3_CSb_MAX (0x0000000F) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH3_CSb_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH3_CKE_OFF (11) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH3_CKE_WID ( 4) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH3_CKE_MSK (0x00007800) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH3_CKE_MAX (0x0000000F) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH3_CKE_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH3_MA_OFF (15) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH3_MA_WID (16) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH3_MA_MSK (0x7FFF8000) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH3_MA_MAX (0x0000FFFF) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH3_MA_DEF (0x00000000) + +#define MCHBAR_CH1_CR_ODLAT_CMD_MASK0_REG (0x00004750) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK0_ODT_OFF ( 0) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK0_ODT_WID ( 4) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK0_ODT_MSK (0x0000000F) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK0_ODT_MAX (0x0000000F) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK0_ODT_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK0_Web_OFF ( 4) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK0_Web_WID ( 1) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK0_Web_MSK (0x00000010) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK0_Web_MAX (0x00000001) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK0_Web_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK0_CASb_OFF ( 5) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK0_CASb_WID ( 1) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK0_CASb_MSK (0x00000020) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK0_CASb_MAX (0x00000001) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK0_CASb_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK0_RASb_OFF ( 6) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK0_RASb_WID ( 1) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK0_RASb_MSK (0x00000040) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK0_RASb_MAX (0x00000001) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK0_RASb_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK0_CSb_OFF ( 7) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK0_CSb_WID ( 4) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK0_CSb_MSK (0x00000780) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK0_CSb_MAX (0x0000000F) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK0_CSb_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK0_CKE_OFF (11) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK0_CKE_WID ( 4) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK0_CKE_MSK (0x00007800) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK0_CKE_MAX (0x0000000F) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK0_CKE_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK0_MA_OFF (15) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK0_MA_WID (16) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK0_MA_MSK (0x7FFF8000) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK0_MA_MAX (0x0000FFFF) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK0_MA_DEF (0x00000000) + +#define MCHBAR_CH1_CR_ODLAT_CMD_MASK1_REG (0x00004754) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK1_ODT_OFF ( 0) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK1_ODT_WID ( 4) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK1_ODT_MSK (0x0000000F) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK1_ODT_MAX (0x0000000F) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK1_ODT_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK1_Web_OFF ( 4) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK1_Web_WID ( 1) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK1_Web_MSK (0x00000010) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK1_Web_MAX (0x00000001) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK1_Web_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK1_CASb_OFF ( 5) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK1_CASb_WID ( 1) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK1_CASb_MSK (0x00000020) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK1_CASb_MAX (0x00000001) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK1_CASb_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK1_RASb_OFF ( 6) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK1_RASb_WID ( 1) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK1_RASb_MSK (0x00000040) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK1_RASb_MAX (0x00000001) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK1_RASb_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK1_CSb_OFF ( 7) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK1_CSb_WID ( 4) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK1_CSb_MSK (0x00000780) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK1_CSb_MAX (0x0000000F) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK1_CSb_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK1_CKE_OFF (11) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK1_CKE_WID ( 4) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK1_CKE_MSK (0x00007800) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK1_CKE_MAX (0x0000000F) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK1_CKE_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK1_MA_OFF (15) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK1_MA_WID (16) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK1_MA_MSK (0x7FFF8000) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK1_MA_MAX (0x0000FFFF) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK1_MA_DEF (0x00000000) + +#define MCHBAR_CH1_CR_ODLAT_CMD_MASK2_REG (0x00004758) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK2_ODT_OFF ( 0) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK2_ODT_WID ( 4) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK2_ODT_MSK (0x0000000F) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK2_ODT_MAX (0x0000000F) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK2_ODT_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK2_Web_OFF ( 4) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK2_Web_WID ( 1) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK2_Web_MSK (0x00000010) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK2_Web_MAX (0x00000001) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK2_Web_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK2_CASb_OFF ( 5) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK2_CASb_WID ( 1) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK2_CASb_MSK (0x00000020) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK2_CASb_MAX (0x00000001) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK2_CASb_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK2_RASb_OFF ( 6) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK2_RASb_WID ( 1) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK2_RASb_MSK (0x00000040) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK2_RASb_MAX (0x00000001) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK2_RASb_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK2_CSb_OFF ( 7) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK2_CSb_WID ( 4) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK2_CSb_MSK (0x00000780) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK2_CSb_MAX (0x0000000F) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK2_CSb_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK2_CKE_OFF (11) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK2_CKE_WID ( 4) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK2_CKE_MSK (0x00007800) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK2_CKE_MAX (0x0000000F) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK2_CKE_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK2_MA_OFF (15) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK2_MA_WID (16) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK2_MA_MSK (0x7FFF8000) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK2_MA_MAX (0x0000FFFF) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK2_MA_DEF (0x00000000) + +#define MCHBAR_CH1_CR_ODLAT_CMD_MASK3_REG (0x0000475C) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK3_ODT_OFF ( 0) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK3_ODT_WID ( 4) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK3_ODT_MSK (0x0000000F) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK3_ODT_MAX (0x0000000F) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK3_ODT_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK3_Web_OFF ( 4) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK3_Web_WID ( 1) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK3_Web_MSK (0x00000010) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK3_Web_MAX (0x00000001) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK3_Web_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK3_CASb_OFF ( 5) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK3_CASb_WID ( 1) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK3_CASb_MSK (0x00000020) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK3_CASb_MAX (0x00000001) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK3_CASb_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK3_RASb_OFF ( 6) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK3_RASb_WID ( 1) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK3_RASb_MSK (0x00000040) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK3_RASb_MAX (0x00000001) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK3_RASb_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK3_CSb_OFF ( 7) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK3_CSb_WID ( 4) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK3_CSb_MSK (0x00000780) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK3_CSb_MAX (0x0000000F) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK3_CSb_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK3_CKE_OFF (11) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK3_CKE_WID ( 4) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK3_CKE_MSK (0x00007800) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK3_CKE_MAX (0x0000000F) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK3_CKE_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK3_MA_OFF (15) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK3_MA_WID (16) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK3_MA_MSK (0x7FFF8000) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK3_MA_MAX (0x0000FFFF) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK3_MA_DEF (0x00000000) + +#define MCHBAR_CH1_CR_ODLAT_CMD_BANK_REG (0x00004760) + #define MCHBAR_CH1_CR_ODLAT_CMD_BANK_BankMatch0_OFF ( 0) + #define MCHBAR_CH1_CR_ODLAT_CMD_BANK_BankMatch0_WID ( 3) + #define MCHBAR_CH1_CR_ODLAT_CMD_BANK_BankMatch0_MSK (0x00000007) + #define MCHBAR_CH1_CR_ODLAT_CMD_BANK_BankMatch0_MAX (0x00000007) + #define MCHBAR_CH1_CR_ODLAT_CMD_BANK_BankMatch0_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_CMD_BANK_BankMatch1_OFF ( 3) + #define MCHBAR_CH1_CR_ODLAT_CMD_BANK_BankMatch1_WID ( 3) + #define MCHBAR_CH1_CR_ODLAT_CMD_BANK_BankMatch1_MSK (0x00000038) + #define MCHBAR_CH1_CR_ODLAT_CMD_BANK_BankMatch1_MAX (0x00000007) + #define MCHBAR_CH1_CR_ODLAT_CMD_BANK_BankMatch1_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_CMD_BANK_BankMatch2_OFF ( 6) + #define MCHBAR_CH1_CR_ODLAT_CMD_BANK_BankMatch2_WID ( 3) + #define MCHBAR_CH1_CR_ODLAT_CMD_BANK_BankMatch2_MSK (0x000001C0) + #define MCHBAR_CH1_CR_ODLAT_CMD_BANK_BankMatch2_MAX (0x00000007) + #define MCHBAR_CH1_CR_ODLAT_CMD_BANK_BankMatch2_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_CMD_BANK_BankMatch3_OFF ( 9) + #define MCHBAR_CH1_CR_ODLAT_CMD_BANK_BankMatch3_WID ( 3) + #define MCHBAR_CH1_CR_ODLAT_CMD_BANK_BankMatch3_MSK (0x00000E00) + #define MCHBAR_CH1_CR_ODLAT_CMD_BANK_BankMatch3_MAX (0x00000007) + #define MCHBAR_CH1_CR_ODLAT_CMD_BANK_BankMatch3_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_CMD_BANK_BankMask0_OFF (12) + #define MCHBAR_CH1_CR_ODLAT_CMD_BANK_BankMask0_WID ( 3) + #define MCHBAR_CH1_CR_ODLAT_CMD_BANK_BankMask0_MSK (0x00007000) + #define MCHBAR_CH1_CR_ODLAT_CMD_BANK_BankMask0_MAX (0x00000007) + #define MCHBAR_CH1_CR_ODLAT_CMD_BANK_BankMask0_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_CMD_BANK_BankMask1_OFF (15) + #define MCHBAR_CH1_CR_ODLAT_CMD_BANK_BankMask1_WID ( 3) + #define MCHBAR_CH1_CR_ODLAT_CMD_BANK_BankMask1_MSK (0x00038000) + #define MCHBAR_CH1_CR_ODLAT_CMD_BANK_BankMask1_MAX (0x00000007) + #define MCHBAR_CH1_CR_ODLAT_CMD_BANK_BankMask1_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_CMD_BANK_BankMask2_OFF (18) + #define MCHBAR_CH1_CR_ODLAT_CMD_BANK_BankMask2_WID ( 3) + #define MCHBAR_CH1_CR_ODLAT_CMD_BANK_BankMask2_MSK (0x001C0000) + #define MCHBAR_CH1_CR_ODLAT_CMD_BANK_BankMask2_MAX (0x00000007) + #define MCHBAR_CH1_CR_ODLAT_CMD_BANK_BankMask2_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_CMD_BANK_BankMask3_OFF (21) + #define MCHBAR_CH1_CR_ODLAT_CMD_BANK_BankMask3_WID ( 3) + #define MCHBAR_CH1_CR_ODLAT_CMD_BANK_BankMask3_MSK (0x00E00000) + #define MCHBAR_CH1_CR_ODLAT_CMD_BANK_BankMask3_MAX (0x00000007) + #define MCHBAR_CH1_CR_ODLAT_CMD_BANK_BankMask3_DEF (0x00000000) + +#define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL0_REG (0x00004764) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL0_InputMatch_OFF ( 0) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL0_InputMatch_WID ( 4) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL0_InputMatch_MSK (0x0000000F) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL0_InputMatch_MAX (0x0000000F) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL0_InputMatch_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL0_InputInvert_OFF ( 4) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL0_InputInvert_WID ( 4) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL0_InputInvert_MSK (0x000000F0) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL0_InputInvert_MAX (0x0000000F) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL0_InputInvert_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL0_CountMatches_OFF ( 8) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL0_CountMatches_WID ( 1) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL0_CountMatches_MSK (0x00000100) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL0_CountMatches_MAX (0x00000001) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL0_CountMatches_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL0_CounterThreshold_OFF ( 9) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL0_CounterThreshold_WID (15) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL0_CounterThreshold_MSK (0x00FFFE00) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL0_CounterThreshold_MAX (0x00007FFF) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL0_CounterThreshold_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL0_CounterAction_OFF (24) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL0_CounterAction_WID ( 2) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL0_CounterAction_MSK (0x03000000) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL0_CounterAction_MAX (0x00000003) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL0_CounterAction_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL0_CounterNextState_OFF (26) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL0_CounterNextState_WID ( 2) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL0_CounterNextState_MSK (0x0C000000) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL0_CounterNextState_MAX (0x00000003) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL0_CounterNextState_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL0_MatchAction_OFF (28) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL0_MatchAction_WID ( 2) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL0_MatchAction_MSK (0x30000000) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL0_MatchAction_MAX (0x00000003) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL0_MatchAction_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL0_MatchNextState_OFF (30) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL0_MatchNextState_WID ( 2) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL0_MatchNextState_MSK (0xC0000000) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL0_MatchNextState_MAX (0x00000003) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL0_MatchNextState_DEF (0x00000000) + +#define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL1_REG (0x00004768) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL1_InputMatch_OFF ( 0) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL1_InputMatch_WID ( 4) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL1_InputMatch_MSK (0x0000000F) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL1_InputMatch_MAX (0x0000000F) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL1_InputMatch_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL1_InputInvert_OFF ( 4) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL1_InputInvert_WID ( 4) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL1_InputInvert_MSK (0x000000F0) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL1_InputInvert_MAX (0x0000000F) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL1_InputInvert_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL1_CountMatches_OFF ( 8) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL1_CountMatches_WID ( 1) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL1_CountMatches_MSK (0x00000100) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL1_CountMatches_MAX (0x00000001) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL1_CountMatches_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL1_CounterThreshold_OFF ( 9) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL1_CounterThreshold_WID (15) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL1_CounterThreshold_MSK (0x00FFFE00) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL1_CounterThreshold_MAX (0x00007FFF) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL1_CounterThreshold_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL1_CounterAction_OFF (24) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL1_CounterAction_WID ( 2) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL1_CounterAction_MSK (0x03000000) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL1_CounterAction_MAX (0x00000003) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL1_CounterAction_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL1_CounterNextState_OFF (26) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL1_CounterNextState_WID ( 2) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL1_CounterNextState_MSK (0x0C000000) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL1_CounterNextState_MAX (0x00000003) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL1_CounterNextState_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL1_MatchAction_OFF (28) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL1_MatchAction_WID ( 2) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL1_MatchAction_MSK (0x30000000) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL1_MatchAction_MAX (0x00000003) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL1_MatchAction_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL1_MatchNextState_OFF (30) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL1_MatchNextState_WID ( 2) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL1_MatchNextState_MSK (0xC0000000) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL1_MatchNextState_MAX (0x00000003) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL1_MatchNextState_DEF (0x00000000) + +#define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL2_REG (0x0000476C) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL2_InputMatch_OFF ( 0) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL2_InputMatch_WID ( 4) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL2_InputMatch_MSK (0x0000000F) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL2_InputMatch_MAX (0x0000000F) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL2_InputMatch_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL2_InputInvert_OFF ( 4) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL2_InputInvert_WID ( 4) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL2_InputInvert_MSK (0x000000F0) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL2_InputInvert_MAX (0x0000000F) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL2_InputInvert_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL2_CountMatches_OFF ( 8) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL2_CountMatches_WID ( 1) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL2_CountMatches_MSK (0x00000100) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL2_CountMatches_MAX (0x00000001) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL2_CountMatches_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL2_CounterThreshold_OFF ( 9) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL2_CounterThreshold_WID (15) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL2_CounterThreshold_MSK (0x00FFFE00) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL2_CounterThreshold_MAX (0x00007FFF) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL2_CounterThreshold_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL2_CounterAction_OFF (24) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL2_CounterAction_WID ( 2) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL2_CounterAction_MSK (0x03000000) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL2_CounterAction_MAX (0x00000003) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL2_CounterAction_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL2_CounterNextState_OFF (26) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL2_CounterNextState_WID ( 2) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL2_CounterNextState_MSK (0x0C000000) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL2_CounterNextState_MAX (0x00000003) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL2_CounterNextState_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL2_MatchAction_OFF (28) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL2_MatchAction_WID ( 2) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL2_MatchAction_MSK (0x30000000) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL2_MatchAction_MAX (0x00000003) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL2_MatchAction_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL2_MatchNextState_OFF (30) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL2_MatchNextState_WID ( 2) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL2_MatchNextState_MSK (0xC0000000) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL2_MatchNextState_MAX (0x00000003) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL2_MatchNextState_DEF (0x00000000) + +#define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL3_REG (0x00004770) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL3_InputMatch_OFF ( 0) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL3_InputMatch_WID ( 4) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL3_InputMatch_MSK (0x0000000F) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL3_InputMatch_MAX (0x0000000F) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL3_InputMatch_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL3_InputInvert_OFF ( 4) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL3_InputInvert_WID ( 4) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL3_InputInvert_MSK (0x000000F0) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL3_InputInvert_MAX (0x0000000F) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL3_InputInvert_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL3_CountMatches_OFF ( 8) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL3_CountMatches_WID ( 1) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL3_CountMatches_MSK (0x00000100) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL3_CountMatches_MAX (0x00000001) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL3_CountMatches_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL3_CounterThreshold_OFF ( 9) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL3_CounterThreshold_WID (15) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL3_CounterThreshold_MSK (0x00FFFE00) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL3_CounterThreshold_MAX (0x00007FFF) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL3_CounterThreshold_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL3_CounterAction_OFF (24) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL3_CounterAction_WID ( 2) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL3_CounterAction_MSK (0x03000000) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL3_CounterAction_MAX (0x00000003) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL3_CounterAction_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL3_CounterNextState_OFF (26) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL3_CounterNextState_WID ( 2) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL3_CounterNextState_MSK (0x0C000000) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL3_CounterNextState_MAX (0x00000003) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL3_CounterNextState_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL3_MatchAction_OFF (28) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL3_MatchAction_WID ( 2) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL3_MatchAction_MSK (0x30000000) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL3_MatchAction_MAX (0x00000003) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL3_MatchAction_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL3_MatchNextState_OFF (30) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL3_MatchNextState_WID ( 2) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL3_MatchNextState_MSK (0xC0000000) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL3_MatchNextState_MAX (0x00000003) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL3_MatchNextState_DEF (0x00000000) + +#define MCHBAR_CH1_CR_ODLAT_SEQ_GLOBAL_REG (0x00004774) + #define MCHBAR_CH1_CR_ODLAT_SEQ_GLOBAL_TriggerBlockEnable_OFF ( 0) + #define MCHBAR_CH1_CR_ODLAT_SEQ_GLOBAL_TriggerBlockEnable_WID ( 1) + #define MCHBAR_CH1_CR_ODLAT_SEQ_GLOBAL_TriggerBlockEnable_MSK (0x00000001) + #define MCHBAR_CH1_CR_ODLAT_SEQ_GLOBAL_TriggerBlockEnable_MAX (0x00000001) + #define MCHBAR_CH1_CR_ODLAT_SEQ_GLOBAL_TriggerBlockEnable_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_SEQ_GLOBAL_GlobalCounterThreshold_OFF ( 1) + #define MCHBAR_CH1_CR_ODLAT_SEQ_GLOBAL_GlobalCounterThreshold_WID (16) + #define MCHBAR_CH1_CR_ODLAT_SEQ_GLOBAL_GlobalCounterThreshold_MSK (0x0001FFFE) + #define MCHBAR_CH1_CR_ODLAT_SEQ_GLOBAL_GlobalCounterThreshold_MAX (0x0000FFFF) + #define MCHBAR_CH1_CR_ODLAT_SEQ_GLOBAL_GlobalCounterThreshold_DEF (0x00000000) + +#define MCHBAR_CH1_CR_SC_WDBWM_REG (0x0000478C) + #define MCHBAR_CH1_CR_SC_WDBWM_WMM_Enter_OFF ( 0) + #define MCHBAR_CH1_CR_SC_WDBWM_WMM_Enter_WID ( 8) + #define MCHBAR_CH1_CR_SC_WDBWM_WMM_Enter_MSK (0x000000FF) + #define MCHBAR_CH1_CR_SC_WDBWM_WMM_Enter_MAX (0x000000FF) + #define MCHBAR_CH1_CR_SC_WDBWM_WMM_Enter_DEF (0x00000038) + #define MCHBAR_CH1_CR_SC_WDBWM_WMM_Exit_OFF ( 8) + #define MCHBAR_CH1_CR_SC_WDBWM_WMM_Exit_WID ( 8) + #define MCHBAR_CH1_CR_SC_WDBWM_WMM_Exit_MSK (0x0000FF00) + #define MCHBAR_CH1_CR_SC_WDBWM_WMM_Exit_MAX (0x000000FF) + #define MCHBAR_CH1_CR_SC_WDBWM_WMM_Exit_DEF (0x00000030) + #define MCHBAR_CH1_CR_SC_WDBWM_WPQ_IS_OFF (16) + #define MCHBAR_CH1_CR_SC_WDBWM_WPQ_IS_WID ( 8) + #define MCHBAR_CH1_CR_SC_WDBWM_WPQ_IS_MSK (0x00FF0000) + #define MCHBAR_CH1_CR_SC_WDBWM_WPQ_IS_MAX (0x000000FF) + #define MCHBAR_CH1_CR_SC_WDBWM_WPQ_IS_DEF (0x0000003C) + #define MCHBAR_CH1_CR_SC_WDBWM_Starve_count_OFF (24) + #define MCHBAR_CH1_CR_SC_WDBWM_Starve_count_WID ( 8) + #define MCHBAR_CH1_CR_SC_WDBWM_Starve_count_MSK (0xFF000000) + #define MCHBAR_CH1_CR_SC_WDBWM_Starve_count_MAX (0x000000FF) + #define MCHBAR_CH1_CR_SC_WDBWM_Starve_count_DEF (0x000000FF) + +#define MCHBAR_CH1_CR_VISA_CTL_MCMNTS_REG (0x00004790) + #define MCHBAR_CH1_CR_VISA_CTL_MCMNTS_Data_OFF ( 0) + #define MCHBAR_CH1_CR_VISA_CTL_MCMNTS_Data_WID (18) + #define MCHBAR_CH1_CR_VISA_CTL_MCMNTS_Data_MSK (0x0003FFFF) + #define MCHBAR_CH1_CR_VISA_CTL_MCMNTS_Data_MAX (0x0003FFFF) + #define MCHBAR_CH1_CR_VISA_CTL_MCMNTS_Data_DEF (0x00000000) + #define MCHBAR_CH1_CR_VISA_CTL_MCMNTS_VORANGE_OFF (31) + #define MCHBAR_CH1_CR_VISA_CTL_MCMNTS_VORANGE_WID ( 1) + #define MCHBAR_CH1_CR_VISA_CTL_MCMNTS_VORANGE_MSK (0x80000000) + #define MCHBAR_CH1_CR_VISA_CTL_MCMNTS_VORANGE_MAX (0x00000001) + #define MCHBAR_CH1_CR_VISA_CTL_MCMNTS_VORANGE_DEF (0x00000000) + +#pragma pack(pop) +#endif // __McMain_h__ diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcRegisters/McScramble.h b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcRegisters/McScramble.h new file mode 100644 index 0000000..a387610 --- /dev/null +++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcRegisters/McScramble.h @@ -0,0 +1,148 @@ +/** @file + This file was automatically generated. Modify at your own risk. + +@copyright + Copyright (c) 2010 - 2012 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +**/ +#ifndef __McScramble_h__ +#define __McScramble_h__ + +#pragma pack(push, 1) +#include "MrcTypes.h" + +typedef union { + struct { + U32 ScramEn : 1; // Bits 0:0 + U32 ScramKey : 16; // Bits 16:1 + U32 Spare : 15; // Bits 31:17 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRSCRAM_CR_DDRSCRAMBLECH0_STRUCT; + +typedef union { + struct { + U32 ScramEn : 1; // Bits 0:0 + U32 ScramKey : 16; // Bits 16:1 + U32 Spare : 15; // Bits 31:17 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRSCRAM_CR_DDRSCRAMBLECH1_STRUCT; + +typedef union { + struct { + U32 WL_WakeCycles : 2; // Bits 1:0 + U32 WL_SleepCycles : 3; // Bits 4:2 + U32 ForceCompUpdate : 1; // Bits 5:5 + U32 WeakLock_Latency : 4; // Bits 9:6 + U32 DdrNoChInterleave : 1; // Bits 10:10 + U32 LPDDR_Mode : 1; // Bits 11:11 + U32 CKEMappingCh0 : 4; // Bits 15:12 + U32 CKEMappingCh1 : 4; // Bits 19:16 + U32 Spare : 12; // Bits 31:20 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DDRSCRAM_CR_DDRMISCCONTROL0_STRUCT; + +#define DDRSCRAM_CR_DDRSCRAMBLECH0_REG (0x00002000) + #define DDRSCRAM_CR_DDRSCRAMBLECH0_ScramEn_OFF ( 0) + #define DDRSCRAM_CR_DDRSCRAMBLECH0_ScramEn_WID ( 1) + #define DDRSCRAM_CR_DDRSCRAMBLECH0_ScramEn_MSK (0x00000001) + #define DDRSCRAM_CR_DDRSCRAMBLECH0_ScramEn_MAX (0x00000001) + #define DDRSCRAM_CR_DDRSCRAMBLECH0_ScramEn_DEF (0x00000000) + #define DDRSCRAM_CR_DDRSCRAMBLECH0_ScramKey_OFF ( 1) + #define DDRSCRAM_CR_DDRSCRAMBLECH0_ScramKey_WID (16) + #define DDRSCRAM_CR_DDRSCRAMBLECH0_ScramKey_MSK (0x0001FFFE) + #define DDRSCRAM_CR_DDRSCRAMBLECH0_ScramKey_MAX (0x0000FFFF) + #define DDRSCRAM_CR_DDRSCRAMBLECH0_ScramKey_DEF (0x00000000) + #define DDRSCRAM_CR_DDRSCRAMBLECH0_Spare_OFF (17) + #define DDRSCRAM_CR_DDRSCRAMBLECH0_Spare_WID (15) + #define DDRSCRAM_CR_DDRSCRAMBLECH0_Spare_MSK (0xFFFE0000) + #define DDRSCRAM_CR_DDRSCRAMBLECH0_Spare_MAX (0x00007FFF) + #define DDRSCRAM_CR_DDRSCRAMBLECH0_Spare_DEF (0x00000000) + +#define DDRSCRAM_CR_DDRSCRAMBLECH1_REG (0x00002004) + #define DDRSCRAM_CR_DDRSCRAMBLECH1_ScramEn_OFF ( 0) + #define DDRSCRAM_CR_DDRSCRAMBLECH1_ScramEn_WID ( 1) + #define DDRSCRAM_CR_DDRSCRAMBLECH1_ScramEn_MSK (0x00000001) + #define DDRSCRAM_CR_DDRSCRAMBLECH1_ScramEn_MAX (0x00000001) + #define DDRSCRAM_CR_DDRSCRAMBLECH1_ScramEn_DEF (0x00000000) + #define DDRSCRAM_CR_DDRSCRAMBLECH1_ScramKey_OFF ( 1) + #define DDRSCRAM_CR_DDRSCRAMBLECH1_ScramKey_WID (16) + #define DDRSCRAM_CR_DDRSCRAMBLECH1_ScramKey_MSK (0x0001FFFE) + #define DDRSCRAM_CR_DDRSCRAMBLECH1_ScramKey_MAX (0x0000FFFF) + #define DDRSCRAM_CR_DDRSCRAMBLECH1_ScramKey_DEF (0x00000000) + #define DDRSCRAM_CR_DDRSCRAMBLECH1_Spare_OFF (17) + #define DDRSCRAM_CR_DDRSCRAMBLECH1_Spare_WID (15) + #define DDRSCRAM_CR_DDRSCRAMBLECH1_Spare_MSK (0xFFFE0000) + #define DDRSCRAM_CR_DDRSCRAMBLECH1_Spare_MAX (0x00007FFF) + #define DDRSCRAM_CR_DDRSCRAMBLECH1_Spare_DEF (0x00000000) + +#define DDRSCRAM_CR_DDRMISCCONTROL0_REG (0x00002008) + #define DDRSCRAM_CR_DDRMISCCONTROL0_WL_WakeCycles_OFF ( 0) + #define DDRSCRAM_CR_DDRMISCCONTROL0_WL_WakeCycles_WID ( 2) + #define DDRSCRAM_CR_DDRMISCCONTROL0_WL_WakeCycles_MSK (0x00000003) + #define DDRSCRAM_CR_DDRMISCCONTROL0_WL_WakeCycles_MAX (0x00000003) + #define DDRSCRAM_CR_DDRMISCCONTROL0_WL_WakeCycles_DEF (0x00000000) + #define DDRSCRAM_CR_DDRMISCCONTROL0_WL_SleepCycles_OFF ( 2) + #define DDRSCRAM_CR_DDRMISCCONTROL0_WL_SleepCycles_WID ( 3) + #define DDRSCRAM_CR_DDRMISCCONTROL0_WL_SleepCycles_MSK (0x0000001C) + #define DDRSCRAM_CR_DDRMISCCONTROL0_WL_SleepCycles_MAX (0x00000007) + #define DDRSCRAM_CR_DDRMISCCONTROL0_WL_SleepCycles_DEF (0x00000000) + #define DDRSCRAM_CR_DDRMISCCONTROL0_ForceCompUpdate_OFF ( 5) + #define DDRSCRAM_CR_DDRMISCCONTROL0_ForceCompUpdate_WID ( 1) + #define DDRSCRAM_CR_DDRMISCCONTROL0_ForceCompUpdate_MSK (0x00000020) + #define DDRSCRAM_CR_DDRMISCCONTROL0_ForceCompUpdate_MAX (0x00000001) + #define DDRSCRAM_CR_DDRMISCCONTROL0_ForceCompUpdate_DEF (0x00000000) + #define DDRSCRAM_CR_DDRMISCCONTROL0_WeakLock_Latency_OFF ( 6) + #define DDRSCRAM_CR_DDRMISCCONTROL0_WeakLock_Latency_WID ( 4) + #define DDRSCRAM_CR_DDRMISCCONTROL0_WeakLock_Latency_MSK (0x000003C0) + #define DDRSCRAM_CR_DDRMISCCONTROL0_WeakLock_Latency_MAX (0x0000000F) + #define DDRSCRAM_CR_DDRMISCCONTROL0_WeakLock_Latency_DEF (0x0000000C) + #define DDRSCRAM_CR_DDRMISCCONTROL0_DdrNoChInterleave_OFF (10) + #define DDRSCRAM_CR_DDRMISCCONTROL0_DdrNoChInterleave_WID ( 1) + #define DDRSCRAM_CR_DDRMISCCONTROL0_DdrNoChInterleave_MSK (0x00000400) + #define DDRSCRAM_CR_DDRMISCCONTROL0_DdrNoChInterleave_MAX (0x00000001) + #define DDRSCRAM_CR_DDRMISCCONTROL0_DdrNoChInterleave_DEF (0x00000000) + #define DDRSCRAM_CR_DDRMISCCONTROL0_LPDDR_Mode_OFF (11) + #define DDRSCRAM_CR_DDRMISCCONTROL0_LPDDR_Mode_WID ( 1) + #define DDRSCRAM_CR_DDRMISCCONTROL0_LPDDR_Mode_MSK (0x00000800) + #define DDRSCRAM_CR_DDRMISCCONTROL0_LPDDR_Mode_MAX (0x00000001) + #define DDRSCRAM_CR_DDRMISCCONTROL0_LPDDR_Mode_DEF (0x00000000) + #define DDRSCRAM_CR_DDRMISCCONTROL0_CKEMappingCh0_OFF (12) + #define DDRSCRAM_CR_DDRMISCCONTROL0_CKEMappingCh0_WID ( 4) + #define DDRSCRAM_CR_DDRMISCCONTROL0_CKEMappingCh0_MSK (0x0000F000) + #define DDRSCRAM_CR_DDRMISCCONTROL0_CKEMappingCh0_MAX (0x0000000F) + #define DDRSCRAM_CR_DDRMISCCONTROL0_CKEMappingCh0_DEF (0x0000000A) + #define DDRSCRAM_CR_DDRMISCCONTROL0_CKEMappingCh1_OFF (16) + #define DDRSCRAM_CR_DDRMISCCONTROL0_CKEMappingCh1_WID ( 4) + #define DDRSCRAM_CR_DDRMISCCONTROL0_CKEMappingCh1_MSK (0x000F0000) + #define DDRSCRAM_CR_DDRMISCCONTROL0_CKEMappingCh1_MAX (0x0000000F) + #define DDRSCRAM_CR_DDRMISCCONTROL0_CKEMappingCh1_DEF (0x0000000A) + #define DDRSCRAM_CR_DDRMISCCONTROL0_Spare_OFF (20) + #define DDRSCRAM_CR_DDRMISCCONTROL0_Spare_WID (12) + #define DDRSCRAM_CR_DDRMISCCONTROL0_Spare_MSK (0xFFF00000) + #define DDRSCRAM_CR_DDRMISCCONTROL0_Spare_MAX (0x00000FFF) + #define DDRSCRAM_CR_DDRMISCCONTROL0_Spare_DEF (0x00000000) + +#pragma pack(pop) +#endif // __McScramble_h__ diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcRegisters/Msa.h b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcRegisters/Msa.h new file mode 100644 index 0000000..ed8e90d --- /dev/null +++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcRegisters/Msa.h @@ -0,0 +1,6827 @@ +/** @file + This file was automatically generated. Modify at your own risk. + +@copyright + Copyright (c) 2010 - 2012 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +**/ +#ifndef __Msa_h__ +#define __Msa_h__ + +#pragma pack(push, 1) +#include "MrcTypes.h" + +typedef union { + struct { + U32 GFXVTBAREN : 1; // Bits 0:0 + U32 : 11; // Bits 11:1 + U32 GFXVTBAR : 27; // Bits 38:12 + U32 : 25; // Bits 63:39 + } Bits; + U64 Data; + U32 Data32[2]; + U16 Data16[4]; + U8 Data8[8]; +} NCDECS_CR_GFXVTBAR_NCU_STRUCT; + +typedef union { + struct { + U32 EDRAMBAREN : 1; // Bits 0:0 + U32 : 13; // Bits 13:1 + U32 EDRAMBAR : 25; // Bits 38:14 + U32 : 25; // Bits 63:39 + } Bits; + U64 Data; + U32 Data32[2]; + U16 Data16[4]; + U8 Data8[8]; +} NCDECS_CR_EDRAMBAR_NCU_STRUCT; + +typedef union { + struct { + U32 VTVC0BAREN : 1; // Bits 0:0 + U32 : 11; // Bits 11:1 + U32 VTVC0BAR : 27; // Bits 38:12 + U32 : 25; // Bits 63:39 + } Bits; + U64 Data; + U32 Data32[2]; + U16 Data16[4]; + U8 Data8[8]; +} NCDECS_CR_VTDPVC0BAR_NCU_STRUCT; + +typedef union { + struct { + U32 RdrModSel : 3; // Bits 2:0 + U32 ClastChkSmpMod : 1; // Bits 3:3 + U32 LogFltClustMod : 1; // Bits 4:4 + U32 LogFlatClustOvrEn : 1; // Bits 5:5 + U32 HashModCtr : 3; // Bits 8:6 + U32 : 23; // Bits 31:9 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} NCDECS_CR_INTRDIRCTL_NCU_STRUCT; + +typedef union { + struct { + U32 : 28; // Bits 27:0 + U32 PLIM : 3; // Bits 30:28 + U32 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} NCDECS_CR_NCUCTL0_NCU_STRUCT; + +typedef union { + struct { + U32 GDXCBAREN : 1; // Bits 0:0 + U32 : 11; // Bits 11:1 + U32 GDXCBAR : 27; // Bits 38:12 + U32 : 25; // Bits 63:39 + } Bits; + U64 Data; + U32 Data32[2]; + U16 Data16[4]; + U8 Data8[8]; +} NCDECS_CR_GDXCBAR_NCU_STRUCT; + +typedef union { + struct { + U32 Data : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} NCDECS_CR_SCRATCHPAD_NCU_0_STRUCT; + +typedef union { + struct { + U32 Data : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} NCDECS_CR_SCRATCHPAD_NCU_1_STRUCT; + +typedef union { + struct { + U32 Data : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} NCDECS_CR_SCRATCHPAD_NCU_2_STRUCT; + +typedef union { + struct { + U32 Data : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} NCDECS_CR_SCRATCHPAD_NCU_3_STRUCT; + +typedef union { + struct { + U32 LOCK : 1; // Bits 0:0 + U32 : 19; // Bits 19:1 + U32 OFFSET : 12; // Bits 31:20 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} NCDECS_CR_PAVPMSGOFFST_NCU_STRUCT; + +typedef union { + struct { + U32 VCPVTDLIM : 3; // Bits 2:0 + U32 : 29; // Bits 31:3 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MPVTDTRK_CR_VTDLIM_IMPH_STRUCT; + +typedef union { + struct { + U32 : 3; // Bits 2:0 + U32 DEVNUM : 5; // Bits 7:3 + U32 BUSNUM : 8; // Bits 15:8 + U32 : 15; // Bits 30:16 + U32 HDAUD_EN : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MPVTDTRK_CR_HDAUDRID_IMPH_STRUCT; + +typedef union { + struct { + U32 : 20; // Bits 19:0 + U32 UMAB : 19; // Bits 38:20 + U32 : 25; // Bits 63:39 + } Bits; + U64 Data; + U32 Data32[2]; + U16 Data16[4]; + U8 Data8[8]; +} MPVTDTRK_CR_UMAGFXBASE_IMPH_STRUCT; + +typedef union { + struct { + U32 : 20; // Bits 19:0 + U32 UMAL : 19; // Bits 38:20 + U32 : 25; // Bits 63:39 + } Bits; + U64 Data; + U32 Data32[2]; + U16 Data16[4]; + U8 Data8[8]; +} MPVTDTRK_CR_UMAGFXLIMIT_IMPH_STRUCT; + +typedef union { + struct { + U32 LCK : 1; // Bits 0:0 + U32 : 9; // Bits 9:1 + U32 PEG10EN : 1; // Bits 10:10 + U32 PEG11EN : 1; // Bits 11:11 + U32 PEG12EN : 1; // Bits 12:12 + U32 DMIEN : 1; // Bits 13:13 + U32 : 18; // Bits 31:14 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MPVTDTRK_CR_UMAGFXCTL_IMPH_STRUCT; + +typedef union { + struct { + U32 FUNNUM : 3; // Bits 2:0 + U32 DEVNUM : 5; // Bits 7:3 + U32 BUSNUM : 8; // Bits 15:8 + U32 BARNUM : 3; // Bits 18:16 + U32 : 13; // Bits 31:19 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MPVTDTRK_CR_VDMBDFBARKVM_IMPH_STRUCT; + +typedef union { + struct { + U32 FUNNUM : 3; // Bits 2:0 + U32 DEVNUM : 5; // Bits 7:3 + U32 BUSNUM : 8; // Bits 15:8 + U32 BARNUM : 3; // Bits 18:16 + U32 : 13; // Bits 31:19 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MPVTDTRK_CR_VDMBDFBARPAVP_IMPH_STRUCT; + +typedef union { + struct { + U32 DATA : 18; // Bits 17:0 + U32 : 13; // Bits 30:18 + U32 VORANGE : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MPVTDTRK_CR_VISA_CTL_MPVTDTLBS_IMPH_STRUCT; + +typedef union { + struct { + U32 DATA : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MPVTDTRK_CR_VISA_XBAR_MPVTDTLBS_IMPH_STRUCT; + +typedef union { + struct { + U32 DATA : 18; // Bits 17:0 + U32 : 13; // Bits 30:18 + U32 VORANGE : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MPVTDTRK_CR_VISA_CTL_MPVTMISCS_IMPH_STRUCT; + +typedef union { + struct { + U32 DATA : 18; // Bits 17:0 + U32 : 13; // Bits 30:18 + U32 VORANGE : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MPVTDTRK_CR_VISA_CTL_MPVTTRKS_IMPH_STRUCT; + +typedef union { + struct { + U32 VC : 4; // Bits 3:0 + U32 FMT_CMDTYPE : 6; // Bits 9:4 + U32 TC : 4; // Bits 13:10 + U32 CHAIN : 1; // Bits 14:14 + U32 NS : 1; // Bits 15:15 + U32 RO : 1; // Bits 16:16 + U32 LENGTH : 5; // Bits 21:17 + U32 EP : 1; // Bits 22:22 + U32 AT : 2; // Bits 24:23 + U32 : 7; // Bits 31:25 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MPVTDTRK_CR_PRIMUP_MASK1_IMPH_STRUCT; + +typedef union { + struct { + U32 RQID : 16; // Bits 15:0 + U32 TAG : 8; // Bits 23:16 + U32 LBEFBE_MSGTYPE : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MPVTDTRK_CR_PRIMUP_MASK2_IMPH_STRUCT; + +typedef union { + struct { + U32 ADDR_31_0 : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MPVTDTRK_CR_PRIMUP_MASK3_IMPH_STRUCT; + +typedef union { + struct { + U32 ADDR_63_32 : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MPVTDTRK_CR_PRIMUP_MASK4_IMPH_STRUCT; + +typedef union { + struct { + U32 VC : 4; // Bits 3:0 + U32 FMT_CMDTYPE : 6; // Bits 9:4 + U32 TC : 4; // Bits 13:10 + U32 CHAIN : 1; // Bits 14:14 + U32 NS : 1; // Bits 15:15 + U32 RO : 1; // Bits 16:16 + U32 LENGTH : 5; // Bits 21:17 + U32 EP : 1; // Bits 22:22 + U32 AT : 2; // Bits 24:23 + U32 : 7; // Bits 31:25 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MPVTDTRK_CR_PRIMUP_COMP1_IMPH_STRUCT; + +typedef union { + struct { + U32 RQID : 16; // Bits 15:0 + U32 TAG : 8; // Bits 23:16 + U32 LBEFBE_MSGTYPE : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MPVTDTRK_CR_PRIMUP_COMP2_IMPH_STRUCT; + +typedef union { + struct { + U32 ADDR_31_0 : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MPVTDTRK_CR_PRIMUP_COMP3_IMPH_STRUCT; + +typedef union { + struct { + U32 ADDR_63_32 : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MPVTDTRK_CR_PRIMUP_COMP4_IMPH_STRUCT; + +typedef union { + struct { + U32 ENABLE : 1; // Bits 0:0 + U32 TRIGGERED : 1; // Bits 1:1 + U32 STALL_DNARB : 1; // Bits 2:2 + U32 STALL_UPARB : 1; // Bits 3:3 + U32 STALL_SNPARB : 1; // Bits 4:4 + U32 : 18; // Bits 22:5 + U32 STALL_DELAY : 9; // Bits 31:23 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MPVTDTRK_CR_PRIMUP_TRIGGER_IMPH_STRUCT; + +typedef union { + struct { + U32 PEG2DMIDIS : 1; // Bits 0:0 + U32 EOIB : 1; // Bits 1:1 + U32 MSIBYPDIS : 1; // Bits 2:2 + U32 : 1; // Bits 3:3 + U32 PHLDDIS : 1; // Bits 4:4 + U32 : 1; // Bits 5:5 + U32 BKSNPDIS : 1; // Bits 6:6 + U32 FRCVC0SNP : 1; // Bits 7:7 + U32 FRCVCPSNP : 1; // Bits 8:8 + U32 PHLDBLKDIS : 1; // Bits 9:9 + U32 BLKWRPOSTVC1 : 1; // Bits 10:10 + U32 DIS_VLW_PEG : 1; // Bits 11:11 + U32 SPECRDDIS : 1; // Bits 12:12 + U32 IR_RSRV_CTL : 1; // Bits 13:13 + U32 RSVD : 18; // Bits 31:14 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MPVTDTRK_CR_HCTL0_IMPH_STRUCT; + +typedef union { + struct { + U32 : 4; // Bits 3:0 + U64 REGBAR : 35; // Bits 38:4 + U32 : 25; // Bits 63:39 + } Bits; + U64 Data; + U32 Data32[2]; + U16 Data16[4]; + U8 Data8[8]; +} MPVTDTRK_CR_REGBAR_IMPH_STRUCT; + +typedef union { + struct { + U32 THERMAL_MONITOR_STATUS : 1; // Bits 0:0 + U32 THERMAL_MONITOR_LOG : 1; // Bits 1:1 + U32 PROCHOT_STATUS : 1; // Bits 2:2 + U32 PROCHOT_LOG : 1; // Bits 3:3 + U32 OUT_OF_SPEC_STATUS : 1; // Bits 4:4 + U32 OUT_OF_SPEC_LOG : 1; // Bits 5:5 + U32 THRESHOLD1_STATUS : 1; // Bits 6:6 + U32 THRESHOLD1_LOG : 1; // Bits 7:7 + U32 THRESHOLD2_STATUS : 1; // Bits 8:8 + U32 THRESHOLD2_LOG : 1; // Bits 9:9 + U32 POWER_LIMITATION_STATUS : 1; // Bits 10:10 + U32 POWER_LIMITATION_LOG : 1; // Bits 11:11 + U32 : 4; // Bits 15:12 + U32 Temperature : 7; // Bits 22:16 + U32 : 4; // Bits 26:23 + U32 Resolution : 4; // Bits 30:27 + U32 Valid : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_STRUCT; + +typedef union { + struct { + U32 WARM_THRESHOLD_STATUS : 1; // Bits 0:0 + U32 WARM_THRESHOLD_LOG : 1; // Bits 1:1 + U32 HOT_THRESHOLD_STATUS : 1; // Bits 2:2 + U32 HOT_THRESHOLD_LOG : 1; // Bits 3:3 + U32 REFRESH2X_STATUS : 1; // Bits 4:4 + U32 REFRESH2X_LOG : 1; // Bits 5:5 + U32 FORCEMEMPR_STATUS : 1; // Bits 6:6 + U32 FORCEMEMPR_LOG : 1; // Bits 7:7 + U32 THRESHOLD1_STATUS : 1; // Bits 8:8 + U32 THRESHOLD1_LOG : 1; // Bits 9:9 + U32 THRESHOLD2_STATUS : 1; // Bits 10:10 + U32 THRESHOLD2_LOG : 1; // Bits 11:11 + U32 : 20; // Bits 31:12 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MPVTDTRK_CR_DDR_THERM_CAMARILLO_STATUS_IMPH_STRUCT; + +typedef union { + struct { + U32 LOCK : 1; // Bits 0:0 + U32 : 31; // Bits 31:1 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MPVTDTRK_CR_VTDTRKLCK_IMPH_STRUCT; + +typedef union { + struct { + U32 RDLIM : 3; // Bits 2:0 + U32 : 1; // Bits 3:3 + U32 WRLIM : 3; // Bits 6:4 + U32 : 24; // Bits 30:7 + U32 LOCK : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MPCBOTRK_CR_REQLIM_IMPH_STRUCT; + +typedef union { + struct { + U32 VCPNPLIM : 3; // Bits 2:0 + U32 : 1; // Bits 3:3 + U32 VCPPLIM : 3; // Bits 6:4 + U32 : 1; // Bits 7:7 + U32 VCMNPLIM : 3; // Bits 10:8 + U32 : 1; // Bits 11:11 + U32 VCMPLIM : 3; // Bits 14:12 + U32 : 1; // Bits 15:15 + U32 VCPCMPLIM : 3; // Bits 18:16 + U32 : 1; // Bits 19:19 + U32 VCMCMPLIM : 3; // Bits 22:20 + U32 : 8; // Bits 30:23 + U32 LOCK : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} HUBS_CR_DMIVCLIM_HUBS_STRUCT; + +typedef union { + struct { + U32 P0 : 1; // Bits 0:0 + U32 P1 : 1; // Bits 1:1 + U32 P2 : 1; // Bits 2:2 + U32 P3 : 1; // Bits 3:3 + U32 : 28; // Bits 31:4 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} HUBS_CR_HUB0_PWRDN_OVRD_HUBS_STRUCT; + +typedef union { + struct { + U32 P0 : 1; // Bits 0:0 + U32 P1 : 1; // Bits 1:1 + U32 P2 : 1; // Bits 2:2 + U32 P3 : 1; // Bits 3:3 + U32 : 28; // Bits 31:4 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} HUBS_CR_HUB1_PWRDN_OVRD_HUBS_STRUCT; + +typedef union { + struct { + U32 P0 : 1; // Bits 0:0 + U32 P1 : 1; // Bits 1:1 + U32 P2 : 1; // Bits 2:2 + U32 P3 : 1; // Bits 3:3 + U32 : 28; // Bits 31:4 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} HUBS_CR_HUB2_PWRDN_OVRD_HUBS_STRUCT; + +typedef union { + struct { + U32 BLK_GNT_P0 : 1; // Bits 0:0 + U32 BLK_GNT_P1 : 1; // Bits 1:1 + U32 BLK_GNT_P2 : 1; // Bits 2:2 + U32 BLK_PUT_P0 : 1; // Bits 3:3 + U32 BLK_PUT_P1 : 1; // Bits 4:4 + U32 BLK_PUT_P2 : 1; // Bits 5:5 + U32 BLK_PUT_P3 : 1; // Bits 6:6 + U32 NO_CHAIN_P0 : 1; // Bits 7:7 + U32 NO_CHAIN_P1 : 1; // Bits 8:8 + U32 NO_CHAIN_P2 : 1; // Bits 9:9 + U32 SLOW_UP_P0 : 1; // Bits 10:10 + U32 SLOW_UP_P1 : 1; // Bits 11:11 + U32 SLOW_UP_P2 : 1; // Bits 12:12 + U32 SLOW_DN_P0 : 1; // Bits 13:13 + U32 SLOW_DN_P1 : 1; // Bits 14:14 + U32 SLOW_DN_P2 : 1; // Bits 15:15 + U32 SLOW_DN_P3 : 1; // Bits 16:16 + U32 SLOWER_CMD : 1; // Bits 17:17 + U32 DMI_NOPUSH : 1; // Bits 18:18 + U32 RO_PASS_NP : 1; // Bits 19:19 + U32 RST_CRD_P3 : 1; // Bits 20:20 + U32 : 11; // Bits 31:21 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} HUBS_CR_HUB0_DEFEATURE_HUBS_STRUCT; + +typedef union { + struct { + U32 BLK_GNT_P1 : 1; // Bits 0:0 + U32 BLK_GNT_P2 : 1; // Bits 1:1 + U32 BLK_PUT_P0 : 1; // Bits 2:2 + U32 BLK_PUT_P1 : 1; // Bits 3:3 + U32 BLK_PUT_P2 : 1; // Bits 4:4 + U32 BLK_PUT_P3 : 1; // Bits 5:5 + U32 NO_CHAIN_P1 : 1; // Bits 6:6 + U32 NO_CHAIN_P2 : 1; // Bits 7:7 + U32 SLOW_UP_P0 : 1; // Bits 8:8 + U32 SLOW_UP_P1 : 1; // Bits 9:9 + U32 SLOW_UP_P2 : 1; // Bits 10:10 + U32 SLOW_DN_P1 : 1; // Bits 11:11 + U32 SLOW_DN_P2 : 1; // Bits 12:12 + U32 SLOW_DN_P3 : 1; // Bits 13:13 + U32 SLOWER_CMD : 1; // Bits 14:14 + U32 RO_PASS_NP : 1; // Bits 15:15 + U32 RST_CRD_P0 : 1; // Bits 16:16 + U32 RST_CRD_P3 : 1; // Bits 17:17 + U32 : 14; // Bits 31:18 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} HUBS_CR_HUB1_DEFEATURE_HUBS_STRUCT; + +typedef union { + struct { + U32 BLK_GNT_P1 : 1; // Bits 0:0 + U32 BLK_GNT_P2 : 1; // Bits 1:1 + U32 BLK_PUT_P0 : 1; // Bits 2:2 + U32 BLK_PUT_P1 : 1; // Bits 3:3 + U32 BLK_PUT_P2 : 1; // Bits 4:4 + U32 NO_CHAIN_P1 : 1; // Bits 5:5 + U32 NO_CHAIN_P2 : 1; // Bits 6:6 + U32 SLOW_UP_P0 : 1; // Bits 7:7 + U32 SLOW_UP_P1 : 1; // Bits 8:8 + U32 SLOW_UP_P2 : 1; // Bits 9:9 + U32 SLOW_DN_P1 : 1; // Bits 10:10 + U32 SLOW_DN_P2 : 1; // Bits 11:11 + U32 SLOWER_CMD : 1; // Bits 12:12 + U32 RST_CRD_P0 : 1; // Bits 13:13 + U32 : 18; // Bits 31:14 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} HUBS_CR_HUB2_DEFEATURE_HUBS_STRUCT; + +typedef union { + struct { + U32 PCIPWRGAT : 1; // Bits 0:0 + U32 : 31; // Bits 31:1 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} HUBS_CR_PEGCTL_HUBS_STRUCT; + +typedef union { + struct { + U32 H0_EMPTY : 1; // Bits 0:0 + U32 H1_EMPTY : 1; // Bits 1:1 + U32 H2_EMPTY : 1; // Bits 2:2 + U32 : 29; // Bits 31:3 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} HUBS_CR_HUB_EMPTY_HUBS_STRUCT; + +typedef union { + struct { + U32 REQ_VLD_P0 : 1; // Bits 0:0 + U32 REQ_VLD_P1 : 1; // Bits 1:1 + U32 REQ_VLD_P2 : 1; // Bits 2:2 + U32 REQ_VLD_P3 : 1; // Bits 3:3 + U32 TNX_VLD_P0 : 1; // Bits 4:4 + U32 TNX_VLD_P1 : 1; // Bits 5:5 + U32 TNX_VLD_P2 : 1; // Bits 6:6 + U32 TNX_VLD_P3 : 1; // Bits 7:7 + U32 : 24; // Bits 31:8 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} HUBS_CR_HUB0_STATUS_HUBS_STRUCT; + +typedef union { + struct { + U32 REQ_VLD_P0 : 1; // Bits 0:0 + U32 REQ_VLD_P1 : 1; // Bits 1:1 + U32 REQ_VLD_P2 : 1; // Bits 2:2 + U32 REQ_VLD_P3 : 1; // Bits 3:3 + U32 TNX_VLD_P0 : 1; // Bits 4:4 + U32 TNX_VLD_P1 : 1; // Bits 5:5 + U32 TNX_VLD_P2 : 1; // Bits 6:6 + U32 TNX_VLD_P3 : 1; // Bits 7:7 + U32 : 24; // Bits 31:8 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} HUBS_CR_HUB1_STATUS_HUBS_STRUCT; + +typedef union { + struct { + U32 REQ_VLD_P0 : 1; // Bits 0:0 + U32 REQ_VLD_P1 : 1; // Bits 1:1 + U32 REQ_VLD_P2 : 1; // Bits 2:2 + U32 REQ_VLD_P3 : 1; // Bits 3:3 + U32 TNX_VLD_P0 : 1; // Bits 4:4 + U32 TNX_VLD_P1 : 1; // Bits 5:5 + U32 TNX_VLD_P2 : 1; // Bits 6:6 + U32 TNX_VLD_P3 : 1; // Bits 7:7 + U32 : 24; // Bits 31:8 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} HUBS_CR_HUB2_STATUS_HUBS_STRUCT; + +typedef union { + struct { + U32 Data : 18; // Bits 17:0 + U32 : 13; // Bits 30:18 + U32 VORANGE : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} HUBS_CR_VISA_CTL_SABHUB0S_HUBS_STRUCT; + +typedef union { + struct { + U32 Data : 18; // Bits 17:0 + U32 : 13; // Bits 30:18 + U32 VORANGE : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} HUBS_CR_VISA_CTL_SABHUB1S_HUBS_STRUCT; + +typedef union { + struct { + U32 Data : 18; // Bits 17:0 + U32 : 13; // Bits 30:18 + U32 VORANGE : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} HUBS_CR_VISA_CTL_SABHUB2S_HUBS_STRUCT; + +typedef union { + struct { + U32 DATA : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} HUBS_CR_MBOX_WR_DATA_HUBS_STRUCT; + +typedef union { + struct { + U32 DATA : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} HUBS_CR_MBOX_RD_DATA_HUBS_STRUCT; + +typedef union { + struct { + U32 ADDR : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} HUBS_CR_MBOX_ADDR_LO_HUBS_STRUCT; + +typedef union { + struct { + U32 ADDR : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} HUBS_CR_MBOX_ADDR_HI_HUBS_STRUCT; + +typedef union { + struct { + U32 FBE : 4; // Bits 3:0 + U32 LBE : 4; // Bits 7:4 + U32 TAG : 8; // Bits 15:8 + U32 RQID : 16; // Bits 31:16 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} HUBS_CR_MBOX_CMD_LO_HUBS_STRUCT; + +typedef union { + struct { + U32 AT : 2; // Bits 1:0 + U32 POISON : 1; // Bits 2:2 + U32 LENGTH : 5; // Bits 7:3 + U32 RELAXED : 1; // Bits 8:8 + U32 NOSNOOP : 1; // Bits 9:9 + U32 CHAIN : 1; // Bits 10:10 + U32 CTYPE : 5; // Bits 15:11 + U32 FMT : 2; // Bits 17:16 + U32 TC : 4; // Bits 21:18 + U32 RESERVED : 2; // Bits 23:22 + U32 DMI_PRIV : 1; // Bits 24:24 + U32 CHID : 4; // Bits 28:25 + U32 RTYPE : 2; // Bits 30:29 + U32 START : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} HUBS_CR_MBOX_CMD_HI_HUBS_STRUCT; + +typedef union { + struct { + U32 ENABLE : 1; // Bits 0:0 + U32 LOCK_IA : 1; // Bits 1:1 + U32 RESET : 1; // Bits 2:2 + U32 BLK_CYCLES : 6; // Bits 8:3 + U32 WR_DWORD_SEL : 4; // Bits 12:9 + U32 RD_DWORD_SEL : 4; // Bits 16:13 + U32 RPT_CMD_CNT : 6; // Bits 22:17 + U32 RPT_NXT_ADDR : 1; // Bits 23:23 + U32 RPT_NXT_PAGE : 1; // Bits 24:24 + U32 DIS_CMP_INV : 1; // Bits 25:25 + U32 FSM_STATE : 4; // Bits 29:26 + U32 P2P_ALL : 1; // Bits 30:30 + U32 SPARE : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} HUBS_CR_MBOX_CFG_HUBS_STRUCT; + +typedef union { + struct { + U32 FSM_STATE : 4; // Bits 3:0 + U32 RPT_CMD_CNT : 6; // Bits 9:4 + U32 OPCODE : 7; // Bits 16:10 + U32 WR_DWORD_SEL : 4; // Bits 20:17 + U32 RD_DWORD_SEL : 4; // Bits 24:21 + U32 P2P_RD_UP : 1; // Bits 25:25 + U32 P2P_RD_DN : 1; // Bits 26:26 + U32 SPARE : 5; // Bits 31:27 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} HUBS_CR_MBOX_STATUS_HUBS_STRUCT; + +typedef union { + struct { + U32 XTM_CHID : 9; // Bits 8:0 + U32 NP : 1; // Bits 9:9 + U32 PC : 1; // Bits 10:10 + U32 : 21; // Bits 31:11 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} HUBS_CR_HUB0_BLOCK_UP_HUBS_STRUCT; + +typedef union { + struct { + U32 DMIVC0_PMIN : 3; // Bits 2:0 + U32 P10VC0_PMIN : 3; // Bits 5:3 + U32 P11VC0_PMIN : 3; // Bits 8:6 + U32 P12VC0_PMIN : 3; // Bits 11:9 + U32 DEVC0_PMIN : 3; // Bits 14:12 + U32 DMIVCP_PMIN : 3; // Bits 17:15 + U32 DMIVCM_PMIN : 3; // Bits 20:18 + U32 DMIVC1_PMIN : 3; // Bits 23:21 + U32 : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MPRDRTRN_CR_CRDTCTL0_IMPH_STRUCT; + +typedef union { + struct { + U32 DMIVC0_NPMIN : 3; // Bits 2:0 + U32 P10VC0_NPMIN : 3; // Bits 5:3 + U32 P11VC0_NPMIN : 3; // Bits 8:6 + U32 P12VC0_NPMIN : 3; // Bits 11:9 + U32 DEVC0_NPMIN : 3; // Bits 14:12 + U32 DMIVCP_NPMIN : 3; // Bits 17:15 + U32 DMIVCM_NPMIN : 3; // Bits 20:18 + U32 DMIVC1_NPMIN : 3; // Bits 23:21 + U32 : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MPRDRTRN_CR_CRDTCTL1_IMPH_STRUCT; + +typedef union { + struct { + U32 DMIVC0_RRMIN : 3; // Bits 2:0 + U32 P10VC0_RRMIN : 3; // Bits 5:3 + U32 P11VC0_RRMIN : 3; // Bits 8:6 + U32 P12VC0_RRMIN : 3; // Bits 11:9 + U32 DEVC0_RRMIN : 3; // Bits 14:12 + U32 DMIVCP_RRMIN : 3; // Bits 17:15 + U32 DMIVCM_RRMIN : 3; // Bits 20:18 + U32 DMIVC1_RRMIN : 3; // Bits 23:21 + U32 DEVC1_RRMIN : 6; // Bits 29:24 + U32 : 2; // Bits 31:30 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MPRDRTRN_CR_CRDTCTL2_IMPH_STRUCT; + +typedef union { + struct { + U32 IOTRK_SHRD : 6; // Bits 5:0 + U32 RRTRK_SHRD : 7; // Bits 12:6 + U32 : 19; // Bits 31:13 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MPRDRTRN_CR_CRDTCTL3_IMPH_STRUCT; + +typedef union { + struct { + U32 DMIVC0_PMAX : 5; // Bits 4:0 + U32 P10VC0_PMAX : 5; // Bits 9:5 + U32 P11VC0_PMAX : 5; // Bits 14:10 + U32 P12VC0_PMAX : 5; // Bits 19:15 + U32 DEVC0_PMAX : 5; // Bits 24:20 + U32 : 7; // Bits 31:25 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MPRDRTRN_CR_CRDTCTL4_IMPH_STRUCT; + +typedef union { + struct { + U32 DMIVCP_PMAX : 5; // Bits 4:0 + U32 DMIVCM_PMAX : 5; // Bits 9:5 + U32 DMIVC1_PMAX : 5; // Bits 14:10 + U32 : 17; // Bits 31:15 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MPRDRTRN_CR_CRDTCTL5_IMPH_STRUCT; + +typedef union { + struct { + U32 DMIVC0_NPMAX : 5; // Bits 4:0 + U32 P10VC0_NPMAX : 5; // Bits 9:5 + U32 P11VC0_NPMAX : 5; // Bits 14:10 + U32 P12VC0_NPMAX : 5; // Bits 19:15 + U32 DEVC0_NPMAX : 5; // Bits 24:20 + U32 : 7; // Bits 31:25 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MPRDRTRN_CR_CRDTCTL6_IMPH_STRUCT; + +typedef union { + struct { + U32 DMIVCP_NPMAX : 5; // Bits 4:0 + U32 DMIVCM_NPMAX : 5; // Bits 9:5 + U32 DMIVC1_NPMAX : 5; // Bits 14:10 + U32 : 17; // Bits 31:15 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MPRDRTRN_CR_CRDTCTL7_IMPH_STRUCT; + +typedef union { + struct { + U32 DATA : 18; // Bits 17:0 + U32 : 13; // Bits 30:18 + U32 VORANGE : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MPRDRTRN_CR_VISA_CTL_MPIORDTRKS_IMPH_STRUCT; + +typedef union { + struct { + U32 DATA : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MPRDRTRN_CR_VISA_XBAR_MPIORDTRKS_IMPH_STRUCT; + +typedef union { + struct { + U32 DATA : 18; // Bits 17:0 + U32 : 13; // Bits 30:18 + U32 VORANGE : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MPRDRTRN_CR_VISA_CTL_MPIOTRKS_IMPH_STRUCT; + +typedef union { + struct { + U32 VC : 4; // Bits 3:0 + U32 FMT_CMDTYPE : 6; // Bits 9:4 + U32 TC : 4; // Bits 13:10 + U32 NS : 1; // Bits 14:14 + U32 RO : 1; // Bits 15:15 + U32 LENGTH : 5; // Bits 20:16 + U32 EP : 1; // Bits 21:21 + U32 : 10; // Bits 31:22 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MPRDRTRN_CR_PRIMDN_MASK1_IMPH_STRUCT; + +typedef union { + struct { + U32 RQID : 16; // Bits 15:0 + U32 TAG : 8; // Bits 23:16 + U32 LBEFBE_MSGTYPE : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MPRDRTRN_CR_PRIMDN_MASK2_IMPH_STRUCT; + +typedef union { + struct { + U32 ADDR_31_0 : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MPRDRTRN_CR_PRIMDN_MASK3_IMPH_STRUCT; + +typedef union { + struct { + U32 ADDR_63_32 : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MPRDRTRN_CR_PRIMDN_MASK4_IMPH_STRUCT; + +typedef union { + struct { + U32 VC : 4; // Bits 3:0 + U32 FMT_CMDTYPE : 6; // Bits 9:4 + U32 TC : 4; // Bits 13:10 + U32 EP : 1; // Bits 14:14 + U32 NS : 1; // Bits 15:15 + U32 RO : 1; // Bits 16:16 + U32 LENGTH : 5; // Bits 21:17 + U32 : 10; // Bits 31:22 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MPRDRTRN_CR_PRIMDN_COMP1_IMPH_STRUCT; + +typedef union { + struct { + U32 RQID : 16; // Bits 15:0 + U32 TAG : 8; // Bits 23:16 + U32 LBEFBE_MSGTYPE : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MPRDRTRN_CR_PRIMDN_COMP2_IMPH_STRUCT; + +typedef union { + struct { + U32 ADDR_31_0 : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MPRDRTRN_CR_PRIMDN_COMP3_IMPH_STRUCT; + +typedef union { + struct { + U32 ADDR_63_32 : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MPRDRTRN_CR_PRIMDN_COMP4_IMPH_STRUCT; + +typedef union { + struct { + U32 ENABLE : 1; // Bits 0:0 + U32 TRIGGERED : 1; // Bits 1:1 + U32 STALL_DNARB : 1; // Bits 2:2 + U32 : 20; // Bits 22:3 + U32 STALL_DELAY : 9; // Bits 31:23 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MPRDRTRN_CR_PRIMDN_TRIGGER_IMPH_STRUCT; + +typedef union { + struct { + U32 DMIVC0_RRMAX : 6; // Bits 5:0 + U32 P10VC0_RRMAX : 6; // Bits 11:6 + U32 P11VC0_RRMAX : 6; // Bits 17:12 + U32 P12VC0_RRMAX : 6; // Bits 23:18 + U32 DEVC0_RRMAX : 6; // Bits 29:24 + U32 : 2; // Bits 31:30 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MPRDRTRN_CR_CRDTCTL8_IMPH_STRUCT; + +typedef union { + struct { + U32 DMIVCP_RRMAX : 6; // Bits 5:0 + U32 DMIVCM_RRMAX : 6; // Bits 11:6 + U32 DMIVC1_RRMAX : 6; // Bits 17:12 + U32 DEVC1_RRMAX : 6; // Bits 23:18 + U32 : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MPRDRTRN_CR_CRDTCTL9_IMPH_STRUCT; + +typedef union { + struct { + U32 LIM : 16; // Bits 15:0 + U32 MSK : 3; // Bits 18:16 + U32 : 13; // Bits 31:19 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MPRDRTRN_CR_PCIE_POPUP_CTL_IMPH_STRUCT; + +typedef union { + struct { + U32 FUNNUM : 3; // Bits 2:0 + U32 DEVNUM : 5; // Bits 7:3 + U32 BUSNUM : 8; // Bits 15:8 + U32 BARNUM : 3; // Bits 18:16 + U32 : 13; // Bits 31:19 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MPRDRTRN_CR_VDMBDFBARSSKU_IMPH_STRUCT; + +typedef union { + struct { + U32 LOCK : 1; // Bits 0:0 + U32 : 31; // Bits 31:1 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MPRDRTRN_CR_CRDTLCK_IMPH_STRUCT; + +typedef union { + struct { + U32 VCPNPLIM : 3; // Bits 2:0 + U32 : 1; // Bits 3:3 + U32 VCPPLIM : 3; // Bits 6:4 + U32 : 1; // Bits 7:7 + U32 VCMNPLIM : 3; // Bits 10:8 + U32 : 1; // Bits 11:11 + U32 VCMPLIM : 3; // Bits 14:12 + U32 : 1; // Bits 15:15 + U32 VC0VTDLIM : 3; // Bits 18:16 + U32 : 1; // Bits 19:19 + U32 VCPVTDLIM : 3; // Bits 22:20 + U32 : 9; // Bits 31:23 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MPMCARB_CR_VCLIM0_IMPH_STRUCT; + +typedef union { + struct { + U32 IARD : 3; // Bits 2:0 + U32 : 1; // Bits 3:3 + U32 IAWR : 3; // Bits 6:4 + U32 : 1; // Bits 7:7 + U32 VTDL3 : 3; // Bits 10:8 + U32 : 1; // Bits 11:11 + U32 VTDNL3 : 3; // Bits 14:12 + U32 : 17; // Bits 31:15 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MPMCARB_CR_VCLIM1_IMPH_STRUCT; + +typedef union { + struct { + U32 VC1_WR_CNFLT : 1; // Bits 0:0 + U32 VC1_RD_CNFLT : 1; // Bits 1:1 + U32 : 30; // Bits 31:2 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MPMCARB_CR_ATMC_STS_IMPH_STRUCT; + +typedef union { + struct { + U32 DATA : 18; // Bits 17:0 + U32 : 13; // Bits 30:18 + U32 VORANGE : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MPMCARB_CR_VISA_CTL_MPMCARBS_F_IMPH_STRUCT; + +typedef union { + struct { + U32 DATA : 18; // Bits 17:0 + U32 : 13; // Bits 30:18 + U32 VORANGE : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MPMCARB_CR_VISA_CTL_MPMCARBS_D_IMPH_STRUCT; + +typedef union { + struct { + U32 LOCK : 1; // Bits 0:0 + U32 : 31; // Bits 31:1 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MPMCARB_CR_MCARBLCK_IMPH_STRUCT; + +typedef union { + struct { + U32 DATA : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} PCU_CR_CAMARILLO_MAILBOX_DATA0_PCU_STRUCT; + +typedef union { + struct { + U32 DATA : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} PCU_CR_CAMARILLO_MAILBOX_DATA1_PCU_STRUCT; + +typedef union { + struct { + U32 COMMAND : 8; // Bits 7:0 + U32 ADDR_CNTL : 21; // Bits 28:8 + U32 : 2; // Bits 30:29 + U32 RUN_BUSY : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} PCU_CR_CAMARILLO_MAILBOX_INTERFACE_PCU_STRUCT; + +typedef union { + struct { + U32 HIGH_TEMP_INT_ENABLE : 1; // Bits 0:0 + U32 LOW_TEMP_INT_ENABLE : 1; // Bits 1:1 + U32 PROCHOT_INT_ENABLE : 1; // Bits 2:2 + U32 : 1; // Bits 3:3 + U32 OUT_OF_SPEC_INT_ENABLE : 1; // Bits 4:4 + U32 : 3; // Bits 7:5 + U32 THRESHOLD_1_REL_TEMP : 7; // Bits 14:8 + U32 THRESHOLD_1_INT_ENABLE : 1; // Bits 15:15 + U32 THRESHOLD_2_REL_TEMP : 7; // Bits 22:16 + U32 THRESHOLD_2_INT_ENABLE : 1; // Bits 23:23 + U32 POWER_INT_ENABLE : 1; // Bits 24:24 + U32 : 7; // Bits 31:25 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} PCU_CR_PACKAGE_THERM_CAMARILLO_INTERRUPT_PCU_STRUCT; + +typedef union { + struct { + U32 OLTM_ENABLE : 1; // Bits 0:0 + U32 CLTM_ENABLE : 1; // Bits 1:1 + U32 REFRESH_2X_MODE : 2; // Bits 3:2 + U32 EXTTS_ENABLE : 1; // Bits 4:4 + U32 LOCK_PTM_REGS_PCU : 1; // Bits 5:5 + U32 PDWN_CONFIG_CTL : 1; // Bits 6:6 + U32 DISABLE_DRAM_TS : 1; // Bits 7:7 + U32 : 24; // Bits 31:8 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} PCU_CR_DDR_PTM_CTL_PCU_STRUCT; + +typedef union { + struct { + U32 SCALEFACTOR : 3; // Bits 2:0 + U32 : 29; // Bits 31:3 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} PCU_CR_DDR_ENERGY_SCALEFACTOR_PCU_STRUCT; + +typedef union { + struct { + U32 CH0 : 8; // Bits 7:0 + U32 CH1 : 8; // Bits 15:8 + U32 : 16; // Bits 31:16 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} PCU_CR_DDR_RAPL_CHANNEL_POWER_FLOOR_PCU_STRUCT; + +typedef union { + struct { + U32 CH0_DIMM0 : 2; // Bits 1:0 + U32 CH0_DIMM1 : 2; // Bits 3:2 + U32 : 4; // Bits 7:4 + U32 CH1_DIMM0 : 2; // Bits 9:8 + U32 CH1_DIMM1 : 2; // Bits 11:10 + U32 : 20; // Bits 31:12 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} PCU_CR_DDR_THERM_PERDIMM_STATUS_PCU_STRUCT; + +typedef union { + struct { + U32 DIMM0 : 8; // Bits 7:0 + U32 DIMM1 : 8; // Bits 15:8 + U32 : 16; // Bits 31:16 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} PCU_CR_DDR_WARM_THRESHOLD_CH0_PCU_STRUCT; + +typedef union { + struct { + U32 DIMM0 : 8; // Bits 7:0 + U32 DIMM1 : 8; // Bits 15:8 + U32 : 16; // Bits 31:16 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} PCU_CR_DDR_WARM_THRESHOLD_CH1_PCU_STRUCT; + +typedef union { + struct { + U32 DIMM0 : 8; // Bits 7:0 + U32 DIMM1 : 8; // Bits 15:8 + U32 : 16; // Bits 31:16 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} PCU_CR_DDR_HOT_THRESHOLD_CH0_PCU_STRUCT; + +typedef union { + struct { + U32 DIMM0 : 8; // Bits 7:0 + U32 DIMM1 : 8; // Bits 15:8 + U32 : 16; // Bits 31:16 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} PCU_CR_DDR_HOT_THRESHOLD_CH1_PCU_STRUCT; + +typedef union { + struct { + U32 ENABLE_WARM_INTERRUPT : 1; // Bits 0:0 + U32 : 1; // Bits 1:1 + U32 ENABLE_HOT_INTERRUPT : 1; // Bits 2:2 + U32 : 1; // Bits 3:3 + U32 ENABLE_2X_REFRESH_INTERRUPT : 1; // Bits 4:4 + U32 : 3; // Bits 7:5 + U32 ENABLE_THRESHOLD1_INTERRUPT : 1; // Bits 8:8 + U32 : 1; // Bits 9:9 + U32 ENABLE_THRESHOLD2_INTERRUPT : 1; // Bits 10:10 + U32 : 5; // Bits 15:11 + U32 POLICY_FREE_THRESHOLD1 : 8; // Bits 23:16 + U32 POLICY_FREE_THRESHOLD2 : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} PCU_CR_DDR_THERM_CAMARILLO_INTERRUPT_PCU_STRUCT; + +typedef union { + struct { + U32 DDR_VOLTAGE : 3; // Bits 2:0 + U32 : 29; // Bits 31:3 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} PCU_CR_DDR_VOLTAGE_PCU_STRUCT; + +typedef union { + struct { + U32 THERM_MARGIN : 16; // Bits 15:0 + U32 : 16; // Bits 31:16 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} PCU_CR_PACKAGE_THERM_MARGIN_PCU_STRUCT; + +typedef union { + struct { + U32 DIMM0 : 8; // Bits 7:0 + U32 DIMM1 : 8; // Bits 15:8 + U32 : 16; // Bits 31:16 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} PCU_CR_DDR_DIMM_TEMPERATURE_CH0_PCU_STRUCT; + +typedef union { + struct { + U32 DIMM0 : 8; // Bits 7:0 + U32 DIMM1 : 8; // Bits 15:8 + U32 : 16; // Bits 31:16 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} PCU_CR_DDR_DIMM_TEMPERATURE_CH1_PCU_STRUCT; + +typedef union { + struct { + U32 TEMPERATURE : 8; // Bits 7:0 + U32 : 24; // Bits 31:8 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} PCU_CR_DDR_DIMM_HOTTEST_ABSOLUTE_PCU_STRUCT; + +typedef union { + struct { + U32 TEMPERATURE : 8; // Bits 7:0 + U32 : 24; // Bits 31:8 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} PCU_CR_DDR_DIMM_HOTTEST_RELATIVE_PCU_STRUCT; + +typedef union { + struct { + U32 DIMM0 : 16; // Bits 15:0 + U32 DIMM1 : 16; // Bits 31:16 + U32 : 32; // Bits 63:32 + } Bits; + U64 Data; + U32 Data32[2]; + U16 Data16[4]; + U8 Data8[8]; +} PCU_CR_DDR_THROTTLE_DURATION_CH0_PCU_STRUCT; + +typedef union { + struct { + U32 DIMM0 : 16; // Bits 15:0 + U32 DIMM1 : 16; // Bits 31:16 + U32 : 32; // Bits 63:32 + } Bits; + U64 Data; + U32 Data32[2]; + U16 Data16[4]; + U8 Data8[8]; +} PCU_CR_DDR_THROTTLE_DURATION_CH1_PCU_STRUCT; + +typedef union { + struct { + U32 DIMM0 : 8; // Bits 7:0 + U32 DIMM1 : 8; // Bits 15:8 + U32 : 16; // Bits 31:16 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} PCU_CR_DDR_WARM_BUDGET_CH0_PCU_STRUCT; + +typedef union { + struct { + U32 DIMM0 : 8; // Bits 7:0 + U32 DIMM1 : 8; // Bits 15:8 + U32 : 16; // Bits 31:16 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} PCU_CR_DDR_WARM_BUDGET_CH1_PCU_STRUCT; + +typedef union { + struct { + U32 DIMM0 : 8; // Bits 7:0 + U32 DIMM1 : 8; // Bits 15:8 + U32 : 16; // Bits 31:16 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} PCU_CR_DDR_HOT_BUDGET_CH0_PCU_STRUCT; + +typedef union { + struct { + U32 DIMM0 : 8; // Bits 7:0 + U32 DIMM1 : 8; // Bits 15:8 + U32 : 16; // Bits 31:16 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} PCU_CR_DDR_HOT_BUDGET_CH1_PCU_STRUCT; + +typedef union { + struct { + U32 LIMIT1_POWER : 15; // Bits 14:0 + U32 LIMIT1_ENABLE : 1; // Bits 15:15 + U32 : 1; // Bits 16:16 + U32 LIMIT1_TIME_WINDOW_Y : 5; // Bits 21:17 + U32 LIMIT1_TIME_WINDOW_X : 2; // Bits 23:22 + U32 : 8; // Bits 31:24 + U32 LIMIT2_POWER : 15; // Bits 46:32 + U32 LIMIT2_ENABLE : 1; // Bits 47:47 + U32 : 1; // Bits 48:48 + U32 LIMIT2_TIME_WINDOW_Y : 5; // Bits 53:49 + U32 LIMIT2_TIME_WINDOW_X : 2; // Bits 55:54 + U32 : 7; // Bits 62:56 + U32 LOCKED : 1; // Bits 63:63 + } Bits; + U64 Data; + U32 Data32[2]; + U16 Data16[4]; + U8 Data8[8]; +} PCU_CR_DDR_RAPL_LIMIT_PCU_STRUCT; + +typedef union { + struct { + U32 JOULES_CONSUMED : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} PCU_CR_DDR_ENERGY_STATUS_PCU_STRUCT; + +typedef union { + struct { + U32 DURATION : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} PCU_CR_DDR_RAPL_PERF_STATUS_PCU_STRUCT; + +typedef union { + struct { + U32 COUNTS : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} PCU_CR_PACKAGE_RAPL_PERF_STATUS_PCU_STRUCT; + +typedef union { + struct { + U32 IA_MIN_RATIO_REQUEST : 8; // Bits 7:0 + U32 CLR_MIN_RATIO_REQUEST : 8; // Bits 15:8 + U32 : 16; // Bits 31:16 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} PCU_CR_GT_RATIOS_OVERRIDE_PCU_STRUCT; + +typedef union { + struct { + U32 DDR_ACCESS_TIME : 14; // Bits 13:0 + U32 RESERVED : 1; // Bits 14:14 + U32 CLR_ACCESS_TIME : 14; // Bits 28:15 + U32 NON_SNOOP_THRESHOLD_RESOLUTION : 1; // Bits 29:29 + U32 SLOW_SNOOP_THRESHOLD_RESOLUTION : 1; // Bits 30:30 + U32 FAST_SNOOP_THRESHOLD_RESOLUTION : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} PCU_CR_PKGC_LTR_LATENCY_MEASUREMENTS_PCU_STRUCT; + +typedef union { + struct { + U32 PROCHOT_STATUS : 1; // Bits 0:0 + U32 THERMAL_STATUS : 1; // Bits 1:1 + U32 SPARE_IA_2 : 1; // Bits 2:2 + U32 PBM_PL1_STATUS : 1; // Bits 3:3 + U32 PBM_PL2_STATUS : 1; // Bits 4:4 + U32 PBM_PLIA_STATUS : 1; // Bits 5:5 + U32 SPARE_IA_6 : 1; // Bits 6:6 + U32 GTDRIVER_STATUS : 1; // Bits 7:7 + U32 VR_THERMALERT_STATUS : 1; // Bits 8:8 + U32 FUSE_MAX_TURBO_LIMIT_STATUS : 1; // Bits 9:9 + U32 EDP_ICC_STATUS : 1; // Bits 10:10 + U32 TURBO_ATTEN_STATUS : 1; // Bits 11:11 + U32 SPARE_IA_12 : 1; // Bits 12:12 + U32 SPARE_IA_13 : 1; // Bits 13:13 + U32 SPARE_IA_14 : 1; // Bits 14:14 + U32 SPARE_IA_15 : 1; // Bits 15:15 + U32 PROCHOT_LOG : 1; // Bits 16:16 + U32 THERMAL_LOG : 1; // Bits 17:17 + U32 SPARE_IA_LOG_2 : 1; // Bits 18:18 + U32 PBM_PL1_LOG : 1; // Bits 19:19 + U32 PBM_PL2_LOG : 1; // Bits 20:20 + U32 PBM_PLIA_LOG : 1; // Bits 21:21 + U32 SPARE_IA_LOG_6 : 1; // Bits 22:22 + U32 GTDRIVER_LOG : 1; // Bits 23:23 + U32 VR_THERMALERT_LOG : 1; // Bits 24:24 + U32 FUSE_MAX_TURBO_LIMIT_LOG : 1; // Bits 25:25 + U32 EDP_ICC_LOG : 1; // Bits 26:26 + U32 TURBO_ATTEN_LOG : 1; // Bits 27:27 + U32 SPARE_IA_LOG_12 : 1; // Bits 28:28 + U32 SPARE_IA_LOG_13 : 1; // Bits 29:29 + U32 SPARE_IA_LOG_14 : 1; // Bits 30:30 + U32 SPARE_IA_LOG_15 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} PCU_CR_IA_PERF_LIMIT_REASONS_PCU_STRUCT; + +typedef union { + struct { + U32 PROCHOT_STATUS : 1; // Bits 0:0 + U32 THERMAL_STATUS : 1; // Bits 1:1 + U32 SPARE_GT_2 : 1; // Bits 2:2 + U32 PBM_PL1_STATUS : 1; // Bits 3:3 + U32 PBM_PL2_STATUS : 1; // Bits 4:4 + U32 PBM_PLGT_STATUS : 1; // Bits 5:5 + U32 SPARE_GT_6 : 1; // Bits 6:6 + U32 SPARE_GT_7 : 1; // Bits 7:7 + U32 VR_THERMALERT_STATUS : 1; // Bits 8:8 + U32 SPARE_GT_9 : 1; // Bits 9:9 + U32 EDP_ICC_STATUS : 1; // Bits 10:10 + U32 SPARE_GT_11 : 1; // Bits 11:11 + U32 SPARE_GT_12 : 1; // Bits 12:12 + U32 SPARE_GT_13 : 1; // Bits 13:13 + U32 SPARE_GT_14 : 1; // Bits 14:14 + U32 SPARE_GT_15 : 1; // Bits 15:15 + U32 PROCHOT_LOG : 1; // Bits 16:16 + U32 THERMAL_LOG : 1; // Bits 17:17 + U32 SPARE_GT_LOG_2 : 1; // Bits 18:18 + U32 PBM_PL1_LOG : 1; // Bits 19:19 + U32 PBM_PL2_LOG : 1; // Bits 20:20 + U32 PBM_PLGT_LOG : 1; // Bits 21:21 + U32 SPARE_GT_LOG_6 : 1; // Bits 22:22 + U32 SPARE_GT_LOG_7 : 1; // Bits 23:23 + U32 VR_THERMALERT_LOG : 1; // Bits 24:24 + U32 SPARE_GT_LOG_9 : 1; // Bits 25:25 + U32 EDP_ICC_LOG : 1; // Bits 26:26 + U32 SPARE_GT_LOG_11 : 1; // Bits 27:27 + U32 SPARE_GT_LOG_12 : 1; // Bits 28:28 + U32 SPARE_GT_LOG_13 : 1; // Bits 29:29 + U32 SPARE_GT_LOG_14 : 1; // Bits 30:30 + U32 SPARE_GT_LOG_15 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} PCU_CR_GT_PERF_LIMIT_REASONS_PCU_STRUCT; + +typedef union { + struct { + U32 PROCHOT_STATUS : 1; // Bits 0:0 + U32 THERMAL_STATUS : 1; // Bits 1:1 + U32 SPARE_CLR_2 : 1; // Bits 2:2 + U32 PBM_PL1_STATUS : 1; // Bits 3:3 + U32 PBM_PL2_STATUS : 1; // Bits 4:4 + U32 SPARE_CLR_5 : 1; // Bits 5:5 + U32 SPARE_CLR_6 : 1; // Bits 6:6 + U32 SPARE_CLR_7 : 1; // Bits 7:7 + U32 VR_THERMALERT_STATUS : 1; // Bits 8:8 + U32 SPARE_CLR_9 : 1; // Bits 9:9 + U32 EDP_ICC_STATUS : 1; // Bits 10:10 + U32 SPARE_CLR_11 : 1; // Bits 11:11 + U32 SPARE_CLR_12 : 1; // Bits 12:12 + U32 SPARE_CLR_13 : 1; // Bits 13:13 + U32 SPARE_CLR_14 : 1; // Bits 14:14 + U32 SPARE_CLR_15 : 1; // Bits 15:15 + U32 PROCHOT_LOG : 1; // Bits 16:16 + U32 THERMAL_LOG : 1; // Bits 17:17 + U32 SPARE_CLR_LOG_2 : 1; // Bits 18:18 + U32 PBM_PL1_LOG : 1; // Bits 19:19 + U32 PBM_PL2_LOG : 1; // Bits 20:20 + U32 SPARE_CLR_LOG_5 : 1; // Bits 21:21 + U32 SPARE_CLR_LOG_6 : 1; // Bits 22:22 + U32 SPARE_CLR_LOG_7 : 1; // Bits 23:23 + U32 VR_THERMALERT_LOG : 1; // Bits 24:24 + U32 SPARE_CLR_LOG_9 : 1; // Bits 25:25 + U32 EDP_ICC_LOG : 1; // Bits 26:26 + U32 SPARE_CLR_LOG_11 : 1; // Bits 27:27 + U32 SPARE_CLR_LOG_12 : 1; // Bits 28:28 + U32 SPARE_CLR_LOG_13 : 1; // Bits 29:29 + U32 SPARE_CLR_LOG_14 : 1; // Bits 30:30 + U32 SPARE_CLR_LOG_15 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_STRUCT; + +typedef union { + struct { + U32 PRIPTP : 5; // Bits 4:0 + U32 : 27; // Bits 31:5 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} PCU_CR_PRIP_TURBO_PLCY_PCU_STRUCT; + +typedef union { + struct { + U32 SECPTP : 5; // Bits 4:0 + U32 : 27; // Bits 31:5 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} PCU_CR_SECP_TURBO_PLCY_PCU_STRUCT; + +typedef union { + struct { + U32 DATA : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} PCU_CR_PRIP_NRG_STTS_PCU_STRUCT; + +typedef union { + struct { + U32 DATA : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} PCU_CR_SECP_NRG_STTS_PCU_STRUCT; + +typedef union { + struct { + U32 PKG_TDP : 15; // Bits 14:0 + U32 : 1; // Bits 15:15 + U32 PKG_MIN_PWR : 15; // Bits 30:16 + U32 : 1; // Bits 31:31 + U32 PKG_MAX_PWR : 15; // Bits 46:32 + U32 : 1; // Bits 47:47 + U32 PKG_MAX_WIN : 7; // Bits 54:48 + U32 : 9; // Bits 63:55 + } Bits; + U64 Data; + U32 Data32[2]; + U16 Data16[4]; + U8 Data8[8]; +} PCU_CR_PACKAGE_POWER_SKU_PCU_STRUCT; + +typedef union { + struct { + U32 PWR_UNIT : 4; // Bits 3:0 + U32 : 4; // Bits 7:4 + U32 ENERGY_UNIT : 5; // Bits 12:8 + U32 : 3; // Bits 15:13 + U32 TIME_UNIT : 4; // Bits 19:16 + U32 : 12; // Bits 31:20 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} PCU_CR_PACKAGE_POWER_SKU_UNIT_PCU_STRUCT; + +typedef union { + struct { + U32 DATA : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} PCU_CR_PACKAGE_ENERGY_STATUS_PCU_STRUCT; + +typedef union { + struct { + U32 DATA : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} PCU_CR_GT_IO_BUSYNESS_PCU_STRUCT; + +typedef union { + struct { + U32 DATA : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} PCU_CR_GT_VIDEO_BUSYNESS_PCU_STRUCT; + +typedef union { + struct { + U32 RP_STATE_VOLTAGE : 8; // Bits 7:0 + U32 RP_STATE_RATIO : 8; // Bits 15:8 + U32 : 16; // Bits 31:16 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} PCU_CR_GT_PERF_STATUS_PCU_STRUCT; + +typedef union { + struct { + U64 : 50; // Bits 49:0 + U32 PLATFORMID : 3; // Bits 52:50 + U32 : 11; // Bits 63:53 + } Bits; + U64 Data; + U32 Data32[2]; + U16 Data16[4]; + U8 Data8[8]; +} PCU_CR_PLATFORM_ID_PCU_STRUCT; + +typedef union { + struct { + U32 : 8; // Bits 7:0 + U32 MAX_NON_TURBO_LIM_RATIO : 8; // Bits 15:8 + U32 SMM_SAVE_CAP : 1; // Bits 16:16 + U32 : 7; // Bits 23:17 + U32 OCVOLT_OVRD_AVAIL : 1; // Bits 24:24 + U32 FIVR_RFI_TUNING_AVAIL : 1; // Bits 25:25 + U32 DCU_16K_MODE_AVAIL : 1; // Bits 26:26 + U32 SAMPLE_PART : 1; // Bits 27:27 + U32 PRG_TURBO_RATIO_EN : 1; // Bits 28:28 + U32 PRG_TDP_LIM_EN : 1; // Bits 29:29 + U32 PRG_TJ_OFFSET_EN : 1; // Bits 30:30 + U32 CPUID_FAULTING_EN : 1; // Bits 31:31 + U32 LPM_SUPPORT : 1; // Bits 32:32 + U32 CONFIG_TDP_LEVELS : 2; // Bits 34:33 + U32 PFAT_ENABLE : 1; // Bits 35:35 + U32 : 1; // Bits 36:36 + U32 TIMED_MWAIT_ENABLE : 1; // Bits 37:37 + U32 : 2; // Bits 39:38 + U32 MAX_EFFICIENCY_RATIO : 8; // Bits 47:40 + U32 MIN_OPERATING_RATIO : 8; // Bits 55:48 + U32 : 8; // Bits 63:56 + } Bits; + U64 Data; + U32 Data32[2]; + U16 Data16[4]; + U8 Data8[8]; +} PCU_CR_PLATFORM_INFO_PCU_STRUCT; + +typedef union { + struct { + U32 DATA : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} PCU_CR_PP1_C0_CORE_CLOCK_PCU_STRUCT; + +typedef union { + struct { + U32 DATA : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} PCU_CR_PP0_ANY_THREAD_ACTIVITY_PCU_STRUCT; + +typedef union { + struct { + U32 DATA : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} PCU_CR_PP0_EFFICIENT_CYCLES_PCU_STRUCT; + +typedef union { + struct { + U32 DATA : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} PCU_CR_PP0_THREAD_ACTIVITY_PCU_STRUCT; + +typedef union { + struct { + U32 DATA : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} PCU_CR_PP1_ANY_THREAD_ACTIVITY_PCU_STRUCT; + +typedef union { + struct { + U32 DATA : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} PCU_CR_PP1_EFFICIENT_CYCLES_PCU_STRUCT; + +typedef union { + struct { + U32 DATA : 8; // Bits 7:0 + U32 : 24; // Bits 31:8 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} PCU_CR_PACKAGE_TEMPERATURE_PCU_STRUCT; + +typedef union { + struct { + U32 DATA : 8; // Bits 7:0 + U32 : 24; // Bits 31:8 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} PCU_CR_PP0_TEMPERATURE_PCU_STRUCT; + +typedef union { + struct { + U32 DATA : 8; // Bits 7:0 + U32 : 24; // Bits 31:8 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} PCU_CR_PP1_TEMPERATURE_PCU_STRUCT; + +typedef union { + struct { + U32 TIME_VAL : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} PCU_CR_PCU_REFERENCE_CLOCK_PCU_STRUCT; + +typedef union { + struct { + U32 RESERVED : 1; // Bits 0:0 + U32 VALID : 1; // Bits 1:1 + U32 RESERVED_BITS : 4; // Bits 5:2 + U32 OD : 1; // Bits 6:6 + U32 IM : 1; // Bits 7:7 + U32 NEXT_DEVICE_ACTIVITY : 21; // Bits 28:8 + U32 : 3; // Bits 31:29 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} PCU_CR_DEVICE_SHARED_IDLE_DURATION_PCU_STRUCT; + +typedef union { + struct { + U32 USED : 1; // Bits 0:0 + U32 VALID : 1; // Bits 1:1 + U32 RESERVED_BITS : 4; // Bits 5:2 + U32 OD : 1; // Bits 6:6 + U32 IM : 1; // Bits 7:7 + U32 NEXT_DEVICE_ACTIVITY : 21; // Bits 28:8 + U32 : 3; // Bits 31:29 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} PCU_CR_DEVICE_DEDICATED_IDLE_DURATION_PCU_STRUCT; + +typedef union { + struct { + U32 PSTT_LIM : 8; // Bits 7:0 + U32 PSTT_MIN : 8; // Bits 15:8 + U32 : 15; // Bits 30:16 + U32 LOCK : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} PCU_CR_P_STATE_LIMITS_PCU_STRUCT; + +typedef union { + struct { + U32 RPSTT_LIM : 8; // Bits 7:0 + U32 : 24; // Bits 31:8 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} PCU_CR_RP_STATE_LIMITS_PCU_STRUCT; + +typedef union { + struct { + U32 RP0_CAP : 8; // Bits 7:0 + U32 RP1_CAP : 8; // Bits 15:8 + U32 RPN_CAP : 8; // Bits 23:16 + U32 : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} PCU_CR_RP_STATE_CAP_PCU_STRUCT; + +typedef union { + struct { + U32 : 8; // Bits 7:0 + U32 FAN_TEMP_TARGET_OFST : 8; // Bits 15:8 + U32 REF_TEMP : 8; // Bits 23:16 + U32 TJ_MAX_TCC_OFFSET : 4; // Bits 27:24 + U32 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} PCU_CR_TEMPERATURE_TARGET_PCU_STRUCT; + +typedef union { + struct { + U32 PKG_PWR_LIM_1 : 15; // Bits 14:0 + U32 PKG_PWR_LIM_1_EN : 1; // Bits 15:15 + U32 PKG_CLMP_LIM_1 : 1; // Bits 16:16 + U32 PKG_PWR_LIM_1_TIME : 7; // Bits 23:17 + U32 : 8; // Bits 31:24 + U32 PKG_PWR_LIM_2 : 15; // Bits 46:32 + U32 PKG_PWR_LIM_2_EN : 1; // Bits 47:47 + U32 PKG_CLMP_LIM_2 : 1; // Bits 48:48 + U32 PKG_PWR_LIM_2_TIME : 7; // Bits 55:49 + U32 : 7; // Bits 62:56 + U32 PKG_PWR_LIM_LOCK : 1; // Bits 63:63 + } Bits; + U64 Data; + U32 Data32[2]; + U16 Data16[4]; + U8 Data8[8]; +} PCU_CR_PACKAGE_RAPL_LIMIT_PCU_STRUCT; + +typedef union { + struct { + U32 IA_PP_PWR_LIM : 15; // Bits 14:0 + U32 PWR_LIM_CTRL_EN : 1; // Bits 15:15 + U32 PP_CLAMP_LIM : 1; // Bits 16:16 + U32 CTRL_TIME_WIN : 7; // Bits 23:17 + U32 : 7; // Bits 30:24 + U32 PP_PWR_LIM_LOCK : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} PCU_CR_PRIP_TURBO_PWR_LIM_PCU_STRUCT; + +typedef union { + struct { + U32 NON_IA_PP_PWR_LIM : 15; // Bits 14:0 + U32 PWR_LIM_CTRL_EN : 1; // Bits 15:15 + U32 PP_CLAMP_LIM : 1; // Bits 16:16 + U32 CTRL_TIME_WIN : 7; // Bits 23:17 + U32 : 7; // Bits 30:24 + U32 SP_PWR_LIM_LOCK : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} PCU_CR_SECP_TURBO_PWR_LIM_PCU_STRUCT; + +typedef union { + struct { + U32 CURRENT_LIMIT : 13; // Bits 12:0 + U32 : 18; // Bits 30:13 + U32 LOCK : 1; // Bits 31:31 + U32 PSI1_THRESHOLD : 10; // Bits 41:32 + U32 PSI2_THRESHOLD : 10; // Bits 51:42 + U32 PSI3_THRESHOLD : 10; // Bits 61:52 + U32 RESERVED : 2; // Bits 63:62 + } Bits; + U64 Data; + U32 Data32[2]; + U16 Data16[4]; + U8 Data8[8]; +} PCU_CR_VR_CURRENT_CONFIG_PCU_STRUCT; + +typedef union { + struct { + U32 MRC_Saving_Rd : 8; // Bits 7:0 + U32 MRC_Saving_Wt : 8; // Bits 15:8 + U32 MRC_Saving_Cmd : 8; // Bits 23:16 + U32 RESERVED : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} PCU_CR_MRC_ODT_POWER_SAVING_PCU_STRUCT; + +typedef union { + struct { + U32 THERMAL_MONITOR_STATUS : 1; // Bits 0:0 + U32 THERMAL_MONITOR_LOG : 1; // Bits 1:1 + U32 PROCHOT_STATUS : 1; // Bits 2:2 + U32 PROCHOT_LOG : 1; // Bits 3:3 + U32 OUT_OF_SPEC_STATUS : 1; // Bits 4:4 + U32 OUT_OF_SPEC_LOG : 1; // Bits 5:5 + U32 THRESHOLD1_STATUS : 1; // Bits 6:6 + U32 THRESHOLD1_LOG : 1; // Bits 7:7 + U32 THRESHOLD2_STATUS : 1; // Bits 8:8 + U32 THRESHOLD2_LOG : 1; // Bits 9:9 + U32 POWER_LIMITATION_STATUS : 1; // Bits 10:10 + U32 POWER_LIMITATION_LOG : 1; // Bits 11:11 + U32 : 4; // Bits 15:12 + U32 TEMPERATURE : 7; // Bits 22:16 + U32 : 4; // Bits 26:23 + U32 RESOLUTION : 4; // Bits 30:27 + U32 VALID : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} PCU_CR_THERM_STATUS_GT_PCU_STRUCT; + +typedef union { + struct { + U32 HIGH_TEMP_INT_ENABLE : 1; // Bits 0:0 + U32 LOW_TEMP_INT_ENABLE : 1; // Bits 1:1 + U32 PROCHOT_INT_ENABLE : 1; // Bits 2:2 + U32 : 1; // Bits 3:3 + U32 OUT_OF_SPEC_INT_ENABLE : 1; // Bits 4:4 + U32 : 3; // Bits 7:5 + U32 THRESHOLD_1_REL_TEMP : 7; // Bits 14:8 + U32 THRESHOLD_1_INT_ENABLE : 1; // Bits 15:15 + U32 THRESHOLD_2_REL_TEMP : 7; // Bits 22:16 + U32 THRESHOLD_2_INT_ENABLE : 1; // Bits 23:23 + U32 POWER_INT_ENABLE : 1; // Bits 24:24 + U32 : 7; // Bits 31:25 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} PCU_CR_THERM_INTERRUPT_GT_PCU_STRUCT; + +typedef union { + struct { + U32 RESERVED : 1; // Bits 0:0 + U32 VALID : 1; // Bits 1:1 + U32 RESERVED_BITS : 4; // Bits 5:2 + U32 OD : 1; // Bits 6:6 + U32 IM : 1; // Bits 7:7 + U32 NEXT_DEVICE_ACTIVITY : 21; // Bits 28:8 + U32 DISABLE_MDID_EVALUATION : 1; // Bits 29:29 + U32 FORCE_MDID_OVERRIDE : 1; // Bits 30:30 + U32 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} PCU_CR_DEVICE_IDLE_DURATION_OVERRIDE_PCU_STRUCT; + +typedef union { + struct { + U32 VALUE : 10; // Bits 9:0 + U32 MULTIPLIER : 3; // Bits 12:10 + U32 : 2; // Bits 14:13 + U32 VALID : 1; // Bits 15:15 + U32 : 16; // Bits 31:16 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} PCU_CR_GRAPHICS_INTERRUPT_RESPONSE_TIME_PCU_STRUCT; + +typedef union { + struct { + U32 : 4; // Bits 3:0 + U32 PECI_CMD : 8; // Bits 11:4 + U32 : 20; // Bits 31:12 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} PCU_CR_CHAP_CONFIG_PCU_STRUCT; + +typedef union { + struct { + U32 FREQ_TH1 : 6; // Bits 5:0 + U32 : 2; // Bits 7:6 + U32 FREQ_TH2 : 6; // Bits 13:8 + U32 : 2; // Bits 15:14 + U32 FREQ_TH3 : 6; // Bits 21:16 + U32 : 10; // Bits 31:22 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} PCU_CR_CHAP_THRESHOLD2_PCU_STRUCT; + +typedef union { + struct { + U32 DEBUG_ENERGY_PP0_VALUE : 10; // Bits 9:0 + U32 DEBUG_ENERGY_PP1_VALUE : 10; // Bits 19:10 + U32 DEBUG_ENERGY_SA_VALUE : 10; // Bits 29:20 + U32 : 2; // Bits 31:30 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} PCU_CR_ENERGY_DEBUG_PCU_STRUCT; + +typedef union { + struct { + U64 SKPD : 64; // Bits 63:0 + } Bits; + U64 Data; + U32 Data32[2]; + U16 Data16[4]; + U8 Data8[8]; +} PCU_CR_SSKPD_PCU_STRUCT; + +typedef union { + struct { + U32 PPDN_INIT : 12; // Bits 11:0 + U32 : 20; // Bits 31:12 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} PCU_CR_C2C3TT_PCU_STRUCT; + +typedef union { + struct { + U32 DDR_TIMER_VALUE : 13; // Bits 12:0 + U32 : 19; // Bits 31:13 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} PCU_CR_C2_DDR_TT_PCU_STRUCT; + +typedef union { + struct { + U32 NSTL : 10; // Bits 9:0 + U32 MULTIPLIER : 3; // Bits 12:10 + U32 : 1; // Bits 13:13 + U32 FORCE_NL : 1; // Bits 14:14 + U32 NL_V : 1; // Bits 15:15 + U32 SXL : 10; // Bits 25:16 + U32 SXLM : 3; // Bits 28:26 + U32 : 1; // Bits 29:29 + U32 FORCE_SXL : 1; // Bits 30:30 + U32 SXL_V : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} PCU_CR_PCIE_ILTR_OVRD_PCU_STRUCT; + +typedef union { + struct { + U32 NL_VALUE : 10; // Bits 9:0 + U32 NL_SCALE : 3; // Bits 12:10 + U32 NL_RESERVED : 2; // Bits 14:13 + U32 NL_VALID : 1; // Bits 15:15 + U32 SXL_VALUE : 10; // Bits 25:16 + U32 SXL_SCALE : 3; // Bits 28:26 + U32 SXL_RESERVED : 2; // Bits 30:29 + U32 SXL_VALID : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} PCU_CR_PCIE_ILTR_VAL_PCU_0_STRUCT; + +typedef union { + struct { + U32 NL_VALUE : 10; // Bits 9:0 + U32 NL_SCALE : 3; // Bits 12:10 + U32 NL_RESERVED : 2; // Bits 14:13 + U32 NL_VALID : 1; // Bits 15:15 + U32 SXL_VALUE : 10; // Bits 25:16 + U32 SXL_SCALE : 3; // Bits 28:26 + U32 SXL_RESERVED : 2; // Bits 30:29 + U32 SXL_VALID : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} PCU_CR_PCIE_ILTR_VAL_PCU_1_STRUCT; + +typedef union { + struct { + U32 NL_VALUE : 10; // Bits 9:0 + U32 NL_SCALE : 3; // Bits 12:10 + U32 NL_RESERVED : 2; // Bits 14:13 + U32 NL_VALID : 1; // Bits 15:15 + U32 SXL_VALUE : 10; // Bits 25:16 + U32 SXL_SCALE : 3; // Bits 28:26 + U32 SXL_RESERVED : 2; // Bits 30:29 + U32 SXL_VALID : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} PCU_CR_PCIE_ILTR_VAL_PCU_2_STRUCT; + +typedef union { + struct { + U32 DATA : 18; // Bits 17:0 + U32 : 13; // Bits 30:18 + U32 VORANGE : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} PCU_CR_VISA_CTL_PTPCFSMS_PCU_STRUCT; + +typedef union { + struct { + U32 DATA : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} PCU_CR_VISA_XBAR_PTPCFSMS_PCU_STRUCT; + +typedef union { + struct { + U32 DATA : 18; // Bits 17:0 + U32 : 13; // Bits 30:18 + U32 VORANGE : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} PCU_CR_VISA_CTL_PTPCIOREGS_PCU_STRUCT; + +typedef union { + struct { + U32 DATA : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} PCU_CR_BIOS_MAILBOX_DATA_PCU_STRUCT; + +typedef union { + struct { + U32 COMMAND : 8; // Bits 7:0 + U32 ADDR : 21; // Bits 28:8 + U32 : 2; // Bits 30:29 + U32 RUN_BUSY : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} PCU_CR_BIOS_MAILBOX_INTERFACE_PCU_STRUCT; + +typedef union { + struct { + U32 RST_CPL : 1; // Bits 0:0 + U32 PCIE_ENUMERATION_DONE : 1; // Bits 1:1 + U32 C7_ALLOWED : 1; // Bits 2:2 + U32 : 29; // Bits 31:3 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} PCU_CR_BIOS_RESET_CPL_PCU_STRUCT; + +typedef union { + struct { + U32 REQ_DATA : 4; // Bits 3:0 + U32 REQ_TYPE : 4; // Bits 7:4 + U32 : 23; // Bits 30:8 + U32 RUN_BUSY : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} PCU_CR_MC_BIOS_REQ_PCU_STRUCT; + +typedef union { + struct { + U32 MC_FREQ : 4; // Bits 3:0 + U32 : 28; // Bits 31:4 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} PCU_CR_MC_BIOS_DATA_PCU_STRUCT; + +typedef union { + struct { + U32 SACG_ENA : 1; // Bits 0:0 + U32 MPLL_OFF_ENA : 1; // Bits 1:1 + U32 PPLL_OFF_ENA : 1; // Bits 2:2 + U32 : 5; // Bits 7:3 + U32 SACG_SEN : 1; // Bits 8:8 + U32 MPLL_OFF_SEN : 1; // Bits 9:9 + U32 MDLL_OFF_SEN : 1; // Bits 10:10 + U32 SACG_SREXIT : 1; // Bits 11:11 + U32 NSWAKE_SREXIT : 1; // Bits 12:12 + U32 SACG_MPLL : 1; // Bits 13:13 + U32 MPLL_ON_DE : 1; // Bits 14:14 + U32 MDLL_ON_DE : 1; // Bits 15:15 + U32 : 16; // Bits 31:16 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} PCU_CR_SAPMCTL_PCU_STRUCT; + +typedef union { + struct { + U32 COMP_DISABLE : 1; // Bits 0:0 + U32 COMP_INTERVAL : 4; // Bits 4:1 + U32 : 3; // Bits 7:5 + U32 COMP_FORCE : 1; // Bits 8:8 + U32 : 23; // Bits 31:9 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} PCU_CR_P_COMP_PCU_STRUCT; + +typedef union { + struct { + U32 COMP_DISABLE : 1; // Bits 0:0 + U32 COMP_INTERVAL : 4; // Bits 4:1 + U32 : 3; // Bits 7:5 + U32 COMP_FORCE : 1; // Bits 8:8 + U32 : 23; // Bits 31:9 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} PCU_CR_M_COMP_PCU_STRUCT; + +typedef union { + struct { + U32 COMP_DISABLE : 1; // Bits 0:0 + U32 COMP_INTERVAL : 4; // Bits 4:1 + U32 : 3; // Bits 7:5 + U32 COMP_FORCE : 1; // Bits 8:8 + U32 : 23; // Bits 31:9 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} PCU_CR_D_COMP_PCU_STRUCT; + +typedef union { + struct { + U32 TDP_RATIO : 8; // Bits 7:0 + U32 : 24; // Bits 31:8 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} PCU_CR_CONFIG_TDP_NOMINAL_PCU_STRUCT; + +typedef union { + struct { + U32 PKG_TDP : 15; // Bits 14:0 + U32 : 1; // Bits 15:15 + U32 TDP_RATIO : 8; // Bits 23:16 + U32 : 8; // Bits 31:24 + U32 PKG_MAX_PWR : 15; // Bits 46:32 + U32 PKG_MIN_PWR : 16; // Bits 62:47 + U32 : 1; // Bits 63:63 + } Bits; + U64 Data; + U32 Data32[2]; + U16 Data16[4]; + U8 Data8[8]; +} PCU_CR_CONFIG_TDP_LEVEL1_PCU_STRUCT; + +typedef union { + struct { + U32 PKG_TDP : 15; // Bits 14:0 + U32 : 1; // Bits 15:15 + U32 TDP_RATIO : 8; // Bits 23:16 + U32 : 8; // Bits 31:24 + U32 PKG_MAX_PWR : 15; // Bits 46:32 + U32 PKG_MIN_PWR : 16; // Bits 62:47 + U32 : 1; // Bits 63:63 + } Bits; + U64 Data; + U32 Data32[2]; + U16 Data16[4]; + U8 Data8[8]; +} PCU_CR_CONFIG_TDP_LEVEL2_PCU_STRUCT; + +typedef union { + struct { + U32 TDP_LEVEL : 2; // Bits 1:0 + U32 : 29; // Bits 30:2 + U32 CONFIG_TDP_LOCK : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} PCU_CR_CONFIG_TDP_CONTROL_PCU_STRUCT; + +typedef union { + struct { + U32 MAX_NON_TURBO_RATIO : 8; // Bits 7:0 + U32 : 23; // Bits 30:8 + U32 TURBO_ACTIVATION_RATIO_LOCK : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} PCU_CR_TURBO_ACTIVATION_RATIO_PCU_STRUCT; + +typedef union { + struct { + U32 DATA : 18; // Bits 17:0 + U32 : 13; // Bits 30:18 + U32 VORANGE : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} DRNG_CR_VISA_CTL_DRNGCTLS_DRNG_STRUCT; + +#define NCDECS_CR_GFXVTBAR_NCU_REG (0x00005400) + #define NCDECS_CR_GFXVTBAR_NCU_GFXVTBAREN_OFF ( 0) + #define NCDECS_CR_GFXVTBAR_NCU_GFXVTBAREN_WID ( 1) + #define NCDECS_CR_GFXVTBAR_NCU_GFXVTBAREN_MSK (0x00000001) + #define NCDECS_CR_GFXVTBAR_NCU_GFXVTBAREN_MAX (0x00000001) + #define NCDECS_CR_GFXVTBAR_NCU_GFXVTBAREN_DEF (0x00000000) + #define NCDECS_CR_GFXVTBAR_NCU_GFXVTBAR_OFF (12) + #define NCDECS_CR_GFXVTBAR_NCU_GFXVTBAR_WID (27) + #define NCDECS_CR_GFXVTBAR_NCU_GFXVTBAR_MSK (0x7FFFFFF000) + #define NCDECS_CR_GFXVTBAR_NCU_GFXVTBAR_MAX (0x07FFFFFF) + #define NCDECS_CR_GFXVTBAR_NCU_GFXVTBAR_DEF (0x00000000) + +#define NCDECS_CR_EDRAMBAR_NCU_REG (0x00005408) + #define NCDECS_CR_EDRAMBAR_NCU_EDRAMBAREN_OFF ( 0) + #define NCDECS_CR_EDRAMBAR_NCU_EDRAMBAREN_WID ( 1) + #define NCDECS_CR_EDRAMBAR_NCU_EDRAMBAREN_MSK (0x00000001) + #define NCDECS_CR_EDRAMBAR_NCU_EDRAMBAREN_MAX (0x00000001) + #define NCDECS_CR_EDRAMBAR_NCU_EDRAMBAREN_DEF (0x00000000) + #define NCDECS_CR_EDRAMBAR_NCU_EDRAMBAR_OFF (14) + #define NCDECS_CR_EDRAMBAR_NCU_EDRAMBAR_WID (25) + #define NCDECS_CR_EDRAMBAR_NCU_EDRAMBAR_MSK (0x7FFFFFC000) + #define NCDECS_CR_EDRAMBAR_NCU_EDRAMBAR_MAX (0x01FFFFFF) + #define NCDECS_CR_EDRAMBAR_NCU_EDRAMBAR_DEF (0x00000000) + +#define NCDECS_CR_VTDPVC0BAR_NCU_REG (0x00005410) + #define NCDECS_CR_VTDPVC0BAR_NCU_VTVC0BAREN_OFF ( 0) + #define NCDECS_CR_VTDPVC0BAR_NCU_VTVC0BAREN_WID ( 1) + #define NCDECS_CR_VTDPVC0BAR_NCU_VTVC0BAREN_MSK (0x00000001) + #define NCDECS_CR_VTDPVC0BAR_NCU_VTVC0BAREN_MAX (0x00000001) + #define NCDECS_CR_VTDPVC0BAR_NCU_VTVC0BAREN_DEF (0x00000000) + #define NCDECS_CR_VTDPVC0BAR_NCU_VTVC0BAR_OFF (12) + #define NCDECS_CR_VTDPVC0BAR_NCU_VTVC0BAR_WID (27) + #define NCDECS_CR_VTDPVC0BAR_NCU_VTVC0BAR_MSK (0x7FFFFFF000) + #define NCDECS_CR_VTDPVC0BAR_NCU_VTVC0BAR_MAX (0x07FFFFFF) + #define NCDECS_CR_VTDPVC0BAR_NCU_VTVC0BAR_DEF (0x00000000) + +#define NCDECS_CR_INTRDIRCTL_NCU_REG (0x00005418) + #define NCDECS_CR_INTRDIRCTL_NCU_RdrModSel_OFF ( 0) + #define NCDECS_CR_INTRDIRCTL_NCU_RdrModSel_WID ( 3) + #define NCDECS_CR_INTRDIRCTL_NCU_RdrModSel_MSK (0x00000007) + #define NCDECS_CR_INTRDIRCTL_NCU_RdrModSel_MAX (0x00000007) + #define NCDECS_CR_INTRDIRCTL_NCU_RdrModSel_DEF (0x00000000) + #define NCDECS_CR_INTRDIRCTL_NCU_ClastChkSmpMod_OFF ( 3) + #define NCDECS_CR_INTRDIRCTL_NCU_ClastChkSmpMod_WID ( 1) + #define NCDECS_CR_INTRDIRCTL_NCU_ClastChkSmpMod_MSK (0x00000008) + #define NCDECS_CR_INTRDIRCTL_NCU_ClastChkSmpMod_MAX (0x00000001) + #define NCDECS_CR_INTRDIRCTL_NCU_ClastChkSmpMod_DEF (0x00000000) + #define NCDECS_CR_INTRDIRCTL_NCU_LogFltClustMod_OFF ( 4) + #define NCDECS_CR_INTRDIRCTL_NCU_LogFltClustMod_WID ( 1) + #define NCDECS_CR_INTRDIRCTL_NCU_LogFltClustMod_MSK (0x00000010) + #define NCDECS_CR_INTRDIRCTL_NCU_LogFltClustMod_MAX (0x00000001) + #define NCDECS_CR_INTRDIRCTL_NCU_LogFltClustMod_DEF (0x00000000) + #define NCDECS_CR_INTRDIRCTL_NCU_LogFlatClustOvrEn_OFF ( 5) + #define NCDECS_CR_INTRDIRCTL_NCU_LogFlatClustOvrEn_WID ( 1) + #define NCDECS_CR_INTRDIRCTL_NCU_LogFlatClustOvrEn_MSK (0x00000020) + #define NCDECS_CR_INTRDIRCTL_NCU_LogFlatClustOvrEn_MAX (0x00000001) + #define NCDECS_CR_INTRDIRCTL_NCU_LogFlatClustOvrEn_DEF (0x00000000) + #define NCDECS_CR_INTRDIRCTL_NCU_HashModCtr_OFF ( 6) + #define NCDECS_CR_INTRDIRCTL_NCU_HashModCtr_WID ( 3) + #define NCDECS_CR_INTRDIRCTL_NCU_HashModCtr_MSK (0x000001C0) + #define NCDECS_CR_INTRDIRCTL_NCU_HashModCtr_MAX (0x00000007) + #define NCDECS_CR_INTRDIRCTL_NCU_HashModCtr_DEF (0x00000000) + +#define NCDECS_CR_NCUCTL0_NCU_REG (0x0000541C) + #define NCDECS_CR_NCUCTL0_NCU_PLIM_OFF (28) + #define NCDECS_CR_NCUCTL0_NCU_PLIM_WID ( 3) + #define NCDECS_CR_NCUCTL0_NCU_PLIM_MSK (0x70000000) + #define NCDECS_CR_NCUCTL0_NCU_PLIM_MAX (0x00000007) + #define NCDECS_CR_NCUCTL0_NCU_PLIM_DEF (0x00000003) + +#define NCDECS_CR_GDXCBAR_NCU_REG (0x00005420) + #define NCDECS_CR_GDXCBAR_NCU_GDXCBAREN_OFF ( 0) + #define NCDECS_CR_GDXCBAR_NCU_GDXCBAREN_WID ( 1) + #define NCDECS_CR_GDXCBAR_NCU_GDXCBAREN_MSK (0x00000001) + #define NCDECS_CR_GDXCBAR_NCU_GDXCBAREN_MAX (0x00000001) + #define NCDECS_CR_GDXCBAR_NCU_GDXCBAREN_DEF (0x00000000) + #define NCDECS_CR_GDXCBAR_NCU_GDXCBAR_OFF (12) + #define NCDECS_CR_GDXCBAR_NCU_GDXCBAR_WID (27) + #define NCDECS_CR_GDXCBAR_NCU_GDXCBAR_MSK (0x7FFFFFF000) + #define NCDECS_CR_GDXCBAR_NCU_GDXCBAR_MAX (0x07FFFFFF) + #define NCDECS_CR_GDXCBAR_NCU_GDXCBAR_DEF (0x00000000) + +#define NCDECS_CR_SCRATCHPAD_NCU_0_REG (0x00005428) + #define NCDECS_CR_SCRATCHPAD_NCU_0_Data_OFF ( 0) + #define NCDECS_CR_SCRATCHPAD_NCU_0_Data_WID (32) + #define NCDECS_CR_SCRATCHPAD_NCU_0_Data_MSK (0xFFFFFFFF) + #define NCDECS_CR_SCRATCHPAD_NCU_0_Data_MAX (0xFFFFFFFF) + #define NCDECS_CR_SCRATCHPAD_NCU_0_Data_DEF (0x00000000) + +#define NCDECS_CR_SCRATCHPAD_NCU_1_REG (0x0000542C) + #define NCDECS_CR_SCRATCHPAD_NCU_1_Data_OFF ( 0) + #define NCDECS_CR_SCRATCHPAD_NCU_1_Data_WID (32) + #define NCDECS_CR_SCRATCHPAD_NCU_1_Data_MSK (0xFFFFFFFF) + #define NCDECS_CR_SCRATCHPAD_NCU_1_Data_MAX (0xFFFFFFFF) + #define NCDECS_CR_SCRATCHPAD_NCU_1_Data_DEF (0x00000000) + +#define NCDECS_CR_SCRATCHPAD_NCU_2_REG (0x00005430) + #define NCDECS_CR_SCRATCHPAD_NCU_2_Data_OFF ( 0) + #define NCDECS_CR_SCRATCHPAD_NCU_2_Data_WID (32) + #define NCDECS_CR_SCRATCHPAD_NCU_2_Data_MSK (0xFFFFFFFF) + #define NCDECS_CR_SCRATCHPAD_NCU_2_Data_MAX (0xFFFFFFFF) + #define NCDECS_CR_SCRATCHPAD_NCU_2_Data_DEF (0x00000000) + +#define NCDECS_CR_SCRATCHPAD_NCU_3_REG (0x00005434) + #define NCDECS_CR_SCRATCHPAD_NCU_3_Data_OFF ( 0) + #define NCDECS_CR_SCRATCHPAD_NCU_3_Data_WID (32) + #define NCDECS_CR_SCRATCHPAD_NCU_3_Data_MSK (0xFFFFFFFF) + #define NCDECS_CR_SCRATCHPAD_NCU_3_Data_MAX (0xFFFFFFFF) + #define NCDECS_CR_SCRATCHPAD_NCU_3_Data_DEF (0x00000000) + +#define NCDECS_CR_PAVPMSGOFFST_NCU_REG (0x00005500) + #define NCDECS_CR_PAVPMSGOFFST_NCU_LOCK_OFF ( 0) + #define NCDECS_CR_PAVPMSGOFFST_NCU_LOCK_WID ( 1) + #define NCDECS_CR_PAVPMSGOFFST_NCU_LOCK_MSK (0x00000001) + #define NCDECS_CR_PAVPMSGOFFST_NCU_LOCK_MAX (0x00000001) + #define NCDECS_CR_PAVPMSGOFFST_NCU_LOCK_DEF (0x00000000) + #define NCDECS_CR_PAVPMSGOFFST_NCU_OFFSET_OFF (20) + #define NCDECS_CR_PAVPMSGOFFST_NCU_OFFSET_WID (12) + #define NCDECS_CR_PAVPMSGOFFST_NCU_OFFSET_MSK (0xFFF00000) + #define NCDECS_CR_PAVPMSGOFFST_NCU_OFFSET_MAX (0x00000FFF) + #define NCDECS_CR_PAVPMSGOFFST_NCU_OFFSET_DEF (0x00000000) + +#define MPVTDTRK_CR_VTDLIM_IMPH_REG (0x00006000) + #define MPVTDTRK_CR_VTDLIM_IMPH_VCPVTDLIM_OFF ( 0) + #define MPVTDTRK_CR_VTDLIM_IMPH_VCPVTDLIM_WID ( 3) + #define MPVTDTRK_CR_VTDLIM_IMPH_VCPVTDLIM_MSK (0x00000007) + #define MPVTDTRK_CR_VTDLIM_IMPH_VCPVTDLIM_MAX (0x00000007) + #define MPVTDTRK_CR_VTDLIM_IMPH_VCPVTDLIM_DEF (0x00000004) + +#define MPVTDTRK_CR_HDAUDRID_IMPH_REG (0x00006008) + #define MPVTDTRK_CR_HDAUDRID_IMPH_DEVNUM_OFF ( 3) + #define MPVTDTRK_CR_HDAUDRID_IMPH_DEVNUM_WID ( 5) + #define MPVTDTRK_CR_HDAUDRID_IMPH_DEVNUM_MSK (0x000000F8) + #define MPVTDTRK_CR_HDAUDRID_IMPH_DEVNUM_MAX (0x0000001F) + #define MPVTDTRK_CR_HDAUDRID_IMPH_DEVNUM_DEF (0x0000001B) + #define MPVTDTRK_CR_HDAUDRID_IMPH_BUSNUM_OFF ( 8) + #define MPVTDTRK_CR_HDAUDRID_IMPH_BUSNUM_WID ( 8) + #define MPVTDTRK_CR_HDAUDRID_IMPH_BUSNUM_MSK (0x0000FF00) + #define MPVTDTRK_CR_HDAUDRID_IMPH_BUSNUM_MAX (0x000000FF) + #define MPVTDTRK_CR_HDAUDRID_IMPH_BUSNUM_DEF (0x00000000) + #define MPVTDTRK_CR_HDAUDRID_IMPH_HDAUD_EN_OFF (31) + #define MPVTDTRK_CR_HDAUDRID_IMPH_HDAUD_EN_WID ( 1) + #define MPVTDTRK_CR_HDAUDRID_IMPH_HDAUD_EN_MSK (0x80000000) + #define MPVTDTRK_CR_HDAUDRID_IMPH_HDAUD_EN_MAX (0x00000001) + #define MPVTDTRK_CR_HDAUDRID_IMPH_HDAUD_EN_DEF (0x00000001) + +#define MPVTDTRK_CR_UMAGFXBASE_IMPH_REG (0x00006010) + #define MPVTDTRK_CR_UMAGFXBASE_IMPH_UMAB_OFF (20) + #define MPVTDTRK_CR_UMAGFXBASE_IMPH_UMAB_WID (19) + #define MPVTDTRK_CR_UMAGFXBASE_IMPH_UMAB_MSK (0x7FFFF00000) + #define MPVTDTRK_CR_UMAGFXBASE_IMPH_UMAB_MAX (0x0007FFFF) + #define MPVTDTRK_CR_UMAGFXBASE_IMPH_UMAB_DEF (0x0007FFFF) + +#define MPVTDTRK_CR_UMAGFXLIMIT_IMPH_REG (0x00006018) + #define MPVTDTRK_CR_UMAGFXLIMIT_IMPH_UMAL_OFF (20) + #define MPVTDTRK_CR_UMAGFXLIMIT_IMPH_UMAL_WID (19) + #define MPVTDTRK_CR_UMAGFXLIMIT_IMPH_UMAL_MSK (0x7FFFF00000) + #define MPVTDTRK_CR_UMAGFXLIMIT_IMPH_UMAL_MAX (0x0007FFFF) + #define MPVTDTRK_CR_UMAGFXLIMIT_IMPH_UMAL_DEF (0x00000000) + +#define MPVTDTRK_CR_UMAGFXCTL_IMPH_REG (0x00006020) + #define MPVTDTRK_CR_UMAGFXCTL_IMPH_LCK_OFF ( 0) + #define MPVTDTRK_CR_UMAGFXCTL_IMPH_LCK_WID ( 1) + #define MPVTDTRK_CR_UMAGFXCTL_IMPH_LCK_MSK (0x00000001) + #define MPVTDTRK_CR_UMAGFXCTL_IMPH_LCK_MAX (0x00000001) + #define MPVTDTRK_CR_UMAGFXCTL_IMPH_LCK_DEF (0x00000000) + #define MPVTDTRK_CR_UMAGFXCTL_IMPH_PEG10EN_OFF (10) + #define MPVTDTRK_CR_UMAGFXCTL_IMPH_PEG10EN_WID ( 1) + #define MPVTDTRK_CR_UMAGFXCTL_IMPH_PEG10EN_MSK (0x00000400) + #define MPVTDTRK_CR_UMAGFXCTL_IMPH_PEG10EN_MAX (0x00000001) + #define MPVTDTRK_CR_UMAGFXCTL_IMPH_PEG10EN_DEF (0x00000000) + #define MPVTDTRK_CR_UMAGFXCTL_IMPH_PEG11EN_OFF (11) + #define MPVTDTRK_CR_UMAGFXCTL_IMPH_PEG11EN_WID ( 1) + #define MPVTDTRK_CR_UMAGFXCTL_IMPH_PEG11EN_MSK (0x00000800) + #define MPVTDTRK_CR_UMAGFXCTL_IMPH_PEG11EN_MAX (0x00000001) + #define MPVTDTRK_CR_UMAGFXCTL_IMPH_PEG11EN_DEF (0x00000000) + #define MPVTDTRK_CR_UMAGFXCTL_IMPH_PEG12EN_OFF (12) + #define MPVTDTRK_CR_UMAGFXCTL_IMPH_PEG12EN_WID ( 1) + #define MPVTDTRK_CR_UMAGFXCTL_IMPH_PEG12EN_MSK (0x00001000) + #define MPVTDTRK_CR_UMAGFXCTL_IMPH_PEG12EN_MAX (0x00000001) + #define MPVTDTRK_CR_UMAGFXCTL_IMPH_PEG12EN_DEF (0x00000000) + #define MPVTDTRK_CR_UMAGFXCTL_IMPH_DMIEN_OFF (13) + #define MPVTDTRK_CR_UMAGFXCTL_IMPH_DMIEN_WID ( 1) + #define MPVTDTRK_CR_UMAGFXCTL_IMPH_DMIEN_MSK (0x00002000) + #define MPVTDTRK_CR_UMAGFXCTL_IMPH_DMIEN_MAX (0x00000001) + #define MPVTDTRK_CR_UMAGFXCTL_IMPH_DMIEN_DEF (0x00000000) + +#define MPVTDTRK_CR_VDMBDFBARKVM_IMPH_REG (0x00006030) + #define MPVTDTRK_CR_VDMBDFBARKVM_IMPH_FUNNUM_OFF ( 0) + #define MPVTDTRK_CR_VDMBDFBARKVM_IMPH_FUNNUM_WID ( 3) + #define MPVTDTRK_CR_VDMBDFBARKVM_IMPH_FUNNUM_MSK (0x00000007) + #define MPVTDTRK_CR_VDMBDFBARKVM_IMPH_FUNNUM_MAX (0x00000007) + #define MPVTDTRK_CR_VDMBDFBARKVM_IMPH_FUNNUM_DEF (0x00000000) + #define MPVTDTRK_CR_VDMBDFBARKVM_IMPH_DEVNUM_OFF ( 3) + #define MPVTDTRK_CR_VDMBDFBARKVM_IMPH_DEVNUM_WID ( 5) + #define MPVTDTRK_CR_VDMBDFBARKVM_IMPH_DEVNUM_MSK (0x000000F8) + #define MPVTDTRK_CR_VDMBDFBARKVM_IMPH_DEVNUM_MAX (0x0000001F) + #define MPVTDTRK_CR_VDMBDFBARKVM_IMPH_DEVNUM_DEF (0x00000016) + #define MPVTDTRK_CR_VDMBDFBARKVM_IMPH_BUSNUM_OFF ( 8) + #define MPVTDTRK_CR_VDMBDFBARKVM_IMPH_BUSNUM_WID ( 8) + #define MPVTDTRK_CR_VDMBDFBARKVM_IMPH_BUSNUM_MSK (0x0000FF00) + #define MPVTDTRK_CR_VDMBDFBARKVM_IMPH_BUSNUM_MAX (0x000000FF) + #define MPVTDTRK_CR_VDMBDFBARKVM_IMPH_BUSNUM_DEF (0x00000000) + #define MPVTDTRK_CR_VDMBDFBARKVM_IMPH_BARNUM_OFF (16) + #define MPVTDTRK_CR_VDMBDFBARKVM_IMPH_BARNUM_WID ( 3) + #define MPVTDTRK_CR_VDMBDFBARKVM_IMPH_BARNUM_MSK (0x00070000) + #define MPVTDTRK_CR_VDMBDFBARKVM_IMPH_BARNUM_MAX (0x00000007) + #define MPVTDTRK_CR_VDMBDFBARKVM_IMPH_BARNUM_DEF (0x00000007) + +#define MPVTDTRK_CR_VDMBDFBARPAVP_IMPH_REG (0x00006034) + #define MPVTDTRK_CR_VDMBDFBARPAVP_IMPH_FUNNUM_OFF ( 0) + #define MPVTDTRK_CR_VDMBDFBARPAVP_IMPH_FUNNUM_WID ( 3) + #define MPVTDTRK_CR_VDMBDFBARPAVP_IMPH_FUNNUM_MSK (0x00000007) + #define MPVTDTRK_CR_VDMBDFBARPAVP_IMPH_FUNNUM_MAX (0x00000007) + #define MPVTDTRK_CR_VDMBDFBARPAVP_IMPH_FUNNUM_DEF (0x00000000) + #define MPVTDTRK_CR_VDMBDFBARPAVP_IMPH_DEVNUM_OFF ( 3) + #define MPVTDTRK_CR_VDMBDFBARPAVP_IMPH_DEVNUM_WID ( 5) + #define MPVTDTRK_CR_VDMBDFBARPAVP_IMPH_DEVNUM_MSK (0x000000F8) + #define MPVTDTRK_CR_VDMBDFBARPAVP_IMPH_DEVNUM_MAX (0x0000001F) + #define MPVTDTRK_CR_VDMBDFBARPAVP_IMPH_DEVNUM_DEF (0x00000016) + #define MPVTDTRK_CR_VDMBDFBARPAVP_IMPH_BUSNUM_OFF ( 8) + #define MPVTDTRK_CR_VDMBDFBARPAVP_IMPH_BUSNUM_WID ( 8) + #define MPVTDTRK_CR_VDMBDFBARPAVP_IMPH_BUSNUM_MSK (0x0000FF00) + #define MPVTDTRK_CR_VDMBDFBARPAVP_IMPH_BUSNUM_MAX (0x000000FF) + #define MPVTDTRK_CR_VDMBDFBARPAVP_IMPH_BUSNUM_DEF (0x00000000) + #define MPVTDTRK_CR_VDMBDFBARPAVP_IMPH_BARNUM_OFF (16) + #define MPVTDTRK_CR_VDMBDFBARPAVP_IMPH_BARNUM_WID ( 3) + #define MPVTDTRK_CR_VDMBDFBARPAVP_IMPH_BARNUM_MSK (0x00070000) + #define MPVTDTRK_CR_VDMBDFBARPAVP_IMPH_BARNUM_MAX (0x00000007) + #define MPVTDTRK_CR_VDMBDFBARPAVP_IMPH_BARNUM_DEF (0x00000007) + +#define MPVTDTRK_CR_VISA_CTL_MPVTDTLBS_IMPH_REG (0x00006040) + #define MPVTDTRK_CR_VISA_CTL_MPVTDTLBS_IMPH_DATA_OFF ( 0) + #define MPVTDTRK_CR_VISA_CTL_MPVTDTLBS_IMPH_DATA_WID (18) + #define MPVTDTRK_CR_VISA_CTL_MPVTDTLBS_IMPH_DATA_MSK (0x0003FFFF) + #define MPVTDTRK_CR_VISA_CTL_MPVTDTLBS_IMPH_DATA_MAX (0x0003FFFF) + #define MPVTDTRK_CR_VISA_CTL_MPVTDTLBS_IMPH_DATA_DEF (0x00000000) + #define MPVTDTRK_CR_VISA_CTL_MPVTDTLBS_IMPH_VORANGE_OFF (31) + #define MPVTDTRK_CR_VISA_CTL_MPVTDTLBS_IMPH_VORANGE_WID ( 1) + #define MPVTDTRK_CR_VISA_CTL_MPVTDTLBS_IMPH_VORANGE_MSK (0x80000000) + #define MPVTDTRK_CR_VISA_CTL_MPVTDTLBS_IMPH_VORANGE_MAX (0x00000001) + #define MPVTDTRK_CR_VISA_CTL_MPVTDTLBS_IMPH_VORANGE_DEF (0x00000000) + +#define MPVTDTRK_CR_VISA_XBAR_MPVTDTLBS_IMPH_REG (0x00006044) + #define MPVTDTRK_CR_VISA_XBAR_MPVTDTLBS_IMPH_DATA_OFF ( 0) + #define MPVTDTRK_CR_VISA_XBAR_MPVTDTLBS_IMPH_DATA_WID (32) + #define MPVTDTRK_CR_VISA_XBAR_MPVTDTLBS_IMPH_DATA_MSK (0xFFFFFFFF) + #define MPVTDTRK_CR_VISA_XBAR_MPVTDTLBS_IMPH_DATA_MAX (0xFFFFFFFF) + #define MPVTDTRK_CR_VISA_XBAR_MPVTDTLBS_IMPH_DATA_DEF (0x76543210) + +#define MPVTDTRK_CR_VISA_CTL_MPVTMISCS_IMPH_REG (0x00006048) + #define MPVTDTRK_CR_VISA_CTL_MPVTMISCS_IMPH_DATA_OFF ( 0) + #define MPVTDTRK_CR_VISA_CTL_MPVTMISCS_IMPH_DATA_WID (18) + #define MPVTDTRK_CR_VISA_CTL_MPVTMISCS_IMPH_DATA_MSK (0x0003FFFF) + #define MPVTDTRK_CR_VISA_CTL_MPVTMISCS_IMPH_DATA_MAX (0x0003FFFF) + #define MPVTDTRK_CR_VISA_CTL_MPVTMISCS_IMPH_DATA_DEF (0x00000000) + #define MPVTDTRK_CR_VISA_CTL_MPVTMISCS_IMPH_VORANGE_OFF (31) + #define MPVTDTRK_CR_VISA_CTL_MPVTMISCS_IMPH_VORANGE_WID ( 1) + #define MPVTDTRK_CR_VISA_CTL_MPVTMISCS_IMPH_VORANGE_MSK (0x80000000) + #define MPVTDTRK_CR_VISA_CTL_MPVTMISCS_IMPH_VORANGE_MAX (0x00000001) + #define MPVTDTRK_CR_VISA_CTL_MPVTMISCS_IMPH_VORANGE_DEF (0x00000000) + +#define MPVTDTRK_CR_VISA_CTL_MPVTTRKS_IMPH_REG (0x0000604C) + #define MPVTDTRK_CR_VISA_CTL_MPVTTRKS_IMPH_DATA_OFF ( 0) + #define MPVTDTRK_CR_VISA_CTL_MPVTTRKS_IMPH_DATA_WID (18) + #define MPVTDTRK_CR_VISA_CTL_MPVTTRKS_IMPH_DATA_MSK (0x0003FFFF) + #define MPVTDTRK_CR_VISA_CTL_MPVTTRKS_IMPH_DATA_MAX (0x0003FFFF) + #define MPVTDTRK_CR_VISA_CTL_MPVTTRKS_IMPH_DATA_DEF (0x00000000) + #define MPVTDTRK_CR_VISA_CTL_MPVTTRKS_IMPH_VORANGE_OFF (31) + #define MPVTDTRK_CR_VISA_CTL_MPVTTRKS_IMPH_VORANGE_WID ( 1) + #define MPVTDTRK_CR_VISA_CTL_MPVTTRKS_IMPH_VORANGE_MSK (0x80000000) + #define MPVTDTRK_CR_VISA_CTL_MPVTTRKS_IMPH_VORANGE_MAX (0x00000001) + #define MPVTDTRK_CR_VISA_CTL_MPVTTRKS_IMPH_VORANGE_DEF (0x00000000) + +#define MPVTDTRK_CR_PRIMUP_MASK1_IMPH_REG (0x00006050) + #define MPVTDTRK_CR_PRIMUP_MASK1_IMPH_VC_OFF ( 0) + #define MPVTDTRK_CR_PRIMUP_MASK1_IMPH_VC_WID ( 4) + #define MPVTDTRK_CR_PRIMUP_MASK1_IMPH_VC_MSK (0x0000000F) + #define MPVTDTRK_CR_PRIMUP_MASK1_IMPH_VC_MAX (0x0000000F) + #define MPVTDTRK_CR_PRIMUP_MASK1_IMPH_VC_DEF (0x00000000) + #define MPVTDTRK_CR_PRIMUP_MASK1_IMPH_FMT_CMDTYPE_OFF ( 4) + #define MPVTDTRK_CR_PRIMUP_MASK1_IMPH_FMT_CMDTYPE_WID ( 6) + #define MPVTDTRK_CR_PRIMUP_MASK1_IMPH_FMT_CMDTYPE_MSK (0x000003F0) + #define MPVTDTRK_CR_PRIMUP_MASK1_IMPH_FMT_CMDTYPE_MAX (0x0000003F) + #define MPVTDTRK_CR_PRIMUP_MASK1_IMPH_FMT_CMDTYPE_DEF (0x00000000) + #define MPVTDTRK_CR_PRIMUP_MASK1_IMPH_TC_OFF (10) + #define MPVTDTRK_CR_PRIMUP_MASK1_IMPH_TC_WID ( 4) + #define MPVTDTRK_CR_PRIMUP_MASK1_IMPH_TC_MSK (0x00003C00) + #define MPVTDTRK_CR_PRIMUP_MASK1_IMPH_TC_MAX (0x0000000F) + #define MPVTDTRK_CR_PRIMUP_MASK1_IMPH_TC_DEF (0x00000000) + #define MPVTDTRK_CR_PRIMUP_MASK1_IMPH_CHAIN_OFF (14) + #define MPVTDTRK_CR_PRIMUP_MASK1_IMPH_CHAIN_WID ( 1) + #define MPVTDTRK_CR_PRIMUP_MASK1_IMPH_CHAIN_MSK (0x00004000) + #define MPVTDTRK_CR_PRIMUP_MASK1_IMPH_CHAIN_MAX (0x00000001) + #define MPVTDTRK_CR_PRIMUP_MASK1_IMPH_CHAIN_DEF (0x00000000) + #define MPVTDTRK_CR_PRIMUP_MASK1_IMPH_NS_OFF (15) + #define MPVTDTRK_CR_PRIMUP_MASK1_IMPH_NS_WID ( 1) + #define MPVTDTRK_CR_PRIMUP_MASK1_IMPH_NS_MSK (0x00008000) + #define MPVTDTRK_CR_PRIMUP_MASK1_IMPH_NS_MAX (0x00000001) + #define MPVTDTRK_CR_PRIMUP_MASK1_IMPH_NS_DEF (0x00000000) + #define MPVTDTRK_CR_PRIMUP_MASK1_IMPH_RO_OFF (16) + #define MPVTDTRK_CR_PRIMUP_MASK1_IMPH_RO_WID ( 1) + #define MPVTDTRK_CR_PRIMUP_MASK1_IMPH_RO_MSK (0x00010000) + #define MPVTDTRK_CR_PRIMUP_MASK1_IMPH_RO_MAX (0x00000001) + #define MPVTDTRK_CR_PRIMUP_MASK1_IMPH_RO_DEF (0x00000000) + #define MPVTDTRK_CR_PRIMUP_MASK1_IMPH_LENGTH_OFF (17) + #define MPVTDTRK_CR_PRIMUP_MASK1_IMPH_LENGTH_WID ( 5) + #define MPVTDTRK_CR_PRIMUP_MASK1_IMPH_LENGTH_MSK (0x003E0000) + #define MPVTDTRK_CR_PRIMUP_MASK1_IMPH_LENGTH_MAX (0x0000001F) + #define MPVTDTRK_CR_PRIMUP_MASK1_IMPH_LENGTH_DEF (0x00000000) + #define MPVTDTRK_CR_PRIMUP_MASK1_IMPH_EP_OFF (22) + #define MPVTDTRK_CR_PRIMUP_MASK1_IMPH_EP_WID ( 1) + #define MPVTDTRK_CR_PRIMUP_MASK1_IMPH_EP_MSK (0x00400000) + #define MPVTDTRK_CR_PRIMUP_MASK1_IMPH_EP_MAX (0x00000001) + #define MPVTDTRK_CR_PRIMUP_MASK1_IMPH_EP_DEF (0x00000000) + #define MPVTDTRK_CR_PRIMUP_MASK1_IMPH_AT_OFF (23) + #define MPVTDTRK_CR_PRIMUP_MASK1_IMPH_AT_WID ( 2) + #define MPVTDTRK_CR_PRIMUP_MASK1_IMPH_AT_MSK (0x01800000) + #define MPVTDTRK_CR_PRIMUP_MASK1_IMPH_AT_MAX (0x00000003) + #define MPVTDTRK_CR_PRIMUP_MASK1_IMPH_AT_DEF (0x00000000) + +#define MPVTDTRK_CR_PRIMUP_MASK2_IMPH_REG (0x00006054) + #define MPVTDTRK_CR_PRIMUP_MASK2_IMPH_RQID_OFF ( 0) + #define MPVTDTRK_CR_PRIMUP_MASK2_IMPH_RQID_WID (16) + #define MPVTDTRK_CR_PRIMUP_MASK2_IMPH_RQID_MSK (0x0000FFFF) + #define MPVTDTRK_CR_PRIMUP_MASK2_IMPH_RQID_MAX (0x0000FFFF) + #define MPVTDTRK_CR_PRIMUP_MASK2_IMPH_RQID_DEF (0x00000000) + #define MPVTDTRK_CR_PRIMUP_MASK2_IMPH_TAG_OFF (16) + #define MPVTDTRK_CR_PRIMUP_MASK2_IMPH_TAG_WID ( 8) + #define MPVTDTRK_CR_PRIMUP_MASK2_IMPH_TAG_MSK (0x00FF0000) + #define MPVTDTRK_CR_PRIMUP_MASK2_IMPH_TAG_MAX (0x000000FF) + #define MPVTDTRK_CR_PRIMUP_MASK2_IMPH_TAG_DEF (0x00000000) + #define MPVTDTRK_CR_PRIMUP_MASK2_IMPH_LBEFBE_MSGTYPE_OFF (24) + #define MPVTDTRK_CR_PRIMUP_MASK2_IMPH_LBEFBE_MSGTYPE_WID ( 8) + #define MPVTDTRK_CR_PRIMUP_MASK2_IMPH_LBEFBE_MSGTYPE_MSK (0xFF000000) + #define MPVTDTRK_CR_PRIMUP_MASK2_IMPH_LBEFBE_MSGTYPE_MAX (0x000000FF) + #define MPVTDTRK_CR_PRIMUP_MASK2_IMPH_LBEFBE_MSGTYPE_DEF (0x00000000) + +#define MPVTDTRK_CR_PRIMUP_MASK3_IMPH_REG (0x00006058) + #define MPVTDTRK_CR_PRIMUP_MASK3_IMPH_ADDR_31_0_OFF ( 0) + #define MPVTDTRK_CR_PRIMUP_MASK3_IMPH_ADDR_31_0_WID (32) + #define MPVTDTRK_CR_PRIMUP_MASK3_IMPH_ADDR_31_0_MSK (0xFFFFFFFF) + #define MPVTDTRK_CR_PRIMUP_MASK3_IMPH_ADDR_31_0_MAX (0xFFFFFFFF) + #define MPVTDTRK_CR_PRIMUP_MASK3_IMPH_ADDR_31_0_DEF (0x00000000) + +#define MPVTDTRK_CR_PRIMUP_MASK4_IMPH_REG (0x0000605C) + #define MPVTDTRK_CR_PRIMUP_MASK4_IMPH_ADDR_63_32_OFF ( 0) + #define MPVTDTRK_CR_PRIMUP_MASK4_IMPH_ADDR_63_32_WID (32) + #define MPVTDTRK_CR_PRIMUP_MASK4_IMPH_ADDR_63_32_MSK (0xFFFFFFFF) + #define MPVTDTRK_CR_PRIMUP_MASK4_IMPH_ADDR_63_32_MAX (0xFFFFFFFF) + #define MPVTDTRK_CR_PRIMUP_MASK4_IMPH_ADDR_63_32_DEF (0x00000000) + +#define MPVTDTRK_CR_PRIMUP_COMP1_IMPH_REG (0x00006060) + #define MPVTDTRK_CR_PRIMUP_COMP1_IMPH_VC_OFF ( 0) + #define MPVTDTRK_CR_PRIMUP_COMP1_IMPH_VC_WID ( 4) + #define MPVTDTRK_CR_PRIMUP_COMP1_IMPH_VC_MSK (0x0000000F) + #define MPVTDTRK_CR_PRIMUP_COMP1_IMPH_VC_MAX (0x0000000F) + #define MPVTDTRK_CR_PRIMUP_COMP1_IMPH_VC_DEF (0x00000000) + #define MPVTDTRK_CR_PRIMUP_COMP1_IMPH_FMT_CMDTYPE_OFF ( 4) + #define MPVTDTRK_CR_PRIMUP_COMP1_IMPH_FMT_CMDTYPE_WID ( 6) + #define MPVTDTRK_CR_PRIMUP_COMP1_IMPH_FMT_CMDTYPE_MSK (0x000003F0) + #define MPVTDTRK_CR_PRIMUP_COMP1_IMPH_FMT_CMDTYPE_MAX (0x0000003F) + #define MPVTDTRK_CR_PRIMUP_COMP1_IMPH_FMT_CMDTYPE_DEF (0x00000000) + #define MPVTDTRK_CR_PRIMUP_COMP1_IMPH_TC_OFF (10) + #define MPVTDTRK_CR_PRIMUP_COMP1_IMPH_TC_WID ( 4) + #define MPVTDTRK_CR_PRIMUP_COMP1_IMPH_TC_MSK (0x00003C00) + #define MPVTDTRK_CR_PRIMUP_COMP1_IMPH_TC_MAX (0x0000000F) + #define MPVTDTRK_CR_PRIMUP_COMP1_IMPH_TC_DEF (0x00000000) + #define MPVTDTRK_CR_PRIMUP_COMP1_IMPH_CHAIN_OFF (14) + #define MPVTDTRK_CR_PRIMUP_COMP1_IMPH_CHAIN_WID ( 1) + #define MPVTDTRK_CR_PRIMUP_COMP1_IMPH_CHAIN_MSK (0x00004000) + #define MPVTDTRK_CR_PRIMUP_COMP1_IMPH_CHAIN_MAX (0x00000001) + #define MPVTDTRK_CR_PRIMUP_COMP1_IMPH_CHAIN_DEF (0x00000000) + #define MPVTDTRK_CR_PRIMUP_COMP1_IMPH_NS_OFF (15) + #define MPVTDTRK_CR_PRIMUP_COMP1_IMPH_NS_WID ( 1) + #define MPVTDTRK_CR_PRIMUP_COMP1_IMPH_NS_MSK (0x00008000) + #define MPVTDTRK_CR_PRIMUP_COMP1_IMPH_NS_MAX (0x00000001) + #define MPVTDTRK_CR_PRIMUP_COMP1_IMPH_NS_DEF (0x00000000) + #define MPVTDTRK_CR_PRIMUP_COMP1_IMPH_RO_OFF (16) + #define MPVTDTRK_CR_PRIMUP_COMP1_IMPH_RO_WID ( 1) + #define MPVTDTRK_CR_PRIMUP_COMP1_IMPH_RO_MSK (0x00010000) + #define MPVTDTRK_CR_PRIMUP_COMP1_IMPH_RO_MAX (0x00000001) + #define MPVTDTRK_CR_PRIMUP_COMP1_IMPH_RO_DEF (0x00000000) + #define MPVTDTRK_CR_PRIMUP_COMP1_IMPH_LENGTH_OFF (17) + #define MPVTDTRK_CR_PRIMUP_COMP1_IMPH_LENGTH_WID ( 5) + #define MPVTDTRK_CR_PRIMUP_COMP1_IMPH_LENGTH_MSK (0x003E0000) + #define MPVTDTRK_CR_PRIMUP_COMP1_IMPH_LENGTH_MAX (0x0000001F) + #define MPVTDTRK_CR_PRIMUP_COMP1_IMPH_LENGTH_DEF (0x00000000) + #define MPVTDTRK_CR_PRIMUP_COMP1_IMPH_EP_OFF (22) + #define MPVTDTRK_CR_PRIMUP_COMP1_IMPH_EP_WID ( 1) + #define MPVTDTRK_CR_PRIMUP_COMP1_IMPH_EP_MSK (0x00400000) + #define MPVTDTRK_CR_PRIMUP_COMP1_IMPH_EP_MAX (0x00000001) + #define MPVTDTRK_CR_PRIMUP_COMP1_IMPH_EP_DEF (0x00000000) + #define MPVTDTRK_CR_PRIMUP_COMP1_IMPH_AT_OFF (23) + #define MPVTDTRK_CR_PRIMUP_COMP1_IMPH_AT_WID ( 2) + #define MPVTDTRK_CR_PRIMUP_COMP1_IMPH_AT_MSK (0x01800000) + #define MPVTDTRK_CR_PRIMUP_COMP1_IMPH_AT_MAX (0x00000003) + #define MPVTDTRK_CR_PRIMUP_COMP1_IMPH_AT_DEF (0x00000000) + +#define MPVTDTRK_CR_PRIMUP_COMP2_IMPH_REG (0x00006064) + #define MPVTDTRK_CR_PRIMUP_COMP2_IMPH_RQID_OFF ( 0) + #define MPVTDTRK_CR_PRIMUP_COMP2_IMPH_RQID_WID (16) + #define MPVTDTRK_CR_PRIMUP_COMP2_IMPH_RQID_MSK (0x0000FFFF) + #define MPVTDTRK_CR_PRIMUP_COMP2_IMPH_RQID_MAX (0x0000FFFF) + #define MPVTDTRK_CR_PRIMUP_COMP2_IMPH_RQID_DEF (0x00000000) + #define MPVTDTRK_CR_PRIMUP_COMP2_IMPH_TAG_OFF (16) + #define MPVTDTRK_CR_PRIMUP_COMP2_IMPH_TAG_WID ( 8) + #define MPVTDTRK_CR_PRIMUP_COMP2_IMPH_TAG_MSK (0x00FF0000) + #define MPVTDTRK_CR_PRIMUP_COMP2_IMPH_TAG_MAX (0x000000FF) + #define MPVTDTRK_CR_PRIMUP_COMP2_IMPH_TAG_DEF (0x00000000) + #define MPVTDTRK_CR_PRIMUP_COMP2_IMPH_LBEFBE_MSGTYPE_OFF (24) + #define MPVTDTRK_CR_PRIMUP_COMP2_IMPH_LBEFBE_MSGTYPE_WID ( 8) + #define MPVTDTRK_CR_PRIMUP_COMP2_IMPH_LBEFBE_MSGTYPE_MSK (0xFF000000) + #define MPVTDTRK_CR_PRIMUP_COMP2_IMPH_LBEFBE_MSGTYPE_MAX (0x000000FF) + #define MPVTDTRK_CR_PRIMUP_COMP2_IMPH_LBEFBE_MSGTYPE_DEF (0x00000000) + +#define MPVTDTRK_CR_PRIMUP_COMP3_IMPH_REG (0x00006068) + #define MPVTDTRK_CR_PRIMUP_COMP3_IMPH_ADDR_31_0_OFF ( 0) + #define MPVTDTRK_CR_PRIMUP_COMP3_IMPH_ADDR_31_0_WID (32) + #define MPVTDTRK_CR_PRIMUP_COMP3_IMPH_ADDR_31_0_MSK (0xFFFFFFFF) + #define MPVTDTRK_CR_PRIMUP_COMP3_IMPH_ADDR_31_0_MAX (0xFFFFFFFF) + #define MPVTDTRK_CR_PRIMUP_COMP3_IMPH_ADDR_31_0_DEF (0x00000000) + +#define MPVTDTRK_CR_PRIMUP_COMP4_IMPH_REG (0x0000606C) + #define MPVTDTRK_CR_PRIMUP_COMP4_IMPH_ADDR_63_32_OFF ( 0) + #define MPVTDTRK_CR_PRIMUP_COMP4_IMPH_ADDR_63_32_WID (32) + #define MPVTDTRK_CR_PRIMUP_COMP4_IMPH_ADDR_63_32_MSK (0xFFFFFFFF) + #define MPVTDTRK_CR_PRIMUP_COMP4_IMPH_ADDR_63_32_MAX (0xFFFFFFFF) + #define MPVTDTRK_CR_PRIMUP_COMP4_IMPH_ADDR_63_32_DEF (0x00000000) + +#define MPVTDTRK_CR_PRIMUP_TRIGGER_IMPH_REG (0x00006070) + #define MPVTDTRK_CR_PRIMUP_TRIGGER_IMPH_ENABLE_OFF ( 0) + #define MPVTDTRK_CR_PRIMUP_TRIGGER_IMPH_ENABLE_WID ( 1) + #define MPVTDTRK_CR_PRIMUP_TRIGGER_IMPH_ENABLE_MSK (0x00000001) + #define MPVTDTRK_CR_PRIMUP_TRIGGER_IMPH_ENABLE_MAX (0x00000001) + #define MPVTDTRK_CR_PRIMUP_TRIGGER_IMPH_ENABLE_DEF (0x00000000) + #define MPVTDTRK_CR_PRIMUP_TRIGGER_IMPH_TRIGGERED_OFF ( 1) + #define MPVTDTRK_CR_PRIMUP_TRIGGER_IMPH_TRIGGERED_WID ( 1) + #define MPVTDTRK_CR_PRIMUP_TRIGGER_IMPH_TRIGGERED_MSK (0x00000002) + #define MPVTDTRK_CR_PRIMUP_TRIGGER_IMPH_TRIGGERED_MAX (0x00000001) + #define MPVTDTRK_CR_PRIMUP_TRIGGER_IMPH_TRIGGERED_DEF (0x00000000) + #define MPVTDTRK_CR_PRIMUP_TRIGGER_IMPH_STALL_DNARB_OFF ( 2) + #define MPVTDTRK_CR_PRIMUP_TRIGGER_IMPH_STALL_DNARB_WID ( 1) + #define MPVTDTRK_CR_PRIMUP_TRIGGER_IMPH_STALL_DNARB_MSK (0x00000004) + #define MPVTDTRK_CR_PRIMUP_TRIGGER_IMPH_STALL_DNARB_MAX (0x00000001) + #define MPVTDTRK_CR_PRIMUP_TRIGGER_IMPH_STALL_DNARB_DEF (0x00000000) + #define MPVTDTRK_CR_PRIMUP_TRIGGER_IMPH_STALL_UPARB_OFF ( 3) + #define MPVTDTRK_CR_PRIMUP_TRIGGER_IMPH_STALL_UPARB_WID ( 1) + #define MPVTDTRK_CR_PRIMUP_TRIGGER_IMPH_STALL_UPARB_MSK (0x00000008) + #define MPVTDTRK_CR_PRIMUP_TRIGGER_IMPH_STALL_UPARB_MAX (0x00000001) + #define MPVTDTRK_CR_PRIMUP_TRIGGER_IMPH_STALL_UPARB_DEF (0x00000000) + #define MPVTDTRK_CR_PRIMUP_TRIGGER_IMPH_STALL_SNPARB_OFF ( 4) + #define MPVTDTRK_CR_PRIMUP_TRIGGER_IMPH_STALL_SNPARB_WID ( 1) + #define MPVTDTRK_CR_PRIMUP_TRIGGER_IMPH_STALL_SNPARB_MSK (0x00000010) + #define MPVTDTRK_CR_PRIMUP_TRIGGER_IMPH_STALL_SNPARB_MAX (0x00000001) + #define MPVTDTRK_CR_PRIMUP_TRIGGER_IMPH_STALL_SNPARB_DEF (0x00000000) + #define MPVTDTRK_CR_PRIMUP_TRIGGER_IMPH_STALL_DELAY_OFF (23) + #define MPVTDTRK_CR_PRIMUP_TRIGGER_IMPH_STALL_DELAY_WID ( 9) + #define MPVTDTRK_CR_PRIMUP_TRIGGER_IMPH_STALL_DELAY_MSK (0xFF800000) + #define MPVTDTRK_CR_PRIMUP_TRIGGER_IMPH_STALL_DELAY_MAX (0x000001FF) + #define MPVTDTRK_CR_PRIMUP_TRIGGER_IMPH_STALL_DELAY_DEF (0x00000000) + +#define MPVTDTRK_CR_HCTL0_IMPH_REG (0x00006100) + #define MPVTDTRK_CR_HCTL0_IMPH_PEG2DMIDIS_OFF ( 0) + #define MPVTDTRK_CR_HCTL0_IMPH_PEG2DMIDIS_WID ( 1) + #define MPVTDTRK_CR_HCTL0_IMPH_PEG2DMIDIS_MSK (0x00000001) + #define MPVTDTRK_CR_HCTL0_IMPH_PEG2DMIDIS_MAX (0x00000001) + #define MPVTDTRK_CR_HCTL0_IMPH_PEG2DMIDIS_DEF (0x00000000) + #define MPVTDTRK_CR_HCTL0_IMPH_EOIB_OFF ( 1) + #define MPVTDTRK_CR_HCTL0_IMPH_EOIB_WID ( 1) + #define MPVTDTRK_CR_HCTL0_IMPH_EOIB_MSK (0x00000002) + #define MPVTDTRK_CR_HCTL0_IMPH_EOIB_MAX (0x00000001) + #define MPVTDTRK_CR_HCTL0_IMPH_EOIB_DEF (0x00000000) + #define MPVTDTRK_CR_HCTL0_IMPH_MSIBYPDIS_OFF ( 2) + #define MPVTDTRK_CR_HCTL0_IMPH_MSIBYPDIS_WID ( 1) + #define MPVTDTRK_CR_HCTL0_IMPH_MSIBYPDIS_MSK (0x00000004) + #define MPVTDTRK_CR_HCTL0_IMPH_MSIBYPDIS_MAX (0x00000001) + #define MPVTDTRK_CR_HCTL0_IMPH_MSIBYPDIS_DEF (0x00000000) + #define MPVTDTRK_CR_HCTL0_IMPH_PHLDDIS_OFF ( 4) + #define MPVTDTRK_CR_HCTL0_IMPH_PHLDDIS_WID ( 1) + #define MPVTDTRK_CR_HCTL0_IMPH_PHLDDIS_MSK (0x00000010) + #define MPVTDTRK_CR_HCTL0_IMPH_PHLDDIS_MAX (0x00000001) + #define MPVTDTRK_CR_HCTL0_IMPH_PHLDDIS_DEF (0x00000000) + #define MPVTDTRK_CR_HCTL0_IMPH_BKSNPDIS_OFF ( 6) + #define MPVTDTRK_CR_HCTL0_IMPH_BKSNPDIS_WID ( 1) + #define MPVTDTRK_CR_HCTL0_IMPH_BKSNPDIS_MSK (0x00000040) + #define MPVTDTRK_CR_HCTL0_IMPH_BKSNPDIS_MAX (0x00000001) + #define MPVTDTRK_CR_HCTL0_IMPH_BKSNPDIS_DEF (0x00000000) + #define MPVTDTRK_CR_HCTL0_IMPH_FRCVC0SNP_OFF ( 7) + #define MPVTDTRK_CR_HCTL0_IMPH_FRCVC0SNP_WID ( 1) + #define MPVTDTRK_CR_HCTL0_IMPH_FRCVC0SNP_MSK (0x00000080) + #define MPVTDTRK_CR_HCTL0_IMPH_FRCVC0SNP_MAX (0x00000001) + #define MPVTDTRK_CR_HCTL0_IMPH_FRCVC0SNP_DEF (0x00000000) + #define MPVTDTRK_CR_HCTL0_IMPH_FRCVCPSNP_OFF ( 8) + #define MPVTDTRK_CR_HCTL0_IMPH_FRCVCPSNP_WID ( 1) + #define MPVTDTRK_CR_HCTL0_IMPH_FRCVCPSNP_MSK (0x00000100) + #define MPVTDTRK_CR_HCTL0_IMPH_FRCVCPSNP_MAX (0x00000001) + #define MPVTDTRK_CR_HCTL0_IMPH_FRCVCPSNP_DEF (0x00000000) + #define MPVTDTRK_CR_HCTL0_IMPH_PHLDBLKDIS_OFF ( 9) + #define MPVTDTRK_CR_HCTL0_IMPH_PHLDBLKDIS_WID ( 1) + #define MPVTDTRK_CR_HCTL0_IMPH_PHLDBLKDIS_MSK (0x00000200) + #define MPVTDTRK_CR_HCTL0_IMPH_PHLDBLKDIS_MAX (0x00000001) + #define MPVTDTRK_CR_HCTL0_IMPH_PHLDBLKDIS_DEF (0x00000000) + #define MPVTDTRK_CR_HCTL0_IMPH_BLKWRPOSTVC1_OFF (10) + #define MPVTDTRK_CR_HCTL0_IMPH_BLKWRPOSTVC1_WID ( 1) + #define MPVTDTRK_CR_HCTL0_IMPH_BLKWRPOSTVC1_MSK (0x00000400) + #define MPVTDTRK_CR_HCTL0_IMPH_BLKWRPOSTVC1_MAX (0x00000001) + #define MPVTDTRK_CR_HCTL0_IMPH_BLKWRPOSTVC1_DEF (0x00000000) + #define MPVTDTRK_CR_HCTL0_IMPH_DIS_VLW_PEG_OFF (11) + #define MPVTDTRK_CR_HCTL0_IMPH_DIS_VLW_PEG_WID ( 1) + #define MPVTDTRK_CR_HCTL0_IMPH_DIS_VLW_PEG_MSK (0x00000800) + #define MPVTDTRK_CR_HCTL0_IMPH_DIS_VLW_PEG_MAX (0x00000001) + #define MPVTDTRK_CR_HCTL0_IMPH_DIS_VLW_PEG_DEF (0x00000000) + #define MPVTDTRK_CR_HCTL0_IMPH_SPECRDDIS_OFF (12) + #define MPVTDTRK_CR_HCTL0_IMPH_SPECRDDIS_WID ( 1) + #define MPVTDTRK_CR_HCTL0_IMPH_SPECRDDIS_MSK (0x00001000) + #define MPVTDTRK_CR_HCTL0_IMPH_SPECRDDIS_MAX (0x00000001) + #define MPVTDTRK_CR_HCTL0_IMPH_SPECRDDIS_DEF (0x00000000) + #define MPVTDTRK_CR_HCTL0_IMPH_IR_RSRV_CTL_OFF (13) + #define MPVTDTRK_CR_HCTL0_IMPH_IR_RSRV_CTL_WID ( 1) + #define MPVTDTRK_CR_HCTL0_IMPH_IR_RSRV_CTL_MSK (0x00002000) + #define MPVTDTRK_CR_HCTL0_IMPH_IR_RSRV_CTL_MAX (0x00000001) + #define MPVTDTRK_CR_HCTL0_IMPH_IR_RSRV_CTL_DEF (0x00000000) + #define MPVTDTRK_CR_HCTL0_IMPH_RSVD_OFF (14) + #define MPVTDTRK_CR_HCTL0_IMPH_RSVD_WID (18) + #define MPVTDTRK_CR_HCTL0_IMPH_RSVD_MSK (0xFFFFC000) + #define MPVTDTRK_CR_HCTL0_IMPH_RSVD_MAX (0x0003FFFF) + #define MPVTDTRK_CR_HCTL0_IMPH_RSVD_DEF (0x00000000) + +#define MPVTDTRK_CR_REGBAR_IMPH_REG (0x00006110) + #define MPVTDTRK_CR_REGBAR_IMPH_REGBAR_OFF ( 4) + #define MPVTDTRK_CR_REGBAR_IMPH_REGBAR_WID (35) + #define MPVTDTRK_CR_REGBAR_IMPH_REGBAR_MSK (0x7FFFFFFFF0) + #define MPVTDTRK_CR_REGBAR_IMPH_REGBAR_MAX (0x7FFFFFFFF) + #define MPVTDTRK_CR_REGBAR_IMPH_REGBAR_DEF (0x00000000) + +#define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_REG (0x00006200) + #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_THERMAL_MONITOR_STATUS_OFF ( 0) + #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_THERMAL_MONITOR_STATUS_WID ( 1) + #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_THERMAL_MONITOR_STATUS_MSK (0x00000001) + #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_THERMAL_MONITOR_STATUS_MAX (0x00000001) + #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_THERMAL_MONITOR_STATUS_DEF (0x00000000) + #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_THERMAL_MONITOR_LOG_OFF ( 1) + #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_THERMAL_MONITOR_LOG_WID ( 1) + #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_THERMAL_MONITOR_LOG_MSK (0x00000002) + #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_THERMAL_MONITOR_LOG_MAX (0x00000001) + #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_THERMAL_MONITOR_LOG_DEF (0x00000000) + #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_PROCHOT_STATUS_OFF ( 2) + #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_PROCHOT_STATUS_WID ( 1) + #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_PROCHOT_STATUS_MSK (0x00000004) + #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_PROCHOT_STATUS_MAX (0x00000001) + #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_PROCHOT_STATUS_DEF (0x00000000) + #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_PROCHOT_LOG_OFF ( 3) + #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_PROCHOT_LOG_WID ( 1) + #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_PROCHOT_LOG_MSK (0x00000008) + #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_PROCHOT_LOG_MAX (0x00000001) + #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_PROCHOT_LOG_DEF (0x00000000) + #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_OUT_OF_SPEC_STATUS_OFF ( 4) + #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_OUT_OF_SPEC_STATUS_WID ( 1) + #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_OUT_OF_SPEC_STATUS_MSK (0x00000010) + #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_OUT_OF_SPEC_STATUS_MAX (0x00000001) + #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_OUT_OF_SPEC_STATUS_DEF (0x00000000) + #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_OUT_OF_SPEC_LOG_OFF ( 5) + #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_OUT_OF_SPEC_LOG_WID ( 1) + #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_OUT_OF_SPEC_LOG_MSK (0x00000020) + #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_OUT_OF_SPEC_LOG_MAX (0x00000001) + #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_OUT_OF_SPEC_LOG_DEF (0x00000000) + #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_THRESHOLD1_STATUS_OFF ( 6) + #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_THRESHOLD1_STATUS_WID ( 1) + #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_THRESHOLD1_STATUS_MSK (0x00000040) + #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_THRESHOLD1_STATUS_MAX (0x00000001) + #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_THRESHOLD1_STATUS_DEF (0x00000000) + #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_THRESHOLD1_LOG_OFF ( 7) + #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_THRESHOLD1_LOG_WID ( 1) + #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_THRESHOLD1_LOG_MSK (0x00000080) + #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_THRESHOLD1_LOG_MAX (0x00000001) + #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_THRESHOLD1_LOG_DEF (0x00000000) + #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_THRESHOLD2_STATUS_OFF ( 8) + #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_THRESHOLD2_STATUS_WID ( 1) + #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_THRESHOLD2_STATUS_MSK (0x00000100) + #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_THRESHOLD2_STATUS_MAX (0x00000001) + #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_THRESHOLD2_STATUS_DEF (0x00000000) + #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_THRESHOLD2_LOG_OFF ( 9) + #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_THRESHOLD2_LOG_WID ( 1) + #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_THRESHOLD2_LOG_MSK (0x00000200) + #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_THRESHOLD2_LOG_MAX (0x00000001) + #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_THRESHOLD2_LOG_DEF (0x00000000) + #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_POWER_LIMITATION_STATUS_OFF (10) + #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_POWER_LIMITATION_STATUS_WID ( 1) + #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_POWER_LIMITATION_STATUS_MSK (0x00000400) + #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_POWER_LIMITATION_STATUS_MAX (0x00000001) + #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_POWER_LIMITATION_STATUS_DEF (0x00000000) + #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_POWER_LIMITATION_LOG_OFF (11) + #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_POWER_LIMITATION_LOG_WID ( 1) + #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_POWER_LIMITATION_LOG_MSK (0x00000800) + #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_POWER_LIMITATION_LOG_MAX (0x00000001) + #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_POWER_LIMITATION_LOG_DEF (0x00000000) + #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_Temperature_OFF (16) + #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_Temperature_WID ( 7) + #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_Temperature_MSK (0x007F0000) + #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_Temperature_MAX (0x0000007F) + #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_Temperature_DEF (0x00000000) + #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_Resolution_OFF (27) + #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_Resolution_WID ( 4) + #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_Resolution_MSK (0x78000000) + #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_Resolution_MAX (0x0000000F) + #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_Resolution_DEF (0x00000001) + #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_Valid_OFF (31) + #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_Valid_WID ( 1) + #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_Valid_MSK (0x80000000) + #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_Valid_MAX (0x00000001) + #define MPVTDTRK_CR_PKG_THERM_CAMARILLO_STATUS_IMPH_Valid_DEF (0x00000000) + +#define MPVTDTRK_CR_DDR_THERM_CAMARILLO_STATUS_IMPH_REG (0x00006204) + #define MPVTDTRK_CR_DDR_THERM_CAMARILLO_STATUS_IMPH_WARM_THRESHOLD_STATUS_OFF ( 0) + #define MPVTDTRK_CR_DDR_THERM_CAMARILLO_STATUS_IMPH_WARM_THRESHOLD_STATUS_WID ( 1) + #define MPVTDTRK_CR_DDR_THERM_CAMARILLO_STATUS_IMPH_WARM_THRESHOLD_STATUS_MSK (0x00000001) + #define MPVTDTRK_CR_DDR_THERM_CAMARILLO_STATUS_IMPH_WARM_THRESHOLD_STATUS_MAX (0x00000001) + #define MPVTDTRK_CR_DDR_THERM_CAMARILLO_STATUS_IMPH_WARM_THRESHOLD_STATUS_DEF (0x00000000) + #define MPVTDTRK_CR_DDR_THERM_CAMARILLO_STATUS_IMPH_WARM_THRESHOLD_LOG_OFF ( 1) + #define MPVTDTRK_CR_DDR_THERM_CAMARILLO_STATUS_IMPH_WARM_THRESHOLD_LOG_WID ( 1) + #define MPVTDTRK_CR_DDR_THERM_CAMARILLO_STATUS_IMPH_WARM_THRESHOLD_LOG_MSK (0x00000002) + #define MPVTDTRK_CR_DDR_THERM_CAMARILLO_STATUS_IMPH_WARM_THRESHOLD_LOG_MAX (0x00000001) + #define MPVTDTRK_CR_DDR_THERM_CAMARILLO_STATUS_IMPH_WARM_THRESHOLD_LOG_DEF (0x00000000) + #define MPVTDTRK_CR_DDR_THERM_CAMARILLO_STATUS_IMPH_HOT_THRESHOLD_STATUS_OFF ( 2) + #define MPVTDTRK_CR_DDR_THERM_CAMARILLO_STATUS_IMPH_HOT_THRESHOLD_STATUS_WID ( 1) + #define MPVTDTRK_CR_DDR_THERM_CAMARILLO_STATUS_IMPH_HOT_THRESHOLD_STATUS_MSK (0x00000004) + #define MPVTDTRK_CR_DDR_THERM_CAMARILLO_STATUS_IMPH_HOT_THRESHOLD_STATUS_MAX (0x00000001) + #define MPVTDTRK_CR_DDR_THERM_CAMARILLO_STATUS_IMPH_HOT_THRESHOLD_STATUS_DEF (0x00000000) + #define MPVTDTRK_CR_DDR_THERM_CAMARILLO_STATUS_IMPH_HOT_THRESHOLD_LOG_OFF ( 3) + #define MPVTDTRK_CR_DDR_THERM_CAMARILLO_STATUS_IMPH_HOT_THRESHOLD_LOG_WID ( 1) + #define MPVTDTRK_CR_DDR_THERM_CAMARILLO_STATUS_IMPH_HOT_THRESHOLD_LOG_MSK (0x00000008) + #define MPVTDTRK_CR_DDR_THERM_CAMARILLO_STATUS_IMPH_HOT_THRESHOLD_LOG_MAX (0x00000001) + #define MPVTDTRK_CR_DDR_THERM_CAMARILLO_STATUS_IMPH_HOT_THRESHOLD_LOG_DEF (0x00000000) + #define MPVTDTRK_CR_DDR_THERM_CAMARILLO_STATUS_IMPH_REFRESH2X_STATUS_OFF ( 4) + #define MPVTDTRK_CR_DDR_THERM_CAMARILLO_STATUS_IMPH_REFRESH2X_STATUS_WID ( 1) + #define MPVTDTRK_CR_DDR_THERM_CAMARILLO_STATUS_IMPH_REFRESH2X_STATUS_MSK (0x00000010) + #define MPVTDTRK_CR_DDR_THERM_CAMARILLO_STATUS_IMPH_REFRESH2X_STATUS_MAX (0x00000001) + #define MPVTDTRK_CR_DDR_THERM_CAMARILLO_STATUS_IMPH_REFRESH2X_STATUS_DEF (0x00000000) + #define MPVTDTRK_CR_DDR_THERM_CAMARILLO_STATUS_IMPH_REFRESH2X_LOG_OFF ( 5) + #define MPVTDTRK_CR_DDR_THERM_CAMARILLO_STATUS_IMPH_REFRESH2X_LOG_WID ( 1) + #define MPVTDTRK_CR_DDR_THERM_CAMARILLO_STATUS_IMPH_REFRESH2X_LOG_MSK (0x00000020) + #define MPVTDTRK_CR_DDR_THERM_CAMARILLO_STATUS_IMPH_REFRESH2X_LOG_MAX (0x00000001) + #define MPVTDTRK_CR_DDR_THERM_CAMARILLO_STATUS_IMPH_REFRESH2X_LOG_DEF (0x00000000) + #define MPVTDTRK_CR_DDR_THERM_CAMARILLO_STATUS_IMPH_FORCEMEMPR_STATUS_OFF ( 6) + #define MPVTDTRK_CR_DDR_THERM_CAMARILLO_STATUS_IMPH_FORCEMEMPR_STATUS_WID ( 1) + #define MPVTDTRK_CR_DDR_THERM_CAMARILLO_STATUS_IMPH_FORCEMEMPR_STATUS_MSK (0x00000040) + #define MPVTDTRK_CR_DDR_THERM_CAMARILLO_STATUS_IMPH_FORCEMEMPR_STATUS_MAX (0x00000001) + #define MPVTDTRK_CR_DDR_THERM_CAMARILLO_STATUS_IMPH_FORCEMEMPR_STATUS_DEF (0x00000000) + #define MPVTDTRK_CR_DDR_THERM_CAMARILLO_STATUS_IMPH_FORCEMEMPR_LOG_OFF ( 7) + #define MPVTDTRK_CR_DDR_THERM_CAMARILLO_STATUS_IMPH_FORCEMEMPR_LOG_WID ( 1) + #define MPVTDTRK_CR_DDR_THERM_CAMARILLO_STATUS_IMPH_FORCEMEMPR_LOG_MSK (0x00000080) + #define MPVTDTRK_CR_DDR_THERM_CAMARILLO_STATUS_IMPH_FORCEMEMPR_LOG_MAX (0x00000001) + #define MPVTDTRK_CR_DDR_THERM_CAMARILLO_STATUS_IMPH_FORCEMEMPR_LOG_DEF (0x00000000) + #define MPVTDTRK_CR_DDR_THERM_CAMARILLO_STATUS_IMPH_THRESHOLD1_STATUS_OFF ( 8) + #define MPVTDTRK_CR_DDR_THERM_CAMARILLO_STATUS_IMPH_THRESHOLD1_STATUS_WID ( 1) + #define MPVTDTRK_CR_DDR_THERM_CAMARILLO_STATUS_IMPH_THRESHOLD1_STATUS_MSK (0x00000100) + #define MPVTDTRK_CR_DDR_THERM_CAMARILLO_STATUS_IMPH_THRESHOLD1_STATUS_MAX (0x00000001) + #define MPVTDTRK_CR_DDR_THERM_CAMARILLO_STATUS_IMPH_THRESHOLD1_STATUS_DEF (0x00000000) + #define MPVTDTRK_CR_DDR_THERM_CAMARILLO_STATUS_IMPH_THRESHOLD1_LOG_OFF ( 9) + #define MPVTDTRK_CR_DDR_THERM_CAMARILLO_STATUS_IMPH_THRESHOLD1_LOG_WID ( 1) + #define MPVTDTRK_CR_DDR_THERM_CAMARILLO_STATUS_IMPH_THRESHOLD1_LOG_MSK (0x00000200) + #define MPVTDTRK_CR_DDR_THERM_CAMARILLO_STATUS_IMPH_THRESHOLD1_LOG_MAX (0x00000001) + #define MPVTDTRK_CR_DDR_THERM_CAMARILLO_STATUS_IMPH_THRESHOLD1_LOG_DEF (0x00000000) + #define MPVTDTRK_CR_DDR_THERM_CAMARILLO_STATUS_IMPH_THRESHOLD2_STATUS_OFF (10) + #define MPVTDTRK_CR_DDR_THERM_CAMARILLO_STATUS_IMPH_THRESHOLD2_STATUS_WID ( 1) + #define MPVTDTRK_CR_DDR_THERM_CAMARILLO_STATUS_IMPH_THRESHOLD2_STATUS_MSK (0x00000400) + #define MPVTDTRK_CR_DDR_THERM_CAMARILLO_STATUS_IMPH_THRESHOLD2_STATUS_MAX (0x00000001) + #define MPVTDTRK_CR_DDR_THERM_CAMARILLO_STATUS_IMPH_THRESHOLD2_STATUS_DEF (0x00000000) + #define MPVTDTRK_CR_DDR_THERM_CAMARILLO_STATUS_IMPH_THRESHOLD2_LOG_OFF (11) + #define MPVTDTRK_CR_DDR_THERM_CAMARILLO_STATUS_IMPH_THRESHOLD2_LOG_WID ( 1) + #define MPVTDTRK_CR_DDR_THERM_CAMARILLO_STATUS_IMPH_THRESHOLD2_LOG_MSK (0x00000800) + #define MPVTDTRK_CR_DDR_THERM_CAMARILLO_STATUS_IMPH_THRESHOLD2_LOG_MAX (0x00000001) + #define MPVTDTRK_CR_DDR_THERM_CAMARILLO_STATUS_IMPH_THRESHOLD2_LOG_DEF (0x00000000) + +#define MPVTDTRK_CR_VTDTRKLCK_IMPH_REG (0x000063FC) + #define MPVTDTRK_CR_VTDTRKLCK_IMPH_LOCK_OFF ( 0) + #define MPVTDTRK_CR_VTDTRKLCK_IMPH_LOCK_WID ( 1) + #define MPVTDTRK_CR_VTDTRKLCK_IMPH_LOCK_MSK (0x00000001) + #define MPVTDTRK_CR_VTDTRKLCK_IMPH_LOCK_MAX (0x00000001) + #define MPVTDTRK_CR_VTDTRKLCK_IMPH_LOCK_DEF (0x00000000) + +#define MPCBOTRK_CR_REQLIM_IMPH_REG (0x00006800) + #define MPCBOTRK_CR_REQLIM_IMPH_RDLIM_OFF ( 0) + #define MPCBOTRK_CR_REQLIM_IMPH_RDLIM_WID ( 3) + #define MPCBOTRK_CR_REQLIM_IMPH_RDLIM_MSK (0x00000007) + #define MPCBOTRK_CR_REQLIM_IMPH_RDLIM_MAX (0x00000007) + #define MPCBOTRK_CR_REQLIM_IMPH_RDLIM_DEF (0x00000004) + #define MPCBOTRK_CR_REQLIM_IMPH_WRLIM_OFF ( 4) + #define MPCBOTRK_CR_REQLIM_IMPH_WRLIM_WID ( 3) + #define MPCBOTRK_CR_REQLIM_IMPH_WRLIM_MSK (0x00000070) + #define MPCBOTRK_CR_REQLIM_IMPH_WRLIM_MAX (0x00000007) + #define MPCBOTRK_CR_REQLIM_IMPH_WRLIM_DEF (0x00000004) + #define MPCBOTRK_CR_REQLIM_IMPH_LOCK_OFF (31) + #define MPCBOTRK_CR_REQLIM_IMPH_LOCK_WID ( 1) + #define MPCBOTRK_CR_REQLIM_IMPH_LOCK_MSK (0x80000000) + #define MPCBOTRK_CR_REQLIM_IMPH_LOCK_MAX (0x00000001) + #define MPCBOTRK_CR_REQLIM_IMPH_LOCK_DEF (0x00000000) + +#define HUBS_CR_DMIVCLIM_HUBS_REG (0x00007000) + #define HUBS_CR_DMIVCLIM_HUBS_VCPNPLIM_OFF ( 0) + #define HUBS_CR_DMIVCLIM_HUBS_VCPNPLIM_WID ( 3) + #define HUBS_CR_DMIVCLIM_HUBS_VCPNPLIM_MSK (0x00000007) + #define HUBS_CR_DMIVCLIM_HUBS_VCPNPLIM_MAX (0x00000007) + #define HUBS_CR_DMIVCLIM_HUBS_VCPNPLIM_DEF (0x00000004) + #define HUBS_CR_DMIVCLIM_HUBS_VCPPLIM_OFF ( 4) + #define HUBS_CR_DMIVCLIM_HUBS_VCPPLIM_WID ( 3) + #define HUBS_CR_DMIVCLIM_HUBS_VCPPLIM_MSK (0x00000070) + #define HUBS_CR_DMIVCLIM_HUBS_VCPPLIM_MAX (0x00000007) + #define HUBS_CR_DMIVCLIM_HUBS_VCPPLIM_DEF (0x00000004) + #define HUBS_CR_DMIVCLIM_HUBS_VCMNPLIM_OFF ( 8) + #define HUBS_CR_DMIVCLIM_HUBS_VCMNPLIM_WID ( 3) + #define HUBS_CR_DMIVCLIM_HUBS_VCMNPLIM_MSK (0x00000700) + #define HUBS_CR_DMIVCLIM_HUBS_VCMNPLIM_MAX (0x00000007) + #define HUBS_CR_DMIVCLIM_HUBS_VCMNPLIM_DEF (0x00000004) + #define HUBS_CR_DMIVCLIM_HUBS_VCMPLIM_OFF (12) + #define HUBS_CR_DMIVCLIM_HUBS_VCMPLIM_WID ( 3) + #define HUBS_CR_DMIVCLIM_HUBS_VCMPLIM_MSK (0x00007000) + #define HUBS_CR_DMIVCLIM_HUBS_VCMPLIM_MAX (0x00000007) + #define HUBS_CR_DMIVCLIM_HUBS_VCMPLIM_DEF (0x00000004) + #define HUBS_CR_DMIVCLIM_HUBS_VCPCMPLIM_OFF (16) + #define HUBS_CR_DMIVCLIM_HUBS_VCPCMPLIM_WID ( 3) + #define HUBS_CR_DMIVCLIM_HUBS_VCPCMPLIM_MSK (0x00070000) + #define HUBS_CR_DMIVCLIM_HUBS_VCPCMPLIM_MAX (0x00000007) + #define HUBS_CR_DMIVCLIM_HUBS_VCPCMPLIM_DEF (0x00000004) + #define HUBS_CR_DMIVCLIM_HUBS_VCMCMPLIM_OFF (20) + #define HUBS_CR_DMIVCLIM_HUBS_VCMCMPLIM_WID ( 3) + #define HUBS_CR_DMIVCLIM_HUBS_VCMCMPLIM_MSK (0x00700000) + #define HUBS_CR_DMIVCLIM_HUBS_VCMCMPLIM_MAX (0x00000007) + #define HUBS_CR_DMIVCLIM_HUBS_VCMCMPLIM_DEF (0x00000004) + #define HUBS_CR_DMIVCLIM_HUBS_LOCK_OFF (31) + #define HUBS_CR_DMIVCLIM_HUBS_LOCK_WID ( 1) + #define HUBS_CR_DMIVCLIM_HUBS_LOCK_MSK (0x80000000) + #define HUBS_CR_DMIVCLIM_HUBS_LOCK_MAX (0x00000001) + #define HUBS_CR_DMIVCLIM_HUBS_LOCK_DEF (0x00000000) + +#define HUBS_CR_HUB0_PWRDN_OVRD_HUBS_REG (0x00007010) + #define HUBS_CR_HUB0_PWRDN_OVRD_HUBS_P0_OFF ( 0) + #define HUBS_CR_HUB0_PWRDN_OVRD_HUBS_P0_WID ( 1) + #define HUBS_CR_HUB0_PWRDN_OVRD_HUBS_P0_MSK (0x00000001) + #define HUBS_CR_HUB0_PWRDN_OVRD_HUBS_P0_MAX (0x00000001) + #define HUBS_CR_HUB0_PWRDN_OVRD_HUBS_P0_DEF (0x00000000) + #define HUBS_CR_HUB0_PWRDN_OVRD_HUBS_P1_OFF ( 1) + #define HUBS_CR_HUB0_PWRDN_OVRD_HUBS_P1_WID ( 1) + #define HUBS_CR_HUB0_PWRDN_OVRD_HUBS_P1_MSK (0x00000002) + #define HUBS_CR_HUB0_PWRDN_OVRD_HUBS_P1_MAX (0x00000001) + #define HUBS_CR_HUB0_PWRDN_OVRD_HUBS_P1_DEF (0x00000000) + #define HUBS_CR_HUB0_PWRDN_OVRD_HUBS_P2_OFF ( 2) + #define HUBS_CR_HUB0_PWRDN_OVRD_HUBS_P2_WID ( 1) + #define HUBS_CR_HUB0_PWRDN_OVRD_HUBS_P2_MSK (0x00000004) + #define HUBS_CR_HUB0_PWRDN_OVRD_HUBS_P2_MAX (0x00000001) + #define HUBS_CR_HUB0_PWRDN_OVRD_HUBS_P2_DEF (0x00000000) + #define HUBS_CR_HUB0_PWRDN_OVRD_HUBS_P3_OFF ( 3) + #define HUBS_CR_HUB0_PWRDN_OVRD_HUBS_P3_WID ( 1) + #define HUBS_CR_HUB0_PWRDN_OVRD_HUBS_P3_MSK (0x00000008) + #define HUBS_CR_HUB0_PWRDN_OVRD_HUBS_P3_MAX (0x00000001) + #define HUBS_CR_HUB0_PWRDN_OVRD_HUBS_P3_DEF (0x00000000) + +#define HUBS_CR_HUB1_PWRDN_OVRD_HUBS_REG (0x00007014) + #define HUBS_CR_HUB1_PWRDN_OVRD_HUBS_P0_OFF ( 0) + #define HUBS_CR_HUB1_PWRDN_OVRD_HUBS_P0_WID ( 1) + #define HUBS_CR_HUB1_PWRDN_OVRD_HUBS_P0_MSK (0x00000001) + #define HUBS_CR_HUB1_PWRDN_OVRD_HUBS_P0_MAX (0x00000001) + #define HUBS_CR_HUB1_PWRDN_OVRD_HUBS_P0_DEF (0x00000000) + #define HUBS_CR_HUB1_PWRDN_OVRD_HUBS_P1_OFF ( 1) + #define HUBS_CR_HUB1_PWRDN_OVRD_HUBS_P1_WID ( 1) + #define HUBS_CR_HUB1_PWRDN_OVRD_HUBS_P1_MSK (0x00000002) + #define HUBS_CR_HUB1_PWRDN_OVRD_HUBS_P1_MAX (0x00000001) + #define HUBS_CR_HUB1_PWRDN_OVRD_HUBS_P1_DEF (0x00000000) + #define HUBS_CR_HUB1_PWRDN_OVRD_HUBS_P2_OFF ( 2) + #define HUBS_CR_HUB1_PWRDN_OVRD_HUBS_P2_WID ( 1) + #define HUBS_CR_HUB1_PWRDN_OVRD_HUBS_P2_MSK (0x00000004) + #define HUBS_CR_HUB1_PWRDN_OVRD_HUBS_P2_MAX (0x00000001) + #define HUBS_CR_HUB1_PWRDN_OVRD_HUBS_P2_DEF (0x00000000) + #define HUBS_CR_HUB1_PWRDN_OVRD_HUBS_P3_OFF ( 3) + #define HUBS_CR_HUB1_PWRDN_OVRD_HUBS_P3_WID ( 1) + #define HUBS_CR_HUB1_PWRDN_OVRD_HUBS_P3_MSK (0x00000008) + #define HUBS_CR_HUB1_PWRDN_OVRD_HUBS_P3_MAX (0x00000001) + #define HUBS_CR_HUB1_PWRDN_OVRD_HUBS_P3_DEF (0x00000000) + +#define HUBS_CR_HUB2_PWRDN_OVRD_HUBS_REG (0x00007018) + #define HUBS_CR_HUB2_PWRDN_OVRD_HUBS_P0_OFF ( 0) + #define HUBS_CR_HUB2_PWRDN_OVRD_HUBS_P0_WID ( 1) + #define HUBS_CR_HUB2_PWRDN_OVRD_HUBS_P0_MSK (0x00000001) + #define HUBS_CR_HUB2_PWRDN_OVRD_HUBS_P0_MAX (0x00000001) + #define HUBS_CR_HUB2_PWRDN_OVRD_HUBS_P0_DEF (0x00000000) + #define HUBS_CR_HUB2_PWRDN_OVRD_HUBS_P1_OFF ( 1) + #define HUBS_CR_HUB2_PWRDN_OVRD_HUBS_P1_WID ( 1) + #define HUBS_CR_HUB2_PWRDN_OVRD_HUBS_P1_MSK (0x00000002) + #define HUBS_CR_HUB2_PWRDN_OVRD_HUBS_P1_MAX (0x00000001) + #define HUBS_CR_HUB2_PWRDN_OVRD_HUBS_P1_DEF (0x00000000) + #define HUBS_CR_HUB2_PWRDN_OVRD_HUBS_P2_OFF ( 2) + #define HUBS_CR_HUB2_PWRDN_OVRD_HUBS_P2_WID ( 1) + #define HUBS_CR_HUB2_PWRDN_OVRD_HUBS_P2_MSK (0x00000004) + #define HUBS_CR_HUB2_PWRDN_OVRD_HUBS_P2_MAX (0x00000001) + #define HUBS_CR_HUB2_PWRDN_OVRD_HUBS_P2_DEF (0x00000000) + #define HUBS_CR_HUB2_PWRDN_OVRD_HUBS_P3_OFF ( 3) + #define HUBS_CR_HUB2_PWRDN_OVRD_HUBS_P3_WID ( 1) + #define HUBS_CR_HUB2_PWRDN_OVRD_HUBS_P3_MSK (0x00000008) + #define HUBS_CR_HUB2_PWRDN_OVRD_HUBS_P3_MAX (0x00000001) + #define HUBS_CR_HUB2_PWRDN_OVRD_HUBS_P3_DEF (0x00000000) + +#define HUBS_CR_HUB0_DEFEATURE_HUBS_REG (0x0000701C) + #define HUBS_CR_HUB0_DEFEATURE_HUBS_BLK_GNT_P0_OFF ( 0) + #define HUBS_CR_HUB0_DEFEATURE_HUBS_BLK_GNT_P0_WID ( 1) + #define HUBS_CR_HUB0_DEFEATURE_HUBS_BLK_GNT_P0_MSK (0x00000001) + #define HUBS_CR_HUB0_DEFEATURE_HUBS_BLK_GNT_P0_MAX (0x00000001) + #define HUBS_CR_HUB0_DEFEATURE_HUBS_BLK_GNT_P0_DEF (0x00000000) + #define HUBS_CR_HUB0_DEFEATURE_HUBS_BLK_GNT_P1_OFF ( 1) + #define HUBS_CR_HUB0_DEFEATURE_HUBS_BLK_GNT_P1_WID ( 1) + #define HUBS_CR_HUB0_DEFEATURE_HUBS_BLK_GNT_P1_MSK (0x00000002) + #define HUBS_CR_HUB0_DEFEATURE_HUBS_BLK_GNT_P1_MAX (0x00000001) + #define HUBS_CR_HUB0_DEFEATURE_HUBS_BLK_GNT_P1_DEF (0x00000000) + #define HUBS_CR_HUB0_DEFEATURE_HUBS_BLK_GNT_P2_OFF ( 2) + #define HUBS_CR_HUB0_DEFEATURE_HUBS_BLK_GNT_P2_WID ( 1) + #define HUBS_CR_HUB0_DEFEATURE_HUBS_BLK_GNT_P2_MSK (0x00000004) + #define HUBS_CR_HUB0_DEFEATURE_HUBS_BLK_GNT_P2_MAX (0x00000001) + #define HUBS_CR_HUB0_DEFEATURE_HUBS_BLK_GNT_P2_DEF (0x00000000) + #define HUBS_CR_HUB0_DEFEATURE_HUBS_BLK_PUT_P0_OFF ( 3) + #define HUBS_CR_HUB0_DEFEATURE_HUBS_BLK_PUT_P0_WID ( 1) + #define HUBS_CR_HUB0_DEFEATURE_HUBS_BLK_PUT_P0_MSK (0x00000008) + #define HUBS_CR_HUB0_DEFEATURE_HUBS_BLK_PUT_P0_MAX (0x00000001) + #define HUBS_CR_HUB0_DEFEATURE_HUBS_BLK_PUT_P0_DEF (0x00000000) + #define HUBS_CR_HUB0_DEFEATURE_HUBS_BLK_PUT_P1_OFF ( 4) + #define HUBS_CR_HUB0_DEFEATURE_HUBS_BLK_PUT_P1_WID ( 1) + #define HUBS_CR_HUB0_DEFEATURE_HUBS_BLK_PUT_P1_MSK (0x00000010) + #define HUBS_CR_HUB0_DEFEATURE_HUBS_BLK_PUT_P1_MAX (0x00000001) + #define HUBS_CR_HUB0_DEFEATURE_HUBS_BLK_PUT_P1_DEF (0x00000000) + #define HUBS_CR_HUB0_DEFEATURE_HUBS_BLK_PUT_P2_OFF ( 5) + #define HUBS_CR_HUB0_DEFEATURE_HUBS_BLK_PUT_P2_WID ( 1) + #define HUBS_CR_HUB0_DEFEATURE_HUBS_BLK_PUT_P2_MSK (0x00000020) + #define HUBS_CR_HUB0_DEFEATURE_HUBS_BLK_PUT_P2_MAX (0x00000001) + #define HUBS_CR_HUB0_DEFEATURE_HUBS_BLK_PUT_P2_DEF (0x00000000) + #define HUBS_CR_HUB0_DEFEATURE_HUBS_BLK_PUT_P3_OFF ( 6) + #define HUBS_CR_HUB0_DEFEATURE_HUBS_BLK_PUT_P3_WID ( 1) + #define HUBS_CR_HUB0_DEFEATURE_HUBS_BLK_PUT_P3_MSK (0x00000040) + #define HUBS_CR_HUB0_DEFEATURE_HUBS_BLK_PUT_P3_MAX (0x00000001) + #define HUBS_CR_HUB0_DEFEATURE_HUBS_BLK_PUT_P3_DEF (0x00000000) + #define HUBS_CR_HUB0_DEFEATURE_HUBS_NO_CHAIN_P0_OFF ( 7) + #define HUBS_CR_HUB0_DEFEATURE_HUBS_NO_CHAIN_P0_WID ( 1) + #define HUBS_CR_HUB0_DEFEATURE_HUBS_NO_CHAIN_P0_MSK (0x00000080) + #define HUBS_CR_HUB0_DEFEATURE_HUBS_NO_CHAIN_P0_MAX (0x00000001) + #define HUBS_CR_HUB0_DEFEATURE_HUBS_NO_CHAIN_P0_DEF (0x00000000) + #define HUBS_CR_HUB0_DEFEATURE_HUBS_NO_CHAIN_P1_OFF ( 8) + #define HUBS_CR_HUB0_DEFEATURE_HUBS_NO_CHAIN_P1_WID ( 1) + #define HUBS_CR_HUB0_DEFEATURE_HUBS_NO_CHAIN_P1_MSK (0x00000100) + #define HUBS_CR_HUB0_DEFEATURE_HUBS_NO_CHAIN_P1_MAX (0x00000001) + #define HUBS_CR_HUB0_DEFEATURE_HUBS_NO_CHAIN_P1_DEF (0x00000000) + #define HUBS_CR_HUB0_DEFEATURE_HUBS_NO_CHAIN_P2_OFF ( 9) + #define HUBS_CR_HUB0_DEFEATURE_HUBS_NO_CHAIN_P2_WID ( 1) + #define HUBS_CR_HUB0_DEFEATURE_HUBS_NO_CHAIN_P2_MSK (0x00000200) + #define HUBS_CR_HUB0_DEFEATURE_HUBS_NO_CHAIN_P2_MAX (0x00000001) + #define HUBS_CR_HUB0_DEFEATURE_HUBS_NO_CHAIN_P2_DEF (0x00000000) + #define HUBS_CR_HUB0_DEFEATURE_HUBS_SLOW_UP_P0_OFF (10) + #define HUBS_CR_HUB0_DEFEATURE_HUBS_SLOW_UP_P0_WID ( 1) + #define HUBS_CR_HUB0_DEFEATURE_HUBS_SLOW_UP_P0_MSK (0x00000400) + #define HUBS_CR_HUB0_DEFEATURE_HUBS_SLOW_UP_P0_MAX (0x00000001) + #define HUBS_CR_HUB0_DEFEATURE_HUBS_SLOW_UP_P0_DEF (0x00000000) + #define HUBS_CR_HUB0_DEFEATURE_HUBS_SLOW_UP_P1_OFF (11) + #define HUBS_CR_HUB0_DEFEATURE_HUBS_SLOW_UP_P1_WID ( 1) + #define HUBS_CR_HUB0_DEFEATURE_HUBS_SLOW_UP_P1_MSK (0x00000800) + #define HUBS_CR_HUB0_DEFEATURE_HUBS_SLOW_UP_P1_MAX (0x00000001) + #define HUBS_CR_HUB0_DEFEATURE_HUBS_SLOW_UP_P1_DEF (0x00000000) + #define HUBS_CR_HUB0_DEFEATURE_HUBS_SLOW_UP_P2_OFF (12) + #define HUBS_CR_HUB0_DEFEATURE_HUBS_SLOW_UP_P2_WID ( 1) + #define HUBS_CR_HUB0_DEFEATURE_HUBS_SLOW_UP_P2_MSK (0x00001000) + #define HUBS_CR_HUB0_DEFEATURE_HUBS_SLOW_UP_P2_MAX (0x00000001) + #define HUBS_CR_HUB0_DEFEATURE_HUBS_SLOW_UP_P2_DEF (0x00000000) + #define HUBS_CR_HUB0_DEFEATURE_HUBS_SLOW_DN_P0_OFF (13) + #define HUBS_CR_HUB0_DEFEATURE_HUBS_SLOW_DN_P0_WID ( 1) + #define HUBS_CR_HUB0_DEFEATURE_HUBS_SLOW_DN_P0_MSK (0x00002000) + #define HUBS_CR_HUB0_DEFEATURE_HUBS_SLOW_DN_P0_MAX (0x00000001) + #define HUBS_CR_HUB0_DEFEATURE_HUBS_SLOW_DN_P0_DEF (0x00000000) + #define HUBS_CR_HUB0_DEFEATURE_HUBS_SLOW_DN_P1_OFF (14) + #define HUBS_CR_HUB0_DEFEATURE_HUBS_SLOW_DN_P1_WID ( 1) + #define HUBS_CR_HUB0_DEFEATURE_HUBS_SLOW_DN_P1_MSK (0x00004000) + #define HUBS_CR_HUB0_DEFEATURE_HUBS_SLOW_DN_P1_MAX (0x00000001) + #define HUBS_CR_HUB0_DEFEATURE_HUBS_SLOW_DN_P1_DEF (0x00000000) + #define HUBS_CR_HUB0_DEFEATURE_HUBS_SLOW_DN_P2_OFF (15) + #define HUBS_CR_HUB0_DEFEATURE_HUBS_SLOW_DN_P2_WID ( 1) + #define HUBS_CR_HUB0_DEFEATURE_HUBS_SLOW_DN_P2_MSK (0x00008000) + #define HUBS_CR_HUB0_DEFEATURE_HUBS_SLOW_DN_P2_MAX (0x00000001) + #define HUBS_CR_HUB0_DEFEATURE_HUBS_SLOW_DN_P2_DEF (0x00000000) + #define HUBS_CR_HUB0_DEFEATURE_HUBS_SLOW_DN_P3_OFF (16) + #define HUBS_CR_HUB0_DEFEATURE_HUBS_SLOW_DN_P3_WID ( 1) + #define HUBS_CR_HUB0_DEFEATURE_HUBS_SLOW_DN_P3_MSK (0x00010000) + #define HUBS_CR_HUB0_DEFEATURE_HUBS_SLOW_DN_P3_MAX (0x00000001) + #define HUBS_CR_HUB0_DEFEATURE_HUBS_SLOW_DN_P3_DEF (0x00000000) + #define HUBS_CR_HUB0_DEFEATURE_HUBS_SLOWER_CMD_OFF (17) + #define HUBS_CR_HUB0_DEFEATURE_HUBS_SLOWER_CMD_WID ( 1) + #define HUBS_CR_HUB0_DEFEATURE_HUBS_SLOWER_CMD_MSK (0x00020000) + #define HUBS_CR_HUB0_DEFEATURE_HUBS_SLOWER_CMD_MAX (0x00000001) + #define HUBS_CR_HUB0_DEFEATURE_HUBS_SLOWER_CMD_DEF (0x00000000) + #define HUBS_CR_HUB0_DEFEATURE_HUBS_DMI_NOPUSH_OFF (18) + #define HUBS_CR_HUB0_DEFEATURE_HUBS_DMI_NOPUSH_WID ( 1) + #define HUBS_CR_HUB0_DEFEATURE_HUBS_DMI_NOPUSH_MSK (0x00040000) + #define HUBS_CR_HUB0_DEFEATURE_HUBS_DMI_NOPUSH_MAX (0x00000001) + #define HUBS_CR_HUB0_DEFEATURE_HUBS_DMI_NOPUSH_DEF (0x00000000) + #define HUBS_CR_HUB0_DEFEATURE_HUBS_RO_PASS_NP_OFF (19) + #define HUBS_CR_HUB0_DEFEATURE_HUBS_RO_PASS_NP_WID ( 1) + #define HUBS_CR_HUB0_DEFEATURE_HUBS_RO_PASS_NP_MSK (0x00080000) + #define HUBS_CR_HUB0_DEFEATURE_HUBS_RO_PASS_NP_MAX (0x00000001) + #define HUBS_CR_HUB0_DEFEATURE_HUBS_RO_PASS_NP_DEF (0x00000000) + #define HUBS_CR_HUB0_DEFEATURE_HUBS_RST_CRD_P3_OFF (20) + #define HUBS_CR_HUB0_DEFEATURE_HUBS_RST_CRD_P3_WID ( 1) + #define HUBS_CR_HUB0_DEFEATURE_HUBS_RST_CRD_P3_MSK (0x00100000) + #define HUBS_CR_HUB0_DEFEATURE_HUBS_RST_CRD_P3_MAX (0x00000001) + #define HUBS_CR_HUB0_DEFEATURE_HUBS_RST_CRD_P3_DEF (0x00000000) + +#define HUBS_CR_HUB1_DEFEATURE_HUBS_REG (0x00007020) + #define HUBS_CR_HUB1_DEFEATURE_HUBS_BLK_GNT_P1_OFF ( 0) + #define HUBS_CR_HUB1_DEFEATURE_HUBS_BLK_GNT_P1_WID ( 1) + #define HUBS_CR_HUB1_DEFEATURE_HUBS_BLK_GNT_P1_MSK (0x00000001) + #define HUBS_CR_HUB1_DEFEATURE_HUBS_BLK_GNT_P1_MAX (0x00000001) + #define HUBS_CR_HUB1_DEFEATURE_HUBS_BLK_GNT_P1_DEF (0x00000000) + #define HUBS_CR_HUB1_DEFEATURE_HUBS_BLK_GNT_P2_OFF ( 1) + #define HUBS_CR_HUB1_DEFEATURE_HUBS_BLK_GNT_P2_WID ( 1) + #define HUBS_CR_HUB1_DEFEATURE_HUBS_BLK_GNT_P2_MSK (0x00000002) + #define HUBS_CR_HUB1_DEFEATURE_HUBS_BLK_GNT_P2_MAX (0x00000001) + #define HUBS_CR_HUB1_DEFEATURE_HUBS_BLK_GNT_P2_DEF (0x00000000) + #define HUBS_CR_HUB1_DEFEATURE_HUBS_BLK_PUT_P0_OFF ( 2) + #define HUBS_CR_HUB1_DEFEATURE_HUBS_BLK_PUT_P0_WID ( 1) + #define HUBS_CR_HUB1_DEFEATURE_HUBS_BLK_PUT_P0_MSK (0x00000004) + #define HUBS_CR_HUB1_DEFEATURE_HUBS_BLK_PUT_P0_MAX (0x00000001) + #define HUBS_CR_HUB1_DEFEATURE_HUBS_BLK_PUT_P0_DEF (0x00000000) + #define HUBS_CR_HUB1_DEFEATURE_HUBS_BLK_PUT_P1_OFF ( 3) + #define HUBS_CR_HUB1_DEFEATURE_HUBS_BLK_PUT_P1_WID ( 1) + #define HUBS_CR_HUB1_DEFEATURE_HUBS_BLK_PUT_P1_MSK (0x00000008) + #define HUBS_CR_HUB1_DEFEATURE_HUBS_BLK_PUT_P1_MAX (0x00000001) + #define HUBS_CR_HUB1_DEFEATURE_HUBS_BLK_PUT_P1_DEF (0x00000000) + #define HUBS_CR_HUB1_DEFEATURE_HUBS_BLK_PUT_P2_OFF ( 4) + #define HUBS_CR_HUB1_DEFEATURE_HUBS_BLK_PUT_P2_WID ( 1) + #define HUBS_CR_HUB1_DEFEATURE_HUBS_BLK_PUT_P2_MSK (0x00000010) + #define HUBS_CR_HUB1_DEFEATURE_HUBS_BLK_PUT_P2_MAX (0x00000001) + #define HUBS_CR_HUB1_DEFEATURE_HUBS_BLK_PUT_P2_DEF (0x00000000) + #define HUBS_CR_HUB1_DEFEATURE_HUBS_BLK_PUT_P3_OFF ( 5) + #define HUBS_CR_HUB1_DEFEATURE_HUBS_BLK_PUT_P3_WID ( 1) + #define HUBS_CR_HUB1_DEFEATURE_HUBS_BLK_PUT_P3_MSK (0x00000020) + #define HUBS_CR_HUB1_DEFEATURE_HUBS_BLK_PUT_P3_MAX (0x00000001) + #define HUBS_CR_HUB1_DEFEATURE_HUBS_BLK_PUT_P3_DEF (0x00000000) + #define HUBS_CR_HUB1_DEFEATURE_HUBS_NO_CHAIN_P1_OFF ( 6) + #define HUBS_CR_HUB1_DEFEATURE_HUBS_NO_CHAIN_P1_WID ( 1) + #define HUBS_CR_HUB1_DEFEATURE_HUBS_NO_CHAIN_P1_MSK (0x00000040) + #define HUBS_CR_HUB1_DEFEATURE_HUBS_NO_CHAIN_P1_MAX (0x00000001) + #define HUBS_CR_HUB1_DEFEATURE_HUBS_NO_CHAIN_P1_DEF (0x00000000) + #define HUBS_CR_HUB1_DEFEATURE_HUBS_NO_CHAIN_P2_OFF ( 7) + #define HUBS_CR_HUB1_DEFEATURE_HUBS_NO_CHAIN_P2_WID ( 1) + #define HUBS_CR_HUB1_DEFEATURE_HUBS_NO_CHAIN_P2_MSK (0x00000080) + #define HUBS_CR_HUB1_DEFEATURE_HUBS_NO_CHAIN_P2_MAX (0x00000001) + #define HUBS_CR_HUB1_DEFEATURE_HUBS_NO_CHAIN_P2_DEF (0x00000000) + #define HUBS_CR_HUB1_DEFEATURE_HUBS_SLOW_UP_P0_OFF ( 8) + #define HUBS_CR_HUB1_DEFEATURE_HUBS_SLOW_UP_P0_WID ( 1) + #define HUBS_CR_HUB1_DEFEATURE_HUBS_SLOW_UP_P0_MSK (0x00000100) + #define HUBS_CR_HUB1_DEFEATURE_HUBS_SLOW_UP_P0_MAX (0x00000001) + #define HUBS_CR_HUB1_DEFEATURE_HUBS_SLOW_UP_P0_DEF (0x00000000) + #define HUBS_CR_HUB1_DEFEATURE_HUBS_SLOW_UP_P1_OFF ( 9) + #define HUBS_CR_HUB1_DEFEATURE_HUBS_SLOW_UP_P1_WID ( 1) + #define HUBS_CR_HUB1_DEFEATURE_HUBS_SLOW_UP_P1_MSK (0x00000200) + #define HUBS_CR_HUB1_DEFEATURE_HUBS_SLOW_UP_P1_MAX (0x00000001) + #define HUBS_CR_HUB1_DEFEATURE_HUBS_SLOW_UP_P1_DEF (0x00000000) + #define HUBS_CR_HUB1_DEFEATURE_HUBS_SLOW_UP_P2_OFF (10) + #define HUBS_CR_HUB1_DEFEATURE_HUBS_SLOW_UP_P2_WID ( 1) + #define HUBS_CR_HUB1_DEFEATURE_HUBS_SLOW_UP_P2_MSK (0x00000400) + #define HUBS_CR_HUB1_DEFEATURE_HUBS_SLOW_UP_P2_MAX (0x00000001) + #define HUBS_CR_HUB1_DEFEATURE_HUBS_SLOW_UP_P2_DEF (0x00000000) + #define HUBS_CR_HUB1_DEFEATURE_HUBS_SLOW_DN_P1_OFF (11) + #define HUBS_CR_HUB1_DEFEATURE_HUBS_SLOW_DN_P1_WID ( 1) + #define HUBS_CR_HUB1_DEFEATURE_HUBS_SLOW_DN_P1_MSK (0x00000800) + #define HUBS_CR_HUB1_DEFEATURE_HUBS_SLOW_DN_P1_MAX (0x00000001) + #define HUBS_CR_HUB1_DEFEATURE_HUBS_SLOW_DN_P1_DEF (0x00000000) + #define HUBS_CR_HUB1_DEFEATURE_HUBS_SLOW_DN_P2_OFF (12) + #define HUBS_CR_HUB1_DEFEATURE_HUBS_SLOW_DN_P2_WID ( 1) + #define HUBS_CR_HUB1_DEFEATURE_HUBS_SLOW_DN_P2_MSK (0x00001000) + #define HUBS_CR_HUB1_DEFEATURE_HUBS_SLOW_DN_P2_MAX (0x00000001) + #define HUBS_CR_HUB1_DEFEATURE_HUBS_SLOW_DN_P2_DEF (0x00000000) + #define HUBS_CR_HUB1_DEFEATURE_HUBS_SLOW_DN_P3_OFF (13) + #define HUBS_CR_HUB1_DEFEATURE_HUBS_SLOW_DN_P3_WID ( 1) + #define HUBS_CR_HUB1_DEFEATURE_HUBS_SLOW_DN_P3_MSK (0x00002000) + #define HUBS_CR_HUB1_DEFEATURE_HUBS_SLOW_DN_P3_MAX (0x00000001) + #define HUBS_CR_HUB1_DEFEATURE_HUBS_SLOW_DN_P3_DEF (0x00000000) + #define HUBS_CR_HUB1_DEFEATURE_HUBS_SLOWER_CMD_OFF (14) + #define HUBS_CR_HUB1_DEFEATURE_HUBS_SLOWER_CMD_WID ( 1) + #define HUBS_CR_HUB1_DEFEATURE_HUBS_SLOWER_CMD_MSK (0x00004000) + #define HUBS_CR_HUB1_DEFEATURE_HUBS_SLOWER_CMD_MAX (0x00000001) + #define HUBS_CR_HUB1_DEFEATURE_HUBS_SLOWER_CMD_DEF (0x00000000) + #define HUBS_CR_HUB1_DEFEATURE_HUBS_RO_PASS_NP_OFF (15) + #define HUBS_CR_HUB1_DEFEATURE_HUBS_RO_PASS_NP_WID ( 1) + #define HUBS_CR_HUB1_DEFEATURE_HUBS_RO_PASS_NP_MSK (0x00008000) + #define HUBS_CR_HUB1_DEFEATURE_HUBS_RO_PASS_NP_MAX (0x00000001) + #define HUBS_CR_HUB1_DEFEATURE_HUBS_RO_PASS_NP_DEF (0x00000000) + #define HUBS_CR_HUB1_DEFEATURE_HUBS_RST_CRD_P0_OFF (16) + #define HUBS_CR_HUB1_DEFEATURE_HUBS_RST_CRD_P0_WID ( 1) + #define HUBS_CR_HUB1_DEFEATURE_HUBS_RST_CRD_P0_MSK (0x00010000) + #define HUBS_CR_HUB1_DEFEATURE_HUBS_RST_CRD_P0_MAX (0x00000001) + #define HUBS_CR_HUB1_DEFEATURE_HUBS_RST_CRD_P0_DEF (0x00000000) + #define HUBS_CR_HUB1_DEFEATURE_HUBS_RST_CRD_P3_OFF (17) + #define HUBS_CR_HUB1_DEFEATURE_HUBS_RST_CRD_P3_WID ( 1) + #define HUBS_CR_HUB1_DEFEATURE_HUBS_RST_CRD_P3_MSK (0x00020000) + #define HUBS_CR_HUB1_DEFEATURE_HUBS_RST_CRD_P3_MAX (0x00000001) + #define HUBS_CR_HUB1_DEFEATURE_HUBS_RST_CRD_P3_DEF (0x00000000) + +#define HUBS_CR_HUB2_DEFEATURE_HUBS_REG (0x00007024) + #define HUBS_CR_HUB2_DEFEATURE_HUBS_BLK_GNT_P1_OFF ( 0) + #define HUBS_CR_HUB2_DEFEATURE_HUBS_BLK_GNT_P1_WID ( 1) + #define HUBS_CR_HUB2_DEFEATURE_HUBS_BLK_GNT_P1_MSK (0x00000001) + #define HUBS_CR_HUB2_DEFEATURE_HUBS_BLK_GNT_P1_MAX (0x00000001) + #define HUBS_CR_HUB2_DEFEATURE_HUBS_BLK_GNT_P1_DEF (0x00000000) + #define HUBS_CR_HUB2_DEFEATURE_HUBS_BLK_GNT_P2_OFF ( 1) + #define HUBS_CR_HUB2_DEFEATURE_HUBS_BLK_GNT_P2_WID ( 1) + #define HUBS_CR_HUB2_DEFEATURE_HUBS_BLK_GNT_P2_MSK (0x00000002) + #define HUBS_CR_HUB2_DEFEATURE_HUBS_BLK_GNT_P2_MAX (0x00000001) + #define HUBS_CR_HUB2_DEFEATURE_HUBS_BLK_GNT_P2_DEF (0x00000000) + #define HUBS_CR_HUB2_DEFEATURE_HUBS_BLK_PUT_P0_OFF ( 2) + #define HUBS_CR_HUB2_DEFEATURE_HUBS_BLK_PUT_P0_WID ( 1) + #define HUBS_CR_HUB2_DEFEATURE_HUBS_BLK_PUT_P0_MSK (0x00000004) + #define HUBS_CR_HUB2_DEFEATURE_HUBS_BLK_PUT_P0_MAX (0x00000001) + #define HUBS_CR_HUB2_DEFEATURE_HUBS_BLK_PUT_P0_DEF (0x00000000) + #define HUBS_CR_HUB2_DEFEATURE_HUBS_BLK_PUT_P1_OFF ( 3) + #define HUBS_CR_HUB2_DEFEATURE_HUBS_BLK_PUT_P1_WID ( 1) + #define HUBS_CR_HUB2_DEFEATURE_HUBS_BLK_PUT_P1_MSK (0x00000008) + #define HUBS_CR_HUB2_DEFEATURE_HUBS_BLK_PUT_P1_MAX (0x00000001) + #define HUBS_CR_HUB2_DEFEATURE_HUBS_BLK_PUT_P1_DEF (0x00000000) + #define HUBS_CR_HUB2_DEFEATURE_HUBS_BLK_PUT_P2_OFF ( 4) + #define HUBS_CR_HUB2_DEFEATURE_HUBS_BLK_PUT_P2_WID ( 1) + #define HUBS_CR_HUB2_DEFEATURE_HUBS_BLK_PUT_P2_MSK (0x00000010) + #define HUBS_CR_HUB2_DEFEATURE_HUBS_BLK_PUT_P2_MAX (0x00000001) + #define HUBS_CR_HUB2_DEFEATURE_HUBS_BLK_PUT_P2_DEF (0x00000000) + #define HUBS_CR_HUB2_DEFEATURE_HUBS_NO_CHAIN_P1_OFF ( 5) + #define HUBS_CR_HUB2_DEFEATURE_HUBS_NO_CHAIN_P1_WID ( 1) + #define HUBS_CR_HUB2_DEFEATURE_HUBS_NO_CHAIN_P1_MSK (0x00000020) + #define HUBS_CR_HUB2_DEFEATURE_HUBS_NO_CHAIN_P1_MAX (0x00000001) + #define HUBS_CR_HUB2_DEFEATURE_HUBS_NO_CHAIN_P1_DEF (0x00000000) + #define HUBS_CR_HUB2_DEFEATURE_HUBS_NO_CHAIN_P2_OFF ( 6) + #define HUBS_CR_HUB2_DEFEATURE_HUBS_NO_CHAIN_P2_WID ( 1) + #define HUBS_CR_HUB2_DEFEATURE_HUBS_NO_CHAIN_P2_MSK (0x00000040) + #define HUBS_CR_HUB2_DEFEATURE_HUBS_NO_CHAIN_P2_MAX (0x00000001) + #define HUBS_CR_HUB2_DEFEATURE_HUBS_NO_CHAIN_P2_DEF (0x00000000) + #define HUBS_CR_HUB2_DEFEATURE_HUBS_SLOW_UP_P0_OFF ( 7) + #define HUBS_CR_HUB2_DEFEATURE_HUBS_SLOW_UP_P0_WID ( 1) + #define HUBS_CR_HUB2_DEFEATURE_HUBS_SLOW_UP_P0_MSK (0x00000080) + #define HUBS_CR_HUB2_DEFEATURE_HUBS_SLOW_UP_P0_MAX (0x00000001) + #define HUBS_CR_HUB2_DEFEATURE_HUBS_SLOW_UP_P0_DEF (0x00000000) + #define HUBS_CR_HUB2_DEFEATURE_HUBS_SLOW_UP_P1_OFF ( 8) + #define HUBS_CR_HUB2_DEFEATURE_HUBS_SLOW_UP_P1_WID ( 1) + #define HUBS_CR_HUB2_DEFEATURE_HUBS_SLOW_UP_P1_MSK (0x00000100) + #define HUBS_CR_HUB2_DEFEATURE_HUBS_SLOW_UP_P1_MAX (0x00000001) + #define HUBS_CR_HUB2_DEFEATURE_HUBS_SLOW_UP_P1_DEF (0x00000000) + #define HUBS_CR_HUB2_DEFEATURE_HUBS_SLOW_UP_P2_OFF ( 9) + #define HUBS_CR_HUB2_DEFEATURE_HUBS_SLOW_UP_P2_WID ( 1) + #define HUBS_CR_HUB2_DEFEATURE_HUBS_SLOW_UP_P2_MSK (0x00000200) + #define HUBS_CR_HUB2_DEFEATURE_HUBS_SLOW_UP_P2_MAX (0x00000001) + #define HUBS_CR_HUB2_DEFEATURE_HUBS_SLOW_UP_P2_DEF (0x00000000) + #define HUBS_CR_HUB2_DEFEATURE_HUBS_SLOW_DN_P1_OFF (10) + #define HUBS_CR_HUB2_DEFEATURE_HUBS_SLOW_DN_P1_WID ( 1) + #define HUBS_CR_HUB2_DEFEATURE_HUBS_SLOW_DN_P1_MSK (0x00000400) + #define HUBS_CR_HUB2_DEFEATURE_HUBS_SLOW_DN_P1_MAX (0x00000001) + #define HUBS_CR_HUB2_DEFEATURE_HUBS_SLOW_DN_P1_DEF (0x00000000) + #define HUBS_CR_HUB2_DEFEATURE_HUBS_SLOW_DN_P2_OFF (11) + #define HUBS_CR_HUB2_DEFEATURE_HUBS_SLOW_DN_P2_WID ( 1) + #define HUBS_CR_HUB2_DEFEATURE_HUBS_SLOW_DN_P2_MSK (0x00000800) + #define HUBS_CR_HUB2_DEFEATURE_HUBS_SLOW_DN_P2_MAX (0x00000001) + #define HUBS_CR_HUB2_DEFEATURE_HUBS_SLOW_DN_P2_DEF (0x00000000) + #define HUBS_CR_HUB2_DEFEATURE_HUBS_SLOWER_CMD_OFF (12) + #define HUBS_CR_HUB2_DEFEATURE_HUBS_SLOWER_CMD_WID ( 1) + #define HUBS_CR_HUB2_DEFEATURE_HUBS_SLOWER_CMD_MSK (0x00001000) + #define HUBS_CR_HUB2_DEFEATURE_HUBS_SLOWER_CMD_MAX (0x00000001) + #define HUBS_CR_HUB2_DEFEATURE_HUBS_SLOWER_CMD_DEF (0x00000000) + #define HUBS_CR_HUB2_DEFEATURE_HUBS_RST_CRD_P0_OFF (13) + #define HUBS_CR_HUB2_DEFEATURE_HUBS_RST_CRD_P0_WID ( 1) + #define HUBS_CR_HUB2_DEFEATURE_HUBS_RST_CRD_P0_MSK (0x00002000) + #define HUBS_CR_HUB2_DEFEATURE_HUBS_RST_CRD_P0_MAX (0x00000001) + #define HUBS_CR_HUB2_DEFEATURE_HUBS_RST_CRD_P0_DEF (0x00000000) + +#define HUBS_CR_PEGCTL_HUBS_REG (0x00007028) + #define HUBS_CR_PEGCTL_HUBS_PCIPWRGAT_OFF ( 0) + #define HUBS_CR_PEGCTL_HUBS_PCIPWRGAT_WID ( 1) + #define HUBS_CR_PEGCTL_HUBS_PCIPWRGAT_MSK (0x00000001) + #define HUBS_CR_PEGCTL_HUBS_PCIPWRGAT_MAX (0x00000001) + #define HUBS_CR_PEGCTL_HUBS_PCIPWRGAT_DEF (0x00000000) + +#define HUBS_CR_HUB_EMPTY_HUBS_REG (0x0000702C) + #define HUBS_CR_HUB_EMPTY_HUBS_H0_EMPTY_OFF ( 0) + #define HUBS_CR_HUB_EMPTY_HUBS_H0_EMPTY_WID ( 1) + #define HUBS_CR_HUB_EMPTY_HUBS_H0_EMPTY_MSK (0x00000001) + #define HUBS_CR_HUB_EMPTY_HUBS_H0_EMPTY_MAX (0x00000001) + #define HUBS_CR_HUB_EMPTY_HUBS_H0_EMPTY_DEF (0x00000001) + #define HUBS_CR_HUB_EMPTY_HUBS_H1_EMPTY_OFF ( 1) + #define HUBS_CR_HUB_EMPTY_HUBS_H1_EMPTY_WID ( 1) + #define HUBS_CR_HUB_EMPTY_HUBS_H1_EMPTY_MSK (0x00000002) + #define HUBS_CR_HUB_EMPTY_HUBS_H1_EMPTY_MAX (0x00000001) + #define HUBS_CR_HUB_EMPTY_HUBS_H1_EMPTY_DEF (0x00000001) + #define HUBS_CR_HUB_EMPTY_HUBS_H2_EMPTY_OFF ( 2) + #define HUBS_CR_HUB_EMPTY_HUBS_H2_EMPTY_WID ( 1) + #define HUBS_CR_HUB_EMPTY_HUBS_H2_EMPTY_MSK (0x00000004) + #define HUBS_CR_HUB_EMPTY_HUBS_H2_EMPTY_MAX (0x00000001) + #define HUBS_CR_HUB_EMPTY_HUBS_H2_EMPTY_DEF (0x00000001) + +#define HUBS_CR_HUB0_STATUS_HUBS_REG (0x00007030) + #define HUBS_CR_HUB0_STATUS_HUBS_REQ_VLD_P0_OFF ( 0) + #define HUBS_CR_HUB0_STATUS_HUBS_REQ_VLD_P0_WID ( 1) + #define HUBS_CR_HUB0_STATUS_HUBS_REQ_VLD_P0_MSK (0x00000001) + #define HUBS_CR_HUB0_STATUS_HUBS_REQ_VLD_P0_MAX (0x00000001) + #define HUBS_CR_HUB0_STATUS_HUBS_REQ_VLD_P0_DEF (0x00000000) + #define HUBS_CR_HUB0_STATUS_HUBS_REQ_VLD_P1_OFF ( 1) + #define HUBS_CR_HUB0_STATUS_HUBS_REQ_VLD_P1_WID ( 1) + #define HUBS_CR_HUB0_STATUS_HUBS_REQ_VLD_P1_MSK (0x00000002) + #define HUBS_CR_HUB0_STATUS_HUBS_REQ_VLD_P1_MAX (0x00000001) + #define HUBS_CR_HUB0_STATUS_HUBS_REQ_VLD_P1_DEF (0x00000000) + #define HUBS_CR_HUB0_STATUS_HUBS_REQ_VLD_P2_OFF ( 2) + #define HUBS_CR_HUB0_STATUS_HUBS_REQ_VLD_P2_WID ( 1) + #define HUBS_CR_HUB0_STATUS_HUBS_REQ_VLD_P2_MSK (0x00000004) + #define HUBS_CR_HUB0_STATUS_HUBS_REQ_VLD_P2_MAX (0x00000001) + #define HUBS_CR_HUB0_STATUS_HUBS_REQ_VLD_P2_DEF (0x00000000) + #define HUBS_CR_HUB0_STATUS_HUBS_REQ_VLD_P3_OFF ( 3) + #define HUBS_CR_HUB0_STATUS_HUBS_REQ_VLD_P3_WID ( 1) + #define HUBS_CR_HUB0_STATUS_HUBS_REQ_VLD_P3_MSK (0x00000008) + #define HUBS_CR_HUB0_STATUS_HUBS_REQ_VLD_P3_MAX (0x00000001) + #define HUBS_CR_HUB0_STATUS_HUBS_REQ_VLD_P3_DEF (0x00000000) + #define HUBS_CR_HUB0_STATUS_HUBS_TNX_VLD_P0_OFF ( 4) + #define HUBS_CR_HUB0_STATUS_HUBS_TNX_VLD_P0_WID ( 1) + #define HUBS_CR_HUB0_STATUS_HUBS_TNX_VLD_P0_MSK (0x00000010) + #define HUBS_CR_HUB0_STATUS_HUBS_TNX_VLD_P0_MAX (0x00000001) + #define HUBS_CR_HUB0_STATUS_HUBS_TNX_VLD_P0_DEF (0x00000000) + #define HUBS_CR_HUB0_STATUS_HUBS_TNX_VLD_P1_OFF ( 5) + #define HUBS_CR_HUB0_STATUS_HUBS_TNX_VLD_P1_WID ( 1) + #define HUBS_CR_HUB0_STATUS_HUBS_TNX_VLD_P1_MSK (0x00000020) + #define HUBS_CR_HUB0_STATUS_HUBS_TNX_VLD_P1_MAX (0x00000001) + #define HUBS_CR_HUB0_STATUS_HUBS_TNX_VLD_P1_DEF (0x00000000) + #define HUBS_CR_HUB0_STATUS_HUBS_TNX_VLD_P2_OFF ( 6) + #define HUBS_CR_HUB0_STATUS_HUBS_TNX_VLD_P2_WID ( 1) + #define HUBS_CR_HUB0_STATUS_HUBS_TNX_VLD_P2_MSK (0x00000040) + #define HUBS_CR_HUB0_STATUS_HUBS_TNX_VLD_P2_MAX (0x00000001) + #define HUBS_CR_HUB0_STATUS_HUBS_TNX_VLD_P2_DEF (0x00000000) + #define HUBS_CR_HUB0_STATUS_HUBS_TNX_VLD_P3_OFF ( 7) + #define HUBS_CR_HUB0_STATUS_HUBS_TNX_VLD_P3_WID ( 1) + #define HUBS_CR_HUB0_STATUS_HUBS_TNX_VLD_P3_MSK (0x00000080) + #define HUBS_CR_HUB0_STATUS_HUBS_TNX_VLD_P3_MAX (0x00000001) + #define HUBS_CR_HUB0_STATUS_HUBS_TNX_VLD_P3_DEF (0x00000000) + +#define HUBS_CR_HUB1_STATUS_HUBS_REG (0x00007034) + #define HUBS_CR_HUB1_STATUS_HUBS_REQ_VLD_P0_OFF ( 0) + #define HUBS_CR_HUB1_STATUS_HUBS_REQ_VLD_P0_WID ( 1) + #define HUBS_CR_HUB1_STATUS_HUBS_REQ_VLD_P0_MSK (0x00000001) + #define HUBS_CR_HUB1_STATUS_HUBS_REQ_VLD_P0_MAX (0x00000001) + #define HUBS_CR_HUB1_STATUS_HUBS_REQ_VLD_P0_DEF (0x00000000) + #define HUBS_CR_HUB1_STATUS_HUBS_REQ_VLD_P1_OFF ( 1) + #define HUBS_CR_HUB1_STATUS_HUBS_REQ_VLD_P1_WID ( 1) + #define HUBS_CR_HUB1_STATUS_HUBS_REQ_VLD_P1_MSK (0x00000002) + #define HUBS_CR_HUB1_STATUS_HUBS_REQ_VLD_P1_MAX (0x00000001) + #define HUBS_CR_HUB1_STATUS_HUBS_REQ_VLD_P1_DEF (0x00000000) + #define HUBS_CR_HUB1_STATUS_HUBS_REQ_VLD_P2_OFF ( 2) + #define HUBS_CR_HUB1_STATUS_HUBS_REQ_VLD_P2_WID ( 1) + #define HUBS_CR_HUB1_STATUS_HUBS_REQ_VLD_P2_MSK (0x00000004) + #define HUBS_CR_HUB1_STATUS_HUBS_REQ_VLD_P2_MAX (0x00000001) + #define HUBS_CR_HUB1_STATUS_HUBS_REQ_VLD_P2_DEF (0x00000000) + #define HUBS_CR_HUB1_STATUS_HUBS_REQ_VLD_P3_OFF ( 3) + #define HUBS_CR_HUB1_STATUS_HUBS_REQ_VLD_P3_WID ( 1) + #define HUBS_CR_HUB1_STATUS_HUBS_REQ_VLD_P3_MSK (0x00000008) + #define HUBS_CR_HUB1_STATUS_HUBS_REQ_VLD_P3_MAX (0x00000001) + #define HUBS_CR_HUB1_STATUS_HUBS_REQ_VLD_P3_DEF (0x00000000) + #define HUBS_CR_HUB1_STATUS_HUBS_TNX_VLD_P0_OFF ( 4) + #define HUBS_CR_HUB1_STATUS_HUBS_TNX_VLD_P0_WID ( 1) + #define HUBS_CR_HUB1_STATUS_HUBS_TNX_VLD_P0_MSK (0x00000010) + #define HUBS_CR_HUB1_STATUS_HUBS_TNX_VLD_P0_MAX (0x00000001) + #define HUBS_CR_HUB1_STATUS_HUBS_TNX_VLD_P0_DEF (0x00000000) + #define HUBS_CR_HUB1_STATUS_HUBS_TNX_VLD_P1_OFF ( 5) + #define HUBS_CR_HUB1_STATUS_HUBS_TNX_VLD_P1_WID ( 1) + #define HUBS_CR_HUB1_STATUS_HUBS_TNX_VLD_P1_MSK (0x00000020) + #define HUBS_CR_HUB1_STATUS_HUBS_TNX_VLD_P1_MAX (0x00000001) + #define HUBS_CR_HUB1_STATUS_HUBS_TNX_VLD_P1_DEF (0x00000000) + #define HUBS_CR_HUB1_STATUS_HUBS_TNX_VLD_P2_OFF ( 6) + #define HUBS_CR_HUB1_STATUS_HUBS_TNX_VLD_P2_WID ( 1) + #define HUBS_CR_HUB1_STATUS_HUBS_TNX_VLD_P2_MSK (0x00000040) + #define HUBS_CR_HUB1_STATUS_HUBS_TNX_VLD_P2_MAX (0x00000001) + #define HUBS_CR_HUB1_STATUS_HUBS_TNX_VLD_P2_DEF (0x00000000) + #define HUBS_CR_HUB1_STATUS_HUBS_TNX_VLD_P3_OFF ( 7) + #define HUBS_CR_HUB1_STATUS_HUBS_TNX_VLD_P3_WID ( 1) + #define HUBS_CR_HUB1_STATUS_HUBS_TNX_VLD_P3_MSK (0x00000080) + #define HUBS_CR_HUB1_STATUS_HUBS_TNX_VLD_P3_MAX (0x00000001) + #define HUBS_CR_HUB1_STATUS_HUBS_TNX_VLD_P3_DEF (0x00000000) + +#define HUBS_CR_HUB2_STATUS_HUBS_REG (0x00007038) + #define HUBS_CR_HUB2_STATUS_HUBS_REQ_VLD_P0_OFF ( 0) + #define HUBS_CR_HUB2_STATUS_HUBS_REQ_VLD_P0_WID ( 1) + #define HUBS_CR_HUB2_STATUS_HUBS_REQ_VLD_P0_MSK (0x00000001) + #define HUBS_CR_HUB2_STATUS_HUBS_REQ_VLD_P0_MAX (0x00000001) + #define HUBS_CR_HUB2_STATUS_HUBS_REQ_VLD_P0_DEF (0x00000000) + #define HUBS_CR_HUB2_STATUS_HUBS_REQ_VLD_P1_OFF ( 1) + #define HUBS_CR_HUB2_STATUS_HUBS_REQ_VLD_P1_WID ( 1) + #define HUBS_CR_HUB2_STATUS_HUBS_REQ_VLD_P1_MSK (0x00000002) + #define HUBS_CR_HUB2_STATUS_HUBS_REQ_VLD_P1_MAX (0x00000001) + #define HUBS_CR_HUB2_STATUS_HUBS_REQ_VLD_P1_DEF (0x00000000) + #define HUBS_CR_HUB2_STATUS_HUBS_REQ_VLD_P2_OFF ( 2) + #define HUBS_CR_HUB2_STATUS_HUBS_REQ_VLD_P2_WID ( 1) + #define HUBS_CR_HUB2_STATUS_HUBS_REQ_VLD_P2_MSK (0x00000004) + #define HUBS_CR_HUB2_STATUS_HUBS_REQ_VLD_P2_MAX (0x00000001) + #define HUBS_CR_HUB2_STATUS_HUBS_REQ_VLD_P2_DEF (0x00000000) + #define HUBS_CR_HUB2_STATUS_HUBS_REQ_VLD_P3_OFF ( 3) + #define HUBS_CR_HUB2_STATUS_HUBS_REQ_VLD_P3_WID ( 1) + #define HUBS_CR_HUB2_STATUS_HUBS_REQ_VLD_P3_MSK (0x00000008) + #define HUBS_CR_HUB2_STATUS_HUBS_REQ_VLD_P3_MAX (0x00000001) + #define HUBS_CR_HUB2_STATUS_HUBS_REQ_VLD_P3_DEF (0x00000000) + #define HUBS_CR_HUB2_STATUS_HUBS_TNX_VLD_P0_OFF ( 4) + #define HUBS_CR_HUB2_STATUS_HUBS_TNX_VLD_P0_WID ( 1) + #define HUBS_CR_HUB2_STATUS_HUBS_TNX_VLD_P0_MSK (0x00000010) + #define HUBS_CR_HUB2_STATUS_HUBS_TNX_VLD_P0_MAX (0x00000001) + #define HUBS_CR_HUB2_STATUS_HUBS_TNX_VLD_P0_DEF (0x00000000) + #define HUBS_CR_HUB2_STATUS_HUBS_TNX_VLD_P1_OFF ( 5) + #define HUBS_CR_HUB2_STATUS_HUBS_TNX_VLD_P1_WID ( 1) + #define HUBS_CR_HUB2_STATUS_HUBS_TNX_VLD_P1_MSK (0x00000020) + #define HUBS_CR_HUB2_STATUS_HUBS_TNX_VLD_P1_MAX (0x00000001) + #define HUBS_CR_HUB2_STATUS_HUBS_TNX_VLD_P1_DEF (0x00000000) + #define HUBS_CR_HUB2_STATUS_HUBS_TNX_VLD_P2_OFF ( 6) + #define HUBS_CR_HUB2_STATUS_HUBS_TNX_VLD_P2_WID ( 1) + #define HUBS_CR_HUB2_STATUS_HUBS_TNX_VLD_P2_MSK (0x00000040) + #define HUBS_CR_HUB2_STATUS_HUBS_TNX_VLD_P2_MAX (0x00000001) + #define HUBS_CR_HUB2_STATUS_HUBS_TNX_VLD_P2_DEF (0x00000000) + #define HUBS_CR_HUB2_STATUS_HUBS_TNX_VLD_P3_OFF ( 7) + #define HUBS_CR_HUB2_STATUS_HUBS_TNX_VLD_P3_WID ( 1) + #define HUBS_CR_HUB2_STATUS_HUBS_TNX_VLD_P3_MSK (0x00000080) + #define HUBS_CR_HUB2_STATUS_HUBS_TNX_VLD_P3_MAX (0x00000001) + #define HUBS_CR_HUB2_STATUS_HUBS_TNX_VLD_P3_DEF (0x00000000) + +#define HUBS_CR_VISA_CTL_SABHUB0S_HUBS_REG (0x00007100) + #define HUBS_CR_VISA_CTL_SABHUB0S_HUBS_Data_OFF ( 0) + #define HUBS_CR_VISA_CTL_SABHUB0S_HUBS_Data_WID (18) + #define HUBS_CR_VISA_CTL_SABHUB0S_HUBS_Data_MSK (0x0003FFFF) + #define HUBS_CR_VISA_CTL_SABHUB0S_HUBS_Data_MAX (0x0003FFFF) + #define HUBS_CR_VISA_CTL_SABHUB0S_HUBS_Data_DEF (0x00000000) + #define HUBS_CR_VISA_CTL_SABHUB0S_HUBS_VORANGE_OFF (31) + #define HUBS_CR_VISA_CTL_SABHUB0S_HUBS_VORANGE_WID ( 1) + #define HUBS_CR_VISA_CTL_SABHUB0S_HUBS_VORANGE_MSK (0x80000000) + #define HUBS_CR_VISA_CTL_SABHUB0S_HUBS_VORANGE_MAX (0x00000001) + #define HUBS_CR_VISA_CTL_SABHUB0S_HUBS_VORANGE_DEF (0x00000000) + +#define HUBS_CR_VISA_CTL_SABHUB1S_HUBS_REG (0x00007110) + #define HUBS_CR_VISA_CTL_SABHUB1S_HUBS_Data_OFF ( 0) + #define HUBS_CR_VISA_CTL_SABHUB1S_HUBS_Data_WID (18) + #define HUBS_CR_VISA_CTL_SABHUB1S_HUBS_Data_MSK (0x0003FFFF) + #define HUBS_CR_VISA_CTL_SABHUB1S_HUBS_Data_MAX (0x0003FFFF) + #define HUBS_CR_VISA_CTL_SABHUB1S_HUBS_Data_DEF (0x00000000) + #define HUBS_CR_VISA_CTL_SABHUB1S_HUBS_VORANGE_OFF (31) + #define HUBS_CR_VISA_CTL_SABHUB1S_HUBS_VORANGE_WID ( 1) + #define HUBS_CR_VISA_CTL_SABHUB1S_HUBS_VORANGE_MSK (0x80000000) + #define HUBS_CR_VISA_CTL_SABHUB1S_HUBS_VORANGE_MAX (0x00000001) + #define HUBS_CR_VISA_CTL_SABHUB1S_HUBS_VORANGE_DEF (0x00000000) + +#define HUBS_CR_VISA_CTL_SABHUB2S_HUBS_REG (0x00007120) + #define HUBS_CR_VISA_CTL_SABHUB2S_HUBS_Data_OFF ( 0) + #define HUBS_CR_VISA_CTL_SABHUB2S_HUBS_Data_WID (18) + #define HUBS_CR_VISA_CTL_SABHUB2S_HUBS_Data_MSK (0x0003FFFF) + #define HUBS_CR_VISA_CTL_SABHUB2S_HUBS_Data_MAX (0x0003FFFF) + #define HUBS_CR_VISA_CTL_SABHUB2S_HUBS_Data_DEF (0x00000000) + #define HUBS_CR_VISA_CTL_SABHUB2S_HUBS_VORANGE_OFF (31) + #define HUBS_CR_VISA_CTL_SABHUB2S_HUBS_VORANGE_WID ( 1) + #define HUBS_CR_VISA_CTL_SABHUB2S_HUBS_VORANGE_MSK (0x80000000) + #define HUBS_CR_VISA_CTL_SABHUB2S_HUBS_VORANGE_MAX (0x00000001) + #define HUBS_CR_VISA_CTL_SABHUB2S_HUBS_VORANGE_DEF (0x00000000) + +#define HUBS_CR_MBOX_WR_DATA_HUBS_REG (0x00007124) + #define HUBS_CR_MBOX_WR_DATA_HUBS_DATA_OFF ( 0) + #define HUBS_CR_MBOX_WR_DATA_HUBS_DATA_WID (32) + #define HUBS_CR_MBOX_WR_DATA_HUBS_DATA_MSK (0xFFFFFFFF) + #define HUBS_CR_MBOX_WR_DATA_HUBS_DATA_MAX (0xFFFFFFFF) + #define HUBS_CR_MBOX_WR_DATA_HUBS_DATA_DEF (0x00000000) + +#define HUBS_CR_MBOX_RD_DATA_HUBS_REG (0x00007128) + #define HUBS_CR_MBOX_RD_DATA_HUBS_DATA_OFF ( 0) + #define HUBS_CR_MBOX_RD_DATA_HUBS_DATA_WID (32) + #define HUBS_CR_MBOX_RD_DATA_HUBS_DATA_MSK (0xFFFFFFFF) + #define HUBS_CR_MBOX_RD_DATA_HUBS_DATA_MAX (0xFFFFFFFF) + #define HUBS_CR_MBOX_RD_DATA_HUBS_DATA_DEF (0x00000000) + +#define HUBS_CR_MBOX_ADDR_LO_HUBS_REG (0x0000712C) + #define HUBS_CR_MBOX_ADDR_LO_HUBS_ADDR_OFF ( 0) + #define HUBS_CR_MBOX_ADDR_LO_HUBS_ADDR_WID (32) + #define HUBS_CR_MBOX_ADDR_LO_HUBS_ADDR_MSK (0xFFFFFFFF) + #define HUBS_CR_MBOX_ADDR_LO_HUBS_ADDR_MAX (0xFFFFFFFF) + #define HUBS_CR_MBOX_ADDR_LO_HUBS_ADDR_DEF (0x00000000) + +#define HUBS_CR_MBOX_ADDR_HI_HUBS_REG (0x00007130) + #define HUBS_CR_MBOX_ADDR_HI_HUBS_ADDR_OFF ( 0) + #define HUBS_CR_MBOX_ADDR_HI_HUBS_ADDR_WID (32) + #define HUBS_CR_MBOX_ADDR_HI_HUBS_ADDR_MSK (0xFFFFFFFF) + #define HUBS_CR_MBOX_ADDR_HI_HUBS_ADDR_MAX (0xFFFFFFFF) + #define HUBS_CR_MBOX_ADDR_HI_HUBS_ADDR_DEF (0x00000000) + +#define HUBS_CR_MBOX_CMD_LO_HUBS_REG (0x00007134) + #define HUBS_CR_MBOX_CMD_LO_HUBS_FBE_OFF ( 0) + #define HUBS_CR_MBOX_CMD_LO_HUBS_FBE_WID ( 4) + #define HUBS_CR_MBOX_CMD_LO_HUBS_FBE_MSK (0x0000000F) + #define HUBS_CR_MBOX_CMD_LO_HUBS_FBE_MAX (0x0000000F) + #define HUBS_CR_MBOX_CMD_LO_HUBS_FBE_DEF (0x00000000) + #define HUBS_CR_MBOX_CMD_LO_HUBS_LBE_OFF ( 4) + #define HUBS_CR_MBOX_CMD_LO_HUBS_LBE_WID ( 4) + #define HUBS_CR_MBOX_CMD_LO_HUBS_LBE_MSK (0x000000F0) + #define HUBS_CR_MBOX_CMD_LO_HUBS_LBE_MAX (0x0000000F) + #define HUBS_CR_MBOX_CMD_LO_HUBS_LBE_DEF (0x00000000) + #define HUBS_CR_MBOX_CMD_LO_HUBS_TAG_OFF ( 8) + #define HUBS_CR_MBOX_CMD_LO_HUBS_TAG_WID ( 8) + #define HUBS_CR_MBOX_CMD_LO_HUBS_TAG_MSK (0x0000FF00) + #define HUBS_CR_MBOX_CMD_LO_HUBS_TAG_MAX (0x000000FF) + #define HUBS_CR_MBOX_CMD_LO_HUBS_TAG_DEF (0x00000000) + #define HUBS_CR_MBOX_CMD_LO_HUBS_RQID_OFF (16) + #define HUBS_CR_MBOX_CMD_LO_HUBS_RQID_WID (16) + #define HUBS_CR_MBOX_CMD_LO_HUBS_RQID_MSK (0xFFFF0000) + #define HUBS_CR_MBOX_CMD_LO_HUBS_RQID_MAX (0x0000FFFF) + #define HUBS_CR_MBOX_CMD_LO_HUBS_RQID_DEF (0x00000000) + +#define HUBS_CR_MBOX_CMD_HI_HUBS_REG (0x00007138) + #define HUBS_CR_MBOX_CMD_HI_HUBS_AT_OFF ( 0) + #define HUBS_CR_MBOX_CMD_HI_HUBS_AT_WID ( 2) + #define HUBS_CR_MBOX_CMD_HI_HUBS_AT_MSK (0x00000003) + #define HUBS_CR_MBOX_CMD_HI_HUBS_AT_MAX (0x00000003) + #define HUBS_CR_MBOX_CMD_HI_HUBS_AT_DEF (0x00000000) + #define HUBS_CR_MBOX_CMD_HI_HUBS_POISON_OFF ( 2) + #define HUBS_CR_MBOX_CMD_HI_HUBS_POISON_WID ( 1) + #define HUBS_CR_MBOX_CMD_HI_HUBS_POISON_MSK (0x00000004) + #define HUBS_CR_MBOX_CMD_HI_HUBS_POISON_MAX (0x00000001) + #define HUBS_CR_MBOX_CMD_HI_HUBS_POISON_DEF (0x00000000) + #define HUBS_CR_MBOX_CMD_HI_HUBS_LENGTH_OFF ( 3) + #define HUBS_CR_MBOX_CMD_HI_HUBS_LENGTH_WID ( 5) + #define HUBS_CR_MBOX_CMD_HI_HUBS_LENGTH_MSK (0x000000F8) + #define HUBS_CR_MBOX_CMD_HI_HUBS_LENGTH_MAX (0x0000001F) + #define HUBS_CR_MBOX_CMD_HI_HUBS_LENGTH_DEF (0x00000000) + #define HUBS_CR_MBOX_CMD_HI_HUBS_RELAXED_OFF ( 8) + #define HUBS_CR_MBOX_CMD_HI_HUBS_RELAXED_WID ( 1) + #define HUBS_CR_MBOX_CMD_HI_HUBS_RELAXED_MSK (0x00000100) + #define HUBS_CR_MBOX_CMD_HI_HUBS_RELAXED_MAX (0x00000001) + #define HUBS_CR_MBOX_CMD_HI_HUBS_RELAXED_DEF (0x00000000) + #define HUBS_CR_MBOX_CMD_HI_HUBS_NOSNOOP_OFF ( 9) + #define HUBS_CR_MBOX_CMD_HI_HUBS_NOSNOOP_WID ( 1) + #define HUBS_CR_MBOX_CMD_HI_HUBS_NOSNOOP_MSK (0x00000200) + #define HUBS_CR_MBOX_CMD_HI_HUBS_NOSNOOP_MAX (0x00000001) + #define HUBS_CR_MBOX_CMD_HI_HUBS_NOSNOOP_DEF (0x00000000) + #define HUBS_CR_MBOX_CMD_HI_HUBS_CHAIN_OFF (10) + #define HUBS_CR_MBOX_CMD_HI_HUBS_CHAIN_WID ( 1) + #define HUBS_CR_MBOX_CMD_HI_HUBS_CHAIN_MSK (0x00000400) + #define HUBS_CR_MBOX_CMD_HI_HUBS_CHAIN_MAX (0x00000001) + #define HUBS_CR_MBOX_CMD_HI_HUBS_CHAIN_DEF (0x00000000) + #define HUBS_CR_MBOX_CMD_HI_HUBS_CTYPE_OFF (11) + #define HUBS_CR_MBOX_CMD_HI_HUBS_CTYPE_WID ( 5) + #define HUBS_CR_MBOX_CMD_HI_HUBS_CTYPE_MSK (0x0000F800) + #define HUBS_CR_MBOX_CMD_HI_HUBS_CTYPE_MAX (0x0000001F) + #define HUBS_CR_MBOX_CMD_HI_HUBS_CTYPE_DEF (0x00000000) + #define HUBS_CR_MBOX_CMD_HI_HUBS_FMT_OFF (16) + #define HUBS_CR_MBOX_CMD_HI_HUBS_FMT_WID ( 2) + #define HUBS_CR_MBOX_CMD_HI_HUBS_FMT_MSK (0x00030000) + #define HUBS_CR_MBOX_CMD_HI_HUBS_FMT_MAX (0x00000003) + #define HUBS_CR_MBOX_CMD_HI_HUBS_FMT_DEF (0x00000000) + #define HUBS_CR_MBOX_CMD_HI_HUBS_TC_OFF (18) + #define HUBS_CR_MBOX_CMD_HI_HUBS_TC_WID ( 4) + #define HUBS_CR_MBOX_CMD_HI_HUBS_TC_MSK (0x003C0000) + #define HUBS_CR_MBOX_CMD_HI_HUBS_TC_MAX (0x0000000F) + #define HUBS_CR_MBOX_CMD_HI_HUBS_TC_DEF (0x00000000) + #define HUBS_CR_MBOX_CMD_HI_HUBS_RESERVED_OFF (22) + #define HUBS_CR_MBOX_CMD_HI_HUBS_RESERVED_WID ( 2) + #define HUBS_CR_MBOX_CMD_HI_HUBS_RESERVED_MSK (0x00C00000) + #define HUBS_CR_MBOX_CMD_HI_HUBS_RESERVED_MAX (0x00000003) + #define HUBS_CR_MBOX_CMD_HI_HUBS_RESERVED_DEF (0x00000000) + #define HUBS_CR_MBOX_CMD_HI_HUBS_DMI_PRIV_OFF (24) + #define HUBS_CR_MBOX_CMD_HI_HUBS_DMI_PRIV_WID ( 1) + #define HUBS_CR_MBOX_CMD_HI_HUBS_DMI_PRIV_MSK (0x01000000) + #define HUBS_CR_MBOX_CMD_HI_HUBS_DMI_PRIV_MAX (0x00000001) + #define HUBS_CR_MBOX_CMD_HI_HUBS_DMI_PRIV_DEF (0x00000000) + #define HUBS_CR_MBOX_CMD_HI_HUBS_CHID_OFF (25) + #define HUBS_CR_MBOX_CMD_HI_HUBS_CHID_WID ( 4) + #define HUBS_CR_MBOX_CMD_HI_HUBS_CHID_MSK (0x1E000000) + #define HUBS_CR_MBOX_CMD_HI_HUBS_CHID_MAX (0x0000000F) + #define HUBS_CR_MBOX_CMD_HI_HUBS_CHID_DEF (0x00000000) + #define HUBS_CR_MBOX_CMD_HI_HUBS_RTYPE_OFF (29) + #define HUBS_CR_MBOX_CMD_HI_HUBS_RTYPE_WID ( 2) + #define HUBS_CR_MBOX_CMD_HI_HUBS_RTYPE_MSK (0x60000000) + #define HUBS_CR_MBOX_CMD_HI_HUBS_RTYPE_MAX (0x00000003) + #define HUBS_CR_MBOX_CMD_HI_HUBS_RTYPE_DEF (0x00000000) + #define HUBS_CR_MBOX_CMD_HI_HUBS_START_OFF (31) + #define HUBS_CR_MBOX_CMD_HI_HUBS_START_WID ( 1) + #define HUBS_CR_MBOX_CMD_HI_HUBS_START_MSK (0x80000000) + #define HUBS_CR_MBOX_CMD_HI_HUBS_START_MAX (0x00000001) + #define HUBS_CR_MBOX_CMD_HI_HUBS_START_DEF (0x00000000) + +#define HUBS_CR_MBOX_CFG_HUBS_REG (0x0000713C) + #define HUBS_CR_MBOX_CFG_HUBS_ENABLE_OFF ( 0) + #define HUBS_CR_MBOX_CFG_HUBS_ENABLE_WID ( 1) + #define HUBS_CR_MBOX_CFG_HUBS_ENABLE_MSK (0x00000001) + #define HUBS_CR_MBOX_CFG_HUBS_ENABLE_MAX (0x00000001) + #define HUBS_CR_MBOX_CFG_HUBS_ENABLE_DEF (0x00000000) + #define HUBS_CR_MBOX_CFG_HUBS_LOCK_IA_OFF ( 1) + #define HUBS_CR_MBOX_CFG_HUBS_LOCK_IA_WID ( 1) + #define HUBS_CR_MBOX_CFG_HUBS_LOCK_IA_MSK (0x00000002) + #define HUBS_CR_MBOX_CFG_HUBS_LOCK_IA_MAX (0x00000001) + #define HUBS_CR_MBOX_CFG_HUBS_LOCK_IA_DEF (0x00000001) + #define HUBS_CR_MBOX_CFG_HUBS_RESET_OFF ( 2) + #define HUBS_CR_MBOX_CFG_HUBS_RESET_WID ( 1) + #define HUBS_CR_MBOX_CFG_HUBS_RESET_MSK (0x00000004) + #define HUBS_CR_MBOX_CFG_HUBS_RESET_MAX (0x00000001) + #define HUBS_CR_MBOX_CFG_HUBS_RESET_DEF (0x00000000) + #define HUBS_CR_MBOX_CFG_HUBS_BLK_CYCLES_OFF ( 3) + #define HUBS_CR_MBOX_CFG_HUBS_BLK_CYCLES_WID ( 6) + #define HUBS_CR_MBOX_CFG_HUBS_BLK_CYCLES_MSK (0x000001F8) + #define HUBS_CR_MBOX_CFG_HUBS_BLK_CYCLES_MAX (0x0000003F) + #define HUBS_CR_MBOX_CFG_HUBS_BLK_CYCLES_DEF (0x00000000) + #define HUBS_CR_MBOX_CFG_HUBS_WR_DWORD_SEL_OFF ( 9) + #define HUBS_CR_MBOX_CFG_HUBS_WR_DWORD_SEL_WID ( 4) + #define HUBS_CR_MBOX_CFG_HUBS_WR_DWORD_SEL_MSK (0x00001E00) + #define HUBS_CR_MBOX_CFG_HUBS_WR_DWORD_SEL_MAX (0x0000000F) + #define HUBS_CR_MBOX_CFG_HUBS_WR_DWORD_SEL_DEF (0x00000000) + #define HUBS_CR_MBOX_CFG_HUBS_RD_DWORD_SEL_OFF (13) + #define HUBS_CR_MBOX_CFG_HUBS_RD_DWORD_SEL_WID ( 4) + #define HUBS_CR_MBOX_CFG_HUBS_RD_DWORD_SEL_MSK (0x0001E000) + #define HUBS_CR_MBOX_CFG_HUBS_RD_DWORD_SEL_MAX (0x0000000F) + #define HUBS_CR_MBOX_CFG_HUBS_RD_DWORD_SEL_DEF (0x00000000) + #define HUBS_CR_MBOX_CFG_HUBS_RPT_CMD_CNT_OFF (17) + #define HUBS_CR_MBOX_CFG_HUBS_RPT_CMD_CNT_WID ( 6) + #define HUBS_CR_MBOX_CFG_HUBS_RPT_CMD_CNT_MSK (0x007E0000) + #define HUBS_CR_MBOX_CFG_HUBS_RPT_CMD_CNT_MAX (0x0000003F) + #define HUBS_CR_MBOX_CFG_HUBS_RPT_CMD_CNT_DEF (0x00000000) + #define HUBS_CR_MBOX_CFG_HUBS_RPT_NXT_ADDR_OFF (23) + #define HUBS_CR_MBOX_CFG_HUBS_RPT_NXT_ADDR_WID ( 1) + #define HUBS_CR_MBOX_CFG_HUBS_RPT_NXT_ADDR_MSK (0x00800000) + #define HUBS_CR_MBOX_CFG_HUBS_RPT_NXT_ADDR_MAX (0x00000001) + #define HUBS_CR_MBOX_CFG_HUBS_RPT_NXT_ADDR_DEF (0x00000000) + #define HUBS_CR_MBOX_CFG_HUBS_RPT_NXT_PAGE_OFF (24) + #define HUBS_CR_MBOX_CFG_HUBS_RPT_NXT_PAGE_WID ( 1) + #define HUBS_CR_MBOX_CFG_HUBS_RPT_NXT_PAGE_MSK (0x01000000) + #define HUBS_CR_MBOX_CFG_HUBS_RPT_NXT_PAGE_MAX (0x00000001) + #define HUBS_CR_MBOX_CFG_HUBS_RPT_NXT_PAGE_DEF (0x00000000) + #define HUBS_CR_MBOX_CFG_HUBS_DIS_CMP_INV_OFF (25) + #define HUBS_CR_MBOX_CFG_HUBS_DIS_CMP_INV_WID ( 1) + #define HUBS_CR_MBOX_CFG_HUBS_DIS_CMP_INV_MSK (0x02000000) + #define HUBS_CR_MBOX_CFG_HUBS_DIS_CMP_INV_MAX (0x00000001) + #define HUBS_CR_MBOX_CFG_HUBS_DIS_CMP_INV_DEF (0x00000000) + #define HUBS_CR_MBOX_CFG_HUBS_FSM_STATE_OFF (26) + #define HUBS_CR_MBOX_CFG_HUBS_FSM_STATE_WID ( 4) + #define HUBS_CR_MBOX_CFG_HUBS_FSM_STATE_MSK (0x3C000000) + #define HUBS_CR_MBOX_CFG_HUBS_FSM_STATE_MAX (0x0000000F) + #define HUBS_CR_MBOX_CFG_HUBS_FSM_STATE_DEF (0x00000000) + #define HUBS_CR_MBOX_CFG_HUBS_P2P_ALL_OFF (30) + #define HUBS_CR_MBOX_CFG_HUBS_P2P_ALL_WID ( 1) + #define HUBS_CR_MBOX_CFG_HUBS_P2P_ALL_MSK (0x40000000) + #define HUBS_CR_MBOX_CFG_HUBS_P2P_ALL_MAX (0x00000001) + #define HUBS_CR_MBOX_CFG_HUBS_P2P_ALL_DEF (0x00000000) + #define HUBS_CR_MBOX_CFG_HUBS_SPARE_OFF (31) + #define HUBS_CR_MBOX_CFG_HUBS_SPARE_WID ( 1) + #define HUBS_CR_MBOX_CFG_HUBS_SPARE_MSK (0x80000000) + #define HUBS_CR_MBOX_CFG_HUBS_SPARE_MAX (0x00000001) + #define HUBS_CR_MBOX_CFG_HUBS_SPARE_DEF (0x00000000) + +#define HUBS_CR_MBOX_STATUS_HUBS_REG (0x00007140) + #define HUBS_CR_MBOX_STATUS_HUBS_FSM_STATE_OFF ( 0) + #define HUBS_CR_MBOX_STATUS_HUBS_FSM_STATE_WID ( 4) + #define HUBS_CR_MBOX_STATUS_HUBS_FSM_STATE_MSK (0x0000000F) + #define HUBS_CR_MBOX_STATUS_HUBS_FSM_STATE_MAX (0x0000000F) + #define HUBS_CR_MBOX_STATUS_HUBS_FSM_STATE_DEF (0x00000000) + #define HUBS_CR_MBOX_STATUS_HUBS_RPT_CMD_CNT_OFF ( 4) + #define HUBS_CR_MBOX_STATUS_HUBS_RPT_CMD_CNT_WID ( 6) + #define HUBS_CR_MBOX_STATUS_HUBS_RPT_CMD_CNT_MSK (0x000003F0) + #define HUBS_CR_MBOX_STATUS_HUBS_RPT_CMD_CNT_MAX (0x0000003F) + #define HUBS_CR_MBOX_STATUS_HUBS_RPT_CMD_CNT_DEF (0x00000000) + #define HUBS_CR_MBOX_STATUS_HUBS_OPCODE_OFF (10) + #define HUBS_CR_MBOX_STATUS_HUBS_OPCODE_WID ( 7) + #define HUBS_CR_MBOX_STATUS_HUBS_OPCODE_MSK (0x0001FC00) + #define HUBS_CR_MBOX_STATUS_HUBS_OPCODE_MAX (0x0000007F) + #define HUBS_CR_MBOX_STATUS_HUBS_OPCODE_DEF (0x00000000) + #define HUBS_CR_MBOX_STATUS_HUBS_WR_DWORD_SEL_OFF (17) + #define HUBS_CR_MBOX_STATUS_HUBS_WR_DWORD_SEL_WID ( 4) + #define HUBS_CR_MBOX_STATUS_HUBS_WR_DWORD_SEL_MSK (0x001E0000) + #define HUBS_CR_MBOX_STATUS_HUBS_WR_DWORD_SEL_MAX (0x0000000F) + #define HUBS_CR_MBOX_STATUS_HUBS_WR_DWORD_SEL_DEF (0x00000000) + #define HUBS_CR_MBOX_STATUS_HUBS_RD_DWORD_SEL_OFF (21) + #define HUBS_CR_MBOX_STATUS_HUBS_RD_DWORD_SEL_WID ( 4) + #define HUBS_CR_MBOX_STATUS_HUBS_RD_DWORD_SEL_MSK (0x01E00000) + #define HUBS_CR_MBOX_STATUS_HUBS_RD_DWORD_SEL_MAX (0x0000000F) + #define HUBS_CR_MBOX_STATUS_HUBS_RD_DWORD_SEL_DEF (0x00000000) + #define HUBS_CR_MBOX_STATUS_HUBS_P2P_RD_UP_OFF (25) + #define HUBS_CR_MBOX_STATUS_HUBS_P2P_RD_UP_WID ( 1) + #define HUBS_CR_MBOX_STATUS_HUBS_P2P_RD_UP_MSK (0x02000000) + #define HUBS_CR_MBOX_STATUS_HUBS_P2P_RD_UP_MAX (0x00000001) + #define HUBS_CR_MBOX_STATUS_HUBS_P2P_RD_UP_DEF (0x00000000) + #define HUBS_CR_MBOX_STATUS_HUBS_P2P_RD_DN_OFF (26) + #define HUBS_CR_MBOX_STATUS_HUBS_P2P_RD_DN_WID ( 1) + #define HUBS_CR_MBOX_STATUS_HUBS_P2P_RD_DN_MSK (0x04000000) + #define HUBS_CR_MBOX_STATUS_HUBS_P2P_RD_DN_MAX (0x00000001) + #define HUBS_CR_MBOX_STATUS_HUBS_P2P_RD_DN_DEF (0x00000000) + #define HUBS_CR_MBOX_STATUS_HUBS_SPARE_OFF (27) + #define HUBS_CR_MBOX_STATUS_HUBS_SPARE_WID ( 5) + #define HUBS_CR_MBOX_STATUS_HUBS_SPARE_MSK (0xF8000000) + #define HUBS_CR_MBOX_STATUS_HUBS_SPARE_MAX (0x0000001F) + #define HUBS_CR_MBOX_STATUS_HUBS_SPARE_DEF (0x00000000) + +#define HUBS_CR_HUB0_BLOCK_UP_HUBS_REG (0x00007144) + #define HUBS_CR_HUB0_BLOCK_UP_HUBS_XTM_CHID_OFF ( 0) + #define HUBS_CR_HUB0_BLOCK_UP_HUBS_XTM_CHID_WID ( 9) + #define HUBS_CR_HUB0_BLOCK_UP_HUBS_XTM_CHID_MSK (0x000001FF) + #define HUBS_CR_HUB0_BLOCK_UP_HUBS_XTM_CHID_MAX (0x000001FF) + #define HUBS_CR_HUB0_BLOCK_UP_HUBS_XTM_CHID_DEF (0x00000000) + #define HUBS_CR_HUB0_BLOCK_UP_HUBS_NP_OFF ( 9) + #define HUBS_CR_HUB0_BLOCK_UP_HUBS_NP_WID ( 1) + #define HUBS_CR_HUB0_BLOCK_UP_HUBS_NP_MSK (0x00000200) + #define HUBS_CR_HUB0_BLOCK_UP_HUBS_NP_MAX (0x00000001) + #define HUBS_CR_HUB0_BLOCK_UP_HUBS_NP_DEF (0x00000000) + #define HUBS_CR_HUB0_BLOCK_UP_HUBS_PC_OFF (10) + #define HUBS_CR_HUB0_BLOCK_UP_HUBS_PC_WID ( 1) + #define HUBS_CR_HUB0_BLOCK_UP_HUBS_PC_MSK (0x00000400) + #define HUBS_CR_HUB0_BLOCK_UP_HUBS_PC_MAX (0x00000001) + #define HUBS_CR_HUB0_BLOCK_UP_HUBS_PC_DEF (0x00000000) + +#define MPRDRTRN_CR_CRDTCTL0_IMPH_REG (0x00007400) + #define MPRDRTRN_CR_CRDTCTL0_IMPH_DMIVC0_PMIN_OFF ( 0) + #define MPRDRTRN_CR_CRDTCTL0_IMPH_DMIVC0_PMIN_WID ( 3) + #define MPRDRTRN_CR_CRDTCTL0_IMPH_DMIVC0_PMIN_MSK (0x00000007) + #define MPRDRTRN_CR_CRDTCTL0_IMPH_DMIVC0_PMIN_MAX (0x00000007) + #define MPRDRTRN_CR_CRDTCTL0_IMPH_P10VC0_PMIN_OFF ( 3) + #define MPRDRTRN_CR_CRDTCTL0_IMPH_P10VC0_PMIN_WID ( 3) + #define MPRDRTRN_CR_CRDTCTL0_IMPH_P10VC0_PMIN_MSK (0x00000038) + #define MPRDRTRN_CR_CRDTCTL0_IMPH_P10VC0_PMIN_MAX (0x00000007) + #define MPRDRTRN_CR_CRDTCTL0_IMPH_P11VC0_PMIN_OFF ( 6) + #define MPRDRTRN_CR_CRDTCTL0_IMPH_P11VC0_PMIN_WID ( 3) + #define MPRDRTRN_CR_CRDTCTL0_IMPH_P11VC0_PMIN_MSK (0x000001C0) + #define MPRDRTRN_CR_CRDTCTL0_IMPH_P11VC0_PMIN_MAX (0x00000007) + #define MPRDRTRN_CR_CRDTCTL0_IMPH_P12VC0_PMIN_OFF ( 9) + #define MPRDRTRN_CR_CRDTCTL0_IMPH_P12VC0_PMIN_WID ( 3) + #define MPRDRTRN_CR_CRDTCTL0_IMPH_P12VC0_PMIN_MSK (0x00000E00) + #define MPRDRTRN_CR_CRDTCTL0_IMPH_P12VC0_PMIN_MAX (0x00000007) + #define MPRDRTRN_CR_CRDTCTL0_IMPH_DEVC0_PMIN_OFF (12) + #define MPRDRTRN_CR_CRDTCTL0_IMPH_DEVC0_PMIN_WID ( 3) + #define MPRDRTRN_CR_CRDTCTL0_IMPH_DEVC0_PMIN_MSK (0x00007000) + #define MPRDRTRN_CR_CRDTCTL0_IMPH_DEVC0_PMIN_MAX (0x00000007) + #define MPRDRTRN_CR_CRDTCTL0_IMPH_DMIVCP_PMIN_OFF (15) + #define MPRDRTRN_CR_CRDTCTL0_IMPH_DMIVCP_PMIN_WID ( 3) + #define MPRDRTRN_CR_CRDTCTL0_IMPH_DMIVCP_PMIN_MSK (0x00038000) + #define MPRDRTRN_CR_CRDTCTL0_IMPH_DMIVCP_PMIN_MAX (0x00000007) + #define MPRDRTRN_CR_CRDTCTL0_IMPH_DMIVCM_PMIN_OFF (18) + #define MPRDRTRN_CR_CRDTCTL0_IMPH_DMIVCM_PMIN_WID ( 3) + #define MPRDRTRN_CR_CRDTCTL0_IMPH_DMIVCM_PMIN_MSK (0x001C0000) + #define MPRDRTRN_CR_CRDTCTL0_IMPH_DMIVCM_PMIN_MAX (0x00000007) + #define MPRDRTRN_CR_CRDTCTL0_IMPH_DMIVC1_PMIN_OFF (21) + #define MPRDRTRN_CR_CRDTCTL0_IMPH_DMIVC1_PMIN_WID ( 3) + #define MPRDRTRN_CR_CRDTCTL0_IMPH_DMIVC1_PMIN_MSK (0x00E00000) + #define MPRDRTRN_CR_CRDTCTL0_IMPH_DMIVC1_PMIN_MAX (0x00000007) + +#define MPRDRTRN_CR_CRDTCTL1_IMPH_REG (0x00007404) + #define MPRDRTRN_CR_CRDTCTL1_IMPH_DMIVC0_NPMIN_OFF ( 0) + #define MPRDRTRN_CR_CRDTCTL1_IMPH_DMIVC0_NPMIN_WID ( 3) + #define MPRDRTRN_CR_CRDTCTL1_IMPH_DMIVC0_NPMIN_MSK (0x00000007) + #define MPRDRTRN_CR_CRDTCTL1_IMPH_DMIVC0_NPMIN_MAX (0x00000007) + #define MPRDRTRN_CR_CRDTCTL1_IMPH_P10VC0_NPMIN_OFF ( 3) + #define MPRDRTRN_CR_CRDTCTL1_IMPH_P10VC0_NPMIN_WID ( 3) + #define MPRDRTRN_CR_CRDTCTL1_IMPH_P10VC0_NPMIN_MSK (0x00000038) + #define MPRDRTRN_CR_CRDTCTL1_IMPH_P10VC0_NPMIN_MAX (0x00000007) + #define MPRDRTRN_CR_CRDTCTL1_IMPH_P11VC0_NPMIN_OFF ( 6) + #define MPRDRTRN_CR_CRDTCTL1_IMPH_P11VC0_NPMIN_WID ( 3) + #define MPRDRTRN_CR_CRDTCTL1_IMPH_P11VC0_NPMIN_MSK (0x000001C0) + #define MPRDRTRN_CR_CRDTCTL1_IMPH_P11VC0_NPMIN_MAX (0x00000007) + #define MPRDRTRN_CR_CRDTCTL1_IMPH_P12VC0_NPMIN_OFF ( 9) + #define MPRDRTRN_CR_CRDTCTL1_IMPH_P12VC0_NPMIN_WID ( 3) + #define MPRDRTRN_CR_CRDTCTL1_IMPH_P12VC0_NPMIN_MSK (0x00000E00) + #define MPRDRTRN_CR_CRDTCTL1_IMPH_P12VC0_NPMIN_MAX (0x00000007) + #define MPRDRTRN_CR_CRDTCTL1_IMPH_DEVC0_NPMIN_OFF (12) + #define MPRDRTRN_CR_CRDTCTL1_IMPH_DEVC0_NPMIN_WID ( 3) + #define MPRDRTRN_CR_CRDTCTL1_IMPH_DEVC0_NPMIN_MSK (0x00007000) + #define MPRDRTRN_CR_CRDTCTL1_IMPH_DEVC0_NPMIN_MAX (0x00000007) + #define MPRDRTRN_CR_CRDTCTL1_IMPH_DMIVCP_NPMIN_OFF (15) + #define MPRDRTRN_CR_CRDTCTL1_IMPH_DMIVCP_NPMIN_WID ( 3) + #define MPRDRTRN_CR_CRDTCTL1_IMPH_DMIVCP_NPMIN_MSK (0x00038000) + #define MPRDRTRN_CR_CRDTCTL1_IMPH_DMIVCP_NPMIN_MAX (0x00000007) + #define MPRDRTRN_CR_CRDTCTL1_IMPH_DMIVCM_NPMIN_OFF (18) + #define MPRDRTRN_CR_CRDTCTL1_IMPH_DMIVCM_NPMIN_WID ( 3) + #define MPRDRTRN_CR_CRDTCTL1_IMPH_DMIVCM_NPMIN_MSK (0x001C0000) + #define MPRDRTRN_CR_CRDTCTL1_IMPH_DMIVCM_NPMIN_MAX (0x00000007) + #define MPRDRTRN_CR_CRDTCTL1_IMPH_DMIVC1_NPMIN_OFF (21) + #define MPRDRTRN_CR_CRDTCTL1_IMPH_DMIVC1_NPMIN_WID ( 3) + #define MPRDRTRN_CR_CRDTCTL1_IMPH_DMIVC1_NPMIN_MSK (0x00E00000) + #define MPRDRTRN_CR_CRDTCTL1_IMPH_DMIVC1_NPMIN_MAX (0x00000007) + +#define MPRDRTRN_CR_CRDTCTL2_IMPH_REG (0x00007408) + #define MPRDRTRN_CR_CRDTCTL2_IMPH_DMIVC0_RRMIN_OFF ( 0) + #define MPRDRTRN_CR_CRDTCTL2_IMPH_DMIVC0_RRMIN_WID ( 3) + #define MPRDRTRN_CR_CRDTCTL2_IMPH_DMIVC0_RRMIN_MSK (0x00000007) + #define MPRDRTRN_CR_CRDTCTL2_IMPH_DMIVC0_RRMIN_MAX (0x00000007) + #define MPRDRTRN_CR_CRDTCTL2_IMPH_P10VC0_RRMIN_OFF ( 3) + #define MPRDRTRN_CR_CRDTCTL2_IMPH_P10VC0_RRMIN_WID ( 3) + #define MPRDRTRN_CR_CRDTCTL2_IMPH_P10VC0_RRMIN_MSK (0x00000038) + #define MPRDRTRN_CR_CRDTCTL2_IMPH_P10VC0_RRMIN_MAX (0x00000007) + #define MPRDRTRN_CR_CRDTCTL2_IMPH_P11VC0_RRMIN_OFF ( 6) + #define MPRDRTRN_CR_CRDTCTL2_IMPH_P11VC0_RRMIN_WID ( 3) + #define MPRDRTRN_CR_CRDTCTL2_IMPH_P11VC0_RRMIN_MSK (0x000001C0) + #define MPRDRTRN_CR_CRDTCTL2_IMPH_P11VC0_RRMIN_MAX (0x00000007) + #define MPRDRTRN_CR_CRDTCTL2_IMPH_P12VC0_RRMIN_OFF ( 9) + #define MPRDRTRN_CR_CRDTCTL2_IMPH_P12VC0_RRMIN_WID ( 3) + #define MPRDRTRN_CR_CRDTCTL2_IMPH_P12VC0_RRMIN_MSK (0x00000E00) + #define MPRDRTRN_CR_CRDTCTL2_IMPH_P12VC0_RRMIN_MAX (0x00000007) + #define MPRDRTRN_CR_CRDTCTL2_IMPH_DEVC0_RRMIN_OFF (12) + #define MPRDRTRN_CR_CRDTCTL2_IMPH_DEVC0_RRMIN_WID ( 3) + #define MPRDRTRN_CR_CRDTCTL2_IMPH_DEVC0_RRMIN_MSK (0x00007000) + #define MPRDRTRN_CR_CRDTCTL2_IMPH_DEVC0_RRMIN_MAX (0x00000007) + #define MPRDRTRN_CR_CRDTCTL2_IMPH_DMIVCP_RRMIN_OFF (15) + #define MPRDRTRN_CR_CRDTCTL2_IMPH_DMIVCP_RRMIN_WID ( 3) + #define MPRDRTRN_CR_CRDTCTL2_IMPH_DMIVCP_RRMIN_MSK (0x00038000) + #define MPRDRTRN_CR_CRDTCTL2_IMPH_DMIVCP_RRMIN_MAX (0x00000007) + #define MPRDRTRN_CR_CRDTCTL2_IMPH_DMIVCM_RRMIN_OFF (18) + #define MPRDRTRN_CR_CRDTCTL2_IMPH_DMIVCM_RRMIN_WID ( 3) + #define MPRDRTRN_CR_CRDTCTL2_IMPH_DMIVCM_RRMIN_MSK (0x001C0000) + #define MPRDRTRN_CR_CRDTCTL2_IMPH_DMIVCM_RRMIN_MAX (0x00000007) + #define MPRDRTRN_CR_CRDTCTL2_IMPH_DMIVC1_RRMIN_OFF (21) + #define MPRDRTRN_CR_CRDTCTL2_IMPH_DMIVC1_RRMIN_WID ( 3) + #define MPRDRTRN_CR_CRDTCTL2_IMPH_DMIVC1_RRMIN_MSK (0x00E00000) + #define MPRDRTRN_CR_CRDTCTL2_IMPH_DMIVC1_RRMIN_MAX (0x00000007) + #define MPRDRTRN_CR_CRDTCTL2_IMPH_DEVC1_RRMIN_OFF (24) + #define MPRDRTRN_CR_CRDTCTL2_IMPH_DEVC1_RRMIN_WID ( 6) + #define MPRDRTRN_CR_CRDTCTL2_IMPH_DEVC1_RRMIN_MSK (0x3F000000) + #define MPRDRTRN_CR_CRDTCTL2_IMPH_DEVC1_RRMIN_MAX (0x0000003F) + +#define MPRDRTRN_CR_CRDTCTL3_IMPH_REG (0x0000740C) + #define MPRDRTRN_CR_CRDTCTL3_IMPH_IOTRK_SHRD_OFF ( 0) + #define MPRDRTRN_CR_CRDTCTL3_IMPH_IOTRK_SHRD_WID ( 6) + #define MPRDRTRN_CR_CRDTCTL3_IMPH_IOTRK_SHRD_MSK (0x0000003F) + #define MPRDRTRN_CR_CRDTCTL3_IMPH_IOTRK_SHRD_MAX (0x0000003F) + #define MPRDRTRN_CR_CRDTCTL3_IMPH_RRTRK_SHRD_OFF ( 6) + #define MPRDRTRN_CR_CRDTCTL3_IMPH_RRTRK_SHRD_WID ( 7) + #define MPRDRTRN_CR_CRDTCTL3_IMPH_RRTRK_SHRD_MSK (0x00001FC0) + #define MPRDRTRN_CR_CRDTCTL3_IMPH_RRTRK_SHRD_MAX (0x0000007F) + +#define MPRDRTRN_CR_CRDTCTL4_IMPH_REG (0x00007410) + #define MPRDRTRN_CR_CRDTCTL4_IMPH_DMIVC0_PMAX_OFF ( 0) + #define MPRDRTRN_CR_CRDTCTL4_IMPH_DMIVC0_PMAX_WID ( 5) + #define MPRDRTRN_CR_CRDTCTL4_IMPH_DMIVC0_PMAX_MSK (0x0000001F) + #define MPRDRTRN_CR_CRDTCTL4_IMPH_DMIVC0_PMAX_MAX (0x0000001F) + #define MPRDRTRN_CR_CRDTCTL4_IMPH_P10VC0_PMAX_OFF ( 5) + #define MPRDRTRN_CR_CRDTCTL4_IMPH_P10VC0_PMAX_WID ( 5) + #define MPRDRTRN_CR_CRDTCTL4_IMPH_P10VC0_PMAX_MSK (0x000003E0) + #define MPRDRTRN_CR_CRDTCTL4_IMPH_P10VC0_PMAX_MAX (0x0000001F) + #define MPRDRTRN_CR_CRDTCTL4_IMPH_P11VC0_PMAX_OFF (10) + #define MPRDRTRN_CR_CRDTCTL4_IMPH_P11VC0_PMAX_WID ( 5) + #define MPRDRTRN_CR_CRDTCTL4_IMPH_P11VC0_PMAX_MSK (0x00007C00) + #define MPRDRTRN_CR_CRDTCTL4_IMPH_P11VC0_PMAX_MAX (0x0000001F) + #define MPRDRTRN_CR_CRDTCTL4_IMPH_P12VC0_PMAX_OFF (15) + #define MPRDRTRN_CR_CRDTCTL4_IMPH_P12VC0_PMAX_WID ( 5) + #define MPRDRTRN_CR_CRDTCTL4_IMPH_P12VC0_PMAX_MSK (0x000F8000) + #define MPRDRTRN_CR_CRDTCTL4_IMPH_P12VC0_PMAX_MAX (0x0000001F) + #define MPRDRTRN_CR_CRDTCTL4_IMPH_DEVC0_PMAX_OFF (20) + #define MPRDRTRN_CR_CRDTCTL4_IMPH_DEVC0_PMAX_WID ( 5) + #define MPRDRTRN_CR_CRDTCTL4_IMPH_DEVC0_PMAX_MSK (0x01F00000) + #define MPRDRTRN_CR_CRDTCTL4_IMPH_DEVC0_PMAX_MAX (0x0000001F) + +#define MPRDRTRN_CR_CRDTCTL5_IMPH_REG (0x00007414) + #define MPRDRTRN_CR_CRDTCTL5_IMPH_DMIVCP_PMAX_OFF ( 0) + #define MPRDRTRN_CR_CRDTCTL5_IMPH_DMIVCP_PMAX_WID ( 5) + #define MPRDRTRN_CR_CRDTCTL5_IMPH_DMIVCP_PMAX_MSK (0x0000001F) + #define MPRDRTRN_CR_CRDTCTL5_IMPH_DMIVCP_PMAX_MAX (0x0000001F) + #define MPRDRTRN_CR_CRDTCTL5_IMPH_DMIVCM_PMAX_OFF ( 5) + #define MPRDRTRN_CR_CRDTCTL5_IMPH_DMIVCM_PMAX_WID ( 5) + #define MPRDRTRN_CR_CRDTCTL5_IMPH_DMIVCM_PMAX_MSK (0x000003E0) + #define MPRDRTRN_CR_CRDTCTL5_IMPH_DMIVCM_PMAX_MAX (0x0000001F) + #define MPRDRTRN_CR_CRDTCTL5_IMPH_DMIVC1_PMAX_OFF (10) + #define MPRDRTRN_CR_CRDTCTL5_IMPH_DMIVC1_PMAX_WID ( 5) + #define MPRDRTRN_CR_CRDTCTL5_IMPH_DMIVC1_PMAX_MSK (0x00007C00) + #define MPRDRTRN_CR_CRDTCTL5_IMPH_DMIVC1_PMAX_MAX (0x0000001F) + +#define MPRDRTRN_CR_CRDTCTL6_IMPH_REG (0x00007418) + #define MPRDRTRN_CR_CRDTCTL6_IMPH_DMIVC0_NPMAX_OFF ( 0) + #define MPRDRTRN_CR_CRDTCTL6_IMPH_DMIVC0_NPMAX_WID ( 5) + #define MPRDRTRN_CR_CRDTCTL6_IMPH_DMIVC0_NPMAX_MSK (0x0000001F) + #define MPRDRTRN_CR_CRDTCTL6_IMPH_DMIVC0_NPMAX_MAX (0x0000001F) + #define MPRDRTRN_CR_CRDTCTL6_IMPH_P10VC0_NPMAX_OFF ( 5) + #define MPRDRTRN_CR_CRDTCTL6_IMPH_P10VC0_NPMAX_WID ( 5) + #define MPRDRTRN_CR_CRDTCTL6_IMPH_P10VC0_NPMAX_MSK (0x000003E0) + #define MPRDRTRN_CR_CRDTCTL6_IMPH_P10VC0_NPMAX_MAX (0x0000001F) + #define MPRDRTRN_CR_CRDTCTL6_IMPH_P11VC0_NPMAX_OFF (10) + #define MPRDRTRN_CR_CRDTCTL6_IMPH_P11VC0_NPMAX_WID ( 5) + #define MPRDRTRN_CR_CRDTCTL6_IMPH_P11VC0_NPMAX_MSK (0x00007C00) + #define MPRDRTRN_CR_CRDTCTL6_IMPH_P11VC0_NPMAX_MAX (0x0000001F) + #define MPRDRTRN_CR_CRDTCTL6_IMPH_P12VC0_NPMAX_OFF (15) + #define MPRDRTRN_CR_CRDTCTL6_IMPH_P12VC0_NPMAX_WID ( 5) + #define MPRDRTRN_CR_CRDTCTL6_IMPH_P12VC0_NPMAX_MSK (0x000F8000) + #define MPRDRTRN_CR_CRDTCTL6_IMPH_P12VC0_NPMAX_MAX (0x0000001F) + #define MPRDRTRN_CR_CRDTCTL6_IMPH_DEVC0_NPMAX_OFF (20) + #define MPRDRTRN_CR_CRDTCTL6_IMPH_DEVC0_NPMAX_WID ( 5) + #define MPRDRTRN_CR_CRDTCTL6_IMPH_DEVC0_NPMAX_MSK (0x01F00000) + #define MPRDRTRN_CR_CRDTCTL6_IMPH_DEVC0_NPMAX_MAX (0x0000001F) + +#define MPRDRTRN_CR_CRDTCTL7_IMPH_REG (0x0000741C) + #define MPRDRTRN_CR_CRDTCTL7_IMPH_DMIVCP_NPMAX_OFF ( 0) + #define MPRDRTRN_CR_CRDTCTL7_IMPH_DMIVCP_NPMAX_WID ( 5) + #define MPRDRTRN_CR_CRDTCTL7_IMPH_DMIVCP_NPMAX_MSK (0x0000001F) + #define MPRDRTRN_CR_CRDTCTL7_IMPH_DMIVCP_NPMAX_MAX (0x0000001F) + #define MPRDRTRN_CR_CRDTCTL7_IMPH_DMIVCM_NPMAX_OFF ( 5) + #define MPRDRTRN_CR_CRDTCTL7_IMPH_DMIVCM_NPMAX_WID ( 5) + #define MPRDRTRN_CR_CRDTCTL7_IMPH_DMIVCM_NPMAX_MSK (0x000003E0) + #define MPRDRTRN_CR_CRDTCTL7_IMPH_DMIVCM_NPMAX_MAX (0x0000001F) + #define MPRDRTRN_CR_CRDTCTL7_IMPH_DMIVC1_NPMAX_OFF (10) + #define MPRDRTRN_CR_CRDTCTL7_IMPH_DMIVC1_NPMAX_WID ( 5) + #define MPRDRTRN_CR_CRDTCTL7_IMPH_DMIVC1_NPMAX_MSK (0x00007C00) + #define MPRDRTRN_CR_CRDTCTL7_IMPH_DMIVC1_NPMAX_MAX (0x0000001F) + +#define MPRDRTRN_CR_VISA_CTL_MPIORDTRKS_IMPH_REG (0x00007420) + #define MPRDRTRN_CR_VISA_CTL_MPIORDTRKS_IMPH_DATA_OFF ( 0) + #define MPRDRTRN_CR_VISA_CTL_MPIORDTRKS_IMPH_DATA_WID (18) + #define MPRDRTRN_CR_VISA_CTL_MPIORDTRKS_IMPH_DATA_MSK (0x0003FFFF) + #define MPRDRTRN_CR_VISA_CTL_MPIORDTRKS_IMPH_DATA_MAX (0x0003FFFF) + #define MPRDRTRN_CR_VISA_CTL_MPIORDTRKS_IMPH_DATA_DEF (0x00000000) + #define MPRDRTRN_CR_VISA_CTL_MPIORDTRKS_IMPH_VORANGE_OFF (31) + #define MPRDRTRN_CR_VISA_CTL_MPIORDTRKS_IMPH_VORANGE_WID ( 1) + #define MPRDRTRN_CR_VISA_CTL_MPIORDTRKS_IMPH_VORANGE_MSK (0x80000000) + #define MPRDRTRN_CR_VISA_CTL_MPIORDTRKS_IMPH_VORANGE_MAX (0x00000001) + #define MPRDRTRN_CR_VISA_CTL_MPIORDTRKS_IMPH_VORANGE_DEF (0x00000000) + +#define MPRDRTRN_CR_VISA_XBAR_MPIORDTRKS_IMPH_REG (0x00007424) + #define MPRDRTRN_CR_VISA_XBAR_MPIORDTRKS_IMPH_DATA_OFF ( 0) + #define MPRDRTRN_CR_VISA_XBAR_MPIORDTRKS_IMPH_DATA_WID (32) + #define MPRDRTRN_CR_VISA_XBAR_MPIORDTRKS_IMPH_DATA_MSK (0xFFFFFFFF) + #define MPRDRTRN_CR_VISA_XBAR_MPIORDTRKS_IMPH_DATA_MAX (0xFFFFFFFF) + #define MPRDRTRN_CR_VISA_XBAR_MPIORDTRKS_IMPH_DATA_DEF (0x76543210) + +#define MPRDRTRN_CR_VISA_CTL_MPIOTRKS_IMPH_REG (0x00007428) + #define MPRDRTRN_CR_VISA_CTL_MPIOTRKS_IMPH_DATA_OFF ( 0) + #define MPRDRTRN_CR_VISA_CTL_MPIOTRKS_IMPH_DATA_WID (18) + #define MPRDRTRN_CR_VISA_CTL_MPIOTRKS_IMPH_DATA_MSK (0x0003FFFF) + #define MPRDRTRN_CR_VISA_CTL_MPIOTRKS_IMPH_DATA_MAX (0x0003FFFF) + #define MPRDRTRN_CR_VISA_CTL_MPIOTRKS_IMPH_DATA_DEF (0x00000000) + #define MPRDRTRN_CR_VISA_CTL_MPIOTRKS_IMPH_VORANGE_OFF (31) + #define MPRDRTRN_CR_VISA_CTL_MPIOTRKS_IMPH_VORANGE_WID ( 1) + #define MPRDRTRN_CR_VISA_CTL_MPIOTRKS_IMPH_VORANGE_MSK (0x80000000) + #define MPRDRTRN_CR_VISA_CTL_MPIOTRKS_IMPH_VORANGE_MAX (0x00000001) + #define MPRDRTRN_CR_VISA_CTL_MPIOTRKS_IMPH_VORANGE_DEF (0x00000000) + +#define MPRDRTRN_CR_PRIMDN_MASK1_IMPH_REG (0x00007430) + #define MPRDRTRN_CR_PRIMDN_MASK1_IMPH_VC_OFF ( 0) + #define MPRDRTRN_CR_PRIMDN_MASK1_IMPH_VC_WID ( 4) + #define MPRDRTRN_CR_PRIMDN_MASK1_IMPH_VC_MSK (0x0000000F) + #define MPRDRTRN_CR_PRIMDN_MASK1_IMPH_VC_MAX (0x0000000F) + #define MPRDRTRN_CR_PRIMDN_MASK1_IMPH_VC_DEF (0x00000000) + #define MPRDRTRN_CR_PRIMDN_MASK1_IMPH_FMT_CMDTYPE_OFF ( 4) + #define MPRDRTRN_CR_PRIMDN_MASK1_IMPH_FMT_CMDTYPE_WID ( 6) + #define MPRDRTRN_CR_PRIMDN_MASK1_IMPH_FMT_CMDTYPE_MSK (0x000003F0) + #define MPRDRTRN_CR_PRIMDN_MASK1_IMPH_FMT_CMDTYPE_MAX (0x0000003F) + #define MPRDRTRN_CR_PRIMDN_MASK1_IMPH_FMT_CMDTYPE_DEF (0x00000000) + #define MPRDRTRN_CR_PRIMDN_MASK1_IMPH_TC_OFF (10) + #define MPRDRTRN_CR_PRIMDN_MASK1_IMPH_TC_WID ( 4) + #define MPRDRTRN_CR_PRIMDN_MASK1_IMPH_TC_MSK (0x00003C00) + #define MPRDRTRN_CR_PRIMDN_MASK1_IMPH_TC_MAX (0x0000000F) + #define MPRDRTRN_CR_PRIMDN_MASK1_IMPH_TC_DEF (0x00000000) + #define MPRDRTRN_CR_PRIMDN_MASK1_IMPH_NS_OFF (14) + #define MPRDRTRN_CR_PRIMDN_MASK1_IMPH_NS_WID ( 1) + #define MPRDRTRN_CR_PRIMDN_MASK1_IMPH_NS_MSK (0x00004000) + #define MPRDRTRN_CR_PRIMDN_MASK1_IMPH_NS_MAX (0x00000001) + #define MPRDRTRN_CR_PRIMDN_MASK1_IMPH_NS_DEF (0x00000000) + #define MPRDRTRN_CR_PRIMDN_MASK1_IMPH_RO_OFF (15) + #define MPRDRTRN_CR_PRIMDN_MASK1_IMPH_RO_WID ( 1) + #define MPRDRTRN_CR_PRIMDN_MASK1_IMPH_RO_MSK (0x00008000) + #define MPRDRTRN_CR_PRIMDN_MASK1_IMPH_RO_MAX (0x00000001) + #define MPRDRTRN_CR_PRIMDN_MASK1_IMPH_RO_DEF (0x00000000) + #define MPRDRTRN_CR_PRIMDN_MASK1_IMPH_LENGTH_OFF (16) + #define MPRDRTRN_CR_PRIMDN_MASK1_IMPH_LENGTH_WID ( 5) + #define MPRDRTRN_CR_PRIMDN_MASK1_IMPH_LENGTH_MSK (0x001F0000) + #define MPRDRTRN_CR_PRIMDN_MASK1_IMPH_LENGTH_MAX (0x0000001F) + #define MPRDRTRN_CR_PRIMDN_MASK1_IMPH_LENGTH_DEF (0x00000000) + #define MPRDRTRN_CR_PRIMDN_MASK1_IMPH_EP_OFF (21) + #define MPRDRTRN_CR_PRIMDN_MASK1_IMPH_EP_WID ( 1) + #define MPRDRTRN_CR_PRIMDN_MASK1_IMPH_EP_MSK (0x00200000) + #define MPRDRTRN_CR_PRIMDN_MASK1_IMPH_EP_MAX (0x00000001) + #define MPRDRTRN_CR_PRIMDN_MASK1_IMPH_EP_DEF (0x00000000) + +#define MPRDRTRN_CR_PRIMDN_MASK2_IMPH_REG (0x00007434) + #define MPRDRTRN_CR_PRIMDN_MASK2_IMPH_RQID_OFF ( 0) + #define MPRDRTRN_CR_PRIMDN_MASK2_IMPH_RQID_WID (16) + #define MPRDRTRN_CR_PRIMDN_MASK2_IMPH_RQID_MSK (0x0000FFFF) + #define MPRDRTRN_CR_PRIMDN_MASK2_IMPH_RQID_MAX (0x0000FFFF) + #define MPRDRTRN_CR_PRIMDN_MASK2_IMPH_RQID_DEF (0x00000000) + #define MPRDRTRN_CR_PRIMDN_MASK2_IMPH_TAG_OFF (16) + #define MPRDRTRN_CR_PRIMDN_MASK2_IMPH_TAG_WID ( 8) + #define MPRDRTRN_CR_PRIMDN_MASK2_IMPH_TAG_MSK (0x00FF0000) + #define MPRDRTRN_CR_PRIMDN_MASK2_IMPH_TAG_MAX (0x000000FF) + #define MPRDRTRN_CR_PRIMDN_MASK2_IMPH_TAG_DEF (0x00000000) + #define MPRDRTRN_CR_PRIMDN_MASK2_IMPH_LBEFBE_MSGTYPE_OFF (24) + #define MPRDRTRN_CR_PRIMDN_MASK2_IMPH_LBEFBE_MSGTYPE_WID ( 8) + #define MPRDRTRN_CR_PRIMDN_MASK2_IMPH_LBEFBE_MSGTYPE_MSK (0xFF000000) + #define MPRDRTRN_CR_PRIMDN_MASK2_IMPH_LBEFBE_MSGTYPE_MAX (0x000000FF) + #define MPRDRTRN_CR_PRIMDN_MASK2_IMPH_LBEFBE_MSGTYPE_DEF (0x00000000) + +#define MPRDRTRN_CR_PRIMDN_MASK3_IMPH_REG (0x00007438) + #define MPRDRTRN_CR_PRIMDN_MASK3_IMPH_ADDR_31_0_OFF ( 0) + #define MPRDRTRN_CR_PRIMDN_MASK3_IMPH_ADDR_31_0_WID (32) + #define MPRDRTRN_CR_PRIMDN_MASK3_IMPH_ADDR_31_0_MSK (0xFFFFFFFF) + #define MPRDRTRN_CR_PRIMDN_MASK3_IMPH_ADDR_31_0_MAX (0xFFFFFFFF) + #define MPRDRTRN_CR_PRIMDN_MASK3_IMPH_ADDR_31_0_DEF (0x00000000) + +#define MPRDRTRN_CR_PRIMDN_MASK4_IMPH_REG (0x0000743C) + #define MPRDRTRN_CR_PRIMDN_MASK4_IMPH_ADDR_63_32_OFF ( 0) + #define MPRDRTRN_CR_PRIMDN_MASK4_IMPH_ADDR_63_32_WID (32) + #define MPRDRTRN_CR_PRIMDN_MASK4_IMPH_ADDR_63_32_MSK (0xFFFFFFFF) + #define MPRDRTRN_CR_PRIMDN_MASK4_IMPH_ADDR_63_32_MAX (0xFFFFFFFF) + #define MPRDRTRN_CR_PRIMDN_MASK4_IMPH_ADDR_63_32_DEF (0x00000000) + +#define MPRDRTRN_CR_PRIMDN_COMP1_IMPH_REG (0x00007440) + #define MPRDRTRN_CR_PRIMDN_COMP1_IMPH_VC_OFF ( 0) + #define MPRDRTRN_CR_PRIMDN_COMP1_IMPH_VC_WID ( 4) + #define MPRDRTRN_CR_PRIMDN_COMP1_IMPH_VC_MSK (0x0000000F) + #define MPRDRTRN_CR_PRIMDN_COMP1_IMPH_VC_MAX (0x0000000F) + #define MPRDRTRN_CR_PRIMDN_COMP1_IMPH_VC_DEF (0x00000000) + #define MPRDRTRN_CR_PRIMDN_COMP1_IMPH_FMT_CMDTYPE_OFF ( 4) + #define MPRDRTRN_CR_PRIMDN_COMP1_IMPH_FMT_CMDTYPE_WID ( 6) + #define MPRDRTRN_CR_PRIMDN_COMP1_IMPH_FMT_CMDTYPE_MSK (0x000003F0) + #define MPRDRTRN_CR_PRIMDN_COMP1_IMPH_FMT_CMDTYPE_MAX (0x0000003F) + #define MPRDRTRN_CR_PRIMDN_COMP1_IMPH_FMT_CMDTYPE_DEF (0x00000000) + #define MPRDRTRN_CR_PRIMDN_COMP1_IMPH_TC_OFF (10) + #define MPRDRTRN_CR_PRIMDN_COMP1_IMPH_TC_WID ( 4) + #define MPRDRTRN_CR_PRIMDN_COMP1_IMPH_TC_MSK (0x00003C00) + #define MPRDRTRN_CR_PRIMDN_COMP1_IMPH_TC_MAX (0x0000000F) + #define MPRDRTRN_CR_PRIMDN_COMP1_IMPH_TC_DEF (0x00000000) + #define MPRDRTRN_CR_PRIMDN_COMP1_IMPH_EP_OFF (14) + #define MPRDRTRN_CR_PRIMDN_COMP1_IMPH_EP_WID ( 1) + #define MPRDRTRN_CR_PRIMDN_COMP1_IMPH_EP_MSK (0x00004000) + #define MPRDRTRN_CR_PRIMDN_COMP1_IMPH_EP_MAX (0x00000001) + #define MPRDRTRN_CR_PRIMDN_COMP1_IMPH_EP_DEF (0x00000000) + #define MPRDRTRN_CR_PRIMDN_COMP1_IMPH_NS_OFF (15) + #define MPRDRTRN_CR_PRIMDN_COMP1_IMPH_NS_WID ( 1) + #define MPRDRTRN_CR_PRIMDN_COMP1_IMPH_NS_MSK (0x00008000) + #define MPRDRTRN_CR_PRIMDN_COMP1_IMPH_NS_MAX (0x00000001) + #define MPRDRTRN_CR_PRIMDN_COMP1_IMPH_NS_DEF (0x00000000) + #define MPRDRTRN_CR_PRIMDN_COMP1_IMPH_RO_OFF (16) + #define MPRDRTRN_CR_PRIMDN_COMP1_IMPH_RO_WID ( 1) + #define MPRDRTRN_CR_PRIMDN_COMP1_IMPH_RO_MSK (0x00010000) + #define MPRDRTRN_CR_PRIMDN_COMP1_IMPH_RO_MAX (0x00000001) + #define MPRDRTRN_CR_PRIMDN_COMP1_IMPH_RO_DEF (0x00000000) + #define MPRDRTRN_CR_PRIMDN_COMP1_IMPH_LENGTH_OFF (17) + #define MPRDRTRN_CR_PRIMDN_COMP1_IMPH_LENGTH_WID ( 5) + #define MPRDRTRN_CR_PRIMDN_COMP1_IMPH_LENGTH_MSK (0x003E0000) + #define MPRDRTRN_CR_PRIMDN_COMP1_IMPH_LENGTH_MAX (0x0000001F) + #define MPRDRTRN_CR_PRIMDN_COMP1_IMPH_LENGTH_DEF (0x00000000) + +#define MPRDRTRN_CR_PRIMDN_COMP2_IMPH_REG (0x00007444) + #define MPRDRTRN_CR_PRIMDN_COMP2_IMPH_RQID_OFF ( 0) + #define MPRDRTRN_CR_PRIMDN_COMP2_IMPH_RQID_WID (16) + #define MPRDRTRN_CR_PRIMDN_COMP2_IMPH_RQID_MSK (0x0000FFFF) + #define MPRDRTRN_CR_PRIMDN_COMP2_IMPH_RQID_MAX (0x0000FFFF) + #define MPRDRTRN_CR_PRIMDN_COMP2_IMPH_RQID_DEF (0x00000000) + #define MPRDRTRN_CR_PRIMDN_COMP2_IMPH_TAG_OFF (16) + #define MPRDRTRN_CR_PRIMDN_COMP2_IMPH_TAG_WID ( 8) + #define MPRDRTRN_CR_PRIMDN_COMP2_IMPH_TAG_MSK (0x00FF0000) + #define MPRDRTRN_CR_PRIMDN_COMP2_IMPH_TAG_MAX (0x000000FF) + #define MPRDRTRN_CR_PRIMDN_COMP2_IMPH_TAG_DEF (0x00000000) + #define MPRDRTRN_CR_PRIMDN_COMP2_IMPH_LBEFBE_MSGTYPE_OFF (24) + #define MPRDRTRN_CR_PRIMDN_COMP2_IMPH_LBEFBE_MSGTYPE_WID ( 8) + #define MPRDRTRN_CR_PRIMDN_COMP2_IMPH_LBEFBE_MSGTYPE_MSK (0xFF000000) + #define MPRDRTRN_CR_PRIMDN_COMP2_IMPH_LBEFBE_MSGTYPE_MAX (0x000000FF) + #define MPRDRTRN_CR_PRIMDN_COMP2_IMPH_LBEFBE_MSGTYPE_DEF (0x00000000) + +#define MPRDRTRN_CR_PRIMDN_COMP3_IMPH_REG (0x00007448) + #define MPRDRTRN_CR_PRIMDN_COMP3_IMPH_ADDR_31_0_OFF ( 0) + #define MPRDRTRN_CR_PRIMDN_COMP3_IMPH_ADDR_31_0_WID (32) + #define MPRDRTRN_CR_PRIMDN_COMP3_IMPH_ADDR_31_0_MSK (0xFFFFFFFF) + #define MPRDRTRN_CR_PRIMDN_COMP3_IMPH_ADDR_31_0_MAX (0xFFFFFFFF) + #define MPRDRTRN_CR_PRIMDN_COMP3_IMPH_ADDR_31_0_DEF (0x00000000) + +#define MPRDRTRN_CR_PRIMDN_COMP4_IMPH_REG (0x0000744C) + #define MPRDRTRN_CR_PRIMDN_COMP4_IMPH_ADDR_63_32_OFF ( 0) + #define MPRDRTRN_CR_PRIMDN_COMP4_IMPH_ADDR_63_32_WID (32) + #define MPRDRTRN_CR_PRIMDN_COMP4_IMPH_ADDR_63_32_MSK (0xFFFFFFFF) + #define MPRDRTRN_CR_PRIMDN_COMP4_IMPH_ADDR_63_32_MAX (0xFFFFFFFF) + #define MPRDRTRN_CR_PRIMDN_COMP4_IMPH_ADDR_63_32_DEF (0x00000000) + +#define MPRDRTRN_CR_PRIMDN_TRIGGER_IMPH_REG (0x00007450) + #define MPRDRTRN_CR_PRIMDN_TRIGGER_IMPH_ENABLE_OFF ( 0) + #define MPRDRTRN_CR_PRIMDN_TRIGGER_IMPH_ENABLE_WID ( 1) + #define MPRDRTRN_CR_PRIMDN_TRIGGER_IMPH_ENABLE_MSK (0x00000001) + #define MPRDRTRN_CR_PRIMDN_TRIGGER_IMPH_ENABLE_MAX (0x00000001) + #define MPRDRTRN_CR_PRIMDN_TRIGGER_IMPH_ENABLE_DEF (0x00000000) + #define MPRDRTRN_CR_PRIMDN_TRIGGER_IMPH_TRIGGERED_OFF ( 1) + #define MPRDRTRN_CR_PRIMDN_TRIGGER_IMPH_TRIGGERED_WID ( 1) + #define MPRDRTRN_CR_PRIMDN_TRIGGER_IMPH_TRIGGERED_MSK (0x00000002) + #define MPRDRTRN_CR_PRIMDN_TRIGGER_IMPH_TRIGGERED_MAX (0x00000001) + #define MPRDRTRN_CR_PRIMDN_TRIGGER_IMPH_TRIGGERED_DEF (0x00000000) + #define MPRDRTRN_CR_PRIMDN_TRIGGER_IMPH_STALL_DNARB_OFF ( 2) + #define MPRDRTRN_CR_PRIMDN_TRIGGER_IMPH_STALL_DNARB_WID ( 1) + #define MPRDRTRN_CR_PRIMDN_TRIGGER_IMPH_STALL_DNARB_MSK (0x00000004) + #define MPRDRTRN_CR_PRIMDN_TRIGGER_IMPH_STALL_DNARB_MAX (0x00000001) + #define MPRDRTRN_CR_PRIMDN_TRIGGER_IMPH_STALL_DNARB_DEF (0x00000000) + #define MPRDRTRN_CR_PRIMDN_TRIGGER_IMPH_STALL_DELAY_OFF (23) + #define MPRDRTRN_CR_PRIMDN_TRIGGER_IMPH_STALL_DELAY_WID ( 9) + #define MPRDRTRN_CR_PRIMDN_TRIGGER_IMPH_STALL_DELAY_MSK (0xFF800000) + #define MPRDRTRN_CR_PRIMDN_TRIGGER_IMPH_STALL_DELAY_MAX (0x000001FF) + #define MPRDRTRN_CR_PRIMDN_TRIGGER_IMPH_STALL_DELAY_DEF (0x00000000) + +#define MPRDRTRN_CR_CRDTCTL8_IMPH_REG (0x00007454) + #define MPRDRTRN_CR_CRDTCTL8_IMPH_DMIVC0_RRMAX_OFF ( 0) + #define MPRDRTRN_CR_CRDTCTL8_IMPH_DMIVC0_RRMAX_WID ( 6) + #define MPRDRTRN_CR_CRDTCTL8_IMPH_DMIVC0_RRMAX_MSK (0x0000003F) + #define MPRDRTRN_CR_CRDTCTL8_IMPH_DMIVC0_RRMAX_MAX (0x0000003F) + #define MPRDRTRN_CR_CRDTCTL8_IMPH_P10VC0_RRMAX_OFF ( 6) + #define MPRDRTRN_CR_CRDTCTL8_IMPH_P10VC0_RRMAX_WID ( 6) + #define MPRDRTRN_CR_CRDTCTL8_IMPH_P10VC0_RRMAX_MSK (0x00000FC0) + #define MPRDRTRN_CR_CRDTCTL8_IMPH_P10VC0_RRMAX_MAX (0x0000003F) + #define MPRDRTRN_CR_CRDTCTL8_IMPH_P11VC0_RRMAX_OFF (12) + #define MPRDRTRN_CR_CRDTCTL8_IMPH_P11VC0_RRMAX_WID ( 6) + #define MPRDRTRN_CR_CRDTCTL8_IMPH_P11VC0_RRMAX_MSK (0x0003F000) + #define MPRDRTRN_CR_CRDTCTL8_IMPH_P11VC0_RRMAX_MAX (0x0000003F) + #define MPRDRTRN_CR_CRDTCTL8_IMPH_P12VC0_RRMAX_OFF (18) + #define MPRDRTRN_CR_CRDTCTL8_IMPH_P12VC0_RRMAX_WID ( 6) + #define MPRDRTRN_CR_CRDTCTL8_IMPH_P12VC0_RRMAX_MSK (0x00FC0000) + #define MPRDRTRN_CR_CRDTCTL8_IMPH_P12VC0_RRMAX_MAX (0x0000003F) + #define MPRDRTRN_CR_CRDTCTL8_IMPH_DEVC0_RRMAX_OFF (24) + #define MPRDRTRN_CR_CRDTCTL8_IMPH_DEVC0_RRMAX_WID ( 6) + #define MPRDRTRN_CR_CRDTCTL8_IMPH_DEVC0_RRMAX_MSK (0x3F000000) + #define MPRDRTRN_CR_CRDTCTL8_IMPH_DEVC0_RRMAX_MAX (0x0000003F) + +#define MPRDRTRN_CR_CRDTCTL9_IMPH_REG (0x00007458) + #define MPRDRTRN_CR_CRDTCTL9_IMPH_DMIVCP_RRMAX_OFF ( 0) + #define MPRDRTRN_CR_CRDTCTL9_IMPH_DMIVCP_RRMAX_WID ( 6) + #define MPRDRTRN_CR_CRDTCTL9_IMPH_DMIVCP_RRMAX_MSK (0x0000003F) + #define MPRDRTRN_CR_CRDTCTL9_IMPH_DMIVCP_RRMAX_MAX (0x0000003F) + #define MPRDRTRN_CR_CRDTCTL9_IMPH_DMIVCM_RRMAX_OFF ( 6) + #define MPRDRTRN_CR_CRDTCTL9_IMPH_DMIVCM_RRMAX_WID ( 6) + #define MPRDRTRN_CR_CRDTCTL9_IMPH_DMIVCM_RRMAX_MSK (0x00000FC0) + #define MPRDRTRN_CR_CRDTCTL9_IMPH_DMIVCM_RRMAX_MAX (0x0000003F) + #define MPRDRTRN_CR_CRDTCTL9_IMPH_DMIVC1_RRMAX_OFF (12) + #define MPRDRTRN_CR_CRDTCTL9_IMPH_DMIVC1_RRMAX_WID ( 6) + #define MPRDRTRN_CR_CRDTCTL9_IMPH_DMIVC1_RRMAX_MSK (0x0003F000) + #define MPRDRTRN_CR_CRDTCTL9_IMPH_DMIVC1_RRMAX_MAX (0x0000003F) + #define MPRDRTRN_CR_CRDTCTL9_IMPH_DEVC1_RRMAX_OFF (18) + #define MPRDRTRN_CR_CRDTCTL9_IMPH_DEVC1_RRMAX_WID ( 6) + #define MPRDRTRN_CR_CRDTCTL9_IMPH_DEVC1_RRMAX_MSK (0x00FC0000) + #define MPRDRTRN_CR_CRDTCTL9_IMPH_DEVC1_RRMAX_MAX (0x0000003F) + +#define MPRDRTRN_CR_PCIE_POPUP_CTL_IMPH_REG (0x00007500) + #define MPRDRTRN_CR_PCIE_POPUP_CTL_IMPH_LIM_OFF ( 0) + #define MPRDRTRN_CR_PCIE_POPUP_CTL_IMPH_LIM_WID (16) + #define MPRDRTRN_CR_PCIE_POPUP_CTL_IMPH_LIM_MSK (0x0000FFFF) + #define MPRDRTRN_CR_PCIE_POPUP_CTL_IMPH_LIM_MAX (0x0000FFFF) + #define MPRDRTRN_CR_PCIE_POPUP_CTL_IMPH_LIM_DEF (0x00000000) + #define MPRDRTRN_CR_PCIE_POPUP_CTL_IMPH_MSK_OFF (16) + #define MPRDRTRN_CR_PCIE_POPUP_CTL_IMPH_MSK_WID ( 3) + #define MPRDRTRN_CR_PCIE_POPUP_CTL_IMPH_MSK_MSK (0x00070000) + #define MPRDRTRN_CR_PCIE_POPUP_CTL_IMPH_MSK_MAX (0x00000007) + #define MPRDRTRN_CR_PCIE_POPUP_CTL_IMPH_MSK_DEF (0x00000007) + +#define MPRDRTRN_CR_VDMBDFBARSSKU_IMPH_REG (0x00007504) + #define MPRDRTRN_CR_VDMBDFBARSSKU_IMPH_FUNNUM_OFF ( 0) + #define MPRDRTRN_CR_VDMBDFBARSSKU_IMPH_FUNNUM_WID ( 3) + #define MPRDRTRN_CR_VDMBDFBARSSKU_IMPH_FUNNUM_MSK (0x00000007) + #define MPRDRTRN_CR_VDMBDFBARSSKU_IMPH_FUNNUM_MAX (0x00000007) + #define MPRDRTRN_CR_VDMBDFBARSSKU_IMPH_FUNNUM_DEF (0x00000000) + #define MPRDRTRN_CR_VDMBDFBARSSKU_IMPH_DEVNUM_OFF ( 3) + #define MPRDRTRN_CR_VDMBDFBARSSKU_IMPH_DEVNUM_WID ( 5) + #define MPRDRTRN_CR_VDMBDFBARSSKU_IMPH_DEVNUM_MSK (0x000000F8) + #define MPRDRTRN_CR_VDMBDFBARSSKU_IMPH_DEVNUM_MAX (0x0000001F) + #define MPRDRTRN_CR_VDMBDFBARSSKU_IMPH_DEVNUM_DEF (0x00000016) + #define MPRDRTRN_CR_VDMBDFBARSSKU_IMPH_BUSNUM_OFF ( 8) + #define MPRDRTRN_CR_VDMBDFBARSSKU_IMPH_BUSNUM_WID ( 8) + #define MPRDRTRN_CR_VDMBDFBARSSKU_IMPH_BUSNUM_MSK (0x0000FF00) + #define MPRDRTRN_CR_VDMBDFBARSSKU_IMPH_BUSNUM_MAX (0x000000FF) + #define MPRDRTRN_CR_VDMBDFBARSSKU_IMPH_BUSNUM_DEF (0x00000000) + #define MPRDRTRN_CR_VDMBDFBARSSKU_IMPH_BARNUM_OFF (16) + #define MPRDRTRN_CR_VDMBDFBARSSKU_IMPH_BARNUM_WID ( 3) + #define MPRDRTRN_CR_VDMBDFBARSSKU_IMPH_BARNUM_MSK (0x00070000) + #define MPRDRTRN_CR_VDMBDFBARSSKU_IMPH_BARNUM_MAX (0x00000007) + #define MPRDRTRN_CR_VDMBDFBARSSKU_IMPH_BARNUM_DEF (0x00000007) + +#define MPRDRTRN_CR_CRDTLCK_IMPH_REG (0x000077FC) + #define MPRDRTRN_CR_CRDTLCK_IMPH_LOCK_OFF ( 0) + #define MPRDRTRN_CR_CRDTLCK_IMPH_LOCK_WID ( 1) + #define MPRDRTRN_CR_CRDTLCK_IMPH_LOCK_MSK (0x00000001) + #define MPRDRTRN_CR_CRDTLCK_IMPH_LOCK_MAX (0x00000001) + #define MPRDRTRN_CR_CRDTLCK_IMPH_LOCK_DEF (0x00000000) + +#define MPMCARB_CR_VCLIM0_IMPH_REG (0x00007800) + #define MPMCARB_CR_VCLIM0_IMPH_VCPNPLIM_OFF ( 0) + #define MPMCARB_CR_VCLIM0_IMPH_VCPNPLIM_WID ( 3) + #define MPMCARB_CR_VCLIM0_IMPH_VCPNPLIM_MSK (0x00000007) + #define MPMCARB_CR_VCLIM0_IMPH_VCPNPLIM_MAX (0x00000007) + #define MPMCARB_CR_VCLIM0_IMPH_VCPNPLIM_DEF (0x00000004) + #define MPMCARB_CR_VCLIM0_IMPH_VCPPLIM_OFF ( 4) + #define MPMCARB_CR_VCLIM0_IMPH_VCPPLIM_WID ( 3) + #define MPMCARB_CR_VCLIM0_IMPH_VCPPLIM_MSK (0x00000070) + #define MPMCARB_CR_VCLIM0_IMPH_VCPPLIM_MAX (0x00000007) + #define MPMCARB_CR_VCLIM0_IMPH_VCPPLIM_DEF (0x00000004) + #define MPMCARB_CR_VCLIM0_IMPH_VCMNPLIM_OFF ( 8) + #define MPMCARB_CR_VCLIM0_IMPH_VCMNPLIM_WID ( 3) + #define MPMCARB_CR_VCLIM0_IMPH_VCMNPLIM_MSK (0x00000700) + #define MPMCARB_CR_VCLIM0_IMPH_VCMNPLIM_MAX (0x00000007) + #define MPMCARB_CR_VCLIM0_IMPH_VCMNPLIM_DEF (0x00000004) + #define MPMCARB_CR_VCLIM0_IMPH_VCMPLIM_OFF (12) + #define MPMCARB_CR_VCLIM0_IMPH_VCMPLIM_WID ( 3) + #define MPMCARB_CR_VCLIM0_IMPH_VCMPLIM_MSK (0x00007000) + #define MPMCARB_CR_VCLIM0_IMPH_VCMPLIM_MAX (0x00000007) + #define MPMCARB_CR_VCLIM0_IMPH_VCMPLIM_DEF (0x00000004) + #define MPMCARB_CR_VCLIM0_IMPH_VC0VTDLIM_OFF (16) + #define MPMCARB_CR_VCLIM0_IMPH_VC0VTDLIM_WID ( 3) + #define MPMCARB_CR_VCLIM0_IMPH_VC0VTDLIM_MSK (0x00070000) + #define MPMCARB_CR_VCLIM0_IMPH_VC0VTDLIM_MAX (0x00000007) + #define MPMCARB_CR_VCLIM0_IMPH_VC0VTDLIM_DEF (0x00000004) + #define MPMCARB_CR_VCLIM0_IMPH_VCPVTDLIM_OFF (20) + #define MPMCARB_CR_VCLIM0_IMPH_VCPVTDLIM_WID ( 3) + #define MPMCARB_CR_VCLIM0_IMPH_VCPVTDLIM_MSK (0x00700000) + #define MPMCARB_CR_VCLIM0_IMPH_VCPVTDLIM_MAX (0x00000007) + #define MPMCARB_CR_VCLIM0_IMPH_VCPVTDLIM_DEF (0x00000004) + +#define MPMCARB_CR_VCLIM1_IMPH_REG (0x00007804) + #define MPMCARB_CR_VCLIM1_IMPH_IARD_OFF ( 0) + #define MPMCARB_CR_VCLIM1_IMPH_IARD_WID ( 3) + #define MPMCARB_CR_VCLIM1_IMPH_IARD_MSK (0x00000007) + #define MPMCARB_CR_VCLIM1_IMPH_IARD_MAX (0x00000007) + #define MPMCARB_CR_VCLIM1_IMPH_IARD_DEF (0x00000004) + #define MPMCARB_CR_VCLIM1_IMPH_IAWR_OFF ( 4) + #define MPMCARB_CR_VCLIM1_IMPH_IAWR_WID ( 3) + #define MPMCARB_CR_VCLIM1_IMPH_IAWR_MSK (0x00000070) + #define MPMCARB_CR_VCLIM1_IMPH_IAWR_MAX (0x00000007) + #define MPMCARB_CR_VCLIM1_IMPH_IAWR_DEF (0x00000004) + #define MPMCARB_CR_VCLIM1_IMPH_VTDL3_OFF ( 8) + #define MPMCARB_CR_VCLIM1_IMPH_VTDL3_WID ( 3) + #define MPMCARB_CR_VCLIM1_IMPH_VTDL3_MSK (0x00000700) + #define MPMCARB_CR_VCLIM1_IMPH_VTDL3_MAX (0x00000007) + #define MPMCARB_CR_VCLIM1_IMPH_VTDL3_DEF (0x00000004) + #define MPMCARB_CR_VCLIM1_IMPH_VTDNL3_OFF (12) + #define MPMCARB_CR_VCLIM1_IMPH_VTDNL3_WID ( 3) + #define MPMCARB_CR_VCLIM1_IMPH_VTDNL3_MSK (0x00007000) + #define MPMCARB_CR_VCLIM1_IMPH_VTDNL3_MAX (0x00000007) + #define MPMCARB_CR_VCLIM1_IMPH_VTDNL3_DEF (0x00000004) + +#define MPMCARB_CR_ATMC_STS_IMPH_REG (0x00007808) + #define MPMCARB_CR_ATMC_STS_IMPH_VC1_WR_CNFLT_OFF ( 0) + #define MPMCARB_CR_ATMC_STS_IMPH_VC1_WR_CNFLT_WID ( 1) + #define MPMCARB_CR_ATMC_STS_IMPH_VC1_WR_CNFLT_MSK (0x00000001) + #define MPMCARB_CR_ATMC_STS_IMPH_VC1_WR_CNFLT_MAX (0x00000001) + #define MPMCARB_CR_ATMC_STS_IMPH_VC1_WR_CNFLT_DEF (0x00000000) + #define MPMCARB_CR_ATMC_STS_IMPH_VC1_RD_CNFLT_OFF ( 1) + #define MPMCARB_CR_ATMC_STS_IMPH_VC1_RD_CNFLT_WID ( 1) + #define MPMCARB_CR_ATMC_STS_IMPH_VC1_RD_CNFLT_MSK (0x00000002) + #define MPMCARB_CR_ATMC_STS_IMPH_VC1_RD_CNFLT_MAX (0x00000001) + #define MPMCARB_CR_ATMC_STS_IMPH_VC1_RD_CNFLT_DEF (0x00000000) + +#define MPMCARB_CR_VISA_CTL_MPMCARBS_F_IMPH_REG (0x00007820) + #define MPMCARB_CR_VISA_CTL_MPMCARBS_F_IMPH_DATA_OFF ( 0) + #define MPMCARB_CR_VISA_CTL_MPMCARBS_F_IMPH_DATA_WID (18) + #define MPMCARB_CR_VISA_CTL_MPMCARBS_F_IMPH_DATA_MSK (0x0003FFFF) + #define MPMCARB_CR_VISA_CTL_MPMCARBS_F_IMPH_DATA_MAX (0x0003FFFF) + #define MPMCARB_CR_VISA_CTL_MPMCARBS_F_IMPH_DATA_DEF (0x00000000) + #define MPMCARB_CR_VISA_CTL_MPMCARBS_F_IMPH_VORANGE_OFF (31) + #define MPMCARB_CR_VISA_CTL_MPMCARBS_F_IMPH_VORANGE_WID ( 1) + #define MPMCARB_CR_VISA_CTL_MPMCARBS_F_IMPH_VORANGE_MSK (0x80000000) + #define MPMCARB_CR_VISA_CTL_MPMCARBS_F_IMPH_VORANGE_MAX (0x00000001) + #define MPMCARB_CR_VISA_CTL_MPMCARBS_F_IMPH_VORANGE_DEF (0x00000000) + +#define MPMCARB_CR_VISA_CTL_MPMCARBS_D_IMPH_REG (0x00007824) + #define MPMCARB_CR_VISA_CTL_MPMCARBS_D_IMPH_DATA_OFF ( 0) + #define MPMCARB_CR_VISA_CTL_MPMCARBS_D_IMPH_DATA_WID (18) + #define MPMCARB_CR_VISA_CTL_MPMCARBS_D_IMPH_DATA_MSK (0x0003FFFF) + #define MPMCARB_CR_VISA_CTL_MPMCARBS_D_IMPH_DATA_MAX (0x0003FFFF) + #define MPMCARB_CR_VISA_CTL_MPMCARBS_D_IMPH_DATA_DEF (0x00000000) + #define MPMCARB_CR_VISA_CTL_MPMCARBS_D_IMPH_VORANGE_OFF (31) + #define MPMCARB_CR_VISA_CTL_MPMCARBS_D_IMPH_VORANGE_WID ( 1) + #define MPMCARB_CR_VISA_CTL_MPMCARBS_D_IMPH_VORANGE_MSK (0x80000000) + #define MPMCARB_CR_VISA_CTL_MPMCARBS_D_IMPH_VORANGE_MAX (0x00000001) + #define MPMCARB_CR_VISA_CTL_MPMCARBS_D_IMPH_VORANGE_DEF (0x00000000) + +#define MPMCARB_CR_MCARBLCK_IMPH_REG (0x00007FFC) + #define MPMCARB_CR_MCARBLCK_IMPH_LOCK_OFF ( 0) + #define MPMCARB_CR_MCARBLCK_IMPH_LOCK_WID ( 1) + #define MPMCARB_CR_MCARBLCK_IMPH_LOCK_MSK (0x00000001) + #define MPMCARB_CR_MCARBLCK_IMPH_LOCK_MAX (0x00000001) + #define MPMCARB_CR_MCARBLCK_IMPH_LOCK_DEF (0x00000000) + +#define PCU_CR_CAMARILLO_MAILBOX_DATA0_PCU_REG (0x00005810) + #define PCU_CR_CAMARILLO_MAILBOX_DATA0_PCU_DATA_OFF ( 0) + #define PCU_CR_CAMARILLO_MAILBOX_DATA0_PCU_DATA_WID (32) + #define PCU_CR_CAMARILLO_MAILBOX_DATA0_PCU_DATA_MSK (0xFFFFFFFF) + #define PCU_CR_CAMARILLO_MAILBOX_DATA0_PCU_DATA_MAX (0xFFFFFFFF) + #define PCU_CR_CAMARILLO_MAILBOX_DATA0_PCU_DATA_DEF (0x00000000) + +#define PCU_CR_CAMARILLO_MAILBOX_DATA1_PCU_REG (0x00005814) + #define PCU_CR_CAMARILLO_MAILBOX_DATA1_PCU_DATA_OFF ( 0) + #define PCU_CR_CAMARILLO_MAILBOX_DATA1_PCU_DATA_WID (32) + #define PCU_CR_CAMARILLO_MAILBOX_DATA1_PCU_DATA_MSK (0xFFFFFFFF) + #define PCU_CR_CAMARILLO_MAILBOX_DATA1_PCU_DATA_MAX (0xFFFFFFFF) + #define PCU_CR_CAMARILLO_MAILBOX_DATA1_PCU_DATA_DEF (0x00000000) + +#define PCU_CR_CAMARILLO_MAILBOX_INTERFACE_PCU_REG (0x00005818) + #define PCU_CR_CAMARILLO_MAILBOX_INTERFACE_PCU_COMMAND_OFF ( 0) + #define PCU_CR_CAMARILLO_MAILBOX_INTERFACE_PCU_COMMAND_WID ( 8) + #define PCU_CR_CAMARILLO_MAILBOX_INTERFACE_PCU_COMMAND_MSK (0x000000FF) + #define PCU_CR_CAMARILLO_MAILBOX_INTERFACE_PCU_COMMAND_MAX (0x000000FF) + #define PCU_CR_CAMARILLO_MAILBOX_INTERFACE_PCU_COMMAND_DEF (0x00000000) + #define PCU_CR_CAMARILLO_MAILBOX_INTERFACE_PCU_ADDR_CNTL_OFF ( 8) + #define PCU_CR_CAMARILLO_MAILBOX_INTERFACE_PCU_ADDR_CNTL_WID (21) + #define PCU_CR_CAMARILLO_MAILBOX_INTERFACE_PCU_ADDR_CNTL_MSK (0x1FFFFF00) + #define PCU_CR_CAMARILLO_MAILBOX_INTERFACE_PCU_ADDR_CNTL_MAX (0x001FFFFF) + #define PCU_CR_CAMARILLO_MAILBOX_INTERFACE_PCU_ADDR_CNTL_DEF (0x00000000) + #define PCU_CR_CAMARILLO_MAILBOX_INTERFACE_PCU_RUN_BUSY_OFF (31) + #define PCU_CR_CAMARILLO_MAILBOX_INTERFACE_PCU_RUN_BUSY_WID ( 1) + #define PCU_CR_CAMARILLO_MAILBOX_INTERFACE_PCU_RUN_BUSY_MSK (0x80000000) + #define PCU_CR_CAMARILLO_MAILBOX_INTERFACE_PCU_RUN_BUSY_MAX (0x00000001) + #define PCU_CR_CAMARILLO_MAILBOX_INTERFACE_PCU_RUN_BUSY_DEF (0x00000000) + +#define PCU_CR_PACKAGE_THERM_CAMARILLO_INTERRUPT_PCU_REG (0x00005820) + #define PCU_CR_PACKAGE_THERM_CAMARILLO_INTERRUPT_PCU_HIGH_TEMP_INT_ENABLE_OFF ( 0) + #define PCU_CR_PACKAGE_THERM_CAMARILLO_INTERRUPT_PCU_HIGH_TEMP_INT_ENABLE_WID ( 1) + #define PCU_CR_PACKAGE_THERM_CAMARILLO_INTERRUPT_PCU_HIGH_TEMP_INT_ENABLE_MSK (0x00000001) + #define PCU_CR_PACKAGE_THERM_CAMARILLO_INTERRUPT_PCU_HIGH_TEMP_INT_ENABLE_MAX (0x00000001) + #define PCU_CR_PACKAGE_THERM_CAMARILLO_INTERRUPT_PCU_HIGH_TEMP_INT_ENABLE_DEF (0x00000000) + #define PCU_CR_PACKAGE_THERM_CAMARILLO_INTERRUPT_PCU_LOW_TEMP_INT_ENABLE_OFF ( 1) + #define PCU_CR_PACKAGE_THERM_CAMARILLO_INTERRUPT_PCU_LOW_TEMP_INT_ENABLE_WID ( 1) + #define PCU_CR_PACKAGE_THERM_CAMARILLO_INTERRUPT_PCU_LOW_TEMP_INT_ENABLE_MSK (0x00000002) + #define PCU_CR_PACKAGE_THERM_CAMARILLO_INTERRUPT_PCU_LOW_TEMP_INT_ENABLE_MAX (0x00000001) + #define PCU_CR_PACKAGE_THERM_CAMARILLO_INTERRUPT_PCU_LOW_TEMP_INT_ENABLE_DEF (0x00000000) + #define PCU_CR_PACKAGE_THERM_CAMARILLO_INTERRUPT_PCU_PROCHOT_INT_ENABLE_OFF ( 2) + #define PCU_CR_PACKAGE_THERM_CAMARILLO_INTERRUPT_PCU_PROCHOT_INT_ENABLE_WID ( 1) + #define PCU_CR_PACKAGE_THERM_CAMARILLO_INTERRUPT_PCU_PROCHOT_INT_ENABLE_MSK (0x00000004) + #define PCU_CR_PACKAGE_THERM_CAMARILLO_INTERRUPT_PCU_PROCHOT_INT_ENABLE_MAX (0x00000001) + #define PCU_CR_PACKAGE_THERM_CAMARILLO_INTERRUPT_PCU_PROCHOT_INT_ENABLE_DEF (0x00000000) + #define PCU_CR_PACKAGE_THERM_CAMARILLO_INTERRUPT_PCU_OUT_OF_SPEC_INT_ENABLE_OFF ( 4) + #define PCU_CR_PACKAGE_THERM_CAMARILLO_INTERRUPT_PCU_OUT_OF_SPEC_INT_ENABLE_WID ( 1) + #define PCU_CR_PACKAGE_THERM_CAMARILLO_INTERRUPT_PCU_OUT_OF_SPEC_INT_ENABLE_MSK (0x00000010) + #define PCU_CR_PACKAGE_THERM_CAMARILLO_INTERRUPT_PCU_OUT_OF_SPEC_INT_ENABLE_MAX (0x00000001) + #define PCU_CR_PACKAGE_THERM_CAMARILLO_INTERRUPT_PCU_OUT_OF_SPEC_INT_ENABLE_DEF (0x00000000) + #define PCU_CR_PACKAGE_THERM_CAMARILLO_INTERRUPT_PCU_THRESHOLD_1_REL_TEMP_OFF ( 8) + #define PCU_CR_PACKAGE_THERM_CAMARILLO_INTERRUPT_PCU_THRESHOLD_1_REL_TEMP_WID ( 7) + #define PCU_CR_PACKAGE_THERM_CAMARILLO_INTERRUPT_PCU_THRESHOLD_1_REL_TEMP_MSK (0x00007F00) + #define PCU_CR_PACKAGE_THERM_CAMARILLO_INTERRUPT_PCU_THRESHOLD_1_REL_TEMP_MAX (0x0000007F) + #define PCU_CR_PACKAGE_THERM_CAMARILLO_INTERRUPT_PCU_THRESHOLD_1_REL_TEMP_DEF (0x00000000) + #define PCU_CR_PACKAGE_THERM_CAMARILLO_INTERRUPT_PCU_THRESHOLD_1_INT_ENABLE_OFF (15) + #define PCU_CR_PACKAGE_THERM_CAMARILLO_INTERRUPT_PCU_THRESHOLD_1_INT_ENABLE_WID ( 1) + #define PCU_CR_PACKAGE_THERM_CAMARILLO_INTERRUPT_PCU_THRESHOLD_1_INT_ENABLE_MSK (0x00008000) + #define PCU_CR_PACKAGE_THERM_CAMARILLO_INTERRUPT_PCU_THRESHOLD_1_INT_ENABLE_MAX (0x00000001) + #define PCU_CR_PACKAGE_THERM_CAMARILLO_INTERRUPT_PCU_THRESHOLD_1_INT_ENABLE_DEF (0x00000000) + #define PCU_CR_PACKAGE_THERM_CAMARILLO_INTERRUPT_PCU_THRESHOLD_2_REL_TEMP_OFF (16) + #define PCU_CR_PACKAGE_THERM_CAMARILLO_INTERRUPT_PCU_THRESHOLD_2_REL_TEMP_WID ( 7) + #define PCU_CR_PACKAGE_THERM_CAMARILLO_INTERRUPT_PCU_THRESHOLD_2_REL_TEMP_MSK (0x007F0000) + #define PCU_CR_PACKAGE_THERM_CAMARILLO_INTERRUPT_PCU_THRESHOLD_2_REL_TEMP_MAX (0x0000007F) + #define PCU_CR_PACKAGE_THERM_CAMARILLO_INTERRUPT_PCU_THRESHOLD_2_REL_TEMP_DEF (0x00000000) + #define PCU_CR_PACKAGE_THERM_CAMARILLO_INTERRUPT_PCU_THRESHOLD_2_INT_ENABLE_OFF (23) + #define PCU_CR_PACKAGE_THERM_CAMARILLO_INTERRUPT_PCU_THRESHOLD_2_INT_ENABLE_WID ( 1) + #define PCU_CR_PACKAGE_THERM_CAMARILLO_INTERRUPT_PCU_THRESHOLD_2_INT_ENABLE_MSK (0x00800000) + #define PCU_CR_PACKAGE_THERM_CAMARILLO_INTERRUPT_PCU_THRESHOLD_2_INT_ENABLE_MAX (0x00000001) + #define PCU_CR_PACKAGE_THERM_CAMARILLO_INTERRUPT_PCU_THRESHOLD_2_INT_ENABLE_DEF (0x00000000) + #define PCU_CR_PACKAGE_THERM_CAMARILLO_INTERRUPT_PCU_POWER_INT_ENABLE_OFF (24) + #define PCU_CR_PACKAGE_THERM_CAMARILLO_INTERRUPT_PCU_POWER_INT_ENABLE_WID ( 1) + #define PCU_CR_PACKAGE_THERM_CAMARILLO_INTERRUPT_PCU_POWER_INT_ENABLE_MSK (0x01000000) + #define PCU_CR_PACKAGE_THERM_CAMARILLO_INTERRUPT_PCU_POWER_INT_ENABLE_MAX (0x00000001) + #define PCU_CR_PACKAGE_THERM_CAMARILLO_INTERRUPT_PCU_POWER_INT_ENABLE_DEF (0x00000000) + +#define PCU_CR_DDR_PTM_CTL_PCU_REG (0x00005880) + #define PCU_CR_DDR_PTM_CTL_PCU_OLTM_ENABLE_OFF ( 0) + #define PCU_CR_DDR_PTM_CTL_PCU_OLTM_ENABLE_WID ( 1) + #define PCU_CR_DDR_PTM_CTL_PCU_OLTM_ENABLE_MSK (0x00000001) + #define PCU_CR_DDR_PTM_CTL_PCU_OLTM_ENABLE_MAX (0x00000001) + #define PCU_CR_DDR_PTM_CTL_PCU_OLTM_ENABLE_DEF (0x00000000) + #define PCU_CR_DDR_PTM_CTL_PCU_CLTM_ENABLE_OFF ( 1) + #define PCU_CR_DDR_PTM_CTL_PCU_CLTM_ENABLE_WID ( 1) + #define PCU_CR_DDR_PTM_CTL_PCU_CLTM_ENABLE_MSK (0x00000002) + #define PCU_CR_DDR_PTM_CTL_PCU_CLTM_ENABLE_MAX (0x00000001) + #define PCU_CR_DDR_PTM_CTL_PCU_CLTM_ENABLE_DEF (0x00000000) + #define PCU_CR_DDR_PTM_CTL_PCU_REFRESH_2X_MODE_OFF ( 2) + #define PCU_CR_DDR_PTM_CTL_PCU_REFRESH_2X_MODE_WID ( 2) + #define PCU_CR_DDR_PTM_CTL_PCU_REFRESH_2X_MODE_MSK (0x0000000C) + #define PCU_CR_DDR_PTM_CTL_PCU_REFRESH_2X_MODE_MAX (0x00000003) + #define PCU_CR_DDR_PTM_CTL_PCU_REFRESH_2X_MODE_DEF (0x00000000) + #define PCU_CR_DDR_PTM_CTL_PCU_EXTTS_ENABLE_OFF ( 4) + #define PCU_CR_DDR_PTM_CTL_PCU_EXTTS_ENABLE_WID ( 1) + #define PCU_CR_DDR_PTM_CTL_PCU_EXTTS_ENABLE_MSK (0x00000010) + #define PCU_CR_DDR_PTM_CTL_PCU_EXTTS_ENABLE_MAX (0x00000001) + #define PCU_CR_DDR_PTM_CTL_PCU_EXTTS_ENABLE_DEF (0x00000000) + #define PCU_CR_DDR_PTM_CTL_PCU_LOCK_PTM_REGS_PCU_OFF ( 5) + #define PCU_CR_DDR_PTM_CTL_PCU_LOCK_PTM_REGS_PCU_WID ( 1) + #define PCU_CR_DDR_PTM_CTL_PCU_LOCK_PTM_REGS_PCU_MSK (0x00000020) + #define PCU_CR_DDR_PTM_CTL_PCU_LOCK_PTM_REGS_PCU_MAX (0x00000001) + #define PCU_CR_DDR_PTM_CTL_PCU_LOCK_PTM_REGS_PCU_DEF (0x00000000) + #define PCU_CR_DDR_PTM_CTL_PCU_PDWN_CONFIG_CTL_OFF ( 6) + #define PCU_CR_DDR_PTM_CTL_PCU_PDWN_CONFIG_CTL_WID ( 1) + #define PCU_CR_DDR_PTM_CTL_PCU_PDWN_CONFIG_CTL_MSK (0x00000040) + #define PCU_CR_DDR_PTM_CTL_PCU_PDWN_CONFIG_CTL_MAX (0x00000001) + #define PCU_CR_DDR_PTM_CTL_PCU_PDWN_CONFIG_CTL_DEF (0x00000000) + #define PCU_CR_DDR_PTM_CTL_PCU_DISABLE_DRAM_TS_OFF ( 7) + #define PCU_CR_DDR_PTM_CTL_PCU_DISABLE_DRAM_TS_WID ( 1) + #define PCU_CR_DDR_PTM_CTL_PCU_DISABLE_DRAM_TS_MSK (0x00000080) + #define PCU_CR_DDR_PTM_CTL_PCU_DISABLE_DRAM_TS_MAX (0x00000001) + #define PCU_CR_DDR_PTM_CTL_PCU_DISABLE_DRAM_TS_DEF (0x00000000) + +#define PCU_CR_DDR_ENERGY_SCALEFACTOR_PCU_REG (0x00005884) + #define PCU_CR_DDR_ENERGY_SCALEFACTOR_PCU_SCALEFACTOR_OFF ( 0) + #define PCU_CR_DDR_ENERGY_SCALEFACTOR_PCU_SCALEFACTOR_WID ( 3) + #define PCU_CR_DDR_ENERGY_SCALEFACTOR_PCU_SCALEFACTOR_MSK (0x00000007) + #define PCU_CR_DDR_ENERGY_SCALEFACTOR_PCU_SCALEFACTOR_MAX (0x00000007) + #define PCU_CR_DDR_ENERGY_SCALEFACTOR_PCU_SCALEFACTOR_DEF (0x00000003) + +#define PCU_CR_DDR_RAPL_CHANNEL_POWER_FLOOR_PCU_REG (0x00005888) + #define PCU_CR_DDR_RAPL_CHANNEL_POWER_FLOOR_PCU_CH0_OFF ( 0) + #define PCU_CR_DDR_RAPL_CHANNEL_POWER_FLOOR_PCU_CH0_WID ( 8) + #define PCU_CR_DDR_RAPL_CHANNEL_POWER_FLOOR_PCU_CH0_MSK (0x000000FF) + #define PCU_CR_DDR_RAPL_CHANNEL_POWER_FLOOR_PCU_CH0_MAX (0x000000FF) + #define PCU_CR_DDR_RAPL_CHANNEL_POWER_FLOOR_PCU_CH0_DEF (0x00000000) + #define PCU_CR_DDR_RAPL_CHANNEL_POWER_FLOOR_PCU_CH1_OFF ( 8) + #define PCU_CR_DDR_RAPL_CHANNEL_POWER_FLOOR_PCU_CH1_WID ( 8) + #define PCU_CR_DDR_RAPL_CHANNEL_POWER_FLOOR_PCU_CH1_MSK (0x0000FF00) + #define PCU_CR_DDR_RAPL_CHANNEL_POWER_FLOOR_PCU_CH1_MAX (0x000000FF) + #define PCU_CR_DDR_RAPL_CHANNEL_POWER_FLOOR_PCU_CH1_DEF (0x00000000) + +#define PCU_CR_DDR_THERM_PERDIMM_STATUS_PCU_REG (0x0000588C) + #define PCU_CR_DDR_THERM_PERDIMM_STATUS_PCU_CH0_DIMM0_OFF ( 0) + #define PCU_CR_DDR_THERM_PERDIMM_STATUS_PCU_CH0_DIMM0_WID ( 2) + #define PCU_CR_DDR_THERM_PERDIMM_STATUS_PCU_CH0_DIMM0_MSK (0x00000003) + #define PCU_CR_DDR_THERM_PERDIMM_STATUS_PCU_CH0_DIMM0_MAX (0x00000003) + #define PCU_CR_DDR_THERM_PERDIMM_STATUS_PCU_CH0_DIMM0_DEF (0x00000000) + #define PCU_CR_DDR_THERM_PERDIMM_STATUS_PCU_CH0_DIMM1_OFF ( 2) + #define PCU_CR_DDR_THERM_PERDIMM_STATUS_PCU_CH0_DIMM1_WID ( 2) + #define PCU_CR_DDR_THERM_PERDIMM_STATUS_PCU_CH0_DIMM1_MSK (0x0000000C) + #define PCU_CR_DDR_THERM_PERDIMM_STATUS_PCU_CH0_DIMM1_MAX (0x00000003) + #define PCU_CR_DDR_THERM_PERDIMM_STATUS_PCU_CH0_DIMM1_DEF (0x00000000) + #define PCU_CR_DDR_THERM_PERDIMM_STATUS_PCU_CH1_DIMM0_OFF ( 8) + #define PCU_CR_DDR_THERM_PERDIMM_STATUS_PCU_CH1_DIMM0_WID ( 2) + #define PCU_CR_DDR_THERM_PERDIMM_STATUS_PCU_CH1_DIMM0_MSK (0x00000300) + #define PCU_CR_DDR_THERM_PERDIMM_STATUS_PCU_CH1_DIMM0_MAX (0x00000003) + #define PCU_CR_DDR_THERM_PERDIMM_STATUS_PCU_CH1_DIMM0_DEF (0x00000000) + #define PCU_CR_DDR_THERM_PERDIMM_STATUS_PCU_CH1_DIMM1_OFF (10) + #define PCU_CR_DDR_THERM_PERDIMM_STATUS_PCU_CH1_DIMM1_WID ( 2) + #define PCU_CR_DDR_THERM_PERDIMM_STATUS_PCU_CH1_DIMM1_MSK (0x00000C00) + #define PCU_CR_DDR_THERM_PERDIMM_STATUS_PCU_CH1_DIMM1_MAX (0x00000003) + #define PCU_CR_DDR_THERM_PERDIMM_STATUS_PCU_CH1_DIMM1_DEF (0x00000000) + +#define PCU_CR_DDR_WARM_THRESHOLD_CH0_PCU_REG (0x00005890) + #define PCU_CR_DDR_WARM_THRESHOLD_CH0_PCU_DIMM0_OFF ( 0) + #define PCU_CR_DDR_WARM_THRESHOLD_CH0_PCU_DIMM0_WID ( 8) + #define PCU_CR_DDR_WARM_THRESHOLD_CH0_PCU_DIMM0_MSK (0x000000FF) + #define PCU_CR_DDR_WARM_THRESHOLD_CH0_PCU_DIMM0_MAX (0x000000FF) + #define PCU_CR_DDR_WARM_THRESHOLD_CH0_PCU_DIMM0_DEF (0x000000FF) + #define PCU_CR_DDR_WARM_THRESHOLD_CH0_PCU_DIMM1_OFF ( 8) + #define PCU_CR_DDR_WARM_THRESHOLD_CH0_PCU_DIMM1_WID ( 8) + #define PCU_CR_DDR_WARM_THRESHOLD_CH0_PCU_DIMM1_MSK (0x0000FF00) + #define PCU_CR_DDR_WARM_THRESHOLD_CH0_PCU_DIMM1_MAX (0x000000FF) + #define PCU_CR_DDR_WARM_THRESHOLD_CH0_PCU_DIMM1_DEF (0x000000FF) + +#define PCU_CR_DDR_WARM_THRESHOLD_CH1_PCU_REG (0x00005894) + #define PCU_CR_DDR_WARM_THRESHOLD_CH1_PCU_DIMM0_OFF ( 0) + #define PCU_CR_DDR_WARM_THRESHOLD_CH1_PCU_DIMM0_WID ( 8) + #define PCU_CR_DDR_WARM_THRESHOLD_CH1_PCU_DIMM0_MSK (0x000000FF) + #define PCU_CR_DDR_WARM_THRESHOLD_CH1_PCU_DIMM0_MAX (0x000000FF) + #define PCU_CR_DDR_WARM_THRESHOLD_CH1_PCU_DIMM0_DEF (0x000000FF) + #define PCU_CR_DDR_WARM_THRESHOLD_CH1_PCU_DIMM1_OFF ( 8) + #define PCU_CR_DDR_WARM_THRESHOLD_CH1_PCU_DIMM1_WID ( 8) + #define PCU_CR_DDR_WARM_THRESHOLD_CH1_PCU_DIMM1_MSK (0x0000FF00) + #define PCU_CR_DDR_WARM_THRESHOLD_CH1_PCU_DIMM1_MAX (0x000000FF) + #define PCU_CR_DDR_WARM_THRESHOLD_CH1_PCU_DIMM1_DEF (0x000000FF) + +#define PCU_CR_DDR_HOT_THRESHOLD_CH0_PCU_REG (0x00005898) + #define PCU_CR_DDR_HOT_THRESHOLD_CH0_PCU_DIMM0_OFF ( 0) + #define PCU_CR_DDR_HOT_THRESHOLD_CH0_PCU_DIMM0_WID ( 8) + #define PCU_CR_DDR_HOT_THRESHOLD_CH0_PCU_DIMM0_MSK (0x000000FF) + #define PCU_CR_DDR_HOT_THRESHOLD_CH0_PCU_DIMM0_MAX (0x000000FF) + #define PCU_CR_DDR_HOT_THRESHOLD_CH0_PCU_DIMM0_DEF (0x000000FF) + #define PCU_CR_DDR_HOT_THRESHOLD_CH0_PCU_DIMM1_OFF ( 8) + #define PCU_CR_DDR_HOT_THRESHOLD_CH0_PCU_DIMM1_WID ( 8) + #define PCU_CR_DDR_HOT_THRESHOLD_CH0_PCU_DIMM1_MSK (0x0000FF00) + #define PCU_CR_DDR_HOT_THRESHOLD_CH0_PCU_DIMM1_MAX (0x000000FF) + #define PCU_CR_DDR_HOT_THRESHOLD_CH0_PCU_DIMM1_DEF (0x000000FF) + +#define PCU_CR_DDR_HOT_THRESHOLD_CH1_PCU_REG (0x0000589C) + #define PCU_CR_DDR_HOT_THRESHOLD_CH1_PCU_DIMM0_OFF ( 0) + #define PCU_CR_DDR_HOT_THRESHOLD_CH1_PCU_DIMM0_WID ( 8) + #define PCU_CR_DDR_HOT_THRESHOLD_CH1_PCU_DIMM0_MSK (0x000000FF) + #define PCU_CR_DDR_HOT_THRESHOLD_CH1_PCU_DIMM0_MAX (0x000000FF) + #define PCU_CR_DDR_HOT_THRESHOLD_CH1_PCU_DIMM0_DEF (0x000000FF) + #define PCU_CR_DDR_HOT_THRESHOLD_CH1_PCU_DIMM1_OFF ( 8) + #define PCU_CR_DDR_HOT_THRESHOLD_CH1_PCU_DIMM1_WID ( 8) + #define PCU_CR_DDR_HOT_THRESHOLD_CH1_PCU_DIMM1_MSK (0x0000FF00) + #define PCU_CR_DDR_HOT_THRESHOLD_CH1_PCU_DIMM1_MAX (0x000000FF) + #define PCU_CR_DDR_HOT_THRESHOLD_CH1_PCU_DIMM1_DEF (0x000000FF) + +#define PCU_CR_DDR_THERM_CAMARILLO_INTERRUPT_PCU_REG (0x000058A0) + #define PCU_CR_DDR_THERM_CAMARILLO_INTERRUPT_PCU_ENABLE_WARM_INTERRUPT_OFF ( 0) + #define PCU_CR_DDR_THERM_CAMARILLO_INTERRUPT_PCU_ENABLE_WARM_INTERRUPT_WID ( 1) + #define PCU_CR_DDR_THERM_CAMARILLO_INTERRUPT_PCU_ENABLE_WARM_INTERRUPT_MSK (0x00000001) + #define PCU_CR_DDR_THERM_CAMARILLO_INTERRUPT_PCU_ENABLE_WARM_INTERRUPT_MAX (0x00000001) + #define PCU_CR_DDR_THERM_CAMARILLO_INTERRUPT_PCU_ENABLE_WARM_INTERRUPT_DEF (0x00000000) + #define PCU_CR_DDR_THERM_CAMARILLO_INTERRUPT_PCU_ENABLE_HOT_INTERRUPT_OFF ( 2) + #define PCU_CR_DDR_THERM_CAMARILLO_INTERRUPT_PCU_ENABLE_HOT_INTERRUPT_WID ( 1) + #define PCU_CR_DDR_THERM_CAMARILLO_INTERRUPT_PCU_ENABLE_HOT_INTERRUPT_MSK (0x00000004) + #define PCU_CR_DDR_THERM_CAMARILLO_INTERRUPT_PCU_ENABLE_HOT_INTERRUPT_MAX (0x00000001) + #define PCU_CR_DDR_THERM_CAMARILLO_INTERRUPT_PCU_ENABLE_HOT_INTERRUPT_DEF (0x00000000) + #define PCU_CR_DDR_THERM_CAMARILLO_INTERRUPT_PCU_ENABLE_2X_REFRESH_INTERRUPT_OFF ( 4) + #define PCU_CR_DDR_THERM_CAMARILLO_INTERRUPT_PCU_ENABLE_2X_REFRESH_INTERRUPT_WID ( 1) + #define PCU_CR_DDR_THERM_CAMARILLO_INTERRUPT_PCU_ENABLE_2X_REFRESH_INTERRUPT_MSK (0x00000010) + #define PCU_CR_DDR_THERM_CAMARILLO_INTERRUPT_PCU_ENABLE_2X_REFRESH_INTERRUPT_MAX (0x00000001) + #define PCU_CR_DDR_THERM_CAMARILLO_INTERRUPT_PCU_ENABLE_2X_REFRESH_INTERRUPT_DEF (0x00000000) + #define PCU_CR_DDR_THERM_CAMARILLO_INTERRUPT_PCU_ENABLE_THRESHOLD1_INTERRUPT_OFF ( 8) + #define PCU_CR_DDR_THERM_CAMARILLO_INTERRUPT_PCU_ENABLE_THRESHOLD1_INTERRUPT_WID ( 1) + #define PCU_CR_DDR_THERM_CAMARILLO_INTERRUPT_PCU_ENABLE_THRESHOLD1_INTERRUPT_MSK (0x00000100) + #define PCU_CR_DDR_THERM_CAMARILLO_INTERRUPT_PCU_ENABLE_THRESHOLD1_INTERRUPT_MAX (0x00000001) + #define PCU_CR_DDR_THERM_CAMARILLO_INTERRUPT_PCU_ENABLE_THRESHOLD1_INTERRUPT_DEF (0x00000000) + #define PCU_CR_DDR_THERM_CAMARILLO_INTERRUPT_PCU_ENABLE_THRESHOLD2_INTERRUPT_OFF (10) + #define PCU_CR_DDR_THERM_CAMARILLO_INTERRUPT_PCU_ENABLE_THRESHOLD2_INTERRUPT_WID ( 1) + #define PCU_CR_DDR_THERM_CAMARILLO_INTERRUPT_PCU_ENABLE_THRESHOLD2_INTERRUPT_MSK (0x00000400) + #define PCU_CR_DDR_THERM_CAMARILLO_INTERRUPT_PCU_ENABLE_THRESHOLD2_INTERRUPT_MAX (0x00000001) + #define PCU_CR_DDR_THERM_CAMARILLO_INTERRUPT_PCU_ENABLE_THRESHOLD2_INTERRUPT_DEF (0x00000000) + #define PCU_CR_DDR_THERM_CAMARILLO_INTERRUPT_PCU_POLICY_FREE_THRESHOLD1_OFF (16) + #define PCU_CR_DDR_THERM_CAMARILLO_INTERRUPT_PCU_POLICY_FREE_THRESHOLD1_WID ( 8) + #define PCU_CR_DDR_THERM_CAMARILLO_INTERRUPT_PCU_POLICY_FREE_THRESHOLD1_MSK (0x00FF0000) + #define PCU_CR_DDR_THERM_CAMARILLO_INTERRUPT_PCU_POLICY_FREE_THRESHOLD1_MAX (0x000000FF) + #define PCU_CR_DDR_THERM_CAMARILLO_INTERRUPT_PCU_POLICY_FREE_THRESHOLD1_DEF (0x00000000) + #define PCU_CR_DDR_THERM_CAMARILLO_INTERRUPT_PCU_POLICY_FREE_THRESHOLD2_OFF (24) + #define PCU_CR_DDR_THERM_CAMARILLO_INTERRUPT_PCU_POLICY_FREE_THRESHOLD2_WID ( 8) + #define PCU_CR_DDR_THERM_CAMARILLO_INTERRUPT_PCU_POLICY_FREE_THRESHOLD2_MSK (0xFF000000) + #define PCU_CR_DDR_THERM_CAMARILLO_INTERRUPT_PCU_POLICY_FREE_THRESHOLD2_MAX (0x000000FF) + #define PCU_CR_DDR_THERM_CAMARILLO_INTERRUPT_PCU_POLICY_FREE_THRESHOLD2_DEF (0x00000000) + +#define PCU_CR_DDR_VOLTAGE_PCU_REG (0x000058A4) + #define PCU_CR_DDR_VOLTAGE_PCU_DDR_VOLTAGE_OFF ( 0) + #define PCU_CR_DDR_VOLTAGE_PCU_DDR_VOLTAGE_WID ( 3) + #define PCU_CR_DDR_VOLTAGE_PCU_DDR_VOLTAGE_MSK (0x00000007) + #define PCU_CR_DDR_VOLTAGE_PCU_DDR_VOLTAGE_MAX (0x00000007) + #define PCU_CR_DDR_VOLTAGE_PCU_DDR_VOLTAGE_DEF (0x00000000) + +#define PCU_CR_PACKAGE_THERM_MARGIN_PCU_REG (0x000058A8) + #define PCU_CR_PACKAGE_THERM_MARGIN_PCU_THERM_MARGIN_OFF ( 0) + #define PCU_CR_PACKAGE_THERM_MARGIN_PCU_THERM_MARGIN_WID (16) + #define PCU_CR_PACKAGE_THERM_MARGIN_PCU_THERM_MARGIN_MSK (0x0000FFFF) + #define PCU_CR_PACKAGE_THERM_MARGIN_PCU_THERM_MARGIN_MAX (0x0000FFFF) + #define PCU_CR_PACKAGE_THERM_MARGIN_PCU_THERM_MARGIN_DEF (0x00007F00) + +#define PCU_CR_DDR_DIMM_TEMPERATURE_CH0_PCU_REG (0x000058B0) + #define PCU_CR_DDR_DIMM_TEMPERATURE_CH0_PCU_DIMM0_OFF ( 0) + #define PCU_CR_DDR_DIMM_TEMPERATURE_CH0_PCU_DIMM0_WID ( 8) + #define PCU_CR_DDR_DIMM_TEMPERATURE_CH0_PCU_DIMM0_MSK (0x000000FF) + #define PCU_CR_DDR_DIMM_TEMPERATURE_CH0_PCU_DIMM0_MAX (0x000000FF) + #define PCU_CR_DDR_DIMM_TEMPERATURE_CH0_PCU_DIMM0_DEF (0x00000000) + #define PCU_CR_DDR_DIMM_TEMPERATURE_CH0_PCU_DIMM1_OFF ( 8) + #define PCU_CR_DDR_DIMM_TEMPERATURE_CH0_PCU_DIMM1_WID ( 8) + #define PCU_CR_DDR_DIMM_TEMPERATURE_CH0_PCU_DIMM1_MSK (0x0000FF00) + #define PCU_CR_DDR_DIMM_TEMPERATURE_CH0_PCU_DIMM1_MAX (0x000000FF) + #define PCU_CR_DDR_DIMM_TEMPERATURE_CH0_PCU_DIMM1_DEF (0x00000000) + +#define PCU_CR_DDR_DIMM_TEMPERATURE_CH1_PCU_REG (0x000058B4) + #define PCU_CR_DDR_DIMM_TEMPERATURE_CH1_PCU_DIMM0_OFF ( 0) + #define PCU_CR_DDR_DIMM_TEMPERATURE_CH1_PCU_DIMM0_WID ( 8) + #define PCU_CR_DDR_DIMM_TEMPERATURE_CH1_PCU_DIMM0_MSK (0x000000FF) + #define PCU_CR_DDR_DIMM_TEMPERATURE_CH1_PCU_DIMM0_MAX (0x000000FF) + #define PCU_CR_DDR_DIMM_TEMPERATURE_CH1_PCU_DIMM0_DEF (0x00000000) + #define PCU_CR_DDR_DIMM_TEMPERATURE_CH1_PCU_DIMM1_OFF ( 8) + #define PCU_CR_DDR_DIMM_TEMPERATURE_CH1_PCU_DIMM1_WID ( 8) + #define PCU_CR_DDR_DIMM_TEMPERATURE_CH1_PCU_DIMM1_MSK (0x0000FF00) + #define PCU_CR_DDR_DIMM_TEMPERATURE_CH1_PCU_DIMM1_MAX (0x000000FF) + #define PCU_CR_DDR_DIMM_TEMPERATURE_CH1_PCU_DIMM1_DEF (0x00000000) + +#define PCU_CR_DDR_DIMM_HOTTEST_ABSOLUTE_PCU_REG (0x000058B8) + #define PCU_CR_DDR_DIMM_HOTTEST_ABSOLUTE_PCU_TEMPERATURE_OFF ( 0) + #define PCU_CR_DDR_DIMM_HOTTEST_ABSOLUTE_PCU_TEMPERATURE_WID ( 8) + #define PCU_CR_DDR_DIMM_HOTTEST_ABSOLUTE_PCU_TEMPERATURE_MSK (0x000000FF) + #define PCU_CR_DDR_DIMM_HOTTEST_ABSOLUTE_PCU_TEMPERATURE_MAX (0x000000FF) + #define PCU_CR_DDR_DIMM_HOTTEST_ABSOLUTE_PCU_TEMPERATURE_DEF (0x00000000) + +#define PCU_CR_DDR_DIMM_HOTTEST_RELATIVE_PCU_REG (0x000058BC) + #define PCU_CR_DDR_DIMM_HOTTEST_RELATIVE_PCU_TEMPERATURE_OFF ( 0) + #define PCU_CR_DDR_DIMM_HOTTEST_RELATIVE_PCU_TEMPERATURE_WID ( 8) + #define PCU_CR_DDR_DIMM_HOTTEST_RELATIVE_PCU_TEMPERATURE_MSK (0x000000FF) + #define PCU_CR_DDR_DIMM_HOTTEST_RELATIVE_PCU_TEMPERATURE_MAX (0x000000FF) + #define PCU_CR_DDR_DIMM_HOTTEST_RELATIVE_PCU_TEMPERATURE_DEF (0x0000007F) + +#define PCU_CR_DDR_THROTTLE_DURATION_CH0_PCU_REG (0x000058C0) + #define PCU_CR_DDR_THROTTLE_DURATION_CH0_PCU_DIMM0_OFF ( 0) + #define PCU_CR_DDR_THROTTLE_DURATION_CH0_PCU_DIMM0_WID (16) + #define PCU_CR_DDR_THROTTLE_DURATION_CH0_PCU_DIMM0_MSK (0x0000FFFF) + #define PCU_CR_DDR_THROTTLE_DURATION_CH0_PCU_DIMM0_MAX (0x0000FFFF) + #define PCU_CR_DDR_THROTTLE_DURATION_CH0_PCU_DIMM0_DEF (0x00000000) + #define PCU_CR_DDR_THROTTLE_DURATION_CH0_PCU_DIMM1_OFF (16) + #define PCU_CR_DDR_THROTTLE_DURATION_CH0_PCU_DIMM1_WID (16) + #define PCU_CR_DDR_THROTTLE_DURATION_CH0_PCU_DIMM1_MSK (0xFFFF0000) + #define PCU_CR_DDR_THROTTLE_DURATION_CH0_PCU_DIMM1_MAX (0x0000FFFF) + #define PCU_CR_DDR_THROTTLE_DURATION_CH0_PCU_DIMM1_DEF (0x00000000) + +#define PCU_CR_DDR_THROTTLE_DURATION_CH1_PCU_REG (0x000058C8) + #define PCU_CR_DDR_THROTTLE_DURATION_CH1_PCU_DIMM0_OFF ( 0) + #define PCU_CR_DDR_THROTTLE_DURATION_CH1_PCU_DIMM0_WID (16) + #define PCU_CR_DDR_THROTTLE_DURATION_CH1_PCU_DIMM0_MSK (0x0000FFFF) + #define PCU_CR_DDR_THROTTLE_DURATION_CH1_PCU_DIMM0_MAX (0x0000FFFF) + #define PCU_CR_DDR_THROTTLE_DURATION_CH1_PCU_DIMM0_DEF (0x00000000) + #define PCU_CR_DDR_THROTTLE_DURATION_CH1_PCU_DIMM1_OFF (16) + #define PCU_CR_DDR_THROTTLE_DURATION_CH1_PCU_DIMM1_WID (16) + #define PCU_CR_DDR_THROTTLE_DURATION_CH1_PCU_DIMM1_MSK (0xFFFF0000) + #define PCU_CR_DDR_THROTTLE_DURATION_CH1_PCU_DIMM1_MAX (0x0000FFFF) + #define PCU_CR_DDR_THROTTLE_DURATION_CH1_PCU_DIMM1_DEF (0x00000000) + +#define PCU_CR_DDR_WARM_BUDGET_CH0_PCU_REG (0x000058D0) + #define PCU_CR_DDR_WARM_BUDGET_CH0_PCU_DIMM0_OFF ( 0) + #define PCU_CR_DDR_WARM_BUDGET_CH0_PCU_DIMM0_WID ( 8) + #define PCU_CR_DDR_WARM_BUDGET_CH0_PCU_DIMM0_MSK (0x000000FF) + #define PCU_CR_DDR_WARM_BUDGET_CH0_PCU_DIMM0_MAX (0x000000FF) + #define PCU_CR_DDR_WARM_BUDGET_CH0_PCU_DIMM0_DEF (0x000000FF) + #define PCU_CR_DDR_WARM_BUDGET_CH0_PCU_DIMM1_OFF ( 8) + #define PCU_CR_DDR_WARM_BUDGET_CH0_PCU_DIMM1_WID ( 8) + #define PCU_CR_DDR_WARM_BUDGET_CH0_PCU_DIMM1_MSK (0x0000FF00) + #define PCU_CR_DDR_WARM_BUDGET_CH0_PCU_DIMM1_MAX (0x000000FF) + #define PCU_CR_DDR_WARM_BUDGET_CH0_PCU_DIMM1_DEF (0x000000FF) + +#define PCU_CR_DDR_WARM_BUDGET_CH1_PCU_REG (0x000058D4) + #define PCU_CR_DDR_WARM_BUDGET_CH1_PCU_DIMM0_OFF ( 0) + #define PCU_CR_DDR_WARM_BUDGET_CH1_PCU_DIMM0_WID ( 8) + #define PCU_CR_DDR_WARM_BUDGET_CH1_PCU_DIMM0_MSK (0x000000FF) + #define PCU_CR_DDR_WARM_BUDGET_CH1_PCU_DIMM0_MAX (0x000000FF) + #define PCU_CR_DDR_WARM_BUDGET_CH1_PCU_DIMM0_DEF (0x000000FF) + #define PCU_CR_DDR_WARM_BUDGET_CH1_PCU_DIMM1_OFF ( 8) + #define PCU_CR_DDR_WARM_BUDGET_CH1_PCU_DIMM1_WID ( 8) + #define PCU_CR_DDR_WARM_BUDGET_CH1_PCU_DIMM1_MSK (0x0000FF00) + #define PCU_CR_DDR_WARM_BUDGET_CH1_PCU_DIMM1_MAX (0x000000FF) + #define PCU_CR_DDR_WARM_BUDGET_CH1_PCU_DIMM1_DEF (0x000000FF) + +#define PCU_CR_DDR_HOT_BUDGET_CH0_PCU_REG (0x000058D8) + #define PCU_CR_DDR_HOT_BUDGET_CH0_PCU_DIMM0_OFF ( 0) + #define PCU_CR_DDR_HOT_BUDGET_CH0_PCU_DIMM0_WID ( 8) + #define PCU_CR_DDR_HOT_BUDGET_CH0_PCU_DIMM0_MSK (0x000000FF) + #define PCU_CR_DDR_HOT_BUDGET_CH0_PCU_DIMM0_MAX (0x000000FF) + #define PCU_CR_DDR_HOT_BUDGET_CH0_PCU_DIMM0_DEF (0x000000FF) + #define PCU_CR_DDR_HOT_BUDGET_CH0_PCU_DIMM1_OFF ( 8) + #define PCU_CR_DDR_HOT_BUDGET_CH0_PCU_DIMM1_WID ( 8) + #define PCU_CR_DDR_HOT_BUDGET_CH0_PCU_DIMM1_MSK (0x0000FF00) + #define PCU_CR_DDR_HOT_BUDGET_CH0_PCU_DIMM1_MAX (0x000000FF) + #define PCU_CR_DDR_HOT_BUDGET_CH0_PCU_DIMM1_DEF (0x000000FF) + +#define PCU_CR_DDR_HOT_BUDGET_CH1_PCU_REG (0x000058DC) + #define PCU_CR_DDR_HOT_BUDGET_CH1_PCU_DIMM0_OFF ( 0) + #define PCU_CR_DDR_HOT_BUDGET_CH1_PCU_DIMM0_WID ( 8) + #define PCU_CR_DDR_HOT_BUDGET_CH1_PCU_DIMM0_MSK (0x000000FF) + #define PCU_CR_DDR_HOT_BUDGET_CH1_PCU_DIMM0_MAX (0x000000FF) + #define PCU_CR_DDR_HOT_BUDGET_CH1_PCU_DIMM0_DEF (0x000000FF) + #define PCU_CR_DDR_HOT_BUDGET_CH1_PCU_DIMM1_OFF ( 8) + #define PCU_CR_DDR_HOT_BUDGET_CH1_PCU_DIMM1_WID ( 8) + #define PCU_CR_DDR_HOT_BUDGET_CH1_PCU_DIMM1_MSK (0x0000FF00) + #define PCU_CR_DDR_HOT_BUDGET_CH1_PCU_DIMM1_MAX (0x000000FF) + #define PCU_CR_DDR_HOT_BUDGET_CH1_PCU_DIMM1_DEF (0x000000FF) + +#define PCU_CR_DDR_RAPL_LIMIT_PCU_REG (0x000058E0) + #define PCU_CR_DDR_RAPL_LIMIT_PCU_LIMIT1_POWER_OFF ( 0) + #define PCU_CR_DDR_RAPL_LIMIT_PCU_LIMIT1_POWER_WID (15) + #define PCU_CR_DDR_RAPL_LIMIT_PCU_LIMIT1_POWER_MSK (0x00007FFF) + #define PCU_CR_DDR_RAPL_LIMIT_PCU_LIMIT1_POWER_MAX (0x00007FFF) + #define PCU_CR_DDR_RAPL_LIMIT_PCU_LIMIT1_POWER_DEF (0x00000000) + #define PCU_CR_DDR_RAPL_LIMIT_PCU_LIMIT1_ENABLE_OFF (15) + #define PCU_CR_DDR_RAPL_LIMIT_PCU_LIMIT1_ENABLE_WID ( 1) + #define PCU_CR_DDR_RAPL_LIMIT_PCU_LIMIT1_ENABLE_MSK (0x00008000) + #define PCU_CR_DDR_RAPL_LIMIT_PCU_LIMIT1_ENABLE_MAX (0x00000001) + #define PCU_CR_DDR_RAPL_LIMIT_PCU_LIMIT1_ENABLE_DEF (0x00000000) + #define PCU_CR_DDR_RAPL_LIMIT_PCU_LIMIT1_TIME_WINDOW_Y_OFF (17) + #define PCU_CR_DDR_RAPL_LIMIT_PCU_LIMIT1_TIME_WINDOW_Y_WID ( 5) + #define PCU_CR_DDR_RAPL_LIMIT_PCU_LIMIT1_TIME_WINDOW_Y_MSK (0x003E0000) + #define PCU_CR_DDR_RAPL_LIMIT_PCU_LIMIT1_TIME_WINDOW_Y_MAX (0x0000001F) + #define PCU_CR_DDR_RAPL_LIMIT_PCU_LIMIT1_TIME_WINDOW_Y_DEF (0x00000000) + #define PCU_CR_DDR_RAPL_LIMIT_PCU_LIMIT1_TIME_WINDOW_X_OFF (22) + #define PCU_CR_DDR_RAPL_LIMIT_PCU_LIMIT1_TIME_WINDOW_X_WID ( 2) + #define PCU_CR_DDR_RAPL_LIMIT_PCU_LIMIT1_TIME_WINDOW_X_MSK (0x00C00000) + #define PCU_CR_DDR_RAPL_LIMIT_PCU_LIMIT1_TIME_WINDOW_X_MAX (0x00000003) + #define PCU_CR_DDR_RAPL_LIMIT_PCU_LIMIT1_TIME_WINDOW_X_DEF (0x00000000) + #define PCU_CR_DDR_RAPL_LIMIT_PCU_LIMIT2_POWER_OFF (32) + #define PCU_CR_DDR_RAPL_LIMIT_PCU_LIMIT2_POWER_WID (15) + #define PCU_CR_DDR_RAPL_LIMIT_PCU_LIMIT2_POWER_MSK (0x7FFF00000000) + #define PCU_CR_DDR_RAPL_LIMIT_PCU_LIMIT2_POWER_MAX (0x00007FFF) + #define PCU_CR_DDR_RAPL_LIMIT_PCU_LIMIT2_POWER_DEF (0x00000000) + #define PCU_CR_DDR_RAPL_LIMIT_PCU_LIMIT2_ENABLE_OFF (47) + #define PCU_CR_DDR_RAPL_LIMIT_PCU_LIMIT2_ENABLE_WID ( 1) + #define PCU_CR_DDR_RAPL_LIMIT_PCU_LIMIT2_ENABLE_MSK (0x800000000000) + #define PCU_CR_DDR_RAPL_LIMIT_PCU_LIMIT2_ENABLE_MAX (0x00000001) + #define PCU_CR_DDR_RAPL_LIMIT_PCU_LIMIT2_ENABLE_DEF (0x00000000) + #define PCU_CR_DDR_RAPL_LIMIT_PCU_LIMIT2_TIME_WINDOW_Y_OFF (49) + #define PCU_CR_DDR_RAPL_LIMIT_PCU_LIMIT2_TIME_WINDOW_Y_WID ( 5) + #define PCU_CR_DDR_RAPL_LIMIT_PCU_LIMIT2_TIME_WINDOW_Y_MSK (0x3E000000000000) + #define PCU_CR_DDR_RAPL_LIMIT_PCU_LIMIT2_TIME_WINDOW_Y_MAX (0x0000001F) + #define PCU_CR_DDR_RAPL_LIMIT_PCU_LIMIT2_TIME_WINDOW_Y_DEF (0x00000000) + #define PCU_CR_DDR_RAPL_LIMIT_PCU_LIMIT2_TIME_WINDOW_X_OFF (54) + #define PCU_CR_DDR_RAPL_LIMIT_PCU_LIMIT2_TIME_WINDOW_X_WID ( 2) + #define PCU_CR_DDR_RAPL_LIMIT_PCU_LIMIT2_TIME_WINDOW_X_MSK (0xC0000000000000) + #define PCU_CR_DDR_RAPL_LIMIT_PCU_LIMIT2_TIME_WINDOW_X_MAX (0x00000003) + #define PCU_CR_DDR_RAPL_LIMIT_PCU_LIMIT2_TIME_WINDOW_X_DEF (0x00000000) + #define PCU_CR_DDR_RAPL_LIMIT_PCU_LOCKED_OFF (63) + #define PCU_CR_DDR_RAPL_LIMIT_PCU_LOCKED_WID ( 1) + #define PCU_CR_DDR_RAPL_LIMIT_PCU_LOCKED_MSK (0x8000000000000000) + #define PCU_CR_DDR_RAPL_LIMIT_PCU_LOCKED_MAX (0x00000001) + #define PCU_CR_DDR_RAPL_LIMIT_PCU_LOCKED_DEF (0x00000000) + +#define PCU_CR_DDR_ENERGY_STATUS_PCU_REG (0x000058E8) + #define PCU_CR_DDR_ENERGY_STATUS_PCU_JOULES_CONSUMED_OFF ( 0) + #define PCU_CR_DDR_ENERGY_STATUS_PCU_JOULES_CONSUMED_WID (32) + #define PCU_CR_DDR_ENERGY_STATUS_PCU_JOULES_CONSUMED_MSK (0xFFFFFFFF) + #define PCU_CR_DDR_ENERGY_STATUS_PCU_JOULES_CONSUMED_MAX (0xFFFFFFFF) + #define PCU_CR_DDR_ENERGY_STATUS_PCU_JOULES_CONSUMED_DEF (0x00000000) + +#define PCU_CR_DDR_RAPL_PERF_STATUS_PCU_REG (0x000058EC) + #define PCU_CR_DDR_RAPL_PERF_STATUS_PCU_DURATION_OFF ( 0) + #define PCU_CR_DDR_RAPL_PERF_STATUS_PCU_DURATION_WID (32) + #define PCU_CR_DDR_RAPL_PERF_STATUS_PCU_DURATION_MSK (0xFFFFFFFF) + #define PCU_CR_DDR_RAPL_PERF_STATUS_PCU_DURATION_MAX (0xFFFFFFFF) + #define PCU_CR_DDR_RAPL_PERF_STATUS_PCU_DURATION_DEF (0x00000000) + +#define PCU_CR_PACKAGE_RAPL_PERF_STATUS_PCU_REG (0x000058F0) + #define PCU_CR_PACKAGE_RAPL_PERF_STATUS_PCU_COUNTS_OFF ( 0) + #define PCU_CR_PACKAGE_RAPL_PERF_STATUS_PCU_COUNTS_WID (32) + #define PCU_CR_PACKAGE_RAPL_PERF_STATUS_PCU_COUNTS_MSK (0xFFFFFFFF) + #define PCU_CR_PACKAGE_RAPL_PERF_STATUS_PCU_COUNTS_MAX (0xFFFFFFFF) + #define PCU_CR_PACKAGE_RAPL_PERF_STATUS_PCU_COUNTS_DEF (0x00000000) + +#define PCU_CR_GT_RATIOS_OVERRIDE_PCU_REG (0x000058F4) + #define PCU_CR_GT_RATIOS_OVERRIDE_PCU_IA_MIN_RATIO_REQUEST_OFF ( 0) + #define PCU_CR_GT_RATIOS_OVERRIDE_PCU_IA_MIN_RATIO_REQUEST_WID ( 8) + #define PCU_CR_GT_RATIOS_OVERRIDE_PCU_IA_MIN_RATIO_REQUEST_MSK (0x000000FF) + #define PCU_CR_GT_RATIOS_OVERRIDE_PCU_IA_MIN_RATIO_REQUEST_MAX (0x000000FF) + #define PCU_CR_GT_RATIOS_OVERRIDE_PCU_IA_MIN_RATIO_REQUEST_DEF (0x00000000) + #define PCU_CR_GT_RATIOS_OVERRIDE_PCU_CLR_MIN_RATIO_REQUEST_OFF ( 8) + #define PCU_CR_GT_RATIOS_OVERRIDE_PCU_CLR_MIN_RATIO_REQUEST_WID ( 8) + #define PCU_CR_GT_RATIOS_OVERRIDE_PCU_CLR_MIN_RATIO_REQUEST_MSK (0x0000FF00) + #define PCU_CR_GT_RATIOS_OVERRIDE_PCU_CLR_MIN_RATIO_REQUEST_MAX (0x000000FF) + #define PCU_CR_GT_RATIOS_OVERRIDE_PCU_CLR_MIN_RATIO_REQUEST_DEF (0x00000000) + +#define PCU_CR_PKGC_LTR_LATENCY_MEASUREMENTS_PCU_REG (0x000058F8) + #define PCU_CR_PKGC_LTR_LATENCY_MEASUREMENTS_PCU_DDR_ACCESS_TIME_OFF ( 0) + #define PCU_CR_PKGC_LTR_LATENCY_MEASUREMENTS_PCU_DDR_ACCESS_TIME_WID (14) + #define PCU_CR_PKGC_LTR_LATENCY_MEASUREMENTS_PCU_DDR_ACCESS_TIME_MSK (0x00003FFF) + #define PCU_CR_PKGC_LTR_LATENCY_MEASUREMENTS_PCU_DDR_ACCESS_TIME_MAX (0x00003FFF) + #define PCU_CR_PKGC_LTR_LATENCY_MEASUREMENTS_PCU_DDR_ACCESS_TIME_DEF (0x00000000) + #define PCU_CR_PKGC_LTR_LATENCY_MEASUREMENTS_PCU_RESERVED_OFF (14) + #define PCU_CR_PKGC_LTR_LATENCY_MEASUREMENTS_PCU_RESERVED_WID ( 1) + #define PCU_CR_PKGC_LTR_LATENCY_MEASUREMENTS_PCU_RESERVED_MSK (0x00004000) + #define PCU_CR_PKGC_LTR_LATENCY_MEASUREMENTS_PCU_RESERVED_MAX (0x00000001) + #define PCU_CR_PKGC_LTR_LATENCY_MEASUREMENTS_PCU_RESERVED_DEF (0x00000000) + #define PCU_CR_PKGC_LTR_LATENCY_MEASUREMENTS_PCU_CLR_ACCESS_TIME_OFF (15) + #define PCU_CR_PKGC_LTR_LATENCY_MEASUREMENTS_PCU_CLR_ACCESS_TIME_WID (14) + #define PCU_CR_PKGC_LTR_LATENCY_MEASUREMENTS_PCU_CLR_ACCESS_TIME_MSK (0x1FFF8000) + #define PCU_CR_PKGC_LTR_LATENCY_MEASUREMENTS_PCU_CLR_ACCESS_TIME_MAX (0x00003FFF) + #define PCU_CR_PKGC_LTR_LATENCY_MEASUREMENTS_PCU_CLR_ACCESS_TIME_DEF (0x00000000) + #define PCU_CR_PKGC_LTR_LATENCY_MEASUREMENTS_PCU_NON_SNOOP_THRESHOLD_RESOLUTION_OFF (29) + #define PCU_CR_PKGC_LTR_LATENCY_MEASUREMENTS_PCU_NON_SNOOP_THRESHOLD_RESOLUTION_WID ( 1) + #define PCU_CR_PKGC_LTR_LATENCY_MEASUREMENTS_PCU_NON_SNOOP_THRESHOLD_RESOLUTION_MSK (0x20000000) + #define PCU_CR_PKGC_LTR_LATENCY_MEASUREMENTS_PCU_NON_SNOOP_THRESHOLD_RESOLUTION_MAX (0x00000001) + #define PCU_CR_PKGC_LTR_LATENCY_MEASUREMENTS_PCU_NON_SNOOP_THRESHOLD_RESOLUTION_DEF (0x00000000) + #define PCU_CR_PKGC_LTR_LATENCY_MEASUREMENTS_PCU_SLOW_SNOOP_THRESHOLD_RESOLUTION_OFF (30) + #define PCU_CR_PKGC_LTR_LATENCY_MEASUREMENTS_PCU_SLOW_SNOOP_THRESHOLD_RESOLUTION_WID ( 1) + #define PCU_CR_PKGC_LTR_LATENCY_MEASUREMENTS_PCU_SLOW_SNOOP_THRESHOLD_RESOLUTION_MSK (0x40000000) + #define PCU_CR_PKGC_LTR_LATENCY_MEASUREMENTS_PCU_SLOW_SNOOP_THRESHOLD_RESOLUTION_MAX (0x00000001) + #define PCU_CR_PKGC_LTR_LATENCY_MEASUREMENTS_PCU_SLOW_SNOOP_THRESHOLD_RESOLUTION_DEF (0x00000000) + #define PCU_CR_PKGC_LTR_LATENCY_MEASUREMENTS_PCU_FAST_SNOOP_THRESHOLD_RESOLUTION_OFF (31) + #define PCU_CR_PKGC_LTR_LATENCY_MEASUREMENTS_PCU_FAST_SNOOP_THRESHOLD_RESOLUTION_WID ( 1) + #define PCU_CR_PKGC_LTR_LATENCY_MEASUREMENTS_PCU_FAST_SNOOP_THRESHOLD_RESOLUTION_MSK (0x80000000) + #define PCU_CR_PKGC_LTR_LATENCY_MEASUREMENTS_PCU_FAST_SNOOP_THRESHOLD_RESOLUTION_MAX (0x00000001) + #define PCU_CR_PKGC_LTR_LATENCY_MEASUREMENTS_PCU_FAST_SNOOP_THRESHOLD_RESOLUTION_DEF (0x00000000) + +#define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_REG (0x000058FC) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_PROCHOT_STATUS_OFF ( 0) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_PROCHOT_STATUS_WID ( 1) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_PROCHOT_STATUS_MSK (0x00000001) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_PROCHOT_STATUS_MAX (0x00000001) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_PROCHOT_STATUS_DEF (0x00000000) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_THERMAL_STATUS_OFF ( 1) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_THERMAL_STATUS_WID ( 1) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_THERMAL_STATUS_MSK (0x00000002) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_THERMAL_STATUS_MAX (0x00000001) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_THERMAL_STATUS_DEF (0x00000000) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_SPARE_IA_2_OFF ( 2) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_SPARE_IA_2_WID ( 1) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_SPARE_IA_2_MSK (0x00000004) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_SPARE_IA_2_MAX (0x00000001) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_SPARE_IA_2_DEF (0x00000000) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_PBM_PL1_STATUS_OFF ( 3) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_PBM_PL1_STATUS_WID ( 1) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_PBM_PL1_STATUS_MSK (0x00000008) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_PBM_PL1_STATUS_MAX (0x00000001) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_PBM_PL1_STATUS_DEF (0x00000000) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_PBM_PL2_STATUS_OFF ( 4) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_PBM_PL2_STATUS_WID ( 1) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_PBM_PL2_STATUS_MSK (0x00000010) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_PBM_PL2_STATUS_MAX (0x00000001) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_PBM_PL2_STATUS_DEF (0x00000000) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_PBM_PLIA_STATUS_OFF ( 5) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_PBM_PLIA_STATUS_WID ( 1) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_PBM_PLIA_STATUS_MSK (0x00000020) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_PBM_PLIA_STATUS_MAX (0x00000001) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_PBM_PLIA_STATUS_DEF (0x00000000) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_SPARE_IA_6_OFF ( 6) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_SPARE_IA_6_WID ( 1) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_SPARE_IA_6_MSK (0x00000040) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_SPARE_IA_6_MAX (0x00000001) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_SPARE_IA_6_DEF (0x00000000) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_GTDRIVER_STATUS_OFF ( 7) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_GTDRIVER_STATUS_WID ( 1) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_GTDRIVER_STATUS_MSK (0x00000080) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_GTDRIVER_STATUS_MAX (0x00000001) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_GTDRIVER_STATUS_DEF (0x00000000) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_VR_THERMALERT_STATUS_OFF ( 8) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_VR_THERMALERT_STATUS_WID ( 1) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_VR_THERMALERT_STATUS_MSK (0x00000100) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_VR_THERMALERT_STATUS_MAX (0x00000001) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_VR_THERMALERT_STATUS_DEF (0x00000000) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_FUSE_MAX_TURBO_LIMIT_STATUS_OFF ( 9) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_FUSE_MAX_TURBO_LIMIT_STATUS_WID ( 1) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_FUSE_MAX_TURBO_LIMIT_STATUS_MSK (0x00000200) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_FUSE_MAX_TURBO_LIMIT_STATUS_MAX (0x00000001) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_FUSE_MAX_TURBO_LIMIT_STATUS_DEF (0x00000000) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_EDP_ICC_STATUS_OFF (10) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_EDP_ICC_STATUS_WID ( 1) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_EDP_ICC_STATUS_MSK (0x00000400) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_EDP_ICC_STATUS_MAX (0x00000001) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_EDP_ICC_STATUS_DEF (0x00000000) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_TURBO_ATTEN_STATUS_OFF (11) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_TURBO_ATTEN_STATUS_WID ( 1) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_TURBO_ATTEN_STATUS_MSK (0x00000800) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_TURBO_ATTEN_STATUS_MAX (0x00000001) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_TURBO_ATTEN_STATUS_DEF (0x00000000) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_SPARE_IA_12_OFF (12) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_SPARE_IA_12_WID ( 1) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_SPARE_IA_12_MSK (0x00001000) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_SPARE_IA_12_MAX (0x00000001) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_SPARE_IA_12_DEF (0x00000000) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_SPARE_IA_13_OFF (13) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_SPARE_IA_13_WID ( 1) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_SPARE_IA_13_MSK (0x00002000) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_SPARE_IA_13_MAX (0x00000001) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_SPARE_IA_13_DEF (0x00000000) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_SPARE_IA_14_OFF (14) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_SPARE_IA_14_WID ( 1) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_SPARE_IA_14_MSK (0x00004000) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_SPARE_IA_14_MAX (0x00000001) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_SPARE_IA_14_DEF (0x00000000) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_SPARE_IA_15_OFF (15) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_SPARE_IA_15_WID ( 1) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_SPARE_IA_15_MSK (0x00008000) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_SPARE_IA_15_MAX (0x00000001) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_SPARE_IA_15_DEF (0x00000000) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_PROCHOT_LOG_OFF (16) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_PROCHOT_LOG_WID ( 1) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_PROCHOT_LOG_MSK (0x00010000) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_PROCHOT_LOG_MAX (0x00000001) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_PROCHOT_LOG_DEF (0x00000000) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_THERMAL_LOG_OFF (17) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_THERMAL_LOG_WID ( 1) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_THERMAL_LOG_MSK (0x00020000) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_THERMAL_LOG_MAX (0x00000001) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_THERMAL_LOG_DEF (0x00000000) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_SPARE_IA_LOG_2_OFF (18) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_SPARE_IA_LOG_2_WID ( 1) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_SPARE_IA_LOG_2_MSK (0x00040000) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_SPARE_IA_LOG_2_MAX (0x00000001) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_SPARE_IA_LOG_2_DEF (0x00000000) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_PBM_PL1_LOG_OFF (19) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_PBM_PL1_LOG_WID ( 1) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_PBM_PL1_LOG_MSK (0x00080000) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_PBM_PL1_LOG_MAX (0x00000001) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_PBM_PL1_LOG_DEF (0x00000000) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_PBM_PL2_LOG_OFF (20) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_PBM_PL2_LOG_WID ( 1) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_PBM_PL2_LOG_MSK (0x00100000) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_PBM_PL2_LOG_MAX (0x00000001) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_PBM_PL2_LOG_DEF (0x00000000) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_PBM_PLIA_LOG_OFF (21) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_PBM_PLIA_LOG_WID ( 1) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_PBM_PLIA_LOG_MSK (0x00200000) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_PBM_PLIA_LOG_MAX (0x00000001) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_PBM_PLIA_LOG_DEF (0x00000000) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_SPARE_IA_LOG_6_OFF (22) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_SPARE_IA_LOG_6_WID ( 1) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_SPARE_IA_LOG_6_MSK (0x00400000) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_SPARE_IA_LOG_6_MAX (0x00000001) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_SPARE_IA_LOG_6_DEF (0x00000000) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_GTDRIVER_LOG_OFF (23) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_GTDRIVER_LOG_WID ( 1) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_GTDRIVER_LOG_MSK (0x00800000) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_GTDRIVER_LOG_MAX (0x00000001) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_GTDRIVER_LOG_DEF (0x00000000) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_VR_THERMALERT_LOG_OFF (24) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_VR_THERMALERT_LOG_WID ( 1) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_VR_THERMALERT_LOG_MSK (0x01000000) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_VR_THERMALERT_LOG_MAX (0x00000001) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_VR_THERMALERT_LOG_DEF (0x00000000) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_FUSE_MAX_TURBO_LIMIT_LOG_OFF (25) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_FUSE_MAX_TURBO_LIMIT_LOG_WID ( 1) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_FUSE_MAX_TURBO_LIMIT_LOG_MSK (0x02000000) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_FUSE_MAX_TURBO_LIMIT_LOG_MAX (0x00000001) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_FUSE_MAX_TURBO_LIMIT_LOG_DEF (0x00000000) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_EDP_ICC_LOG_OFF (26) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_EDP_ICC_LOG_WID ( 1) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_EDP_ICC_LOG_MSK (0x04000000) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_EDP_ICC_LOG_MAX (0x00000001) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_EDP_ICC_LOG_DEF (0x00000000) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_TURBO_ATTEN_LOG_OFF (27) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_TURBO_ATTEN_LOG_WID ( 1) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_TURBO_ATTEN_LOG_MSK (0x08000000) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_TURBO_ATTEN_LOG_MAX (0x00000001) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_TURBO_ATTEN_LOG_DEF (0x00000000) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_SPARE_IA_LOG_12_OFF (28) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_SPARE_IA_LOG_12_WID ( 1) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_SPARE_IA_LOG_12_MSK (0x10000000) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_SPARE_IA_LOG_12_MAX (0x00000001) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_SPARE_IA_LOG_12_DEF (0x00000000) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_SPARE_IA_LOG_13_OFF (29) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_SPARE_IA_LOG_13_WID ( 1) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_SPARE_IA_LOG_13_MSK (0x20000000) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_SPARE_IA_LOG_13_MAX (0x00000001) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_SPARE_IA_LOG_13_DEF (0x00000000) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_SPARE_IA_LOG_14_OFF (30) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_SPARE_IA_LOG_14_WID ( 1) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_SPARE_IA_LOG_14_MSK (0x40000000) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_SPARE_IA_LOG_14_MAX (0x00000001) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_SPARE_IA_LOG_14_DEF (0x00000000) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_SPARE_IA_LOG_15_OFF (31) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_SPARE_IA_LOG_15_WID ( 1) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_SPARE_IA_LOG_15_MSK (0x80000000) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_SPARE_IA_LOG_15_MAX (0x00000001) + #define PCU_CR_IA_PERF_LIMIT_REASONS_PCU_SPARE_IA_LOG_15_DEF (0x00000000) + +#define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_REG (0x00005900) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_PROCHOT_STATUS_OFF ( 0) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_PROCHOT_STATUS_WID ( 1) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_PROCHOT_STATUS_MSK (0x00000001) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_PROCHOT_STATUS_MAX (0x00000001) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_PROCHOT_STATUS_DEF (0x00000000) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_THERMAL_STATUS_OFF ( 1) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_THERMAL_STATUS_WID ( 1) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_THERMAL_STATUS_MSK (0x00000002) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_THERMAL_STATUS_MAX (0x00000001) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_THERMAL_STATUS_DEF (0x00000000) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_2_OFF ( 2) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_2_WID ( 1) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_2_MSK (0x00000004) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_2_MAX (0x00000001) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_2_DEF (0x00000000) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_PBM_PL1_STATUS_OFF ( 3) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_PBM_PL1_STATUS_WID ( 1) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_PBM_PL1_STATUS_MSK (0x00000008) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_PBM_PL1_STATUS_MAX (0x00000001) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_PBM_PL1_STATUS_DEF (0x00000000) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_PBM_PL2_STATUS_OFF ( 4) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_PBM_PL2_STATUS_WID ( 1) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_PBM_PL2_STATUS_MSK (0x00000010) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_PBM_PL2_STATUS_MAX (0x00000001) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_PBM_PL2_STATUS_DEF (0x00000000) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_PBM_PLGT_STATUS_OFF ( 5) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_PBM_PLGT_STATUS_WID ( 1) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_PBM_PLGT_STATUS_MSK (0x00000020) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_PBM_PLGT_STATUS_MAX (0x00000001) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_PBM_PLGT_STATUS_DEF (0x00000000) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_6_OFF ( 6) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_6_WID ( 1) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_6_MSK (0x00000040) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_6_MAX (0x00000001) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_6_DEF (0x00000000) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_7_OFF ( 7) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_7_WID ( 1) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_7_MSK (0x00000080) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_7_MAX (0x00000001) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_7_DEF (0x00000000) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_VR_THERMALERT_STATUS_OFF ( 8) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_VR_THERMALERT_STATUS_WID ( 1) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_VR_THERMALERT_STATUS_MSK (0x00000100) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_VR_THERMALERT_STATUS_MAX (0x00000001) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_VR_THERMALERT_STATUS_DEF (0x00000000) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_9_OFF ( 9) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_9_WID ( 1) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_9_MSK (0x00000200) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_9_MAX (0x00000001) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_9_DEF (0x00000000) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_EDP_ICC_STATUS_OFF (10) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_EDP_ICC_STATUS_WID ( 1) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_EDP_ICC_STATUS_MSK (0x00000400) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_EDP_ICC_STATUS_MAX (0x00000001) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_EDP_ICC_STATUS_DEF (0x00000000) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_11_OFF (11) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_11_WID ( 1) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_11_MSK (0x00000800) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_11_MAX (0x00000001) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_11_DEF (0x00000000) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_12_OFF (12) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_12_WID ( 1) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_12_MSK (0x00001000) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_12_MAX (0x00000001) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_12_DEF (0x00000000) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_13_OFF (13) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_13_WID ( 1) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_13_MSK (0x00002000) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_13_MAX (0x00000001) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_13_DEF (0x00000000) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_14_OFF (14) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_14_WID ( 1) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_14_MSK (0x00004000) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_14_MAX (0x00000001) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_14_DEF (0x00000000) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_15_OFF (15) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_15_WID ( 1) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_15_MSK (0x00008000) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_15_MAX (0x00000001) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_15_DEF (0x00000000) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_PROCHOT_LOG_OFF (16) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_PROCHOT_LOG_WID ( 1) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_PROCHOT_LOG_MSK (0x00010000) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_PROCHOT_LOG_MAX (0x00000001) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_PROCHOT_LOG_DEF (0x00000000) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_THERMAL_LOG_OFF (17) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_THERMAL_LOG_WID ( 1) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_THERMAL_LOG_MSK (0x00020000) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_THERMAL_LOG_MAX (0x00000001) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_THERMAL_LOG_DEF (0x00000000) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_LOG_2_OFF (18) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_LOG_2_WID ( 1) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_LOG_2_MSK (0x00040000) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_LOG_2_MAX (0x00000001) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_LOG_2_DEF (0x00000000) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_PBM_PL1_LOG_OFF (19) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_PBM_PL1_LOG_WID ( 1) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_PBM_PL1_LOG_MSK (0x00080000) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_PBM_PL1_LOG_MAX (0x00000001) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_PBM_PL1_LOG_DEF (0x00000000) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_PBM_PL2_LOG_OFF (20) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_PBM_PL2_LOG_WID ( 1) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_PBM_PL2_LOG_MSK (0x00100000) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_PBM_PL2_LOG_MAX (0x00000001) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_PBM_PL2_LOG_DEF (0x00000000) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_PBM_PLGT_LOG_OFF (21) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_PBM_PLGT_LOG_WID ( 1) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_PBM_PLGT_LOG_MSK (0x00200000) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_PBM_PLGT_LOG_MAX (0x00000001) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_PBM_PLGT_LOG_DEF (0x00000000) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_LOG_6_OFF (22) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_LOG_6_WID ( 1) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_LOG_6_MSK (0x00400000) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_LOG_6_MAX (0x00000001) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_LOG_6_DEF (0x00000000) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_LOG_7_OFF (23) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_LOG_7_WID ( 1) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_LOG_7_MSK (0x00800000) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_LOG_7_MAX (0x00000001) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_LOG_7_DEF (0x00000000) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_VR_THERMALERT_LOG_OFF (24) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_VR_THERMALERT_LOG_WID ( 1) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_VR_THERMALERT_LOG_MSK (0x01000000) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_VR_THERMALERT_LOG_MAX (0x00000001) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_VR_THERMALERT_LOG_DEF (0x00000000) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_LOG_9_OFF (25) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_LOG_9_WID ( 1) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_LOG_9_MSK (0x02000000) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_LOG_9_MAX (0x00000001) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_LOG_9_DEF (0x00000000) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_EDP_ICC_LOG_OFF (26) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_EDP_ICC_LOG_WID ( 1) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_EDP_ICC_LOG_MSK (0x04000000) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_EDP_ICC_LOG_MAX (0x00000001) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_EDP_ICC_LOG_DEF (0x00000000) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_LOG_11_OFF (27) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_LOG_11_WID ( 1) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_LOG_11_MSK (0x08000000) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_LOG_11_MAX (0x00000001) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_LOG_11_DEF (0x00000000) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_LOG_12_OFF (28) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_LOG_12_WID ( 1) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_LOG_12_MSK (0x10000000) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_LOG_12_MAX (0x00000001) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_LOG_12_DEF (0x00000000) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_LOG_13_OFF (29) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_LOG_13_WID ( 1) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_LOG_13_MSK (0x20000000) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_LOG_13_MAX (0x00000001) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_LOG_13_DEF (0x00000000) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_LOG_14_OFF (30) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_LOG_14_WID ( 1) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_LOG_14_MSK (0x40000000) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_LOG_14_MAX (0x00000001) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_LOG_14_DEF (0x00000000) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_LOG_15_OFF (31) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_LOG_15_WID ( 1) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_LOG_15_MSK (0x80000000) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_LOG_15_MAX (0x00000001) + #define PCU_CR_GT_PERF_LIMIT_REASONS_PCU_SPARE_GT_LOG_15_DEF (0x00000000) + +#define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_REG (0x00005904) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_PROCHOT_STATUS_OFF ( 0) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_PROCHOT_STATUS_WID ( 1) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_PROCHOT_STATUS_MSK (0x00000001) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_PROCHOT_STATUS_MAX (0x00000001) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_PROCHOT_STATUS_DEF (0x00000000) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_THERMAL_STATUS_OFF ( 1) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_THERMAL_STATUS_WID ( 1) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_THERMAL_STATUS_MSK (0x00000002) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_THERMAL_STATUS_MAX (0x00000001) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_THERMAL_STATUS_DEF (0x00000000) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_2_OFF ( 2) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_2_WID ( 1) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_2_MSK (0x00000004) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_2_MAX (0x00000001) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_2_DEF (0x00000000) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_PBM_PL1_STATUS_OFF ( 3) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_PBM_PL1_STATUS_WID ( 1) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_PBM_PL1_STATUS_MSK (0x00000008) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_PBM_PL1_STATUS_MAX (0x00000001) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_PBM_PL1_STATUS_DEF (0x00000000) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_PBM_PL2_STATUS_OFF ( 4) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_PBM_PL2_STATUS_WID ( 1) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_PBM_PL2_STATUS_MSK (0x00000010) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_PBM_PL2_STATUS_MAX (0x00000001) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_PBM_PL2_STATUS_DEF (0x00000000) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_5_OFF ( 5) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_5_WID ( 1) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_5_MSK (0x00000020) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_5_MAX (0x00000001) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_5_DEF (0x00000000) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_6_OFF ( 6) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_6_WID ( 1) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_6_MSK (0x00000040) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_6_MAX (0x00000001) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_6_DEF (0x00000000) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_7_OFF ( 7) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_7_WID ( 1) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_7_MSK (0x00000080) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_7_MAX (0x00000001) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_7_DEF (0x00000000) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_VR_THERMALERT_STATUS_OFF ( 8) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_VR_THERMALERT_STATUS_WID ( 1) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_VR_THERMALERT_STATUS_MSK (0x00000100) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_VR_THERMALERT_STATUS_MAX (0x00000001) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_VR_THERMALERT_STATUS_DEF (0x00000000) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_9_OFF ( 9) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_9_WID ( 1) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_9_MSK (0x00000200) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_9_MAX (0x00000001) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_9_DEF (0x00000000) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_EDP_ICC_STATUS_OFF (10) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_EDP_ICC_STATUS_WID ( 1) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_EDP_ICC_STATUS_MSK (0x00000400) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_EDP_ICC_STATUS_MAX (0x00000001) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_EDP_ICC_STATUS_DEF (0x00000000) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_11_OFF (11) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_11_WID ( 1) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_11_MSK (0x00000800) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_11_MAX (0x00000001) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_11_DEF (0x00000000) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_12_OFF (12) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_12_WID ( 1) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_12_MSK (0x00001000) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_12_MAX (0x00000001) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_12_DEF (0x00000000) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_13_OFF (13) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_13_WID ( 1) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_13_MSK (0x00002000) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_13_MAX (0x00000001) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_13_DEF (0x00000000) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_14_OFF (14) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_14_WID ( 1) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_14_MSK (0x00004000) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_14_MAX (0x00000001) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_14_DEF (0x00000000) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_15_OFF (15) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_15_WID ( 1) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_15_MSK (0x00008000) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_15_MAX (0x00000001) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_15_DEF (0x00000000) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_PROCHOT_LOG_OFF (16) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_PROCHOT_LOG_WID ( 1) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_PROCHOT_LOG_MSK (0x00010000) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_PROCHOT_LOG_MAX (0x00000001) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_PROCHOT_LOG_DEF (0x00000000) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_THERMAL_LOG_OFF (17) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_THERMAL_LOG_WID ( 1) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_THERMAL_LOG_MSK (0x00020000) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_THERMAL_LOG_MAX (0x00000001) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_THERMAL_LOG_DEF (0x00000000) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_LOG_2_OFF (18) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_LOG_2_WID ( 1) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_LOG_2_MSK (0x00040000) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_LOG_2_MAX (0x00000001) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_LOG_2_DEF (0x00000000) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_PBM_PL1_LOG_OFF (19) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_PBM_PL1_LOG_WID ( 1) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_PBM_PL1_LOG_MSK (0x00080000) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_PBM_PL1_LOG_MAX (0x00000001) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_PBM_PL1_LOG_DEF (0x00000000) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_PBM_PL2_LOG_OFF (20) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_PBM_PL2_LOG_WID ( 1) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_PBM_PL2_LOG_MSK (0x00100000) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_PBM_PL2_LOG_MAX (0x00000001) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_PBM_PL2_LOG_DEF (0x00000000) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_LOG_5_OFF (21) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_LOG_5_WID ( 1) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_LOG_5_MSK (0x00200000) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_LOG_5_MAX (0x00000001) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_LOG_5_DEF (0x00000000) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_LOG_6_OFF (22) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_LOG_6_WID ( 1) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_LOG_6_MSK (0x00400000) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_LOG_6_MAX (0x00000001) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_LOG_6_DEF (0x00000000) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_LOG_7_OFF (23) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_LOG_7_WID ( 1) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_LOG_7_MSK (0x00800000) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_LOG_7_MAX (0x00000001) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_LOG_7_DEF (0x00000000) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_VR_THERMALERT_LOG_OFF (24) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_VR_THERMALERT_LOG_WID ( 1) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_VR_THERMALERT_LOG_MSK (0x01000000) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_VR_THERMALERT_LOG_MAX (0x00000001) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_VR_THERMALERT_LOG_DEF (0x00000000) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_LOG_9_OFF (25) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_LOG_9_WID ( 1) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_LOG_9_MSK (0x02000000) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_LOG_9_MAX (0x00000001) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_LOG_9_DEF (0x00000000) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_EDP_ICC_LOG_OFF (26) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_EDP_ICC_LOG_WID ( 1) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_EDP_ICC_LOG_MSK (0x04000000) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_EDP_ICC_LOG_MAX (0x00000001) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_EDP_ICC_LOG_DEF (0x00000000) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_LOG_11_OFF (27) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_LOG_11_WID ( 1) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_LOG_11_MSK (0x08000000) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_LOG_11_MAX (0x00000001) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_LOG_11_DEF (0x00000000) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_LOG_12_OFF (28) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_LOG_12_WID ( 1) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_LOG_12_MSK (0x10000000) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_LOG_12_MAX (0x00000001) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_LOG_12_DEF (0x00000000) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_LOG_13_OFF (29) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_LOG_13_WID ( 1) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_LOG_13_MSK (0x20000000) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_LOG_13_MAX (0x00000001) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_LOG_13_DEF (0x00000000) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_LOG_14_OFF (30) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_LOG_14_WID ( 1) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_LOG_14_MSK (0x40000000) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_LOG_14_MAX (0x00000001) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_LOG_14_DEF (0x00000000) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_LOG_15_OFF (31) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_LOG_15_WID ( 1) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_LOG_15_MSK (0x80000000) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_LOG_15_MAX (0x00000001) + #define PCU_CR_CLR_PERF_LIMIT_REASONS_PCU_SPARE_CLR_LOG_15_DEF (0x00000000) + +#define PCU_CR_PRIP_TURBO_PLCY_PCU_REG (0x00005920) + #define PCU_CR_PRIP_TURBO_PLCY_PCU_PRIPTP_OFF ( 0) + #define PCU_CR_PRIP_TURBO_PLCY_PCU_PRIPTP_WID ( 5) + #define PCU_CR_PRIP_TURBO_PLCY_PCU_PRIPTP_MSK (0x0000001F) + #define PCU_CR_PRIP_TURBO_PLCY_PCU_PRIPTP_MAX (0x0000001F) + #define PCU_CR_PRIP_TURBO_PLCY_PCU_PRIPTP_DEF (0x00000000) + +#define PCU_CR_SECP_TURBO_PLCY_PCU_REG (0x00005924) + #define PCU_CR_SECP_TURBO_PLCY_PCU_SECPTP_OFF ( 0) + #define PCU_CR_SECP_TURBO_PLCY_PCU_SECPTP_WID ( 5) + #define PCU_CR_SECP_TURBO_PLCY_PCU_SECPTP_MSK (0x0000001F) + #define PCU_CR_SECP_TURBO_PLCY_PCU_SECPTP_MAX (0x0000001F) + #define PCU_CR_SECP_TURBO_PLCY_PCU_SECPTP_DEF (0x00000010) + +#define PCU_CR_PRIP_NRG_STTS_PCU_REG (0x00005928) + #define PCU_CR_PRIP_NRG_STTS_PCU_DATA_OFF ( 0) + #define PCU_CR_PRIP_NRG_STTS_PCU_DATA_WID (32) + #define PCU_CR_PRIP_NRG_STTS_PCU_DATA_MSK (0xFFFFFFFF) + #define PCU_CR_PRIP_NRG_STTS_PCU_DATA_MAX (0xFFFFFFFF) + #define PCU_CR_PRIP_NRG_STTS_PCU_DATA_DEF (0x00000000) + +#define PCU_CR_SECP_NRG_STTS_PCU_REG (0x0000592C) + #define PCU_CR_SECP_NRG_STTS_PCU_DATA_OFF ( 0) + #define PCU_CR_SECP_NRG_STTS_PCU_DATA_WID (32) + #define PCU_CR_SECP_NRG_STTS_PCU_DATA_MSK (0xFFFFFFFF) + #define PCU_CR_SECP_NRG_STTS_PCU_DATA_MAX (0xFFFFFFFF) + #define PCU_CR_SECP_NRG_STTS_PCU_DATA_DEF (0x00000000) + +#define PCU_CR_PACKAGE_POWER_SKU_PCU_REG (0x00005930) + #define PCU_CR_PACKAGE_POWER_SKU_PCU_PKG_TDP_OFF ( 0) + #define PCU_CR_PACKAGE_POWER_SKU_PCU_PKG_TDP_WID (15) + #define PCU_CR_PACKAGE_POWER_SKU_PCU_PKG_TDP_MSK (0x00007FFF) + #define PCU_CR_PACKAGE_POWER_SKU_PCU_PKG_TDP_MAX (0x00007FFF) + #define PCU_CR_PACKAGE_POWER_SKU_PCU_PKG_TDP_DEF (0x00000118) + #define PCU_CR_PACKAGE_POWER_SKU_PCU_PKG_MIN_PWR_OFF (16) + #define PCU_CR_PACKAGE_POWER_SKU_PCU_PKG_MIN_PWR_WID (15) + #define PCU_CR_PACKAGE_POWER_SKU_PCU_PKG_MIN_PWR_MSK (0x7FFF0000) + #define PCU_CR_PACKAGE_POWER_SKU_PCU_PKG_MIN_PWR_MAX (0x00007FFF) + #define PCU_CR_PACKAGE_POWER_SKU_PCU_PKG_MIN_PWR_DEF (0x00000060) + #define PCU_CR_PACKAGE_POWER_SKU_PCU_PKG_MAX_PWR_OFF (32) + #define PCU_CR_PACKAGE_POWER_SKU_PCU_PKG_MAX_PWR_WID (15) + #define PCU_CR_PACKAGE_POWER_SKU_PCU_PKG_MAX_PWR_MSK (0x7FFF00000000) + #define PCU_CR_PACKAGE_POWER_SKU_PCU_PKG_MAX_PWR_MAX (0x00007FFF) + #define PCU_CR_PACKAGE_POWER_SKU_PCU_PKG_MAX_PWR_DEF (0x00000240) + #define PCU_CR_PACKAGE_POWER_SKU_PCU_PKG_MAX_WIN_OFF (48) + #define PCU_CR_PACKAGE_POWER_SKU_PCU_PKG_MAX_WIN_WID ( 7) + #define PCU_CR_PACKAGE_POWER_SKU_PCU_PKG_MAX_WIN_MSK (0x7F000000000000) + #define PCU_CR_PACKAGE_POWER_SKU_PCU_PKG_MAX_WIN_MAX (0x0000007F) + #define PCU_CR_PACKAGE_POWER_SKU_PCU_PKG_MAX_WIN_DEF (0x00000012) + +#define PCU_CR_PACKAGE_POWER_SKU_UNIT_PCU_REG (0x00005938) + #define PCU_CR_PACKAGE_POWER_SKU_UNIT_PCU_PWR_UNIT_OFF ( 0) + #define PCU_CR_PACKAGE_POWER_SKU_UNIT_PCU_PWR_UNIT_WID ( 4) + #define PCU_CR_PACKAGE_POWER_SKU_UNIT_PCU_PWR_UNIT_MSK (0x0000000F) + #define PCU_CR_PACKAGE_POWER_SKU_UNIT_PCU_PWR_UNIT_MAX (0x0000000F) + #define PCU_CR_PACKAGE_POWER_SKU_UNIT_PCU_PWR_UNIT_DEF (0x00000003) + #define PCU_CR_PACKAGE_POWER_SKU_UNIT_PCU_ENERGY_UNIT_OFF ( 8) + #define PCU_CR_PACKAGE_POWER_SKU_UNIT_PCU_ENERGY_UNIT_WID ( 5) + #define PCU_CR_PACKAGE_POWER_SKU_UNIT_PCU_ENERGY_UNIT_MSK (0x00001F00) + #define PCU_CR_PACKAGE_POWER_SKU_UNIT_PCU_ENERGY_UNIT_MAX (0x0000001F) + #define PCU_CR_PACKAGE_POWER_SKU_UNIT_PCU_ENERGY_UNIT_DEF (0x0000000E) + #define PCU_CR_PACKAGE_POWER_SKU_UNIT_PCU_TIME_UNIT_OFF (16) + #define PCU_CR_PACKAGE_POWER_SKU_UNIT_PCU_TIME_UNIT_WID ( 4) + #define PCU_CR_PACKAGE_POWER_SKU_UNIT_PCU_TIME_UNIT_MSK (0x000F0000) + #define PCU_CR_PACKAGE_POWER_SKU_UNIT_PCU_TIME_UNIT_MAX (0x0000000F) + #define PCU_CR_PACKAGE_POWER_SKU_UNIT_PCU_TIME_UNIT_DEF (0x0000000A) + +#define PCU_CR_PACKAGE_ENERGY_STATUS_PCU_REG (0x0000593C) + #define PCU_CR_PACKAGE_ENERGY_STATUS_PCU_DATA_OFF ( 0) + #define PCU_CR_PACKAGE_ENERGY_STATUS_PCU_DATA_WID (32) + #define PCU_CR_PACKAGE_ENERGY_STATUS_PCU_DATA_MSK (0xFFFFFFFF) + #define PCU_CR_PACKAGE_ENERGY_STATUS_PCU_DATA_MAX (0xFFFFFFFF) + #define PCU_CR_PACKAGE_ENERGY_STATUS_PCU_DATA_DEF (0x00000000) + +#define PCU_CR_GT_IO_BUSYNESS_PCU_REG (0x00005940) + #define PCU_CR_GT_IO_BUSYNESS_PCU_DATA_OFF ( 0) + #define PCU_CR_GT_IO_BUSYNESS_PCU_DATA_WID (32) + #define PCU_CR_GT_IO_BUSYNESS_PCU_DATA_MSK (0xFFFFFFFF) + #define PCU_CR_GT_IO_BUSYNESS_PCU_DATA_MAX (0xFFFFFFFF) + #define PCU_CR_GT_IO_BUSYNESS_PCU_DATA_DEF (0x00000000) + +#define PCU_CR_GT_VIDEO_BUSYNESS_PCU_REG (0x00005944) + #define PCU_CR_GT_VIDEO_BUSYNESS_PCU_DATA_OFF ( 0) + #define PCU_CR_GT_VIDEO_BUSYNESS_PCU_DATA_WID (32) + #define PCU_CR_GT_VIDEO_BUSYNESS_PCU_DATA_MSK (0xFFFFFFFF) + #define PCU_CR_GT_VIDEO_BUSYNESS_PCU_DATA_MAX (0xFFFFFFFF) + #define PCU_CR_GT_VIDEO_BUSYNESS_PCU_DATA_DEF (0x00000000) + +#define PCU_CR_GT_PERF_STATUS_PCU_REG (0x00005948) + #define PCU_CR_GT_PERF_STATUS_PCU_RP_STATE_VOLTAGE_OFF ( 0) + #define PCU_CR_GT_PERF_STATUS_PCU_RP_STATE_VOLTAGE_WID ( 8) + #define PCU_CR_GT_PERF_STATUS_PCU_RP_STATE_VOLTAGE_MSK (0x000000FF) + #define PCU_CR_GT_PERF_STATUS_PCU_RP_STATE_VOLTAGE_MAX (0x000000FF) + #define PCU_CR_GT_PERF_STATUS_PCU_RP_STATE_VOLTAGE_DEF (0x00000000) + #define PCU_CR_GT_PERF_STATUS_PCU_RP_STATE_RATIO_OFF ( 8) + #define PCU_CR_GT_PERF_STATUS_PCU_RP_STATE_RATIO_WID ( 8) + #define PCU_CR_GT_PERF_STATUS_PCU_RP_STATE_RATIO_MSK (0x0000FF00) + #define PCU_CR_GT_PERF_STATUS_PCU_RP_STATE_RATIO_MAX (0x000000FF) + #define PCU_CR_GT_PERF_STATUS_PCU_RP_STATE_RATIO_DEF (0x00000000) + +#define PCU_CR_PLATFORM_ID_PCU_REG (0x00005950) + #define PCU_CR_PLATFORM_ID_PCU_PLATFORMID_OFF (50) + #define PCU_CR_PLATFORM_ID_PCU_PLATFORMID_WID ( 3) + #define PCU_CR_PLATFORM_ID_PCU_PLATFORMID_MSK (0x1C000000000000) + #define PCU_CR_PLATFORM_ID_PCU_PLATFORMID_MAX (0x00000007) + #define PCU_CR_PLATFORM_ID_PCU_PLATFORMID_DEF (0x00000000) + +#define PCU_CR_PLATFORM_INFO_PCU_REG (0x00005958) + #define PCU_CR_PLATFORM_INFO_PCU_MAX_NON_TURBO_LIM_RATIO_OFF ( 8) + #define PCU_CR_PLATFORM_INFO_PCU_MAX_NON_TURBO_LIM_RATIO_WID ( 8) + #define PCU_CR_PLATFORM_INFO_PCU_MAX_NON_TURBO_LIM_RATIO_MSK (0x0000FF00) + #define PCU_CR_PLATFORM_INFO_PCU_MAX_NON_TURBO_LIM_RATIO_MAX (0x000000FF) + #define PCU_CR_PLATFORM_INFO_PCU_MAX_NON_TURBO_LIM_RATIO_DEF (0x00000000) + #define PCU_CR_PLATFORM_INFO_PCU_SMM_SAVE_CAP_OFF (16) + #define PCU_CR_PLATFORM_INFO_PCU_SMM_SAVE_CAP_WID ( 1) + #define PCU_CR_PLATFORM_INFO_PCU_SMM_SAVE_CAP_MSK (0x00010000) + #define PCU_CR_PLATFORM_INFO_PCU_SMM_SAVE_CAP_MAX (0x00000001) + #define PCU_CR_PLATFORM_INFO_PCU_SMM_SAVE_CAP_DEF (0x00000001) + #define PCU_CR_PLATFORM_INFO_PCU_OCVOLT_OVRD_AVAIL_OFF (24) + #define PCU_CR_PLATFORM_INFO_PCU_OCVOLT_OVRD_AVAIL_WID ( 1) + #define PCU_CR_PLATFORM_INFO_PCU_OCVOLT_OVRD_AVAIL_MSK (0x01000000) + #define PCU_CR_PLATFORM_INFO_PCU_OCVOLT_OVRD_AVAIL_MAX (0x00000001) + #define PCU_CR_PLATFORM_INFO_PCU_OCVOLT_OVRD_AVAIL_DEF (0x00000000) + #define PCU_CR_PLATFORM_INFO_PCU_FIVR_RFI_TUNING_AVAIL_OFF (25) + #define PCU_CR_PLATFORM_INFO_PCU_FIVR_RFI_TUNING_AVAIL_WID ( 1) + #define PCU_CR_PLATFORM_INFO_PCU_FIVR_RFI_TUNING_AVAIL_MSK (0x02000000) + #define PCU_CR_PLATFORM_INFO_PCU_FIVR_RFI_TUNING_AVAIL_MAX (0x00000001) + #define PCU_CR_PLATFORM_INFO_PCU_FIVR_RFI_TUNING_AVAIL_DEF (0x00000000) + #define PCU_CR_PLATFORM_INFO_PCU_DCU_16K_MODE_AVAIL_OFF (26) + #define PCU_CR_PLATFORM_INFO_PCU_DCU_16K_MODE_AVAIL_WID ( 1) + #define PCU_CR_PLATFORM_INFO_PCU_DCU_16K_MODE_AVAIL_MSK (0x04000000) + #define PCU_CR_PLATFORM_INFO_PCU_DCU_16K_MODE_AVAIL_MAX (0x00000001) + #define PCU_CR_PLATFORM_INFO_PCU_DCU_16K_MODE_AVAIL_DEF (0x00000000) + #define PCU_CR_PLATFORM_INFO_PCU_SAMPLE_PART_OFF (27) + #define PCU_CR_PLATFORM_INFO_PCU_SAMPLE_PART_WID ( 1) + #define PCU_CR_PLATFORM_INFO_PCU_SAMPLE_PART_MSK (0x08000000) + #define PCU_CR_PLATFORM_INFO_PCU_SAMPLE_PART_MAX (0x00000001) + #define PCU_CR_PLATFORM_INFO_PCU_SAMPLE_PART_DEF (0x00000000) + #define PCU_CR_PLATFORM_INFO_PCU_PRG_TURBO_RATIO_EN_OFF (28) + #define PCU_CR_PLATFORM_INFO_PCU_PRG_TURBO_RATIO_EN_WID ( 1) + #define PCU_CR_PLATFORM_INFO_PCU_PRG_TURBO_RATIO_EN_MSK (0x10000000) + #define PCU_CR_PLATFORM_INFO_PCU_PRG_TURBO_RATIO_EN_MAX (0x00000001) + #define PCU_CR_PLATFORM_INFO_PCU_PRG_TURBO_RATIO_EN_DEF (0x00000001) + #define PCU_CR_PLATFORM_INFO_PCU_PRG_TDP_LIM_EN_OFF (29) + #define PCU_CR_PLATFORM_INFO_PCU_PRG_TDP_LIM_EN_WID ( 1) + #define PCU_CR_PLATFORM_INFO_PCU_PRG_TDP_LIM_EN_MSK (0x20000000) + #define PCU_CR_PLATFORM_INFO_PCU_PRG_TDP_LIM_EN_MAX (0x00000001) + #define PCU_CR_PLATFORM_INFO_PCU_PRG_TDP_LIM_EN_DEF (0x00000001) + #define PCU_CR_PLATFORM_INFO_PCU_PRG_TJ_OFFSET_EN_OFF (30) + #define PCU_CR_PLATFORM_INFO_PCU_PRG_TJ_OFFSET_EN_WID ( 1) + #define PCU_CR_PLATFORM_INFO_PCU_PRG_TJ_OFFSET_EN_MSK (0x40000000) + #define PCU_CR_PLATFORM_INFO_PCU_PRG_TJ_OFFSET_EN_MAX (0x00000001) + #define PCU_CR_PLATFORM_INFO_PCU_PRG_TJ_OFFSET_EN_DEF (0x00000001) + #define PCU_CR_PLATFORM_INFO_PCU_CPUID_FAULTING_EN_OFF (31) + #define PCU_CR_PLATFORM_INFO_PCU_CPUID_FAULTING_EN_WID ( 1) + #define PCU_CR_PLATFORM_INFO_PCU_CPUID_FAULTING_EN_MSK (0x80000000) + #define PCU_CR_PLATFORM_INFO_PCU_CPUID_FAULTING_EN_MAX (0x00000001) + #define PCU_CR_PLATFORM_INFO_PCU_CPUID_FAULTING_EN_DEF (0x00000001) + #define PCU_CR_PLATFORM_INFO_PCU_LPM_SUPPORT_OFF (32) + #define PCU_CR_PLATFORM_INFO_PCU_LPM_SUPPORT_WID ( 1) + #define PCU_CR_PLATFORM_INFO_PCU_LPM_SUPPORT_MSK (0x100000000) + #define PCU_CR_PLATFORM_INFO_PCU_LPM_SUPPORT_MAX (0x00000001) + #define PCU_CR_PLATFORM_INFO_PCU_LPM_SUPPORT_DEF (0x00000000) + #define PCU_CR_PLATFORM_INFO_PCU_CONFIG_TDP_LEVELS_OFF (33) + #define PCU_CR_PLATFORM_INFO_PCU_CONFIG_TDP_LEVELS_WID ( 2) + #define PCU_CR_PLATFORM_INFO_PCU_CONFIG_TDP_LEVELS_MSK (0x600000000) + #define PCU_CR_PLATFORM_INFO_PCU_CONFIG_TDP_LEVELS_MAX (0x00000003) + #define PCU_CR_PLATFORM_INFO_PCU_CONFIG_TDP_LEVELS_DEF (0x00000000) + #define PCU_CR_PLATFORM_INFO_PCU_PFAT_ENABLE_OFF (35) + #define PCU_CR_PLATFORM_INFO_PCU_PFAT_ENABLE_WID ( 1) + #define PCU_CR_PLATFORM_INFO_PCU_PFAT_ENABLE_MSK (0x800000000) + #define PCU_CR_PLATFORM_INFO_PCU_PFAT_ENABLE_MAX (0x00000001) + #define PCU_CR_PLATFORM_INFO_PCU_PFAT_ENABLE_DEF (0x00000000) + #define PCU_CR_PLATFORM_INFO_PCU_TIMED_MWAIT_ENABLE_OFF (37) + #define PCU_CR_PLATFORM_INFO_PCU_TIMED_MWAIT_ENABLE_WID ( 1) + #define PCU_CR_PLATFORM_INFO_PCU_TIMED_MWAIT_ENABLE_MSK (0x2000000000) + #define PCU_CR_PLATFORM_INFO_PCU_TIMED_MWAIT_ENABLE_MAX (0x00000001) + #define PCU_CR_PLATFORM_INFO_PCU_TIMED_MWAIT_ENABLE_DEF (0x00000000) + #define PCU_CR_PLATFORM_INFO_PCU_MAX_EFFICIENCY_RATIO_OFF (40) + #define PCU_CR_PLATFORM_INFO_PCU_MAX_EFFICIENCY_RATIO_WID ( 8) + #define PCU_CR_PLATFORM_INFO_PCU_MAX_EFFICIENCY_RATIO_MSK (0xFF0000000000) + #define PCU_CR_PLATFORM_INFO_PCU_MAX_EFFICIENCY_RATIO_MAX (0x000000FF) + #define PCU_CR_PLATFORM_INFO_PCU_MAX_EFFICIENCY_RATIO_DEF (0x00000000) + #define PCU_CR_PLATFORM_INFO_PCU_MIN_OPERATING_RATIO_OFF (48) + #define PCU_CR_PLATFORM_INFO_PCU_MIN_OPERATING_RATIO_WID ( 8) + #define PCU_CR_PLATFORM_INFO_PCU_MIN_OPERATING_RATIO_MSK (0xFF000000000000) + #define PCU_CR_PLATFORM_INFO_PCU_MIN_OPERATING_RATIO_MAX (0x000000FF) + #define PCU_CR_PLATFORM_INFO_PCU_MIN_OPERATING_RATIO_DEF (0x00000008) + +#define PCU_CR_PP1_C0_CORE_CLOCK_PCU_REG (0x00005960) + #define PCU_CR_PP1_C0_CORE_CLOCK_PCU_DATA_OFF ( 0) + #define PCU_CR_PP1_C0_CORE_CLOCK_PCU_DATA_WID (32) + #define PCU_CR_PP1_C0_CORE_CLOCK_PCU_DATA_MSK (0xFFFFFFFF) + #define PCU_CR_PP1_C0_CORE_CLOCK_PCU_DATA_MAX (0xFFFFFFFF) + #define PCU_CR_PP1_C0_CORE_CLOCK_PCU_DATA_DEF (0x00000000) + +#define PCU_CR_PP0_ANY_THREAD_ACTIVITY_PCU_REG (0x00005964) + #define PCU_CR_PP0_ANY_THREAD_ACTIVITY_PCU_DATA_OFF ( 0) + #define PCU_CR_PP0_ANY_THREAD_ACTIVITY_PCU_DATA_WID (32) + #define PCU_CR_PP0_ANY_THREAD_ACTIVITY_PCU_DATA_MSK (0xFFFFFFFF) + #define PCU_CR_PP0_ANY_THREAD_ACTIVITY_PCU_DATA_MAX (0xFFFFFFFF) + #define PCU_CR_PP0_ANY_THREAD_ACTIVITY_PCU_DATA_DEF (0x00000000) + +#define PCU_CR_PP0_EFFICIENT_CYCLES_PCU_REG (0x00005968) + #define PCU_CR_PP0_EFFICIENT_CYCLES_PCU_DATA_OFF ( 0) + #define PCU_CR_PP0_EFFICIENT_CYCLES_PCU_DATA_WID (32) + #define PCU_CR_PP0_EFFICIENT_CYCLES_PCU_DATA_MSK (0xFFFFFFFF) + #define PCU_CR_PP0_EFFICIENT_CYCLES_PCU_DATA_MAX (0xFFFFFFFF) + #define PCU_CR_PP0_EFFICIENT_CYCLES_PCU_DATA_DEF (0x00000000) + +#define PCU_CR_PP0_THREAD_ACTIVITY_PCU_REG (0x0000596C) + #define PCU_CR_PP0_THREAD_ACTIVITY_PCU_DATA_OFF ( 0) + #define PCU_CR_PP0_THREAD_ACTIVITY_PCU_DATA_WID (32) + #define PCU_CR_PP0_THREAD_ACTIVITY_PCU_DATA_MSK (0xFFFFFFFF) + #define PCU_CR_PP0_THREAD_ACTIVITY_PCU_DATA_MAX (0xFFFFFFFF) + #define PCU_CR_PP0_THREAD_ACTIVITY_PCU_DATA_DEF (0x00000000) + +#define PCU_CR_PP1_ANY_THREAD_ACTIVITY_PCU_REG (0x00005970) + #define PCU_CR_PP1_ANY_THREAD_ACTIVITY_PCU_DATA_OFF ( 0) + #define PCU_CR_PP1_ANY_THREAD_ACTIVITY_PCU_DATA_WID (32) + #define PCU_CR_PP1_ANY_THREAD_ACTIVITY_PCU_DATA_MSK (0xFFFFFFFF) + #define PCU_CR_PP1_ANY_THREAD_ACTIVITY_PCU_DATA_MAX (0xFFFFFFFF) + #define PCU_CR_PP1_ANY_THREAD_ACTIVITY_PCU_DATA_DEF (0x00000000) + +#define PCU_CR_PP1_EFFICIENT_CYCLES_PCU_REG (0x00005974) + #define PCU_CR_PP1_EFFICIENT_CYCLES_PCU_DATA_OFF ( 0) + #define PCU_CR_PP1_EFFICIENT_CYCLES_PCU_DATA_WID (32) + #define PCU_CR_PP1_EFFICIENT_CYCLES_PCU_DATA_MSK (0xFFFFFFFF) + #define PCU_CR_PP1_EFFICIENT_CYCLES_PCU_DATA_MAX (0xFFFFFFFF) + #define PCU_CR_PP1_EFFICIENT_CYCLES_PCU_DATA_DEF (0x00000000) + +#define PCU_CR_PACKAGE_TEMPERATURE_PCU_REG (0x00005978) + #define PCU_CR_PACKAGE_TEMPERATURE_PCU_DATA_OFF ( 0) + #define PCU_CR_PACKAGE_TEMPERATURE_PCU_DATA_WID ( 8) + #define PCU_CR_PACKAGE_TEMPERATURE_PCU_DATA_MSK (0x000000FF) + #define PCU_CR_PACKAGE_TEMPERATURE_PCU_DATA_MAX (0x000000FF) + #define PCU_CR_PACKAGE_TEMPERATURE_PCU_DATA_DEF (0x00000000) + +#define PCU_CR_PP0_TEMPERATURE_PCU_REG (0x0000597C) + #define PCU_CR_PP0_TEMPERATURE_PCU_DATA_OFF ( 0) + #define PCU_CR_PP0_TEMPERATURE_PCU_DATA_WID ( 8) + #define PCU_CR_PP0_TEMPERATURE_PCU_DATA_MSK (0x000000FF) + #define PCU_CR_PP0_TEMPERATURE_PCU_DATA_MAX (0x000000FF) + #define PCU_CR_PP0_TEMPERATURE_PCU_DATA_DEF (0x00000000) + +#define PCU_CR_PP1_TEMPERATURE_PCU_REG (0x00005980) + #define PCU_CR_PP1_TEMPERATURE_PCU_DATA_OFF ( 0) + #define PCU_CR_PP1_TEMPERATURE_PCU_DATA_WID ( 8) + #define PCU_CR_PP1_TEMPERATURE_PCU_DATA_MSK (0x000000FF) + #define PCU_CR_PP1_TEMPERATURE_PCU_DATA_MAX (0x000000FF) + #define PCU_CR_PP1_TEMPERATURE_PCU_DATA_DEF (0x00000000) + +#define PCU_CR_PCU_REFERENCE_CLOCK_PCU_REG (0x00005984) + #define PCU_CR_PCU_REFERENCE_CLOCK_PCU_TIME_VAL_OFF ( 0) + #define PCU_CR_PCU_REFERENCE_CLOCK_PCU_TIME_VAL_WID (32) + #define PCU_CR_PCU_REFERENCE_CLOCK_PCU_TIME_VAL_MSK (0xFFFFFFFF) + #define PCU_CR_PCU_REFERENCE_CLOCK_PCU_TIME_VAL_MAX (0xFFFFFFFF) + #define PCU_CR_PCU_REFERENCE_CLOCK_PCU_TIME_VAL_DEF (0x00000000) + +#define PCU_CR_DEVICE_SHARED_IDLE_DURATION_PCU_REG (0x00005988) + #define PCU_CR_DEVICE_SHARED_IDLE_DURATION_PCU_RESERVED_OFF ( 0) + #define PCU_CR_DEVICE_SHARED_IDLE_DURATION_PCU_RESERVED_WID ( 1) + #define PCU_CR_DEVICE_SHARED_IDLE_DURATION_PCU_RESERVED_MSK (0x00000001) + #define PCU_CR_DEVICE_SHARED_IDLE_DURATION_PCU_RESERVED_MAX (0x00000001) + #define PCU_CR_DEVICE_SHARED_IDLE_DURATION_PCU_RESERVED_DEF (0x00000000) + #define PCU_CR_DEVICE_SHARED_IDLE_DURATION_PCU_VALID_OFF ( 1) + #define PCU_CR_DEVICE_SHARED_IDLE_DURATION_PCU_VALID_WID ( 1) + #define PCU_CR_DEVICE_SHARED_IDLE_DURATION_PCU_VALID_MSK (0x00000002) + #define PCU_CR_DEVICE_SHARED_IDLE_DURATION_PCU_VALID_MAX (0x00000001) + #define PCU_CR_DEVICE_SHARED_IDLE_DURATION_PCU_VALID_DEF (0x00000000) + #define PCU_CR_DEVICE_SHARED_IDLE_DURATION_PCU_RESERVED_BITS_OFF ( 2) + #define PCU_CR_DEVICE_SHARED_IDLE_DURATION_PCU_RESERVED_BITS_WID ( 4) + #define PCU_CR_DEVICE_SHARED_IDLE_DURATION_PCU_RESERVED_BITS_MSK (0x0000003C) + #define PCU_CR_DEVICE_SHARED_IDLE_DURATION_PCU_RESERVED_BITS_MAX (0x0000000F) + #define PCU_CR_DEVICE_SHARED_IDLE_DURATION_PCU_RESERVED_BITS_DEF (0x00000000) + #define PCU_CR_DEVICE_SHARED_IDLE_DURATION_PCU_OD_OFF ( 6) + #define PCU_CR_DEVICE_SHARED_IDLE_DURATION_PCU_OD_WID ( 1) + #define PCU_CR_DEVICE_SHARED_IDLE_DURATION_PCU_OD_MSK (0x00000040) + #define PCU_CR_DEVICE_SHARED_IDLE_DURATION_PCU_OD_MAX (0x00000001) + #define PCU_CR_DEVICE_SHARED_IDLE_DURATION_PCU_OD_DEF (0x00000000) + #define PCU_CR_DEVICE_SHARED_IDLE_DURATION_PCU_IM_OFF ( 7) + #define PCU_CR_DEVICE_SHARED_IDLE_DURATION_PCU_IM_WID ( 1) + #define PCU_CR_DEVICE_SHARED_IDLE_DURATION_PCU_IM_MSK (0x00000080) + #define PCU_CR_DEVICE_SHARED_IDLE_DURATION_PCU_IM_MAX (0x00000001) + #define PCU_CR_DEVICE_SHARED_IDLE_DURATION_PCU_IM_DEF (0x00000000) + #define PCU_CR_DEVICE_SHARED_IDLE_DURATION_PCU_NEXT_DEVICE_ACTIVITY_OFF ( 8) + #define PCU_CR_DEVICE_SHARED_IDLE_DURATION_PCU_NEXT_DEVICE_ACTIVITY_WID (21) + #define PCU_CR_DEVICE_SHARED_IDLE_DURATION_PCU_NEXT_DEVICE_ACTIVITY_MSK (0x1FFFFF00) + #define PCU_CR_DEVICE_SHARED_IDLE_DURATION_PCU_NEXT_DEVICE_ACTIVITY_MAX (0x001FFFFF) + #define PCU_CR_DEVICE_SHARED_IDLE_DURATION_PCU_NEXT_DEVICE_ACTIVITY_DEF (0x00000000) + +#define PCU_CR_DEVICE_DEDICATED_IDLE_DURATION_PCU_REG (0x0000598C) + #define PCU_CR_DEVICE_DEDICATED_IDLE_DURATION_PCU_USED_OFF ( 0) + #define PCU_CR_DEVICE_DEDICATED_IDLE_DURATION_PCU_USED_WID ( 1) + #define PCU_CR_DEVICE_DEDICATED_IDLE_DURATION_PCU_USED_MSK (0x00000001) + #define PCU_CR_DEVICE_DEDICATED_IDLE_DURATION_PCU_USED_MAX (0x00000001) + #define PCU_CR_DEVICE_DEDICATED_IDLE_DURATION_PCU_USED_DEF (0x00000000) + #define PCU_CR_DEVICE_DEDICATED_IDLE_DURATION_PCU_VALID_OFF ( 1) + #define PCU_CR_DEVICE_DEDICATED_IDLE_DURATION_PCU_VALID_WID ( 1) + #define PCU_CR_DEVICE_DEDICATED_IDLE_DURATION_PCU_VALID_MSK (0x00000002) + #define PCU_CR_DEVICE_DEDICATED_IDLE_DURATION_PCU_VALID_MAX (0x00000001) + #define PCU_CR_DEVICE_DEDICATED_IDLE_DURATION_PCU_VALID_DEF (0x00000000) + #define PCU_CR_DEVICE_DEDICATED_IDLE_DURATION_PCU_RESERVED_BITS_OFF ( 2) + #define PCU_CR_DEVICE_DEDICATED_IDLE_DURATION_PCU_RESERVED_BITS_WID ( 4) + #define PCU_CR_DEVICE_DEDICATED_IDLE_DURATION_PCU_RESERVED_BITS_MSK (0x0000003C) + #define PCU_CR_DEVICE_DEDICATED_IDLE_DURATION_PCU_RESERVED_BITS_MAX (0x0000000F) + #define PCU_CR_DEVICE_DEDICATED_IDLE_DURATION_PCU_RESERVED_BITS_DEF (0x00000000) + #define PCU_CR_DEVICE_DEDICATED_IDLE_DURATION_PCU_OD_OFF ( 6) + #define PCU_CR_DEVICE_DEDICATED_IDLE_DURATION_PCU_OD_WID ( 1) + #define PCU_CR_DEVICE_DEDICATED_IDLE_DURATION_PCU_OD_MSK (0x00000040) + #define PCU_CR_DEVICE_DEDICATED_IDLE_DURATION_PCU_OD_MAX (0x00000001) + #define PCU_CR_DEVICE_DEDICATED_IDLE_DURATION_PCU_OD_DEF (0x00000000) + #define PCU_CR_DEVICE_DEDICATED_IDLE_DURATION_PCU_IM_OFF ( 7) + #define PCU_CR_DEVICE_DEDICATED_IDLE_DURATION_PCU_IM_WID ( 1) + #define PCU_CR_DEVICE_DEDICATED_IDLE_DURATION_PCU_IM_MSK (0x00000080) + #define PCU_CR_DEVICE_DEDICATED_IDLE_DURATION_PCU_IM_MAX (0x00000001) + #define PCU_CR_DEVICE_DEDICATED_IDLE_DURATION_PCU_IM_DEF (0x00000000) + #define PCU_CR_DEVICE_DEDICATED_IDLE_DURATION_PCU_NEXT_DEVICE_ACTIVITY_OFF ( 8) + #define PCU_CR_DEVICE_DEDICATED_IDLE_DURATION_PCU_NEXT_DEVICE_ACTIVITY_WID (21) + #define PCU_CR_DEVICE_DEDICATED_IDLE_DURATION_PCU_NEXT_DEVICE_ACTIVITY_MSK (0x1FFFFF00) + #define PCU_CR_DEVICE_DEDICATED_IDLE_DURATION_PCU_NEXT_DEVICE_ACTIVITY_MAX (0x001FFFFF) + #define PCU_CR_DEVICE_DEDICATED_IDLE_DURATION_PCU_NEXT_DEVICE_ACTIVITY_DEF (0x00000000) + +#define PCU_CR_P_STATE_LIMITS_PCU_REG (0x00005990) + #define PCU_CR_P_STATE_LIMITS_PCU_PSTT_LIM_OFF ( 0) + #define PCU_CR_P_STATE_LIMITS_PCU_PSTT_LIM_WID ( 8) + #define PCU_CR_P_STATE_LIMITS_PCU_PSTT_LIM_MSK (0x000000FF) + #define PCU_CR_P_STATE_LIMITS_PCU_PSTT_LIM_MAX (0x000000FF) + #define PCU_CR_P_STATE_LIMITS_PCU_PSTT_LIM_DEF (0x000000FF) + #define PCU_CR_P_STATE_LIMITS_PCU_PSTT_MIN_OFF ( 8) + #define PCU_CR_P_STATE_LIMITS_PCU_PSTT_MIN_WID ( 8) + #define PCU_CR_P_STATE_LIMITS_PCU_PSTT_MIN_MSK (0x0000FF00) + #define PCU_CR_P_STATE_LIMITS_PCU_PSTT_MIN_MAX (0x000000FF) + #define PCU_CR_P_STATE_LIMITS_PCU_PSTT_MIN_DEF (0x00000000) + #define PCU_CR_P_STATE_LIMITS_PCU_LOCK_OFF (31) + #define PCU_CR_P_STATE_LIMITS_PCU_LOCK_WID ( 1) + #define PCU_CR_P_STATE_LIMITS_PCU_LOCK_MSK (0x80000000) + #define PCU_CR_P_STATE_LIMITS_PCU_LOCK_MAX (0x00000001) + #define PCU_CR_P_STATE_LIMITS_PCU_LOCK_DEF (0x00000000) + +#define PCU_CR_RP_STATE_LIMITS_PCU_REG (0x00005994) + #define PCU_CR_RP_STATE_LIMITS_PCU_RPSTT_LIM_OFF ( 0) + #define PCU_CR_RP_STATE_LIMITS_PCU_RPSTT_LIM_WID ( 8) + #define PCU_CR_RP_STATE_LIMITS_PCU_RPSTT_LIM_MSK (0x000000FF) + #define PCU_CR_RP_STATE_LIMITS_PCU_RPSTT_LIM_MAX (0x000000FF) + #define PCU_CR_RP_STATE_LIMITS_PCU_RPSTT_LIM_DEF (0x000000FF) + +#define PCU_CR_RP_STATE_CAP_PCU_REG (0x00005998) + #define PCU_CR_RP_STATE_CAP_PCU_RP0_CAP_OFF ( 0) + #define PCU_CR_RP_STATE_CAP_PCU_RP0_CAP_WID ( 8) + #define PCU_CR_RP_STATE_CAP_PCU_RP0_CAP_MSK (0x000000FF) + #define PCU_CR_RP_STATE_CAP_PCU_RP0_CAP_MAX (0x000000FF) + #define PCU_CR_RP_STATE_CAP_PCU_RP0_CAP_DEF (0x00000000) + #define PCU_CR_RP_STATE_CAP_PCU_RP1_CAP_OFF ( 8) + #define PCU_CR_RP_STATE_CAP_PCU_RP1_CAP_WID ( 8) + #define PCU_CR_RP_STATE_CAP_PCU_RP1_CAP_MSK (0x0000FF00) + #define PCU_CR_RP_STATE_CAP_PCU_RP1_CAP_MAX (0x000000FF) + #define PCU_CR_RP_STATE_CAP_PCU_RP1_CAP_DEF (0x00000000) + #define PCU_CR_RP_STATE_CAP_PCU_RPN_CAP_OFF (16) + #define PCU_CR_RP_STATE_CAP_PCU_RPN_CAP_WID ( 8) + #define PCU_CR_RP_STATE_CAP_PCU_RPN_CAP_MSK (0x00FF0000) + #define PCU_CR_RP_STATE_CAP_PCU_RPN_CAP_MAX (0x000000FF) + #define PCU_CR_RP_STATE_CAP_PCU_RPN_CAP_DEF (0x00000000) + +#define PCU_CR_TEMPERATURE_TARGET_PCU_REG (0x0000599C) + #define PCU_CR_TEMPERATURE_TARGET_PCU_FAN_TEMP_TARGET_OFST_OFF ( 8) + #define PCU_CR_TEMPERATURE_TARGET_PCU_FAN_TEMP_TARGET_OFST_WID ( 8) + #define PCU_CR_TEMPERATURE_TARGET_PCU_FAN_TEMP_TARGET_OFST_MSK (0x0000FF00) + #define PCU_CR_TEMPERATURE_TARGET_PCU_FAN_TEMP_TARGET_OFST_MAX (0x000000FF) + #define PCU_CR_TEMPERATURE_TARGET_PCU_FAN_TEMP_TARGET_OFST_DEF (0x00000000) + #define PCU_CR_TEMPERATURE_TARGET_PCU_REF_TEMP_OFF (16) + #define PCU_CR_TEMPERATURE_TARGET_PCU_REF_TEMP_WID ( 8) + #define PCU_CR_TEMPERATURE_TARGET_PCU_REF_TEMP_MSK (0x00FF0000) + #define PCU_CR_TEMPERATURE_TARGET_PCU_REF_TEMP_MAX (0x000000FF) + #define PCU_CR_TEMPERATURE_TARGET_PCU_REF_TEMP_DEF (0x00000000) + #define PCU_CR_TEMPERATURE_TARGET_PCU_TJ_MAX_TCC_OFFSET_OFF (24) + #define PCU_CR_TEMPERATURE_TARGET_PCU_TJ_MAX_TCC_OFFSET_WID ( 4) + #define PCU_CR_TEMPERATURE_TARGET_PCU_TJ_MAX_TCC_OFFSET_MSK (0x0F000000) + #define PCU_CR_TEMPERATURE_TARGET_PCU_TJ_MAX_TCC_OFFSET_MAX (0x0000000F) + #define PCU_CR_TEMPERATURE_TARGET_PCU_TJ_MAX_TCC_OFFSET_DEF (0x00000000) + +#define PCU_CR_PACKAGE_RAPL_LIMIT_PCU_REG (0x000059A0) + #define PCU_CR_PACKAGE_RAPL_LIMIT_PCU_PKG_PWR_LIM_1_OFF ( 0) + #define PCU_CR_PACKAGE_RAPL_LIMIT_PCU_PKG_PWR_LIM_1_WID (15) + #define PCU_CR_PACKAGE_RAPL_LIMIT_PCU_PKG_PWR_LIM_1_MSK (0x00007FFF) + #define PCU_CR_PACKAGE_RAPL_LIMIT_PCU_PKG_PWR_LIM_1_MAX (0x00007FFF) + #define PCU_CR_PACKAGE_RAPL_LIMIT_PCU_PKG_PWR_LIM_1_DEF (0x00000000) + #define PCU_CR_PACKAGE_RAPL_LIMIT_PCU_PKG_PWR_LIM_1_EN_OFF (15) + #define PCU_CR_PACKAGE_RAPL_LIMIT_PCU_PKG_PWR_LIM_1_EN_WID ( 1) + #define PCU_CR_PACKAGE_RAPL_LIMIT_PCU_PKG_PWR_LIM_1_EN_MSK (0x00008000) + #define PCU_CR_PACKAGE_RAPL_LIMIT_PCU_PKG_PWR_LIM_1_EN_MAX (0x00000001) + #define PCU_CR_PACKAGE_RAPL_LIMIT_PCU_PKG_PWR_LIM_1_EN_DEF (0x00000000) + #define PCU_CR_PACKAGE_RAPL_LIMIT_PCU_PKG_CLMP_LIM_1_OFF (16) + #define PCU_CR_PACKAGE_RAPL_LIMIT_PCU_PKG_CLMP_LIM_1_WID ( 1) + #define PCU_CR_PACKAGE_RAPL_LIMIT_PCU_PKG_CLMP_LIM_1_MSK (0x00010000) + #define PCU_CR_PACKAGE_RAPL_LIMIT_PCU_PKG_CLMP_LIM_1_MAX (0x00000001) + #define PCU_CR_PACKAGE_RAPL_LIMIT_PCU_PKG_CLMP_LIM_1_DEF (0x00000000) + #define PCU_CR_PACKAGE_RAPL_LIMIT_PCU_PKG_PWR_LIM_1_TIME_OFF (17) + #define PCU_CR_PACKAGE_RAPL_LIMIT_PCU_PKG_PWR_LIM_1_TIME_WID ( 7) + #define PCU_CR_PACKAGE_RAPL_LIMIT_PCU_PKG_PWR_LIM_1_TIME_MSK (0x00FE0000) + #define PCU_CR_PACKAGE_RAPL_LIMIT_PCU_PKG_PWR_LIM_1_TIME_MAX (0x0000007F) + #define PCU_CR_PACKAGE_RAPL_LIMIT_PCU_PKG_PWR_LIM_1_TIME_DEF (0x00000000) + #define PCU_CR_PACKAGE_RAPL_LIMIT_PCU_PKG_PWR_LIM_2_OFF (32) + #define PCU_CR_PACKAGE_RAPL_LIMIT_PCU_PKG_PWR_LIM_2_WID (15) + #define PCU_CR_PACKAGE_RAPL_LIMIT_PCU_PKG_PWR_LIM_2_MSK (0x7FFF00000000) + #define PCU_CR_PACKAGE_RAPL_LIMIT_PCU_PKG_PWR_LIM_2_MAX (0x00007FFF) + #define PCU_CR_PACKAGE_RAPL_LIMIT_PCU_PKG_PWR_LIM_2_DEF (0x00000000) + #define PCU_CR_PACKAGE_RAPL_LIMIT_PCU_PKG_PWR_LIM_2_EN_OFF (47) + #define PCU_CR_PACKAGE_RAPL_LIMIT_PCU_PKG_PWR_LIM_2_EN_WID ( 1) + #define PCU_CR_PACKAGE_RAPL_LIMIT_PCU_PKG_PWR_LIM_2_EN_MSK (0x800000000000) + #define PCU_CR_PACKAGE_RAPL_LIMIT_PCU_PKG_PWR_LIM_2_EN_MAX (0x00000001) + #define PCU_CR_PACKAGE_RAPL_LIMIT_PCU_PKG_PWR_LIM_2_EN_DEF (0x00000000) + #define PCU_CR_PACKAGE_RAPL_LIMIT_PCU_PKG_CLMP_LIM_2_OFF (48) + #define PCU_CR_PACKAGE_RAPL_LIMIT_PCU_PKG_CLMP_LIM_2_WID ( 1) + #define PCU_CR_PACKAGE_RAPL_LIMIT_PCU_PKG_CLMP_LIM_2_MSK (0x1000000000000) + #define PCU_CR_PACKAGE_RAPL_LIMIT_PCU_PKG_CLMP_LIM_2_MAX (0x00000001) + #define PCU_CR_PACKAGE_RAPL_LIMIT_PCU_PKG_CLMP_LIM_2_DEF (0x00000000) + #define PCU_CR_PACKAGE_RAPL_LIMIT_PCU_PKG_PWR_LIM_2_TIME_OFF (49) + #define PCU_CR_PACKAGE_RAPL_LIMIT_PCU_PKG_PWR_LIM_2_TIME_WID ( 7) + #define PCU_CR_PACKAGE_RAPL_LIMIT_PCU_PKG_PWR_LIM_2_TIME_MSK (0xFE000000000000) + #define PCU_CR_PACKAGE_RAPL_LIMIT_PCU_PKG_PWR_LIM_2_TIME_MAX (0x0000007F) + #define PCU_CR_PACKAGE_RAPL_LIMIT_PCU_PKG_PWR_LIM_2_TIME_DEF (0x00000000) + #define PCU_CR_PACKAGE_RAPL_LIMIT_PCU_PKG_PWR_LIM_LOCK_OFF (63) + #define PCU_CR_PACKAGE_RAPL_LIMIT_PCU_PKG_PWR_LIM_LOCK_WID ( 1) + #define PCU_CR_PACKAGE_RAPL_LIMIT_PCU_PKG_PWR_LIM_LOCK_MSK (0x8000000000000000) + #define PCU_CR_PACKAGE_RAPL_LIMIT_PCU_PKG_PWR_LIM_LOCK_MAX (0x00000001) + #define PCU_CR_PACKAGE_RAPL_LIMIT_PCU_PKG_PWR_LIM_LOCK_DEF (0x00000000) + +#define PCU_CR_PRIP_TURBO_PWR_LIM_PCU_REG (0x000059A8) + #define PCU_CR_PRIP_TURBO_PWR_LIM_PCU_IA_PP_PWR_LIM_OFF ( 0) + #define PCU_CR_PRIP_TURBO_PWR_LIM_PCU_IA_PP_PWR_LIM_WID (15) + #define PCU_CR_PRIP_TURBO_PWR_LIM_PCU_IA_PP_PWR_LIM_MSK (0x00007FFF) + #define PCU_CR_PRIP_TURBO_PWR_LIM_PCU_IA_PP_PWR_LIM_MAX (0x00007FFF) + #define PCU_CR_PRIP_TURBO_PWR_LIM_PCU_IA_PP_PWR_LIM_DEF (0x00000000) + #define PCU_CR_PRIP_TURBO_PWR_LIM_PCU_PWR_LIM_CTRL_EN_OFF (15) + #define PCU_CR_PRIP_TURBO_PWR_LIM_PCU_PWR_LIM_CTRL_EN_WID ( 1) + #define PCU_CR_PRIP_TURBO_PWR_LIM_PCU_PWR_LIM_CTRL_EN_MSK (0x00008000) + #define PCU_CR_PRIP_TURBO_PWR_LIM_PCU_PWR_LIM_CTRL_EN_MAX (0x00000001) + #define PCU_CR_PRIP_TURBO_PWR_LIM_PCU_PWR_LIM_CTRL_EN_DEF (0x00000000) + #define PCU_CR_PRIP_TURBO_PWR_LIM_PCU_PP_CLAMP_LIM_OFF (16) + #define PCU_CR_PRIP_TURBO_PWR_LIM_PCU_PP_CLAMP_LIM_WID ( 1) + #define PCU_CR_PRIP_TURBO_PWR_LIM_PCU_PP_CLAMP_LIM_MSK (0x00010000) + #define PCU_CR_PRIP_TURBO_PWR_LIM_PCU_PP_CLAMP_LIM_MAX (0x00000001) + #define PCU_CR_PRIP_TURBO_PWR_LIM_PCU_PP_CLAMP_LIM_DEF (0x00000000) + #define PCU_CR_PRIP_TURBO_PWR_LIM_PCU_CTRL_TIME_WIN_OFF (17) + #define PCU_CR_PRIP_TURBO_PWR_LIM_PCU_CTRL_TIME_WIN_WID ( 7) + #define PCU_CR_PRIP_TURBO_PWR_LIM_PCU_CTRL_TIME_WIN_MSK (0x00FE0000) + #define PCU_CR_PRIP_TURBO_PWR_LIM_PCU_CTRL_TIME_WIN_MAX (0x0000007F) + #define PCU_CR_PRIP_TURBO_PWR_LIM_PCU_CTRL_TIME_WIN_DEF (0x00000000) + #define PCU_CR_PRIP_TURBO_PWR_LIM_PCU_PP_PWR_LIM_LOCK_OFF (31) + #define PCU_CR_PRIP_TURBO_PWR_LIM_PCU_PP_PWR_LIM_LOCK_WID ( 1) + #define PCU_CR_PRIP_TURBO_PWR_LIM_PCU_PP_PWR_LIM_LOCK_MSK (0x80000000) + #define PCU_CR_PRIP_TURBO_PWR_LIM_PCU_PP_PWR_LIM_LOCK_MAX (0x00000001) + #define PCU_CR_PRIP_TURBO_PWR_LIM_PCU_PP_PWR_LIM_LOCK_DEF (0x00000000) + +#define PCU_CR_SECP_TURBO_PWR_LIM_PCU_REG (0x000059AC) + #define PCU_CR_SECP_TURBO_PWR_LIM_PCU_NON_IA_PP_PWR_LIM_OFF ( 0) + #define PCU_CR_SECP_TURBO_PWR_LIM_PCU_NON_IA_PP_PWR_LIM_WID (15) + #define PCU_CR_SECP_TURBO_PWR_LIM_PCU_NON_IA_PP_PWR_LIM_MSK (0x00007FFF) + #define PCU_CR_SECP_TURBO_PWR_LIM_PCU_NON_IA_PP_PWR_LIM_MAX (0x00007FFF) + #define PCU_CR_SECP_TURBO_PWR_LIM_PCU_NON_IA_PP_PWR_LIM_DEF (0x00000000) + #define PCU_CR_SECP_TURBO_PWR_LIM_PCU_PWR_LIM_CTRL_EN_OFF (15) + #define PCU_CR_SECP_TURBO_PWR_LIM_PCU_PWR_LIM_CTRL_EN_WID ( 1) + #define PCU_CR_SECP_TURBO_PWR_LIM_PCU_PWR_LIM_CTRL_EN_MSK (0x00008000) + #define PCU_CR_SECP_TURBO_PWR_LIM_PCU_PWR_LIM_CTRL_EN_MAX (0x00000001) + #define PCU_CR_SECP_TURBO_PWR_LIM_PCU_PWR_LIM_CTRL_EN_DEF (0x00000000) + #define PCU_CR_SECP_TURBO_PWR_LIM_PCU_PP_CLAMP_LIM_OFF (16) + #define PCU_CR_SECP_TURBO_PWR_LIM_PCU_PP_CLAMP_LIM_WID ( 1) + #define PCU_CR_SECP_TURBO_PWR_LIM_PCU_PP_CLAMP_LIM_MSK (0x00010000) + #define PCU_CR_SECP_TURBO_PWR_LIM_PCU_PP_CLAMP_LIM_MAX (0x00000001) + #define PCU_CR_SECP_TURBO_PWR_LIM_PCU_PP_CLAMP_LIM_DEF (0x00000000) + #define PCU_CR_SECP_TURBO_PWR_LIM_PCU_CTRL_TIME_WIN_OFF (17) + #define PCU_CR_SECP_TURBO_PWR_LIM_PCU_CTRL_TIME_WIN_WID ( 7) + #define PCU_CR_SECP_TURBO_PWR_LIM_PCU_CTRL_TIME_WIN_MSK (0x00FE0000) + #define PCU_CR_SECP_TURBO_PWR_LIM_PCU_CTRL_TIME_WIN_MAX (0x0000007F) + #define PCU_CR_SECP_TURBO_PWR_LIM_PCU_CTRL_TIME_WIN_DEF (0x00000000) + #define PCU_CR_SECP_TURBO_PWR_LIM_PCU_SP_PWR_LIM_LOCK_OFF (31) + #define PCU_CR_SECP_TURBO_PWR_LIM_PCU_SP_PWR_LIM_LOCK_WID ( 1) + #define PCU_CR_SECP_TURBO_PWR_LIM_PCU_SP_PWR_LIM_LOCK_MSK (0x80000000) + #define PCU_CR_SECP_TURBO_PWR_LIM_PCU_SP_PWR_LIM_LOCK_MAX (0x00000001) + #define PCU_CR_SECP_TURBO_PWR_LIM_PCU_SP_PWR_LIM_LOCK_DEF (0x00000000) + +#define PCU_CR_VR_CURRENT_CONFIG_PCU_REG (0x000059B0) + #define PCU_CR_VR_CURRENT_CONFIG_PCU_CURRENT_LIMIT_OFF ( 0) + #define PCU_CR_VR_CURRENT_CONFIG_PCU_CURRENT_LIMIT_WID (13) + #define PCU_CR_VR_CURRENT_CONFIG_PCU_CURRENT_LIMIT_MSK (0x00001FFF) + #define PCU_CR_VR_CURRENT_CONFIG_PCU_CURRENT_LIMIT_MAX (0x00001FFF) + #define PCU_CR_VR_CURRENT_CONFIG_PCU_CURRENT_LIMIT_DEF (0x00000190) + #define PCU_CR_VR_CURRENT_CONFIG_PCU_LOCK_OFF (31) + #define PCU_CR_VR_CURRENT_CONFIG_PCU_LOCK_WID ( 1) + #define PCU_CR_VR_CURRENT_CONFIG_PCU_LOCK_MSK (0x80000000) + #define PCU_CR_VR_CURRENT_CONFIG_PCU_LOCK_MAX (0x00000001) + #define PCU_CR_VR_CURRENT_CONFIG_PCU_LOCK_DEF (0x00000000) + #define PCU_CR_VR_CURRENT_CONFIG_PCU_PSI1_THRESHOLD_OFF (32) + #define PCU_CR_VR_CURRENT_CONFIG_PCU_PSI1_THRESHOLD_WID (10) + #define PCU_CR_VR_CURRENT_CONFIG_PCU_PSI1_THRESHOLD_MSK (0x3FF00000000) + #define PCU_CR_VR_CURRENT_CONFIG_PCU_PSI1_THRESHOLD_MAX (0x000003FF) + #define PCU_CR_VR_CURRENT_CONFIG_PCU_PSI1_THRESHOLD_DEF (0x00000000) + #define PCU_CR_VR_CURRENT_CONFIG_PCU_PSI2_THRESHOLD_OFF (42) + #define PCU_CR_VR_CURRENT_CONFIG_PCU_PSI2_THRESHOLD_WID (10) + #define PCU_CR_VR_CURRENT_CONFIG_PCU_PSI2_THRESHOLD_MSK (0xFFC0000000000) + #define PCU_CR_VR_CURRENT_CONFIG_PCU_PSI2_THRESHOLD_MAX (0x000003FF) + #define PCU_CR_VR_CURRENT_CONFIG_PCU_PSI2_THRESHOLD_DEF (0x00000000) + #define PCU_CR_VR_CURRENT_CONFIG_PCU_PSI3_THRESHOLD_OFF (52) + #define PCU_CR_VR_CURRENT_CONFIG_PCU_PSI3_THRESHOLD_WID (10) + #define PCU_CR_VR_CURRENT_CONFIG_PCU_PSI3_THRESHOLD_MSK (0x3FF0000000000000) + #define PCU_CR_VR_CURRENT_CONFIG_PCU_PSI3_THRESHOLD_MAX (0x000003FF) + #define PCU_CR_VR_CURRENT_CONFIG_PCU_PSI3_THRESHOLD_DEF (0x00000000) + #define PCU_CR_VR_CURRENT_CONFIG_PCU_RESERVED_OFF (62) + #define PCU_CR_VR_CURRENT_CONFIG_PCU_RESERVED_WID ( 2) + #define PCU_CR_VR_CURRENT_CONFIG_PCU_RESERVED_MSK (0xC000000000000000) + #define PCU_CR_VR_CURRENT_CONFIG_PCU_RESERVED_MAX (0x00000003) + #define PCU_CR_VR_CURRENT_CONFIG_PCU_RESERVED_DEF (0x00000000) + +#define PCU_CR_MRC_ODT_POWER_SAVING_PCU_REG (0x000059B8) + #define PCU_CR_MRC_ODT_POWER_SAVING_PCU_MRC_Saving_Rd_OFF ( 0) + #define PCU_CR_MRC_ODT_POWER_SAVING_PCU_MRC_Saving_Rd_WID ( 8) + #define PCU_CR_MRC_ODT_POWER_SAVING_PCU_MRC_Saving_Rd_MSK (0x000000FF) + #define PCU_CR_MRC_ODT_POWER_SAVING_PCU_MRC_Saving_Rd_MAX (0x000000FF) + #define PCU_CR_MRC_ODT_POWER_SAVING_PCU_MRC_Saving_Rd_DEF (0x00000000) + #define PCU_CR_MRC_ODT_POWER_SAVING_PCU_MRC_Saving_Wt_OFF ( 8) + #define PCU_CR_MRC_ODT_POWER_SAVING_PCU_MRC_Saving_Wt_WID ( 8) + #define PCU_CR_MRC_ODT_POWER_SAVING_PCU_MRC_Saving_Wt_MSK (0x0000FF00) + #define PCU_CR_MRC_ODT_POWER_SAVING_PCU_MRC_Saving_Wt_MAX (0x000000FF) + #define PCU_CR_MRC_ODT_POWER_SAVING_PCU_MRC_Saving_Wt_DEF (0x00000000) + #define PCU_CR_MRC_ODT_POWER_SAVING_PCU_MRC_Saving_Cmd_OFF (16) + #define PCU_CR_MRC_ODT_POWER_SAVING_PCU_MRC_Saving_Cmd_WID ( 8) + #define PCU_CR_MRC_ODT_POWER_SAVING_PCU_MRC_Saving_Cmd_MSK (0x00FF0000) + #define PCU_CR_MRC_ODT_POWER_SAVING_PCU_MRC_Saving_Cmd_MAX (0x000000FF) + #define PCU_CR_MRC_ODT_POWER_SAVING_PCU_MRC_Saving_Cmd_DEF (0x00000000) + #define PCU_CR_MRC_ODT_POWER_SAVING_PCU_RESERVED_OFF (24) + #define PCU_CR_MRC_ODT_POWER_SAVING_PCU_RESERVED_WID ( 8) + #define PCU_CR_MRC_ODT_POWER_SAVING_PCU_RESERVED_MSK (0xFF000000) + #define PCU_CR_MRC_ODT_POWER_SAVING_PCU_RESERVED_MAX (0x000000FF) + #define PCU_CR_MRC_ODT_POWER_SAVING_PCU_RESERVED_DEF (0x00000000) + +#define PCU_CR_THERM_STATUS_GT_PCU_REG (0x000059C0) + #define PCU_CR_THERM_STATUS_GT_PCU_THERMAL_MONITOR_STATUS_OFF ( 0) + #define PCU_CR_THERM_STATUS_GT_PCU_THERMAL_MONITOR_STATUS_WID ( 1) + #define PCU_CR_THERM_STATUS_GT_PCU_THERMAL_MONITOR_STATUS_MSK (0x00000001) + #define PCU_CR_THERM_STATUS_GT_PCU_THERMAL_MONITOR_STATUS_MAX (0x00000001) + #define PCU_CR_THERM_STATUS_GT_PCU_THERMAL_MONITOR_STATUS_DEF (0x00000000) + #define PCU_CR_THERM_STATUS_GT_PCU_THERMAL_MONITOR_LOG_OFF ( 1) + #define PCU_CR_THERM_STATUS_GT_PCU_THERMAL_MONITOR_LOG_WID ( 1) + #define PCU_CR_THERM_STATUS_GT_PCU_THERMAL_MONITOR_LOG_MSK (0x00000002) + #define PCU_CR_THERM_STATUS_GT_PCU_THERMAL_MONITOR_LOG_MAX (0x00000001) + #define PCU_CR_THERM_STATUS_GT_PCU_THERMAL_MONITOR_LOG_DEF (0x00000000) + #define PCU_CR_THERM_STATUS_GT_PCU_PROCHOT_STATUS_OFF ( 2) + #define PCU_CR_THERM_STATUS_GT_PCU_PROCHOT_STATUS_WID ( 1) + #define PCU_CR_THERM_STATUS_GT_PCU_PROCHOT_STATUS_MSK (0x00000004) + #define PCU_CR_THERM_STATUS_GT_PCU_PROCHOT_STATUS_MAX (0x00000001) + #define PCU_CR_THERM_STATUS_GT_PCU_PROCHOT_STATUS_DEF (0x00000000) + #define PCU_CR_THERM_STATUS_GT_PCU_PROCHOT_LOG_OFF ( 3) + #define PCU_CR_THERM_STATUS_GT_PCU_PROCHOT_LOG_WID ( 1) + #define PCU_CR_THERM_STATUS_GT_PCU_PROCHOT_LOG_MSK (0x00000008) + #define PCU_CR_THERM_STATUS_GT_PCU_PROCHOT_LOG_MAX (0x00000001) + #define PCU_CR_THERM_STATUS_GT_PCU_PROCHOT_LOG_DEF (0x00000000) + #define PCU_CR_THERM_STATUS_GT_PCU_OUT_OF_SPEC_STATUS_OFF ( 4) + #define PCU_CR_THERM_STATUS_GT_PCU_OUT_OF_SPEC_STATUS_WID ( 1) + #define PCU_CR_THERM_STATUS_GT_PCU_OUT_OF_SPEC_STATUS_MSK (0x00000010) + #define PCU_CR_THERM_STATUS_GT_PCU_OUT_OF_SPEC_STATUS_MAX (0x00000001) + #define PCU_CR_THERM_STATUS_GT_PCU_OUT_OF_SPEC_STATUS_DEF (0x00000000) + #define PCU_CR_THERM_STATUS_GT_PCU_OUT_OF_SPEC_LOG_OFF ( 5) + #define PCU_CR_THERM_STATUS_GT_PCU_OUT_OF_SPEC_LOG_WID ( 1) + #define PCU_CR_THERM_STATUS_GT_PCU_OUT_OF_SPEC_LOG_MSK (0x00000020) + #define PCU_CR_THERM_STATUS_GT_PCU_OUT_OF_SPEC_LOG_MAX (0x00000001) + #define PCU_CR_THERM_STATUS_GT_PCU_OUT_OF_SPEC_LOG_DEF (0x00000000) + #define PCU_CR_THERM_STATUS_GT_PCU_THRESHOLD1_STATUS_OFF ( 6) + #define PCU_CR_THERM_STATUS_GT_PCU_THRESHOLD1_STATUS_WID ( 1) + #define PCU_CR_THERM_STATUS_GT_PCU_THRESHOLD1_STATUS_MSK (0x00000040) + #define PCU_CR_THERM_STATUS_GT_PCU_THRESHOLD1_STATUS_MAX (0x00000001) + #define PCU_CR_THERM_STATUS_GT_PCU_THRESHOLD1_STATUS_DEF (0x00000000) + #define PCU_CR_THERM_STATUS_GT_PCU_THRESHOLD1_LOG_OFF ( 7) + #define PCU_CR_THERM_STATUS_GT_PCU_THRESHOLD1_LOG_WID ( 1) + #define PCU_CR_THERM_STATUS_GT_PCU_THRESHOLD1_LOG_MSK (0x00000080) + #define PCU_CR_THERM_STATUS_GT_PCU_THRESHOLD1_LOG_MAX (0x00000001) + #define PCU_CR_THERM_STATUS_GT_PCU_THRESHOLD1_LOG_DEF (0x00000000) + #define PCU_CR_THERM_STATUS_GT_PCU_THRESHOLD2_STATUS_OFF ( 8) + #define PCU_CR_THERM_STATUS_GT_PCU_THRESHOLD2_STATUS_WID ( 1) + #define PCU_CR_THERM_STATUS_GT_PCU_THRESHOLD2_STATUS_MSK (0x00000100) + #define PCU_CR_THERM_STATUS_GT_PCU_THRESHOLD2_STATUS_MAX (0x00000001) + #define PCU_CR_THERM_STATUS_GT_PCU_THRESHOLD2_STATUS_DEF (0x00000000) + #define PCU_CR_THERM_STATUS_GT_PCU_THRESHOLD2_LOG_OFF ( 9) + #define PCU_CR_THERM_STATUS_GT_PCU_THRESHOLD2_LOG_WID ( 1) + #define PCU_CR_THERM_STATUS_GT_PCU_THRESHOLD2_LOG_MSK (0x00000200) + #define PCU_CR_THERM_STATUS_GT_PCU_THRESHOLD2_LOG_MAX (0x00000001) + #define PCU_CR_THERM_STATUS_GT_PCU_THRESHOLD2_LOG_DEF (0x00000000) + #define PCU_CR_THERM_STATUS_GT_PCU_POWER_LIMITATION_STATUS_OFF (10) + #define PCU_CR_THERM_STATUS_GT_PCU_POWER_LIMITATION_STATUS_WID ( 1) + #define PCU_CR_THERM_STATUS_GT_PCU_POWER_LIMITATION_STATUS_MSK (0x00000400) + #define PCU_CR_THERM_STATUS_GT_PCU_POWER_LIMITATION_STATUS_MAX (0x00000001) + #define PCU_CR_THERM_STATUS_GT_PCU_POWER_LIMITATION_STATUS_DEF (0x00000000) + #define PCU_CR_THERM_STATUS_GT_PCU_POWER_LIMITATION_LOG_OFF (11) + #define PCU_CR_THERM_STATUS_GT_PCU_POWER_LIMITATION_LOG_WID ( 1) + #define PCU_CR_THERM_STATUS_GT_PCU_POWER_LIMITATION_LOG_MSK (0x00000800) + #define PCU_CR_THERM_STATUS_GT_PCU_POWER_LIMITATION_LOG_MAX (0x00000001) + #define PCU_CR_THERM_STATUS_GT_PCU_POWER_LIMITATION_LOG_DEF (0x00000000) + #define PCU_CR_THERM_STATUS_GT_PCU_TEMPERATURE_OFF (16) + #define PCU_CR_THERM_STATUS_GT_PCU_TEMPERATURE_WID ( 7) + #define PCU_CR_THERM_STATUS_GT_PCU_TEMPERATURE_MSK (0x007F0000) + #define PCU_CR_THERM_STATUS_GT_PCU_TEMPERATURE_MAX (0x0000007F) + #define PCU_CR_THERM_STATUS_GT_PCU_TEMPERATURE_DEF (0x00000000) + #define PCU_CR_THERM_STATUS_GT_PCU_RESOLUTION_OFF (27) + #define PCU_CR_THERM_STATUS_GT_PCU_RESOLUTION_WID ( 4) + #define PCU_CR_THERM_STATUS_GT_PCU_RESOLUTION_MSK (0x78000000) + #define PCU_CR_THERM_STATUS_GT_PCU_RESOLUTION_MAX (0x0000000F) + #define PCU_CR_THERM_STATUS_GT_PCU_RESOLUTION_DEF (0x00000001) + #define PCU_CR_THERM_STATUS_GT_PCU_VALID_OFF (31) + #define PCU_CR_THERM_STATUS_GT_PCU_VALID_WID ( 1) + #define PCU_CR_THERM_STATUS_GT_PCU_VALID_MSK (0x80000000) + #define PCU_CR_THERM_STATUS_GT_PCU_VALID_MAX (0x00000001) + #define PCU_CR_THERM_STATUS_GT_PCU_VALID_DEF (0x00000000) + +#define PCU_CR_THERM_INTERRUPT_GT_PCU_REG (0x000059C4) + #define PCU_CR_THERM_INTERRUPT_GT_PCU_HIGH_TEMP_INT_ENABLE_OFF ( 0) + #define PCU_CR_THERM_INTERRUPT_GT_PCU_HIGH_TEMP_INT_ENABLE_WID ( 1) + #define PCU_CR_THERM_INTERRUPT_GT_PCU_HIGH_TEMP_INT_ENABLE_MSK (0x00000001) + #define PCU_CR_THERM_INTERRUPT_GT_PCU_HIGH_TEMP_INT_ENABLE_MAX (0x00000001) + #define PCU_CR_THERM_INTERRUPT_GT_PCU_HIGH_TEMP_INT_ENABLE_DEF (0x00000000) + #define PCU_CR_THERM_INTERRUPT_GT_PCU_LOW_TEMP_INT_ENABLE_OFF ( 1) + #define PCU_CR_THERM_INTERRUPT_GT_PCU_LOW_TEMP_INT_ENABLE_WID ( 1) + #define PCU_CR_THERM_INTERRUPT_GT_PCU_LOW_TEMP_INT_ENABLE_MSK (0x00000002) + #define PCU_CR_THERM_INTERRUPT_GT_PCU_LOW_TEMP_INT_ENABLE_MAX (0x00000001) + #define PCU_CR_THERM_INTERRUPT_GT_PCU_LOW_TEMP_INT_ENABLE_DEF (0x00000000) + #define PCU_CR_THERM_INTERRUPT_GT_PCU_PROCHOT_INT_ENABLE_OFF ( 2) + #define PCU_CR_THERM_INTERRUPT_GT_PCU_PROCHOT_INT_ENABLE_WID ( 1) + #define PCU_CR_THERM_INTERRUPT_GT_PCU_PROCHOT_INT_ENABLE_MSK (0x00000004) + #define PCU_CR_THERM_INTERRUPT_GT_PCU_PROCHOT_INT_ENABLE_MAX (0x00000001) + #define PCU_CR_THERM_INTERRUPT_GT_PCU_PROCHOT_INT_ENABLE_DEF (0x00000000) + #define PCU_CR_THERM_INTERRUPT_GT_PCU_OUT_OF_SPEC_INT_ENABLE_OFF ( 4) + #define PCU_CR_THERM_INTERRUPT_GT_PCU_OUT_OF_SPEC_INT_ENABLE_WID ( 1) + #define PCU_CR_THERM_INTERRUPT_GT_PCU_OUT_OF_SPEC_INT_ENABLE_MSK (0x00000010) + #define PCU_CR_THERM_INTERRUPT_GT_PCU_OUT_OF_SPEC_INT_ENABLE_MAX (0x00000001) + #define PCU_CR_THERM_INTERRUPT_GT_PCU_OUT_OF_SPEC_INT_ENABLE_DEF (0x00000000) + #define PCU_CR_THERM_INTERRUPT_GT_PCU_THRESHOLD_1_REL_TEMP_OFF ( 8) + #define PCU_CR_THERM_INTERRUPT_GT_PCU_THRESHOLD_1_REL_TEMP_WID ( 7) + #define PCU_CR_THERM_INTERRUPT_GT_PCU_THRESHOLD_1_REL_TEMP_MSK (0x00007F00) + #define PCU_CR_THERM_INTERRUPT_GT_PCU_THRESHOLD_1_REL_TEMP_MAX (0x0000007F) + #define PCU_CR_THERM_INTERRUPT_GT_PCU_THRESHOLD_1_REL_TEMP_DEF (0x00000000) + #define PCU_CR_THERM_INTERRUPT_GT_PCU_THRESHOLD_1_INT_ENABLE_OFF (15) + #define PCU_CR_THERM_INTERRUPT_GT_PCU_THRESHOLD_1_INT_ENABLE_WID ( 1) + #define PCU_CR_THERM_INTERRUPT_GT_PCU_THRESHOLD_1_INT_ENABLE_MSK (0x00008000) + #define PCU_CR_THERM_INTERRUPT_GT_PCU_THRESHOLD_1_INT_ENABLE_MAX (0x00000001) + #define PCU_CR_THERM_INTERRUPT_GT_PCU_THRESHOLD_1_INT_ENABLE_DEF (0x00000000) + #define PCU_CR_THERM_INTERRUPT_GT_PCU_THRESHOLD_2_REL_TEMP_OFF (16) + #define PCU_CR_THERM_INTERRUPT_GT_PCU_THRESHOLD_2_REL_TEMP_WID ( 7) + #define PCU_CR_THERM_INTERRUPT_GT_PCU_THRESHOLD_2_REL_TEMP_MSK (0x007F0000) + #define PCU_CR_THERM_INTERRUPT_GT_PCU_THRESHOLD_2_REL_TEMP_MAX (0x0000007F) + #define PCU_CR_THERM_INTERRUPT_GT_PCU_THRESHOLD_2_REL_TEMP_DEF (0x00000000) + #define PCU_CR_THERM_INTERRUPT_GT_PCU_THRESHOLD_2_INT_ENABLE_OFF (23) + #define PCU_CR_THERM_INTERRUPT_GT_PCU_THRESHOLD_2_INT_ENABLE_WID ( 1) + #define PCU_CR_THERM_INTERRUPT_GT_PCU_THRESHOLD_2_INT_ENABLE_MSK (0x00800000) + #define PCU_CR_THERM_INTERRUPT_GT_PCU_THRESHOLD_2_INT_ENABLE_MAX (0x00000001) + #define PCU_CR_THERM_INTERRUPT_GT_PCU_THRESHOLD_2_INT_ENABLE_DEF (0x00000000) + #define PCU_CR_THERM_INTERRUPT_GT_PCU_POWER_INT_ENABLE_OFF (24) + #define PCU_CR_THERM_INTERRUPT_GT_PCU_POWER_INT_ENABLE_WID ( 1) + #define PCU_CR_THERM_INTERRUPT_GT_PCU_POWER_INT_ENABLE_MSK (0x01000000) + #define PCU_CR_THERM_INTERRUPT_GT_PCU_POWER_INT_ENABLE_MAX (0x00000001) + #define PCU_CR_THERM_INTERRUPT_GT_PCU_POWER_INT_ENABLE_DEF (0x00000000) + +#define PCU_CR_DEVICE_IDLE_DURATION_OVERRIDE_PCU_REG (0x000059C8) + #define PCU_CR_DEVICE_IDLE_DURATION_OVERRIDE_PCU_RESERVED_OFF ( 0) + #define PCU_CR_DEVICE_IDLE_DURATION_OVERRIDE_PCU_RESERVED_WID ( 1) + #define PCU_CR_DEVICE_IDLE_DURATION_OVERRIDE_PCU_RESERVED_MSK (0x00000001) + #define PCU_CR_DEVICE_IDLE_DURATION_OVERRIDE_PCU_RESERVED_MAX (0x00000001) + #define PCU_CR_DEVICE_IDLE_DURATION_OVERRIDE_PCU_RESERVED_DEF (0x00000000) + #define PCU_CR_DEVICE_IDLE_DURATION_OVERRIDE_PCU_VALID_OFF ( 1) + #define PCU_CR_DEVICE_IDLE_DURATION_OVERRIDE_PCU_VALID_WID ( 1) + #define PCU_CR_DEVICE_IDLE_DURATION_OVERRIDE_PCU_VALID_MSK (0x00000002) + #define PCU_CR_DEVICE_IDLE_DURATION_OVERRIDE_PCU_VALID_MAX (0x00000001) + #define PCU_CR_DEVICE_IDLE_DURATION_OVERRIDE_PCU_VALID_DEF (0x00000000) + #define PCU_CR_DEVICE_IDLE_DURATION_OVERRIDE_PCU_RESERVED_BITS_OFF ( 2) + #define PCU_CR_DEVICE_IDLE_DURATION_OVERRIDE_PCU_RESERVED_BITS_WID ( 4) + #define PCU_CR_DEVICE_IDLE_DURATION_OVERRIDE_PCU_RESERVED_BITS_MSK (0x0000003C) + #define PCU_CR_DEVICE_IDLE_DURATION_OVERRIDE_PCU_RESERVED_BITS_MAX (0x0000000F) + #define PCU_CR_DEVICE_IDLE_DURATION_OVERRIDE_PCU_RESERVED_BITS_DEF (0x00000000) + #define PCU_CR_DEVICE_IDLE_DURATION_OVERRIDE_PCU_OD_OFF ( 6) + #define PCU_CR_DEVICE_IDLE_DURATION_OVERRIDE_PCU_OD_WID ( 1) + #define PCU_CR_DEVICE_IDLE_DURATION_OVERRIDE_PCU_OD_MSK (0x00000040) + #define PCU_CR_DEVICE_IDLE_DURATION_OVERRIDE_PCU_OD_MAX (0x00000001) + #define PCU_CR_DEVICE_IDLE_DURATION_OVERRIDE_PCU_OD_DEF (0x00000000) + #define PCU_CR_DEVICE_IDLE_DURATION_OVERRIDE_PCU_IM_OFF ( 7) + #define PCU_CR_DEVICE_IDLE_DURATION_OVERRIDE_PCU_IM_WID ( 1) + #define PCU_CR_DEVICE_IDLE_DURATION_OVERRIDE_PCU_IM_MSK (0x00000080) + #define PCU_CR_DEVICE_IDLE_DURATION_OVERRIDE_PCU_IM_MAX (0x00000001) + #define PCU_CR_DEVICE_IDLE_DURATION_OVERRIDE_PCU_IM_DEF (0x00000000) + #define PCU_CR_DEVICE_IDLE_DURATION_OVERRIDE_PCU_NEXT_DEVICE_ACTIVITY_OFF ( 8) + #define PCU_CR_DEVICE_IDLE_DURATION_OVERRIDE_PCU_NEXT_DEVICE_ACTIVITY_WID (21) + #define PCU_CR_DEVICE_IDLE_DURATION_OVERRIDE_PCU_NEXT_DEVICE_ACTIVITY_MSK (0x1FFFFF00) + #define PCU_CR_DEVICE_IDLE_DURATION_OVERRIDE_PCU_NEXT_DEVICE_ACTIVITY_MAX (0x001FFFFF) + #define PCU_CR_DEVICE_IDLE_DURATION_OVERRIDE_PCU_NEXT_DEVICE_ACTIVITY_DEF (0x00000000) + #define PCU_CR_DEVICE_IDLE_DURATION_OVERRIDE_PCU_DISABLE_MDID_EVALUATION_OFF (29) + #define PCU_CR_DEVICE_IDLE_DURATION_OVERRIDE_PCU_DISABLE_MDID_EVALUATION_WID ( 1) + #define PCU_CR_DEVICE_IDLE_DURATION_OVERRIDE_PCU_DISABLE_MDID_EVALUATION_MSK (0x20000000) + #define PCU_CR_DEVICE_IDLE_DURATION_OVERRIDE_PCU_DISABLE_MDID_EVALUATION_MAX (0x00000001) + #define PCU_CR_DEVICE_IDLE_DURATION_OVERRIDE_PCU_DISABLE_MDID_EVALUATION_DEF (0x00000000) + #define PCU_CR_DEVICE_IDLE_DURATION_OVERRIDE_PCU_FORCE_MDID_OVERRIDE_OFF (30) + #define PCU_CR_DEVICE_IDLE_DURATION_OVERRIDE_PCU_FORCE_MDID_OVERRIDE_WID ( 1) + #define PCU_CR_DEVICE_IDLE_DURATION_OVERRIDE_PCU_FORCE_MDID_OVERRIDE_MSK (0x40000000) + #define PCU_CR_DEVICE_IDLE_DURATION_OVERRIDE_PCU_FORCE_MDID_OVERRIDE_MAX (0x00000001) + #define PCU_CR_DEVICE_IDLE_DURATION_OVERRIDE_PCU_FORCE_MDID_OVERRIDE_DEF (0x00000000) + +#define PCU_CR_GRAPHICS_INTERRUPT_RESPONSE_TIME_PCU_REG (0x000059D0) + #define PCU_CR_GRAPHICS_INTERRUPT_RESPONSE_TIME_PCU_VALUE_OFF ( 0) + #define PCU_CR_GRAPHICS_INTERRUPT_RESPONSE_TIME_PCU_VALUE_WID (10) + #define PCU_CR_GRAPHICS_INTERRUPT_RESPONSE_TIME_PCU_VALUE_MSK (0x000003FF) + #define PCU_CR_GRAPHICS_INTERRUPT_RESPONSE_TIME_PCU_VALUE_MAX (0x000003FF) + #define PCU_CR_GRAPHICS_INTERRUPT_RESPONSE_TIME_PCU_VALUE_DEF (0x00000000) + #define PCU_CR_GRAPHICS_INTERRUPT_RESPONSE_TIME_PCU_MULTIPLIER_OFF (10) + #define PCU_CR_GRAPHICS_INTERRUPT_RESPONSE_TIME_PCU_MULTIPLIER_WID ( 3) + #define PCU_CR_GRAPHICS_INTERRUPT_RESPONSE_TIME_PCU_MULTIPLIER_MSK (0x00001C00) + #define PCU_CR_GRAPHICS_INTERRUPT_RESPONSE_TIME_PCU_MULTIPLIER_MAX (0x00000007) + #define PCU_CR_GRAPHICS_INTERRUPT_RESPONSE_TIME_PCU_MULTIPLIER_DEF (0x00000000) + #define PCU_CR_GRAPHICS_INTERRUPT_RESPONSE_TIME_PCU_VALID_OFF (15) + #define PCU_CR_GRAPHICS_INTERRUPT_RESPONSE_TIME_PCU_VALID_WID ( 1) + #define PCU_CR_GRAPHICS_INTERRUPT_RESPONSE_TIME_PCU_VALID_MSK (0x00008000) + #define PCU_CR_GRAPHICS_INTERRUPT_RESPONSE_TIME_PCU_VALID_MAX (0x00000001) + #define PCU_CR_GRAPHICS_INTERRUPT_RESPONSE_TIME_PCU_VALID_DEF (0x00000000) + +#define PCU_CR_CHAP_CONFIG_PCU_REG (0x00005A00) + #define PCU_CR_CHAP_CONFIG_PCU_PECI_CMD_OFF ( 4) + #define PCU_CR_CHAP_CONFIG_PCU_PECI_CMD_WID ( 8) + #define PCU_CR_CHAP_CONFIG_PCU_PECI_CMD_MSK (0x00000FF0) + #define PCU_CR_CHAP_CONFIG_PCU_PECI_CMD_MAX (0x000000FF) + #define PCU_CR_CHAP_CONFIG_PCU_PECI_CMD_DEF (0x00000000) + +#define PCU_CR_CHAP_THRESHOLD2_PCU_REG (0x00005A08) + #define PCU_CR_CHAP_THRESHOLD2_PCU_FREQ_TH1_OFF ( 0) + #define PCU_CR_CHAP_THRESHOLD2_PCU_FREQ_TH1_WID ( 6) + #define PCU_CR_CHAP_THRESHOLD2_PCU_FREQ_TH1_MSK (0x0000003F) + #define PCU_CR_CHAP_THRESHOLD2_PCU_FREQ_TH1_MAX (0x0000003F) + #define PCU_CR_CHAP_THRESHOLD2_PCU_FREQ_TH1_DEF (0x00000000) + #define PCU_CR_CHAP_THRESHOLD2_PCU_FREQ_TH2_OFF ( 8) + #define PCU_CR_CHAP_THRESHOLD2_PCU_FREQ_TH2_WID ( 6) + #define PCU_CR_CHAP_THRESHOLD2_PCU_FREQ_TH2_MSK (0x00003F00) + #define PCU_CR_CHAP_THRESHOLD2_PCU_FREQ_TH2_MAX (0x0000003F) + #define PCU_CR_CHAP_THRESHOLD2_PCU_FREQ_TH2_DEF (0x00000000) + #define PCU_CR_CHAP_THRESHOLD2_PCU_FREQ_TH3_OFF (16) + #define PCU_CR_CHAP_THRESHOLD2_PCU_FREQ_TH3_WID ( 6) + #define PCU_CR_CHAP_THRESHOLD2_PCU_FREQ_TH3_MSK (0x003F0000) + #define PCU_CR_CHAP_THRESHOLD2_PCU_FREQ_TH3_MAX (0x0000003F) + #define PCU_CR_CHAP_THRESHOLD2_PCU_FREQ_TH3_DEF (0x00000000) + +#define PCU_CR_ENERGY_DEBUG_PCU_REG (0x00005B04) + #define PCU_CR_ENERGY_DEBUG_PCU_DEBUG_ENERGY_PP0_VALUE_OFF ( 0) + #define PCU_CR_ENERGY_DEBUG_PCU_DEBUG_ENERGY_PP0_VALUE_WID (10) + #define PCU_CR_ENERGY_DEBUG_PCU_DEBUG_ENERGY_PP0_VALUE_MSK (0x000003FF) + #define PCU_CR_ENERGY_DEBUG_PCU_DEBUG_ENERGY_PP0_VALUE_MAX (0x000003FF) + #define PCU_CR_ENERGY_DEBUG_PCU_DEBUG_ENERGY_PP0_VALUE_DEF (0x00000000) + #define PCU_CR_ENERGY_DEBUG_PCU_DEBUG_ENERGY_PP1_VALUE_OFF (10) + #define PCU_CR_ENERGY_DEBUG_PCU_DEBUG_ENERGY_PP1_VALUE_WID (10) + #define PCU_CR_ENERGY_DEBUG_PCU_DEBUG_ENERGY_PP1_VALUE_MSK (0x000FFC00) + #define PCU_CR_ENERGY_DEBUG_PCU_DEBUG_ENERGY_PP1_VALUE_MAX (0x000003FF) + #define PCU_CR_ENERGY_DEBUG_PCU_DEBUG_ENERGY_PP1_VALUE_DEF (0x00000000) + #define PCU_CR_ENERGY_DEBUG_PCU_DEBUG_ENERGY_SA_VALUE_OFF (20) + #define PCU_CR_ENERGY_DEBUG_PCU_DEBUG_ENERGY_SA_VALUE_WID (10) + #define PCU_CR_ENERGY_DEBUG_PCU_DEBUG_ENERGY_SA_VALUE_MSK (0x3FF00000) + #define PCU_CR_ENERGY_DEBUG_PCU_DEBUG_ENERGY_SA_VALUE_MAX (0x000003FF) + #define PCU_CR_ENERGY_DEBUG_PCU_DEBUG_ENERGY_SA_VALUE_DEF (0x00000000) + +#define PCU_CR_SSKPD_PCU_REG (0x00005D10) + #define PCU_CR_SSKPD_PCU_SKPD_OFF ( 0) + #define PCU_CR_SSKPD_PCU_SKPD_WID (64) + #define PCU_CR_SSKPD_PCU_SKPD_MSK (0xFFFFFFFFFFFFFFFF) + #define PCU_CR_SSKPD_PCU_SKPD_MAX (0xFFFFFFFFFFFFFFFF) + #define PCU_CR_SSKPD_PCU_SKPD_DEF (0x00000000) + +#define PCU_CR_C2C3TT_PCU_REG (0x00005D20) + #define PCU_CR_C2C3TT_PCU_PPDN_INIT_OFF ( 0) + #define PCU_CR_C2C3TT_PCU_PPDN_INIT_WID (12) + #define PCU_CR_C2C3TT_PCU_PPDN_INIT_MSK (0x00000FFF) + #define PCU_CR_C2C3TT_PCU_PPDN_INIT_MAX (0x00000FFF) + #define PCU_CR_C2C3TT_PCU_PPDN_INIT_DEF (0x00000005) + +#define PCU_CR_C2_DDR_TT_PCU_REG (0x00005D24) + #define PCU_CR_C2_DDR_TT_PCU_DDR_TIMER_VALUE_OFF ( 0) + #define PCU_CR_C2_DDR_TT_PCU_DDR_TIMER_VALUE_WID (13) + #define PCU_CR_C2_DDR_TT_PCU_DDR_TIMER_VALUE_MSK (0x00001FFF) + #define PCU_CR_C2_DDR_TT_PCU_DDR_TIMER_VALUE_MAX (0x00001FFF) + #define PCU_CR_C2_DDR_TT_PCU_DDR_TIMER_VALUE_DEF (0x000001F4) + +#define PCU_CR_PCIE_ILTR_OVRD_PCU_REG (0x00005D30) + #define PCU_CR_PCIE_ILTR_OVRD_PCU_NSTL_OFF ( 0) + #define PCU_CR_PCIE_ILTR_OVRD_PCU_NSTL_WID (10) + #define PCU_CR_PCIE_ILTR_OVRD_PCU_NSTL_MSK (0x000003FF) + #define PCU_CR_PCIE_ILTR_OVRD_PCU_NSTL_MAX (0x000003FF) + #define PCU_CR_PCIE_ILTR_OVRD_PCU_NSTL_DEF (0x00000000) + #define PCU_CR_PCIE_ILTR_OVRD_PCU_MULTIPLIER_OFF (10) + #define PCU_CR_PCIE_ILTR_OVRD_PCU_MULTIPLIER_WID ( 3) + #define PCU_CR_PCIE_ILTR_OVRD_PCU_MULTIPLIER_MSK (0x00001C00) + #define PCU_CR_PCIE_ILTR_OVRD_PCU_MULTIPLIER_MAX (0x00000007) + #define PCU_CR_PCIE_ILTR_OVRD_PCU_MULTIPLIER_DEF (0x00000000) + #define PCU_CR_PCIE_ILTR_OVRD_PCU_FORCE_NL_OFF (14) + #define PCU_CR_PCIE_ILTR_OVRD_PCU_FORCE_NL_WID ( 1) + #define PCU_CR_PCIE_ILTR_OVRD_PCU_FORCE_NL_MSK (0x00004000) + #define PCU_CR_PCIE_ILTR_OVRD_PCU_FORCE_NL_MAX (0x00000001) + #define PCU_CR_PCIE_ILTR_OVRD_PCU_FORCE_NL_DEF (0x00000000) + #define PCU_CR_PCIE_ILTR_OVRD_PCU_NL_V_OFF (15) + #define PCU_CR_PCIE_ILTR_OVRD_PCU_NL_V_WID ( 1) + #define PCU_CR_PCIE_ILTR_OVRD_PCU_NL_V_MSK (0x00008000) + #define PCU_CR_PCIE_ILTR_OVRD_PCU_NL_V_MAX (0x00000001) + #define PCU_CR_PCIE_ILTR_OVRD_PCU_NL_V_DEF (0x00000000) + #define PCU_CR_PCIE_ILTR_OVRD_PCU_SXL_OFF (16) + #define PCU_CR_PCIE_ILTR_OVRD_PCU_SXL_WID (10) + #define PCU_CR_PCIE_ILTR_OVRD_PCU_SXL_MSK (0x03FF0000) + #define PCU_CR_PCIE_ILTR_OVRD_PCU_SXL_MAX (0x000003FF) + #define PCU_CR_PCIE_ILTR_OVRD_PCU_SXL_DEF (0x00000000) + #define PCU_CR_PCIE_ILTR_OVRD_PCU_SXLM_OFF (26) + #define PCU_CR_PCIE_ILTR_OVRD_PCU_SXLM_WID ( 3) + #define PCU_CR_PCIE_ILTR_OVRD_PCU_SXLM_MSK (0x1C000000) + #define PCU_CR_PCIE_ILTR_OVRD_PCU_SXLM_MAX (0x00000007) + #define PCU_CR_PCIE_ILTR_OVRD_PCU_SXLM_DEF (0x00000000) + #define PCU_CR_PCIE_ILTR_OVRD_PCU_FORCE_SXL_OFF (30) + #define PCU_CR_PCIE_ILTR_OVRD_PCU_FORCE_SXL_WID ( 1) + #define PCU_CR_PCIE_ILTR_OVRD_PCU_FORCE_SXL_MSK (0x40000000) + #define PCU_CR_PCIE_ILTR_OVRD_PCU_FORCE_SXL_MAX (0x00000001) + #define PCU_CR_PCIE_ILTR_OVRD_PCU_FORCE_SXL_DEF (0x00000000) + #define PCU_CR_PCIE_ILTR_OVRD_PCU_SXL_V_OFF (31) + #define PCU_CR_PCIE_ILTR_OVRD_PCU_SXL_V_WID ( 1) + #define PCU_CR_PCIE_ILTR_OVRD_PCU_SXL_V_MSK (0x80000000) + #define PCU_CR_PCIE_ILTR_OVRD_PCU_SXL_V_MAX (0x00000001) + #define PCU_CR_PCIE_ILTR_OVRD_PCU_SXL_V_DEF (0x00000000) + +#define PCU_CR_PCIE_ILTR_VAL_PCU_0_REG (0x00005D34) + #define PCU_CR_PCIE_ILTR_VAL_PCU_0_NL_VALUE_OFF ( 0) + #define PCU_CR_PCIE_ILTR_VAL_PCU_0_NL_VALUE_WID (10) + #define PCU_CR_PCIE_ILTR_VAL_PCU_0_NL_VALUE_MSK (0x000003FF) + #define PCU_CR_PCIE_ILTR_VAL_PCU_0_NL_VALUE_MAX (0x000003FF) + #define PCU_CR_PCIE_ILTR_VAL_PCU_0_NL_VALUE_DEF (0x00000000) + #define PCU_CR_PCIE_ILTR_VAL_PCU_0_NL_SCALE_OFF (10) + #define PCU_CR_PCIE_ILTR_VAL_PCU_0_NL_SCALE_WID ( 3) + #define PCU_CR_PCIE_ILTR_VAL_PCU_0_NL_SCALE_MSK (0x00001C00) + #define PCU_CR_PCIE_ILTR_VAL_PCU_0_NL_SCALE_MAX (0x00000007) + #define PCU_CR_PCIE_ILTR_VAL_PCU_0_NL_SCALE_DEF (0x00000000) + #define PCU_CR_PCIE_ILTR_VAL_PCU_0_NL_RESERVED_OFF (13) + #define PCU_CR_PCIE_ILTR_VAL_PCU_0_NL_RESERVED_WID ( 2) + #define PCU_CR_PCIE_ILTR_VAL_PCU_0_NL_RESERVED_MSK (0x00006000) + #define PCU_CR_PCIE_ILTR_VAL_PCU_0_NL_RESERVED_MAX (0x00000003) + #define PCU_CR_PCIE_ILTR_VAL_PCU_0_NL_RESERVED_DEF (0x00000000) + #define PCU_CR_PCIE_ILTR_VAL_PCU_0_NL_VALID_OFF (15) + #define PCU_CR_PCIE_ILTR_VAL_PCU_0_NL_VALID_WID ( 1) + #define PCU_CR_PCIE_ILTR_VAL_PCU_0_NL_VALID_MSK (0x00008000) + #define PCU_CR_PCIE_ILTR_VAL_PCU_0_NL_VALID_MAX (0x00000001) + #define PCU_CR_PCIE_ILTR_VAL_PCU_0_NL_VALID_DEF (0x00000000) + #define PCU_CR_PCIE_ILTR_VAL_PCU_0_SXL_VALUE_OFF (16) + #define PCU_CR_PCIE_ILTR_VAL_PCU_0_SXL_VALUE_WID (10) + #define PCU_CR_PCIE_ILTR_VAL_PCU_0_SXL_VALUE_MSK (0x03FF0000) + #define PCU_CR_PCIE_ILTR_VAL_PCU_0_SXL_VALUE_MAX (0x000003FF) + #define PCU_CR_PCIE_ILTR_VAL_PCU_0_SXL_VALUE_DEF (0x00000000) + #define PCU_CR_PCIE_ILTR_VAL_PCU_0_SXL_SCALE_OFF (26) + #define PCU_CR_PCIE_ILTR_VAL_PCU_0_SXL_SCALE_WID ( 3) + #define PCU_CR_PCIE_ILTR_VAL_PCU_0_SXL_SCALE_MSK (0x1C000000) + #define PCU_CR_PCIE_ILTR_VAL_PCU_0_SXL_SCALE_MAX (0x00000007) + #define PCU_CR_PCIE_ILTR_VAL_PCU_0_SXL_SCALE_DEF (0x00000000) + #define PCU_CR_PCIE_ILTR_VAL_PCU_0_SXL_RESERVED_OFF (29) + #define PCU_CR_PCIE_ILTR_VAL_PCU_0_SXL_RESERVED_WID ( 2) + #define PCU_CR_PCIE_ILTR_VAL_PCU_0_SXL_RESERVED_MSK (0x60000000) + #define PCU_CR_PCIE_ILTR_VAL_PCU_0_SXL_RESERVED_MAX (0x00000003) + #define PCU_CR_PCIE_ILTR_VAL_PCU_0_SXL_RESERVED_DEF (0x00000000) + #define PCU_CR_PCIE_ILTR_VAL_PCU_0_SXL_VALID_OFF (31) + #define PCU_CR_PCIE_ILTR_VAL_PCU_0_SXL_VALID_WID ( 1) + #define PCU_CR_PCIE_ILTR_VAL_PCU_0_SXL_VALID_MSK (0x80000000) + #define PCU_CR_PCIE_ILTR_VAL_PCU_0_SXL_VALID_MAX (0x00000001) + #define PCU_CR_PCIE_ILTR_VAL_PCU_0_SXL_VALID_DEF (0x00000000) + +#define PCU_CR_PCIE_ILTR_VAL_PCU_1_REG (0x00005D38) + #define PCU_CR_PCIE_ILTR_VAL_PCU_1_NL_VALUE_OFF ( 0) + #define PCU_CR_PCIE_ILTR_VAL_PCU_1_NL_VALUE_WID (10) + #define PCU_CR_PCIE_ILTR_VAL_PCU_1_NL_VALUE_MSK (0x000003FF) + #define PCU_CR_PCIE_ILTR_VAL_PCU_1_NL_VALUE_MAX (0x000003FF) + #define PCU_CR_PCIE_ILTR_VAL_PCU_1_NL_VALUE_DEF (0x00000000) + #define PCU_CR_PCIE_ILTR_VAL_PCU_1_NL_SCALE_OFF (10) + #define PCU_CR_PCIE_ILTR_VAL_PCU_1_NL_SCALE_WID ( 3) + #define PCU_CR_PCIE_ILTR_VAL_PCU_1_NL_SCALE_MSK (0x00001C00) + #define PCU_CR_PCIE_ILTR_VAL_PCU_1_NL_SCALE_MAX (0x00000007) + #define PCU_CR_PCIE_ILTR_VAL_PCU_1_NL_SCALE_DEF (0x00000000) + #define PCU_CR_PCIE_ILTR_VAL_PCU_1_NL_RESERVED_OFF (13) + #define PCU_CR_PCIE_ILTR_VAL_PCU_1_NL_RESERVED_WID ( 2) + #define PCU_CR_PCIE_ILTR_VAL_PCU_1_NL_RESERVED_MSK (0x00006000) + #define PCU_CR_PCIE_ILTR_VAL_PCU_1_NL_RESERVED_MAX (0x00000003) + #define PCU_CR_PCIE_ILTR_VAL_PCU_1_NL_RESERVED_DEF (0x00000000) + #define PCU_CR_PCIE_ILTR_VAL_PCU_1_NL_VALID_OFF (15) + #define PCU_CR_PCIE_ILTR_VAL_PCU_1_NL_VALID_WID ( 1) + #define PCU_CR_PCIE_ILTR_VAL_PCU_1_NL_VALID_MSK (0x00008000) + #define PCU_CR_PCIE_ILTR_VAL_PCU_1_NL_VALID_MAX (0x00000001) + #define PCU_CR_PCIE_ILTR_VAL_PCU_1_NL_VALID_DEF (0x00000000) + #define PCU_CR_PCIE_ILTR_VAL_PCU_1_SXL_VALUE_OFF (16) + #define PCU_CR_PCIE_ILTR_VAL_PCU_1_SXL_VALUE_WID (10) + #define PCU_CR_PCIE_ILTR_VAL_PCU_1_SXL_VALUE_MSK (0x03FF0000) + #define PCU_CR_PCIE_ILTR_VAL_PCU_1_SXL_VALUE_MAX (0x000003FF) + #define PCU_CR_PCIE_ILTR_VAL_PCU_1_SXL_VALUE_DEF (0x00000000) + #define PCU_CR_PCIE_ILTR_VAL_PCU_1_SXL_SCALE_OFF (26) + #define PCU_CR_PCIE_ILTR_VAL_PCU_1_SXL_SCALE_WID ( 3) + #define PCU_CR_PCIE_ILTR_VAL_PCU_1_SXL_SCALE_MSK (0x1C000000) + #define PCU_CR_PCIE_ILTR_VAL_PCU_1_SXL_SCALE_MAX (0x00000007) + #define PCU_CR_PCIE_ILTR_VAL_PCU_1_SXL_SCALE_DEF (0x00000000) + #define PCU_CR_PCIE_ILTR_VAL_PCU_1_SXL_RESERVED_OFF (29) + #define PCU_CR_PCIE_ILTR_VAL_PCU_1_SXL_RESERVED_WID ( 2) + #define PCU_CR_PCIE_ILTR_VAL_PCU_1_SXL_RESERVED_MSK (0x60000000) + #define PCU_CR_PCIE_ILTR_VAL_PCU_1_SXL_RESERVED_MAX (0x00000003) + #define PCU_CR_PCIE_ILTR_VAL_PCU_1_SXL_RESERVED_DEF (0x00000000) + #define PCU_CR_PCIE_ILTR_VAL_PCU_1_SXL_VALID_OFF (31) + #define PCU_CR_PCIE_ILTR_VAL_PCU_1_SXL_VALID_WID ( 1) + #define PCU_CR_PCIE_ILTR_VAL_PCU_1_SXL_VALID_MSK (0x80000000) + #define PCU_CR_PCIE_ILTR_VAL_PCU_1_SXL_VALID_MAX (0x00000001) + #define PCU_CR_PCIE_ILTR_VAL_PCU_1_SXL_VALID_DEF (0x00000000) + +#define PCU_CR_PCIE_ILTR_VAL_PCU_2_REG (0x00005D3C) + #define PCU_CR_PCIE_ILTR_VAL_PCU_2_NL_VALUE_OFF ( 0) + #define PCU_CR_PCIE_ILTR_VAL_PCU_2_NL_VALUE_WID (10) + #define PCU_CR_PCIE_ILTR_VAL_PCU_2_NL_VALUE_MSK (0x000003FF) + #define PCU_CR_PCIE_ILTR_VAL_PCU_2_NL_VALUE_MAX (0x000003FF) + #define PCU_CR_PCIE_ILTR_VAL_PCU_2_NL_VALUE_DEF (0x00000000) + #define PCU_CR_PCIE_ILTR_VAL_PCU_2_NL_SCALE_OFF (10) + #define PCU_CR_PCIE_ILTR_VAL_PCU_2_NL_SCALE_WID ( 3) + #define PCU_CR_PCIE_ILTR_VAL_PCU_2_NL_SCALE_MSK (0x00001C00) + #define PCU_CR_PCIE_ILTR_VAL_PCU_2_NL_SCALE_MAX (0x00000007) + #define PCU_CR_PCIE_ILTR_VAL_PCU_2_NL_SCALE_DEF (0x00000000) + #define PCU_CR_PCIE_ILTR_VAL_PCU_2_NL_RESERVED_OFF (13) + #define PCU_CR_PCIE_ILTR_VAL_PCU_2_NL_RESERVED_WID ( 2) + #define PCU_CR_PCIE_ILTR_VAL_PCU_2_NL_RESERVED_MSK (0x00006000) + #define PCU_CR_PCIE_ILTR_VAL_PCU_2_NL_RESERVED_MAX (0x00000003) + #define PCU_CR_PCIE_ILTR_VAL_PCU_2_NL_RESERVED_DEF (0x00000000) + #define PCU_CR_PCIE_ILTR_VAL_PCU_2_NL_VALID_OFF (15) + #define PCU_CR_PCIE_ILTR_VAL_PCU_2_NL_VALID_WID ( 1) + #define PCU_CR_PCIE_ILTR_VAL_PCU_2_NL_VALID_MSK (0x00008000) + #define PCU_CR_PCIE_ILTR_VAL_PCU_2_NL_VALID_MAX (0x00000001) + #define PCU_CR_PCIE_ILTR_VAL_PCU_2_NL_VALID_DEF (0x00000000) + #define PCU_CR_PCIE_ILTR_VAL_PCU_2_SXL_VALUE_OFF (16) + #define PCU_CR_PCIE_ILTR_VAL_PCU_2_SXL_VALUE_WID (10) + #define PCU_CR_PCIE_ILTR_VAL_PCU_2_SXL_VALUE_MSK (0x03FF0000) + #define PCU_CR_PCIE_ILTR_VAL_PCU_2_SXL_VALUE_MAX (0x000003FF) + #define PCU_CR_PCIE_ILTR_VAL_PCU_2_SXL_VALUE_DEF (0x00000000) + #define PCU_CR_PCIE_ILTR_VAL_PCU_2_SXL_SCALE_OFF (26) + #define PCU_CR_PCIE_ILTR_VAL_PCU_2_SXL_SCALE_WID ( 3) + #define PCU_CR_PCIE_ILTR_VAL_PCU_2_SXL_SCALE_MSK (0x1C000000) + #define PCU_CR_PCIE_ILTR_VAL_PCU_2_SXL_SCALE_MAX (0x00000007) + #define PCU_CR_PCIE_ILTR_VAL_PCU_2_SXL_SCALE_DEF (0x00000000) + #define PCU_CR_PCIE_ILTR_VAL_PCU_2_SXL_RESERVED_OFF (29) + #define PCU_CR_PCIE_ILTR_VAL_PCU_2_SXL_RESERVED_WID ( 2) + #define PCU_CR_PCIE_ILTR_VAL_PCU_2_SXL_RESERVED_MSK (0x60000000) + #define PCU_CR_PCIE_ILTR_VAL_PCU_2_SXL_RESERVED_MAX (0x00000003) + #define PCU_CR_PCIE_ILTR_VAL_PCU_2_SXL_RESERVED_DEF (0x00000000) + #define PCU_CR_PCIE_ILTR_VAL_PCU_2_SXL_VALID_OFF (31) + #define PCU_CR_PCIE_ILTR_VAL_PCU_2_SXL_VALID_WID ( 1) + #define PCU_CR_PCIE_ILTR_VAL_PCU_2_SXL_VALID_MSK (0x80000000) + #define PCU_CR_PCIE_ILTR_VAL_PCU_2_SXL_VALID_MAX (0x00000001) + #define PCU_CR_PCIE_ILTR_VAL_PCU_2_SXL_VALID_DEF (0x00000000) + +#define PCU_CR_VISA_CTL_PTPCFSMS_PCU_REG (0x00005D40) + #define PCU_CR_VISA_CTL_PTPCFSMS_PCU_DATA_OFF ( 0) + #define PCU_CR_VISA_CTL_PTPCFSMS_PCU_DATA_WID (18) + #define PCU_CR_VISA_CTL_PTPCFSMS_PCU_DATA_MSK (0x0003FFFF) + #define PCU_CR_VISA_CTL_PTPCFSMS_PCU_DATA_MAX (0x0003FFFF) + #define PCU_CR_VISA_CTL_PTPCFSMS_PCU_DATA_DEF (0x00000000) + #define PCU_CR_VISA_CTL_PTPCFSMS_PCU_VORANGE_OFF (31) + #define PCU_CR_VISA_CTL_PTPCFSMS_PCU_VORANGE_WID ( 1) + #define PCU_CR_VISA_CTL_PTPCFSMS_PCU_VORANGE_MSK (0x80000000) + #define PCU_CR_VISA_CTL_PTPCFSMS_PCU_VORANGE_MAX (0x00000001) + #define PCU_CR_VISA_CTL_PTPCFSMS_PCU_VORANGE_DEF (0x00000000) + +#define PCU_CR_VISA_XBAR_PTPCFSMS_PCU_REG (0x00005D44) + #define PCU_CR_VISA_XBAR_PTPCFSMS_PCU_DATA_OFF ( 0) + #define PCU_CR_VISA_XBAR_PTPCFSMS_PCU_DATA_WID (32) + #define PCU_CR_VISA_XBAR_PTPCFSMS_PCU_DATA_MSK (0xFFFFFFFF) + #define PCU_CR_VISA_XBAR_PTPCFSMS_PCU_DATA_MAX (0xFFFFFFFF) + #define PCU_CR_VISA_XBAR_PTPCFSMS_PCU_DATA_DEF (0x76543210) + +#define PCU_CR_VISA_CTL_PTPCIOREGS_PCU_REG (0x00005D48) + #define PCU_CR_VISA_CTL_PTPCIOREGS_PCU_DATA_OFF ( 0) + #define PCU_CR_VISA_CTL_PTPCIOREGS_PCU_DATA_WID (18) + #define PCU_CR_VISA_CTL_PTPCIOREGS_PCU_DATA_MSK (0x0003FFFF) + #define PCU_CR_VISA_CTL_PTPCIOREGS_PCU_DATA_MAX (0x0003FFFF) + #define PCU_CR_VISA_CTL_PTPCIOREGS_PCU_DATA_DEF (0x00000000) + #define PCU_CR_VISA_CTL_PTPCIOREGS_PCU_VORANGE_OFF (31) + #define PCU_CR_VISA_CTL_PTPCIOREGS_PCU_VORANGE_WID ( 1) + #define PCU_CR_VISA_CTL_PTPCIOREGS_PCU_VORANGE_MSK (0x80000000) + #define PCU_CR_VISA_CTL_PTPCIOREGS_PCU_VORANGE_MAX (0x00000001) + #define PCU_CR_VISA_CTL_PTPCIOREGS_PCU_VORANGE_DEF (0x00000000) + +#define PCU_CR_BIOS_MAILBOX_DATA_PCU_REG (0x00005DA0) + #define PCU_CR_BIOS_MAILBOX_DATA_PCU_DATA_OFF ( 0) + #define PCU_CR_BIOS_MAILBOX_DATA_PCU_DATA_WID (32) + #define PCU_CR_BIOS_MAILBOX_DATA_PCU_DATA_MSK (0xFFFFFFFF) + #define PCU_CR_BIOS_MAILBOX_DATA_PCU_DATA_MAX (0xFFFFFFFF) + #define PCU_CR_BIOS_MAILBOX_DATA_PCU_DATA_DEF (0x00000000) + +#define PCU_CR_BIOS_MAILBOX_INTERFACE_PCU_REG (0x00005DA4) + #define PCU_CR_BIOS_MAILBOX_INTERFACE_PCU_COMMAND_OFF ( 0) + #define PCU_CR_BIOS_MAILBOX_INTERFACE_PCU_COMMAND_WID ( 8) + #define PCU_CR_BIOS_MAILBOX_INTERFACE_PCU_COMMAND_MSK (0x000000FF) + #define PCU_CR_BIOS_MAILBOX_INTERFACE_PCU_COMMAND_MAX (0x000000FF) + #define PCU_CR_BIOS_MAILBOX_INTERFACE_PCU_COMMAND_DEF (0x00000000) + #define PCU_CR_BIOS_MAILBOX_INTERFACE_PCU_ADDR_OFF ( 8) + #define PCU_CR_BIOS_MAILBOX_INTERFACE_PCU_ADDR_WID (21) + #define PCU_CR_BIOS_MAILBOX_INTERFACE_PCU_ADDR_MSK (0x1FFFFF00) + #define PCU_CR_BIOS_MAILBOX_INTERFACE_PCU_ADDR_MAX (0x001FFFFF) + #define PCU_CR_BIOS_MAILBOX_INTERFACE_PCU_ADDR_DEF (0x00000000) + #define PCU_CR_BIOS_MAILBOX_INTERFACE_PCU_RUN_BUSY_OFF (31) + #define PCU_CR_BIOS_MAILBOX_INTERFACE_PCU_RUN_BUSY_WID ( 1) + #define PCU_CR_BIOS_MAILBOX_INTERFACE_PCU_RUN_BUSY_MSK (0x80000000) + #define PCU_CR_BIOS_MAILBOX_INTERFACE_PCU_RUN_BUSY_MAX (0x00000001) + #define PCU_CR_BIOS_MAILBOX_INTERFACE_PCU_RUN_BUSY_DEF (0x00000000) + +#define PCU_CR_BIOS_RESET_CPL_PCU_REG (0x00005DA8) + #define PCU_CR_BIOS_RESET_CPL_PCU_RST_CPL_OFF ( 0) + #define PCU_CR_BIOS_RESET_CPL_PCU_RST_CPL_WID ( 1) + #define PCU_CR_BIOS_RESET_CPL_PCU_RST_CPL_MSK (0x00000001) + #define PCU_CR_BIOS_RESET_CPL_PCU_RST_CPL_MAX (0x00000001) + #define PCU_CR_BIOS_RESET_CPL_PCU_RST_CPL_DEF (0x00000000) + #define PCU_CR_BIOS_RESET_CPL_PCU_PCIE_ENUMERATION_DONE_OFF ( 1) + #define PCU_CR_BIOS_RESET_CPL_PCU_PCIE_ENUMERATION_DONE_WID ( 1) + #define PCU_CR_BIOS_RESET_CPL_PCU_PCIE_ENUMERATION_DONE_MSK (0x00000002) + #define PCU_CR_BIOS_RESET_CPL_PCU_PCIE_ENUMERATION_DONE_MAX (0x00000001) + #define PCU_CR_BIOS_RESET_CPL_PCU_PCIE_ENUMERATION_DONE_DEF (0x00000000) + #define PCU_CR_BIOS_RESET_CPL_PCU_C7_ALLOWED_OFF ( 2) + #define PCU_CR_BIOS_RESET_CPL_PCU_C7_ALLOWED_WID ( 1) + #define PCU_CR_BIOS_RESET_CPL_PCU_C7_ALLOWED_MSK (0x00000004) + #define PCU_CR_BIOS_RESET_CPL_PCU_C7_ALLOWED_MAX (0x00000001) + #define PCU_CR_BIOS_RESET_CPL_PCU_C7_ALLOWED_DEF (0x00000000) + +#define PCU_CR_MC_BIOS_REQ_PCU_REG (0x00005E00) + #define PCU_CR_MC_BIOS_REQ_PCU_REQ_DATA_OFF ( 0) + #define PCU_CR_MC_BIOS_REQ_PCU_REQ_DATA_WID ( 4) + #define PCU_CR_MC_BIOS_REQ_PCU_REQ_DATA_MSK (0x0000000F) + #define PCU_CR_MC_BIOS_REQ_PCU_REQ_DATA_MAX (0x0000000F) + #define PCU_CR_MC_BIOS_REQ_PCU_REQ_DATA_DEF (0x00000000) + #define PCU_CR_MC_BIOS_REQ_PCU_REQ_TYPE_OFF ( 4) + #define PCU_CR_MC_BIOS_REQ_PCU_REQ_TYPE_WID ( 4) + #define PCU_CR_MC_BIOS_REQ_PCU_REQ_TYPE_MSK (0x000000F0) + #define PCU_CR_MC_BIOS_REQ_PCU_REQ_TYPE_MAX (0x0000000F) + #define PCU_CR_MC_BIOS_REQ_PCU_REQ_TYPE_DEF (0x00000000) + #define PCU_CR_MC_BIOS_REQ_PCU_RUN_BUSY_OFF (31) + #define PCU_CR_MC_BIOS_REQ_PCU_RUN_BUSY_WID ( 1) + #define PCU_CR_MC_BIOS_REQ_PCU_RUN_BUSY_MSK (0x80000000) + #define PCU_CR_MC_BIOS_REQ_PCU_RUN_BUSY_MAX (0x00000001) + #define PCU_CR_MC_BIOS_REQ_PCU_RUN_BUSY_DEF (0x00000000) + +#define PCU_CR_MC_BIOS_DATA_PCU_REG (0x00005E04) + #define PCU_CR_MC_BIOS_DATA_PCU_MC_FREQ_OFF ( 0) + #define PCU_CR_MC_BIOS_DATA_PCU_MC_FREQ_WID ( 4) + #define PCU_CR_MC_BIOS_DATA_PCU_MC_FREQ_MSK (0x0000000F) + #define PCU_CR_MC_BIOS_DATA_PCU_MC_FREQ_MAX (0x0000000F) + #define PCU_CR_MC_BIOS_DATA_PCU_MC_FREQ_DEF (0x00000000) + +#define PCU_CR_SAPMCTL_PCU_REG (0x00005F00) + #define PCU_CR_SAPMCTL_PCU_SACG_ENA_OFF ( 0) + #define PCU_CR_SAPMCTL_PCU_SACG_ENA_WID ( 1) + #define PCU_CR_SAPMCTL_PCU_SACG_ENA_MSK (0x00000001) + #define PCU_CR_SAPMCTL_PCU_SACG_ENA_MAX (0x00000001) + #define PCU_CR_SAPMCTL_PCU_SACG_ENA_DEF (0x00000000) + #define PCU_CR_SAPMCTL_PCU_MPLL_OFF_ENA_OFF ( 1) + #define PCU_CR_SAPMCTL_PCU_MPLL_OFF_ENA_WID ( 1) + #define PCU_CR_SAPMCTL_PCU_MPLL_OFF_ENA_MSK (0x00000002) + #define PCU_CR_SAPMCTL_PCU_MPLL_OFF_ENA_MAX (0x00000001) + #define PCU_CR_SAPMCTL_PCU_MPLL_OFF_ENA_DEF (0x00000001) + #define PCU_CR_SAPMCTL_PCU_PPLL_OFF_ENA_OFF ( 2) + #define PCU_CR_SAPMCTL_PCU_PPLL_OFF_ENA_WID ( 1) + #define PCU_CR_SAPMCTL_PCU_PPLL_OFF_ENA_MSK (0x00000004) + #define PCU_CR_SAPMCTL_PCU_PPLL_OFF_ENA_MAX (0x00000001) + #define PCU_CR_SAPMCTL_PCU_PPLL_OFF_ENA_DEF (0x00000001) + #define PCU_CR_SAPMCTL_PCU_SACG_SEN_OFF ( 8) + #define PCU_CR_SAPMCTL_PCU_SACG_SEN_WID ( 1) + #define PCU_CR_SAPMCTL_PCU_SACG_SEN_MSK (0x00000100) + #define PCU_CR_SAPMCTL_PCU_SACG_SEN_MAX (0x00000001) + #define PCU_CR_SAPMCTL_PCU_SACG_SEN_DEF (0x00000001) + #define PCU_CR_SAPMCTL_PCU_MPLL_OFF_SEN_OFF ( 9) + #define PCU_CR_SAPMCTL_PCU_MPLL_OFF_SEN_WID ( 1) + #define PCU_CR_SAPMCTL_PCU_MPLL_OFF_SEN_MSK (0x00000200) + #define PCU_CR_SAPMCTL_PCU_MPLL_OFF_SEN_MAX (0x00000001) + #define PCU_CR_SAPMCTL_PCU_MPLL_OFF_SEN_DEF (0x00000000) + #define PCU_CR_SAPMCTL_PCU_MDLL_OFF_SEN_OFF (10) + #define PCU_CR_SAPMCTL_PCU_MDLL_OFF_SEN_WID ( 1) + #define PCU_CR_SAPMCTL_PCU_MDLL_OFF_SEN_MSK (0x00000400) + #define PCU_CR_SAPMCTL_PCU_MDLL_OFF_SEN_MAX (0x00000001) + #define PCU_CR_SAPMCTL_PCU_MDLL_OFF_SEN_DEF (0x00000000) + #define PCU_CR_SAPMCTL_PCU_SACG_SREXIT_OFF (11) + #define PCU_CR_SAPMCTL_PCU_SACG_SREXIT_WID ( 1) + #define PCU_CR_SAPMCTL_PCU_SACG_SREXIT_MSK (0x00000800) + #define PCU_CR_SAPMCTL_PCU_SACG_SREXIT_MAX (0x00000001) + #define PCU_CR_SAPMCTL_PCU_SACG_SREXIT_DEF (0x00000000) + #define PCU_CR_SAPMCTL_PCU_NSWAKE_SREXIT_OFF (12) + #define PCU_CR_SAPMCTL_PCU_NSWAKE_SREXIT_WID ( 1) + #define PCU_CR_SAPMCTL_PCU_NSWAKE_SREXIT_MSK (0x00001000) + #define PCU_CR_SAPMCTL_PCU_NSWAKE_SREXIT_MAX (0x00000001) + #define PCU_CR_SAPMCTL_PCU_NSWAKE_SREXIT_DEF (0x00000000) + #define PCU_CR_SAPMCTL_PCU_SACG_MPLL_OFF (13) + #define PCU_CR_SAPMCTL_PCU_SACG_MPLL_WID ( 1) + #define PCU_CR_SAPMCTL_PCU_SACG_MPLL_MSK (0x00002000) + #define PCU_CR_SAPMCTL_PCU_SACG_MPLL_MAX (0x00000001) + #define PCU_CR_SAPMCTL_PCU_SACG_MPLL_DEF (0x00000001) + #define PCU_CR_SAPMCTL_PCU_MPLL_ON_DE_OFF (14) + #define PCU_CR_SAPMCTL_PCU_MPLL_ON_DE_WID ( 1) + #define PCU_CR_SAPMCTL_PCU_MPLL_ON_DE_MSK (0x00004000) + #define PCU_CR_SAPMCTL_PCU_MPLL_ON_DE_MAX (0x00000001) + #define PCU_CR_SAPMCTL_PCU_MPLL_ON_DE_DEF (0x00000000) + #define PCU_CR_SAPMCTL_PCU_MDLL_ON_DE_OFF (15) + #define PCU_CR_SAPMCTL_PCU_MDLL_ON_DE_WID ( 1) + #define PCU_CR_SAPMCTL_PCU_MDLL_ON_DE_MSK (0x00008000) + #define PCU_CR_SAPMCTL_PCU_MDLL_ON_DE_MAX (0x00000001) + #define PCU_CR_SAPMCTL_PCU_MDLL_ON_DE_DEF (0x00000000) + +#define PCU_CR_P_COMP_PCU_REG (0x00005F04) + #define PCU_CR_P_COMP_PCU_COMP_DISABLE_OFF ( 0) + #define PCU_CR_P_COMP_PCU_COMP_DISABLE_WID ( 1) + #define PCU_CR_P_COMP_PCU_COMP_DISABLE_MSK (0x00000001) + #define PCU_CR_P_COMP_PCU_COMP_DISABLE_MAX (0x00000001) + #define PCU_CR_P_COMP_PCU_COMP_DISABLE_DEF (0x00000000) + #define PCU_CR_P_COMP_PCU_COMP_INTERVAL_OFF ( 1) + #define PCU_CR_P_COMP_PCU_COMP_INTERVAL_WID ( 4) + #define PCU_CR_P_COMP_PCU_COMP_INTERVAL_MSK (0x0000001E) + #define PCU_CR_P_COMP_PCU_COMP_INTERVAL_MAX (0x0000000F) + #define PCU_CR_P_COMP_PCU_COMP_INTERVAL_DEF (0x00000008) + #define PCU_CR_P_COMP_PCU_COMP_FORCE_OFF ( 8) + #define PCU_CR_P_COMP_PCU_COMP_FORCE_WID ( 1) + #define PCU_CR_P_COMP_PCU_COMP_FORCE_MSK (0x00000100) + #define PCU_CR_P_COMP_PCU_COMP_FORCE_MAX (0x00000001) + #define PCU_CR_P_COMP_PCU_COMP_FORCE_DEF (0x00000000) + +#define PCU_CR_M_COMP_PCU_REG (0x00005F08) + #define PCU_CR_M_COMP_PCU_COMP_DISABLE_OFF ( 0) + #define PCU_CR_M_COMP_PCU_COMP_DISABLE_WID ( 1) + #define PCU_CR_M_COMP_PCU_COMP_DISABLE_MSK (0x00000001) + #define PCU_CR_M_COMP_PCU_COMP_DISABLE_MAX (0x00000001) + #define PCU_CR_M_COMP_PCU_COMP_DISABLE_DEF (0x00000000) + #define PCU_CR_M_COMP_PCU_COMP_INTERVAL_OFF ( 1) + #define PCU_CR_M_COMP_PCU_COMP_INTERVAL_WID ( 4) + #define PCU_CR_M_COMP_PCU_COMP_INTERVAL_MSK (0x0000001E) + #define PCU_CR_M_COMP_PCU_COMP_INTERVAL_MAX (0x0000000F) + #define PCU_CR_M_COMP_PCU_COMP_INTERVAL_DEF (0x0000000D) + #define PCU_CR_M_COMP_PCU_COMP_FORCE_OFF ( 8) + #define PCU_CR_M_COMP_PCU_COMP_FORCE_WID ( 1) + #define PCU_CR_M_COMP_PCU_COMP_FORCE_MSK (0x00000100) + #define PCU_CR_M_COMP_PCU_COMP_FORCE_MAX (0x00000001) + #define PCU_CR_M_COMP_PCU_COMP_FORCE_DEF (0x00000000) + +#define PCU_CR_D_COMP_PCU_REG (0x00005F0C) + #define PCU_CR_D_COMP_PCU_COMP_DISABLE_OFF ( 0) + #define PCU_CR_D_COMP_PCU_COMP_DISABLE_WID ( 1) + #define PCU_CR_D_COMP_PCU_COMP_DISABLE_MSK (0x00000001) + #define PCU_CR_D_COMP_PCU_COMP_DISABLE_MAX (0x00000001) + #define PCU_CR_D_COMP_PCU_COMP_DISABLE_DEF (0x00000000) + #define PCU_CR_D_COMP_PCU_COMP_INTERVAL_OFF ( 1) + #define PCU_CR_D_COMP_PCU_COMP_INTERVAL_WID ( 4) + #define PCU_CR_D_COMP_PCU_COMP_INTERVAL_MSK (0x0000001E) + #define PCU_CR_D_COMP_PCU_COMP_INTERVAL_MAX (0x0000000F) + #define PCU_CR_D_COMP_PCU_COMP_INTERVAL_DEF (0x00000008) + #define PCU_CR_D_COMP_PCU_COMP_FORCE_OFF ( 8) + #define PCU_CR_D_COMP_PCU_COMP_FORCE_WID ( 1) + #define PCU_CR_D_COMP_PCU_COMP_FORCE_MSK (0x00000100) + #define PCU_CR_D_COMP_PCU_COMP_FORCE_MAX (0x00000001) + #define PCU_CR_D_COMP_PCU_COMP_FORCE_DEF (0x00000000) + +#define PCU_CR_CONFIG_TDP_NOMINAL_PCU_REG (0x00005F3C) + #define PCU_CR_CONFIG_TDP_NOMINAL_PCU_TDP_RATIO_OFF ( 0) + #define PCU_CR_CONFIG_TDP_NOMINAL_PCU_TDP_RATIO_WID ( 8) + #define PCU_CR_CONFIG_TDP_NOMINAL_PCU_TDP_RATIO_MSK (0x000000FF) + #define PCU_CR_CONFIG_TDP_NOMINAL_PCU_TDP_RATIO_MAX (0x000000FF) + #define PCU_CR_CONFIG_TDP_NOMINAL_PCU_TDP_RATIO_DEF (0x00000000) + +#define PCU_CR_CONFIG_TDP_LEVEL1_PCU_REG (0x00005F40) + #define PCU_CR_CONFIG_TDP_LEVEL1_PCU_PKG_TDP_OFF ( 0) + #define PCU_CR_CONFIG_TDP_LEVEL1_PCU_PKG_TDP_WID (15) + #define PCU_CR_CONFIG_TDP_LEVEL1_PCU_PKG_TDP_MSK (0x00007FFF) + #define PCU_CR_CONFIG_TDP_LEVEL1_PCU_PKG_TDP_MAX (0x00007FFF) + #define PCU_CR_CONFIG_TDP_LEVEL1_PCU_PKG_TDP_DEF (0x00000000) + #define PCU_CR_CONFIG_TDP_LEVEL1_PCU_TDP_RATIO_OFF (16) + #define PCU_CR_CONFIG_TDP_LEVEL1_PCU_TDP_RATIO_WID ( 8) + #define PCU_CR_CONFIG_TDP_LEVEL1_PCU_TDP_RATIO_MSK (0x00FF0000) + #define PCU_CR_CONFIG_TDP_LEVEL1_PCU_TDP_RATIO_MAX (0x000000FF) + #define PCU_CR_CONFIG_TDP_LEVEL1_PCU_TDP_RATIO_DEF (0x00000000) + #define PCU_CR_CONFIG_TDP_LEVEL1_PCU_PKG_MAX_PWR_OFF (32) + #define PCU_CR_CONFIG_TDP_LEVEL1_PCU_PKG_MAX_PWR_WID (15) + #define PCU_CR_CONFIG_TDP_LEVEL1_PCU_PKG_MAX_PWR_MSK (0x7FFF00000000) + #define PCU_CR_CONFIG_TDP_LEVEL1_PCU_PKG_MAX_PWR_MAX (0x00007FFF) + #define PCU_CR_CONFIG_TDP_LEVEL1_PCU_PKG_MAX_PWR_DEF (0x00000000) + #define PCU_CR_CONFIG_TDP_LEVEL1_PCU_PKG_MIN_PWR_OFF (47) + #define PCU_CR_CONFIG_TDP_LEVEL1_PCU_PKG_MIN_PWR_WID (16) + #define PCU_CR_CONFIG_TDP_LEVEL1_PCU_PKG_MIN_PWR_MSK (0x7FFF800000000000) + #define PCU_CR_CONFIG_TDP_LEVEL1_PCU_PKG_MIN_PWR_MAX (0x0000FFFF) + #define PCU_CR_CONFIG_TDP_LEVEL1_PCU_PKG_MIN_PWR_DEF (0x00000000) + +#define PCU_CR_CONFIG_TDP_LEVEL2_PCU_REG (0x00005F48) + #define PCU_CR_CONFIG_TDP_LEVEL2_PCU_PKG_TDP_OFF ( 0) + #define PCU_CR_CONFIG_TDP_LEVEL2_PCU_PKG_TDP_WID (15) + #define PCU_CR_CONFIG_TDP_LEVEL2_PCU_PKG_TDP_MSK (0x00007FFF) + #define PCU_CR_CONFIG_TDP_LEVEL2_PCU_PKG_TDP_MAX (0x00007FFF) + #define PCU_CR_CONFIG_TDP_LEVEL2_PCU_PKG_TDP_DEF (0x00000000) + #define PCU_CR_CONFIG_TDP_LEVEL2_PCU_TDP_RATIO_OFF (16) + #define PCU_CR_CONFIG_TDP_LEVEL2_PCU_TDP_RATIO_WID ( 8) + #define PCU_CR_CONFIG_TDP_LEVEL2_PCU_TDP_RATIO_MSK (0x00FF0000) + #define PCU_CR_CONFIG_TDP_LEVEL2_PCU_TDP_RATIO_MAX (0x000000FF) + #define PCU_CR_CONFIG_TDP_LEVEL2_PCU_TDP_RATIO_DEF (0x00000000) + #define PCU_CR_CONFIG_TDP_LEVEL2_PCU_PKG_MAX_PWR_OFF (32) + #define PCU_CR_CONFIG_TDP_LEVEL2_PCU_PKG_MAX_PWR_WID (15) + #define PCU_CR_CONFIG_TDP_LEVEL2_PCU_PKG_MAX_PWR_MSK (0x7FFF00000000) + #define PCU_CR_CONFIG_TDP_LEVEL2_PCU_PKG_MAX_PWR_MAX (0x00007FFF) + #define PCU_CR_CONFIG_TDP_LEVEL2_PCU_PKG_MAX_PWR_DEF (0x00000000) + #define PCU_CR_CONFIG_TDP_LEVEL2_PCU_PKG_MIN_PWR_OFF (47) + #define PCU_CR_CONFIG_TDP_LEVEL2_PCU_PKG_MIN_PWR_WID (16) + #define PCU_CR_CONFIG_TDP_LEVEL2_PCU_PKG_MIN_PWR_MSK (0x7FFF800000000000) + #define PCU_CR_CONFIG_TDP_LEVEL2_PCU_PKG_MIN_PWR_MAX (0x0000FFFF) + #define PCU_CR_CONFIG_TDP_LEVEL2_PCU_PKG_MIN_PWR_DEF (0x00000000) + +#define PCU_CR_CONFIG_TDP_CONTROL_PCU_REG (0x00005F50) + #define PCU_CR_CONFIG_TDP_CONTROL_PCU_TDP_LEVEL_OFF ( 0) + #define PCU_CR_CONFIG_TDP_CONTROL_PCU_TDP_LEVEL_WID ( 2) + #define PCU_CR_CONFIG_TDP_CONTROL_PCU_TDP_LEVEL_MSK (0x00000003) + #define PCU_CR_CONFIG_TDP_CONTROL_PCU_TDP_LEVEL_MAX (0x00000003) + #define PCU_CR_CONFIG_TDP_CONTROL_PCU_TDP_LEVEL_DEF (0x00000000) + #define PCU_CR_CONFIG_TDP_CONTROL_PCU_CONFIG_TDP_LOCK_OFF (31) + #define PCU_CR_CONFIG_TDP_CONTROL_PCU_CONFIG_TDP_LOCK_WID ( 1) + #define PCU_CR_CONFIG_TDP_CONTROL_PCU_CONFIG_TDP_LOCK_MSK (0x80000000) + #define PCU_CR_CONFIG_TDP_CONTROL_PCU_CONFIG_TDP_LOCK_MAX (0x00000001) + #define PCU_CR_CONFIG_TDP_CONTROL_PCU_CONFIG_TDP_LOCK_DEF (0x00000000) + +#define PCU_CR_TURBO_ACTIVATION_RATIO_PCU_REG (0x00005F54) + #define PCU_CR_TURBO_ACTIVATION_RATIO_PCU_MAX_NON_TURBO_RATIO_OFF ( 0) + #define PCU_CR_TURBO_ACTIVATION_RATIO_PCU_MAX_NON_TURBO_RATIO_WID ( 8) + #define PCU_CR_TURBO_ACTIVATION_RATIO_PCU_MAX_NON_TURBO_RATIO_MSK (0x000000FF) + #define PCU_CR_TURBO_ACTIVATION_RATIO_PCU_MAX_NON_TURBO_RATIO_MAX (0x000000FF) + #define PCU_CR_TURBO_ACTIVATION_RATIO_PCU_MAX_NON_TURBO_RATIO_DEF (0x00000000) + #define PCU_CR_TURBO_ACTIVATION_RATIO_PCU_TURBO_ACTIVATION_RATIO_LOCK_OFF (31) + #define PCU_CR_TURBO_ACTIVATION_RATIO_PCU_TURBO_ACTIVATION_RATIO_LOCK_WID ( 1) + #define PCU_CR_TURBO_ACTIVATION_RATIO_PCU_TURBO_ACTIVATION_RATIO_LOCK_MSK (0x80000000) + #define PCU_CR_TURBO_ACTIVATION_RATIO_PCU_TURBO_ACTIVATION_RATIO_LOCK_MAX (0x00000001) + #define PCU_CR_TURBO_ACTIVATION_RATIO_PCU_TURBO_ACTIVATION_RATIO_LOCK_DEF (0x00000000) + +#define DRNG_CR_VISA_CTL_DRNGCTLS_DRNG_REG (0x00006680) + #define DRNG_CR_VISA_CTL_DRNGCTLS_DRNG_DATA_OFF ( 0) + #define DRNG_CR_VISA_CTL_DRNGCTLS_DRNG_DATA_WID (18) + #define DRNG_CR_VISA_CTL_DRNGCTLS_DRNG_DATA_MSK (0x0003FFFF) + #define DRNG_CR_VISA_CTL_DRNGCTLS_DRNG_DATA_MAX (0x0003FFFF) + #define DRNG_CR_VISA_CTL_DRNGCTLS_DRNG_DATA_DEF (0x00000000) + #define DRNG_CR_VISA_CTL_DRNGCTLS_DRNG_VORANGE_OFF (31) + #define DRNG_CR_VISA_CTL_DRNGCTLS_DRNG_VORANGE_WID ( 1) + #define DRNG_CR_VISA_CTL_DRNGCTLS_DRNG_VORANGE_MSK (0x80000000) + #define DRNG_CR_VISA_CTL_DRNGCTLS_DRNG_VORANGE_MAX (0x00000001) + #define DRNG_CR_VISA_CTL_DRNGCTLS_DRNG_VORANGE_DEF (0x00000000) + +#pragma pack(pop) +#endif // __Msa_h__ diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcRegisters/Pci000.h b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcRegisters/Pci000.h new file mode 100644 index 0000000..050187b --- /dev/null +++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcRegisters/Pci000.h @@ -0,0 +1,970 @@ +/*++ @file + PCI bus 0, device 0, function 0 register definitions + + +@copyright + Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved. + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement. +--*/ + +#ifndef _Pci000_h_ +#define _Pci000_h_ +#pragma pack (push, 1) +#include "MrcTypes.h" + +typedef union { + struct { + U32 Mchbaren : 1; /// Bits 0:0 + U32 : 14; /// Bits 14:1 + U32 Mchbar : 17; /// Bits 31:15 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MRC_PCI_000_MCHBAR_LOW_STRUCT; + +typedef union { + struct { + U32 Mchbar : 7; /// Bits 38:32 + U32 : 25; /// Bits 63:39 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MRC_PCI_000_MCHBAR_HIGH_STRUCT; + +typedef union { + struct { + U64 Mchbaren : 1; /// Bits 0:0 + U64 : 14; /// Bits 14:1 + U64 Mchbar : 24; /// Bits 38:15 + U64 : 25; /// Bits 63:39 + } Bits; + U64 Data; + struct { + MRC_PCI_000_MCHBAR_LOW_STRUCT Low; + MRC_PCI_000_MCHBAR_HIGH_STRUCT High; + } Data32; +} MRC_PCI_000_MCHBAR_STRUCT; + +#define MRC_PCI_000_MCHBAR_REG (0x48) + #define MCHBAR_MCHBAREN_OFF (0) + #define MCHBAR_MCHBAREN_WID (1) + #define MCHBAR_MCHBAREN_MSK (0x1) + #define MCHBAR_MCHBAREN_MAX (0x1) + #define MCHBAR_MCHBAREN_DEF (0x0) + #define MCHBAR_MCHBAR_OFF (15) + #define MCHBAR_MCHBAR_WID (24) + #define MCHBAR_MCHBAR_MSK (0x0000007FFFFF8000) + #define MCHBAR_MCHBAR_MAX (0xFFFFFF) + #define MCHBAR_MCHBAR_DEF (0x0) + +typedef union { + struct { + U32 Ggclck : 1; /// Bits 0:0 + U32 Ivd : 1; /// Bits 1:1 + U32 : 1; /// Bits 2:2 + U32 Gms : 5; /// Bits 7:3 + U32 Ggms : 2; /// Bits 9:8 + U32 : 4; /// Bits 13:10 + U32 Vamen : 1; /// Bits 14:14 + U32 : 17; /// Bits 31:15 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MRC_PCI_000_GGC_STRUCT; + +#define MRC_PCI_000_GGC_REG (0x50) + #define GGC_GGCLCK_OFF (0) + #define GGC_GGCLCK_WID (1) + #define GGC_GGCLCK_MSK (0x1) + #define GGC_GGCLCK_MAX (0x1) + #define GGC_GGCLCK_DEF (0x0) + #define GGC_IVD_OFF (1) + #define GGC_IVD_WID (1) + #define GGC_IVD_MSK (0x2) + #define GGC_IVD_MAX (0x1) + #define GGC_IVD_DEF (0x0) + #define GGC_GMS_OFF (3) + #define GGC_GMS_WID (5) + #define GGC_GMS_MSK (0xF8) + #define GGC_GMS_MAX (0x1F) + #define GGC_GMS_DEF (0x5) + #define GGC_GGMS_OFF (8) + #define GGC_GGMS_WID (2) + #define GGC_GGMS_MSK (0x300) + #define GGC_GGMS_MAX (0x3) + #define GGC_GGMS_DEF (0x0) + #define GGC_VAMEN_OFF (0xe) + #define GGC_VAMEN_WID (0x1) + #define GGC_VAMEN_MSK (0x4000) + #define GGC_VAMEN_MAX (0x1) + #define GGC_VAMEN_DEF (0x0) + +typedef union { + struct { + U32 D0EN : 1; /// Bits 0:0 + U32 D1F2EN : 1; /// Bits 1:1 + U32 D1F1EN : 1; /// Bits 2:2 + U32 D1F0EN : 1; /// Bits 3:3 + U32 D2EN : 1; /// Bits 4:4 + U32 D3EN : 1; /// Bits 5:5 + U32 : 1; /// Bits 6:6 + U32 D4EN : 1; /// Bits 7:7 + U32 : 6; /// Bits 13:8 + U32 D7EN : 1; /// Bits 14:14 + U32 : 17; /// Bits 31:15 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MRC_PCI_000_DEVEN_STRUCT; + +#define MRC_PCI_000_DEVEN_REG (0x54) + #define DEVEN_D0EN_OFF (0) + #define DEVEN_D0EN_WID (1) + #define DEVEN_D0EN_MSK (0x1) + #define DEVEN_D0EN_MAX (0x1) + #define DEVEN_D0EN_DEF (0x1) + #define DEVEN_D1F2EN_OFF (1) + #define DEVEN_D1F2EN_WID (1) + #define DEVEN_D1F2EN_MSK (0x2) + #define DEVEN_D1F2EN_MAX (0x1) + #define DEVEN_D1F2EN_DEF (0x1) + #define DEVEN_D1F1EN_OFF (2) + #define DEVEN_D1F1EN_WID (1) + #define DEVEN_D1F1EN_MSK (0x4) + #define DEVEN_D1F1EN_MAX (0x1) + #define DEVEN_D1F1EN_DEF (0x1) + #define DEVEN_D1F0EN_OFF (3) + #define DEVEN_D1F0EN_WID (1) + #define DEVEN_D1F0EN_MSK (0x8) + #define DEVEN_D1F0EN_MAX (0x1) + #define DEVEN_D1F0EN_DEF (0x1) + #define DEVEN_D2EN_OFF (4) + #define DEVEN_D2EN_WID (1) + #define DEVEN_D2EN_MSK (0x10) + #define DEVEN_D2EN_MAX (0x1) + #define DEVEN_D2EN_DEF (0x1) + #define DEVEN_D3EN_OFF (5) + #define DEVEN_D3EN_WID (1) + #define DEVEN_D3EN_MSK (0x20) + #define DEVEN_D3EN_MAX (0x1) + #define DEVEN_D3EN_DEF (0x1) + #define DEVEN_D4EN_OFF (7) + #define DEVEN_D4EN_WID (1) + #define DEVEN_D4EN_MSK (0x80) + #define DEVEN_D4EN_MAX (0x1) + #define DEVEN_D4EN_DEF (0x1) + #define DEVEN_D7EN_OFF (14) + #define DEVEN_D7EN_WID (1) + #define DEVEN_D7EN_MSK (0x4000) + #define DEVEN_D7EN_MAX (0x1) + #define DEVEN_D7EN_DEF (0x0) + +typedef union { + struct { + U32 Pciexbaren : 1; /// Bits 0:0 + U32 Length : 2; /// Bits 2:1 + U32 : 23; /// Bits 25:3 + U32 Admsk64 : 1; /// Bits 26:26 + U32 Admsk128 : 1; /// Bits 27:27 + U32 Pciexbar : 4; /// Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MRC_PCI_000_PCIEXBAR_LOW_STRUCT; + +typedef union { + struct { + U32 Pciexbar : 7; /// Bits 38:32 + U32 : 25; /// Bits 63:39 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MRC_PCI_000_PCIEXBAR_HIGH_STRUCT; + +typedef union { + struct { + U64 Pciexbaren : 1; /// Bits 0:0 + U64 Length : 2; /// Bits 2:1 + U64 : 23; /// Bits 25:3 + U64 Admsk64 : 1; /// Bits 26:26 + U64 Admsk128 : 1; /// Bits 27:27 + U64 Pciexbar : 11; /// Bits 38:28 + U64 : 25; /// Bits 63:39 + } Bits; + U64 Data; + struct { + MRC_PCI_000_PCIEXBAR_LOW_STRUCT Low; + MRC_PCI_000_PCIEXBAR_HIGH_STRUCT High; + } Data32; +} MRC_PCI_000_PCIEXBAR_STRUCT; + +#define MRC_PCI_000_PCIEXBAR_REG (0x60) + #define PCIEXBAR_PCIEXBAREN_OFF (0) + #define PCIEXBAR_PCIEXBAREN_WID (1) + #define PCIEXBAR_PCIEXBAREN_MSK (0x1) + #define PCIEXBAR_PCIEXBAREN_MAX (0x1) + #define PCIEXBAR_PCIEXBAREN_DEF (0x0) + #define PCIEXBAR_LENGTH_OFF (1) + #define PCIEXBAR_LENGTH_WID (2) + #define PCIEXBAR_LENGTH_MSK (0x6) + #define PCIEXBAR_LENGTH_MAX (0x3) + #define PCIEXBAR_LENGTH_DEF (0x0) + #define PCIEXBAR_ADMSK64_OFF (26) + #define PCIEXBAR_ADMSK64_WID (1) + #define PCIEXBAR_ADMSK64_MSK (0x4000000) + #define PCIEXBAR_ADMSK64_MAX (0x1) + #define PCIEXBAR_ADMSK64_DEF (0x1) + #define PCIEXBAR_ADMSK128_OFF (27) + #define PCIEXBAR_ADMSK128_WID (1) + #define PCIEXBAR_ADMSK128_MSK (0x8000000) + #define PCIEXBAR_ADMSK128_MAX (0x1) + #define PCIEXBAR_ADMSK128_DEF (0x1) + #define PCIEXBAR_PCIEXBAR_OFF (28) + #define PCIEXBAR_PCIEXBAR_WID (11) + #define PCIEXBAR_PCIEXBAR_MSK (0x7FF0000000) + #define PCIEXBAR_PCIEXBAR_MAX (0x7FF) + #define PCIEXBAR_PCIEXBAR_DEF (0x0) + +typedef union { + struct { + U32 : 20; /// Bits 19:0 + U32 Value : 12; /// Bits 31:20 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MRC_PCI_000_MESEG_BASE_LOW_STRUCT; + +typedef union { + struct { + U32 Value : 7; /// Bits 38:32 + U32 : 25; /// Bits 63:39 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MRC_PCI_000_MESEG_BASE_HIGH_STRUCT; + +typedef union { + struct { + U64 : 20; /// Bits 19:0 + U64 Value : 19; /// Bits 38:20 + U64 : 25; /// Bits 63:39 + } Bits; + U64 Data; + struct { + MRC_PCI_000_MESEG_BASE_LOW_STRUCT Low; + MRC_PCI_000_MESEG_BASE_HIGH_STRUCT High; + } Data32; +} MRC_PCI_000_MESEG_BASE_STRUCT; + +#define MRC_PCI_000_MESEG_BASE_REG (0x70) + #define MESEG_BASE_MEBASE_OFF (20) + #define MESEG_BASE_MEBASE_WID (19) + #define MESEG_BASE_MEBASE_MSK (0x7FFFF00000) + #define MESEG_BASE_MEBASE_MAX (0x7FFFF) + #define MESEG_BASE_MEBASE_DEF (0x7FFFF) + +typedef union { + struct { + U32 : 10; /// Bits 9:0 + U32 Lock : 1; /// Bits 10:10 + U32 Enable : 1; /// Bits 11:11 + U32 : 8; /// Bits 19:12 + U32 Value : 12; /// Bits 31:20 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MRC_PCI_000_MESEG_MASK_LOW_STRUCT; + +typedef union { + struct { + U32 Value : 7; /// Bits 38:32 + U32 : 25; /// Bits 63:39 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MRC_PCI_000_MESEG_MASK_HIGH_STRUCT; + +typedef union { + struct { + U64 : 10; /// Bits 9:0 + U64 Lock : 1; /// Bits 10:10 + U64 Enable : 1; /// Bits 11:11 + U64 : 8; /// Bits 19:12 + U64 Value : 19; /// Bits 38:20 + U64 : 25; /// Bits 63:39 + } Bits; + U64 Data; + struct { + MRC_PCI_000_MESEG_MASK_LOW_STRUCT Low; + MRC_PCI_000_MESEG_MASK_HIGH_STRUCT High; + } Data32; +} MRC_PCI_000_MESEG_MASK_STRUCT; + +#define MRC_PCI_000_MESEG_MASK_REG (0x78) + #define MESEG_MASK_MELCK_OFF (10) + #define MESEG_MASK_MELCK_WID (1) + #define MESEG_MASK_MELCK_MSK (0x400) + #define MESEG_MASK_MELCK_MAX (1) + #define MESEG_MASK_MELCK_DEF (0x0) + #define MESEG_MASK_ME_STLEN_EN_OFF (11) + #define MESEG_MASK_ME_STLEN_EN_WID (1) + #define MESEG_MASK_ME_STLEN_EN_MSK (0x800) + #define MESEG_MASK_ME_STLEN_EN_MAX (0x1) + #define MESEG_MASK_ME_STLEN_EN_DEF (0x0) + #define MESEG_MASK_MEMASK_OFF (20) + #define MESEG_MASK_MEMASK_WID (19) + #define MESEG_MASK_MEMASK_MSK (0x7FFFF00000) + #define MESEG_MASK_MEMASK_MAX (0x7FFFF) + #define MESEG_MASK_MEMASK_DEF (0x0) + +typedef union { + struct { + U32 Lock : 1; /// Bits 0:0 + U32 : 19; /// Bits 19:1 + U32 Value : 12; /// Bits 31:20 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MRC_PCI_000_REMAPBASE_LOW_STRUCT; + +typedef union { + struct { + U32 Value : 7; /// Bits 38:32 + U32 : 25; /// Bits 63:39 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MRC_PCI_000_REMAPBASE_HIGH_STRUCT; + +typedef union { + struct { + U64 Lock : 1; /// Bits 0:0 + U64 : 19; /// Bits 19:1 + U64 Value : 19; /// Bits 38:20 + U64 : 25; /// Bits 63:39 + } Bits; + U64 Data; + struct { + MRC_PCI_000_REMAPBASE_LOW_STRUCT Low; + MRC_PCI_000_REMAPBASE_HIGH_STRUCT High; + } Data32; +} MRC_PCI_000_REMAPBASE_STRUCT; + +#define MRC_PCI_000_REMAPBASE_REG (0x90) + #define REMAPBASE_LOCK_OFF (0) + #define REMAPBASE_LOCK_WID (1) + #define REMAPBASE_LOCK_MSK (0x1) + #define REMAPBASE_LOCK_MAX (0x1) + #define REMAPBASE_LOCK_DEF (0x0) + #define REMAPBASE_REMAPBASE_OFF (20) + #define REMAPBASE_REMAPBASE_WID (19) + #define REMAPBASE_REMAPBASE_MSK (0x7FFFF00000) + #define REMAPBASE_REMAPBASE_MAX (0x7FFFF) + #define REMAPBASE_REMAPBASE_DEF (0xFFFFF) + +typedef union { + struct { + U32 Lock : 1; /// Bits 0:0 + U32 : 19; /// Bits 19:1 + U32 Value : 12; /// Bits 31:20 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MRC_PCI_000_REMAPLIMIT_LOW_STRUCT; + +typedef union { + struct { + U32 Value : 7; /// Bits 38:32 + U32 : 25; /// Bits 63:39 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MRC_PCI_000_REMAPLIMIT_HIGH_STRUCT; + +typedef union { + struct { + U64 Lock : 1; /// Bits 0:0 + U64 : 19; /// Bits 19:1 + U64 Value : 19; /// Bits 38:20 + U64 : 25; /// Bits 63:39 + } Bits; + U64 Data; + struct { + MRC_PCI_000_REMAPLIMIT_LOW_STRUCT Low; + MRC_PCI_000_REMAPLIMIT_HIGH_STRUCT High; + } Data32; +} MRC_PCI_000_REMAPLIMIT_STRUCT; + +#define MRC_PCI_000_REMAPLIMIT_REG (0x98) + #define REMAPLIMIT_LOCK_OFF (0) + #define REMAPLIMIT_LOCK_WID (1) + #define REMAPLIMIT_LOCK_MSK (0x1) + #define REMAPLIMIT_LOCK_MAX (0x1) + #define REMAPLIMIT_LOCK_DEF (0x0) + #define REMAPLIMIT_REMAPLMT_OFF (20) + #define REMAPLIMIT_REMAPLMT_WID (19) + #define REMAPLIMIT_REMAPLMT_MSK (0x7FFFF00000) + #define REMAPLIMIT_REMAPLMT_MAX (0x7FFFF) + #define REMAPLIMIT_REMAPLMT_DEF (0x0) + +typedef union { + struct { + U32 Lock : 1; /// Bits 0:0 + U32 : 19; /// Bits 19:1 + U32 Value : 12; /// Bits 31:20 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MRC_PCI_000_TOM_LOW_STRUCT; + +typedef union { + struct { + U32 Value : 7; /// Bits 38:32 + U32 : 25; /// Bits 63:39 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MRC_PCI_000_TOM_HIGH_STRUCT; + +typedef union { + struct { + U64 Lock : 1; /// Bits 0:0 + U64 : 19; /// Bits 19:1 + U64 Value : 19; /// Bits 38:20 + U64 : 25; /// Bits 63:39 + } Bits; + U64 Data; + struct { + MRC_PCI_000_TOM_LOW_STRUCT Low; + MRC_PCI_000_TOM_HIGH_STRUCT High; + } Data32; +} MRC_PCI_000_TOM_STRUCT; + +#define MRC_PCI_000_TOM_REG (0xA0) + #define TOM_LOCK_OFF (0) + #define TOM_LOCK_WID (1) + #define TOM_LOCK_MSK (0x1) + #define TOM_LOCK_MAX (0x1) + #define TOM_LOCK_DEF (0x0) + #define TOM_TOM_OFF (20) + #define TOM_TOM_WID (19) + #define TOM_TOM_MSK (0x7FFFF00000) + #define TOM_TOM_MAX (0x7FFFF) + #define TOM_TOM_DEF (0x7FFFF) + +typedef union { + struct { + U32 Lock : 1; /// Bits 0:0 + U32 : 19; /// Bits 19:1 + U32 Value : 12; /// Bits 31:20 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MRC_PCI_000_TOUUD_LOW_STRUCT; + +typedef union { + struct { + U32 Value : 7; /// Bits 38:32 + U32 : 25; /// Bits 63:39 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MRC_PCI_000_TOUUD_HIGH_STRUCT; + +typedef union { + struct { + U64 Lock : 1; /// Bits 0:0 + U64 : 19; /// Bits 19:1 + U64 Value : 19; /// Bits 38:20 + U64 : 25; /// Bits 63:39 + } Bits; + U64 Data; + struct { + MRC_PCI_000_TOUUD_LOW_STRUCT Low; + MRC_PCI_000_TOUUD_HIGH_STRUCT High; + } Data32; +} MRC_PCI_000_TOUUD_STRUCT; + +#define MRC_PCI_000_TOUUD_REG (0xA8) + #define TOUUD_LOCK_OFF (0) + #define TOUUD_LOCK_WID (1) + #define TOUUD_LOCK_MSK (0x1) + #define TOUUD_LOCK_MAX (0x1) + #define TOUUD_LOCK_DEF (0x0) + #define TOUUD_TOUUD_OFF (20) + #define TOUUD_TOUUD_WID (19) + #define TOUUD_TOUUD_MSK (0x7FFFF00000) + #define TOUUD_TOUUD_MAX (0x7FFFF) + #define TOUUD_TOUUD_DEF (0x0) + +typedef union { + struct { + U32 Lock : 1; /// Bits 0:0 + U32 : 19; /// Bits 19:1 + U32 Value : 12; /// Bits 31:20 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MRC_PCI_000_BDSM_STRUCT; + +#define MRC_PCI_000_BDSM_REG (0xB0) + #define BDSM_LOCK_OFF (0) + #define BDSM_LOCK_WID (1) + #define BDSM_LOCK_MSK (0x1) + #define BDSM_LOCK_MAX (0x1) + #define BDSM_LOCK_DEF (0x0) + #define BDSM_BDSM_OFF (20) + #define BDSM_BDSM_WID (12) + #define BDSM_BDSM_MSK (0xFFF00000) + #define BDSM_BDSM_MAX (0xFFF) + #define BDSM_BDSM_DEF (0x0) + +typedef union { + struct { + U32 Lock : 1; /// Bits 0:0 + U32 : 19; /// Bits 19:1 + U32 Value : 12; /// Bits 31:20 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MRC_PCI_000_BGSM_STRUCT; + +#define MRC_PCI_000_BGSM_REG (0xB4) + #define BGSM_LOCK_OFF (0) + #define BGSM_LOCK_WID (1) + #define BGSM_LOCK_MSK (0x1) + #define BGSM_LOCK_MAX (0x1) + #define BGSM_LOCK_DEF (0x0) + #define BGSM_BGSM_OFF (20) + #define BGSM_BGSM_WID (12) + #define BGSM_BGSM_MSK (0xFFF00000) + #define BGSM_BGSM_MAX (0xFFF) + #define BGSM_BGSM_DEF (0x001) + +typedef union { + struct { + U32 Lock : 1; /// Bits 0:0 + U32 : 19; /// Bits 19:1 + U32 Value : 12; /// Bits 31:20 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MRC_PCI_000_TSEGMB_STRUCT; + +#define MRC_PCI_000_TSEGMB_REG (0xB8) + #define TSEGMB_LOCK_OFF (0) + #define TSEGMB_LOCK_WID (1) + #define TSEGMB_LOCK_MSK (0x1) + #define TSEGMB_LOCK_MAX (0x1) + #define TSEGMB_LOCK_DEF (0x0) + #define TSEGMB_TSEGMB_OFF (20) + #define TSEGMB_TSEGMB_WID (12) + #define TSEGMB_TSEGMB_MSK (0xFFF00000) + #define TSEGMB_TSEGMB_MAX (0xFFF) + #define TSEGMB_TSEGMB_DEF (0x0) + +typedef union { + struct { + U32 Lock : 1; /// Bits 0:0 + U32 Prs : 1; /// Bits 1:1 + U32 Epm : 1; /// Bits 2:2 + U32 : 1; /// Bits 3:3 + U32 Dprsize : 8; /// Bits 11:4 + U32 : 20; /// Bits 31:12 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MRC_PCI_000_DPR_STRUCT; + +#define MRC_PCI_000_DPR_REG (0x5c) + #define DPR_LOCK_OFF (0) + #define DPR_LOCK_WID (1) + #define DPR_LOCK_MSK (0x1) + #define DPR_LOCK_MAX (0x1) + #define DPR_LOCK_DEF (0x0) + #define DPR_EPM_OFF (2) + #define DPR_EPM_WID (1) + #define DPR_EPM_MSK (0x4) + #define DPR_EPM_MAX (0x1) + #define DPR_EPM_DEF (0x0) + +typedef union { + struct { + U32 Lock : 1; /// Bits 0:0 + U32 : 19; /// Bits 19:1 + U32 Value : 12; /// Bits 31:20 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MRC_PCI_000_TOLUD_STRUCT; + +#define MRC_PCI_000_TOLUD_REG (0xBC) + #define TOLUD_LOCK_OFF (0) + #define TOLUD_LOCK_WID (1) + #define TOLUD_LOCK_MSK (0x1) + #define TOLUD_LOCK_MAX (0x1) + #define TOLUD_LOCK_DEF (0x0) + #define TOLUD_TOLUD_OFF (20) + #define TOLUD_TOLUD_WID (12) + #define TOLUD_TOLUD_MSK (0xFFF00000) + #define TOLUD_TOLUD_MAX (0xFFF) + #define TOLUD_TOLUD_DEF (0x001) + +typedef union { + struct { + U32 DDR3L_EN : 1; /// Bits 0:0 + U32 DDR_WRTVREF : 1; /// Bits 1:1 + U32 OC_ENABLED_DSKU : 1; /// Bits 2:2 + U32 DDR_OVERCLOCK : 1; /// Bits 3:3 + U32 CRID : 4; /// Bits 7:4 + U32 CDID : 2; /// Bits 9:8 + U32 DIDOE : 1; /// Bits 10:10 + U32 IGD : 1; /// Bits 11:11 + U32 PDCD : 1; /// Bits 12:12 + U32 X2APIC_EN : 1; /// Bits 13:13 + U32 DDPCD : 1; /// Bits 14:14 + U32 CDD : 1; /// Bits 15:15 + U32 FUFRD : 1; /// Bits 16:16 + U32 D1NM : 1; /// Bits 17:17 + U32 PCIE_RATIO_DIS : 1; /// Bits 18:18 + U32 DDRSZ : 2; /// Bits 20:19 + U32 PEGG2DIS : 1; /// Bits 21:21 + U32 DMIG2DIS : 1; /// Bits 22:22 + U32 VTDDD : 1; /// Bits 23:23 + U32 FDEE : 1; /// Bits 24:24 + U32 ECCDIS : 1; /// Bits 25:25 + U32 DW : 1; /// Bits 26:26 + U32 PELWUD : 1; /// Bits 27:27 + U32 PEG10D : 1; /// Bits 28:28 + U32 PEG11D : 1; /// Bits 29:29 + U32 PEG12D : 1; /// Bits 30:30 + U32 DHDAD : 1; /// Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MRC_PCI_000_CAPID0_A_STRUCT; + +#define MRC_PCI_000_CAPID0_REG (0xE4) +#define MRC_PCI_000_CAPID0_A_REG (0xE4) + #define CAPID0_A_DDR3L_EN_OFF (0) + #define CAPID0_A_DDR3L_EN_WID (1) + #define CAPID0_A_DDR3L_EN_MSK (0x1) + #define CAPID0_A_DDR3L_EN_MAX (0x1) + #define CAPID0_A_DDR3L_EN_DEF (0x0) + #define CAPID0_A_DDR_WRTVREF_OFF (0x0) + #define CAPID0_A_DDR_WRTVREF_WID (0x1) + #define CAPID0_A_DDR_WRTVREF_MSK (0x1) + #define CAPID0_A_DDR_WRTVREF_MAX (0x1) + #define CAPID0_A_DDR_WRTVREF_DEF (0x0) + #define CAPID0_A_DDR_OVERCLOCK_OFF (3) + #define CAPID0_A_DDR_OVERCLOCK_WID (1) + #define CAPID0_A_DDR_OVERCLOCK_MSK (0x8) + #define CAPID0_A_DDR_OVERCLOCK_MAX (0x1) + #define CAPID0_A_DDR_OVERCLOCK_DEF (0x0) + #define CAPID0_A_CRID_OFF (4) + #define CAPID0_A_CRID_WID (4) + #define CAPID0_A_CRID_MSK (0xF0) + #define CAPID0_A_CRID_MAX (0xF) + #define CAPID0_A_CRID_DEF (0x0) + #define CAPID0_A_CDID_OFF (8) + #define CAPID0_A_CDID_WID (2) + #define CAPID0_A_CDID_MSK (0x300) + #define CAPID0_A_CDID_MAX (0x3) + #define CAPID0_A_CDID_DEF (0x0) + #define CAPID0_A_DIDOE_OFF (10) + #define CAPID0_A_DIDOE_WID (1) + #define CAPID0_A_DIDOE_MSK (0x400) + #define CAPID0_A_DIDOE_MAX (0x1) + #define CAPID0_A_DIDOE_DEF (0x0) + #define CAPID0_A_IGD_OFF (11) + #define CAPID0_A_IGD_WID (1) + #define CAPID0_A_IGD_MSK (0x800) + #define CAPID0_A_IGD_MAX (0x1) + #define CAPID0_A_IGD_DEF (0x0) + #define CAPID0_A_PDCD_OFF (12) + #define CAPID0_A_PDCD_WID (1) + #define CAPID0_A_PDCD_MSK (0x1000) + #define CAPID0_A_PDCD_MAX (0x1) + #define CAPID0_A_PDCD_DEF (0x0) + #define CAPID0_A_X2APIC_EN_OFF (13) + #define CAPID0_A_X2APIC_EN_WID (1) + #define CAPID0_A_X2APIC_EN_MSK (0x2000) + #define CAPID0_A_X2APIC_EN_MAX (0x1) + #define CAPID0_A_X2APIC_EN_DEF (0x0) + #define CAPID0_A_DDPCD_OFF (14) + #define CAPID0_A_DDPCD_WID (1) + #define CAPID0_A_DDPCD_MSK (0x4000) + #define CAPID0_A_DDPCD_MAX (0x1) + #define CAPID0_A_DDPCD_DEF (0x0) + #define CAPID0_A_CDD_OFF (15) + #define CAPID0_A_CDD_WID (1) + #define CAPID0_A_CDD_MSK (0x8000) + #define CAPID0_A_CDD_MAX (0x1) + #define CAPID0_A_CDD_DEF (0x0) + #define CAPID0_A_FUFRD_OFF (16) + #define CAPID0_A_FUFRD_WID (1) + #define CAPID0_A_FUFRD_MSK (0x10000) + #define CAPID0_A_FUFRD_MAX (0x1) + #define CAPID0_A_FUFRD_DEF (0x0) + #define CAPID0_A_D1NM_OFF (17) + #define CAPID0_A_D1NM_WID (1) + #define CAPID0_A_D1NM_MSK (0x20000) + #define CAPID0_A_D1NM_MAX (0x1) + #define CAPID0_A_D1NM_DEF (0x0) + #define CAPID0_A_PEGX16D_OFF (18) + #define CAPID0_A_PEGX16D_WID (1) + #define CAPID0_A_PEGX16D_MSK (0x40000) + #define CAPID0_A_PEGX16D_MAX (0x1) + #define CAPID0_A_PEGX16D_DEF (0x0) + #define CAPID0_A_DDRSZ_OFF (19) + #define CAPID0_A_DDRSZ_WID (2) + #define CAPID0_A_DDRSZ_MSK (0x180000) + #define CAPID0_A_DDRSZ_MAX (0x3) + #define CAPID0_A_DDRSZ_DEF (0x0) + #define CAPID0_A_PEGG2DIS_OFF (21) + #define CAPID0_A_PEGG2DIS_WID (1) + #define CAPID0_A_PEGG2DIS_MSK (0x200000) + #define CAPID0_A_PEGG2DIS_MAX (0x1) + #define CAPID0_A_PEGG2DIS_DEF (0x0) + #define CAPID0_A_DMIG2DIS_OFF (22) + #define CAPID0_A_DMIG2DIS_WID (1) + #define CAPID0_A_DMIG2DIS_MSK (0x400000) + #define CAPID0_A_DMIG2DIS_MAX (0x1) + #define CAPID0_A_DMIG2DIS_DEF (0x0) + #define CAPID0_A_VTDD_OFF (23) + #define CAPID0_A_VTDD_WID (1) + #define CAPID0_A_VTDD_MSK (0x800000) + #define CAPID0_A_VTDD_MAX (0x1) + #define CAPID0_A_VTDD_DEF (0x0) + #define CAPID0_A_FDEE_OFF (24) + #define CAPID0_A_FDEE_WID (1) + #define CAPID0_A_FDEE_MSK (0x1000000) + #define CAPID0_A_FDEE_MAX (0x1) + #define CAPID0_A_FDEE_DEF (0x0) + #define CAPID0_A_ECCDIS_OFF (25) + #define CAPID0_A_ECCDIS_WID (1) + #define CAPID0_A_ECCDIS_MSK (0x2000000) + #define CAPID0_A_ECCDIS_MAX (0x1) + #define CAPID0_A_ECCDIS_DEF (0x0) + #define CAPID0_A_DW_OFF (26) + #define CAPID0_A_DW_WID (1) + #define CAPID0_A_DW_MSK (0x4000000) + #define CAPID0_A_DW_MAX (0x1) + #define CAPID0_A_DW_DEF (0x0) + #define CAPID0_A_PELWUD_OFF (27) + #define CAPID0_A_PELWUD_WID (1) + #define CAPID0_A_PELWUD_MSK (0x8000000) + #define CAPID0_A_PELWUD_MAX (0x1) + #define CAPID0_A_PELWUD_DEF (0x0) + #define CAPID0_A_PEG10D_OFF (28) + #define CAPID0_A_PEG10D_WID (1) + #define CAPID0_A_PEG10D_MSK (0x10000000) + #define CAPID0_A_PEG10D_MAX (0x1) + #define CAPID0_A_PEG10D_DEF (0x0) + #define CAPID0_A_PEG11D_OFF (29) + #define CAPID0_A_PEG11D_WID (1) + #define CAPID0_A_PEG11D_MSK (0x20000000) + #define CAPID0_A_PEG11D_MAX (0x1) + #define CAPID0_A_PEG11D_DEF (0x0) + #define CAPID0_A_PEG12D_OFF (30) + #define CAPID0_A_PEG12D_WID (1) + #define CAPID0_A_PEG12D_MSK (0x40000000) + #define CAPID0_A_PEG12D_MAX (0x1) + #define CAPID0_A_PEG12D_DEF (0x0) + +typedef union { + struct { + U32 SPEGFX1 : 1; /// Bits 0:0 + U32 DPEGFX1 : 1; /// Bits 1:1 + U32 : 2; /// Bits 3:2 + U32 DMFC : 3; /// Bits 6:4 + U32 DDD : 1; /// Bits 7:7 + U32 : 3; /// Bits 10:8 + U32 HDCPD : 1; /// Bits 11:11 + U32 : 4; /// Bits 15:12 + U32 PEGX16D : 1; /// Bits 16:16 + U32 ADDGFXCAP : 1; /// Bits 17:17 + U32 ADDGFXEN : 1; /// Bits 18:18 + U32 PKGTYP : 1; /// Bits 19:19 + U32 PEGG3_DIS : 1; /// Bits 20:20 + U32 PLL_REF100_CFG : 3; /// Bits 23:21 + U32 SOFTBIN : 1; /// Bits 24:24 + U32 CACHESZ : 3; /// Bits 27:25 + U32 SMT : 1; /// Bits 28:28 + U32 OC_ENABLED_SSKU : 1; /// Bits 29:29 + U32 OC_CTL_SSKU : 1; /// Bits 30:30 + U32 : 1; /// Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MRC_PCI_000_CAPID0_B_STRUCT; + +#define MRC_PCI_000_CAPID0_B_REG (0xE8) + #define CAPID0_B_SPEGFX1_OFF (0) + #define CAPID0_B_SPEGFX1_WID (1) + #define CAPID0_B_SPEGFX1_MSK (0x1) + #define CAPID0_B_SPEGFX1_MAX (0x1) + #define CAPID0_B_SPEGFX1_DEF (0x0) + #define CAPID0_B_DPEGFX1_OFF (1) + #define CAPID0_B_DPEGFX1_WID (1) + #define CAPID0_B_DPEGFX1_MSK (0x2) + #define CAPID0_B_DPEGFX1_MAX (0x1) + #define CAPID0_B_DPEGFX1_DEF (0x0) + #define CAPID0_B_DMFC_OFF (4) + #define CAPID0_B_DMFC_WID (3) + #define CAPID0_B_DMFC_MSK (0x70) + #define CAPID0_B_DMFC_MAX (0x7) + #define CAPID0_B_DMFC_DEF (0x0) + #define CAPID0_B_DDD_OFF (7) + #define CAPID0_B_DDD_WID (1) + #define CAPID0_B_DDD_MSK (0x80) + #define CAPID0_B_DDD_MAX (0x1) + #define CAPID0_B_DDD_DEF (0x0) + #define CAPID0_B_HGKS_OFF (8) + #define CAPID0_B_HGKS_WID (3) + #define CAPID0_B_HGKS_MSK (0x700) + #define CAPID0_B_HGKS_MAX (0x7) + #define CAPID0_B_HGKS_DEF (0x0) + #define CAPID0_B_HDCPD_OFF (11) + #define CAPID0_B_HDCPD_WID (1) + #define CAPID0_B_HDCPD_MSK (0x800) + #define CAPID0_B_HDCPD_MAX (0x1) + #define CAPID0_B_HDCPD_DEF (0x0) + #define CAPID0_B_ADDGFXCAP_OFF (17) + #define CAPID0_B_ADDGFXCAP_WID (1) + #define CAPID0_B_ADDGFXCAP_MSK (0x20000) + #define CAPID0_B_ADDGFXCAP_MAX (0x1) + #define CAPID0_B_ADDGFXCAP_DEF (0x0) + #define CAPID0_B_ADDGFXEN_OFF (18) + #define CAPID0_B_ADDGFXEN_WID (1) + #define CAPID0_B_ADDGFXEN_MSK (0x40000) + #define CAPID0_B_ADDGFXEN_MAX (0x1) + #define CAPID0_B_ADDGFXEN_DEF (0x0) + #define CAPID0_B_PKGTYP_OFF (19) + #define CAPID0_B_PKGTYP_WID (1) + #define CAPID0_B_PKGTYP_MSK (0x80000) + #define CAPID0_B_PKGTYP_MAX (0x1) + #define CAPID0_B_PKGTYP_DEF (0x0) + #define CAPID0_B_PLL_REF100_CFG_OFF (21) + #define CAPID0_B_PLL_REF100_CFG_WID (3) + #define CAPID0_B_PLL_REF100_CFG_MSK (0xE00000) + #define CAPID0_B_PLL_REF100_CFG_MAX (0x7) + #define CAPID0_B_PLL_REF100_CFG_DEF (0x0) + #define CAPID0_B_SOFTBIN_OFF (24) + #define CAPID0_B_SOFTBIN_WID (1) + #define CAPID0_B_SOFTBIN_MSK (0x1000000) + #define CAPID0_B_SOFTBIN_MAX (0x1) + #define CAPID0_B_SOFTBIN_DEF (0x0) + #define CAPID0_B_CACHESZ_OFF (25) + #define CAPID0_B_CACHESZ_WID (3) + #define CAPID0_B_CACHESZ_MSK (0xe000000) + #define CAPID0_B_CACHESZ_MAX (0x7) + #define CAPID0_B_CACHESZ_DEF (0x0) + #define CAPID0_B_SMT_OFF (28) + #define CAPID0_B_SMT_WID (1) + #define CAPID0_B_SMT_MSK (0x10000000) + #define CAPID0_B_SMT_MAX (0x1) + #define CAPID0_B_SMT_DEF (0x0) + #define CAPID0_B_OC_ENABLED_SSKU_OFF (29) + #define CAPID0_B_OC_ENABLED_SSKU_WID (1) + #define CAPID0_B_OC_ENABLED_SSKU_MSK (0x20000000) + #define CAPID0_B_OC_ENABLED_SSKU_MAX (0x1) + #define CAPID0_B_OC_ENABLED_SSKU_DEF (0x0) + +typedef union { + struct { + U64 DDR3L_EN : 1; /// Bits 0:0 + U64 DDR_WRTVREF : 1; /// Bits 1:1 + U64 OC_ENABLED_DSKU : 1; /// Bits 2:2 + U64 DDR_OVERCLOCK : 1; /// Bits 3:3 + U64 CRID : 4; /// Bits 7:4 + U64 CDID : 2; /// Bits 9:8 + U64 DIDOE : 1; /// Bits 10:10 + U64 IGD : 1; /// Bits 11:11 + U64 PDCD : 1; /// Bits 12:12 + U64 X2APIC_EN : 1; /// Bits 13:13 + U64 DDPCD : 1; /// Bits 14:14 + U64 CDD : 1; /// Bits 15:15 + U64 FUFRD : 1; /// Bits 16:16 + U64 D1NM : 1; /// Bits 17:17 + U64 PCIE_RATIO_DIS : 1; /// Bits 18:18 + U64 DDRSZ : 2; /// Bits 20:19 + U64 PEGG2DIS : 1; /// Bits 21:21 + U64 DMIG2DIS : 1; /// Bits 22:22 + U64 VTDDD : 1; /// Bits 23:23 + U64 FDEE : 1; /// Bits 24:24 + U64 ECCDIS : 1; /// Bits 25:25 + U64 DW : 1; /// Bits 26:26 + U64 PELWUD : 1; /// Bits 27:27 + U64 PEG10D : 1; /// Bits 28:28 + U64 PEG11D : 1; /// Bits 29:29 + U64 PEG12D : 1; /// Bits 30:30 + U64 DHDAD : 1; /// Bits 31:31 + U64 SPEGFX1 : 1; /// Bits 32:32 + U64 DPEGFX1 : 1; /// Bits 33:33 + U64 : 2; /// Bits 35:34 + U64 DMFC : 3; /// Bits 38:36 + U64 DDD : 1; /// Bits 39:39 + U64 : 3; /// Bits 42:40 + U64 HDCPD : 1; /// Bits 43:43 + U64 : 4; /// Bits 47:44 + U64 PEGX16D : 1; /// Bits 48:48 + U64 ADDGFXCAP : 1; /// Bits 49:49 + U64 ADDGFXEN : 1; /// Bits 50:50 + U64 PKGTYP : 1; /// Bits 51:51 + U64 PEGG3_DIS : 1; /// Bits 52:52 + U64 PLL_REF100_CFG : 3; /// Bits 55:53 + U64 SOFTBIN : 1; /// Bits 56:56 + U64 CACHESZ : 3; /// Bits 59:57 + U64 SMT : 1; /// Bits 60:60 + U64 OC_ENABLED_SSKU : 1; /// Bits 61:61 + U64 OC_CTL_SSKU : 1; /// Bits 62:62 + U64 : 1; /// Bits 63:63 + } Bits; + U64 Data; + struct { + MRC_PCI_000_CAPID0_A_STRUCT A; + MRC_PCI_000_CAPID0_B_STRUCT B; + } Data32; +} MRC_PCI_000_CAPID0_STRUCT; + +#pragma pack (pop) +#endif /// _Pci000_h_ diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcRegisters/PttHciRegs.h b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcRegisters/PttHciRegs.h new file mode 100644 index 0000000..5646768 --- /dev/null +++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcRegisters/PttHciRegs.h @@ -0,0 +1,101 @@ +/** + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement + +@copyright + Copyright (c) 2012 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + +@file + PttHciRegs.h + +@brief + Register definitions for PTT HCI (Platform Trust Technology - Host Controller Interface). + + Conventions: + + - Prefixes: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values of bits within the registers + Definitions beginning with "S_" are register sizes + Definitions beginning with "N_" are the bit position +**/ +#ifndef _PTT_HCI_REGS_H_ +#define _PTT_HCI_REGS_H_ + +#ifdef PTT_FLAG + +/// +/// FTPM HCI register base address +/// +#define R_PTT_HCI_BASE_ADDRESS 0xFED70000 + +/// +/// FTPM HCI Control Area +/// +#define R_PTT_HCI_CA_RSVD 0x00 +#define R_PTT_HCI_CA_ERROR 0x04 +#define R_PTT_HCI_CA_CANCEL 0x08 +#define R_PTT_HCI_CA_START 0x0C +#define R_PTT_HCI_CA_INT_RSVD 0x10 +#define R_PTT_HCI_CA_CMD_SZ 0x18 +#define R_PTT_HCI_CA_CMD 0x1C +#define R_PTT_HCI_CA_RSP_SZ 0x24 +#define R_PTT_HCI_CA_RSP 0x28 + +/// +/// FTPM HCI Private Area +/// +#define R_PTT_HCI_CMD 0x40 +#define R_PTT_HCI_STS 0x44 + +/// +/// FTPM HCI Command and Response Buffer +/// +#define R_PTT_HCI_CRB 0x80 + +/// +/// R_PTT_HCI_STS Flags +/// +#define B_PTT_HCI_STS_ENABLED 0x00000001 ///< BIT0 +#define B_PTT_HCI_STS_READY 0x00000002 ///< BIT1 +#define B_PTT_HCI_STS_ACM_AS_CRTM 0x00000004 ///< BIT2 +#define B_PTT_HCI_STS_STARTUP_EXEC 0x00000008 ///< BIT3 + +/// +/// Value written to R_PTT_HCI_CMD and CA_START +/// to indicate that a command is available for processing +/// +#define V_PTT_HCI_COMMAND_AVAILABLE_START 0x00000001 +#define V_PTT_HCI_COMMAND_AVAILABLE_CMD 0x00000000 +#define V_PTT_HCI_BUFFER_ADDRESS_RDY 0x00000003 + +/// +/// Ignore bit setting mask for WaitRegisterBits +/// +#define V_PTT_HCI_IGNORE_BITS 0x00000000 + +/// +/// All bits clear mask for WaitRegisterBits +/// +#define V_PTT_HCI_ALL_BITS_CLEAR 0xFFFFFFFF +#define V_PTT_HCI_START_CLEAR 0x00000001 + +/// +/// Max FTPM command/reponse buffer length +/// +#define S_PTT_HCI_CRB_LENGTH 3968 ///< 0xFED70080:0xFED70FFF = 3968 Bytes + +#endif /// PTT_FLAG +#endif diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcReset.h b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcReset.h new file mode 100644 index 0000000..7b95234 --- /dev/null +++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcReset.h @@ -0,0 +1,127 @@ +/** @file + The DDR3 reset sequence definitions. + +@copyright + Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved. + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement. +**/ + +#ifndef _MrcReset_h_ +#define _MrcReset_h_ + +#include "MrcTypes.h" +#include "MrcApi.h" +#include "McAddress.h" +#include "MrcCommon.h" +#include "MrcDdr3.h" +#include "MrcOemPlatform.h" + +#include "PchRegsRcrb.h" + +/** +@brief + Perform full JEDEC reset and init sequence. + + @param[in] MrcData - Include all MRC global data. + + @retval MrcStatus - mrcSuccess or reason for failure. +**/ +extern +MrcStatus +MrcResetSequence ( + IN MrcParameters *const MrcData + ); + +/** +@brief + Perform JEDEC DIMM reset sequence. + + @param[in] MrcData - Include all MRC global data. + + @retval - none +**/ +extern +void +MrcJedecReset ( + IN MrcParameters *const MrcData + ); + +#ifdef ULT_FLAG + +/** +@brief + Perform JEDEC LPDDR3 DIMM reset sequence. + + @param[in] MrcData - Include all MRC global data. + + @retval mrcSuccess if succeeded +**/ +extern +MrcStatus +MrcJedecResetLpddr3 ( + IN MrcParameters *const MrcData + ); + +/** +@brief + Perform JEDEC LPDDR3 DIMM init sequence. + + @param[in] MrcData - Include all MRC global data. + + @retval mrcSuccess if succeeded +**/ +MrcStatus +MrcJedecInitLpddr3 ( + IN MrcParameters *const MrcData + ); + +#endif // ULT_FLAG + +/** +@brief + Wait in a loop until the first RCOMP has been completed. + MRC should wait until this bit is set before executing any DDR command. + + @param[in] MrcData - Include all MRC global data. + + @retval mrcDeviceBusy - On Rcomp completion timeout. + @retval mrcSuccess - On Rcomp completion. +**/ +extern +MrcStatus +CheckFirstRcompDone ( + IN MrcParameters *const MrcData + ); + +/** +@brief + Perform the required steps to exit self refresh in S3/Warm reset: + Download the Read Reg File for all populated ranks. + Assert CKE for all the ranks present to pull Dimms out of Self-Refresh. + Issue long ZQ Calibration for all the ranks present in the channel. + Set REUT to normal mode for all channels. + Set the Power Down Config Register. + + @param[in] MrcData - Include all MRC global data. + + @retval mrcSuccess +**/ +MrcStatus +MrcSelfRefreshExit ( + IN MrcParameters *const MrcData + ); + +#endif // _MrcReset_h_ diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcRmtData.h b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcRmtData.h new file mode 100644 index 0000000..38f1c08 --- /dev/null +++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcRmtData.h @@ -0,0 +1,226 @@ +/** @file + Copies the memory related timing and configuration information into the + Compatible BIOS data (BDAT) table. + +@copyright + Copyright (c) 2010 - 2012 Intel Corporation. All rights reserved. + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement. +**/ +#ifndef _MrcRmtData_h_ +#define _MrcRmtData_h_ + +#include "MrcTypes.h" +#include "MrcApi.h" + +#define VDD_1_350 1350 ///< VDD in millivolts +#define VDD_1_500 1500 ///< VDD in millivolts +#define PI_STEP_BASE 2048 ///< Magic number from spec +#define PI_STEP_INTERVAL 128 ///< tCK is split into this amount of intervals +#define PI_STEP ((PI_STEP_BASE) / (PI_STEP_INTERVAL)) +#define VREF_STEP_BASE 100 ///< Magic number from spec +#define TX_VREF_STEP 7800 ///< TX Vref step in microvolts +#define TX_VREF(VDD) (((TX_VREF_STEP) * (VREF_STEP_BASE)) / (VDD)) ///< VDD passed in is in millivolts +#define RX_VREF_STEP 8000 ///< TX Vref step in microvolts +#define RX_VREF(VDD) (((RX_VREF_STEP) * (VREF_STEP_BASE)) / (VDD)) ///< VDD passed in is in millivolts +#define CA_VREF_STEP 8000 ///< TX Vref step in microvolts +#define CA_VREF(VDD) (((CA_VREF_STEP) * (VREF_STEP_BASE)) / (VDD)) ///< VDD passed in is in millivolts +#define PRIMARY_OFFSET 0 ///< Offset into the BDAT header version. +#define SECONDARY_OFFSET 1 ///< Offset into the BDAT header version. +#define RMT_PRIMARY_VERSION 3 ///< The BDAT structure that is currently supported. +#define RMT_SECONDARY_VERSION 0 ///< The BDAT structure that is currently supported. +#define OEM_OFFSET 0 ///< The current offset to the OEM data in the BDAT structure. +#define MAX_SPD_RMT 256 ///< The maximum amount of data, in bytes, in an SPD structure. + +#pragma pack(push, 1) + +typedef struct { + U8 BiosDataSignature[CHAR_BITS * sizeof (U8)]; ///< "BDATHEAD" + U32 BiosDataStructSize; ///< sizeof BDAT_STRUCTURE + U16 Crc16; ///< 16-bit CRC of BDAT_STRUCTURE (calculated with 0 in this field) + U16 Reserved; + union { + U32 L; + U16 S[2]; + } Version; ///< Version, primary then secondary. + U32 OemOffset; ///< Optional offset to OEM-defined structure + U32 Reserved1; + U32 Reserved2; +} RmtHeader; + +typedef struct { + U8 RxDqLeft; ///< Units = piStep + U8 RxDqRight; + U8 TxDqLeft; + U8 TxDqRight; + U8 RxVrefLow; ///< Units = rxVrefStep + U8 RxVrefHigh; + U8 TxVrefLow; ///< Units = txVrefStep + U8 TxVrefHigh; +} RmtDqMargin; + +typedef struct { + U8 RxDqLeft; ///< Units = piStep + U8 RxDqRight; + U8 TxDqLeft; + U8 TxDqRight; + U8 CmdLeft; + U8 CmdRight; + U8 RecvenLeft; ///< Units = recvenStep + U8 RecvenRight; + U8 WrLevelLeft; ///< Units = wrLevelStep + U8 WrLevelRight; + U8 RxVrefLow; ///< Units = rxVrefStep + U8 RxVrefHigh; + U8 TxVrefLow; ///< Units = txVrefStep + U8 TxVrefHigh; + U8 CmdVrefLow; ///< Units = caVrefStep + U8 CmdVrefHigh; +} RmtRankMargin; + +typedef struct { + U16 RecEnDelay[MAX_STROBE]; + U16 WlDelay[MAX_STROBE]; + U8 RxDqDelay[MAX_STROBE]; + U8 TxDqDelay[MAX_STROBE]; + U8 ClkDelay; + U8 CtlDelay; + U8 CmdDelay[3]; + U8 IoLatency; + U8 Roundtrip; +} RmtRankTraining; + +typedef union { + U16 ModeRegister[MAX_MR_IN_DIMM]; ///< Dimm mode registers MR0 - MR3. +#if 0 + struct { + struct { + U16 BurstLength : 2; ///< A1:A0 - Burst length + U16 CasLatency0 : 1; ///< A2 - CAS latency bit 0 + U16 ReadBurstType : 1; ///< A3 - Read burst type + U16 CasLatency : 3; ///< A6:A4 - CAS latency bits 3:1 + U16 Mode : 1; ///< A7 - Test/Normal mode + U16 DllReset : 1; ///< A8 - DLL reset + U16 WriteRecovery : 3; ///< A11:A9 - CAS latency bits 3:1 + U16 DllPd : 1; ///< A12 - DLL control for precharge power down + U16 : 3; ///< A15:A13 - Reserved + } Mr0; + struct { + U16 DllEnable : 1; ///< A0 - DLL enable + U16 DriverImpCtrl0 : 1; ///< A1 - Output driver impedance control bit 0 + U16 RttNom0 : 1; ///< A2 - Odt Rtt values bit 0 + U16 AdditiveLatency : 2; ///< A4:A3 - Additive latency + U16 DriverImpCtrl : 1; ///< A5 - Output driver impedance control bit 1 + U16 RttNom1 : 1; ///< A6 - Odt Rtt values bit 1 + U16 WriteLeveling : 1; ///< A7 - Write leveling enable + U16 : 1; ///< A8 - Reserved + U16 RttNom2 : 1; ///< A9 - Odt Rtt values bit 2 + U16 : 1; ///< A10 - Reserved + U16 TdqsEnable : 1; ///< A11 - Termination data strobe + U16 Qoff : 1; ///< A12 - Output disable + U16 : 3; ///< A15:A13 - Reserved + } Mr1; + struct { + U16 Pasr : 3; ///< A2:A0 - Partial array self refresh + U16 CasWrLatency : 3; ///< A5:A3 - CAS write latency + U16 AutoSelfRefresh : 1; ///< A6 - Automatic self refresh + U16 SelfRefreshTemp : 1; ///< A7 - Self refresh temperature range + U16 : 1; ///< A8 - Reserved + U16 RttWrite : 2; ///< A10:A9 - Dynamic ODT + U16 : 5; ///< A15:A11 - Reserved + } Mr2; + struct { + U16 MprAddress : 2; ///< A1:A0 - Multi-purpose register address + U16 MprControl : 1; ///< A2 - Multi-purpose register control + U16 : 13; ///< A15:A3 - Reserved + } Mr3; + } b; +#endif +} RmtRankMrs; + +typedef struct { + U8 RankEnabled; ///< 0 = Rank disabled + U8 RankMarginEnabled; ///< 0 = Rank margin disabled + U8 DqMarginEnabled; ///< 0 = Dq margin disabled + RmtRankMargin RankMargin; ///< Rank margin data + RmtDqMargin DqMargin[MAX_DQ]; ///< Array of Dq margin data per rank + RmtRankTraining RankTraining; ///< Rank training settings + RmtRankMrs RankMRS; ///< Rank MRS settings +} RmtRankList; + +typedef struct { + U8 SpdValid[MAX_SPD_RMT / (CHAR_BITS * sizeof (U8))]; ///< Each valid bit maps to SPD byte + U8 SpdData[MAX_SPD_RMT]; ///< Array of raw SPD data bytes +} RmtSpd; + +typedef struct { + U8 DimmEnabled; ///< 0 = DIMM disabled + RmtRankList RankList[MAX_RANK_IN_DIMM]; ///< Array of ranks per DIMM + RmtSpd SpdBytes; ///< SPD data per DIMM +} RmtDimmList; + +typedef struct { + U8 ChannelEnabled; ///< 0 = Channel disabled + U8 NumDimmSlot; ///< Number of slots per channel on the board + RmtDimmList DimmList[MAX_DIMMS_IN_CHANNEL]; ///< Array of DIMMs per channel +} RmtChannelList; + +typedef struct { + U8 ControllerEnabled; ///< 0 = MC disabled + U16 ControllerDeviceId; ///< MC device Id + U8 ControllerRevisionId; ///< MC revision Id + U16 MemoryFrequency; ///< Memory frequency in units of MHz / 10 + ///< e.g. ddrFreq = 13333 for tCK = 1.5 ns + U16 MemoryVoltage; ///< Memory Vdd in units of mV + ///< e.g. ddrVoltage = 1350 for Vdd = 1.35 V + U8 PiStep; ///< Step unit = piStep * tCK / 2048 + ///< e.g. piStep = 16 for step = 11.7 ps (1/128 tCK) + U16 RxVrefStep; ///< Step unit = rxVrefStep * Vdd / 100 + ///< e.g. rxVrefStep = 520 for step = 7.02 mV + U16 TxVrefStep; ///< Step unit = txVrefStep * Vdd / 100 + U16 CaVrefStep; ///< Step unit = caVrefStep * Vdd / 100 + U8 RecvenStep; ///< Step unit = recvenStep * tCK / 2048 + U8 WrLevelStep; ///< Step unit = wrLevelStep * tCK / 2048 + RmtChannelList ChannelList[MAX_CHANNEL]; ///< Array of channels per memory controller +} RmtControllerList; + +typedef struct { + union { + U32 l; ///< MRC version: Major.Minor.Revision.Build + struct { + U8 Build; ///< MRC version: Build + U8 Revision; ///< MRC version: Revision + U8 Minor; ///< MRC version: Minor + U8 Major; ///< MRC version: Major + } c; + } RefCodeRevision; ///< Major.Minor.Revision.Build + U8 MaxController; ///< Max controllers per system, e.g. 1 + U8 MaxChannel; ///< Max channels per memory controller, e.g. 2 + U8 MaxDimm; ///< Max DIMM per channel, e.g. 2 + U8 MaxRankDimm; ///< Max ranks per DIMM, e.g. 2 + U8 MaxStrobe; ///< Number of Dqs used by the rank, e.g. 18 + U8 MaxDq; ///< Number of Dq bits used by the rank, e.g. 72 + U32 MarginLoopCount; ///< Units of cache line + RmtControllerList ControllerList[MAX_CONTROLLERS]; ///< Array of memory controllers per system +} RmtSystem; + +typedef struct RmtStruct { + RmtHeader RmtHeader; + RmtSystem RmtSystem; +} RmtData; + +#pragma pack (pop) + +#endif //_MrcRmtData_h_ diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcSpdData.h b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcSpdData.h new file mode 100644 index 0000000..a2b68d8 --- /dev/null +++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcSpdData.h @@ -0,0 +1,671 @@ +/** @file + SPD data format header file. + +@copyright + Copyright (c) 2010 - 2012 Intel Corporation. All rights reserved. + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement. +**/ + +#ifndef _MrcSpdData_h_ +#define _MrcSpdData_h_ +#pragma pack (push, 1) + +#include "MrcTypes.h" + +#define MAX_XMP_PROFILES (2) +#define SPD3_MANUF_SIZE (SPD3_MANUF_END - SPD3_MANUF_START + 1) ///< The size of the SPD manufacturing data. +typedef union { + struct { + U8 BytesUsed : 4; ///< Bits 3:0 + U8 BytesTotal : 3; ///< Bits 6:4 + U8 CrcCoverage : 1; ///< Bits 7:7 + } Bits; + U8 Data; +} SPD_DEVICE_DESCRIPTION_STRUCT; + +typedef union { + struct { + U8 Minor : 4; ///< Bits 3:0 + U8 Major : 4; ///< Bits 7:4 + } Bits; + U8 Data; +} SPD_REVISION_STRUCT; + +typedef union { + struct { + U8 Type : 8; ///< Bits 7:0 + } Bits; + U8 Data; +} SPD_DRAM_DEVICE_TYPE_STRUCT; + +typedef union { + struct { + U8 ModuleType : 4; ///< Bits 3:0 + U8 : 4; ///< Bits 7:4 + } Bits; + U8 Data; +} SPD_MODULE_TYPE_STRUCT; + +typedef union { + struct { + U8 Density : 4; ///< Bits 3:0 + U8 BankAddress : 3; ///< Bits 6:4 + U8 : 1; ///< Bits 7:7 + } Bits; + U8 Data; +} SPD_SDRAM_DENSITY_BANKS_STRUCT; + +typedef union { + struct { + U8 ColumnAddress : 3; ///< Bits 2:0 + U8 RowAddress : 3; ///< Bits 5:3 + U8 : 2; ///< Bits 7:6 + } Bits; + U8 Data; +} SPD_SDRAM_ADDRESSING_STRUCT; + +typedef union { + struct { + U8 OperationAt1_50 : 1; ///< Bits 0:0 + U8 OperationAt1_35 : 1; ///< Bits 1:1 + U8 OperationAt1_25 : 1; ///< Bits 2:2 + U8 : 5; ///< Bits 7:3 + } Bits; + U8 Data; +} SPD_MODULE_NOMINAL_VOLTAGE_STRUCT; + +typedef union { + struct { + U8 SdramDeviceWidth : 3; ///< Bits 2:0 + U8 RankCount : 3; ///< Bits 5:3 + U8 : 2; ///< Bits 7:6 + } Bits; + U8 Data; +} SPD_MODULE_ORGANIZATION_STRUCT; + +typedef union { + struct { + U8 PrimaryBusWidth : 3; ///< Bits 2:0 + U8 BusWidthExtension : 2; ///< Bits 4:3 + U8 : 3; ///< Bits 7:5 + } Bits; + U8 Data; +} SPD_MODULE_MEMORY_BUS_WIDTH_STRUCT; + +typedef union { + struct { + U8 Divisor : 4; ///< Bits 3:0 + U8 Dividend : 4; ///< Bits 7:4 + } Bits; + U8 Data; +} SPD_FINE_TIMEBASE_STRUCT; + +typedef union { + struct { + U8 Dividend : 8; ///< Bits 7:0 + } Bits; + U8 Data; +} SPD_MEDIUM_TIMEBASE_DIVIDEND_STRUCT; + +typedef union { + struct { + U8 Divisor : 8; ///< Bits 7:0 + } Bits; + U8 Data; +} SPD_MEDIUM_TIMEBASE_DIVISOR_STRUCT; + +typedef struct { + SPD_MEDIUM_TIMEBASE_DIVIDEND_STRUCT Dividend; ///< Medium Timebase (MTB) Dividend + SPD_MEDIUM_TIMEBASE_DIVISOR_STRUCT Divisor; ///< Medium Timebase (MTB) Divisor +} SPD_MEDIUM_TIMEBASE; + +typedef union { + struct { + U8 tCKmin : 8; ///< Bits 7:0 + } Bits; + U8 Data; +} SPD_TCK_MIN_MTB_STRUCT; + +typedef union { + struct { + U16 CL4 : 1; ///< Bits 0:0 + U16 CL5 : 1; ///< Bits 1:1 + U16 CL6 : 1; ///< Bits 2:2 + U16 CL7 : 1; ///< Bits 3:3 + U16 CL8 : 1; ///< Bits 4:4 + U16 CL9 : 1; ///< Bits 5:5 + U16 CL10 : 1; ///< Bits 6:6 + U16 CL11 : 1; ///< Bits 7:7 + U16 CL12 : 1; ///< Bits 8:8 + U16 CL13 : 1; ///< Bits 9:9 + U16 CL14 : 1; ///< Bits 10:10 + U16 CL15 : 1; ///< Bits 11:11 + U16 CL16 : 1; ///< Bits 12:12 + U16 CL17 : 1; ///< Bits 13:13 + U16 CL18 : 1; ///< Bits 14:14 + U16 : 1; ///< Bits 15:15 + } Bits; + U16 Data; + U8 Data8; +} SPD_CAS_LATENCIES_SUPPORTED_STRUCT; + +typedef union { + struct { + U8 tAAmin : 8; ///< Bits 7:0 + } Bits; + U8 Data; +} SPD_TAA_MIN_MTB_STRUCT; + +typedef union { + struct { + U8 tWRmin : 8; ///< Bits 7:0 + } Bits; + U8 Data; +} SPD_TWR_MIN_MTB_STRUCT; + +typedef union { + struct { + U8 tRCDmin : 8; ///< Bits 7:0 + } Bits; + U8 Data; +} SPD_TRCD_MIN_MTB_STRUCT; + +typedef union { + struct { + U8 tRRDmin : 8; ///< Bits 7:0 + } Bits; + U8 Data; +} SPD_TRRD_MIN_MTB_STRUCT; + +typedef union { + struct { + U8 tRPmin : 8; ///< Bits 7:0 + } Bits; + U8 Data; +} SPD_TRP_MIN_MTB_STRUCT; + +typedef union { + struct { + U8 tRPab : 8; ///< Bits 7:0 + } Bits; + U8 Data; +} SPD_TRP_AB_MTB_STRUCT; + +typedef union { + struct { + S8 tRPabFine : 8; ///< Bits 7:0 + } Bits; + S8 Data; +} SPD_TRP_AB_FTB_STRUCT; + +typedef union { + struct { + U8 tRASminUpper : 4; ///< Bits 3:0 + U8 tRCminUpper : 4; ///< Bits 7:4 + } Bits; + U8 Data; +} SPD_TRAS_TRC_MIN_MTB_STRUCT; + +typedef union { + struct { + U8 tRASmin : 8; ///< Bits 7:0 + } Bits; + U8 Data; +} SPD_TRAS_MIN_MTB_STRUCT; + +typedef union { + struct { + U8 tRCmin : 8; ///< Bits 7:0 + } Bits; + U8 Data; +} SPD_TRC_MIN_MTB_STRUCT; + +typedef union { + struct { + U16 tRFCmin : 16; ///< Bits 15:0 + } Bits; + U16 Data; + U8 Data8; +} SPD_TRFC_MIN_MTB_STRUCT; + +typedef union { + struct { + U8 tWTRmin : 8; ///< Bits 7:0 + } Bits; + U8 Data; +} SPD_TWTR_MIN_MTB_STRUCT; + +typedef union { + struct { + U8 tRTPmin : 8; ///< Bits 7:0 + } Bits; + U8 Data; +} SPD_TRTP_MIN_MTB_STRUCT; + +typedef union { + struct { + U8 tFAWminUpper : 4; ///< Bits 3:0 + U8 : 4; ///< Bits 7:4 + } Bits; + U8 Data; +} SPD_TFAW_MIN_MTB_UPPER_STRUCT; + +typedef union { + struct { + U8 tFAWmin : 8; ///< Bits 7:0 + } Bits; + U8 Data; +} SPD_TFAW_MIN_MTB_STRUCT; + +typedef union { + struct { + U8 tCWLmin : 8; ///< Bits 7:0 + } Bits; + U8 Data; +} SPD_TCWL_MIN_MTB_STRUCT; + +typedef union { + struct { + U8 NMode : 8; ///< Bits 7:0 + } Bits; + U8 Data; +} SPD_SYSTEM_COMMAND_RATE_STRUCT; + +typedef union { + struct { + U16 tREFImin : 16; ///< Bits 15:0 + } Bits; + U16 Data; + U8 Data8; +} SPD_TREFI_MIN_MTB_STRUCT; + +typedef union { + struct { + U8 RZQ6 : 1; ///< Bits 0:0 + U8 RZQ7 : 1; ///< Bits 1:1 + U8 : 5; ///< Bits 6:2 + U8 DllOff : 1; ///< Bits 7:7 + } Bits; + U8 Data; +} SPD_SDRAM_OPTIONAL_FEATURES_STRUCT; + +typedef union { + struct { + U8 ExtendedTemperatureRange : 1; ///< Bits 0:0 + U8 ExtendedTemperatureRefreshRate : 1; ///< Bits 1:1 + U8 AutoSelfRefresh : 1; ///< Bits 2:2 + U8 OnDieThermalSensor : 1; ///< Bits 3:3 + U8 : 3; ///< Bits 6:4 + U8 PartialArraySelfRefresh : 1; ///< Bits 7:7 + } Bits; + U8 Data; +} SPD_SDRAM_THERMAL_REFRESH_STRUCT; + +typedef union { + struct { + U8 ThermalSensorAccuracy : 7; ///< Bits 6:0 + U8 ThermalSensorPresence : 1; ///< Bits 7:7 + } Bits; + U8 Data; +} SPD_MODULE_THERMAL_SENSOR_STRUCT; + +typedef union { + struct { + U8 NonStandardDeviceDescription : 7; ///< Bits 6:0 + U8 SdramDeviceType : 1; ///< Bits 7:7 + } Bits; + U8 Data; +} SPD_SDRAM_DEVICE_TYPE_STRUCT; + +typedef union { + struct { + U8 : 8; ///< Bits 7:0 + } Bits; + U8 Data; +} SPD_AUTO_SELF_REFRESH_PERF_STRUCT; + +typedef union { + struct { + S8 tCKminFine : 8; ///< Bits 7:0 + } Bits; + S8 Data; +} SPD_TCK_MIN_FTB_STRUCT; + +typedef union { + struct { + S8 tAAminFine : 8; ///< Bits 7:0 + } Bits; + S8 Data; +} SPD_TAA_MIN_FTB_STRUCT; + +typedef union { + struct { + S8 tRCDminFine : 8; ///< Bits 7:0 + } Bits; + S8 Data; +} SPD_TRCD_MIN_FTB_STRUCT; + +typedef union { + struct { + S8 tRPminFine : 8; ///< Bits 7:0 + } Bits; + S8 Data; +} SPD_TRP_MIN_FTB_STRUCT; + +typedef union { + struct { + S8 tRCminFine : 8; ///< Bits 7:0 + } Bits; + S8 Data; +} SPD_TRC_MIN_FTB_STRUCT; + +typedef union { + struct { + S8 tRRDminFine : 8; ///< Bits 7:0 + } Bits; + S8 Data; +} SPD_TRRD_MIN_FTB_STRUCT; + +typedef union { + struct { + U8 Height : 5; ///< Bits 4:0 + U8 RawCardExtension : 3; ///< Bits 7:5 + } Bits; + U8 Data; +} SPD_UNBUF_MODULE_NOMINAL_HEIGHT; + +typedef union { + struct { + U8 FrontThickness : 4; ///< Bits 3:0 + U8 BackThickness : 4; ///< Bits 7:4 + } Bits; + U8 Data; +} SPD_UNBUF_MODULE_NOMINAL_THICKNESS; + +typedef union { + struct { + U8 Card : 5; ///< Bits 4:0 + U8 Revision : 2; ///< Bits 6:5 + U8 Extension : 1; ///< Bits 7:7 + } Bits; + U8 Data; +} SPD_UNBUF_REFERENCE_RAW_CARD; + +typedef union { + struct { + U8 MappingRank1 : 1; ///< Bits 0:0 + U8 : 7; ///< Bits 7:1 + } Bits; + U8 Data; +} SPD_UNBUF_ADDRESS_MAPPING; + +typedef union { + struct { + U8 Height : 5; ///< Bits 4:0 + U8 : 3; ///< Bits 7:5 + } Bits; + U8 Data; +} SPD_RDIMM_MODULE_NOMINAL_HEIGHT; + +typedef union { + struct { + U8 FrontThickness : 4; ///< Bits 3:0 + U8 BackThickness : 4; ///< Bits 7:4 + } Bits; + U8 Data; +} SPD_RDIMM_MODULE_NOMINAL_THICKNESS; + +typedef union { + struct { + U8 Card : 5; ///< Bits 4:0 + U8 Revision : 2; ///< Bits 6:5 + U8 Extension : 1; ///< Bits 7:7 + } Bits; + U8 Data; +} SPD_RDIMM_REFERENCE_RAW_CARD; + +typedef union { + struct { + U8 RegisterCount : 2; ///< Bits 1:0 + U8 DramRowCount : 2; ///< Bits 3:2 + U8 : 4; ///< Bits 7:4 + } Bits; + U8 Data; +} SPD_RDIMM_MODULE_ATTRIBUTES; + +typedef union { + struct { + U16 ContinuationCount : 7; ///< Bits 6:0 + U16 ContinuationParity : 1; ///< Bits 7:7 + U16 LastNonZeroByte : 8; ///< Bits 15:8 + } Bits; + U16 Data; + U8 Data8; +} SPD_MANUFACTURER_ID_CODE; + +typedef struct { + U8 Year; ///< Year represented in BCD (00h = 2000) + U8 Week; ///< Year represented in BCD (47h = week 47) +} SPD_MANUFACTURING_DATE; + +typedef union { + U32 Data; + U16 SerialNumber16[2]; + U8 SerialNumber8[4]; +} SPD_MANUFACTURER_SERIAL_NUMBER; + +typedef union { + U16 Crc[1]; + U8 Data8[2]; +} SPD_CYCLIC_REDUNDANCY_CODE; + +typedef union { + struct { + U8 ProfileEnable1 : 1; ///< Bits 0:0 + U8 ProfileEnable2 : 1; ///< Bits 1:1 + U8 ProfileConfig1 : 2; ///< Bits 3:2 + U8 ProfileConfig2 : 2; ///< Bits 5:4 + U8 : 2; ///< Bits 7:6 + } Bits; + U8 Data; +} SPD_XMP_ORG_CONFIG; + +typedef struct { + U16 XmpId; ///< 176-177 XMP Identification String + SPD_XMP_ORG_CONFIG XmpOrgConf; ///< 178 XMP Organization & Configuration + SPD_REVISION_STRUCT XmpRevision; ///< 179 XMP Revision + SPD_MEDIUM_TIMEBASE MediumTimeBase[MAX_XMP_PROFILES]; ///< 180-183 Medium Timebase (MTB) + SPD_FINE_TIMEBASE_STRUCT FineTimeBase; ///< 184 Fine Timebase (FTB) Dividend / Divisor +} SPD_EXTREME_MEMORY_PROFILE_HEADER; + +typedef union { + struct { + U8 Decimal : 5; + U8 Integer : 2; + U8 : 1; + } Bits; + U8 Data; +} SPD_VDD_VOLTAGE_LEVEL_STRUCT; + +typedef struct { + SPD_VDD_VOLTAGE_LEVEL_STRUCT Vdd; ///< 185, 220 XMP Module VDD Voltage Level + SPD_TCK_MIN_MTB_STRUCT tCKmin; ///< 186, 221 XMP SDRAM Minimum Cycle Time (tCKmin) + SPD_TAA_MIN_MTB_STRUCT tAAmin; ///< 187, 222 XMP Minimum CAS Latency Time (tAAmin) + SPD_CAS_LATENCIES_SUPPORTED_STRUCT CasLatencies; ///< 188-189, 223-224 XMP CAS Latencies Supported, Least Significant Byte + SPD_TCWL_MIN_MTB_STRUCT tCWLmin; ///< 190, 225 XMP Minimum CAS Write Latency Time (tCWLmin) + SPD_TRP_MIN_MTB_STRUCT tRPmin; ///< 191, 226 XMP Minimum Row Precharge Delay Time (tRPmin) + SPD_TRCD_MIN_MTB_STRUCT tRCDmin; ///< 192, 227 XMP Minimum RAS# to CAS# Delay Time (tRCDmin) + SPD_TWR_MIN_MTB_STRUCT tWRmin; ///< 193, 228 XMP Minimum Write Recovery Time (tWRmin) + SPD_TRAS_TRC_MIN_MTB_STRUCT tRASMintRCMinUpper; ///< 194, 229 XMP Upper Nibbles for tRAS and tRC + SPD_TRAS_MIN_MTB_STRUCT tRASmin; ///< 195, 230 XMP Minimum Active to Precharge Delay Time (tRASmin), Least Significant Byte + SPD_TRC_MIN_MTB_STRUCT tRCmin; ///< 196, 231 XMP Minimum Active to Active/Refresh Delay Time (tRCmin), Least Significant Byte + SPD_TREFI_MIN_MTB_STRUCT tREFImin; ///< 197-198, 232-233 XMP Maximum tREFI Time (Average Periodic Refresh Interval), Least Significant Byte + SPD_TRFC_MIN_MTB_STRUCT tRFCmin; ///< 199-200, 234-235 XMP Minimum Refresh Recovery Delay Time (tRFCmin), Least Significant Byte + SPD_TRTP_MIN_MTB_STRUCT tRTPmin; ///< 201, 236 XMP Minimum Internal Read to Precharge Command Delay Time (tRTPmin) + SPD_TRRD_MIN_MTB_STRUCT tRRDmin; ///< 202, 237 XMP Minimum Row Active to Row Active Delay Time (tRRDmin) + SPD_TFAW_MIN_MTB_UPPER_STRUCT tFAWMinUpper; ///< 203, 238 XMP Upper Nibble for tFAW + SPD_TFAW_MIN_MTB_STRUCT tFAWmin; ///< 204, 239 XMP Minimum Four Activate Window Delay Time (tFAWmin) + SPD_TWTR_MIN_MTB_STRUCT tWTRmin; ///< 205, 240 XMP Minimum Internal Write to Read Command Delay Time (tWTRmin) + U8 Reserved1[207 - 206 + 1]; ///< 206-207, 241-242 XMP Reserved + SPD_SYSTEM_COMMAND_RATE_STRUCT SystemCmdRate; ///< 208, 243 XMP System ADD/CMD Rate (1N or 2N mode) + SPD_AUTO_SELF_REFRESH_PERF_STRUCT AsrPerf; ///< 209, 244 XMP SDRAM Auto Self Refresh Performance (Sub 1x Refresh and IDD6 impact) + U8 VoltageLevel; ///< 210, 245 XMP Memory Controller Voltage Level + SPD_TCK_MIN_FTB_STRUCT tCKminFine; ///< 211, 246 XMP Fine Offset for SDRAM Minimum Cycle Time (tCKmin) + SPD_TAA_MIN_FTB_STRUCT tAAminFine; ///< 212, 247 XMP Fine Offset for Minimum CAS Latency Time (tAAmin) + SPD_TRP_MIN_FTB_STRUCT tRPminFine; ///< 213, 248 XMP Minimum Row Precharge Delay Time (tRPmin) + SPD_TRCD_MIN_FTB_STRUCT tRCDminFine; ///< 214, 249 XMP Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin) + SPD_TRC_MIN_FTB_STRUCT tRCminFine; ///< 215, 250 XMP Fine Offset for Minimum Active to Active/Refresh Delay Time (tRCmin) + U8 Reserved2[218 - 216 + 1]; ///< 216-218, 251-253 XMP Reserved + U8 VendorPersonality; ///< 219, 254 XMP Vendor Personality +} SPD_EXTREME_MEMORY_PROFILE_DATA; + +typedef struct { + SPD_EXTREME_MEMORY_PROFILE_HEADER Header; ///< 176-184 XMP header + SPD_EXTREME_MEMORY_PROFILE_DATA Data[MAX_XMP_PROFILES]; ///< 185-254 XMP profiles +} SPD_EXTREME_MEMORY_PROFILE; + +typedef struct { + SPD_DEVICE_DESCRIPTION_STRUCT Description; ///< 0 Number of Serial PD Bytes Written / SPD Device Size / CRC Coverage 1, 2 + SPD_REVISION_STRUCT Revision; ///< 1 SPD Revision + SPD_DRAM_DEVICE_TYPE_STRUCT DramDeviceType; ///< 2 DRAM Device Type + SPD_MODULE_TYPE_STRUCT ModuleType; ///< 3 Module Type + SPD_SDRAM_DENSITY_BANKS_STRUCT SdramDensityAndBanks; ///< 4 SDRAM Density and Banks + SPD_SDRAM_ADDRESSING_STRUCT SdramAddressing; ///< 5 SDRAM Addressing + SPD_MODULE_NOMINAL_VOLTAGE_STRUCT ModuleNominalVoltage; ///< 6 Module Nominal Voltage, VDD + SPD_MODULE_ORGANIZATION_STRUCT ModuleOrganization; ///< 7 Module Organization + SPD_MODULE_MEMORY_BUS_WIDTH_STRUCT ModuleMemoryBusWidth; ///< 8 Module Memory Bus Width + SPD_FINE_TIMEBASE_STRUCT FineTimebase; ///< 9 Fine Timebase (FTB) Dividend / Divisor + SPD_MEDIUM_TIMEBASE MediumTimebase; ///< 10-11 Medium Timebase (MTB) Dividend + SPD_TCK_MIN_MTB_STRUCT tCKmin; ///< 12 SDRAM Minimum Cycle Time (tCKmin) + U8 Reserved1; ///< 13 Reserved + SPD_CAS_LATENCIES_SUPPORTED_STRUCT CasLatencies; ///< 14-15 CAS Latencies Supported + SPD_TAA_MIN_MTB_STRUCT tAAmin; ///< 16 Minimum CAS Latency Time (tAAmin) + SPD_TWR_MIN_MTB_STRUCT tWRmin; ///< 17 Minimum Write Recovery Time (tWRmin) + SPD_TRCD_MIN_MTB_STRUCT tRCDmin; ///< 18 Minimum RAS# to CAS# Delay Time (tRCDmin) + SPD_TRRD_MIN_MTB_STRUCT tRRDmin; ///< 19 Minimum Row Active to Row Active Delay Time (tRRDmin) + SPD_TRP_MIN_MTB_STRUCT tRPmin; ///< 20 Minimum Row Precharge Delay Time (tRPmin) + SPD_TRAS_TRC_MIN_MTB_STRUCT tRASMintRCMinUpper; ///< 21 Upper Nibbles for tRAS and tRC + SPD_TRAS_MIN_MTB_STRUCT tRASmin; ///< 22 Minimum Active to Precharge Delay Time (tRASmin), Least Significant Byte + SPD_TRC_MIN_MTB_STRUCT tRCmin; ///< 23 Minimum Active to Active/Refresh Delay Time (tRCmin), Least Significant Byte + SPD_TRFC_MIN_MTB_STRUCT tRFCmin; ///< 24-25 Minimum Refresh Recovery Delay Time (tRFCmin) + SPD_TWTR_MIN_MTB_STRUCT tWTRmin; ///< 26 Minimum Internal Write to Read Command Delay Time (tWTRmin) + SPD_TRTP_MIN_MTB_STRUCT tRTPmin; ///< 27 Minimum Internal Read to Precharge Command Delay Time (tRTPmin) + SPD_TFAW_MIN_MTB_UPPER_STRUCT tFAWMinUpper; ///< 28 Upper Nibble for tFAW + SPD_TFAW_MIN_MTB_STRUCT tFAWmin; ///< 29 Minimum Four Activate Window Delay Time (tFAWmin) + SPD_SDRAM_OPTIONAL_FEATURES_STRUCT SdramOptionalFeatures; ///< 30 SDRAM Optional Features + SPD_SDRAM_THERMAL_REFRESH_STRUCT ThermalAndRefreshOptions; ///< 31 SDRAMThermalAndRefreshOptions + SPD_MODULE_THERMAL_SENSOR_STRUCT ModuleThermalSensor; ///< 32 Module Thermal Sensor + SPD_SDRAM_DEVICE_TYPE_STRUCT SdramDeviceType; ///< 33 SDRAM Device Type + SPD_TCK_MIN_FTB_STRUCT tCKminFine; ///< 34 Fine Offset for SDRAM Minimum Cycle Time (tCKmin) + SPD_TAA_MIN_FTB_STRUCT tAAminFine; ///< 35 Fine Offset for Minimum CAS Latency Time (tAAmin) + SPD_TRCD_MIN_FTB_STRUCT tRCDminFine; ///< 36 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin) + SPD_TRP_MIN_FTB_STRUCT tRPminFine; ///< 37 Minimum Row Precharge Delay Time (tRPmin) + SPD_TRC_MIN_FTB_STRUCT tRCminFine; ///< 38 Fine Offset for Minimum Active to Active/Refresh Delay Time (tRCmin) +#if (SUPPORT_LPDDR3 == SUPPORT) + SPD_TRP_AB_MTB_STRUCT tRPab; ///< 39 Minimum Row Precharge Delay Time for all banks (tRPab) + SPD_TRP_AB_FTB_STRUCT tRPabFine; ///< 40 Fine Offset for Minimum Row Precharge Delay Time for all banks (tRPab) + U8 Reserved2[59 - 41 + 1]; ///< 41 - 59 Reserved +#else + U8 Reserved2[59 - 39 + 1]; ///< 39 - 59 Reserved +#endif +} SPD_GENERAL_SECTION; + +typedef struct { + SPD_UNBUF_MODULE_NOMINAL_HEIGHT ModuleNominalHeight; ///< 60 Module Nominal Height + SPD_UNBUF_MODULE_NOMINAL_THICKNESS ModuleMaximumThickness; ///< 61 Module Maximum Thickness + SPD_UNBUF_REFERENCE_RAW_CARD ReferenceRawCardUsed; ///< 62 Reference Raw Card Used + SPD_UNBUF_ADDRESS_MAPPING AddressMappingEdgeConn; ///< 63 Address Mapping from Edge Connector to DRAM + U8 Reserved[116 - 64 + 1]; ///< 64-116 Reserved +} SPD_MODULE_UNBUFFERED; + +typedef struct { + SPD_RDIMM_MODULE_NOMINAL_HEIGHT ModuleNominalHeight; ///< 60 Module Nominal Height + SPD_RDIMM_MODULE_NOMINAL_THICKNESS ModuleMaximumThickness; ///< 61 Module Maximum Thickness + SPD_RDIMM_REFERENCE_RAW_CARD ReferenceRawCardUsed; ///< 62 Reference Raw Card Used + SPD_RDIMM_MODULE_ATTRIBUTES DimmModuleAttributes; ///< 63 DIMM Module Attributes + U8 Reserved[116 - 64 + 1]; ///< 64-116 Reserved +} SPD_MODULE_REGISTERED; + +typedef union { + SPD_MODULE_UNBUFFERED Unbuffered; + SPD_MODULE_REGISTERED Registered; +} SPD_MODULE_SPECIFIC; + +typedef struct { + U8 Location; ///< 119 Module Manufacturing Location +} SPD_MANUFACTURING_LOCATION; + +typedef struct { + SPD_MANUFACTURER_ID_CODE IdCode; ///< 117-118 Module Manufacturer ID Code + SPD_MANUFACTURING_LOCATION Location; ///< 119 Module Manufacturing Location + SPD_MANUFACTURING_DATE Date; ///< 120-121 Module Manufacturing Year, in BCD (range: 2000-2255) + SPD_MANUFACTURER_SERIAL_NUMBER SerialNumber; ///< 122-125 Module Serial Number +} SPD_UNIQUE_MODULE_ID; + +typedef struct { + U8 ModulePartNumber[145 - 128 + 1]; ///< 128-145 Module Part Number +} SPD_MODULE_PART_NUMBER; + +typedef struct { + U8 ModuleRevisionCode[147 - 146 + 1]; ///< 146-147 Module Revision Code +} SPD_MODULE_REVISION_CODE; + +typedef struct { + U8 ManufactureSpecificData[175 - 150 + 1]; ///< 150-175 Manufacturer's Specific Data +} SPD_MANUFACTURE_SPECIFIC; + +/// +/// DDR3 Serial Presence Detect structure +/// +typedef struct { + SPD_GENERAL_SECTION General; ///< 0-59 General Section + SPD_MODULE_SPECIFIC Module; ///< 60-116 Module-Specific Section + SPD_UNIQUE_MODULE_ID ModuleId; ///< 117-125 Unique Module ID + SPD_CYCLIC_REDUNDANCY_CODE Crc; ///< 126-127 Cyclical Redundancy Code (CRC) + SPD_MODULE_PART_NUMBER ModulePartNumber; ///< 128-145 Module Part Number + SPD_MODULE_REVISION_CODE ModuleRevisionCode; ///< 146-147 Module Revision Code + SPD_MANUFACTURER_ID_CODE DramIdCode; ///< 148-149 Dram Manufacturer ID Code + SPD_MANUFACTURE_SPECIFIC ManufactureSpecificData; ///< 150-175 Manufacturer's Specific Data + SPD_EXTREME_MEMORY_PROFILE Xmp; ///< 176-254 Intel(r) Extreme Memory Profile support + U8 Reserved; ///< 255 Reserved +} MrcSpdDdr3; +typedef union { + MrcSpdDdr3 Ddr3; +} MrcSpd; + +typedef struct { + SPD_MODULE_TYPE_STRUCT ModuleType; ///< 3 Module Type + SPD_MODULE_MEMORY_BUS_WIDTH_STRUCT ModuleMemoryBusWidth; ///< 8/14 Module Memory Bus Width +} SMBIOS_SPD_SAVE; + +typedef struct { + SPD_UNIQUE_MODULE_ID ModuleId; ///< 117-125 Unique Module ID + SPD_CYCLIC_REDUNDANCY_CODE Crc; ///< 126-127 Cyclical Redundancy Code (CRC) + SPD_MODULE_PART_NUMBER ModulePartNumber; ///< 128-145 Module Part Number + SPD_MODULE_REVISION_CODE ModuleRevisionCode; ///< 146-147 Module Revision Code +} MANUFACTURING_SPD_SAVE_DDR3; + +typedef union { + MANUFACTURING_SPD_SAVE_DDR3 Ddr3Data; +} MANUFACTURING_SPD_SAVE; + +typedef struct { + SMBIOS_SPD_SAVE SmbiosData; + MANUFACTURING_SPD_SAVE ManufacturingData; +} MrcSpdSave; + +#pragma pack (pop) +#endif // _MrcSpdData_h_ diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcTypes.h b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcTypes.h new file mode 100644 index 0000000..e445942 --- /dev/null +++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcTypes.h @@ -0,0 +1,175 @@ +/** @file + + Include the the general MRC types + +@copyright + Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +**/ +#ifndef _MRC_TYPES_H +#define _MRC_TYPES_H + +// +// Data Types +// +typedef unsigned long long U64; +typedef unsigned long U32; +typedef unsigned short U16; +typedef unsigned char U8; +typedef signed long long S64; +typedef signed long S32; +typedef signed short S16; +typedef signed char S8; +typedef unsigned char MrcBool; + +#ifndef BOOL +#undef FALSE +#undef TRUE +typedef enum { + FALSE = (0 == 1), + TRUE = (1 == 1) +} BOOL; +#endif + +#ifndef NULL +#define NULL ((void *) 0) +#endif + +#ifndef IN +#define IN +#endif + +#ifndef OPTIONAL +#define OPTIONAL +#endif + +#ifndef OUT +#define OUT +#endif + +#define UNSUPPORT 0 +#define SUPPORT 1 + +typedef enum { + mrcSuccess, + mrcFail, + mrcWrongInputParameter, + mrcCasError, + mrcTimingError, + mrcSenseAmpErr, + mrcReadMPRErr, + mrcReadLevelingError, + mrcWriteLevelingError, + mrcDataTimeCentering1DErr, + mrcWriteVoltage2DError, + mrcReadVoltage2DError, + mrcWrError, + mrcDimmNotSupport, + mrcChannelNotSupport, + mrcPiSettingError, + mrcDqsPiSettingError, + mrcDeviceBusy, + mrcFrequencyChange, + mrcReutSequenceError, + mrcCrcError, + mrcFrequencyError, + mrcDimmNotExist, + mrcColdBootRequired, + mrcRoundTripLatencyError, + mrcMixedDimmSystem, + mrcAliasDetected, + mrcRetrain +} MrcStatus; + +// +// general macros +// +#ifndef MIN +#define MIN(a, b) (((a) < (b)) ? (a) : (b)) +#endif + +#ifndef MAX +#define MAX(a, b) (((a) > (b)) ? (a) : (b)) +#endif + +#ifndef ABS +#define ABS(x) (((x) < 0) ? (-(x)) : (x)) +#endif +// +// use for ignore parames +// +// #define MRC_IGNORE_PARAM(x) ((x) = (x)) +// +#if _MSC_EXTENSIONS +// +// Disable warning that make it impossible to compile at /W4 +// This only works for Microsoft* tools +// +// +// Disabling bitfield type checking warnings. +// +#pragma warning (disable : 4214) +// +// Unreferenced formal parameter - We are object oriented, so we pass parameters even +// if we don't need them. +// +#pragma warning (disable : 4100) +// +// ASSERT(FALSE) or while (TRUE) are legal constructs so supress this warning +// +#pragma warning(disable : 4127) + +#endif // _MSC_EXTENSIONS +#define MRC_BIT0 0x00000001 +#define MRC_BIT1 0x00000002 +#define MRC_BIT2 0x00000004 +#define MRC_BIT3 0x00000008 +#define MRC_BIT4 0x00000010 +#define MRC_BIT5 0x00000020 +#define MRC_BIT6 0x00000040 +#define MRC_BIT7 0x00000080 +#define MRC_BIT8 0x00000100 +#define MRC_BIT9 0x00000200 +#define MRC_BIT10 0x00000400 +#define MRC_BIT11 0x00000800 +#define MRC_BIT12 0x00001000 +#define MRC_BIT13 0x00002000 +#define MRC_BIT14 0x00004000 +#define MRC_BIT15 0x00008000 +#define MRC_BIT16 0x00010000 +#define MRC_BIT17 0x00020000 +#define MRC_BIT18 0x00040000 +#define MRC_BIT19 0x00080000 +#define MRC_BIT20 0x00100000 +#define MRC_BIT21 0x00200000 +#define MRC_BIT22 0x00400000 +#define MRC_BIT23 0x00800000 +#define MRC_BIT24 0x01000000 +#define MRC_BIT25 0x02000000 +#define MRC_BIT26 0x04000000 +#define MRC_BIT27 0x08000000 +#define MRC_BIT28 0x10000000 +#define MRC_BIT29 0x20000000 +#define MRC_BIT30 0x40000000 +#define MRC_BIT31 0x80000000 + +#define MRC_DEADLOOP() { volatile int __iii; __iii = 1; while (__iii); } + +#ifndef ASM +#define ASM __asm +#endif + +#endif diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcVersion.h b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcVersion.h new file mode 100644 index 0000000..fccbf94 --- /dev/null +++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcVersion.h @@ -0,0 +1,24 @@ +/** @file + Include the MRC version + +@copyright + Copyright (c) 1999 - 2014 Intel Corporation. All rights reserved. + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +**/ + +/// Major minor Rev build +/// ----- ----- ---- ----- + 1, 9, 0, 0 |