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author | raywu <raywu0301@gmail.com> | 2018-06-15 00:00:50 +0800 |
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committer | raywu <raywu0301@gmail.com> | 2018-06-15 00:00:50 +0800 |
commit | b7c51c9cf4864df6aabb99a1ae843becd577237c (patch) | |
tree | eebe9b0d0ca03062955223097e57da84dd618b9a /ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/WriteTraining/MrcWriteLeveling.h | |
download | zprj-master.tar.xz |
Diffstat (limited to 'ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/WriteTraining/MrcWriteLeveling.h')
-rw-r--r-- | ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/WriteTraining/MrcWriteLeveling.h | 85 |
1 files changed, 85 insertions, 0 deletions
diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/WriteTraining/MrcWriteLeveling.h b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/WriteTraining/MrcWriteLeveling.h new file mode 100644 index 0000000..bbb6ceb --- /dev/null +++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/WriteTraining/MrcWriteLeveling.h @@ -0,0 +1,85 @@ +/** @file + The write leveling training algorithm definitions. + +@copyright + Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved. + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement. +**/ + +#ifndef _MrcWriteLeveling_h_ +#define _MrcWriteLeveling_h_ + +#include "MrcTypes.h" +#include "MrcApi.h" +#include "McAddress.h" +#include "MrcCommon.h" +#include "MrcReset.h" +#include "MrcDdr3.h" +#include "MrcIoControl.h" +#include "MrcReadReceiveEnable.h" +#include "MrcOem.h" + +/// +/// This defines the maximum ADD delay that can be programmed to the register. It may change in the future +/// +#define MAX_ADD_DELAY (2) + +/** +@brief + this function execute the Jedec write leveling Cleanup. + Center TxDQS-CLK timing + + @param[in, out] MrcData - Include all MRC global data. + + @retval MrcStatus - if it succeded return mrcSuccess +**/ +extern +MrcStatus +MrcJedecWriteLevelingCleanUp ( + IN OUT MrcParameters *const MrcData + ); + +/** +@brief + this function execute the functional write leveling training. + Center TxDQS-CLK timing + + @param[in, out] MrcData - Include all MRC global data. + + @retval MrcStatus - if it succeded return mrcSuccess +**/ +extern +MrcStatus +MrcWriteLevelingTraining ( + IN OUT MrcParameters *const MrcData + ); + +/** +@brief + this function execute the Jedec write leveling training. + Center TxDQS-CLK timing + + @param[in, out] MrcData - Include all MRC global data. + + @retval MrcStatus - if it succedes return mrcSuccess +**/ +extern +MrcStatus +MrcJedecWriteLevelingTraining ( + IN OUT MrcParameters *const MrcData + ); + +#endif // _MrcWriteLeveling_h_ |